JPH01117543A - Access controller - Google Patents

Abstract

PURPOSE:To keep the impartiality by outputting an exclusive OR signal between an access address to be assigned and a signal on a 1st bus to a 2nd bus by each terminal equipment and stopping the transmission when discrepancy is detected with its own sent address signal on a 3rd bus. CONSTITUTION:Assuming addresses assigned to terminal equipments 1, 2, 3 is 0000, 0001, 0010 respectively and the output of a random number generating circuit 4 from the leating point of time of a control signal 41 is 0101, the output of an exclusive OR circuit 3 of a terminal equipment 3 whose 3rd bit of the address is not 0 is logical 1, which represents the discrepancy. Thus, the terminal equipments 3 gives up the transmission request. The exclusive OR gate 15 outputs 1, 0 in the terminal equipments 1, 2 respectively. The terminal equipment recognizing the discrepancy gives up the transmission request and a terminale equipment 2 acquires the transmission right to the data bus 50. Since the reception priority of the transmission request depends on a random in this way, the impartiality of each terminal equipment is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an apparatus for controlling access contention to a common communication resource from a plurality of terminals or an interface circuit accommodating the terminals.

(Prior art) As a method to prevent access collisions between terminals, each terminal sends its own address number to a commonly connected bus before transmission, and receives a logical sum signal on the bus. A method in which if the terminal does not match its own sending signal, it stops sending the remaining address signals and gives up on acquiring access rights, and the terminal that does not detect a mismatch even after sending all address signals gains access rights. is well known.

(Problems to be Solved by the Invention) This system has the problem that access priority is determined by the value of the assigned address number, resulting in unfairness.

An object of the present invention is to provide an access control device that maintains fairness even when performing access control based on address values unique to each terminal.

(Means for Solving the Problems) The access control device of the present invention provides access control for controlling contention of accesses from the plurality of terminals to the communication resource in a communication system in which a plurality of terminals share communication resources. a first device that connects the terminals in common;
second and third buses, a bias value generation circuit that supplies an output value to each of the terminals via the first bus, and an exclusive OR of the output of the bias value generation circuit and the signal of the second bus. a logic circuit that outputs a signal to the third bus; and a control means that synchronizes the sending of the transmission request signal of each terminal, and each terminal is provided with a signal that is exclusively assigned to each terminal as the transmission request signal. An exclusive OR signal of the access address value and the signal on the first bus is output to the second bus, and the signal on the third bus is monitored, and a mismatch with the own sending address signal is detected. If no match is detected after stopping the transmission of the transmission request signal and transmitting all of its own transmission access address values, it is recognized that the right to access the communication resource has been acquired.

(Example) An example of the present invention is shown in FIG.
This will be explained using Figure (a). Note that FIG. 2(a) shows an example of Itami signals sent to the bus 42, control signal 41, and buses 6, 7, and 8 in FIG. 1.

The random number generation circuit 4 serially sends the generated random numbers to the bus 6. The timing control circuit 40 is a control circuit that starts transmission right acquisition control. The bus 42 indicates the busy state of the data bus 50, and the control circuit 1) of the transmitting terminal sets the bus 42 to O. Timing control circuit 1
) becomes 1 for a certain period of time t when the bus 42 becomes 1 and detects that the data bus 50 is free. A control signal 41 for starting transmission right acquisition control is then sent. The control circuit 1) of the terminal that has a transmission request among the terminals 1, 2, and 3 detects the rising edge of the control signal 41, outputs the wired logical sum product (for example, open collector output), sets the gate 13 to the operating state, and registers the register 12. start sending out its own address value. Set the address values assigned to terminals 1, 2, and 3 to 0, respectively.
000.0001.0010. Now, terminal 1.2.3
makes a transmission request, and the output value of the random number generation circuit 4 from the rising edge of the control signal 41 is 01 inches.
For the first and second bits, the upper two bits of all address values are 00, so the output value of the exclusive OR gate 14 of each terminal becomes 01, and the signal on the bus 7 also becomes 01.

Since the re-input to the exclusive OR gate 5 becomes 01, its output value becomes 00. In this way, since the signal on the bus 8 is the same as the address value of each terminal up to the second bit, no terminal gives up on the transmission request.

At the third bit, the exclusive OR gate 14 of terminal 1.2
0 is output from the terminal 3, and a 1 is output from the exclusive OR gate 14 of the terminal 3. The output of the gate 13, ie, the signal on the bus 7, is the logical product of these, so it becomes 0. Then, the output of the exclusive OR gate 5 becomes 0 and is supplied to the bus 8. As a result, the output of the exclusive OR circuit 3 of the terminal 3 where the third bit of the address value is not 0 becomes 1, indicating a mismatch. As a result, the terminal 3 abandons the transmission request, closes the gate 13, and does not transmit the fourth and subsequent bits of the address value.

At the fourth bit, the outputs of the exclusive OR gates 14 of terminals 1 and 2 become 1 and O, respectively.

Therefore, the signal on bus 7 becomes the logical product O. and,
The signal on the bus 8 output from the exclusive OR gate 5 becomes 1. As a result, the exclusive OR gate 15 of terminal 1.2 is 1
．． Outputs 0 for each. In this case, terminal 1, which has a mismatch, abandons the transmission request, and when terminal 2 sends out all address values, all match, so the data bus 50
Obtain the right to send to. The control circuit 1) of the terminal 2 which has acquired the transmission right turns the bus 42 to O, indicating that transmission is in progress, and at the same time sends the data in the buffer 16 to the data bus 50. In this case, since the signal on bus 6 was 0101, terminal 2
has acquired the right to transmit, but if it is 1010, terminal 3 will have the right to transmit. As described above, according to the present invention, since the priority level for accepting and accepting transmission requests is determined by random numbers, fairness among each terminal can be maintained.

Note that the present invention does not limit the starting point of transmission right acquisition control, and two other examples are shown below. Figure 2 (b)
In this case, acquisition control of the transmission right is not started from the time when access to the data bus 50 ends as described above, but
An example is shown in which acquisition control for the next transmission right is started from the moment transmission is started. When the bus 42 becomes 0, the timing control circuit 40 activates the control signal after a certain period of time.If the signal on the bus 6 at this time is 1010, the terminal 3 acquires the transmission right, but the transmission is performed on the bus 42. becomes 1 and data bus 5
It starts after confirming that 0 is empty (Fig. 2
1)) when a downward arrow is attached to the signal of bus 42).

FIG. 2(c) shows yet another example of transmission right allocation control. The control signal 41 is sent at a constant cycle, and transmission right acquisition control is repeatedly performed at the cycle regardless of whether the data bus 50 is empty or not. Then, when the bus 42 becomes empty, the terminal to which the transmission right has been assigned acquires the transmission right. In the figure, terminal 2 initially acquires the transmission right, but data bus 50 is not free (bus 42 is 1).
Therefore, sending is not allowed. Terminal 2 at the end of the next cycle
will relinquish the transmission rights it has acquired. In this case, terminal 3 acquires the transmission right in the second cycle. Furthermore, if the data bus 50 becomes empty during this period, the terminal 3 is allowed to transmit. That is, the assignment of the transmission right is repeated regardless of the state of the data bus 50, and when the data bus 50 becomes vacant, the terminal that has acquired the transmission right is permitted to transmit.

A second embodiment of the invention is shown in FIG. This embodiment has a function of rejecting transmission requests from all terminals. All terminals are assigned addresses with a specific bit 1 to, for example, a least significant bit of 1 and which are mutually exclusive. If transmission is permitted, the access prohibition circuit 43 supplies a signal of 1 to the gate 9. As a result, the operation is exactly the same as in the first embodiment. When access is prohibited, the access prohibition circuit 43 supplies O to the gate 9. This causes the bus 8 to become O. On the other hand, since the least significant bit of the address of each terminal is 1, the exclusive OR gate 15
Always outputs 1 indicating a mismatch at the position. Therefore, transmission from all terminals can be prohibited.

In this way, by supplying address values that are not assigned to terminals, transmission can be prohibited all at once.

FIG. 4 shows a third embodiment of the present invention, and its operation will be explained using FIG. This embodiment has a function of detecting the presence or absence of a transmission request. All terminals are assigned mutually exclusive addresses with a specific bit position, eg, an O in the most significant bit. The detection circuit 44 that detects a transmission request has a function of determining that a transmission request has occurred if the first bit at the start of transmission right acquisition control is O. The timing control circuit 40 supplies the gate 10 and the detection circuit 44 with a pulse f that provides the first bit of the signal output to the bus 41 . As a result, the signal on bus 6 becomes O at this bit position. Therefore, if there is at least one terminal making a transmission request, the most significant bit of the address in the register 12 is sent to the bus 7 as is and becomes 0.

Then, the signal on bus 8 also becomes 0. On the other hand, if there is no one, the signal on bus 7 becomes 1, so the signal on bus 8 becomes 1. Therefore, by taking in the signal on the bus 8 at the timing given by the pulse f, the detection circuit 44 can know whether there is a transmission request.

FIG. 6 shows a fourth embodiment of the invention. This embodiment is for performing access control in a system in which a plurality of groups managed by one access control device are arranged and the groups are connected by one data bus 50 (not shown). . Each group 101.102
．． Reference numeral 103 has the functions shown in FIGS. 3 and 4. It is also assumed that the address of each terminal is uniquely given within the group, and that the most significant bit is set to O1 and the least significant bit is set to 1. When the detection circuit 44 detects a transmission request, it sends the transmission request to the group acquisition circuit 100. The group arbiter circuit 100 selects one group from among the supplied transmission requests and sends a prohibition signal to the other groups. The access prohibition circuit 43 prohibits transmission of all terminals within the group based on this prohibition signal. Therefore, one terminal that accesses the data bus 50 commonly connected between groups is identified.

(Effects of the Invention) As explained above, according to the present invention, the following (1) to (
4) advantages can be obtained.

(1) Access control between terminals can be made fair.

+2) Transmission requests from all terminals can be rejected.

(3) The presence or absence of transmission requests can be centrally monitored.

(4) Access control across groups is possible.

[Brief explanation of the drawing]

1, 3, 4, and 6 show embodiments of the present invention, and FIGS. 2(a), (b), (c), and 5 are diagrams showing its operation. . In the figure, 1.2.3 is the terminal, 4 is the random number generation circuit, and 5 is the terminal.
．． 9.1O1) 3, 14, 15 are gates, 1) is a control circuit, 12 is a register, 16 is a buffer, 6.7.8.4
2.50 is a bus, 40 is a timing control circuit, 43 is an access prohibition circuit, 44 is a detection circuit, 100 is a group arbiter circuit, and 101.102.103 is a group.

Claims (4)

[Claims] (1) In a communication system in which a plurality of terminals share a communication resource, an access control device that controls conflicting accesses from the plurality of terminals to the communication resource, the first access control device commonly connecting the terminals; , second and third buses, a bias value generation circuit that supplies an output value to each of the terminals via the first bus, and exclusive logic of the output of the bias value generation circuit and the signal of the second bus. a logic circuit that outputs a sum signal to the third bus; and a control means that synchronizes the sending of transmission request signals from each of the terminals; outputs an exclusive OR signal of the access address value and the signal on the first bus to the second bus, monitors the signal on the third bus, and detects a mismatch with its own sending address signal. The access control device is characterized in that the access control device stops sending the transmission request signal when the transmission request signal is transmitted, and recognizes that the access right to the communication resource has been acquired if no mismatch is detected after sending all of its own transmission access address values. (2) The logic circuit uses an access address value that is not assigned to any terminal when prohibiting access to the terminal, and an access address value that is not assigned to any terminal when access is permitted, and an output from the bias value generation circuit and the output from the second bus when allowing access. The access control device according to claim 1, wherein an exclusive OR signal of the signals is output to the third bus. (3) Predetermined bits of the access address are set to 0 in common, and a transmission request detection circuit is provided, and the bias value generation circuit is defined based on the start time of access control activated by the control means. Claim 1, characterized in that 0 is always output at the bit position, and the transmission request detection circuit determines the presence or absence of a transmission request based on the value at the bit position of the output of the logic circuit. ) and (2). (4) The control means starts sending out the request signal at regular intervals.
), (2), and (3).