JPH01116962A - Disk controller - Google Patents

Abstract

PURPOSE:To vary a data format at a high speed by enabling data stored in a buffer memory to be read and written selectively while putting a counter in counting operation. CONSTITUTION:When data transferred from a host computer is stored in the buffer memory 5, necessary control information is generated or read out of the buffer memory 5 according to the counted value of the counter 9, and transferred to and written on a disk 1 in prescribed format order. Actual data are also read out of the buffer memory 5 at prescribed timing and transferred to the disk 1 simultaneously. Further, when the data and control information are read out of the disk 1 and written in the buffer memory 5, their write addresses are selected and both of them are written in prescribed areas properly distinctively. Consequently, format conversion is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a disk control device that converts or inversely converts the format of data read from or written to a disk.

(Prior Art) When information is written on a disk using magnetism or light, control information indicating the write address, data length, etc. of the data is stored in a predetermined format along with the actual data. The disk also contains error detection information (generally EC
C code.

Control information such as a CRC code (CRC code) is also stored.

In contrast, only the actual write data is transferred from the host computer or the like to the disk control device. Furthermore, even when data is read from a disk, only the actual data portion is transferred to a host computer or the like.

Therefore, conventionally, when data is accepted via a host interface and written to a disk, predetermined control information is generated, combined with the data, format converted, and written to the disk.

Furthermore, when reading from a disk, format conversion is performed so that various control information read at the same time is cut off and only the actual data is sent to the host computer.

(Problem to be Solved by the Invention) By the way, when writing or reading data using such a method, the format conversion conventionally involves storing the data in a predetermined buffer memory and rearranging it using a program. method has been adopted.

However, in such a method, format conversion processing usually requires a lot of time, which hinders speeding up of data reading or writing processing.

The present invention has been made with attention to the above points, and an object of the present invention is to provide a disk control device that speeds up format conversion processing and shortens disk write/read time.

(Means for Solving the Problems) A disk control device of the present invention includes: a disk into which data and its control information are written; a buffer memory which stores the data and control information read from or written to the disk; 1 for this buffer memory
a counter that performs a counting operation at the timing of reading or writing unit data or control information;
Reading/controlling the data or control information stored in the buffer memory selectively at a predetermined timing by accepting the count value output from the counter.
The device is characterized in that it has a write control circuit.

(Function) When the data transferred from the host computer is stored in the buffer memory, the above device generates necessary control information or reads it from the buffer memory according to the count value of the counter and formats it in a predetermined format. The data is sequentially transferred to the disk and written. During this time, actual data is also read from the buffer memory and transferred to the disk at a predetermined timing. Furthermore, when data and control information are read from the disk and written to the buffer memory, the write address is selected and the two are appropriately distinguished and written to a predetermined area.

As a result, the host computer can easily read data directly from the buffer memory.

(Embodiment) Block Configuration of Device> FIG. 1 is a block diagram showing an embodiment of a disk control device of the present invention.

In the figure, a disk 1 is connected to an inter-disk data transfer control section 3 via a serial transmission line 2.

This inter-disk data transfer control section 3 is connected to a path line 4 that transmits parallel data. The pass line 4 also includes a buffer memory 5 and a central processing unit (
CPU) 6 and a host data transfer control unit 7 are connected. A host computer (not shown) is connected to the host data transfer control unit 7 via a host interface 8 .

Further, this circuit is provided with a counter 9, and the output of this counter 9 is connected to be input to a read/write control circuit 10.

The read/write control circuit 10 includes a read-only memory (ROM) 11 and two counters 12 and 13.
, a selector 14 , an impark 15 , and an error detection and correction circuit 16 .

In this circuit, the inter-disk data transfer control unit 3:
When reading data or control information from the disk 1, this circuit receives the data serially, converts it into a parallel signal, and outputs it to the pass line 4. Further, this circuit is a circuit that outputs the control clock 21 to the counter 9°12.13. Furthermore, this circuit outputs a control signal 22 to the error detection and correction circuit 16 incorporated in the read/write control circuit 10 to control the timing of outputting the error correction code. Also, for the buffer memory 5,
This circuit outputs a control signal 23 that controls the timing of data output.

The buffer memory 5 is composed of a random access memory made of a semiconductor memory device or the like.

The central processing unit 6 is a circuit mainly for controlling communication between the disk control device and the host computer. This device also includes a circuit that operates to output a mode switching signal 25 to the read-only memory 11 for identifying a mode for writing data etc. to the disk and a mode for reading data etc. from the disk. It is. Furthermore, this central processing unit 6 has a counter 9゜1.
2.13, a reset signal is output to return these to their initial values at the start of a write or read process. Note that illustration of this reset control line is omitted.

Host data transfer control unit 7 and host interface 8
constitutes a known data input/output interface circuit, and is a circuit that controls data exchange with an external circuit such as a host computer (not shown).

The counter 9 counts the control clock 21 output from the inter-disk data transfer control unit 3 and has a count value of 2.
This is a circuit that outputs 4.

The read-only memory 11 is a circuit that receives a mode switching signal 25 and a count value 24 output from the counter 9 at its address, and outputs various control signals as described later.

Even if the read-only memory 11 receives the same count value 24 from the counter 9, it outputs different control signals in read mode and write mode.

Configuration of read/write control circuit> Next, read/write control circuit configuration
The configuration of each block of the write control circuit 1o will be explained.

In the read-only memory 11, in the order of their addresses,
Control signals are written to control circuit operations of various parts of the device in write mode and read mode.

That is, first, a part of the output of this read-only memory 11 is used as the counter selection signal 29. This counter selection signal 29 is connected to be input to the control information read counter 12 and the data read counter 13. Both counters accept the control clock 21 and count up, but the counter selection signal 29
For example, assume that the count is increased only when is at a high level. That is, since this counter selection signal 29 is input to the control information read counter 13 via the inverter 15, when the counter selection signal 29 is at a high level,
Only the control information read counter 12 counts up, and when the counter selection signal 29 is at a low level, only the data read counter 13 counts up.

A counter selection signal 29 is also input to the selector 14 for selection control. The selector 14 outputs the output of the control information read counter 12 as an address signal 31 to the buffer memory 5 when the counter selection signal 29 is at a high level, and outputs the output signal of the data read counter 13 when the counter selection signal 29 is at a low level. This circuit outputs the address signal 31 to the buffer memory 5.

In addition, the read/write control circuit 10 includes:
An error detection and correction circuit 16 is provided. In the read mode, the error detection and correction circuit 16 executes a data error detection operation based on an error detection code (ECC code, 'CRC code) included in the control information, and corrects the data as necessary. It is a circuit. Furthermore, in the write mode, an operation of generating an error detection code based on the data stored in the buffer memory 5 is also performed.

Note that this error detection and correction circuit 16 has a read-only type.
In the read mode from the memory 11, the error detection and correction calculation execution signal 26 is input, and in the write mode, the calculation result output signal 27 is input. This calculation result output signal 27 is also input to the buffer memory 5, and becomes a read enable signal for the buffer memory 5.

Note that this signal 26 is generated by reading data etc. from the buffer memory 5 and calculating results from the error detection and correction circuit 16 (
The output of error detection code) is executed exclusively.

In addition, from the read-only memory 11, ■
A completion signal 28 is output to the inter-disk data transfer control section 3 every time writing or reading of data for a block is completed.

<Contents stored in buffer memory> Here, data and control information written to the buffer memory 5 will be explained.

In this embodiment, when the memory address O-ρ,m''-m+n is set in the buffer memory, β pieces of data H(0) to H
(I2) is stored. Also, memory address m-”m+n
Until now, n pieces of control information C(O) to C(n) are stored.

Format of Disk Data, etc. On the other hand, data and control information are generally written on a disk in a format as shown in FIG.

In the figure, for example, one square is shown as one byte of information. In the figure, data etc. are written sequentially from top to bottom and from left to right. The information marked with an asterisk (*) in the square is control information, and the other information is data.

First, there is a C mark called a data mark at the beginning of the disc.
Four bytes of information from (0) to C(3) are written. Then, for example, H(○), H(1,)...
・Data is written one byte at a time,
Every time 20 bytes of this data are written, control information called resync for synchronization is written. This information is 1 byte each, and in the figure, C(4) and C(5)
It was displayed as follows. In this way, 1 byte of control information is written for every 20 bytes of data, and the last data H (
When data is written up to l, 20
Approximately 0 bytes of control information is written. This control information includes information indicating the data address, error detection code (
CRC, ECC code), etc.

Operation in Write Mode> FIG. 4 is a timing chart showing the read control operation of the buffer memory of the device of the present invention.

Using this diagram, the operation when writing data and control information to the disk 1 shown in FIG. 1 will be explained.

First, connect the host interface 8 from the host computer.
Data is input to the buffer memory 5 via the host data transfer control unit 7 and stored therein. This is stored between memory addresses O and β, as shown in FIG.

The central processing unit 6 controls communication with the host computer at that time, and generates and stores control information to be written on the disk 1 up to memory address m−m+n of the buffer memory 5.

As for the error detection code to be generated by the error detection and correction circuit 16, dummy data is stored in the area of the buffer memory 5 where the control information is to be stored. This is because, in this embodiment, the error detection code is generated by the error detection and correction circuit 16, is held therein, and is directly transferred to the disk 1.

Next, the central processing unit 6 instructs to start transferring the data stored in the buffer memory 5 to the disk 1.
The mode switching signal 25 is set to write mode and output to the read-only memory 11. Further, the counter 9 is reset to the initial value, that is, 0. Also, the initial value of the control information read counter 12 is reset to m. Then, the initial value of the data read counter 13 is reset to zero. Thereafter, the inter-disk data transfer control unit 3 is instructed to start a write operation.

Thereafter, the inter-disk data transfer control unit 3 controls all write operations until the write is completed.

When the counter 9 indicates the initial value O, the read-only memory 11 outputs a counter selection signal 29 having a high level content, as shown in FIG. As a result, the signal 5 output from the control information read counter 12 is selected by the selector 14 as the address signal 31 of the buffer memory 5. Since the content is m, the control information C (0
) is read out. The inter-disk data transfer control unit 3
This data is received in parallel from the pass line 4, converted into serial data, transferred to the disk 1, and written. At the same time as writing this 1-byte control signal, the inter-disk data transfer control unit 3 outputs the control clock 21,
Counters 9 and 12 or 13 are counted up.

As shown in FIG. 4, the read-only memory 11 keeps the counter selection signal 29 at a high level until the count value 24 output from the counter 9 reaches 0.1 or 2.3, and the control information readout counter Control is performed so that the output signal of 12 becomes the address signal 31 of the buffer memory 5. Then, at the next timing, the read-only memory 11 sets the counter selection signal 29 to a low level, and the selector 14 selects the output of the data read counter 13 as the address signal 31 of the buffer memory 5.

As a result, data H(0) having the contents shown in FIG. 2 is read from the buffer memory 5.

When this is written to the disk 1 by the inter-disk data transfer control unit 3, writing of 20 pieces of data continues in the same way up to H(19). Then, as shown in FIG. 4, the output of the read-only memory 11 changes to high level again at the next count value.

Then, the output of the control information read counter 12 is used again as the address signal 31 of the buffer memory 5, and the control information C(4) stored at the memory address m+4 is read out. At the next timing, the counter selection signal 29 output from the read-only memory 11 switches to low level again, and as shown in FIG. 4, 20 bytes of data H(20) to H(38) are read out. .

When this operation is repeated and all the data up to the memory address β of the buffer memory 5 is read out, the counter selection signal 29 output from the read-only memory 11 becomes high level, and after that, data writing for one block is completed. Until then, the output of the control read counter 12 is output as the address signal 31 of the buffer memory 5. As a result, the remaining control information up to C (n) shown in FIG. 2 stored in the buffer memory 5 is written to the disk 1.

Incidentally, each time the above data is written, an error detection and correction operation execution signal 26 is outputted from the read-only memory 11 to the error detection and correction circuit 16. As a result, an error detection code is generated by the error detection and correction circuit, and is temporarily stored in a memory (not shown) in the error detection and correction circuit 16. Further, in the control information writing stage after the data transfer is completed, the calculation result output signal 27 is output at a predetermined timing, and the error detection code generated by the error detection and correction circuit is written to the disk 1 as control information. This error detection and correction code typically has a data amount of about 200 bytes, for example. As described above, the read operation of the buffer memory is prohibited while the error detection code is being output.

When all of this control information is written to the disk 1, a termination signal 28 is output from the read-only memory 11 to the inter-disk data transfer control section 3, and the operation of the inter-disk data transfer control section 3 is completed.

Operation in Readout Mode> Next, the operation of reading data and control information from the disk 1 will be described.

First, the central processing unit 6 performs preparation processing for a read operation. The reset process of the counters 9 and 12 or 13 is almost the same as the preparation operation for the write operation, but the mode switching signal 25 output to the read-only memory 11 is changed to one that instructs the read operation. do. In this case as well, the inter-disk data transfer control unit 3
Every time one byte of data or control information is read from the disk 1, the control clock 21 causes the counter 9.12.
13 counts up and inputs the write address signal 31 to the buffer memory 5. As shown in FIG. 2, this write address signal 31 has data up to memory address O-β and control information up to memory address m''.
The outputs of the counters 12 and 13 are selected so that they are written by -m+n.

On the other hand, an error detection and correction operation execution signal 26 is output from the read-only memory 11 to the error detection and correction circuit 16, instructing the error detection and correction operation of the signal read from the disk 1. If there is an error in the read data, correct data is output from the error detection and correction circuit 16 and stored in the buffer memory 5.

In this way, when the data and control information are stored in the buffer memory 5 in the order shown in FIG. 2, reading of data from the disk 1 in the disk control device is completed. Thereafter, the central processing unit 6 notifies the host computer via the host data transfer control unit 7 and the host interface 8 that preparations for data transfer are complete. When the host computer receives this notification, it sequentially reads four pieces of data from memory address O of the buffer memory 5. This operation is performed using the known DMAC (Direct Memory Access Controller). This can be easily implemented because the data is stored sequentially in the buffer memory.

In the case of inter-disk transfer, that is, data transfer to another disk control device of the same type (not shown), the data and control information stored in this buffer memory 5 are transferred in their entirety.

The present invention is not limited to the above embodiments.

The read-only memory 11 provided in the read/write control circuit 10 may be constituted by a random access memory or the like whose contents can be rewritten. This allows the amount and format of data to be written and read by a series of operations to be freely set. Further, the buffer memory 5 is not necessarily a memory configured in one piece,
It may be divided into several parts. Also, a part of it may be configured by read-only memory.

Furthermore, in the above embodiment, 1. Although each counter is assumed to count up each time 1 byte of data is written or read, it is sufficient if an appropriate unit is determined and the counter is counted up every 1 unit. Further, each counter does not necessarily have to count up to increase its count value. In other words, it may be something like a countdown.

Furthermore, various circuits that generate predetermined control information based on the output signal of the read-only memory 11 are provided inside the read/write control circuit, and the control information is output at a predetermined timing instead of the buffer memory. There is no problem in configuring it to do so.

(Effects of the Invention) According to the disk control device of the present invention described above, when writing or reading data etc. to the disk, data etc. stored in the buffer memory can be selectively read out while the counter is performing a counting operation. / writing, the processing speed for so-called data format change processing is increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the disk control device of the present invention, FIG. 2 is an explanatory diagram showing the contents stored in the buffer memory, and FIG. 3 is an explanatory diagram showing the data and control information written to the disk. FIG. 4 is an explanatory diagram of read control of the buffer memory in the apparatus of the present invention. 1...Disk, 2...Serial transmission line, 3.
... Inter-disk data transfer control unit, 4... Pass line, 5... Buffer memory, 6... Central processing unit, 7... Host data transfer control unit, 8... Host interface, 9. 12.13... Counter, 10... Read/write control circuit, 11... Read only memory, 14... Selector, 15-... Inverter, 16...
・Error detection and correction circuit, 21... control clock, 23... enable signal,
24...Count value, 25...Mode switching signal, 28...End signal, 29...Counter selection signal,
31...Address signal. Patent Applicant: Oki Electric Industry Co., Ltd./141 Block diagram of VR installation Figure 1: Memory address Panzer Memory contents Figure 2: (a) Counter 9 0123456 25 ・
・・・ 45 ・ ・ ・Figure 4

Claims (1)

[Scope of Claims] A disk into which data and its control information are written; a buffer memory which stores the data and control information read from or written to this disk; and one unit of data or control information for this buffer memory. A counter that performs a counting operation at read or write timing, and a read/write control circuit that accepts the count value output from this counter and selectively controls reading of data or control information stored in the buffer memory at a predetermined timing. A disk control device comprising: