JPH01113339U - - Google Patents
Info
- Publication number
- JPH01113339U JPH01113339U JP1988008512U JP851288U JPH01113339U JP H01113339 U JPH01113339 U JP H01113339U JP 1988008512 U JP1988008512 U JP 1988008512U JP 851288 U JP851288 U JP 851288U JP H01113339 U JPH01113339 U JP H01113339U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- evaluation
- bonding pad
- edge
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011156 evaluation Methods 0.000 claims description 4
- 239000011093 chipboard Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988008512U JPH01113339U (US07494231-20090224-C00006.png) | 1988-01-26 | 1988-01-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988008512U JPH01113339U (US07494231-20090224-C00006.png) | 1988-01-26 | 1988-01-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01113339U true JPH01113339U (US07494231-20090224-C00006.png) | 1989-07-31 |
Family
ID=31214453
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988008512U Pending JPH01113339U (US07494231-20090224-C00006.png) | 1988-01-26 | 1988-01-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01113339U (US07494231-20090224-C00006.png) |
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1988
- 1988-01-26 JP JP1988008512U patent/JPH01113339U/ja active Pending