JPH01113338U - - Google Patents

Info

Publication number
JPH01113338U
JPH01113338U JP1988008511U JP851188U JPH01113338U JP H01113338 U JPH01113338 U JP H01113338U JP 1988008511 U JP1988008511 U JP 1988008511U JP 851188 U JP851188 U JP 851188U JP H01113338 U JPH01113338 U JP H01113338U
Authority
JP
Japan
Prior art keywords
chip
evaluation
bonding pad
edge
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988008511U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988008511U priority Critical patent/JPH01113338U/ja
Publication of JPH01113338U publication Critical patent/JPH01113338U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP1988008511U 1988-01-26 1988-01-26 Pending JPH01113338U (US07135483-20061114-C00003.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988008511U JPH01113338U (US07135483-20061114-C00003.png) 1988-01-26 1988-01-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988008511U JPH01113338U (US07135483-20061114-C00003.png) 1988-01-26 1988-01-26

Publications (1)

Publication Number Publication Date
JPH01113338U true JPH01113338U (US07135483-20061114-C00003.png) 1989-07-31

Family

ID=31214451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988008511U Pending JPH01113338U (US07135483-20061114-C00003.png) 1988-01-26 1988-01-26

Country Status (1)

Country Link
JP (1) JPH01113338U (US07135483-20061114-C00003.png)

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