JPH01112357A - Multiprocessor circuit - Google Patents

Abstract

PURPOSE:To perform fast operations by plural processors by performing the load of data to be processed on each CPU module and the readout work of processed result data in parallel with a processing in each CPU module. CONSTITUTION:When the data to be processed are loaded sequentially from an input bus, those data are divided appropriately by a load control part 4 and sent to the memory 101 of each of the CPU modules 1-1-1-3. After that, those data to be processed are worked and processed in each CPU module, and a processed result is accumulated in the memory 101 of each CPU module. An accumulative processed result is outputted to the outside under the control of a readout control part 5 via an output bus 3. And on the CPU module completing one divided data and being set at a null state, the next data to be processed is loaded from an input bus 2 after being divided, and such processing is repeated. In such a way, it is possible to increase processing speed and to improve the performance of data transfer in a main bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor circuit that uses a plurality of processor units to perform data processing in parallel at high speed.

[Prior art] In fields where large amounts of data need to be processed at high speed, such as various simulation processing and image processing,
Parallel processing is gaining momentum.

One such parallel processing is SIMD (Single Ins), which is an extension of conventional sequential processing.
tractionMulti Data Stream
) type of parallel processing processor, it is composed of a large number of processors, and by dividing and performing processing in parallel, MIM
D (MultiInstruction Mul
tiData Stream) type multiprocessor systems have been prototyped or partially commercialized.

In order to use this MIMD type system as a general-purpose system, there is a major algorithmic problem of how to perform so-called parallelization of processing.
Thanks to research into program description languages, an environment more suitable for parallel processing is beginning to be created. Furthermore, when looking at these systems from a hardware perspective, advances in LSI technology have made it possible to use microcomputers at low cost, and there is a possibility of realizing low-cost MIMD-type systems by using multiple microcomputers to create multiprocessors. is also becoming visible.

The general characteristics of MIMD-type systems include (a) a highly cyclical hardware configuration using multiple processors, and a large-scale system can be constructed with a small number of hardware components;

(b) This depends on the composition method, but the faith of the processor is
Since the system can be easily modified without changing the overall system architecture or by making a slight change, it is easy to obtain a system that has a processing capacity suitable for the purpose.

(C) Because it has a periodic hardware configuration, it has many similar circuit parts. For example, when a hardware failure occurs, the faulty part is isolated and other parts take over and continue processing. It is conceivable that a fault-tolerant computer system (so-called fault-tolerant system) can be obtained.

In this way, in place of the SIMD type, which has begun to show its limits in processing capacity, MIMD type systems, which can improve their processing capacity by adding processors, are expected to expand new fields of application for computers.

Now, as a method for connecting individual processors in a MIMD type processor system, a two-dimensional or three-dimensional mesh type configuration as shown in FIG. 7, or a plurality of processors connected to a common bus 81 as shown in FIG. Some processors are connected in parallel. The former is suitable for processing a large amount of data that is mutually correlated, or for data flow processing that changes the processing bus depending on the data processing, while the latter is suitable for processing a large number of data that has relatively weak correlation between data and is easy to divide and process ( For example, it is suitable for processing vector data). This is because when the data correlation is large, processing data is transferred frequently between the processors, which requires more communication paths (buses) between the processors.

The mesh type configuration as shown in Fig. 7 requires many circuits for the interface (1/F) between processors and is expensive, so for certain specific data processing applications, The bus-type coupling shown in FIG. 8 is often more advantageous.

By the way, in recent years, DSP (Digit
Al Signal Processor) has appeared on the market and is beginning to be used for communication signal processing and the like. Communication signals are required to be processed at high speed, that is, to output processed results quickly in response to data input.

For example, if a very high-speed DSP or a multi-channel DSP (processing multiple signals in parallel) can be developed, it can be used not only for still images but also for video signal processing. It is expected that such a market will become very large in the future.

The configuration of the SP is similar to that of a SIMD system, and internally the Vibration method is used to speed up processing, but since it is a single processor, improvements in processing performance can be made in addition to speeding up the elements. Therefore, it is disadvantageous in terms of multi-channel processing. Therefore,
If a processor system capable of high-speed processing can be obtained by connecting such SPs in a multiprocessor configuration such as the MIMD type system described above, it could become a very promising system in many fields.

The general trends of the prior art have been described above, but if we examine the surroundings of the processor in more detail, there are major problems.

As mentioned above, an inexpensive system can be realized by constructing a general-purpose microcomputer that is compatible with MIMD system systems, but the architecture of commercially available microcomputers has been developed as a mini-model of conventional mainframe computers. It has been developed with the focus on improving the performance of the car's CPU, rather than multiprocessorization. Therefore, multiprocessorization using such a microcomputer has a very disadvantageous aspect.

In other words, the system configuration using a microcomputer is based on the "bus" of the microcomputer, as shown in Figure 9, and includes a CPU, memory such as ROM/RAM, DMA controller (DMAC), timer, and other I10 devices. take the form of a connection. All data such as program data, processing data, and input/output data from Ilo are transferred by a one-tree microcomputer bus. Therefore, each device connected to this bus must operate with defined bus timing specifications.

Therefore, even if a memory that can operate at a higher speed than this bus timing is adopted in such a system, the memory must operate at a lower speed due to the timing limitations mentioned above, and these systems This will not contribute to improving the performance of.

Furthermore, when DMA (direct memory access) operation is used, the speed of normal data processing by the CPU is reduced. This is because the CPU is temporarily stopped during DMA operation. Thus, the transfer capacity of such a bus is not high enough to allow several devices connected to the bus of a microcomputer to operate simultaneously in parallel.

Therefore, even if a plurality of CPUs are connected to the bus of a numerical microcomputer to construct the above-mentioned bus type MIMD system, parallel operation is impossible and the system becomes meaningless as a multiprocessor.

One solution to this problem is a hierarchical structure of the microcomputer bus. Hierarchical bus configurations have long been used in so-called mainframe computers, but recently, for purposes that exceed the capabilities of a single microprocessor, multiprocessor configurations have been used to increase processing power. It is used to improve Along with this, microcomputer manufacturers have proposed several methods to eliminate the above-mentioned "bus neck."

For example, Intel's Mult as shown in Figure 10
As seen in the iBus, there is a system that provides a trunk bus (main bus) in addition to a bus for each CPU (local bus), and connects these buses by a bus arbiter circuit. This allows each CPU in the system to operate independently because it is given an individual bus, and each CPU
Only when communicating between devices, data is transferred and received via the bus arbiter and main bus.

However, when this main bus is compared with an internal bus corresponding to the main bus of conventional mainframe computers, there is a clear difference. In other words, while the conventional internal bus in the main claim has sufficient data transfer capacity to operate multiple CPUs simultaneously, the main bus in FIG. It only has the data transfer ability of .

Nevertheless, as part of the MIMD machine operation, when processing results from each CPU are collected from each CPtJ all at once, it is expected that a considerable load will be added to the main bus, but the main bus data Since the transfer capacity is small, a bus neck condition occurs in the same way as in the case of the post-CPU bus, and the throughput of the system decreases. In other words, even if you have a bus hierarchy configuration, simply providing buses distributed among cars will only probabilistically reduce the frequency of bus access, and in cases where the load is concentrated on a specific bus at a time. This effect cannot be obtained, and a bus having a transfer capacity corresponding to the hierarchical level is required.

In order to expand the transfer capacity of such a main bus, the specifications of the local bus and the main bus must be changed, and in this case, the bus access configuration becomes complicated. In addition, each CPU is composed of a commercially available microcomputer that has been converted into an LSI, and the surrounding LSIs are also used in accordance with the operating timing of the CPU.
The bus timing can only be changed within the timing specified by . For these reasons, the local bus and the main bus are configured with buses that use the same system or the same system, making it difficult to increase the transfer capacity of only the main bus.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned conventional examples, and provides a multiprocessor circuit that improves the processing speed in multiprocessor microcomputers and expands the data transfer capacity of the main bus. The purpose is to

[Means for Solving the Problems] In order to achieve the above object, the multiprocessor circuit of the present invention has the following configuration. That is, a plurality of CPU circuits connected in parallel between an input bus and an output bus, a selection means for cycling through and selecting a predetermined number of data blocks from the plurality of CPU circuits, and a memory address of the selected CPU circuit. an address means for outputting a signal; an access means for directly inputting and outputting data to and from the memory of the CPU circuit via the input bus and the output bus; when accessing by the access means, the CPU circuit is placed in a halt state; and means for releasing the halt state when data is input to the CPU circuit to be accessed.

[Operation] In the above configuration, the selection means circulates and selects a plurality of CPU circuits connected in parallel between the input bus and the output bus, and the CPU circuit selected by the address means Outputs memory address signal. In the memory of the CPU circuit selected in this way,
Directly input and output data via input and output buses.

At this time, the CPU of the CPU circuit is placed in a halt state, and operates to release the halt state when data is input to the CPU circuit to be accessed next.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Multiprocessor Circuit (FIG. 1)] FIG. 1 is a block diagram showing the configuration of a multiprocessor circuit according to an embodiment.

The circuit shown in Figure 1 is an MIMD type multiprocessor circuit, and the data transfer timing to each CPU is determined by the host C
It is not controlled by the PU or the like, but can be determined between each CPU module. This enables high-speed data transfer, and is configured to be able to be incorporated into a circuit that inputs, processes, and outputs data to be processed, such as the above-mentioned DSP.

In Figure 1, 1-1 to 1-3 are CPs for data processing.
In the U module, each CPU module has the same configuration. The CPU module includes a CPU 100 such as a microprocessor. A ROM that stores control programs and data for the CPU 100, and an RA that is used as a work area for the CPU and temporarily stores various data.
It includes a memory 101 including M and the like, an input/output board 102, and the like. Further, 103 and 104 are both bus switching circuits that perform connection switching between the local bus 12 inside the CPU module and an input/output bus outside the CPU module.

2 is a data input bus, 3 is a data output bus, and a plurality of CPU modules 1-1 to 1-3 are connected in parallel between the input bus 2 and the output bus 3. The number of CPLJ modules can be increased or decreased depending on the load caused by processing data. For example, when one page of image data to be processed is sequentially loaded from the input bus 2, these data are sequentially sent to the memory 101 of each appropriately divided CPU module. Thereafter, these processed data are processed within each CPU module, and the processing results are stored in the memory 101 of each CPU module.

The processing results stored in the memory 101 of each CPU module in this way are output to the outside via the output bus 3 under the control of the read control section 5.

Then, the next divided data to be processed is further divided and loaded from the input bus 2 to the CPU module which is in the "empty" state after processing one divided data, and the above processing is repeated. These operations continue until there is no more data to be processed input to the system, or until some kind of operation termination instruction is received.

Reference numeral 4 designates a load control unit that determines whether to distribute input data to the CPU module, and reference numeral 5 designates a read control unit that determines whether to read and output data from the CPU module. These control the switching of the connection between the input bus 2 or output bus 3 and the CPU module by outputting a selection signal for each CPU module or memory address data.

The input of processed data from the input bus 2 to the multiplexer circuit and the output of processed result data from the output bus 3 and readout control unit 5 are similar to input/output operations to a FIFO (first-in, first-out) circuit. There is. That is, the strobe signal 6 is input to the load control section 4, and the input enable signal 7 is output from the load control section 4. The strobe signal 6 is a timing signal for inputting the data to be processed to the input bus 2. Further, the input enable signal 7 is a signal indicating to the outside that input to the multiplexer circuit is possible.

Therefore, the external device checks the input enable signal 7, and
If is true (high level), the data may be output to the input bus 2 and the strobe signal 6 may be output.

Further, the strobe signal 10 of the read control section 5 is transmitted to the output bus 3.
This is a signal from the outside indicating that the above processing result data has been taken out to the outside, and instructs the multiprocessor circuit to output the next data to the output bus 3. Further, the output enable signal 11 is a signal for indicating to the outside that valid processing data exists on the output bus 3.

The input/output bus interface operation described above allows multiprocessor circuits to be incorporated not only into conventional large-scale calculation systems but also into devices as circuit units similar to FIFO circuits, expanding the range of applications of multiprocessor circuits. I have to.

FIG. 2 is a diagram showing connections between the input bus 2 and output bus 3 of the multiprocessor circuit of the embodiment and the local bus 12.

Data on the input bus 2 is input to the local bus 12 when the enable signal 13 is at a low level, and at the same time, the address signal 8 from the load control section 4 is also input to the local bus through the bus switching circuit 103. Similarly, when outputting from the local bus 12, the enable signal 14 from the read control unit 5 becomes low level, so that the address signal 9 is transferred from the bus switching circuit 104 to the local bus 12.
It is output to the second address line. The data designated by this address is then read out onto the data line of the local bus 12 and output to the output bus 3 through the bus switching circuit 104.

Note that when the enable signals 13 and 14 go low, the CPU of the corresponding CPU module must be stopped (in a halt state) and the local bus of that CPU module must be in a floating state.

[Description of the load control unit and readout control unit (Figs. 3 to 4)] Fig. 3 is a block diagram showing a schematic configuration of the load control unit 4. It is the composition.

40 is a counter that inputs and counts the strobe signal 6. The upper several bits of the output of the counter 40 are input to a decoder 41, and the output of the decoder 41 serves as a CPU module selection signal (enable signal). The lower output bit of the counter 40 is output as an address signal 8 and becomes the address of the memory 101 of the CPtJ module. The output of the decoder 41 is output as an enable signal for the bus switching circuit 103 or a halt signal for the CPU. These operations will be explained in detail with reference to FIG.

Note that after the counter 40 overflows, it returns to the "zero state" and the count operation reaches 1! Continued. Therefore, every time access for a certain address block is completed, the CPU modules 1-1 to 1-n are sequentially selected and the CPU
The CPU module 1-1 is selected again after the U module 1-n.

[Operation Description (FIGS. 4 to 6)] FIG. 4 is a diagram showing a specific example of the multiprocessor circuit of the embodiment, and FIG. 5 is a diagram showing the operation timing of each CPU module.

In the initialization process before starting operation, the CPU of each CPU module sets the flip-flop 105 by ■10 ports and waits in a halt state (C
The PU 100 enters a halt state when the halt signal 25 is at a high level).

Flip-flops 106 and 107 are initially reset, signal 20 is at low level (not ready), and signal 22 is at high level (ready). Initially, the output of the counter 40 of the load control unit 4 is “0”, so
The 0 input (signal 22) of the selection circuit 43 is selected by the upper bit data 44 and outputted as the input enable signal 7.

Now, when loading to the CPU module is performed through the load control unit 4, since the CPU module 1-1 is selected by the decoder 41, the data on the input bus 2 is sequentially transferred to the address of the memory 101 addressed by the counter 40. Stored. When a predetermined number of data is stored in the memory 101 in this way, the upper bit data 44 is +1
Then, CPU module 1-2 is selected.

The above operation is shown at timing T60 in FIG.

To explain this operation with a concrete example, if the address space used in the memory 101 is 64 bytes and the number of CPU modules is 8, the number of bits in the counter 40 is 19.
Becomes a bit. Since all outputs of the counter 40 are initially O, memory address 10100 of the CPU module 1-1 is accessed, and data on the input bus 2 is written to the memory 101 at the timing of the strobe signal 6. As a result, the counter 40 is incremented by 1, and data is then written to address 1 of the memory 101. When the 64th byte of data is transferred to the memory 101 in this way, the upper 3 bits are incremented by 1 and the CPU module 1-2 is selected.

Since the upper bit data is incremented by +1, the CPU module 1-2 is selected and the signal 23 is output from the selection circuit 43 as the input enable signal 7.

At this time, when the load signal 24 is output from the decoder 41, the flip-flop 105 of the CPU module 1-1 is reset, the CPU 100 is released from the halt state, and starts processing operation (timing T61).

When the CPU 100 starts operating, it first sets the flip-flop 106 and makes the signal 22 low level (C
input to PU module 1-1 is not possible). After the data processing in the memory 101 is completed and the processed data is stored in the memory 101 again, the flip-flop 107 is set, the signal 2° is set to high level, and the CPU module 1-1
Outputs the output enable signal. At the same time, the flip-flop 105 is set to make the signal 25 high level, and the system enters the halt state again.

Since the output of the counter 50 of the read control section 5 is "0", the 0 input of the selection circuit 53 is selected, and when the output enable signal 11 is output, the memory 101 is read from the external device.

When this reading is completed, flip-flops 106 and 10
7 is reset and signal 20 is low level (output not possible),
The signal 22 becomes high level (timing T62). Note that at this time, since the flip-flop 105 remains set, the CPU 100 remains in the halt state.

CPU modules 1-1 to 1-n are sequentially accessed,
When the timing comes to load data into the CPU module 1-1 again, the counter 40 has become "0", so the data is loaded into the CPU module 1-1 again as described above.
Data is loaded into the input bus 2 through the input bus 2.

In this way, the CPU of each CPU module is released from the halt state in the order in which the processing data has been loaded, and the data stored in memory is processed, and after the processing is completed, the processing result is transferred to the CPLI module. It is stored in its own memory and becomes halted again. Similarly to the input bus 2 side, on the output bus 3 side, the address is updated by the strobe signal 10, and the output bus 3 and the modules are switched in the order of CPU modules 1-1 to 1-n.
The processing results are being read from the module's memory.

FIG. 6 is a flowchart showing the CPU operation program of each CPU module, and this program is stored in the memory of the CPtJ module.

The case of the CPU module 1-1 will be explained below.

At the start of the program, flip-flops 105-107 are all reset. In step S1, the flip-flop 105 is set from the I10 port 102 to enter a halt state. During this halt state, data is transferred from the input bus 2 to the memory 101 and stored therein.

After the data transfer to CPU module 1-1 is completed,
When the PtJ module 1-2 is selected, the flip-flop 105 is reset by the signal 24, and the CPU 10
The halt state of 0 is released.

The process then proceeds to step S2, where the flip-flop 106 is set and the signal 22 is turned off. In step S3, the data stored in the memory 101 is processed, and in step S3 it is checked whether all data has been processed. When all data has been processed, the process proceeds to step S5.
In addition to storing processed data in the memory 101,
Set the flip-flop 107 to make the signal 2LO high level (output enable signal on). At the same time, the flip-flop 105 is set to put the CPU 100 into the halt state again.

In this way, while the CPU 100 is halted, the data in the memory 101 is read, and when the CPU module 1-2 is accessed next, the flip-flop 106 is reset and the signal 22 becomes high level, causing the CPU module 1-2 to be accessed.
One input enable signal will be output.

In this way, as shown in FIG. 5, each CPU module is sequentially accessed cyclically, and data processing is executed within each module.

At the point indicated by 69 in Figure 5, processing by each CPU is being performed in parallel, and if n is the small number of CPtJ modules, data processing is n times faster than in the case of a single CPU. However, when looking at the effective value of the overall processing speed, it is lower than n times. This is because the time required for loading the data to be processed and reading the processing result data (the time during which the CPU is in a halt state) is involved, during which each CPU temporarily stops operating. In the worst case, two CPUs out of the n-times CPUs, one for load operations and one for read operations, may be stopped, and the actual processing capacity is approximately n. times~n
-It will be doubled. In order to improve this substantial throughput, it is desirable to shorten the time required for loading/reading.

This problem can be solved very easily by this embodiment.

That is, since the CPU of each CPU module is in the halt state, loading/reading is directly performed from the main bus to the memory, so the main bus operation can be performed regardless of the operation timing of the local bus. Therefore, it is only necessary to make the memory element of the CPU module high-speed. This makes it possible to perform memory access that takes full advantage of the access time of high-speed memory, which was conventionally controlled in accordance with the timing of the microcomputer.

As explained above, according to this embodiment, it is possible to load processed data from the main bus to each CPU module, read processing result data, and perform processing in each CPU module in parallel. High-speed processing was achieved using the processor.

Furthermore, since the CPU of the local bus is placed in a halt state to stop the operation of the local bus and the RAM of the local bus is accessed from the main bus, the configuration of the bus switching circuit corresponding to the bus arbiter can be made inexpensive and simple. realizable.

In addition, by making the RAM in the local bus high-speed that satisfies the access speed from the main bus, the data transfer speed of the main bus can be improved, and the bus switching circuit can be used to increase the speed of the main bus and local bus. Buffering function for difference absorption can be made unnecessary.

[Effects of the Invention] As explained above, according to the present invention, loading of processed data to each CPU module, reading of processing result data, and processing in each CPU module can be performed in parallel. High-speed processing using multiple processors is now possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of the multiplexer circuit of the embodiment, FIG. 2 is a diagram showing a specific example of the bus switching circuit, FIG. 3 is a diagram showing the schematic configuration of the load control section, and FIG. 4 is the CPU 5 is a diagram showing the timing of FIG. 4, FIG. 6 is a flowchart showing the operation of the CPU of each CPU module, FIG. FIG. 8 is a diagram showing an example of a conventional multiplexer circuit, FIG. 9 is a diagram showing a bus configuration of a single processor system, and FIG. 10 is a diagram showing a bus configuration of a conventional multiprocessor system. In the figure, 1-1 to 1-n = CPU module, 2
...Input bus, 3...Output bus, 4...Load I
J fil section, 5...readout control section, 6.1o...
Strobe signal, 7... Input enabled signal, 8.9... Address signal, 11... Output enabled (i number, 12... Local bus, 13.14... Enable signal, 25...
・Halt signal, 40.50...Counter, 41.5
1... Decoder, 43.53... Selection circuit, 100
...CPU, 101...Memory, 102...Bow 10
Boat, 103, 104...Bus switching circuit, 105~
107...Flip-flop. Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] Multiple CPs connected in parallel between input bus and output bus
a U circuit, a selection means for cycling through and selecting the plurality of CPU circuits in units of a predetermined number of data, an address means for outputting a memory address signal of the selected CPU circuit, and the input bus and the output bus. an access means for directly inputting and outputting data to the memory of the CPU circuit; and when accessing by the access means, the CPU circuit is placed in a halt state, and when data is input to the CPU circuit to be accessed next, the halt state is brought to a halt state. A multiprocessor circuit comprising means for releasing the signal.