JPH01109593A - Memory control circuit - Google Patents

Abstract

PURPOSE:To shorten a time lapse until the outputting of a column address strobing signal and to shorten access time to a memory by detecting the switching of an address signal from raw address to column address directly and outputting a column address strobing signal. CONSTITUTION:The processor 1 of a memory control circuit controls the whole circuit, and a timing control circuit 2 generates a timing control signal for a write/read to/from a memory, at this time, the circuit 2 outputs an address switching signal ACS and a raw address strobing signal RAS. By this switching signal ACS from the circuit 2, an address signal from the processor 1 is switched. In a comparator circuit 4, a column address from the processor 1 and that from an address selector 3 are compared with each other, and a coincidence signal is outputted therefrom. By this signal, the switching from an address to a column address is confirmed; an AND circuit 5 takes the AND of a switching signal and a coincidence signal, to output a column address signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control circuit for controlling a memory such as a DRAM that requires a row address strobe signal and a column address strobe signal in addition to an address signal. The present invention relates to a memory control circuit configured to reduce the output time of a strobe signal.

[Conventional technology]

- DRAM used in i (Guinaminoku RAM
), in addition to the address input signal, the row address strobe signal (RAS signal) and column address strobe signal (
CAS signal). The general configuration of this DRAM is explained in the third section.
As shown in the figure. In the figure number, 10 is DRAM, 11
is a memory section, 12 is a data bus, 13 is an internal row address signal, 14 is an internal column address signal, 15 is an address buffer, and 16 is an address bus.

FIG. 4 shows a time chart of the DRAM address control signal. As shown in the figure, the row address signal is output to the address bus 16, the RAS signal becomes "0", the address switching signal changes to "0", and the address is switched from the row address to the column address. After the address is switched, the CAS signal becomes rOJ. Here, the time Tc from when the address switches until the CAS signal switches
can theoretically be zero.

Since it is not possible to directly detect the CAS signal from changes in the address, the C
The AS signal was being switched. To generate the time Td,
Using delay elements or clock timing.

[Problems to be solved by the invention] However, the general accuracy of the delay element is low, and it is necessary to provide a margin for safety, which increases the time Td.
Memory access time increases.

Furthermore, when clock timing is used, since it is restricted by the clock time, it is not possible to use the optimum time, resulting in wasted time.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a memory control circuit configured to reduce the output time of a column address strobe signal.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a memory control circuit that controls a memory that requires a row address strobe signal and a column address strobe signal in addition to an address signal. a timing control circuit that generates a signal, a row address strobe signal, etc.; an address selector that switches an address signal from a processor according to an address switching signal from the timing control circuit; a column address signal from the processor; a comparison circuit that compares column address signals from the address selector and outputs a match signal when they match, and performs a logical product of the match signal of the comparison circuit and the address switching signal from the timing control circuit;
A memory control circuit is provided, comprising: an AND circuit that outputs the AND signal as a column address signal.

[Effect]

The comparison circuit compares the column address signal from the processor with the column address signal from the address selector, confirms that the output of the address selector has been switched to the column address signal, and outputs a match signal.

Next, the address switching signal of the timing control circuit and the coincidence signal of the comparison circuit are ANDed, and this is output as a column address strobe signal (CAS signal).

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 shows a block diagram of a memory control circuit according to an embodiment of the present invention. In the figure, 1 is a processor, and 2 is a timing control circuit that generates timing control signals for writing, reading, etc. to the memory.

Here, the timing control circuit 2 uses an address switching signal (AC3 signal) and a row address strobe signal (
RAS signal) is output. 3 is an address selector, which switches the address signal from the processor 1 in response to an address switching signal from the timing control circuit 2; A comparison circuit 4 compares the column address signal from the processor 1 and the column address signal from the address selector 3, confirms that they match, and outputs a match signal. - If there is a match signal, it means that the address signal has completely switched to the column address signal.

Reference numeral 5 denotes an AND circuit, which performs an AND operation between the address switching signal from the timing control circuit 2 and the match signal from the comparison circuit 4. Since the address switching signal changes from 'IJ' to '0' when switching from a row address to a column address, a dwarf is attached to the input of the AND circuit 5 to indicate inversion. Furthermore, the output of the AND circuit 5 is output as a column address strobe signal (CAS signal);
Since the S signal side also changes from "1" to "0" when the address switches from a row address to a column address, a dwarf is attached to the output to indicate the inversion of the signal. 6 is a DRAM (dynamic RAM).

Next, the operation of the memory control circuit of this embodiment will be described.

FIG. 2 shows a time chart of the operation of the memory control circuit of this embodiment. An address signal is output from the processor 1 and input to the DRAM 6 via the address selector 3. The RAS signal changes from "1" to 'OJ' and the row address is stored in the DRAM 6. Next, an address switching signal (AC8 signal) is output from the timing control circuit 2 to the address selector 3, and the address selector 3 switches the output from the row address to the column address.

Comparison circuit 4 compares the column address signal of processor 1 and the column address signal output from address selector 3, confirms that the address signal to DRAM 6 has been switched to the column address signal, and outputs a match signal. The AND circuit 5 takes the AND of the address switching signal and the coincidence signal, and outputs this as a CAS signal. Therefore, the CAS signal signal is output after the delay time Ta of the AND circuit 5 after the address is switched, and the time is considerably shortened compared to the conventional memory control circuit. Generally speaking, in a conventional memory control circuit using a delay element, the delay time was about 40 ns, but in this embodiment, it was possible to reduce the delay time to about 1 Qns.

〔Effect of the invention〕

As explained above, in the present invention, the switching of the address signal from the row address to the column address is directly detected and the column address strobe signal is output. The time required to access memory such as DRAM is reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory control circuit according to an embodiment of the present invention. FIG. 2 is a time chart of the operation of the memory control circuit of this embodiment. FIG. 3 is a schematic configuration diagram of a DRAM. 1 is a time chart of DRAM address control signals; FIG. 1-111--------Processor 2-----1 Timing control circuit 3-
-----------Address selector 4---m---
・-・-Comparison circuit 5--・---1--Local product circuit 6------1・DRAM CA 5---------1 Column address strobe signal RA 5- ---------1 Row address strobe signal A C5-- Address switching signal Patent applicant: FANUC Co., Ltd. Agent Patent attorney: Takeiwa Hattori Figure 3 Figure 4

Claims (2)

[Claims] (1) In a memory control circuit that controls a memory that requires a row address strobe signal and a column address strobe signal in addition to an address signal, an address switching signal for writing to and reading from the memory, a row address strobe signal, etc. are generated. a timing control circuit; an address selector that switches an address signal from a processor in response to an address switching signal from the timing control circuit; a column address signal from the processor and a column address signal from the address selector; , a comparison circuit that outputs a match signal when a match occurs, and a logical product of the match signal of the comparison circuit and the address switching signal from the timing control circuit;
A memory control circuit comprising: an AND circuit that outputs the AND signal as a column address signal. (2) The memory control circuit according to claim 1, wherein the memory is a DRAM.