JPH01108825A - Receiver - Google Patents

Abstract

PURPOSE:To obtain a receiver with simple constitution and high accuracy by discriminating an extracted timing signal, and correcting a frequency error of a signal supplied to an equalizing means. CONSTITUTION:The titled receiver is provided with an equalizing means 114 absorbing a phase error of a demodulated data, a means 180 extracting a timing signal from the demodulated data and a means discriminating the timing extracted by the means 180, and correcting the frequency error of the signal supplied to the equalizing means. That is, the phase error in the timing error is absorbed by the equalizer 114 by using the equalizing method as the equalizer 114 and only the remaining timing frequency error is eliminated by only providing a counter 172, a comparator 174 and a counter overflow detection circuit 181 without providing any complicated PLL(Phase Locked Loop) circuit. Thus, the timing error is cancelled with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a receiving device, and particularly to a receiving device that corrects distortion of a received signal in a transmission path.

<Prior art> By using a conventional modem, it is possible to transmit signals via a general public line.

In this case, in order to reliably transmit data, it is necessary to match the data timing between transmission and reception, that is, the timing at which data is sent out on the sending side, and the timing at which data is taken in on the receiving side. This timing deviation includes an error in the frequency component of each timing and an error in the phase component of each timing. The former is due to differences in oscillators that are provided separately on the transmitting and receiving sides and determines various data processing timings, and the latter is due to differences in initial timing between the two.

Conventionally, these phases and frequencies are both controlled by valves, so P L
Feedback control was performed using a method called L (Phase 1ock 1oop).

<Problems to be Solved by the Invention> However, this method has a complicated structure. For example, when a digital signal processor (DSP) is used, the calculations for PLL control are relatively complicated, so It takes time, and the amount of software required to predetermine the calculation steps described above increases, and in the worst case, it may be necessary to use a plurality of DSPs in multiple ways.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a highly accurate receiving device with a simple configuration that eliminates the drawbacks of the above-mentioned conventional example.

<Means for solving the problem> Equalizing means for absorbing phase errors of demodulated data, means for extracting a timing signal from the demodulated data, and determining the timing signal extracted by the means to and means for correcting frequency errors in the signal supplied to the equalization means.

<Embodiment> First, the configuration of a modem to which the timing regeneration method of the present invention is applied will be explained using FIG. 4.

In FIG. 4, 100 is a transmitting terminal that generates a transmitted digital signal, and 118 is a receiving terminal.

101 is a scrambler that whitens data to prevent continuous output of the same data; 102 is a scrambler 10;
1 is an encoder that assigns a code to the signal from 1 to each tribit, dibit, etc., 103 is a waveform type filter (roll-off filter) that prevents signal code amount interference, and 104 is a modulator that modulates the signal.

Many modulation methods have been considered, depending on data transfer speed, etc., and typical ones include phase modulation, which changes the phase of the carrier wave, and frequency modulation, which changes the same frequency.
FSX), amplitude modulation (AM) that changes the amplitude, and quadrature amplitude modulation (QAM) that changes the amplitude and phase.

This modulated signal is sent to the analog line by D/
The A converter 105 converts the signal into an analog signal, and a low-pass filter 106 removes excess harmonic components, and the signal is transmitted to a transmission line.

Next, on the receiving side, components outside the transmission band of the transmitted signal are removed by a bandpass filter 110, the signal level is controlled by the AGCll, which is handled by the receiving side, and the A/D
A converter 112 converts the signal into a digital signal, and a demodulator 113 demodulates it to the original signal (signal before modulation).

Here, reference numeral 114 is referred to as a filter, which removes mold components from the phase distortion received in the transmission path from the transmitted signal, thereby extracting the original transmitted signal.

The output signal of this equalizer 114 is determined to be a code point by a determiner 115, decoded by a decoder 116, and sent to a transmitting terminal by a discranturer 11γ for restoring the whitened signal by a scrambler 101. 100 is returned to the generated signal and received by the receiving terminal 11B.

Next, using FIG. 1, the A/D converter 11 shown in FIG.
A detailed explanation will be given of an example of the timing frequency error control section that controls the 2 demodulator 113, the 114, etc.

In Fig. 1, 112, 113, 114 are the A/
It is a D conversion, a demodulator, and a double sample vase. From the demodulated output signal Rk=A+jb (normally data is treated as a complex number), a timing extraction section 180 (as is well known, this section passes only the modulation frequency and the section 170 that squares and adds the real and imaginary parts of Rk, A bandpass filter 171 that extracts only the modulated carrier component extracts only the modulated frequency (=1/T) component. An example of this extracted signal is shown in FIG. Since the data is a discrete system, A/D conversion 11 is shown in Figure 2, where the data in the analgeg region is also added as a dotted line to make it easier to see whether it is actually obtained as shown in the solid line.
The conversion interval Δt of 2 is set to 1/8 of the modulation synchronization.

Signal inversion (zer) of the signal obtained in this FIG.

cross point) are sequentially counted by the counter B172. In other words, this count value becomes regular timing information because it is a modulation synchronization component included in the data.

On the other hand, the conversion timing of the A/D converter 112 is generated by dividing the basic clock from the reference oscillator 175 by a frequency divider 176. The frequency division ratio of the frequency divider 176 is set in advance so that the synchronization of its output corresponds to 1/8 of the modulation period T' shown in FIG. Frequency divider 177 further divides the output of frequency divider 176 by four. Therefore, the period of the output of the frequency divider 177 is set to 1/2T'', and this signal is input to the counter A173, which counts up using this signal as a trigger.In other words, the count value of the counter A is information including a timing error from the receiving side. 185 is a difference device that calculates the difference between the count values of counter A 173 and counter B 172, and 181 is the difference device 185 at that time when a carry-up output is obtained from either counter A or counter B 172.
This is an overflow detector that outputs an addition instruction that causes the differential integrator 186 to settle the output of , and then outputs an instruction that clears counters A and B, respectively. The overflow detector 181 is a delay circuit that outputs the OR of the carry-up outputs of the counters A and B to the differential integrator 186, and also outputs a signal obtained by delaying the OR output by a predetermined time to the counters A and B as a clear signal. It consists of

186 is the difference integrator, which integrates the output of the difference integrator 185 every time the output from the overflow detector 181 is obtained. Reference numeral 174 indicates a counter value comparison circuit that compares the output of the integrator 186 and the preset value output from the preset value generation circuit 187, although the reference numerals are different.

Further, the frequency divider 176 increases or decreases the frequency division ratio only during a certain period when the output of the counter comparator 174 is inverted.

In the embodiment with the above configuration, the integrated result of the difference between the count values of counter A and counter B corresponds to the phase difference and frequency difference between the transmitting clock on the transmitting side and the receiving clock generated from the oscillator 175 on the receiving side. However, in this embodiment, since the above-mentioned four phase differences are corrected by the equalizer 114, the integration result of the difference between the counts of counters A and B is used to correct the above-mentioned frequency difference.

That is, if the integration result in the counter value comparator 174 exceeds a preset value, the A/D conversion timing of the A/D converter 112 is thinned out by increasing or decreasing the frequency division ratio of the frequency divider 176. , or the above-mentioned frequency difference is corrected by controlling it to increase.

Next, an example of the equalizer 114 that absorbs timing phase errors will be explained using FIG. 3. The details of this equalizer are described in ``Equalization Method to Absorb Timing Phase Shift'' published in May 1949 during the Communication System Research Interval. FIG. 3 shows a block diagram of the double sampling equalizer. The isolator is generally a transversal filter. 130 is a delay element that delays the received data, 131 is the delayed data directly above and the multiplier 13
The tap gain 133 multiplied by 2 is a summator that sums up the multiplication results. In the equalizer of this embodiment, the interval of data entering the equalizer and the delay time of the delay element of the filter are set to 1/2 that of a normal equalizer. That is, a T/2 sec sampler 136 is arranged at the data input section, and the delay time of the delay element is set to T/2 Sec. In other words, in a normal equalizer, data is input at intervals of T5ec (modulation period), so the delay time of the filter delay element is also Tsec, whereas in double sample equalization, data is input manually at intervals of T/2sec,
The delay time is also T/2 sec. However, in the case of double sample equalization, T sec sampler 137 is sent to the equalizer output section.
The MSE method (MeanSquave Er
Adjustment of the isofloral characteristics (actually, adjustment of the isoflorum tap gain) using the ror method (one of the two equalization methods) is performed using the modulation period (T
sec) intervals.

This double sample equalizer has been proven to equalize any timing phase error. Note that this double equalizer is not limited to this, but any equalization means that absorbs phase errors can be used.By using the above-mentioned equalization method, the phase error of the timing error shall be absorbed by the equalizer, and the remaining The timing frequency error can be realized without using a complicated PLL circuit by simply providing the counter, comparator, and counter overflow detection circuit shown in this embodiment.

Accordingly, according to this embodiment, timing errors can be eliminated with a very simple configuration.

In this embodiment, the structure shown in FIG. 1 is used as a means for correcting frequency errors, but it goes without saying that other structures may be used as long as the frequency errors can be corrected.

<Effects of the Invention> As explained above, according to the present invention, it is possible to provide a highly accurate receiving device with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a timing control section according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the blocks shown in FIG. 1, and FIG. FIG. 4 is a schematic diagram of a modem according to an embodiment of the present invention. 172.173...Counter 174...Counter value comparator 181...Overflow detector 185...Differentiator 186...Difference integrator

Claims (3)

[Claims] (1) Equalizing means for absorbing phase errors of demodulated data; means for extracting a timing signal from the demodulated data; and determining the timing signal extracted by the means and supplying it to the equalizing means. 1. A receiving device comprising: means for correcting a frequency error of a signal. (2) The correcting means includes a reference timing signal generating means, a first means for counting the reference timing signal generated by the means, and a second means for counting the timing signal extracted by the extracting means. The receiving device according to claim 1, further comprising means for correcting a frequency error of the signal supplied to the equalizing means according to the difference between the count values of the first and second means. . (3) The receiving device according to any one of claims 1 to 2, wherein the equalizing means is a double sample equalizing means.