Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filedfiledCritical
Priority to JP90388UpriorityCriticalpatent/JPH01107154U/ja
Publication of JPH01107154UpublicationCriticalpatent/JPH01107154U/ja
238000004806packaging method and processMethods0.000claims1
238000010586diagramMethods0.000description2
Classifications
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
H01L2224/42—Wire connectors; Manufacturing methods related thereto
H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
H01L2224/4805—Shape
H01L2224/4809—Loop shape
H01L2224/48091—Arched
Landscapes
Testing Of Individual Semiconductor Devices
(AREA)
Testing Or Measuring Of Semiconductors Or The Like
(AREA)
