JPH01106614A - Multiplier - Google Patents
MultiplierInfo
- Publication number
- JPH01106614A JPH01106614A JP62265641A JP26564187A JPH01106614A JP H01106614 A JPH01106614 A JP H01106614A JP 62265641 A JP62265641 A JP 62265641A JP 26564187 A JP26564187 A JP 26564187A JP H01106614 A JPH01106614 A JP H01106614A
- Authority
- JP
- Japan
- Prior art keywords
- component
- real
- multiplexer
- imaginary
- phase shifters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000003044 adaptive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- RDYMFSUJUZBWLH-UHFFFAOYSA-N endosulfan Chemical compound C12COS(=O)OCC2C2(Cl)C(Cl)=C(Cl)C1(Cl)C2(Cl)Cl RDYMFSUJUZBWLH-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Complex Calculations (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Radio Transmission System (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は見通し外通信方式等の中に用いられる乗算器に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplier used in non-line-of-sight communication systems and the like.
見通し外通信方式では、グイバシティの最大比合成、適
応整合濾波器(Adaptive MatchedFi
lter)及び判定帰還型等化器(Deci−sion
Feedback Egualiger)が採用されて
おり、その中に乗算器が用いらhている。In non-line-of-sight communication systems, maximum ratio combining of Guivasity and adaptive matched filters (Adaptive Matched Filter) are used.
alter) and decision feedback equalizer (Deci-sion
Feedback Evaluator) is adopted, and a multiplier is used in it.
、第2図は、この種の従来の乗算器のプルツク図である
。高周波信号入力ボート9からの入力信号はπ/2分波
器1でπ/2の差を有するリアル成分及びイマジナリ成
分に分けられ、それぞれO−πリニア位相器2及び3に
与えらhる。一方ベースバンド信号のリアル成分及びイ
マジナリ成分の信号もそhぞれリアルボート11及びイ
マジナリボート12からインターフェース回路7及び8
(電圧シフト等を行う)を介してO−πリニア位相器2
及び3に与え、られる。〇−πリニア位相器2及び3そ
れぞれに与えられた上述の2人力は乗算されて、それぞ
れ減衰器4及び5に送られる。, FIG. 2 is a pull diagram of a conventional multiplier of this type. The input signal from the high-frequency signal input port 9 is separated into a real component and an imaginary component having a difference of π/2 by a π/2 splitter 1, and is applied to O-π linear phase shifters 2 and 3, respectively. On the other hand, the signals of the real component and imaginary component of the baseband signal are also transmitted from the real port 11 and the imaginary port 12 to the interface circuits 7 and 8, respectively.
(performs voltage shift, etc.) through O-π linear phaser 2
and 3. The above-mentioned two forces applied to the 0-π linear phase shifters 2 and 3 are multiplied and sent to the attenuators 4 and 5, respectively.
0−πリニア位相器2及び3は、ベースバンド信号の振
幅に対し出力レベルがリニアに変化し、ベースバンド信
号の極性に応じ出力位相がO−πの位相変化をする信号
を出力するものであり、例えばリング変調器等で構成で
きる減衰器4及び5では、リアル成分とイマジナリ成分
経路間のレベル差を無くすように入力信号を減衰させて
合波器6に与える。合波器6に与えられた乗算された等
レベルのリアル成分及びイマジナリ成分は合波され信号
出力ポート10から出力される。The 0-π linear phase shifters 2 and 3 output a signal whose output level changes linearly with respect to the amplitude of the baseband signal, and whose output phase changes by O-π according to the polarity of the baseband signal. For example, the attenuators 4 and 5, which can be configured with a ring modulator or the like, attenuate the input signal so as to eliminate the level difference between the real component and imaginary component paths, and provide it to the multiplexer 6. The multiplied equal-level real components and imaginary components applied to the multiplexer 6 are multiplexed and output from the signal output port 10.
上述の従来の乗算器では、乗算された後の高周波信号路
に減衰器が挿入されレベル調整が行なわれているので、
調整がむずかしく、また回路も複雑になっている。In the conventional multiplier described above, an attenuator is inserted in the high frequency signal path after multiplication to adjust the level.
Adjustment is difficult and the circuit is complicated.
本発明の目的は、レベル調整が容易で回路構成が簡単な
乗算器を提供することにある。An object of the present invention is to provide a multiplier with easy level adjustment and a simple circuit configuration.
上述の目的を達成するために、本発明によれば高周波信
号を互いにπ/2の位相差を有する(または同相の2信
号に分岐する)分波器と、この分波器の分岐されたそれ
ぞれの出力とベースバンド信号のリアル成分及びイマジ
ナリ成分とをそれぞれ乗算する第1及び第2の位相器と
、この第1及び第2の位相器のそれぞれの出力を同相で
(またはπ/2の位相差を与えて)合波する合波器とを
備えた乗算器において、ベースバンド信号のリアル成分
及びイマジナリ成分の少なくとも一方の利得を可変する
手段を含むことを特徴とする乗算器が得られる。In order to achieve the above-mentioned object, the present invention provides a branching filter that branches high-frequency signals into two signals having a phase difference of π/2 (or the same phase), and each branched signal of the branching filter. first and second phase shifters that multiply the output of the baseband signal by the real component and the imaginary component of the baseband signal, respectively; In the multiplier equipped with a multiplexer that performs multiplexing (by giving a phase difference), there is obtained a multiplier characterized in that it includes means for varying the gain of at least one of the real component and the imaginary component of the baseband signal.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の実施例のブロック図である。従来例と
同様、π/2分波器1でリアル成分とイマジナリ成分に
分けられた高周波信号はそれぞれ、〇−πリニア位相器
2及び3に与えられる。一方、リアルボート11及びイ
マジナリボート12からのベースバンド信号のリアル成
分及びイマジナリ成分はそれぞれ、インターフェース回
路7及び8を通った後、可変増幅器20及び30で増幅
され、O−πリニア位相器2及び3に与えられる。o
−πリニア位相器2及び3は与えられた上述の2人力を
乗算し、乗算結果を合波器6に供給する。合波器6は2
人力を合波し出力ポート10に合波信号を出力する。FIG. 1 is a block diagram of an embodiment of the invention. As in the conventional example, the high frequency signals separated into real components and imaginary components by the π/2 splitter 1 are applied to 0-π linear phase shifters 2 and 3, respectively. On the other hand, the real component and imaginary component of the baseband signals from the real port 11 and the imaginary port 12 pass through interface circuits 7 and 8, respectively, and are amplified by variable amplifiers 20 and 30, and are amplified by O-π linear phase shifter 2 and given to 3. o
The -π linear phase shifters 2 and 3 multiply the above-mentioned two-power inputs and supply the multiplication results to the multiplexer 6. The multiplexer 6 is 2
The human power is combined and a combined signal is output to the output port 10.
ここで、可変増幅器20及び30の利得は、信号出力ポ
ート10から所望の波形が得られるように設定する。Here, the gains of the variable amplifiers 20 and 30 are set so that a desired waveform can be obtained from the signal output port 10.
なお、π/2分波器1及び合波器6の代わりに、それぞ
れ同相で2分岐する分波器及びπ/2の位相差を与えて
合波する合波器を用いてもよい。Note that instead of the π/2 demultiplexer 1 and the multiplexer 6, a demultiplexer that branches into two signals in the same phase and a multiplexer that multiplexes the signals with a phase difference of π/2 may be used.
以上説明したように本発明によれば、高周波信号経路の
レベル調整をベースバンド信号のレベル調整によって行
っているので調整が容易になり、また回路構成も簡単に
なる。As explained above, according to the present invention, the level adjustment of the high frequency signal path is performed by the level adjustment of the baseband signal, which facilitates the adjustment and also simplifies the circuit configuration.
第1図は本発明の一実施例を示すブロック図、第2図は
従来例を示すブロック図である。
1・・・・・・π/2分波器、2,3・・・・・・Q−
πリニア位相器、4,5・・・・・・減衰器、6・・・
・・・合波器、7゜8・・・・・・インターフェース回
路、9・・・・・・高周波信号入力ポート、10・・・
・・・信号出力ポート、20゜30・・・・・・可変増
幅器。
代理人 弁理士 内 原 晋FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1...π/2 splitter, 2, 3...Q-
π linear phase shifter, 4, 5... Attenuator, 6...
...Multiplexer, 7゜8...Interface circuit, 9...High frequency signal input port, 10...
...Signal output port, 20°30...Variable amplifier. Agent Patent Attorney Susumu Uchihara
Claims (1)
同相の2信号に分岐する)分波器と、この分波器の分岐
されたそれぞれの出力とベースバンド信号のリアル成分
及びイマジナリ成分とをそれぞれ乗算する第1及び第2
の位相器と、この第1及び第2の位相器のそれぞれの出
力を同相で、(またはπ/2の位相差を与えて)合波す
る合波器とを備えた乗算器において、前記ベースバンド
信号のリアル成分及びイマジナリ成分の少なくとも一方
の利得を可変する手段を含むことを特徴とする乗算器。A splitter that splits high-frequency signals into two signals having a phase difference of π/2 (or the same phase), and the split outputs of this splitter and the real and imaginary components of the baseband signal. the first and second to multiply respectively
and a multiplexer that combines the outputs of the first and second phase shifters in the same phase (or with a phase difference of π/2), in which the base A multiplier comprising means for varying the gain of at least one of a real component and an imaginary component of a band signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62265641A JP2716130B2 (en) | 1987-10-20 | 1987-10-20 | Multiplier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62265641A JP2716130B2 (en) | 1987-10-20 | 1987-10-20 | Multiplier |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01106614A true JPH01106614A (en) | 1989-04-24 |
JP2716130B2 JP2716130B2 (en) | 1998-02-18 |
Family
ID=17419953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62265641A Expired - Lifetime JP2716130B2 (en) | 1987-10-20 | 1987-10-20 | Multiplier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2716130B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10219908A1 (en) * | 2002-05-03 | 2003-11-27 | Epcos Ag | Electrode and a method for its production |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773422B1 (en) * | 1998-01-06 | 2000-02-04 | Alsthom Cge Alcatel | DEVICE FOR MONITORING THE AMPLITUDE AND PHASE OF A RADIO FREQUENCY SIGNAL |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57154962A (en) * | 1981-03-19 | 1982-09-24 | Nec Corp | Digital multiphase and multivalue modulator |
JPS61163730A (en) * | 1985-01-14 | 1986-07-24 | Nec Corp | Transmitter |
-
1987
- 1987-10-20 JP JP62265641A patent/JP2716130B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57154962A (en) * | 1981-03-19 | 1982-09-24 | Nec Corp | Digital multiphase and multivalue modulator |
JPS61163730A (en) * | 1985-01-14 | 1986-07-24 | Nec Corp | Transmitter |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10219908A1 (en) * | 2002-05-03 | 2003-11-27 | Epcos Ag | Electrode and a method for its production |
US7139162B2 (en) | 2002-05-03 | 2006-11-21 | Epcos Ag | Electrode and method for the production thereof |
Also Published As
Publication number | Publication date |
---|---|
JP2716130B2 (en) | 1998-02-18 |
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