JPH01106366A - System and device for recording and reproducing digital information by enciphering and decoding - Google Patents

Abstract

PURPOSE:To ensure liquidation of charge in the reproduction of a writing source and to preclude the illegal use of the writing source by applying a countermeasure for an error to audio, video, or software information, and recording the information after enciphering the information. CONSTITUTION:Digital raw data are made into input data 1, an enciphering processing 2 and an error countermeasure 3, such as an interleaving, are applied to the input data 1, and the input data 1 are inputted to a recording circuit system 4. Or, the digital input data 1 is inputted to the recording circuit system 4 after the procedure itself of the error countermeasure such as the interleaving is made into the procedure of the enciphering processing, and a combined-use processing 5 is applied to the input data 1. Further, in order to reproduced the data, for example, an error processing 7 and a cipher decoding processing 8 are applied to digital input data 6, which are enciphered and worked by the error countermeasure, and the input data 6 are inputted to a reproducing downstream circuit system 9. Moreover, for the digital input data 6, to which an error countermeasure '1' is executed first then a processing is executed in which the procedure of an error countermeasure '2' such as the interleaving is combined with the procedure of the enciphering processing, a processing 10 is executed, in which the error processing '2' is combined with the cipher decoding, and further, an error processing '1' 11 is applied, and the input data 6 is inputted to the reproducing downstream circuit system 9.

Description

[Detailed Description of the Invention] [Object of the Invention] The present invention relates to a method, apparatus, and system for encrypting and recording information such as audio, video, or software information, as well as combination information thereof, and decrypting and reproducing information. It is. In particular, recordings that are characterized by the encryption and decoding of digital audio and digital video, the payment of fees for the reproduction of copyrighted material sources, the elimination of unauthorized use of copyrighted material sources, or the optional introduction of user-specific encryption systems. The present invention relates to a reproduction method, device, and system.

A first object of the present invention is to realize a method and apparatus configuration for recording digital information such as digital audio and video by encrypting and reproducing by decoding.

The second object of the present invention is to realize not only a method for encrypting and decoding all data to be recorded and reproduced, but also a method for encrypting and decoding only a part of the data, and a method for recording and reproducing the same. It is in.

Another object of the present invention is to realize the configuration of a playback device using dual port RAM, PCMLSI, PU, etc. in order to implement the methods for each of the above objects.

A further object of the present invention is to realize an address instruction circuit, an address bus output generation circuit, and a PU necessary for the above device.

[Description of the invention]

1. Recording method using encryption In conventional digital audio and digital video, the input raw data was not encrypted.

In the recording method according to the present invention, as shown in FIG. 1 [a], raw data of a digital signal is converted into digital input data (1).
After encrypting the data (2), it is subjected to error countermeasures (3) such as interleaving, and its output is input to the recording circuit system (4). Or, as shown in Figure 1 [b], the digital input data (1) is subjected to error countermeasure procedures such as interleaving, which are also used as encryption processing procedures (5), and then the recording circuit system (4) Enter. At this time, in (1), the error countermeasure processing and the security processing in the previous stage may have already been performed.

2. For example, in a conventional CD audio playback system, the raw data read from the source is subjected to jitter removal, deinterleaving, and error correction, and is then corrected by interpolation, passed through a digital filter, and then input to the DA converter. I am getting an analog signal. In the present invention, the following circuit starting from this interpolation correction is defined as a downstream circuit system for reproduction.

In the reproduction method of the present invention, for example, as shown in FIG. 1 [c], the digital input data (6) that has been encrypted and subjected to error countermeasure processing is subjected to error processing (7), and then the encrypted data is decrypted (7). 8) and then input to the downstream circuit system for reproduction (9), or as shown in Figure 1 [d], after error countermeasure 1 has been implemented, the procedure for error countermeasure 2 such as interleaving is encrypted. The digital input data (6) that has been processed in conjunction with the processing procedure is subjected to a process (10) that combines error processing 2 and decryption, and then error processing 1 (
11) and then input to the downstream circuit system (9) for reproduction.

Note that the order of (7) and (8) can also be changed according to the processing order of (6). In addition, the technology of each element in the figure, such as the downstream circuit system for reproduction (9), is known, and FIG. It consists of a combination of converters (15).

Hereinafter, the encryption procedure will be indicated by W, and the decryption procedure will be indicated by W-1.

3. Data to be encrypted and decrypted In conventional DAT, one data for the left and right channels is
By 8-10 conversion, one symbol is treated as 10 channel bits and is treated in units of two symbols, but it is desirable to encrypt in units of multiples of this symbol.

Furthermore, in the present invention, in addition to processing all of the data to be recorded and reproduced as a subject of incoming decoding, it is also possible to encrypt and decrypt only a part of the data.

If only a portion of the data is encrypted, what data was targeted?
In other words, it is necessary to let the decryption device know which data has been encrypted. One of the methods is
In FIG. 2 (a), a mark consisting of a plurality of bits is added to a specific portion of the digital data, such as the beginning or MSB of the data. The reproducing device decodes only the data for which this mark is detected, as shown in FIG. 2 (b). Another method is to load several pieces of data in one block for DAT or one frame for CD, for example.
Among these, as shown in FIG. 2 [C], only data located at a predetermined position is encrypted.

The predetermined location information itself can also be recorded on a predetermined portion of the medium.

As shown in FIG. 2 (d), the playback device decodes only data at a predetermined position within a block or frame. As shown in [e], information K(
29) is read from memory (31) and registers, but
Alternatively, the information may be read from the recording medium (30) or input from outside (32), such as by key input. At this time, the position information (33) read out from the medium itself must be encrypted, and the decryption password must be entered using a key, or it must be paired with the parameter R (34) stored in memory in advance. It is also possible to obtain the decoding procedure (35) using the following steps.

These configurations allow the device to obtain data to be decoded during playback.

4. Configuration of Apparatus Next, in order to carry out the method of the present invention described above, the present invention uses an apparatus having the configuration shown as an example in FIGS. 7 and 8. Now, in the digital audio playback device shown in Fig. 7, the PCMLSI (100) stores the digital raw data (106) read from the DAT tape or CD into the instep area (40) of the dual port RAM (hereinafter referred to as DPRAM) (40). 41), and this is stored in the error detection and correction unit (134).
After the data is read and error correction is performed, the DPRAM is loaded again.
The data is stored in the B area (41b). On the other hand, the processing unit (hereinafter referred to as PU) (101) takes out this data from the B area (41b), performs the decryption process using W-1, and then rewrites the data to the C area (41c) of the DPRAM.
), the PCMLSI (100) again takes out this data from the C area (41c) of the DPRAM, and inputs it to the downstream circuit system (9) for regeneration, which consists of an interpolator, digital Hilter, DA converter, etc. .

Thus, PCMLSI (100) performs the following three types of work while performing regeneration.

First, the digital raw data read from the source is
Store in the upper area of PRAM.

The second is to perform error correction on the raw data read from Area A and store it in Area B.

The third step is to take out the decoded data from the C area and send it to the downstream circuit system for reproduction.

On the other hand, while the PU (101) is performing playback, the PCMLSI
(100) stores the error corrected data stored in the B area (4).
1b), performs decoding processing, and stores the result in area C (41c). Therefore, if the unit period during which playback is executed is, for example, one set of DAT blocks, in order to have PCMLSI (100) and PU (101) execute the above operations within the same block period, ), and the writing and reading to area C (41c) are repeated. In order to avoid this, the present invention is shown in Figure 3 (
As shown in a), the Otsu area is divided into the Otsu 1 area (42) and the Otsu 2 area (43), and the C area is also divided into the C area 1 (43).
4) and C2 area (45), and within the same block period, as shown in α in Figure 3 [a], PCMLS
I performs error correction processing (46) and writes the error-corrected data into one area of the Otsu area, for example, the Otsu 1 area (42), while the PU writes the error-corrected data into an area of the Otsu area, in this figure, the Otsu 2 area (43). ), PCMLSI reads the data written in it within the previous block period, and within the same block period, after the PU decodes it at W-1 (47), The decoded data is written into one area of the area, here the C2 area (45). On the other hand, the PCMLSI reads the data (48) written by the PU in the previous block period from another area of the C region, here the C1 area (44), and the downstream circuit for playback Configure it to send to. Then, in the next block period,
As shown in β in Figure 3 [a], if the aforementioned areas are reversed and executed, and then α and β are executed alternately so as to return to α again in the next block, the playback will be smooth. Continuous, with no interruptions or stagnation.

This area change and associated address change will be performed on P
CMLSI and PU can also do it with software,
Since software processing requires time, the present invention has developed an address destination and an address server that meet this purpose, and implemented them in hardware to save time.

This eliminates the need for both the PCMLSI and the PU to be concerned with the designation of each area within the B area and the designation of each area within the C area, which not only saves time but also facilitates control.

Furthermore, by using a dual-port RAM of existing technology as the RAM, the PCMLSI and PU can access different memory cells on the RAM independently and simultaneously even in the same or repeated machine cycles. By apparently doubling the number of limited steps in a block, more complex decoding processing can be applied. In addition to the above-mentioned tasks that have strict time constraints, which are processed in real time by PCMLSI and PU during playback, there are also tasks that have relatively loose time constraints, such as W&W-1 registration and updates. . These will be referred to as A-class jobs and B-class jobs, respectively.

An example of area division and addressing of the dual port RAM is shown in FIG. 3 [6].

If the memory area of the DPRAM, whose address can be expressed by L bits, is divided in half into the A and non-A, the 1 and 0 of the Lth bit can be associated with the A and the non-A. For example, 256
Byte memory area is 128 bytes each (41
) and non-A (41a), the address data (4
9) of the eighth bit (hereinafter referred to as bg; the same applies to other bits), 1 can be made to correspond to the instep area (41), and 0 can be made to correspond to the non-instep area 41a, respectively.

Furthermore, the non-A area (41a) is
By dividing the area in half into both areas of c), an area of 64 bytes each will be created, and the 7th bit of address data (49) corresponds to C (41c) to 1 of 7 and Otsu (41b) to 0, respectively. I can do it.

Furthermore, for Otsu and Hei, these are divided in half and Otsu 1 (42), Otsu 2 (43) and Hei 1 (44) each have 32 bytes.
If divided into 2 (45) areas, b691 area 1
and 0 can be made to correspond to area 2, respectively. 1 and 2 may be reversely associated.

FIG. 4 shows an example of timing design for a DAT recorder according to the present invention. Let's assume that the system clock of the DAT system we are currently focusing on is 2.8224 Mc/s,
The PCMLSI outputs one piece of sound signal data of the right or left channel to the downstream circuit system for reproduction during a time period corresponding to 32 clocks, and one block is made up of five pairs of left and right sound signal data. For example, the number of clocks in one block is 320, and the time of one block is about 113 microseconds. In the system of the present invention, the clock of 320
In MLSI, the three types of work mentioned above are distributed and used, while in PU, the same 320 clocks are used for decryption processing of encrypted data.

In the present invention, the DPRAM is divided into areas A, B, and C, and each C is divided into two areas, and the PCMLSI and PU never access the same memory cell repeatedly within a certain block time period. Since it is configured, PCM
Both LSI and PU coordinate with the work of the other party,
There is no need to set up a waiting time. That is, for example, the PU only needs to use 320 clocks until the end of this block to complete storing the decoded data from C1 to C2 area. These 5 sets of 10 sound signal data stored are sent to the downstream circuit system for reproduction by the PCMLSI in the next block. The above block configuration is only an example, and various block configurations may be used, such as 4 sets of 8 blocks, 8 sets of 16 blocks, etc.
You can take pieces etc.

Next, the address destination will be explained.

The address destination is a circuit for automatically performing the above-mentioned area exchange for each block, and has the configuration shown in the example of FIG. 5(a). In the example shown in this figure, the address data has an 8-bit configuration.

The address destination (50) is composed of a flip-flop (hereinafter referred to as FF) (51), an address server (52) on the PCMLSI side, an address server (53) on the PU side, and a DPRAM (40). At the time corresponding to the start of the block, the generated signal (55) is input to the FF (51), so that the signal (55) is automatically output to the FF outputs Q (56) and Q (
57) polarity (“H” and “L” or 1 and 0) is reversed. That is, each time the block changes, Q changes from 1 to 0 and from 0 to 1, while Q changes from 0 to 1 and from 1 to 0.

When both Q(56) and Q(57) have a value of 1, DPRA
For example, if the value is 0, areas Otsu 1 or C 1 of M(40) are made to correspond to areas Otsu 2 or C 2. Now Q (56)
Then, the address data (58) that outputs PCMLSI (this includes access to the A area of DPRAM (40)) is input to the address server (52) on the PCMLSI side, and the output is input to the PCMLSI of DPRAM (40). output to the side address bus (59). On the other hand, Q(57) and P
The address data (60) issued by U (this does not include access to area A) is input to the address server (53) on the PU side, and the output is sent to P of DPRAM (40).
Output to the U side address bus (61). The signal (55) is created by the frequency divider shown in Fig. 7, and its clock 0 is XT
AL type is preferable.

As an example, the 256-byte DPR shown in Figure 3 [b]
When addressing AM with 8 bits, A area 12
8B, Otsu 1, Otsu, Hei 1 and Hei 2 each consist of 32B, and b8 of the address data corresponds to A with 1 and non-A area with 0, respectively. Also, b7 is 0 for Otsu area, 1 for C area, and b6 is 0 for Otsu1 or C1, b
6 and 1 correspond to Otsu 2 and Chou 2, respectively. In this way, the memory cells in Otsu 1 and Otsu, Hei 1 and Hei 2 can be fixed between b5 and b1. Therefore, PCMLSI sets b8 to 1 when extracting the instep area, that is, raw data.
Then, by writing to B, b8 = 0, b7 = 0, reading from C, b8 = 0, b7 = 1, the memory cell to be accessed is identified from b5 to b1, and this signal is (58) and sends it to the address server on the PCMLSI side.

Here, when b8=0, b6 may be arbitrary. On the other hand, P
U sets b7 to 0 when reading from B, sets b7 to 1 when writing to C, identifies the address of the memory cell to be accessed with b1 in b5, and sends P as a signal (60).
Send to Uβ address server. At this time, the value of b6 may be arbitrary.

The address server (52) on the PCMLSI side is the PCM
If the address data (58) issued by the LSI is received and i5b8 is 1, that is, it indicates the oscillation region, all bits are sent as they are to the DPRAM address bus (58) on the PCMLSI side.
9), if b8 is 0, that is, indicates a non-instep region, then each bit of b8, b7, and b5 to b1 is adopted as is, while the 6th bit b6 is set to Q from FF (51). Adopt the values corresponding to the output (56) and convert these to P
It is placed on the DPRAM address bus (59) on the CMLSI side. Figure 5 [b] shows the bit configuration, where (a) is access to area A, (2) is written into Otsu 1, (3) is written into Otsu 2, (4) is read from C 1, ( 5) shows reading from C2.

The address server (53) on the PU side is the b7 issued by the PU.
Receive one address data (60) of b1 from , use them as they are except for b6, and use the value corresponding to Q output (57) from FF (51) for b6. DPRAM address bus (61
). At this time, since the PU does not access the A region, the eighth terminal of the PU side address of the DPRAM is fixed to 0. In Figure 5 [b], (6) is read out from Otsu 2, (7) is read out from Otsu 1, (8) is written into C2, and (9) is written into C1.

Next, address servers will be explained.

An address server is a system that processes address data input from PCMLSI or PU by using Q or Q as an input value, which has the property of inverting the output value for each block of input data and retaining that value until the next block. This is an address bus output generation circuit that generates an address bus output to the DPRAM.

The content of the processing is to output the bits that do not need to be changed as is, regardless of the block, for the address data that was input within the period corresponding to that block, and to output the bits that do not need to be changed as is, for the bits whose value needs to be changed for each block. It is automatically generated from the values of and Q, and output to the address bus in place of this.

An example of an address server is shown in FIG.

Figure 6 [a] shows the configuration of Figure 5 [a] and Figure 3 [b].
] In the configuration example of the address server (52) on the PCMLSI side, which corresponds to the DRAM memory 6 area, gate 2 (6
5) from the first system to the fifth system (66) is PCML.
Connect the lower 5 bits (67) of address data A (58) input from SI, and connect (68) F in Figure 5 to the 6th system.
Input signal Q (56) from F (51), input signal Q (56) from 7th system (69
) and the eighth system (70) are connected to b7 (71) and b8 (72) of A (58), respectively, and the gate 2 outputs (73) of these eight systems are connected to the DPRAM address bus (59) on the PCMLSI side. ). Gate 2 (65) is controlled to open or close according to the value of (75) by connecting the output (75) of logic circuit 2 (74) to select terminal G (76) of gate 2.

In logic circuit 1 (77), b8 (72) of A (58) is 1
When , the output (78) is 1, and the logic circuit 2 (74) is b
When 8 (72) is 0, the output (75) is set to 1. now,
b8 (72) of A (58) input is 0, that is, non-instep area (
41a) is selected, b7 (71) is 0, that is, area B (4
1b) is selected, the Q(5) input to the 6th system (68)
Depending on the value of 6), 21 (42) or Otsu 2 (of Otsu area)
43) can be determined. At this time, b6(7) of A(58)
9) can be read. For example, if 0 is input as the value of Q (56), one memory cell in Otsu 2 (43) will be determined by the lower 5 bits (67) of A (58). Here, if the value of Q (56) changes to 1, one memory cell in Otsu 1 (42) is determined, replacing Otsu 2 (43). Thus, due to the reversal of the value of Q (56), Otsu 1 (42)
and Otsu 2 (43) can be easily selected, so A (58)
), that is, the PCMLSI, does not need to be aware of whether it is Otsu 1 or Otsu 2.

If b7 (71) is set to 1, it becomes area C (41c),
The selection and switching of area 1 and area 2, that is, area 1 (44) and area 2 (45), is the same as described in area B above.
This can be done automatically depending on the value of 6). With the above, gate 1
(80) remains non-conducting. Now, if A (58)
b8 (72) is 1, that is, if the instep region (41) is selected, the output (78) is 1, and gate 1 (80)
As a result of being input to the select terminal G (81) of the gate 1
(80) becomes conductive, while gate 2 (65) is closed. In this way, the 8 bits of A (58) directly pass through gate 1 (80) and appear on the DPRAM address bus (59), and thus the memory cells in the instep area are connected from b7 inner diameter to b1.
selected by the bit of Therefore, PCMLSI
It becomes possible to create and execute programs without considering area exchange at all.

Since the operation is as described above, the DAT playback data before error correction is now stored in the A area (41), and the DAT playback data before error correction is stored in the A area (41b).
) contains the error-corrected data in area A, and area C (41c) contains the data in area B with W.
If the configuration is such that data subjected to -1 processing is stored, area exchange for each block is automatically performed, and data reproduction can be continued smoothly.

In addition, when a large size is required for the instep region, the instep can be divided so that the instep is large instead of dividing the instep and non-instep equally to increase the memory. The method according to the present invention can be carried out even if the division into B and C is not equal. For example, as shown in Figure 6 [b] and [c], the size of B to C is 3 to 1.
Let's explain the case.

The DPRAM (82), which has a total of 256 bytes, is divided into 16 groups of 16 bytes, and Otsu 1 (83) and Otsu 2 (84) each have 3 groups of 48 bytes, Hei 1 (85) and Hei 2 (86).
When each set is composed of 16 bytes, the address is represented by 8 bits, and the b7b6b5 correspond to each other as shown in [b]. B8 is 1 for the instep and 0 for the non-instep. b6 and b
Focusing on 7, when both are 1, it is the C area (89), and when both are not 1, it is the B area (88), and furthermore, the address display of C2 (86) is b5 of that of C1 (85).
Furthermore, the address display of Otsu No. 2 (84) is the addition of 1 to b5 and b6 of Otsu No. 1 (83) (the rising digit shall be placed in b7), so the above is as follows. An example in which an address server is created on the PU side with a focus on this is shown in FIG. 6 [c]. PU will send all instructions regarding Party B to Party B 1's address, and all orders regarding Party C to Party 1's address.
If you decide to display the address of b1b2b among the address data (60) input from PU,
3b4 and b8 can be output to DPRAM as is. b
For 5b6b7, if the Q output from the FF (57) is 1, Otsu1 (83) is C1 (85), so these 3 bits are outputted to the DPRAM by opening the gate (90). When Q=0, the logic gate 3 (93) determines whether it is C2 or Otsu2, and if C2, it is output to the DPRAM via the adder (94), and if Otsu2, it is output to the DPRAM via the gate (95).

FIGS. 7 and 8 show configuration examples of the device according to the present invention.
An example of application to a playback device is shown below. Figure 7 shows an address destination, or FF (51), two address servers (52) and (53), and a DPRAM (40) in PCM.
An example in which (51) and (52) are provided outside of LSI (100) and PU (101) is shown in Figure 8 in (100).
An example in which (53) is incorporated into the middle part of (101) is shown. 8th
In the figure, the Q output (57) in PCMLSI is taken out,
Input to address server (53) in PU. The timing corresponding to the start of the block is clock φ(102
) and notify the PU by interrupt (104), but there are two types: one by NMI input (103) as shown in Fig. 7, and the other by INT3 input (105) as shown in Fig. 8. street is possible. NMI has a fast response,
Since the number of steps can be saved, it is suitable for high-speed processing such as the configuration of the present invention and when there is no need to return before an interrupt. However, since masking cannot be performed, when updating W or W-1, In order to avoid work relay by NMI, PU
The NMI input (103) to (101) must be cut off.

Therefore, as shown in Figure 7, the FF (111) is connected to the PU.
It is controlled by the O port output (113), and its FF output makes the TG (114) non-conductive for a necessary period to cut off the block interrupt (104), thereby cutting off the NMI input.

As a result, the update work of W and W-1 can proceed without interruption, and at the same time, the Q output (115) of FF (111) can be changed to DPR.
By also inputting the signal to the AM reset terminal R (116), you can prevent the old data remaining in C1 (44) and C2 (45) from continuing to flow to the downstream circuit system (9) for reproduction and generating noise. It can be prevented.

In the case of the INT interrupt shown in Figure 8, INT1 (17)
When entering the W8W-1 registration update mode, first enter the IN
By masking T3 (105), block interrupt (
104) can be killed. Also, INT1 interrupt (117)
When there is, the I/O port output (118) is output and D
If you input it to the PRAM reset terminal R (116), the seventh
As in the case shown in the figure, in addition to preventing noise generation, the analog switch (1
20), or via the halt terminal (121) provided on the PCMLSI, each internal element, ie, FF (51), address server (52), interpolator (122), digital filter ( 123),
Noise generation can also be prevented by temporarily stopping the selector (124). After entering the registration update mode of W8W-1 using the INT1 interrupt, enter the parameter Pj (126) from the keyboard (125),
Pj is input to generation routine 2 (127) to generate W and W-1 and stored in RAM (128). At this time, the fee can be settled by communicating with an external electronic ticket or the like via the terminal H (129).

In addition, to enter W&W-1 registration update mode, W&W-1
INT1 (117) with the registration update switch (130) of 1
) can be configured to be entered automatically in response to input data from PCMLSI.

The gist of the device according to the present invention is that in order to accomplish many jobs with a limited number of states, the previously defined A class job is shared between PCMLSI and PU, and DPRAM is used to increase the apparent number of states. , and when dividing the area and accessing it alternately for continuous processing, address dispatching is performed by hardware to save switching loss time. Therefore, the B class job, that is, the W&W-1 registration update, can be executed on the PCMLSI side in addition to being executed on the PU as shown in Fig. 7 or 8, or by incorporating another set of processing mechanisms. It is also possible. However, W and W-1 generated by registration update,
After all, since it is used by the PU, it must be placed inside the PU or easily accessible during execution, which also poses a security problem. Therefore, the effects of the present invention are maximized when the configuration is such that generation, registration, access, and execution of W&W-1 are executed consistently within the PU.

In addition, for more complex data that requires decoding processing with a large number of steps, for example, multiple microprocessors (indicated by μP) and address destinations are serially connected to decode data within a block period determined by division. The process can be completed. In this case, for example, it is preferable to input the outputs Q and Q from the FF of the first address destination to the subsequent ones.

Thus, for example, when data of a certain block is serially processed by M μPs and M-1 address destinations, the processed data flows out continuously from the last μP. It is ideal for structures where the processing procedure is unidirectional and has no loops, branches, or feedback, such as digital audio decoding. Further, W-1 is configured by a combination of known techniques such as bit exchange and bit inversion between a plurality of pieces of data. For example, the total number of cases due to 80-digit bit exchange and bit reversal is (■80Cn) x 80! becomes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the order of the recording and reproducing method of the present invention, [a] and [b] are a recording method using encryption,
[c] and [d] are playback methods by decryption, [a] is a configuration example of a downstream circuit system for conventional playback. Figure 2 is a flow diagram for each type of data to be encrypted and decrypted using the method of the present invention. in,
[a] is encryption of a specific part target, [b] is decryption of a specific part target, [c] is encryption of a data target at a predetermined position,
[d] is the decoding of the data object at the specified position, [e] is the method for obtaining the specified position. Figure 3 shows an example of area division of dual port RAM, and [a] is the flow of area division and processing. , [b] is an example of area division and addressing. FIG. 4 is a playback timing diagram of a DAT recorder.
Example of the bit configuration of the signal output to the AM address bus Figure 6 [a]
] is an example of a configuration diagram of a PCMLSI side address server according to the present invention, [b] is an example of area division of dual port RAM,
[c] shows an example of the configuration of the PU side address server. FIGS. 7 and 8 show examples of the configuration of the reproducing apparatus of the present invention. 1... Digital input data, 2... Encryption processing, 3... Error countermeasures, 4... Recording circuit system, 5... Combined processing of encryption and error countermeasures, 6... Digital input data, 7... Error processing, 8...
Decoding processing, 9...Downstream circuit system for reproduction, 10...Combined processing for error processing 2 and decoding, 11...Error processing 1, 13...Interpolation circuit, 14...Digital filter, 15...DA converter, 20...Random target Determine data D, 21...encrypt D, 22...add n-bit mark to the beginning of D, 23...perform interleaving and record, 24...apply dittering leaving to input data, 25...error processing, 26...Presence or absence of n-bit mark, 27...Decoding, 28...Is the data at a predetermined position? , 29...Predetermined position information K
, 30... Recording medium, 31... Memo, 32... Key input, 33
...Encrypted location information on the recording medium, 34...Parameter R on the memory or key input password 35...Decryption procedure for the location information, 40...Dual port RA
M, 41...A area, 41a...Non-A area, 41b...Otsu area, 41c...Hei area, 42...Otsu 1 area, 43...Otsu 2 area, M4...Hei 1 area, 45...Hei 2 area, 46... PC
Error correction processing by MLSI, 47...W-1, 48...
Data sent to downstream playback system, 49...Bit configuration of address data, 50...Address destination;
51...Flip-flop FF, 52...PCMLSI side address server, 53...PU side address server,
55...Signal, 56...Output Q, 57...Output Q, 58...PC
Address data issued by MLSI, 59...PCMLSI side address bus, 60...Address data issued by PU side, 6
1. Address bus on PU side, 65...at gate, 66...
1st to 5th system, 67...lower 5 bits of 58, 68
...6th system, 69...7th system, 70...8th system, 71...
7th bit of 58, 72...8th bit of 58, 73...gate 2 output, 74...output of 75...74 in logic circuit,
76...Select terminal of 65, 77...Logic circuit 1, 78...
77 output, 79...6th bit of 58, 80...gate 1
, 81...80 select terminals 82...256B DPRAM, 83...Otsu 1, 84...Otsu, 85...Hei 1, 86...Hei, 87...A, 88...Otsu,
89...C, 90...Gate, 91...Logic gate 1, 92...
In the logic gate, 93...logic gate 3, 94...addition circuit, 95...gate, 100...PCMLSI, 101...PU
, 10, clock φ, 103...NMI input, 104
...Block interrupt, 105...INT3 input, 106...Raw data, 107...PCMLSI side data bus, 108
...Data bus on the PU side, 109...Frequency divider, 110...Frequency divider, 111...FF, 112...I/O port, 113...I
/O port output, 114...Trigger gate TG, 115
...Q output of 111, reset terminal R of 116...40, 1
17...INT1, 118...2/3 port output, 119...
Digital output βD, 120...Analog switch, 121
...Halt terminal, 122...Interpolator, 123...
Digital filter, 124...Selector, 125...Keyboard, 126...Parameter Pγ, 127...Generation routine T
, 128...RAM, 129...Communication terminal H with electronic ticket, 130...W&W-1 registration update switch, 131...recording mode switch, 132...INT2 input, 133...P
U's CPU U, 134...Error detection and correction device

Claims (1)

[Scope of Claims] 1. Encrypted digital audio, digital video, and digital information recording method and apparatus for creating recorded data from the output after encrypting digital input data and taking error countermeasures. Configuration 2: Encrypted digital audio, digital video, and digital information recording method and apparatus for creating recorded data from the output of digital input data processed using error countermeasure procedures such as interleaving as an encryption means. Configuration 3: error correcting encrypted digital input data;
Then, after decrypting the code, or decrypting the input data, and then performing error correction,
In addition to error countermeasure 1 and error countermeasure 2, error countermeasure 2 is also used as the encryption processing procedure. Processed digital input data is subjected to processing that combines error processing 2 and decoding, and then error processing 1
5. Method and apparatus configuration for reproducing digital audio, digital video, and digital information with decoding, which are input to the downstream circuit system for reproduction as shown in the main text. Method 6 for recording encrypted digital audio, digital video, and digital information according to claim 1 or 2, in which only part of the data is encrypted and a mark is added to the data, and the mark is added when decoding the data. Claim 3 or 4, which detects and decodes only the data that is
Method 7 for reproducing digital audio, digital video, and digital information with decryption described in Section 7, when encrypting data, only encrypting data in predetermined positions such as blocks and frames;
A method for recording encrypted digital audio, digital video, and digital information according to claim 1 or 2. 8. When decoding data, only the data at predetermined positions such as blocks and frames are decoded.
A method 9 for reproducing digital audio, digital video, and digital information with decoding according to claim 3 or 4, in which the B area of the memory is set to Area O 1 and Area O 2, and the C area is set to Area C 1 and Area C 2. Within the same block or frame period, the PCMLSI writes error-corrected data into one area of the Otsu region, for example Otsu 1, while the PU writes error-corrected data into another area of the Otsu region, in this case Otsu. From 2, the PCMLSI reads the data written in the previous block or frame period, and within the same period, the PU decodes it to one area of the C area of the memory, for example, C2. While the PCMLSI is writing in the data of the
In this case, from C1, the decoded data written by the PU in the previous block or frame period is read out, and in the next period, the above areas are reversed and executed respectively. 10. Configuration 10 of a method and apparatus for reproducing digital audio, digital video, and digital information having a configuration of repeating this, inputting a signal to a flip-flop at the start of a block or frame of input data or at a predetermined timing,
The output Q and the address data output by PCMLSI are
It is input to the address bus output generation circuit on the CMLSI side, and its output is sent to the address bus on the PCMLSI side of the dual port RAM.On the other hand, the output @Q@ and the address data output by the PU are input to the address bus output generation circuit on the PU side. and sends the output to the PU side address bus of the dual-port RAM. Configuration 11 of the address instruction circuit holds an output value for each block or frame of input data. Q or @Q@ is used as an input value, and the block For address data input within a period corresponding to a block or frame, etc., bits that do not change depending on the block or frame, etc. are output as is, and bits whose value should be changed for each block, frame, etc. are output as is. Configuration of an address bus output generation circuit that replaces the value automatically generated from @Q@ and outputs it to the address bus.