JPH01105397A - Data erasing method for storage device - Google Patents

Abstract

PURPOSE:To reduce a chip damage by externally irradiating X rays while impressing a voltage to the word line of a memory element. CONSTITUTION:An incorporated range package 8 in a chip is mounted on a voltage impressing device 11. This device 11 is constituted so as to impress the voltage to the word line of a memory cell. According to the device of such a constitution, the X rays are projected on the chip 7 incorporated in the package 8 externally of the package 8 and simultaneously, the voltage is impressed to the word line of the memory cell disposed on the memory matrix of the chip 7. As mentioned above, by impressing the voltage to the word line of the memory cell, an electron stored in a floating gate can be lost in a short time together with an effect for discharging the electron stored on the floating gate 30 by the irradiation of the X ray as a photoelectric current. Thereby, the irradiating time of the X rays to the chip 7 can be shortened to reduce the damage of the chip 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data erasing method in a storage device, particularly a non-volatile memory such as an EFROM.

[Prior art]

Erasable programmable read-only memory using MOSFET (insulated gate field effect transistor)
e Read 0nly Memory+Hereafter EPRO
M), it is well known that a window section is provided on the main surface of the ceramic package and ultraviolet rays are irradiated from this section to erase the memory, but since this ceramic package is expensive, it has not been There are some products whose packages are sealed with resin (plastic) to reduce costs.

Such products are One Time Electrically Programmable Read Only Memory (One Time Electrically Programmable Read Only Memory).
ElectrlcallyProgrammable
Read 0nly Memoryw Below OTFR
OM). For example, the product name HN482764F-3 is listed on page 290 of "Hitachi IC Data Book, September 1982 Edition" published by Hitachi, Ltd. Such storage devices are low cost, but on the other hand, data cannot be erased by ultraviolet rays. As a method of erasing such a resin-sealed EFROM, X-rays are irradiated from outside the sealing body, and J! By subsequently performing heat treatment, RO
Japanese Patent Application No. 60-17415 describes how to delete data on M.
2 is proposed. This method first uses X-ray irradiation to
The electrons injected into the 0-ting gate are released as photocurrent, and then heat treatment is performed to enable stable rewriting. In other words, the positive charges (holes) among the hole and electron pairs generated during xi thermal irradiation are trapped in the sIO, film, and the Si substrate and sIO, film interface, so they can be thermally excited by performing a subsequent heat treatment process. In this way, electrons are injected to neutralize or move this charge to return it to a normal state and perform stable rewriting.

[Problem that the invention seeks to solve]

As described above, in the technology described above, long-term or high-output X-ray irradiation causes fluctuations in Vth of peripheral elements other than memory elements, and in order to completely recover from the fluctuations, high temperature required heat treatment. but,
There is a problem in that when a resin-sealed package is subjected to heat treatment at a high temperature exceeding the thermal transition point, the package becomes defective in appearance.

[Means for solving problems]

In order to solve the above problem, the inventor of the present invention not only erases data by X-ray irradiation, but also applies voltage to the word line of the memory element to erase written electrons in a short time. It is.

[For production]

As described above, since the voltage is applied to the word line of the memory element at the same time as the X-ray irradiation, data in the memory element can be erased in a short time. Further, fluctuations in Vth of peripheral elements other than the memory element can be kept to a minimum. Further, it is desirable to perform heat treatment after that, but in that case, even if the treatment is performed at a low temperature, fluctuations in Vth of elements other than the memory element can be reliably returned to normal.

Furthermore, by using the above method, it is also possible to use a resin with a low thermal transition point.

Furthermore, since the X-ray irradiation time and heat treatment time are shortened,
Erasing processing time is significantly shorter than before.

〔Example〕

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 1 is a process diagram of a data erasing method according to the present invention.

As can be seen from this figure, the resin package 8 containing the chip 7 is placed at a predetermined position on the voltage application device 11. This chip has a system configuration as shown in Figure 2, and has a memory matrix (Memory Mat
rix) 24, X decoder 18, Y-7' coater 17. Y game) 20. Dekaha 7a 19. It consists of a program logic control circuit 16 that controls the disable or enable state. The circuit configuration of the memory matrix 21 is, for example, as shown in FIG. 4, and the memory cells thereof are, for example, a stacked gate memory cell configuration using MOSFETs as shown in FIG. 3. That is, an n-type source region 25 is formed on a p-type substrate 28.
．． An n-type drain region 26 is formed, and a p-type ion implantation layer 27 is provided in the channel portion to set the threshold voltage to a predetermined value. On the main surface of the substrate 28,
A fluting gate made of polysilicon 30. control gate 29
are provided, and metal electrodes 22, 23, and 24 made of aluminum are provided, respectively.

The voltage application device 11 on which the package 8 is placed is configured to apply a voltage to the word line of the memory cell.

The X-ray 6 emits thermoelectrons from the electrode 3 and hits the target (C
r) Generated by colliding with 5.

As shown in FIG. 1a, an apparatus using the above-mentioned configuration irradiates the chip 7 built into the package 8 with X-rays from outside the package 8, and at the same time irradiates the chip 7 with X-rays placed in the memory matrix of the chip 7. Apply voltage to the word line of the cell. As for the method of applying this voltage, there are three different methods shown in FIG.

(1) Apply a positive ← to the gate, apply a negative (→) to the source (drain) side, activate the electrons trapped in the 70-ting gate, and
irradiate i.

(2) Apply a negative (-) voltage to the gate, set the source (drain) side to GND (ground), and use the tunnel effect of electrons trapped in the floating gate to irradiate X-rays.

(3) Same as (2) above, but the gate is set to GND (ground), + (plus) is applied to the source (drain) side, and X-rays are irradiated.

Furthermore, in the methods (1) and (2) above, it is necessary to select and erase word lines one by one in order to apply negative and negative weights to the gates, respectively. ) According to the method, the gate electrode is set to GND (ground),
Since the source (drain) side is set to 10, a plurality of word lines can be erased simultaneously.

As described above, by applying a voltage to the word line of the memory cell, the electrons accumulated in the 70-ting gate 30 due to X-ray irradiation are synergistically released as photocurrent, and the 70-ting gate 30 is The electrons accumulated within can be dissipated in a short time.

Thereafter, annealing is performed in an annealing furnace equipped with a heat block 12 as shown in FIG. 1 and filled with an inert gas such as N2 gas, and S10. Holes trapped in the film or Si substrate are recombined by injecting electrons through thermal excitation, and fluctuations in Vth of peripheral elements can be restored to their original state, making it possible to perform stable writing.

〔Effect of the invention〕

According to the present invention, it is possible to shorten the irradiation time of Xi to a chip, and to reduce the voltage of elements other than memory cells in the chip.
Fluctuations in th can be minimized and damage to the chip can be reduced.

Since fluctuations in Vth of elements within the chip can be minimized, the temperature of the subsequent annealing process can be lowered.

Since the annealing temperature can be lowered, it is also possible to erase the ROM using a resin with a low thermal transition point.

[Brief explanation of the drawing]

FIGS. 1(a), (b), and (c) are process diagrams showing an embodiment of the present invention, FIG. 2 is a system configuration diagram of an OTFROM, and FIG. 3 is a
A cross-sectional view showing a device structure of a memory cell. FIG. 4 is a schematic diagram of an example of application of circuit pressure to a memory cell portion of an OTFROM. 1... Power supply, 2... Sealed tube, 3... Electrode, 4...
・Electron beam, 5... Terkerat, 6... X-ray, 7...
・Chip, 8... Sealing body, 9... Lead, 10...
・Voltage application device insertion hole, 11... Voltage application device, 12
... heat block, 13 ... hot jet injection cylinder, 14 ... annealing device, 15 ... ROM writer,
16...Control circuit, 17...X decoder, 18...
・X decoder, 19...output buffer, 20...Y
Gate, 21...Memory matrix, 22, 23,
24...AI electrode, 25...source, 26...drain, 27...implant p region, 28...silicon substrate, 29...control gate, 30...floating gate. DLb/ DLty-f DLaZ pL
b2 Figure 5 (lnn and 7

Claims (1)

[Scope of Claims] 1. A data erasing method for a storage device having a storage means and a sealing member for sealing the storage means, the method comprising: applying a voltage to a word line of the storage means; A method for erasing data from a storage device, characterized by irradiating X-rays from the outside. 2. A method for erasing data from a storage device according to claim 1, which comprises performing heat treatment after irradiation with X-rays.