JPH01105241U - - Google Patents
Info
- Publication number
- JPH01105241U JPH01105241U JP20018287U JP20018287U JPH01105241U JP H01105241 U JPH01105241 U JP H01105241U JP 20018287 U JP20018287 U JP 20018287U JP 20018287 U JP20018287 U JP 20018287U JP H01105241 U JPH01105241 U JP H01105241U
- Authority
- JP
- Japan
- Prior art keywords
- data processing
- scsi standard
- processing device
- input
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
- Bus Control (AREA)
Description
第１図は本考案の一実施例に係わるインタフエ
ース回路の構成をデータ処理装置やケーブルとの
関連と共に示す平面図、第２図は第１図の終端抵
抗器３の内部構成を示す分解斜視図、第３図は第
１図の終端抵抗器３の回路図である。
１……データ処理装置、１ａ……インタフエー
スボード、１ｂ……入出力端子群を内蔵する雌コ
ネクタ、２……ケーブル、２ａ……ケーブル本体
、２ｂ……雄コネクタ、３……終端抵抗器、３ａ
，３ａ′……モジユール抵抗、３ｂ……雄コネク
タ、３ｃ……雌コネクタ、３ｄ……プリント配線
板。
FIG. 1 is a plan view showing the configuration of an interface circuit according to an embodiment of the present invention together with the relationship with a data processing device and a cable, and FIG. 2 is an exploded perspective view showing the internal configuration of the terminating resistor 3 of FIG. 3 is a circuit diagram of the terminating resistor 3 shown in FIG. 1. DESCRIPTION OF SYMBOLS 1...Data processing device, 1a...Interface board, 1b...Female connector with built-in input/output terminal group, 2...Cable, 2a...Cable body, 2b...Male connector, 3...Terminal resistor , 3a
, 3a'...module resistor, 3b...male connector, 3c...female connector, 3d...printed wiring board.
Claims (1)
理装置とデイジーチエイン状に相互接続されるこ
とのあるデータ処理装置の本体側に設置される入
出力端子群と、 この入出力端子群と前記ＳＣＳＩ規格のケーブ
ルとの間に着脱自在に挿入されるＳＣＳＩ規格の
デイフアレンシヤル型終端抵抗器とを備えたこと
を特徴とするデータ処理装置の入出力インタフエ
ース回路。[Claim for Utility Model Registration] A group of input/output terminals installed on the main body side of a data processing device that may be interconnected with other data processing devices in a daisy chain form using SCSI standard cables; An input/output interface circuit for a data processing device, comprising a SCSI standard differential type termination resistor that is detachably inserted between an output terminal group and the SCSI standard cable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20018287U JPH01105241U (en) | 1987-12-29 | 1987-12-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20018287U JPH01105241U (en) | 1987-12-29 | 1987-12-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01105241U true JPH01105241U (en) | 1989-07-14 |
Family
ID=31490606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20018287U Pending JPH01105241U (en) | 1987-12-29 | 1987-12-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01105241U (en) |
-
1987
- 1987-12-29 JP JP20018287U patent/JPH01105241U/ja active Pending
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