JPH01102952A - Semiconductor chip carrier system - Google Patents

Semiconductor chip carrier system

Info

Publication number
JPH01102952A
JPH01102952A JP62256144A JP25614487A JPH01102952A JP H01102952 A JPH01102952 A JP H01102952A JP 62256144 A JP62256144 A JP 62256144A JP 25614487 A JP25614487 A JP 25614487A JP H01102952 A JPH01102952 A JP H01102952A
Authority
JP
Japan
Prior art keywords
substrate
chip carrier
semiconductor chip
housing
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62256144A
Other languages
Japanese (ja)
Other versions
JPH0834278B2 (en
Inventor
Dimitry G Grabbe
ディミトリー　ジー　グラッベ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TE Connectivity Corp
Original Assignee
AMP Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AMP Inc filed Critical AMP Inc
Publication of JPH01102952A publication Critical patent/JPH01102952A/en
Publication of JPH0834278B2 publication Critical patent/JPH0834278B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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Abstract

PURPOSE: To obtain a semiconductor chip carrier system that allows semiconductor chips to be connected to external circuits with reliability at various temperatures and under various stresses, by providing a housing, a plurality of semiconductor chips placed on a substrate and a plurality of flexible conductor devices containing cover plates and non-rigid and flexible portions extending inward and outward from the housing. CONSTITUTION: A chip carrier substrate 12 mounted with semiconductor chips 13 and conductors 31 is fixed in the recess 26 in a frame 15. At this time contact pads 32 are attached to the ends of the inner part 36b of leads 36 by soldering 59 or the like. Since the lead sections 36b are non-rigid and flexible, it is possible to connect them direct to the contact pads 32. Distortions produced by thermal expansion, thermal contraction and mechanical stress is absorbed by the lead sections 36b, and reliable connection is ensured. Then polydimethylsiloxyne, for example, is implanted in a chamber 18 to protect the substrate 12 and the semiconductor chips against environment. Subsequently, a cover 17 is installed in the recess 27 in the frame 15.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体チップキャリヤーシステム、特に色々の
温度並びに応力の環境下において外部回路に半導体チッ
プを確実に電気的に接続できる半導体チップキャリヤー
システムに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor chip carrier system, and more particularly to a semiconductor chip carrier system that can reliably electrically connect a semiconductor chip to an external circuit under various temperature and stress environments. .

（従来の技術とその問題点） 集積回路半導体チップは大きさが小さいことと脆い性質
を有するので通常集積回路チップキャリヤーに梱包され
ている。チップキャリヤーは通常集積回路を取付けたセ
ラミックその他の剛性絶縁材料からなる基板を包含し且
つ前記基板は前記チップの近くから該基板の周囲に延在
して拡大コンタクト域又はコンタクトパッドで終端され
る複数本のコンダクタ−を含んでいる。BACKGROUND OF THE INVENTION Due to their small size and fragile nature, integrated circuit semiconductor chips are typically packaged in integrated circuit chip carriers. The chip carrier typically includes a substrate of ceramic or other rigid insulating material on which is mounted an integrated circuit, and the substrate has a plurality of contact areas extending from near the chip to the periphery of the substrate and terminating in enlarged contact areas or contact pads. Contains a book conductor.

しばしば、マルチチップキャリヤー基板はそれとその上
のチップを防護し且つ支持するフレーム又はハウジング
内に内包され、且つ前記基板を印刷回路盤またはその他
の外部回路に電気的に接続するためのコネクタを提供す
る。一般に、前記フレームまたはハウジングは複数本の
リードを含んでいる。前記各リードの一端は基板のコン
タクトパッドの１つに電気的に接続されるためハウジン
グの中に延び、且つ前記各リードの他端はハウジングが
延出して印刷回路盤のコンタクトに直接またはソケット
コネクタを通じて接続される。Often, a multichip carrier board is enclosed within a frame or housing that protects and supports it and the chips thereon, and provides connectors for electrically connecting the board to a printed circuit board or other external circuitry. . Generally, the frame or housing includes a plurality of leads. One end of each lead extends into the housing for electrical connection to one of the contact pads of the board, and the other end of each lead extends from the housing to connect directly to a contact on the printed circuit board or to a socket connector. connected through.

従来、集積回路半導体チップキャリヤーシステムは集積
回路チップを取付けるセラミックその他の非可撓性材料
からなる剛性基板を包含するどとを特徴としている。る
前記剛性セラミック基板はその中に埋め込まれたコンダ
クタ−（多層コーファヤードセラミック基板）、また該
基板の表面に積層されたコンダクタ−（薄いかまたは厚
い膜のセラミック基板）を備えている。成る場合に、前
記コンダクタ−は基板の表面に均一に付むされた膜に含
まれた。チップから基板のコンダクタ−への電気的接続
並びに基板のコンダクタ−からハウジングリードへの電
気的接続は金やアルミニウムのボンドワイヤーによって
行われ、システムの各種部品の熱膨脹や収縮における変
化と物理的歪みを補償し、且つ半導体チップと基板の間
に接続を行う。しかしながら、このような接続は製作が
高価であり且つ完全に満足と（よ認められなかった。Conventionally, integrated circuit semiconductor chip carrier systems have been characterized as including a rigid substrate of ceramic or other non-flexible material to which an integrated circuit chip is mounted. The rigid ceramic substrate has conductors embedded therein (multilayer coffered ceramic substrate) and conductors laminated to the surface of the substrate (thin or thick film ceramic substrate). In this case, the conductor was included in a film that was uniformly applied to the surface of the substrate. Electrical connections from the chip to the board conductors and from the board conductors to the housing leads are made by gold or aluminum bond wires, which resist changes in thermal expansion and contraction and physical distortion of the various components of the system. compensation and connections between the semiconductor chip and the substrate. However, such connections are expensive to make and have not been completely satisfactory.

また、従来の半導体チップキャリヤーシステムはハウジ
ングを密封するためにハウジングとそこを貫通するリー
ドとの間を密封するためガラスシールを含んだ大体剛性
のあるハウジング構造体を備えていた。また、このよう
なシステムはハウジング部品の温度膨張及び収縮の変化
とその他外部応力の結果として密封性を維持することの
困難性の故に、またこのような構造物が非常に高価であ
る故に、完全に満足ではなかった。Additionally, conventional semiconductor chip carrier systems have included a generally rigid housing structure that includes a glass seal to seal between the housing and the leads passing therethrough. Additionally, such systems are not perfect due to the difficulty of maintaining a tight seal as a result of changes in temperature expansion and contraction of housing components and other external stresses, and because such construction is very expensive. I wasn't satisfied with it.

また、従来の多くの半導体マルチチップキャリヤーシス
テムは大きさを制限されてきた。特に、従来のセラミッ
ク基板の製造法は約２インチ×２インチ（５０，８ａｗ
Ｘ　５０．８■）以上の大きさの充分偏平な基板を作る
ことができなかった。これはファイヤリング作業中にセ
ラミックの寸法上の安定性を維持することが困難なこと
に基因している。Additionally, many conventional semiconductor multichip carrier systems have been limited in size. In particular, conventional ceramic substrate manufacturing methods are approximately 2 inches by 2 inches (50.8 aw
It was not possible to produce a sufficiently flat substrate with a size larger than 50.8 cm). This is due to the difficulty in maintaining the dimensional stability of the ceramic during firing operations.

（問題点を解決するための手段） 本発明は使用が容易で低摩であり、且つ色々の温度と応
力の状態で１個以上の半導体チップを外部回路に確実に
相互接続できる集積回路半導体チップを提供する。本発
明のシステムはシステムのハウジングに介在する小さな
部分以外は殆んど仝体が非剛性で可撓性であるコンダク
タ−装置を含んでいる。本発明の好適な実施例はハウジ
ングと基板上の１個以上の半導体チ・ツブと、前記ハウ
ジングの１個以上の壁に支持される第１部分を有し且つ
基板に接続するためハウジングから内方へ延び且つ外部
回路へと外方へ延びる実質的に非剛性で柔軟な部分を有
する複数本の可撓性コンダクタ−装置を包含する。前記
可撓性コンダクタ−装置は数が１８００８ｉ類であ−り
また間隔が０．０１０インチ（０，０２５４ａｍ）程度
である。SUMMARY OF THE INVENTION The present invention provides an integrated circuit semiconductor chip that is easy to use, has low friction, and provides reliable interconnection of one or more semiconductor chips to external circuitry at a variety of temperatures and stress conditions. I will provide a. The system of the present invention includes a conductor device that is substantially non-rigid and flexible except for a small portion interposed in the housing of the system. A preferred embodiment of the invention includes a housing and one or more semiconductor chips on a substrate, a first portion supported by one or more walls of the housing and extending from the housing for connection to the substrate. and includes a plurality of flexible conductor devices having substantially non-rigid, flexible portions extending toward the external circuit and outwardly to the external circuit. The flexible conductor devices are 18008i in number and spaced on the order of 0.010 inch (0.0254 am).

基板上のチップ間の相互接続は厚い膜、薄い膜、コーフ
ァイヤード、プレーテッド　コンダクタ−のような中間
装置において作ることができる。また、相互接続を新ら
しい装置で作っても良く、その場合にチップとチップの
接続用ネットを少くとも１つの層に、成る場合には“マ
イクロストリップ”状又は“ストリップ−ライン１状に
配置した４５層のような多層に配置した薄い可撓性のコ
ンダクタ−を含む有機性材料で作る。すべての場合に相
互接続用ネットの集積回路に窓が設けられる。Interconnections between chips on a substrate can be made in intermediate devices such as thick film, thin film, cofired, and plated conductors. Alternatively, the interconnections may be made with new equipment, in which case the chip-to-chip connecting nets are arranged in at least one layer, if in the form of a "microstrip" or "strip-line". In all cases, windows are provided in the integrated circuit of the interconnection net.

相互接続用ネットは基板の全面に取付けられなくて、成
る点のみに取付けて、基板と相互接続用ネットを温度変
化の結果それぞれの膨張係数に応じてそれぞれ別々に膨
張又は収縮せしめる。これが一般に“バイ−メタル”効
果と称されているカップリングの有害な干渉を排除する
。このようにして本発明は従来さけることのできなかっ
たシステムの歪と応力を排除した電気的接続を行う。The interconnection net is not attached to the entire surface of the substrate, but only at points, allowing the substrate and the interconnection net to expand or contract separately as a result of temperature changes, depending on their respective coefficients of expansion. This eliminates the harmful interference of the coupling, commonly referred to as the "bi-metal" effect. In this manner, the present invention provides an electrical connection that eliminates system distortion and stress that was previously unavoidable.

好適な実施例において、前記半導体チップキャリヤーシ
ステムは１個又はそれ以上の周囲壁を貫いて延びる複数
個のリードを有する大体矩形のハウジングを包含する。In a preferred embodiment, the semiconductor chip carrier system includes a generally rectangular housing having a plurality of leads extending through one or more peripheral walls.

前記リードはハウジング璧に埋めた中央部分と、ハウジ
ングの外側に延びて外部回路に電気的に接続されるよう
になった外側の柔軟部分と、ハウジングの中１こ含まれ
るチップキャリヤー基板上のコンタクトパッドに電気的
に接続されるようになった内側の柔軟部分とを包含する
。チップキャリヤー基板は電気的に取付けられているチ
ップキャリヤーに配置された複数個の半導体チップを担
持するようになった例えばセラミックや金属のような剛
性材料で作る。チップキャリヤー基板はハウジングの壁
に固定されている。The lead includes a central portion embedded in the housing wall, an outer flexible portion extending outside the housing to be electrically connected to an external circuit, and a contact on a chip carrier board contained within the housing. and an inner flexible portion adapted to be electrically connected to the pad. The chip carrier substrate is made of a rigid material, such as ceramic or metal, adapted to carry a plurality of semiconductor chips disposed on an electrically attached chip carrier. A chip carrier substrate is fixed to the wall of the housing.

なるべく薄く可撓性のあるプラスチック膜を含む電気接
続部材またはネットは、複数個のチップを電気的に相互
接続するため、並びに膜の周囲に置いたパッドをフレー
ムの内側リードに接続するため複数個の可撓性のコンダ
クタ−を含み且つ支持している。前記膜は成る点におい
て機械的に保持されて前記膜の基板に対する横方向の移
動を制限しているが、一般に基板の殆んど全域から取り
外されて前記膜と基板が互いに別々に撓み歪ませるよう
になっている。A plurality of electrical connection members or nets comprising a preferably thin and flexible plastic membrane are used to electrically interconnect multiple chips and to connect pads placed around the membrane to the inner leads of the frame. It contains and supports a flexible conductor. The membrane is mechanically retained at points to limit lateral movement of the membrane relative to the substrate, but is typically removed from most areas of the substrate to allow the membrane and substrate to flex and strain independently of each other. It looks like this.

前記リードはハウジングにより支持され且つチップキャ
リヤーのコンダクタ−は殆んど非剛性で柔軟であり且つ
温度変化及びその他のストレスにより生じたシステム部
品の変形を許すことができるので、リードと膜の可撓性
コンダクタ−の間及び基板端縁パッドとフレームリード
の間の中間のワイヤーボンド接続を省略することができ
る。本発明の多くの実施例において、リードは直接チッ
プキャリヤー基板のコンタクトパッドに接続することが
でき、且つチップのターミナル域はもっと効果的なテー
プ自動式接着法によりまた標準のワイヤーボンドにより
膜コンダクタ−に接続できる。Flexibility of the leads and membranes because the leads are supported by the housing and the conductors of the chip carrier are mostly non-rigid and flexible and can tolerate deformation of system components caused by temperature changes and other stresses. Intermediate wire bond connections between the conductors and between the substrate edge pads and the frame leads can be omitted. In many embodiments of the present invention, the leads can be connected directly to contact pads on the chip carrier substrate, and the terminal areas of the chip can be connected to membrane conductors by standard wire bonding as well as by the more effective tape automatic bonding method. can be connected to.

前記システムは集積回路を湿気から防護するため、また
チップの環境防護を提供するため防護用シェリー状コン
パウンドを部分的に満たした囲繞ハウジングを提供する
。前記ハウジングのチップキャリヤー基板の反対側は金
属その他の材料のカバーで閉ざされて構造上の防護を行
っている。The system provides an enclosing housing partially filled with a protective shelly compound to protect the integrated circuit from moisture and to provide environmental protection for the chip. The side of the housing opposite the chip carrier substrate is closed with a cover of metal or other material to provide structural protection.

本発明において、チップキャリヤー基板の電気的相互接
続部材またはネットは実質的に剛性基板から分離できる
。したがって、特殊な応用分野に対し剛性基板の構造上
並びに温度特性を最高にし且つ同時にコンダクタ−の送
電線特性を最適化するようチップキャリヤーを設、計す
るに当り大なる融通性が得られる。例えば、本発明にお
いて剛性基板を特殊な応用分野に対し必要に応じ高熱伝
導性を有する金属その他の材料で作ることができる。In the present invention, the electrical interconnects or nets of the chip carrier substrate can be substantially separated from the rigid substrate. Great flexibility is thus provided in designing and designing the chip carrier to maximize the structural and thermal properties of the rigid substrate and at the same time optimize the conductor's transmission line properties for a particular application. For example, the rigid substrate in the present invention can be made of metal or other materials with high thermal conductivity as needed for a particular application.

更に、電気接続部材をチップキャリヤー基板のチップ支
持基板から分離できるので、偏平でなく曲った表面を相
互接続用ネットに許容することができ、且つこのように
して基板をもつと大きな寸法、例えば６インチ×６イン
チ（１５，２１１１１Ｘ　１５．２ｃｍ）以上広く作る
ことができ。且つ単一のチップキャリヤー基板に多くの
半導体チップを収容することができる。また、コンダク
タ−を多層可撓性膜の中に含めることによって、チップ
に対し必要な電気接続を増大するため従来より以上にコ
ンダクタ−の密度を大きくすることができる。基板の毎
平方インチ当り６００以上のチャンネルが必要となる。Furthermore, since the electrical connection members can be separated from the chip support substrate of the chip carrier substrate, curved surfaces rather than flat surfaces can be accommodated in the interconnection net, and with the substrate in this way large dimensions, e.g. Can be made wider than 15.2 inches x 6 inches (15,21111 x 15.2 cm). Moreover, many semiconductor chips can be accommodated on a single chip carrier substrate. Also, by including the conductors in a multilayer flexible membrane, a greater density of conductors than previously possible can be achieved to increase the required electrical connections to the chip. More than 600 channels are required per square inch of substrate.

本発明の１つの実施例において、セラミック基板は集積
回路半導体チップを取付ける複数個のへこみを形成され
ている。このような構造であるから、チップのターミナ
ル域をチップキャリヤー基板のコンダクタ−に接続する
ため短いワイヤーやテープ自動式ボンディング法の使用
が可能となり、かくして電気抵抗とインダクタンスを減
少し且つシステムの信頼性を増大する。相互接続用ネッ
トにおける窓の中に延びたリードを設け、このようなリ
ードを直接シップに送ることができるように、相互接続
用ネットを形成し、ＴＡＢ　（テープ自動式ボンディン
グ）やワイヤーボンドの中間接続の必要性を無くす。本
発明の別の実施例において、前記チップキャリヤー基板
を金属で作ることができる。チップを基板上に一層正確
に位置決めするため該チップを該基板に形成したベデス
タイルに取付けることができる。In one embodiment of the invention, a ceramic substrate is formed with a plurality of recesses for mounting integrated circuit semiconductor chips. This construction allows the use of short wire or tape automatic bonding methods to connect the terminal area of the chip to the conductors of the chip carrier board, thus reducing electrical resistance and inductance and increasing system reliability. increase. The interconnect net is formed with leads extending into windows in the interconnect net so that such leads can be routed directly to the ship, allowing for TAB (tape automated bonding) or wire bond intermediaries. Eliminate the need for connections. In another embodiment of the invention, the chip carrier substrate can be made of metal. To more accurately position the chip on the substrate, the chip can be attached to a bede tile formed on the substrate.

本発明において、個々の半導体チップを色々の工法によ
りチップキャリヤー基板に取付けることができる。例え
ば、チップを“フリップチップ２取付は構造及びモジュ
ールスプリング取付は構造を使用して基板に取付けるこ
とができるのでチップキャリヤーの設計に大きな融通性
を与える。このような取付法は誘電率１〜６を有し且つ
“アズファヤード”状態における５ミクロンインチ表面
仕上げ以上の良好な仕上げを有するセラミック基板を使
用して、基板上に支持された複数個のチップの間に必要
な相互接続用ネットワークを提供できる多数層の有機性
コンパウンドを支持することができる。In the present invention, individual semiconductor chips can be attached to a chip carrier substrate by various methods. For example, chips can be attached to a substrate using a "flip chip 2 mounting structure and a module spring mounting structure, providing great flexibility in the design of chip carriers. Such mounting methods provide Ceramic substrates having a surface finish of 5 micron inches or better in an “as-fayed” condition can be used to provide the necessary interconnection network between the chips supported on the substrate. Multiple layers of organic compounds can be supported.

本発明のそれ以上の効果と詳細がここに提供した実施例
の詳細な説明に関連して以下詳しく述べられる。Further advantages and details of the invention will be described in detail below in connection with the detailed description of the embodiments provided herein.

（実　施　例） 第１図および第２図は本発明の半導体チップキャリーシ
ステムの好適実施例を示す。前記システムは全体的に参
照番号１０で示され且つハウジング１１を備えている。(Embodiment) FIGS. 1 and 2 show a preferred embodiment of the semiconductor chip carrying system of the present invention. The system is indicated generally by the reference numeral 10 and includes a housing 11.

該ハウジング１１は複数個の集積回路半導体チップ１３
を取付けたチップキャリヤー基板１２を収容している。The housing 11 houses a plurality of integrated circuit semiconductor chips 13.
The chip carrier board 12 with attached chip carrier board 12 is housed therein.

ハウジング１１はチップキャリヤー基板１２とその上の
チップ１３を防護し且つ支持し、且つチップキャリヤー
基板１２上のチップ１３を印刷回路盤１４のような外部
回路に電気的に接続する。Housing 11 protects and supports chip carrier substrate 12 and chips 13 thereon, and electrically connects chips 13 on chip carrier substrate 12 to external circuitry, such as printed circuit board 14.

ハウジング１１は凡そ正方形または矩形の箱状構造体を
含み且つ側壁２１．２２．２３．２４とチップキャリヤ
ー基板１２が形成する頂壁とカバー板１７が形成する底
壁を有する周囲フレーム１５を含んでいる。組立てたと
き前記ハウジングの壁が第２図に示すよう密閉室１８を
形成する。フレーム１５は頑丈であるが幾分柔軟な塑造
性プラスチック（液状クリスタルポリマーが特に適して
いる）でなるべく作られ且つチップキャリヤー基板１２
とカバー板１７をそれぞれ収容するための上部へこみ２
６と下部へこみ２７を形成している。チップキャリヤー
基板１２は第２図において頂板を形成するように図示さ
れているが、チップキャリヤー基板１２とカバー板１７
を第３図に示すように逆にして、チップキャリヤー基板
１２が底壁を形成し且つカバー板１７が頂板を形成する
ようにしても良い。The housing 11 comprises a generally square or rectangular box-like structure and includes a peripheral frame 15 having side walls 21, 22, 23, 24 and a top wall formed by the chip carrier substrate 12 and a bottom wall formed by the cover plate 17. There is. When assembled, the walls of the housing form a sealed chamber 18 as shown in FIG. The frame 15 is preferably made of a sturdy but somewhat flexible plastic plastic (liquid crystal polymer is particularly suitable) and the chip carrier substrate 12
and a cover plate 17, respectively.
6 and a lower recess 27 is formed. Although chip carrier substrate 12 is shown forming the top plate in FIG. 2, chip carrier substrate 12 and cover plate 17
may be reversed, as shown in FIG. 3, so that the chip carrier substrate 12 forms the bottom wall and the cover plate 17 forms the top plate.

あとで詳細に説明するチップキャリヤー基板１２は剛性
材料例えばセラミックのような偏平で比較的薄い板から
なる基板３０を含んでいる。複数個の集積回路半導体チ
ップ１３が当業者の熟知の方法で基板３０の表面３５に
取付けられている。しかしながら、後述するようにその
他の取付は構造を使用しても良い。Chip carrier substrate 12, which will be described in more detail below, includes a substrate 30 comprised of a flat, relatively thin plate of rigid material, such as ceramic. A plurality of integrated circuit semiconductor chips 13 are attached to surface 35 of substrate 30 in a manner well known to those skilled in the art. However, other attachment structures may be used as described below.

また、チップキャリヤー基板１２は複数個のチップ１３
を互に接続するため並びにキャリヤー基板１２の周囲の
近くに設けた複数個の接触パッド３２に接続するための
複数本のコンダクタ−３１（第１図）を備えている。当
業者が熟知しているように、コンダクタ−３１が基板３
０（多層のコーファヤードセラミック拭板）の中に埋め
込まれるか、または基板３０（薄いかまたは厚い膜状セ
ラミック基板）の表面３０に層状に造られる。セミコン
ダクターチップ１３のターミナル域はゴールドワイヤー
テープまたはテープ状ボンド３３によってコンダクタ−
３１に接続される。Further, the chip carrier substrate 12 has a plurality of chips 13
A plurality of conductors 31 (FIG. 1) are provided for connecting the carrier substrates 12 to each other and to a plurality of contact pads 32 provided near the periphery of the carrier substrate 12. As those skilled in the art are familiar with, conductor 31 is connected to substrate 3.
0 (multilayer coffered ceramic wipe) or layered onto the surface 30 of a substrate 30 (thin or thick membrane ceramic substrate). The terminal area of the semiconductor chip 13 is connected to a conductor using gold wire tape or tape-like bond 33.
31.

複数本の導電性リード３６がフレーム１５によって支持
されている。リード３６はフレーム１５の周囲に殆んど
均一に隔置され且つ例えば銅合金のような可撓性金属で
作ったリボン状部材を備えている。A plurality of conductive leads 36 are supported by the frame 15. The leads 36 include ribbon-like members spaced nearly uniformly around the periphery of the frame 15 and made of a flexible metal, such as a copper alloy.

このようにして１８００本以上の多くのリードがＯ８旧
インチ（’０．２５４　Ｊｉｌｔ）の間隔で使用される
。第２図に示すように、リード３６はそれぞれフレーム
１５を貫通し且つ該フレームによフて支持される中央部
分３６ａと、ハウジング１１の中に延在する内側部分３
６ｂと、ハウジング１１の外に延在する外側部分３６Ｃ
とを備えている。リープ３６はなるべくリード中央部分
３６ａの周りにフレーム１５をモールドすることにより
該フレーム１５に固定される。In this way, over 1800 leads are used with O8 old inch ('0.254 Jilt) spacing. As shown in FIG. 2, each lead 36 has a central portion 36a that extends through and is supported by the frame 15, and an inner portion 36a that extends into the housing 11.
6b and an outer portion 36C extending outside the housing 11.
It is equipped with Leap 36 is secured to frame 15, preferably by molding frame 15 around lead central portion 36a.

内側リード部分３６ｂはフレーム１５から内側に一定の
距離突出し且つ曲げられて、チップキャリヤー基板」２
上のコンタクトパッド３２に直接接続されるビームを形
成する。内側リード部分３６ｂの端部はパッド３２に接
触する場所が大体偏平となるように配置されている。外
側リード部分３６ｃはフレーム１５から外方に突出し且
つ印刷回路盤１４のコンタクトパッド３７（第２図参照
）に直接接続される形状となっている。第１図および第
２図の実施例において、外側リード部分８６ｃはＪ形で
あるるが、例えば第３図に示すような別の形状を使用す
るこもできる。The inner lead portion 36b protrudes inwardly from the frame 15 by a certain distance and is bent to connect the chip carrier substrate 2.
Forming a beam that is directly connected to the contact pad 32 above. The end of the inner lead portion 36b is arranged so that the portion where it contacts the pad 32 is generally flat. The outer lead portion 36c is shaped to project outwardly from the frame 15 and to be directly connected to a contact pad 37 (see FIG. 2) on the printed circuit board 14. In the embodiment of FIGS. 1 and 2, the outer lead portion 86c is J-shaped, but other shapes may be used, such as shown in FIG. 3, for example.

システム１０を組立てるため、半導体チップ１３を取付
は且つコンダクタ−３１を設けであるチップキャリヤー
基板１２がフレーム１５のへこみ２Ｂの中に配置されて
いる。つぎにチップキャリヤー基板１２がそれとたな２
８との間に施された適当な接着剤８８によってフレーム
１５に固定されている。To assemble system 10, chip carrier substrate 12, on which semiconductor chip 13 is mounted and conductor 31 is provided, is placed in recess 2B of frame 15. Next, the chip carrier board 12 is attached to it.
It is fixed to the frame 15 by a suitable adhesive 88 applied between the frame 15 and the frame 15.

チップキャリヤー基板１２をフレーム１５に取付ける際
に、コンタクトパッド８２がリード３６の内側部分３６
ｂの端部に整列して接触させられる。つぎに各リード部
分３１３ｂの端部が加熱加圧接着法、半田付は法、蝋付
は法やその他の適当な方法で前述の整列したコンタクト
パッドに取付けられる。第２図に半田付は部３９を示す
。リード部分３６ｂは非剛性で柔軟性を有するので、中
間の接続部を使用しなくて、直接コンタクトパッド３２
に接続することができる。熱膨張並びに熱収縮または機
械的な応力によって発生したチップキャリヤー基板１２
またはハウジング１１の歪みや曲がりはリード部分３６
ｂの弾力性によって許容され、その結果信頼性の高い接
続がリード３６とコンタクトパッド３２の間に確保され
る。When attaching the chip carrier substrate 12 to the frame 15, the contact pads 82 are attached to the inner portions 36 of the leads 36.
are aligned and brought into contact with the ends of b. The ends of each lead portion 313b are then attached to the aligned contact pads by heat and pressure bonding, soldering, brazing, or any other suitable method. The soldering portion 39 is shown in FIG. Since the lead portion 36b is non-rigid and flexible, it can be connected directly to the contact pad 32 without the use of an intermediate connection.
can be connected to. Chip carrier substrate 12 caused by thermal expansion and contraction or mechanical stress
Or if the housing 11 is distorted or bent, the lead portion 36
b, so that a reliable connection is ensured between the lead 36 and the contact pad 32.

組立てを一部分完成したハウジングをつぎに裏返えし且
つ室１８の一部分又は全部にコンパウンド例えばポリジ
メチルシロキシン（第２図に４０で示す）を注入して、
チップキャリヤー基板１２と半導体チップに対し湿気と
環境の防護を与える。つぎに、金属製またはその他の材
料で作ったカバー１７をフレーム１５のへこみ２７の中
に取付は且つカバー１７とたな２９の間に接骨剤４１を
施すことによって該へこみに接骨するかまたは機械的に
取付ける。The partially assembled housing is then turned over and a portion or all of the chamber 18 is injected with a compound such as polydimethylsiloxine (shown at 40 in FIG. 2).
Provides moisture and environmental protection for the chip carrier substrate 12 and semiconductor chips. Next, a cover 17 made of metal or other material is installed in the recess 27 of the frame 15 and either bone-sewn into the recess by applying bone cement 41 between the cover 17 and the sheath 29, or mechanically cemented into the recess. Install it.

組立てたとき前記ハウジング１１はチップキャリヤー基
板１２と該基板上の傷つき易い半導体チップ１３を密閉
シールを施さずに確実に防護することができる完全囲繞
コンテーナーを包含する。リード３６は柔軟性があるの
で破かいや割れを発生ずに一定限曲げたり撓わませるこ
とができ、したがって熱応力と機械的応力のもとてハウ
ジングの形状を保つことができる。When assembled, the housing 11 includes a fully enclosed container that can reliably protect the chip carrier substrate 12 and the sensitive semiconductor chips 13 thereon without the need for a hermetic seal. The lead 36 is flexible and can be bent or flexed to a certain extent without tearing or cracking, thus allowing the housing to maintain its shape under thermal and mechanical stresses.

組立作業に続いてシステム１０を使用のためまたは試験
のため印刷回路盤１４やその他の外部回路に接続する。Following assembly, system 10 is connected to printed circuit board 14 or other external circuitry for use or testing.

第２図に示すように、リード３６の外側部分３６ｃは印
刷回路盤１４のコンタクトパッド３７にのせられ、そこ
に導電性半田４３によって直接接続されて、チップキャ
リヤー基ｌＲ１２とその上の半導体チップ１３を印刷回
路盤に電気的に接続する。As shown in FIG. 2, the outer portions 36c of the leads 36 rest on the contact pads 37 of the printed circuit board 14 and are directly connected thereto by conductive solder 43 to connect the chip carrier base lR12 and the semiconductor chip 13 thereon. electrically connect to the printed circuit board.

、第３図は本発明の数種の実施例を示す。例えば第３図
においてリード５６は印刷回路盤１４のコンタクトパッ
ド３７に直接接続するためかもめの羽根の形状をした外
側部分５６ｃ（実線部分）を含んでいる。, FIG. 3 shows several embodiments of the invention. For example, in FIG. 3, lead 56 includes a seagull wing shaped outer portion 56c (shown in solid lines) for direct connection to contact pad 37 of printed circuit board 14.

リード５６の内側部分５８ｂは第１図及び第２図の実施
例の中より幾分長い距離ハウジング１１の中に延在して
該リード部分に大きな可撓性を与えるような形状をして
いる。第３図に点線で示すように、またリード５６は印
刷回路盤１４にソケット接続できるよう偏平な外側リー
ド部分５６ｄを設けることもできる。これらの例は説明
上のものであって、リード５Ｂの外側部分をこれら図示
の形状に限定しようとする考えはない。The inner portion 58b of the lead 56 is shaped to extend into the housing 11 a somewhat greater distance than in the embodiment of FIGS. 1 and 2, giving the lead portion greater flexibility. . As shown in dotted lines in FIG. 3, the leads 56 may also be provided with a flattened outer lead portion 56d for socket connection to the printed circuit board 14. These examples are for illustrative purposes only, and there is no intention to limit the outer portions of the leads 5B to the shapes shown.

第３図の実施例において、防護用コンパウンド４０とカ
バー１７を、半導体チップ１３のそれぞれを外部環境か
ら密閉するための分離状のキャップ６１ととりかえてい
る。キャップ６１はセラミックやその他の適当な材料で
作り且つ半導体チップ１３を完全に囲繞する形状にする
ことができる。キャップ６１はチップを囲繞して収容す
るようにチップキャリヤー１２ａの基板３０に接着され
て外部環境からチップを防護する。このようなキャップ
が使用されるとき、相互連結装置はキャップの下に延長
するコンダクタ一部分６２を含んでいる。この明細書の
中に参考のため含まれている米国特許第４．４２８．７
８９号に適当な密封用キャップが図示且つ説明されてお
り、これについて詳細に説明する必要がない。In the embodiment of FIG. 3, the protective compound 40 and cover 17 are replaced by separate caps 61 for sealing each semiconductor chip 13 from the external environment. Cap 61 may be made of ceramic or other suitable material and shaped to completely surround semiconductor chip 13. The cap 61 is adhered to the substrate 30 of the chip carrier 12a so as to surround and house the chip, thereby protecting the chip from the external environment. When such a cap is used, the interconnection device includes a conductor portion 62 that extends beneath the cap. U.S. Pat. No. 4.428.7, incorporated herein by reference.
A suitable sealing cap is shown and described in No. 89 and need not be described in detail.

第４Ａ図と第５Ａ図は本発明のチップキャリヤーシステ
ムに組入れることができる別のチップキャリヤー基板７
１のそれぞれ分解図及び組立断面図である。チップキャ
リヤー基板７１は表面７４（第５Ａ図）に複数個の半導
体チップ７３を取付けたセラミックやその他の材料から
なる剛性基板７２を包含する。チップキャリヤー基板７
１のために相互連結部材７Ｂが設けられている。相互連
結部材７６は半導体チップ７３を互に電気的に接続し且
つ該相互連結部材７Ｂの周囲近くに配置したコンタクト
パッド７８（第４Ａ図）に電気的に接続するための複数
本のコンダクタ−７７を提供する。相互連結部材７Ｂは
なるべく一層または複数層からなる薄い可撓性のプラス
チック膜またはシート７９を包含している。前記膜の表
面または該膜の内部にコンダクターフ７を備えるか、ま
たは表面と膜の内部の両方においてリード７７が窓８０
の中に延びている。FIGS. 4A and 5A illustrate another chip carrier substrate 7 that can be incorporated into the chip carrier system of the present invention.
1 is an exploded view and an assembled cross-sectional view, respectively. Chip carrier substrate 71 includes a rigid substrate 72 of ceramic or other material having a plurality of semiconductor chips 73 mounted on a surface 74 (FIG. 5A). Chip carrier board 7
1, an interconnection member 7B is provided. Interconnect member 76 includes a plurality of conductors 77 for electrically connecting semiconductor chips 73 to each other and to contact pads 78 (FIG. 4A) located near the periphery of interconnect member 7B. I will provide a. Interconnecting member 7B includes a thin flexible plastic membrane or sheet 79, preferably consisting of one or more layers. Either the conductor 7 is provided on the surface of the membrane or inside the membrane, or the lead 77 is provided with a window 80 on both the surface and inside the membrane.
extends into the

例えば、プラスチック膜７９は誘電率１〜３を有するポ
リアミド、テフロンその他の誘電性有機材料で作ること
ができ、且つ例えば第４Ｂ図に示すように高密度の誘電
体を提供するため多数層膜をなるべく包含する。第４Ｂ
図において、相互連結部材７Ｂは２枚の誘電性箔層８４
，８Ｂによって分離されている３枚の誘電層８１．８２
．８３を持った多層膜を包含する。誘電層８１．８２．
８３はそれぞれ複数本のコンダクタ−８７，８８，８９
（第４Ｂ図の面に垂直方向に延びるよう図示している）
を有する。For example, the plastic film 79 can be made of polyamide, Teflon, or other dielectric organic material with a dielectric constant of 1 to 3, and can be made of multiple layers to provide a high density dielectric, as shown in FIG. 4B, for example. Be as inclusive as possible. 4th B
In the figure, interconnection member 7B includes two dielectric foil layers 84.
, 8B, three dielectric layers 81, 82 separated by
．． 83 is included. Dielectric layer 81.82.
83 is a plurality of conductors - 87, 88, 89
(Illustrated to extend perpendicular to the plane of Figure 4B)
has.

コンダクタ−８７，８８，８９は多くの半導体チップ７
３の間並びにチップ７３からコンタクトパッド７８に信
号を送るための信号搬送用コンダクタ−を包含する。箔
層８４はパワープレイン（ｐｏｗｅｒ　ｐｌａｎｅ）を
含み、且つ箔層８Ｂはグランドプレイン（ｇｒｏｕｎｄ
　ｐｌａｎｅ）を含むことができる。コンダクタ−担持
用の多層膜とその製造方法は当業者に公知であり且つ例
えば米国特許箱４．４８０．２８８号に説明されており
、ここに詳細に説明する必要がない。基本的に、前記コ
ンダクタ−は印刷技法とエツチング技法によって形成さ
れ且つ一緒に積層されて完全な膜を形成する。またその
代りに、スパッタ法と真空蒸着法とプラズマエツチング
法によって絶縁層や導電層を順番に蒸着する方法を使用
し、同様に半導体溶液に相互接続を行なったときに使用
する加算法と減算法の組合せを使用しても良い。Conductors 87, 88, 89 are many semiconductor chips 7
3 as well as signal carrying conductors for transmitting signals from the chip 73 to the contact pads 78. Foil layer 84 includes a power plane, and foil layer 8B includes a ground plane.
plane). Multilayer membranes for carrying conductors and methods for their manufacture are known to those skilled in the art and are described, for example, in U.S. Pat. No. 4,480,288, and need not be described in detail here. Basically, the conductors are formed by printing and etching techniques and are laminated together to form a complete membrane. Alternatively, sputtering, vacuum deposition, and plasma etching can be used to sequentially deposit insulating and conductive layers, as well as the additive and subtractive methods used when making interconnections in semiconductor solutions. A combination of these may also be used.

可撓性の相互接続部材７Ｂは約６〜２０ミル（０，１５
〜０．５０ｍ）の厚さを有し、且つ各誘電層は約３ミル
（０，０７５ａｍ）の厚さを有する。前記コンダクタ−
は例えば約ｏ、ｏｏｏｓ〜０．００２インチ（０，０１
２７〜０．０５Ｊｌｌ）の厚さとｏ、ｏｏｔ〜ｏ、ｏｏ
ａインチ（０，０２５〜０．０７５１１ｅｓ）の幅を有
し且つ前記箔層は約１ミル（０，０２５４＃）の厚さを
有する。膜の層の数とその大きさは勿論特定の使用に応
じて変えることができる。The flexible interconnect member 7B is about 6-20 mils (0.15
~0.50 m) and each dielectric layer has a thickness of approximately 3 mils (0.075 am). The conductor
For example, about o,oos to 0.002 inches (0,01
27~0.05Jll) thickness and o,oot~o,oo
The foil layer has a width of a inch (0.025-0.07511 es) and a thickness of about 1 mil (0.0254#). The number of membrane layers and their size can, of course, vary depending on the particular use.

特に第４Ａ図の実施例を参照すれば、相互接続部材７６
は複数個の孔８０を備え、該部材７８を基板７４上にの
せるときチップ７３が前記孔８０の中を貫通する。With particular reference to the embodiment of FIG. 4A, interconnect member 76
has a plurality of holes 80, and when the member 78 is placed on the substrate 74, the chip 73 passes through the holes 80.

可撓性膜７９を備え表面にコンダクタ−７７とコンタク
トパッド７８を有する相互接続部材７６が接着剤や任意
の適当な機械的取付装置によって第４Ａ図の数個所（例
えば４個所）　９１で基板７２の表面に取付けられてい
る。相互接続部材７Ｇはこのようにして保持されている
が、そうしなければ基板７２の表面の全域から外れて、
幾分該表面にゆるく　（張った状態でない）配置されて
いる。相互接続部材７Ｂを剛性のある基板に対し非常に
少数の個所で取付けているので、相互接続部材７Ｂが基
板７２に対し横方向に移動するのを抑制するが、コンダ
クタ−７７を自由に基板７２とチップ７３に対し撓わま
せ且つ変形させる。換言すれば、チップキャリヤー基質
７１において可撓性のコンダクタ−担持用相互接続部材
７Ｂは物理的に剛性基板７２から分離しており、基板７
２の歪みや曲りがコンダクタ−７７に影響せず且つチッ
プキャリヤー基板７１の電気的性能に干渉しない。相互
接続部材７Ｂとコンダクタ−７７は可撓性を有するので
、基板Ｔ２と膜の膨張係数に差が存在しても、チップキ
ャリヤー基板７１に電気的接続を確実に維持するように
充分に撓み且つ曲ることができる。An interconnect member 76 having a flexible membrane 79 and having conductors 77 and contact pads 78 on its surface is attached to the substrate 72 at several locations (e.g. four locations) 91 in FIG. 4A by adhesive or any suitable mechanical attachment device. installed on the surface of the Interconnect member 7G is retained in this manner and would otherwise be dislodged from the entire surface of substrate 72.
It is placed somewhat loosely (not taut) on the surface. Because the interconnect member 7B is attached to the rigid substrate at a very small number of points, the interconnect member 7B is restrained from moving laterally relative to the substrate 72, but the conductor 77 is still free to attach to the substrate 72. and bends and deforms the chip 73. In other words, in the chip carrier substrate 71 the flexible conductor-carrying interconnect member 7B is physically separate from the rigid substrate 72 and the substrate 7
2 will not affect the conductor 77 and will not interfere with the electrical performance of the chip carrier substrate 71. Interconnect member 7B and conductor 77 are flexible so that they can flex and flex sufficiently to ensure electrical connection to chip carrier substrate 71, even if there is a difference in coefficient of expansion between substrate T2 and the membrane. Can be bent.

コンダクタ−担持用相互接続部材７Ｂと基板７２が物理
的に分離しているので、チップキャリヤー基板７１を設
計するに当り大きな融通性が存在する。Because the conductor-carrying interconnect 7B and substrate 72 are physically separated, there is great flexibility in designing the chip carrier substrate 71.

例えば、相互連結部材７Ｇはチップキャリヤーシステム
７１の送電線特性を最適化させるように設計することが
でき、且つ基板７２をチップキャリヤー７１の構造特性
と温度特性を最大限になるように設計することができる
。For example, the interconnect member 7G can be designed to optimize the transmission line characteristics of the chip carrier system 71, and the substrate 72 can be designed to maximize the structural and thermal characteristics of the chip carrier 71. Can be done.

第５Ａ図に示すように、各半導体チップ７３のターミナ
ル域はワイヤーボンド９３によって相互連結部材７Ｂの
導電性通路７７に電気的に接続することができ、且つ表
面膜７９に形成されている部材７Ｂ上のコンタクトパッ
ド７８（第４Ａ図）は第１図乃至第３図に示すようにリ
ード３６又はリード５Ｂの内側部分に直接取付ける。こ
のようにして、第１図の印刷凹路盤１４から第４Ａ図及
び第５Ａ図の半導体チップ７３に至る複数本の電気コン
ダクタ−の殆んど全長が可撓性の非剛性となるが、但し
ハウジングのフレーム内に含まれるリード３６．５８の
一部分３６ａ；５６ａのみは例外である。As shown in FIG. 5A, the terminal area of each semiconductor chip 73 can be electrically connected to conductive passages 77 of interconnect member 7B by wire bonds 93 and formed in surface film 79 of member 7B. The upper contact pad 78 (FIG. 4A) attaches directly to the inner portion of lead 36 or lead 5B as shown in FIGS. 1-3. In this way, almost the entire length of the plurality of electrical conductors from the printed concave roadbed 14 in FIG. 1 to the semiconductor chip 73 in FIGS. 4A and 5A becomes flexible and non-rigid. The only exception is the portion 36a; 56a of the lead 36.58 which is contained within the frame of the housing.

第５Ｂ図及び第５Ｃ図は可撓性の相互接続部材を支持す
るチップキャリヤー基板の別の実施例を示す。Figures 5B and 5C illustrate another embodiment of a chip carrier substrate supporting flexible interconnect members.

第５Ｂ図において、チップキャリヤー基板７１ｂは個々
の半導体チップ１０３を中に配置している複数個のへこ
み１０２を存するセラミック基板１０１を包含する。チ
ップ１０３は例えばチップ１０３とへこみ１０２の底部
との間に施された半田によって基板１０１に固定できる
。へこみ１０２の深さはなるべく半導体チップ１０３の
厚さよりも僅かに深い。第５Ｂ図の実施例において、チ
ップ１０３のターミナル域はもっと低置でもつと信頼性
のあるテープ自動式接着法により可撓性部材１０６のコ
ンダクタ−に接続できる。当業者が熟知しているように
、導電性バンプ１０７が相互接続ブリッジ１０８の導電
域とチップ１０３に接着されている。ブリッジ１０Ｂは
加熱加圧接着法すなわちＡｕ　Ｓｕ　　″ＥｕＬｅｃｔ
ｉｃ’接着法によって接着され、且つチップキャリヤー
のすべてのブリッジ１０８は当業者の熟知しているよう
に同時に接着することができる。また、第４Ａ図に示す
ようにリードがネット７６から窓８０に延び且つ上述の
方法と同じように直接チップチーミナル１０７に接着さ
れている。チップ１０３とコンダクタ−を相互接続部材
１０６上で整列させることにより、ワイヤーボンドによ
ってもまたテープ自動式接着法によっても、相互接続部
の長さは極限されて相互接続の抵抗を減少し且つ一層効
果的な導電通路を提供する。In FIG. 5B, chip carrier substrate 71b includes a ceramic substrate 101 having a plurality of recesses 102 in which individual semiconductor chips 103 are placed. The chip 103 can be fixed to the substrate 101, for example, by solder applied between the chip 103 and the bottom of the recess 102. The depth of the recess 102 is preferably slightly deeper than the thickness of the semiconductor chip 103. In the embodiment of FIG. 5B, the terminal area of the chip 103 can be kept lower and connected to the conductor of the flexible member 106 by a reliable tape adhesive method. As those skilled in the art are familiar with, conductive bumps 107 are bonded to the conductive areas of interconnect bridge 108 and to chip 103. The bridge 10B is bonded using a hot pressure bonding method, that is, AuSu''EuLect
ic' bonding method, and all bridges 108 of the chip carrier can be bonded simultaneously as is well known to those skilled in the art. Also, as shown in FIG. 4A, leads extend from net 76 to window 80 and are bonded directly to chip terminal 107 in the same manner as described above. By aligning the chip 103 and the conductor on the interconnect member 106, the length of the interconnect is minimized, reducing interconnect resistance and making the interconnect more efficient, whether by wire bonding or by tape automated bonding. Provides a conductive path.

上述のように、２つの非類似の材料を一緒に接着して温
度の変化を受けるとき、この２つの材料は異なった量膨
張する。このことはサンドイッチ接着を生じ、いわゆる
“パイメタリック効果”をもたらす。これはつぎに半導
体を圧縮して、例えばゲインやりニアリティの変化のよ
うな性能変化を生ずる。基板と連続用ネットを物理的に
分離しているので、チップキャリヤーシステムの設計に
大きな融通性を与える。As mentioned above, when two dissimilar materials are bonded together and subjected to a change in temperature, the two materials expand by different amounts. This results in sandwich adhesion, resulting in the so-called "pi-metallic effect". This in turn compresses the semiconductor, resulting in performance changes, such as changes in gain or linearity. The physical separation of the substrate and continuity net provides great flexibility in the design of the chip carrier system.

例えば、第５Ｃ図においてチップキャリヤー７１Ｃは金
属で作った基板ｌｌｌを有する。強力な熱伝達を必要と
する分野に金属基板が望ましい。第５Ｃ図に示すように
、金属基板は使用するとき、集積回路チップ１１３を取
付ける複数個のペデスタル１１２を形成している。この
ペデスタルは公知のパンチ成形法によって基板に形成し
、且つなるべくそれに取付けるチップと大体同一大きさ
である。For example, in FIG. 5C, chip carrier 71C has a substrate made of metal. Metal substrates are desirable for areas that require strong heat transfer. In use, the metal substrate forms a plurality of pedestals 112 on which integrated circuit chips 113 are mounted, as shown in FIG. 5C. The pedestal is formed in the substrate by conventional punch molding techniques and is preferably approximately the same size as the chip to be attached thereto.

ペデスタル１１２はチップを簡単な方法で基板上に正確
に位置決めさせる。特に、ペデスタルの土石に半田成形
品を載せ、チップをこの半田の上に載せる。つぎに半田
を水素の存在のもとに加熱して半田を溶かす。チップが
半田の表面を浮遊し、表面張力によってチップをペデス
タル上で自動的に中心に位置決めし、半田が硬化したと
きにチップがペデスタル上に正しく配置され且つ半田付
けされるようにする。この方法によって複数個のチップ
が同時にそれぞれのペデスタル上に配置され且つ半田付
けされる。また、表面張力によって半田がペデスタルか
らこぼれるのを防止する。The pedestal 112 allows the chip to be accurately positioned on the substrate in a simple manner. In particular, a solder molded product is placed on the clay of the pedestal, and the chip is placed on top of this solder. Next, the solder is heated in the presence of hydrogen to melt it. The chip floats on the surface of the solder, and surface tension automatically centers the chip on the pedestal so that when the solder hardens, the chip is properly placed on the pedestal and soldered. This method allows multiple chips to be simultaneously placed and soldered onto their respective pedestals. It also prevents solder from spilling from the pedestal due to surface tension.

半導体チップ１１３は？イヤボンド１１７やその他の連
結構造体例えばＴＡＢやＴＡＢ状装置によって可撓性膜
１１６の導電性通路に電気的に接続できる。What about semiconductor chip 113? Earbonds 117 or other connecting structures, such as TABs or TAB-like devices, can electrically connect to the conductive passages of flexible membrane 116.

コンダクタ−とチップを基板から絶縁するために金属基
板の表面に非導電性すなわち絶縁性被膜１１８を施すこ
とが通常望ましい。この被膜は公知のスパッタリング法
によっても施すことができるテフロンやその他の材料で
作る。被膜１８はマイクロウェーブを使用するメタン・
水素法によりまたはアセトン法その他の方法によって付
着されるダイヤモンドの薄層である。ダイヤモンドは理
想的な熱の伝導体すなわちコンダクタ−である。ボンド
１１７の長さを縮小するため凡そペデスタル１１２のレ
ベルに達するまで基板から相互接続部材１１６を隔てる
ために非伝導性のスペーサ１１９を設けても良い。It is usually desirable to apply a non-conductive or insulating coating 118 to the surface of the metal substrate to isolate the conductors and chips from the substrate. This coating may be made of Teflon or other materials that may also be applied by known sputtering methods. The coating 18 is made of methane using microwaves.
A thin layer of diamond deposited by hydrogen or acetone or other methods. Diamond is an ideal conductor of heat. A non-conductive spacer 119 may be provided to separate interconnect member 116 from the substrate until approximately the level of pedestal 112 is reached to reduce the length of bond 117.

本発明の好適な実施例について説明したけれども、本発
明はその他色々の形態を取ることができる。したがって
、本発明は特許請求の範囲によってのみ限定されると解
釈すべきである。Although preferred embodiments of the invention have been described, the invention may take many other forms. Accordingly, the invention should be construed as limited only by the scope of the claims.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の半導体チップキャリヤーシステムと該
システムを取付ける印刷回路盤の分解斜視図、第２図は
組立状態にある第１図のシステムの一部分の断面図、第
３図は本発明の半導体チップキャリヤーの別の実施例を
示す断面図、第４Ａ図は本発明の好適実施例のチップキ
ャリヤーシステムの分解斜視図、第４Ｂ図は第４Ａ図の
可撓性相互接続部材の拡大断面図、第５Ａ図は組立状態
にある第４Ａ図及び第４Ｂ図のチップキャリヤーの一部
分の断面図、第５Ｂ図と第５Ｃ図は本発明のチップキャ
リヤーの別の実施例を示す断面図である。 ＩＯ・・・半導体チップキャリヤーシステムｔｉ・・・
ハウジング １２・・・チップキャリヤー基板 １３・・・半導体チップ　″ １４・・・印刷回路盤　　　１５・・・フレーム１７・
・・カバー板　　　　２１．２２．２３．２４・・・側
壁２６・・・上部へこみ　　　２７・・・下部へこみ２
９・・・たな　　　　　　３０・・・基板３１・・・コ
ンダクタ−３２・・・コンタクトパッド３５・・・表面
　　　　　　３６・・・リード　　　　−３７・・・コ
ンタクトパッド ３６・・・接合剤　　　　　３９・・・半田付は部４０
・・・防護性コンパウンド ４１・・・接着剤　　　　　５６・・・リード６１・・
・キャップ ７１・・・チップキャリヤー基板 、７２・・・剛性基板　　　　７３・・・半導体チップ
７Ｂ・・・相互接続部材　　７７・・・コンダクタ−７
９・・・プラスチック膜　８０・・・窓８１．８２．８
３・・・誘電層　　８４．８６・・・誘電性箔層８７、
ｌ１８．８９・・・コンダクタ−１０２・・・へこみ　
　　　１０３・・・半導体チップ１０Ｂ・・・可撓性部
材　　１０７・・・チップ端子１０ｇ・・・ブリッジ　
　　ｌｌｌ・・・金属基板１１２・・・ヘテスタル　　
１１３・・・半導体チップ１１６・・・可撓性膜　　　
１１７・・・ワイヤーボンドｌ１８・・・被１１１＋　
　　　　　１１９・・・スペーサー１２２・・・基板　
　　　　１４１・・・半導体チップ１４２・・・基板　
　　　　１４３・・・スプリング部材１４５．１４６・
・・コンタクト板 １４９・・・圧カー板1 is an exploded perspective view of a semiconductor chip carrier system of the present invention and a printed circuit board on which the system is mounted; FIG. 2 is a cross-sectional view of a portion of the system of FIG. 1 in an assembled state; and FIG. 3 is a cross-sectional view of a portion of the system of FIG. FIG. 4A is an exploded perspective view of a chip carrier system according to a preferred embodiment of the present invention; FIG. 4B is an enlarged cross-sectional view of the flexible interconnection member of FIG. 4A; , FIG. 5A is a cross-sectional view of a portion of the chip carrier of FIGS. 4A and 4B in an assembled state, and FIGS. 5B and 5C are cross-sectional views of another embodiment of the chip carrier of the present invention. IO...Semiconductor chip carrier system ti...
Housing 12...Chip carrier board 13...Semiconductor chip'' 14...Printed circuit board 15...Frame 17.
...Cover plate 21.22.23.24...Side wall 26...Top dent 27...Bottom dent 2
9...Top 30...Substrate 31...Conductor 32...Contact pad 35...Surface 36...Lead -37...Contact pad 36...Binding agent 39... Soldering part 40
...Protective compound 41...Adhesive 56...Lead 61...
- Cap 71...Chip carrier board, 72...Rigid substrate 73...Semiconductor chip 7B...Interconnection member 77...Conductor-7
9...Plastic membrane 80...Window 81.82.8
3...Dielectric layer 84.86...Dielectric foil layer 87,
l18.89...Conductor-102...Dent
103... Semiconductor chip 10B... Flexible member 107... Chip terminal 10g... Bridge
lll... Metal substrate 112... Hetestal
113...Semiconductor chip 116...Flexible film
117...Wire bond l18...Target 111+
119...Spacer 122...Substrate
141...Semiconductor chip 142...Substrate
143... Spring member 145.146.
...Contact plate 149...Pressure car plate

Claims (10)

【特許請求の範囲】[Claims] （１）マルチブルチップキャリヤー基板（１２）に使用
する半導体チップキャリヤーシステム（１０）において
；基板受入れ域（２６）を備えた第１主要面と第２主要
面と該両面を連続する壁（２１、２２、２３、２４）と
を有する大体矩形のハウジング（１１）と； 前記ハウジング（１１）の１個以上の壁（２１、２２、
２３、２４）を貫通して延びる複数本の電気ターミナル
（３６）であって、前記壁に埋め込んだ中央部分（３６
ａ）と前記ハウジング（１１）の外側を延びて外部回路
に電気的に接続されるようになった外側の柔軟性部分（
３６ｃ）と前記マルチブルチップキャリヤー基板（１２
）の半導体チップ（１３）と電気的に係合したコンタク
トパッド（３２）に電気的に接続されるようになってい
る内側の柔軟部分（３６ｂ）とを有する前記電気ターミ
ナル（３６）と； 前記基板（１２）が前記基板受入れ域（２６）に配置し
且つここに固定され、前記基板（１２）がその上に複数
個の半導体チップ（１３）を取付けていることと；前記
半導体チップ（１３）を環境の害から保護するために設
けたカバー装置（１７）と； 前記基板（１２）が温度変化に応じて膨張収縮するとき
前記内側柔軟部分（３６ｂ）がそれに応じて移動し、か
くして前記基板（１２）とターミナル（３６）の間に発
生する有害な応力を排除することができるよう前記ター
ミナル（３６）の内側柔軟部分（３６ｂ）が前記コンタ
クトパッド（３２）に接続されていること；を包含する
半導体チップキャリヤーシステム。(1) In a semiconductor chip carrier system (10) used for a multi-chip carrier substrate (12); a first major surface and a second major surface provided with a substrate receiving area (26) and a wall (21 , 22, 23, 24); and one or more walls (21, 22, 24) of said housing (11);
a plurality of electrical terminals (36) extending through the walls (23, 24), the central portion (36) being recessed in said wall;
a) and an outer flexible portion extending outside said housing (11) and adapted to be electrically connected to an external circuit;
36c) and the multiple chip carrier substrate (12
said electrical terminal (36) having an inner flexible portion (36b) adapted to be electrically connected to a contact pad (32) electrically engaged with a semiconductor chip (13) of ); a substrate (12) is disposed in and fixed to said substrate receiving area (26), said substrate (12) having a plurality of semiconductor chips (13) mounted thereon; ) a covering device (17) provided for protecting the substrate (17) from environmental hazards; when the substrate (12) expands and contracts in response to temperature changes, the inner flexible portion (36b) moves accordingly, thus an inner flexible portion (36b) of said terminal (36) is connected to said contact pad (32) so as to be able to eliminate harmful stresses occurring between the substrate (12) and the terminal (36); A semiconductor chip carrier system that includes: （２）前記カバー装置（１７）が前記ハウジング（１２
）の第２主要面のカバー受入れ域（２７）に挿入されて
固定されるカバー板（１７）を包含する特許請求の範囲
第１項記載のシステム。(2) The cover device (17) is connected to the housing (12).
2. System according to claim 1, comprising a cover plate (17) inserted and fixed in the cover receiving area (27) of the second major side of the holder. （３）前記基板（１２）とカバー板（１７）との間に設
けたへこみ（１８）が半導体チップ（１３）を環境の害
と湿気から防護するための防護用密封材料を有する特許
請求の範囲第２項記載のシステム。(3) The recess (18) provided between the substrate (12) and the cover plate (17) has a protective sealing material for protecting the semiconductor chip (13) from environmental hazards and moisture. The system described in Scope No. 2. （４）前記カバー装置が各々の半導体チップ（１３）の
上にのせられて密封される複数個のばらばらのカバー部
材（６１）を包含する特許請求の範囲第１項記載のシス
テム。4. The system of claim 1, wherein said cover device includes a plurality of separate cover members (61) placed over and sealed over each semiconductor chip (13). （５）前記端子（３６）が前記基板（１２）のコンタク
トパッドに直接付着されている特許請求の範囲第１項記
載のシステム。5. The system of claim 1, wherein said terminal (36) is attached directly to a contact pad of said substrate (12). （６）コンダクター（７７）を有する可撓性回路（７９
）が複数個所で基板（１２）に機械的に固定され、前記
回路（７９）と基板（１２）に互いに独立して温度変化
を受けさせ乍ら、基板（１２）に対する回路（７９）の
横方向の移動を制限する特許請求の範囲第１項記載のシ
ステム。(6) Flexible circuit (79) with conductor (77)
) is mechanically fixed to the substrate (12) at a plurality of locations, and while the circuit (79) and the substrate (12) are subjected to temperature changes independently of each other, the lateral side of the circuit (79) with respect to the substrate (12) is 2. A system as claimed in claim 1 for limiting directional movement. （７）コンタクトパッド（７８）を可撓性回路（７９）
のコンダクター（７７）の端部に設け、前記リード（３
６）の内側部分（３６ｂ）がコンタクトパッド（７９）
に接触し且つ前記コンダクター（７７）をリード（３６
）に電気的に接続する特許請求の範囲第６項記載のシス
テム。(7) Connect the contact pad (78) to the flexible circuit (79)
The conductor (77) is provided at the end of the lead (3).
The inner part (36b) of 6) is the contact pad (79)
and leads the conductor (77) to the lead (36).
7. The system of claim 6, wherein the system is electrically connected to a （８）前記基板（１２）がそれぞれの半導体チップ（１
１３）を支持するための複数個のペデスタル（１１２）
を有する金属基板（１１１）を包含する特許請求の範囲
第６項記載のシステム。(8) The substrate (12) is connected to each semiconductor chip (1).
a plurality of pedestals (112) for supporting 13);
7. The system of claim 6, comprising a metal substrate (111) having a metal substrate (111). （９）前記金属基板（１１１）の表面に非導電性被膜（
１１８）が設けられている特許請求の範囲第８項記載の
システム。(9) A non-conductive coating (
118). The system according to claim 8, wherein: （１０）前記可撓性回路（１１６）が非導電性被膜（１
１８）に設けられ、前記可撓性回路（１１６）がこれを
前記金属基板（１１１）から隔置するための非導電性ス
ペーサ装置（１１９）を有する特許請求の範囲第９項記
載のシステム。(10) The flexible circuit (116) has a non-conductive coating (1
10. The system of claim 9, wherein said flexible circuit (116) has a non-conductive spacer device (119) provided at said flexible circuit (116) for spacing it from said metal substrate (111).
JP62256144A 1986-10-09 1987-10-09 Semiconductor chip carrier device Expired - Lifetime JPH0834278B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US91697486A 1986-10-09 1986-10-09
US916974 1986-10-09

Publications (2)

Publication Number Publication Date
JPH01102952A true JPH01102952A (en) 1989-04-20
JPH0834278B2 JPH0834278B2 (en) 1996-03-29

Family

ID=25438169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62256144A Expired - Lifetime JPH0834278B2 (en) 1986-10-09 1987-10-09 Semiconductor chip carrier device

Country Status (2)

Country Link
JP (1) JPH0834278B2 (en)
GB (1) GB2196178B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007141667A (en) * 2005-11-18 2007-06-07 Furukawa Electric Co Ltd:The Method for connecting terminals on base plates

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW212261B (en) * 1992-03-09 1993-09-01 Matsushita Electric Ind Co Ltd Electronic circuit device and manufacturing method
EP0576735B1 (en) * 1992-06-29 1997-09-10 Océ-Nederland B.V. Mounting structure for electro-optical devices
US5824950A (en) * 1994-03-11 1998-10-20 The Panda Project Low profile semiconductor die carrier
US5821457A (en) * 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
US6339191B1 (en) 1994-03-11 2002-01-15 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier
US6016256A (en) 1997-11-14 2000-01-18 The Panda Project Multi-chip module having interconnect dies
US6141869A (en) * 1998-10-26 2000-11-07 Silicon Bandwidth, Inc. Apparatus for and method of manufacturing a semiconductor die carrier
EP1324386B1 (en) * 2001-12-24 2011-06-15 ABB Research Ltd. Semiconductor module and method of manufacturing a semiconductor module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4976066A (en) * 1972-11-27 1974-07-23
JPS5875863A (en) * 1981-10-13 1983-05-07 フエアチヤイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Hybrid circuit module and method of producing same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
DE3124692A1 (en) * 1981-06-24 1983-01-13 Robert Bosch Gmbh, 7000 Stuttgart "SEMICONDUCTOR RECTIFIER"
DE3241509A1 (en) * 1982-11-10 1984-05-10 Brown, Boveri & Cie Ag, 6800 Mannheim POWER TRANSISTOR MODULE

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4976066A (en) * 1972-11-27 1974-07-23
JPS5875863A (en) * 1981-10-13 1983-05-07 フエアチヤイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Hybrid circuit module and method of producing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007141667A (en) * 2005-11-18 2007-06-07 Furukawa Electric Co Ltd:The Method for connecting terminals on base plates

Also Published As

Publication number Publication date
GB2196178B (en) 1990-04-11
JPH0834278B2 (en) 1996-03-29
GB8721203D0 (en) 1987-10-14
GB2196178A (en) 1988-04-20

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