JPH01101020A - Voltage signal input multiplexer circuit - Google Patents

Abstract

PURPOSE:To detect the abnormalities of an analog multiplexer, a decoder, a channel selecting digital signal line, etc., with a high probability by AD- converting a certain voltage signal through two different analog multiplexers, making the two AD-converting values into output signals, and comparing them. CONSTITUTION:Analog multiplexers 11X and 11Y are connected like in parallel, they are doubled, four voltage signals V1-V4 are received by the different two multiplexers 11X and 11Y, the signals are AD-converted through an amplifier 12 by an AD converter 13, respectively, and they are fetched in a CPU system 14. Here, the obtained two AD-converting values are compared, and whether the difference stays within a certain range or not is checked. When the difference is deviated from the range from the result, that any abnormality is generated can be decided. Consequently, a reliability as a system can be increased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an analog input device suitable for diagnosing an analog multiplexer circuit into which a voltage signal is input, and particularly relates to an improvement of the manually operated multiplexer circuit. .

[Conventional technology]

In the conventional technology, as shown in FIG.
It consists of an AD converter 13 for digital) conversion, a CPU system 14 consisting of a microprocessor (CPU), memory such as ROM, RAM, etc., and a decoder 16a. A common method is to perform AD conversion on the voltages of each channel CH1 to CH4, and to import the AD converted values into the CPU. In FIG. 2, 21 is a pass line, 23 is a channel selection digital signal line, symbols A and B are channel address terminals of the analog multiplexer 11, and similarly symbol E is an enable terminal.

[Problem that the invention seeks to solve]

However, in such conventional methods, even if an abnormality (failure) as shown in item 0 or item 0 below occurs, the CPU side does not notice that it is an abnormal AD conversion value and processes it as a normal value. There was a problem in that the reliability of the system was low.

■ Due to an abnormality in the path line 21 from the CPU system 14 to the decoder 16a, another channel (CHI to CH4
) will be selected.

(2) An abnormality in the decoder 16a or the channel selection digital signal line 23 causes a different channel to be selected.

■Another channel is selected due to an abnormality in the analog multiplexer 11. Or, even if the correct channel is selected, a different voltage than the input will be output.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention connects analog multiplexers in parallel to make them redundant, inputs the same voltage signal to the two analog multiplexers, and compares the output signals. A voltage signal input multiplexer circuit in an analog input device in which it is difficult to diagnose a multiplexer circuit, characterized in that input connections are made so that selection digital code values given to the two analog multiplexers are different when selecting an analog input signal. It is.

[Effect]

In the present invention, one voltage signal is AD-converted through two different analog multiplexers, and the two AD-converted values are compared as output signals, and if the difference is within a certain range, then It is considered normal, and if it is successful, it is considered abnormal. Therefore, by devising the addresses of each channel of two analog multiplexers that input the same voltage signal using FMECA, it is possible to detect abnormalities in the analog multiplexer, decoder, channel selection digital signal line, etc. with a high probability. become.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on embodiments shown in the drawings and planes.

FIG. 1 is a block diagram showing an embodiment in which a voltage/signal input multiplexer circuit according to the present invention is applied to an analog input system of a CPU system. In this embodiment, an analog multiplexer (hereinafter referred to as multiplexer)
11X, 11 pieces are connected in parallel to make it redundant, 4
The two voltage signals v1 to v4 are received by two different multiplexers 11x and 11y, passed through the amplifier 12, and then AD converted by the AD converter 13 for each of them and taken into the CPU system 14. By comparing the two AD converted values, It is used to diagnose differential color analog multiplexer systems.

At this time, a channel selection data input and a latch strobe signal are input from the CPU system 14 to each terminal of the latch circuit 15 through the pass line 21 and the latch loop signal line 22, respectively.
Among the outputs of this latch circuit 15, outputs Ql and Qt are sent to the multiplexer 11 as channel selection digital code signals.
It is input to each channel address terminal A, H of x and 11y. The outputs Qs+Q4 and Qs are input to the data input terminals AD, BD and enable terminal ED of the decoder 16, and the output Qs of the decoder 16 is input to the enable terminal gs of the multiplexer 11y, and the output Q4 is input to the enable terminal gs of the multiplexer 11. The terminals Es and K are respectively input. In this case, one voltage signal V, ~v4 as an analog input signal is selected through two different multiplexers 11x and 11y, AD converted by the AD converter 13, and the two AD converted values are sent to the CPU. It is intended to be taken into the system 14. In FIG. 1, the same reference numerals as in FIG. 2 indicate the same or corresponding parts. In addition, the outputs Q1 to Q5 of the latch circuit 15 and each multiplexer 11x, 11y
The voltage signal V! selected by V! An example of the correspondence relationship with v4 is shown in Table 1.

Therefore, when diagnosing an analog multiplexer circuit, for example, for the voltage signal Vl, first select channel CH1 of the multiplexer 11x, and then select the channel CH1 of the multiplexer 11x,
3 performs AD conversion, and then multiplexer 11! The channel CH4 is selected, AD conversion is performed, and the result is taken into the CPU system 14. And the two A obtained here
By comparing the D-converted values and checking whether the difference is within a certain range, if the difference is out of range, it can be determined that some abnormality has occurred.

In this embodiment, voltage signal v1 is input to channel CHI in multiplexer 11x, but is input to channel CH4 instead of channel CH1 in multiplexer 11y. Similarly, for the voltage signal V:~v4, the multiplexers 11x and 11y do not have the same channel, but are shifted by one channel. therefore,
By making the channels of the two multiplexers 11x and 11y different when selecting the voltage signals v and %V4, the path line 21 from the CPU system 14 to the decoder 16 shown in the above-mentioned conventional section 0 to 0, and the decoder 16 or the channel selection digital signal line 23 can be detected at a high rate.

That is, the conventional detection mechanism for each of the above-mentioned 0 to 0 terms will be explained using examples. First of all, the above 0 weight■
Due to an abnormality in the path line 21 from the CPU system 14 to the decoder 16, the
The case where 2) is selected is as follows. Now, the output Q1 of the latch circuit (see Table 1) is r OJ (LO
Suppose that it is stuck on the W side). When AD converting the voltage signal vl in this state, multiplexer 1
In 1x, channel CH1 is selected normally (Table 1)
. However, in the 11 multiplexers, since the output Q1 of the latch circuit 15 is "0", channel CH3 is selected instead of channel CH4. Therefore, AD conversion of the voltage signal v4 is performed, and at the time of comparison check, the AD conversion values of the voltage signals v1 and v4 are compared. As a result, these 7 layers and v4
If the difference is large, it can be determined that there is an abnormality. Furthermore, abnormality can be similarly detected for the outputs Q2 to Q5 of the latch circuit 15.

On the other hand, if another channel υ is selected due to the abnormality of the multiplexer in term 0, the channel selection digital signal line 23 is normal, and the multiplexer 11
It is assumed that some abnormality has occurred in x″′! or 11y. At this time, the multiplexer 1
Since 1X cannot output a normal voltage, the abnormality can be detected by a comparison check similar to that described above.

〔Effect of the invention〕

As explained above, according to the present invention, multiplexers are connected in parallel to make them redundant, and the output signals of two multiplexers to which the same voltage signal is input are compared, and based on the comparison result, The multiplexer circuit system can be diagnosed and the reliability of the system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the multiplexer circuit according to the present invention applied to an analog input system of a CPU system, and FIG. 2 is a block diagram showing a conventional example. 11x, 11y--... analog multiplexer,
13・ψ fist・AD converter, 14#・war・CPU system, 15... latch circuit, 16... de;-da.

Claims (1)

[Claims] Duplicate by connecting analog multiplexers in parallel,
In an analog input device that diagnoses an analog multiplexer circuit by inputting the same voltage signal to these two analog multiplexers and comparing their output signals, when selecting an analog input signal,
A voltage signal input multiplexer circuit characterized in that input connections are made so that selected digital code values given to two analog multiplexers are different from each other.