JP7884279B2 - Gaming machine - Google Patents

Description

This invention relates to a gaming machine.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters, for example, a ball entry section in the game area, the game ball is dispensed back into the tray storage section from, for example, a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section (see, for example, Patent Document 1).

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

Japanese Patent Publication No. 2009-261415

In the case of gaming machines like those exemplified above, it is necessary for the gaming machines to be managed appropriately, and there is still room for improvement in this regard.

This invention has been made in view of the circumstances illustrated above, and aims to provide a gaming machine that can be suitably managed .

To solve the above problems, the invention described in claim 1 includes a history storage execution means that stores in a history storage means the history information of a game corresponding to a predetermined event that occurs when a game is played,
Information deriving means for deriving behavioral information corresponding to the result of the game using the history information stored in the history storage means,
A configuration information storage means for storing the configuration information derived by the information derivation means,
A manner information display control means that controls the display of manner information corresponding to the manner information stored in the manner information storage means to be displayed by the information display means,
A predetermined corresponding display control means that controls the information display means to ensure that a predetermined corresponding display is performed before a new display corresponding to the aspect information is initiated, based on the occurrence of a predetermined display trigger.
A setting means for setting a value corresponding to the player's advantage,
A condition generating means that creates a condition in which the setting value can be set by the setting means,
Equipped with,
The aforementioned aspect information storage means includes a plurality of specific storage areas that enable the storage of each of the plurality of aspect information,
The aspect information display control means controls the information display means to sequentially execute displays corresponding to each of the multiple aspect information stored in the multiple specific storage areas according to a predetermined display order, and when the information display means is to be made to perform a display corresponding to the aspect information after the predetermined corresponding display has been performed, it starts with the display corresponding to the aspect information corresponding to the first order in the predetermined display order.
The information derivation means derives the aspect information using the historical information during a predetermined advantageous period.
This gaming machine is equipped with control means for performing various processes,
The control means is
An in-area processing execution means that executes in-area processing, which is processing that uses a program stored in a predetermined address range storage area of a program storage means,
An out-of-bounds processing execution means for executing out-of-bounds processing, which is processing that utilizes a program stored in a storage area of an address range outside the predetermined address range of the program storage means,
Equipped with,
This gaming machine is
When processing within the aforementioned region is performed, information can be written to and read from the corresponding storage area within the region, while when processing outside the aforementioned region is performed, information can be read but information cannot be written to the corresponding storage area within the region.
When the aforementioned out-of-area processing is performed, information can be written to and read from the out-of-area corresponding storage area, while when the aforementioned in-area processing is performed, information can be read but information cannot be written to the out-of-area corresponding storage area,
Equipped with,
The domain-based processing execution means is characterized by comprising means capable of executing a process as a domain-based process that can determine whether or not the setting value set as the target for use is normal .

According to the present invention, it becomes possible to suitably manage gaming machines .

This is a perspective view showing a pachinko machine in the first embodiment. This is a perspective view showing the main components of a pachinko machine in disassembled form. This is a front view showing the configuration of the game board. This is an explanatory diagram illustrating the configuration for discharging game balls that have flowed down the game area. This is a front view of the main control unit. This is a block diagram showing the electrical configuration of a pachinko machine. This is an explanatory diagram illustrating the functions of various counters used in lotteries and other similar processes. This is an explanatory diagram illustrating the various tables stored in the main ROM. This is a flowchart showing the main processes executed on the primary CPU. This flowchart shows the configuration value update process executed by the main CPU. This flowchart shows the timer interrupt processing performed by the main CPU. This is a flowchart showing the special control processing performed by the main CPU. This flowchart shows the special feature variation start process executed by the main CPU. This is an explanatory diagram illustrating a configuration in which the detection results of the ball entry detection sensor are input to the main CPU. This flowchart shows the ball entry detection process executed by the main CPU. This is a block diagram illustrating the electrical configuration of the dispensing control device and the various devices that communicate with the dispensing control device. This flowchart shows the timer interrupt processing performed by the payout-side CPU. This is a block diagram illustrating the electrical configuration of the management IC. This is an explanatory diagram illustrating the configuration of the input ports on the management interface. This is an explanatory diagram illustrating the configuration of the memory used for correspondence relationships. This is an explanatory diagram illustrating the configuration of the history memory. The recognition process executed by the main CPU is shown in the flowchart. This log lists the management processes executed by the management CPU. (a) to (d) are time charts showing how information regarding the correspondence between the first to fifteenth buffers and the types of signals is stored in the correspondence memory. This is a flowchart showing the management output processing performed by the main CPU. This section analyzes the history setting process executed by the management CPU. (a) to (e) are time charts showing how history information is stored in the history memory. This flowchart shows the output process of the setting value update signal executed by the main CPU. This flowchart shows the configuration update recognition process executed by the management CPU. This flowchart outlines the display output processing performed by the management CPU. This flowchart shows the display processing performed by the management CPU. (a) A flowchart showing the data output process executed by the main CPU, and (b) A flowchart showing the external output process executed by the management CPU. This is an explanatory diagram illustrating the various tables stored in the main ROM in the second embodiment. This is an explanatory diagram illustrating the configuration of a separate storage memory in the third embodiment. This flowchart shows the configuration update recognition process executed by the management CPU. This flowchart shows the recurring change monitoring process executed by the management CPU. This flowchart shows the recurring change monitoring process executed by the main CPU in the fourth embodiment. This is a flowchart showing the configuration update recognition process executed by the management CPU in the fifth embodiment. This is an explanatory diagram illustrating the configuration of the history memory in the sixth embodiment. This section analyzes the history setting process executed by the management CPU. This flowchart shows the configuration update recognition process executed by the management CPU. This is an explanatory diagram illustrating the configuration of the history memory in the seventh embodiment. This flowchart shows the configuration update recognition process executed by the management CPU. This is an explanatory diagram illustrating the configuration of the history memory in the eighth embodiment. This flowchart shows the configuration update recognition process executed by the management CPU. This section analyzes the history setting process executed by the management CPU. This flowchart outlines the display output processing performed by the management CPU. This is an explanatory diagram illustrating the configuration of the input ports of the management-side I/F in the ninth embodiment. The recognition process executed by the main CPU is shown in the flowchart. This log lists the management processes executed by the management CPU. (a) to (h) are time charts showing how information regarding the correspondence between the 1st to 12th buffers and the types of signals is stored in the correspondence memory. This is a block diagram illustrating the configuration of the signal path for transmitting the detection results of each ball entry detection sensor to the main CPU and the management IC in the tenth embodiment. This is a front view of the main control device in the eleventh embodiment. This is a block diagram illustrating the electrical configuration for displaying various information in the first to fourth notification display devices based on the control of the MPU. This flowchart shows the display processing performed by the management CPU. This flowchart shows the configuration value update process executed by the main CPU. (a) This is an explanatory diagram for illustrating the display modes of the first to fourth notification display devices when the results of the game history management are displayed, and (b) This is an explanatory diagram for illustrating the display modes of the first to fourth notification display devices when the settings of the pachinko machine are changed. (a) to (h) are time charts showing the state in which the first to fourth notification display devices are displayed. (a) is an explanatory diagram illustrating the configuration of the first notification display device in the twelfth embodiment, and (b) is an explanatory diagram illustrating the configuration of the second notification display device. This is an explanatory diagram illustrating the display contents of the first and second notification display devices when displaying the results of game history management on the first to fourth notification display devices, and when indicating that the settings of the pachinko machine can be changed. This flowchart shows the configuration value update process executed by the main CPU. This is an explanatory diagram illustrating the configuration of the abnormality display area in the 13th embodiment. This flowchart shows the abnormal setting process executed by the main CPU. This flowchart shows the error display process executed by the main CPU. This is a flowchart showing the management output processing performed by the main CPU in the 14th embodiment. This flowchart shows the main processing performed by the primary CPU in a different configuration. This is an explanatory diagram illustrating the setting configuration of the program and data of the main ROM in the 15th embodiment. This is an explanatory diagram illustrating the configuration of each area in the main RAM. This flowchart shows the timer interrupt processing performed by the main CPU. This is a flowchart showing the management processes executed on the primary CPU. This log shows the management execution processes performed on the primary CPU. This is an explanatory diagram illustrating the various areas of the work area used for non-specific control, which is used to manage game history. This flowchart shows the check process executed on the primary CPU. This flowchart shows the normal ball entry management process executed by the main CPU. This flowchart shows the result calculation process performed by the primary CPU. This flowchart shows the display processing performed by the primary CPU. This is a flowchart showing the management process executed by the main CPU in the 16th embodiment. This is a flowchart showing the management execution process performed by the main CPU in the 17th embodiment. This is a flowchart showing the management execution process performed by the main CPU in the 18th embodiment. This is a flowchart showing the management execution process performed by the main CPU in the 19th embodiment. This flowchart shows the management process executed by the main CPU in the 20th embodiment. This logs the management execution processes performed on the primary CPU. This is an explanatory diagram illustrating the electrical configuration in the 21st embodiment. This is a flowchart showing the main processing performed by the main CPU in the 22nd embodiment. This flowchart shows the configuration value update process executed by the main CPU. This flowchart shows the timer interrupt processing performed by the main CPU. This flowchart shows the configuration verification process executed on the main CPU. This flowchart shows the RAM monitoring process executed by the primary CPU. This flowchart shows the main processing performed by the primary CPU in a different configuration. This flowchart shows the configuration value update process executed by the main CPU in a different configuration. This is a flowchart showing the main processing performed by the main CPU in the 23rd embodiment. This is a flowchart showing the RAM monitoring process executed by the main CPU in the 24th embodiment. This is a flowchart showing the RAM monitoring process executed by the main CPU in the 25th embodiment. This logs the management execution processes performed on the primary CPU. This flowchart shows the separate monitoring process executed on the primary CPU. This flowchart shows the management process executed by the main CPU in the 26th embodiment. This flowchart shows the management process executed by the main CPU in the 27th embodiment. This flowchart shows the management process executed by the main CPU in the 28th embodiment. This is a flowchart showing the management process executed by the main CPU in the 29th embodiment. This is a flowchart showing the main processing performed by the main CPU in the 30th embodiment. This flowchart shows the power outage information storage process executed by the main CPU. (a) A block diagram illustrating the configuration of the MPU, and (b) A time chart showing the output of the reset signal by the reset signal output unit. This flowchart shows the timer interrupt processing performed by the main CPU. This flowchart shows the configuration monitoring process executed by the primary CPU. This is a flowchart showing the management processes executed on the primary CPU. This logs the management execution processes performed on the primary CPU. This flowchart shows the separate monitoring process executed on the primary CPU. This is a flowchart showing the main processing performed by the main CPU in the 31st embodiment. This flowchart shows the error clearing process executed by the primary CPU. This flowchart shows the clearing process for non-specific control that is executed on the main CPU. This is a flowchart showing the power outage information storage process executed by the main CPU in the 32nd embodiment. This flowchart shows the checksum monitoring process performed on the primary CPU. This flowchart shows the clearing process for non-specific control that is executed on the main CPU. This is a flowchart showing the main processing performed by the main CPU in the 33rd embodiment. This flowchart shows the configuration verification process executed on the main CPU. This flowchart shows the configuration value update process executed by the main CPU. This flowchart shows the first timer interrupt processing performed by the main CPU. This flowchart shows the configuration monitoring process executed by the primary CPU. This is a block diagram illustrating the configuration for controlling various display circuits using the main CPU. (a) This is an explanatory diagram for illustrating the various buffers provided in the work area for specific control, and (b) This is an explanatory diagram for illustrating the various storage areas provided in the work area for non-specific control. This is an explanatory diagram illustrating the electrical configuration of the display IC. (a) to (g) are time charts showing how type data and display data are transmitted from the main CPU to the display IC, and how the display data transmitted from the display IC is received by the first display circuit or the second display circuit. This flowchart shows the second timer interrupt processing performed by the main CPU. (a) This is an explanatory diagram for explaining the display content of the first to fourth notification display devices when the setting value is being updated, and (b) This is an explanatory diagram for explaining the display content of the first to fourth notification display devices when the setting value is being confirmed. This is a flowchart showing the setting value update process executed by the main CPU in the 34th embodiment. This is an explanatory diagram illustrating the electrical configuration of the calculation result storage area in the 35th embodiment. (a) to (d) are explanatory diagrams for explaining the display contents of the first to fourth notification display devices. (a) to (c) are explanatory diagrams for explaining the display contents of the first to fourth notification display devices. (a) to (e) are time charts showing how the base values for various areas are broadcast on the first to fourth notification display devices. This flowchart shows the result calculation process performed by the primary CPU. This flowchart shows the display processing performed by the main CPU. This is a flowchart showing the main processes executed on the primary CPU. This flowchart shows the first timer interrupt processing performed by the main CPU. This flowchart shows the second timer interrupt processing performed by the main CPU. This flowchart shows the normal configuration process executed by the main CPU. This flowchart shows the configuration verification process executed on the main CPU. This flowchart shows the configuration value update process executed by the main CPU. (a) to (f) are time charts to explain the display contents of the first to fourth notification display devices when the supply of operating power to the main CPU is started. This is a flowchart showing the main processing performed by the main CPU in the 36th embodiment. This is a flowchart showing the main processing performed by the main CPU in the 37th embodiment. This is a flowchart showing the normal setting process executed by the main CPU in the 38th embodiment. (a) to (d) are explanatory diagrams illustrating the setting-compatible storage area provided in the main ROM in the 39th embodiment. This flowchart shows the process of reading the success/failure table executed by the main CPU. This flowchart shows the setting process for the fifth display data buffer during a configuration update performed by the main CPU. (a) to (c) are explanatory diagrams illustrating the setting-compatible storage area provided in the main ROM in the 40th embodiment. (a) An explanatory diagram for illustrating various display units provided in an area visible from the front of the pachinko machine through a window panel in the 41st embodiment, and (b) An explanatory diagram for illustrating the display content of the round display unit. This is a flowchart showing the main processing performed by the main CPU in the 42nd embodiment. This flowchart shows the first timer interrupt processing performed by the main CPU. This is a flowchart showing the result calculation process executed by the main CPU in the 43rd embodiment. This flowchart shows the display processing performed by the main CPU. (a) to (g) are time charts showing how the base values for various areas are reported on the first to fourth notification display devices. (a) to (g) are time charts showing how the base values of various areas are reported by the first to fourth notification display devices in the 44th embodiment. This flowchart shows the main processing performed by the main CPU in the 45th embodiment. This is an explanatory diagram illustrating the contents of the memory area for set values provided in the work area for specific control. This flowchart shows the configuration verification process executed on the main CPU. This flowchart shows the setting process for the fifth display data buffer during configuration verification, which is performed by the main CPU. This flowchart shows the configuration value update process executed by the main CPU. This flowchart shows the setting process for the fifth display data buffer during a configuration update performed by the main CPU. This diagram explains the process executed in the main process when power is restored after a power outage occurs while a setting value update process or setting confirmation process is running. (a) to (e) are time charts showing the completion timing of the setting value update process and the setting confirmation process in relation to the operation status of the setting key insertion part. This flowchart shows the main processing performed by the main CPU in the 46th embodiment. This diagram explains the process executed in the main process when power is restored after a power outage occurs while a setting value update process or setting confirmation process is running. This is an explanatory diagram illustrating the content of the processing performed in the main process when the power supply is resumed after a power outage is executed while the setting value update process or setting confirmation process is being executed in the 47th embodiment. This is an explanatory diagram illustrating the content of the processing performed in the main process when the power supply is resumed after a power outage is executed while the setting value update process or setting confirmation process is being executed in the 48th embodiment.

<First Embodiment>
The following describes in detail a first embodiment of a pachinko gaming machine (hereinafter referred to as "pachinko machine"), a type of gaming machine, based on the drawings. Figure 1 is a perspective view of the pachinko machine 10, and Figure 2 is a perspective view showing the main components of the pachinko machine 10 in an exploded view. For convenience, the components within the gaming area PA of the pachinko machine 10 are omitted in Figure 2.

As shown in Figure 1, the pachinko machine 10 comprises an outer frame 11 that forms the outer shell of the pachinko machine 10, and a game machine body 12 that is rotatably mounted forward on the outer frame 11. The outer frame 11 is constructed by connecting wooden boards on all four sides and has a rectangular frame shape. The pachinko machine 10 is installed in a gaming hall by attaching and fixing the outer frame 11 to the island equipment. Note that the outer frame 11 is not an essential component of the pachinko machine 10; the outer frame 11 may be installed on the island equipment of the gaming hall.

As shown in Figure 2, the gaming machine body 12 comprises an inner frame 13, a front door frame 14 positioned in front of the inner frame 13, and a back pack unit 15 positioned behind the inner frame 13. The inner frame 13 of the gaming machine body 12 is rotatably supported by the outer frame 11. Specifically, in a front view, the inner frame 13 is rotatable forward, with the left side being the base end and the right side the tip end.

The front door frame 14 is rotatably supported within the inner frame 13, allowing it to rotate forward with the left side as the base end and the right side as the leading end when viewed from the front. Furthermore, the rear pack unit 15 is rotatably supported within the inner frame 13, allowing it to rotate backward with the left side as the base end and the right side as the leading end when viewed from the front.

Furthermore, the gaming machine body 12 is equipped with a locking device at its rotating tip, which has the function of locking the gaming machine body 12 to the outer frame 11 in an inoperable state, and also locking the front door frame 14 to the inner frame 13 in an inoperable state. These locking states can be released by using an unlocking key to unlock the cylinder lock 17, which is exposed on the front of the pachinko machine 10.

Next, the configuration of the front side of the gaming machine body 12 will be described.

The inner frame 13 is mainly composed of a resin base 21 whose outer shape is almost identical to that of the outer frame 11. A roughly oval-shaped window opening 23 is formed in the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front of the game board 24 is exposed to the front side of the inner frame 13 through the window opening 23 of the resin base 21.

Here, the configuration of the game board 24 will be explained based on Figure 3. Figure 3 is a front view of the game board 24.

The game board 24 has an inner rail section 25 and an outer rail section 26 attached to it, partitioning a portion of the outer edge of the game area PA. These inner and outer rail sections 25 and 26 constitute a guide rail, which serves as a guidance means. Game balls launched from the game ball launching mechanism 27 (see Figure 2), which is mounted below the window opening 23 on the resin base 21, are guided to the upper part of the game area PA by the guide rail.

Incidentally, the game ball launching mechanism 27 comprises a launching rail 27a extending toward a guide rail, a ball feeding device 27b that supplies game balls stored in the upper tray 55a (described later) onto the launching rail 27a, and a solenoid 27c, which is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. The solenoid 27c is driven and controlled by the rotation of the launching operation device (or operating handle) 28 provided on the front door frame 14, thereby launching the game balls.

The game board 24 has multiple openings of varying sizes that penetrate in the front-to-back direction. Each opening is provided with a general prize entry point 31, a special electric prize entry device 32, a first operation opening 33, a second operation opening 34, a through gate 35, a variable display unit 36, a special symbol unit 37, and a regular symbol unit 38, among others. There are a total of four general prize entry points 31, and one of each of the other types.

Even if a ball enters the through gate 35, no game balls are dispensed. On the other hand, when a ball enters the general prize entry point 31, the special electric prize entry device 32, the first operation point 33, or the second operation point 34, a predetermined number of game balls are dispensed. Specifically, if one game ball enters the first operation point 33 or the second operation point 34, one prize ball is dispensed; if one game ball enters the general prize entry point 31, ten prize balls are dispensed; and if one game ball enters the special electric prize entry device 32, fifteen prize balls are dispensed.

The number of prize balls awarded is arbitrary. For example, the second operating port 34 may award fewer prize balls than the first operating port 33, or the second operating port 34 may award more prize balls than the first operating port 33.

In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various prize slots are discharged from the game area PA through the outlet 24a. Furthermore, the game board 24 is equipped with numerous nails 24b to appropriately disperse and adjust the direction of the game balls' descent, as well as various components such as windmills.

Here, "ball entry" refers to a game ball passing through a predetermined opening. This includes not only the mode in which the game ball is discharged from the game area PA after passing through the opening, but also the mode in which the game ball continues to flow down the game area PA without being discharged after passing through the opening. However, in the following explanation, to clearly distinguish it from the entry of a game ball into the out opening 24a, the entry of a game ball into the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, the second operation opening 34, and the through gate 35 will also be referred to as "prize entry."

The first and second operating ports 33 and 34 are unitized as an operating port device and installed on the game board 24. Both the first and second operating ports 33 and 34 are open upwards. Furthermore, the two operating ports 33 and 34 are aligned vertically, with the first operating port 33 facing upwards. The second operating port 34 is equipped with a guide piece, a standard electrical mechanism 34a, consisting of a pair of movable left and right pieces. When the standard electrical mechanism 34a is closed, game balls cannot enter the second operating port 34; entry into the second operating port 34 becomes possible when the standard electrical mechanism 34a is open.

A through gate 35 is provided upstream of the second operating port 34 in the direction of the flow of the game ball. The through gate 35 has a vertically penetrating through-hole (not shown), and game balls that enter the through gate 35 flow down the game area PA after entering. This allows game balls that enter the through gate 35 to enter the second operating port 34.

Based on the ball entering the through gate 35, the normal electric mechanism 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is conducted triggered by the ball entering the through gate 35, and the normal diagram display section 38a of the normal diagram unit 38, located in the lower right corner of the game area PA where the game ball does not pass, displays a changing pattern. If the result of the internal lottery is a successful electric mechanism opening, and the corresponding stop result is displayed and the changing display on the normal diagram display section 38a ends, the system transitions to the normal electric open state. In the normal electric open state, the normal electric mechanism 34a is in an open state in a predetermined manner.

The general display unit 38a is configured as a segment display device in which multiple LED display segments are arranged in a predetermined manner, but it is not limited to this, and may be configured as other types of display devices such as liquid crystal displays, organic EL displays, CRTs, or dot matrix displays. Furthermore, the patterns displayed in the general display unit 38a may include configurations in which multiple types of characters are displayed in a variable manner, configurations in which multiple types of symbols are displayed in a variable manner, configurations in which multiple types of characters are displayed in a variable manner, or configurations in which multiple types of colors are switched and displayed.

In the general display unit 38, a general display hold display unit 38b is provided adjacent to the general display display unit 38a. Up to four game balls are held when they enter the through gate 35, and the number of held balls is displayed by the illumination of the general display hold display unit 38b.

A prize draw is triggered when a ball enters either the first or second operating port 33. The result of this draw is then clearly displayed through the display effects on the symbol display device 41 of the special display unit 37 and the variable display unit 36.

Regarding the special symbol unit 37, it is equipped with a special symbol display unit 37a. The display area of the special symbol display unit 37a is narrower than the display surface 41a of the symbol display device 41. In the special symbol display unit 37a, a winning lottery is conducted triggered by a winning entry into the first operation port 33 or the second operation port 34, resulting in the display of changing patterns or a predetermined display. The result corresponding to the lottery result is then displayed. While the special symbol display unit 37a is configured as a segment display device with multiple LED display segments arranged in a predetermined manner, it is not limited to this and may be configured as other types of display devices such as liquid crystal displays, organic EL displays, CRTs, or dot matrix displays. Furthermore, the patterns displayed in the special symbol display unit 37a could include configurations displaying multiple types of characters, multiple types of symbols, multiple types of characters, or multiple types of colors.

In the special feature unit 37, a special feature hold display unit 37b is provided adjacent to the special feature display unit 37a. Up to four game balls are held in the first or second operation opening 33, and the number of held balls is displayed by the illumination of the special feature hold display unit 37b.

Regarding the pattern display device 41 in detail, it is configured as a liquid crystal display device equipped with a liquid crystal display, and its display content is controlled by a display control device described later. Note that the pattern display device 41 is not limited to a liquid crystal display device; it may be other display devices with a display screen, such as a plasma display device, an organic EL display device, or a CRT, or it may be a dot matrix display device.

In the symbol display device 41, when a symbol variation display or predetermined display is performed on the special symbol display unit 37a based on a win in the first operation opening 33 or a win in the second operation opening 34, the symbol variation display or predetermined display is performed accordingly. For example, the display surface 41a of the symbol display device 41 has three symbol rows set as multiple display areas: upper, middle, and lower. In each symbol row, the main symbols numbered "1" to "9" are displayed in ascending or descending order in a scrolling display. In this scrolling display, scrolling is started for all symbol rows first, then switches from scrolling to standby display in the order of upper symbol row → lower symbol row → middle symbol row, and finally ends with a predetermined symbol displayed statically in each symbol row. Then, in a game round in which the game result is a jackpot, a predetermined combination of symbols is displayed statically on the active line set in advance on the display surface 41a of the symbol display device 41. Specifically, in the case of the most advantageous jackpot result (described later), the same odd-numbered symbol combination will be displayed. In the case of the low-probability jackpot result (described later), the same even-numbered symbol combination will be displayed. In the case of the low-winning, high-probability jackpot result (described later), a combination of symbols that is not identical, but which would not be displayed in the case of a low-winning, high-probability jackpot result, will be displayed.

Furthermore, the symbol display device 41 not only displays an effect triggered by a win in the first or second operation slot 33, but also displays an effect during the opening/closing execution mode that is entered after a win is achieved. Also, based on a win in either operation slot 33 or 34, the display on the special symbol display unit 37a and the symbol display device 41 begins, and one game round is considered to be the period from displaying a predetermined result until it ends. The manner in which the symbols are displayed in the symbol display device 41 is not limited to those described above and is arbitrary; the number of symbol rows, the direction of symbol display in each row, and the number of symbols in each row can be changed as appropriate. Also, the symbols displayed in the symbol display device 41 are not limited to those described above; for example, a configuration where only numbers are displayed as symbols is also possible.

If a jackpot is won in the winning lottery based on a ball entering the first operating port 33 or the second operating port 34, the system transitions to an opening/closing execution mode, which allows balls to enter the special electric prize entry device 32. The special electric prize entry device 32 has a large prize entry port (not shown) leading to the back of the game board 24, and also has an opening/closing door 32a that opens and closes this large prize entry port. The opening/closing door 32a can be positioned in either a closed or open state. Specifically, the opening/closing door 32a is normally in a closed state where game balls cannot enter, and is switched to an open state where game balls can enter if the internal lottery results in a transition to the opening/closing execution mode. Incidentally, the opening/closing execution mode is the mode that is entered when a winning result is obtained. Note that while entry is not impossible in the closed state, the system may be configured such that entry is less likely to occur than in the open state.

Figure 4 is an explanatory diagram illustrating the configuration for discharging game balls that have flowed down the game area PA.

As already explained, game balls that enter any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, the second operation slot 34, and the out slot 24a are discharged from the game area PA. In other words, game balls launched from the game ball launching mechanism 27 and flowing into the game area PA are discharged from the game area PA by entering any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, the second operation slot 34, and the out slot 24a. Game balls that enter any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, the second operation slot 34, and the out slot 24a are guided to the back side of the game board 24.

On the back of the game board 24, discharge passages 42-48 are formed, corresponding to the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a, respectively. Game balls flowing into the discharge passages 42-48 are guided down these passages to the lower end of the game board 24 on the back side and collected in a ball collection section (not shown). The collected game balls are then discharged into the ball circulation device of the island equipment where the pachinko machine 10 is installed in the gaming hall.

Each of the discharge passages 42 to 48 is equipped with various detection sensors 42a to 48a for detecting game balls. These discharge passages 42 to 48 and detection sensors 42a to 48a will be described below. As already explained, there are four general prize winning slots 31, and there are discharge passages 42 to 44 corresponding to each of these four slots. In this case, one detection sensor 42a and one detection sensor 43a are provided for the first discharge passage 42 corresponding to the leftmost general prize winning slot 31 and the second discharge passage 43 corresponding to the general prize winning slot 31 to its right. Specifically, the first prize winning slot detection sensor 42a is provided such that its detection range is located midway through the first discharge passage 42, and the second prize winning slot detection sensor 43a is provided such that its detection range is located midway through the second discharge passage 43. A game ball entering the leftmost general prize slot 31 is detected by the first prize slot detection sensor 42a while passing through the first discharge passage 42. A game ball entering the general prize slot 31 to its right is detected by the second prize slot detection sensor 43a while passing through the second discharge passage 43. Furthermore, a third discharge passage 44 is provided, formed to merge the two rightmost general prize slots 31 at an intermediate position. This third discharge passage 44 has entrance-side regions corresponding to each of the two general prize slots 31, and these entrance-side regions merge to form a single exit-side region. A third prize slot detection sensor 44a is provided such that its detection range exists at an intermediate position within the exit-side region of the third discharge passage 44. A game ball entering either of the two rightmost general prize slots 31 is detected by the third prize slot detection sensor 44a while passing through the third discharge passage 44.

A fourth discharge passage section 45 exists corresponding to the special electric prize entry device 32. A special electric detection sensor 45a is provided so that a detection range exists at an intermediate position in the fourth discharge passage section 45, and game balls that enter the special electric prize entry device 32 are detected by the special electric detection sensor 45a as they pass through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operation port 33. A first operation port detection sensor 46a is provided so that a detection range exists at an intermediate position in the fifth discharge passage section 46, and game balls that enter the first operation port 33 are detected by the first operation port detection sensor 46a as they pass through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operation port 34. A second operation port detection sensor 47a is provided so that its detection range exists midway through the sixth discharge passage 47. Game balls entering the second operation port 34 are detected by the second operation port detection sensor 47a while passing through the sixth discharge passage 47. A seventh discharge passage 48 exists corresponding to the out port 24a. An out port detection sensor 48a is provided so that its detection range exists midway through the seventh discharge passage 48. Game balls entering the out port 24a are detected by the out port detection sensor 48a while passing through the seventh discharge passage 48.

Furthermore, a game ball detected by any one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. Additionally, a gate detection sensor 49a is provided for the through gate 35, and game balls passing through the through gate 35 while flowing down the game area PA are detected by the gate detection sensor 49a.

The various detection sensors 42a to 49a are all electromagnetic induction type proximity sensors, but any sensor can be used as long as it can individually detect the game balls. Furthermore, the various detection sensors 42a to 49a are electrically connected to the main control unit 60, which will be described later, and the detection results from the various detection sensors 42a to 49a are output to the main control unit 60. Specifically, the various detection sensors 42a to 49a output a LOW level signal when no game balls are detected and a HI level signal when game balls are detected. However, this is not limited to this, and the relationship between HI and LOW may be reversed.

As shown in Figure 2, the front door frame 14 is provided so as to cover the entire front side of the inner frame 13, to which the game board 24 with the above configuration is attached to the resin base 21. As shown in Figure 1, the front door frame 14 has a window portion 51 formed therein, allowing almost the entire game area PA to be viewed from the front. The window portion 51 is roughly elliptical in shape, and a window panel 52 is fitted into it. The window panel 52 is made of glass and is colorless and transparent, but is not limited to this; it may also be made of synthetic resin and is colorless and transparent, or it may be made of colored and transparent material as long as the game area PA can be viewed from the front of the pachinko machine 10 through the window panel 52.

A display light-emitting unit 53 is provided above the window section 51. A pair of left and right speaker sections 54 are also provided, which output sound effects corresponding to the game state. Below the window section 51, an upper bulge 55 and a lower bulge 56 are arranged vertically. An upper tray 55a, opening upwards, is provided inside the upper bulge 55, and a lower tray 56a, also opening upwards, is provided inside the lower bulge 56. The upper tray 55a has the function of temporarily storing game balls dispensed from the dispensing device (described later) and guiding them to the game ball launching mechanism 27 while aligning them in a line. The lower tray 56a has the function of storing any excess game balls in the upper tray 55a.

Next, we will explain the configuration of the rear side of the gaming machine unit 12.

As shown in Figure 2, the main control device 60, which is responsible for the primary control of the game, is mounted on the back of the inner frame 13 (specifically, the game board 24). Figure 5 is a front view of the main control device 60.

As shown in Figure 5, the main control device 60 consists of a main control board 61 housed in a board box 60a. An MPU 62 is mounted on one of the board surfaces of the main control board 61, which is the element mounting surface. The board box 60a is made transparent so that the MPU 62 housed inside the board box 60a can be visually inspected from outside the board box 60a. Although the board box 60a is made of colorless transparency, it may be made of colored transparency if it is possible to visually inspect the MPU 62 housed inside the board box 60a from outside the board box 60a. The main control device 60 is mounted on the back of the resin base 21 such that the opposing wall portion 60b facing the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10 in the board box 60a. Therefore, by opening the gaming machine body 12 toward the front of the pachinko machine 10 relative to the outer frame 11 and exposing the back surface of the resin base 21, it becomes possible to visually inspect the opposing wall portion 60b of the circuit board box 60a, and to visually inspect the MPU 62 through the opposing wall portion 60b.

The circuit board box 60a is formed by combining multiple case bodies 60c front to back. These case bodies 60c are provided with connecting parts 60e to prevent separation of the case bodies 60c and to leave a trace when the case bodies 60c are separated. Multiple connecting parts 60e are arranged side by side on one side of the substantially rectangular parallelepiped circuit board box 60a. This allows for the separation of the case bodies 60c to be prevented by using some of the connecting parts 60e, and even if some of those connecting parts 60e are destroyed to separate the case bodies 60c, the separation of the case bodies 60c can be prevented again by subsequently connecting other connecting parts 60e. Furthermore, because the connecting parts 60e are destroyed and a trace is left when the case bodies 60c are separated, it is possible to determine whether the separation of the case bodies 60c has been performed improperly by visually inspecting the connecting parts 60e. Furthermore, on the side of the circuit board box 60a opposite to the side where the connecting portion 60e is located, a sealing sticker 60f is attached so as to straddle the boundary between the case bodies 60c. When the sealing sticker 60f is peeled off, the adhesive layer remains on the case body 60c. This allows for the sealing sticker 60f to leave a trace when it is removed during the separation of the case bodies 60c.

In the main control device 60 with the above configuration, the main control board 61 is provided with a setting key insertion unit 68a into which a setting key owned by the manager of the gaming hall is inserted and turned ON to create an opportunity to change the setting state of the pachinko machine 10 within the range of "setting 1" to "setting 6"; an update button 68b which is operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion unit 68a has been turned ON; a reset button 68c which is operated to clear the data in the main RAM 65, which will be described later, provided in the MPU 62 of the main control device 60; and first to third notification display devices 69a to 69c for notifying the results of the game history management. Furthermore, the MPU 62 mounted on the main control board 61 is provided with a reading terminal 68d for connecting the connection terminal of an external device in order to read the results of the game history management or information (programs and data) stored in the main ROM 64 by an external device. Furthermore, the settings for the pachinko machine 10 are not limited to the six levels from "Setting 1" to "Setting 6"; any number of levels is acceptable.

The setting key insertion section 68a, update button 68b, reset button 68c, reading terminal 68d (i.e., MPU 62), and the first to third notification display devices 69a to 69c are all provided on the element mounting surface of the main control board 61. Furthermore, as already explained, the element mounting surface of the main control board 61 faces the opposing wall 60b of the board box 60a, but the setting key insertion section 68a, update button 68b, reset button 68c, and reading terminal 68d are not covered by the opposing wall 60b. In other words, the opposing wall 60b has separate openings in the areas facing the setting key insertion section 68a, update button 68b, reset button 68c, and reading terminal 68d, respectively. This allows for the insertion of a setting key into the setting key insertion section 68a, the pressing of the update button 68b, the pressing of the reset button 68c, and the connection of an external device to the reading terminal 68d, all without requiring the board box 60a to be opened.

By inserting a setting key into the setting key insertion section 68a and rotating it in a predetermined direction, the setting key insertion section 68a is turned ON. In this state, by starting the supply of operating power to the pachinko machine 10 (i.e., by starting the supply of operating power to the MPU 62 of the main control device 60), the setting state of the pachinko machine 10 becomes changeable. Then, each time the update button 68b is pressed in this state, the setting state of the pachinko machine 10 is changed one step at a time in ascending order within the range of "Setting 1" to "Setting 6". Note that if the update button 68b is operated while the setting state is "Setting 6", it will be updated to "Setting 1". Furthermore, by rotating the setting key inserted in the setting key insertion section 68a from the ON position in the opposite direction to the predetermined direction to return it to its initial position, the setting key insertion section 68a becomes OFF. When the setting key insertion section 68a is turned OFF, the above changeable state ends, and the machine becomes playable with the current setting value. In other words, you cannot change the setting value by operating the update button 68b after the changeable state has ended.

The ON operation on the setting key insertion unit 68a is only effective when power is supplied to the pachinko machine 10 (i.e., when power is supplied to the MPU 62 of the main control unit 60). Therefore, even if the ON operation on the setting key insertion unit 68a is performed after the power supply start processing in the MPU 62 of the main control unit 60 has finished, the setting value cannot be changed.

The settings of the pachinko machine 10 determine the degree of advantage per unit time in that pachinko machine 10. The larger the value of "setting n" (where n is an integer from "1" to "6"), the higher the degree of advantage. As will be explained in detail later, there are two win/loss lottery modes that determine the probability of winning a jackpot: a low-probability mode where the winning probability is relatively low, and a high-probability mode where the winning probability is relatively high. The higher the setting value, the higher the probability of winning a jackpot in the low-probability mode. On the other hand, the probability of winning a jackpot in the high-probability mode remains constant regardless of the setting value.

As described above, the reset button 68c is operated to clear the data in the main RAM 65. However, in order to trigger this data clearing, it is necessary to start supplying operating power to the pachinko machine 10 while the reset button 68c is pressed (i.e., to start supplying operating power to the MPU 62 of the main control unit 60). The ON operation of the reset button 68c is only effective when the supply of operating power to the pachinko machine 10 begins (i.e., when the supply of operating power to the MPU 62 of the main control unit 60 begins). Therefore, even if the reset button 68c is pressed after the processing for starting the supply of operating power in the MPU 62 of the main control unit 60 has finished, the data in the main RAM 65 cannot be cleared.

As previously explained, the reading terminal 68d is used to connect an external device to read the game history management results or information (programs and data) stored in the main ROM 64. However, in order to output to an external device, it is necessary to start supplying operating power to the pachinko machine 10 while the external device's connection terminal is connected to the reading terminal 68d (i.e., to start supplying operating power to the MPU 62 of the main control unit 60). The connection of an external device to the reading terminal 68d is only valid when the supply of operating power to the pachinko machine 10 begins (i.e., when the supply of operating power to the MPU 62 of the main control unit 60 begins). Therefore, even if an external device is connected to the reading terminal 68d after the processing for starting the supply of operating power in the MPU 62 of the main control unit 60 has finished, no external output will be produced to that external device.

The first to third notification display devices 69a to 69c are all segment displays with seven LED display segments arranged in a row, but are not limited to this; they may also be single multi-color light-emitting devices, liquid crystal displays, or organic EL displays. The first to third notification display devices 69a to 69c are all installed so that their display surfaces face the direction of the element mounting surface of the main control board 61, and are covered by the opposing wall portion 60b of the board box 60a. In this case, because the board box 60a is made transparent, it is possible to visually inspect the display surfaces of the first to third notification display devices 69a to 69c housed inside the board box 60a from outside the board box 60a. Furthermore, as already explained, the main control device 60 is mounted on the back of the resin base 21 in the circuit board box 60a such that the opposing wall portion 60b facing the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, when the game machine body 12 is opened in front of the pachinko machine 10 relative to the outer frame 11, exposing the back of the resin base 21 to the front of the pachinko machine 10, the display surfaces of the first to third notification display devices 69a to 69c can be visually inspected through the opposing wall portion 60b.

The display surface of the first notification display device 69a displays not only the numbers "0" to "9" but also various characters, including alphabetical characters. On the other hand, the second notification display device 69b and the third notification display device 69c display only the numbers "0" to "9". The results of the game history management are reported using the first to third notification display devices 69a to 69c, and the content of this report will be explained in detail later. Furthermore, when the setting state of the pachinko machine 10 is changeable, the value corresponding to the current setting is displayed on the third notification display device 69c. Note that the value corresponding to this setting may be displayed on the first notification display device 69a, or on the second notification display device 69b. Alternatively, the setting value before the changeable state is entered may be displayed on one of the first to third notification display devices 69a to 69c, while the current setting value is displayed on the other of the first to third notification display devices 69a to 69c.

As shown in Figure 2, the back pack unit 15 is installed so as to cover the back side of the inner frame 13, including the main control device 60. The back pack unit 15 includes a back pack 72 made of transparent synthetic resin, and the dispensing mechanism 73 and the control device assembly unit 74 are attached to this back pack 72.

The dispensing mechanism 73 comprises a tank 75 into which game balls supplied from the island equipment of the gaming hall are continuously replenished, and a dispensing device 76 for dispensing the game balls stored in the tank 75. The game balls dispensed from the dispensing device 76 are discharged into the upper tray 55a or lower tray 56a through a dispensing passage located downstream of the dispensing device 76. The dispensing mechanism 73 is supplied with, for example, a 24-volt AC main power supply and is equipped with a back-pack circuit board having a power switch for turning the power ON and OFF.

The control unit 74 comprises a payout control device 77 that controls the payout device 76, and a power supply/launch control device 78 that generates and outputs predetermined power required by various control devices, and controls the launch of game balls in response to the player's operation of the launching device 28. The payout control device 77 and the power supply/launch control device 78 are arranged front to back, with the payout control device 77 facing the rear of the pachinko machine 10.

<Electrical configuration of pachinko machine 10>
Figure 6 is a block diagram showing the electrical configuration of the pachinko machine 10.

The main control unit 60 comprises a main control board 61 that controls the main aspects of gameplay, and a power failure monitoring board 67 that monitors the power supply. The main control board 61 is equipped with an MPU 62. The MPU 62 contains a main CPU 63, which is an arithmetic processing unit including a control unit and an arithmetic unit, as well as a main ROM 64, a main RAM 65, and a management IC 66. In addition to the above components, the MPU 62 also incorporates interrupt circuits, timer circuits, data input/output circuits, and various counter circuits acting as random number generators.

The main ROM 64 is a memory (i.e., a non-volatile storage means) that does not require external power supply for storage, such as NOR-type flash memory and NAND-type flash memory, and is used in read-only mode. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

The main RAM 65 is a memory (i.e., volatile memory) that requires external power supply for storage, such as SRAM and DRAM, and is used for both reading and writing. The main RAM 65 allows random access and, when compared with the main ROM 64 for the same data capacity, has a faster read time. The main RAM 65 temporarily stores various data for the execution of the control program stored in the main ROM 64.

The management IC 66 is a management device that manages the game history based on information supplied from the main CPU 63. As will be described in detail later, the management IC 66 tracks the entry history of game balls into the general prize entry port 31, the special electric prize entry device 32, the first operation port 33, the second operation port 34, and the out port 24a. Based on this tracked entry history, the frequency of ball entry into the general prize entry port 31, the special electric prize entry device 32, the first operation port 33, and the second operation port 34 is also determined. Furthermore, the management IC 66 tracks the frequency of occurrence of the opening/closing execution mode and the high-frequency support mode, which will be described later.

The MPU 62 is provided with both input and output ports. The input side of the MPU 62 is connected to the power outage monitoring board 67 and the payout control device 77, both located on the main control device 60. The power outage monitoring board 67 is connected to a power supply/discharge control device 78, which has the function of supplying operating power. Operating power is supplied to the MPU 62 via the power outage monitoring board 67.

Various sensors, including ball entry detection sensors 42a to 49a, are connected to the input side of the MPU 62. As previously explained, the ball entry detection sensors 42a to 49a include the first prize entry sensor 42a, the second prize entry sensor 43a, the third prize entry sensor 44a, the special electric detection sensor 45a, the first operation opening sensor 46a, the second operation opening sensor 47a, the out opening sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a to 49a, the main CPU 63 performs ball entry determination for each entry section. Furthermore, the main CPU 63 executes various lotteries based on ball entry into the first operation opening 33 and also based on ball entry into the second operation opening 34.

The input side of the MPU 62 is provided with a setting key insertion section 68a, an update button 68b, and a reset button 68c, all located on the main control board 61. The setting key insertion section 68a is equipped with a sensor (not shown) that detects whether it is in the ON or OFF position. The main CPU 63 then determines whether the setting key insertion section 68a is in the ON or OFF position based on the sensor's detection result. The update button 68b is equipped with a sensor (not shown) that detects whether it is being pressed. The main CPU 63 then determines whether the update button 68b is being pressed based on the sensor's detection result. The reset button 68c is equipped with a sensor (not shown) that detects whether it is being pressed. The main CPU 63 then determines whether the reset button 68c is being pressed based on the sensor's detection result.

The output side of the MPU 62 is connected to a power outage monitoring board 67, a payout control device 77, and a sound and light emission control device 81. The payout control device 77 outputs a prize ball command based, for example, when a game ball enters the prize ball corresponding to the payout of game balls within the aforementioned ball entry section. The sound and light emission control device 81 outputs various commands, such as variation commands, type commands, and opening commands.

The output side of the MPU 62 is connected to the special electric drive unit 32b, which opens and closes the opening/closing door 32a of the special electric prize winning device 32; the general electric drive unit 34b, which opens and closes the general electric mechanism 34a of the second operating port 34; the special symbol unit 37; and the general symbol unit 38. Incidentally, the special symbol unit 37 is equipped with a special symbol display unit 37a and a special symbol hold display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the general symbol unit 38 is equipped with a general symbol display unit 38a and a general symbol hold display unit 38b, all of which are connected to the output side of the MPU 62. The main control board 61 is provided with various driver circuits, and through these driver circuits, the MPU 62 performs drive control for the various drive units and various display units.

In other words, in the opening/closing execution mode, the main CPU 63 controls the drive unit 32b for the special electric prize device 32 so that it is opened and closed. Also, if the open state of the regular electric prize device 34a is selected, the main CPU 63 controls the drive unit 34b for the regular electric prize device 34a so that it is opened and closed. Furthermore, for each game round, the main CPU 63 controls the display of the special symbol display unit 37a. In addition, when the result of the lottery to determine whether or not to open the regular electric prize device 34a is to be displayed, the main CPU 63 controls the display of the regular symbol display unit 38a. Furthermore, when a winning combination occurs in the first or second operating port 33, or when a variable display is initiated in the special symbol display unit 37a, the main CPU 63 executes display control for the special symbol hold display unit 37b. Similarly, when a winning combination occurs in the through gate 35, or when a variable display is initiated in the general symbol display unit 38a, the main CPU 63 executes display control for the general symbol hold display unit 38b.

The output side of the MPU 62 is connected to the first to third notification display devices 69a to 69c. Furthermore, the management results of the game history in the management IC 66 are notified through the displays of the first to third notification display devices 69a to 69c. When the settings of the pachinko machine 10 are changed, the current settings are displayed on the third notification display device 69c. In this case, the first notification display device 69a and the second notification display device 69b are controlled by the management IC 66 and not by the main CPU 63, while the third notification display device 69c is controlled by both the main CPU 63 and the management IC 66. The display control by the main CPU 63 takes precedence over the display control by the management IC 66 for the third notification display device 69c.

However, this is not the only possible configuration. The third notification display device 69c may also be controlled by the management IC 66 and not by the main CPU 63. In this case, when the current setting value is to be displayed on the third notification display device 69c during a change in the settings of the pachinko machine 10, the main CPU 63 should issue a display instruction to the management IC 66.

The MPU 62 is provided with a reading terminal 68d. A sensor (not shown) is attached to the reading terminal 68d, and this sensor detects whether or not an external device's connection terminal is connected to the reading terminal 68d. The main CPU 63 then determines whether or not an external device's connection terminal is connected to the reading terminal 68d based on the detection result from the sensor. Furthermore, if an external device is connected to the reading terminal 68d, the game history management results from the management IC 66 or information (programs and data) stored in the main ROM 64 is output to the external device.

The power outage monitoring board 67 acts as a relay between the main control board 61 and the power supply/launch control device 78, monitoring the maximum voltage output from the power supply/launch control device 78, which is a stable DC voltage of 24 volts. The payout control device 77 controls the payout of prize balls and rental balls via the payout device 76 based on the prize ball command received from the main control device 60.

The power supply and launch control device 78 is connected to a commercial power supply (external power supply) in, for example, a gaming hall. Based on the external power supplied from this commercial power supply, it generates the necessary operating power for the main control board 61, the payout control device 77, etc., and supplies that generated operating power. Incidentally, the power supply and launch control device 78 is equipped with a backup power supply unit, such as a backup capacitor, for use during power outages. Even when the power to the pachinko machine 10 is OFF, power for memory retention is supplied from this backup power supply unit to the main RAM 65 of the main control device 60 and the payout control device 77. Furthermore, the power supply and launch control device 78 is responsible for controlling the launch of the game ball launch mechanism 27, which is driven when predetermined launch conditions are met. Also, as already explained, the payout mechanism 73 is equipped with a power switch. When the power switch is turned ON, the supply of operating power to the pachinko machine 10 begins, and when the power switch is turned OFF, the supply of operating power to the pachinko machine 10 stops.

The sound and light emission control device 81 controls the operation of the display light emission unit 53 and speaker unit 54, which are installed on the front door frame 14, based on various commands received from the main control device 60, and also controls the display control device 82. The display control device 82 performs display control of the graphic display device 41 based on commands received from the sound and light emission control device 81.

<Electrical configuration for performing various lottery draws on the main CPU 63>
Next, the electrical configuration for performing various lotteries on the main CPU 63 will be explained using Figure 7.

The main CPU 63 uses various counter information during gameplay to perform tasks such as the lottery for the occurrence of a jackpot, setting the display of the special symbol display unit 37a, setting the symbol display of the symbol display device 41, and setting the display of the regular symbol display unit 38a. Specifically, as shown in Figure 7, it uses a random number counter C1 used for the lottery for the occurrence of a jackpot, a jackpot type counter C2 used for determining the type of jackpot, a random number counter C3 used for the lottery for the occurrence of a reach when the symbol display device 41 is fluctuating to a miss, a random number initial value counter CINI used for setting the initial value of the random number counter C1, and a fluctuation type counter CS that determines the display duration in the special symbol display unit 37a and the symbol display device 41. Furthermore, it uses a regular power function release counter C4 used for a lottery to determine whether or not to set the regular power function 34a of the second operation port 34 to the regular power release state. Note that each of the above counters C1 to C3, CINI, CS, and C4 are provided in the various counter areas 65b of the main RAM 65.

Each counter C1-C3, CINI, CS, and C4 is a loop counter that adds 1 to its previous value each time it is updated, and returns to "0" after reaching its maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored in the reserve storage area 65a, which is provided as an acquired information storage means in the main RAM 65, when a prize is awarded to the first operation port 33 or the second operation port 34.

The hold storage area 65a comprises a hold area RE and an execution area AE. The hold area RE includes a first hold area RE1, a second hold area RE2, a third hold area RE3, and a fourth hold area RE4. Based on the winning history at the first or second operation port 33, a combination of numerical information from the winning random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored as hold information in one of the hold areas RE1 to RE4.

In this case, when multiple consecutive entries into the first or second operating port 33 occur, the numerical information is stored chronologically in the first to fourth holding areas RE1, RE2, RE3, and RE4, respectively. By providing these four holding areas RE1 to RE4, up to four entries of the game ball entry history into the first or second operating port 33 can be stored.

Furthermore, the number of items that can be stored is not limited to four; it can be any number, such as two, three, five or more, or even a single item.

The execution area AE is an area for moving the numerical information stored in the first holding area RE1 of the holding area RE when the variable display of the special figure display unit 37a begins. At the start of each game round, a win/loss determination is made based on the various numerical information stored in the execution area AE.

The above counters will be explained in detail below.

First, let's explain the regular electric feature release counter C4. The regular electric feature release counter C4 is configured to increment by 1 sequentially within the range of 0 to 250, and then return to "0" after reaching the maximum value. The regular electric feature release counter C4 is updated periodically and stored in the regular electric reserve area 65c of the main RAM 65 when a game ball enters the through gate 35. Then, at a predetermined timing, a lottery is held to determine whether or not to control the regular electric feature 34a to the open state based on the value of the stored regular electric feature release counter C4.

In this pachinko machine 10, multiple support modes are set so that the support provided by the electric power mechanism 34a differs from one another. Specifically, the support modes include a high-frequency support mode and a low-frequency support mode, so that, when comparing situations where game balls are continuously launched in the game area PA in a similar manner, the frequency at which the electric power mechanism 34a of the second operating port 34 opens per unit time is relatively high or low.

In both the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power opening state in the normal power opening lottery using the normal power mechanism opening counter C4 is the same (for example, 4/5 in both modes). However, in the high-frequency support mode, the number of times the normal power mechanism 34a opens when the normal power opening state is won is set to be greater than in the low-frequency support mode, and the opening time for each instance is also set to be longer. In this case, when the normal power opening state is won in the high-frequency support mode and the normal power mechanism 34a opens multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for each instance. Furthermore, in the high-frequency support mode, the minimum time required to ensure that the next normal power opening lottery is conducted after one normal power opening lottery is performed (i.e., the duration of one display on the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

As described above, in high-frequency support mode, the probability of a ball entering the second operating port 34 is higher than in low-frequency support mode. In other words, in low-frequency support mode, the probability of a ball entering the first operating port 33 is higher than in the second operating port 34, but in high-frequency support mode, the probability of a ball entering the second operating port 34 is higher than in the first operating port 33. Furthermore, when a ball enters the second operating port 34, a predetermined number of game balls are dispensed. Therefore, in high-frequency support mode, players can play while minimizing the loss of their game balls.

Furthermore, the configuration for making the high-frequency support mode more frequent than the low-frequency support mode in terms of the frequency of normal power opening per unit time is not limited to the above. For example, a configuration that increases the probability of winning the normal power opening state in the normal power opening lottery may also be used. Also, in a configuration where multiple types of reservation times are available for the period between one normal power opening lottery and the next (for example, the time for the variable display executed on the normal power display unit 38a based on entry into the through gate 35), the high-frequency support mode may be configured to more easily select a shorter reservation time or to have a shorter average reservation time than the low-frequency support mode. Moreover, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying one or any combination of the following conditions: increasing the number of openings, increasing the opening time, shortening the reservation time between one normal power opening lottery and the next, shortening the average reservation time, and increasing the winning probability.

As explained earlier, the pachinko machine 10 has six settings, "Setting 1" to "Setting 6." However, the opening frequency and manner of the electric device 34a in the low-frequency support mode are the same regardless of the setting value, and the opening frequency and manner of the electric device 34a in the high-frequency support mode are also the same regardless of the setting value. However, this is not the only option, and the machine may be configured such that at least one of the opening frequency and manner of the electric device 34a in at least one of the low-frequency support mode and high-frequency support mode varies according to the setting of the pachinko machine 10. For example, the machine may be configured so that the opening frequency of the electric device 34a in the low-frequency support mode increases as the setting value increases, or the probability of a game ball entering the second operating port 34 when the electric device 34a is open once in the low-frequency support mode increases. Furthermore, the higher the setting value, the more frequently the normal electric mechanism 34a opens in high-frequency support mode. Alternatively, the configuration may be such that the probability of a game ball entering the second operating port 34 increases when the normal electric mechanism 34a opens once in high-frequency support mode.

Next, the winning random number counter C1 will be explained. The winning random number counter C1 is configured to increment by 1 sequentially within a range of, for example, 0 to 599, and then return to "0" after reaching the maximum value. In particular, when the winning random number counter C1 completes one cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is updated periodically and stored in the reserve storage area 65a of the main RAM 65 at the timing when a game ball enters the first operation opening 33 or the second operation opening 34.

The random number values that result in a jackpot are stored in the main ROM 64 as a win/loss table. Figure 8 is an explanatory diagram illustrating the various tables stored in the main ROM 64. The win/loss tables stored include low-probability win/loss tables 64a to 64f for low-probability modes and high-probability win/loss table 64g for high-probability modes.

The low probability win/loss tables 64a to 64f are provided with a one-to-one correspondence to the setting states "Setting 1" through "Setting 6". Specifically, there is a low probability win/loss table 64a for Setting 1, which is referenced when the pachinko machine 10 is set to "Setting 1"; a low probability win/loss table 64b for Setting 2, which is referenced when the pachinko machine 10 is set to "Setting 2"; a low probability win/loss table 64c for Setting 3, which is referenced when the pachinko machine 10 is set to "Setting 3"; a low probability win/loss table 64d for Setting 4, which is referenced when the pachinko machine 10 is set to "Setting 4"; a low probability win/loss table 64e for Setting 5, which is referenced when the pachinko machine 10 is set to "Setting 5"; and a low probability win/loss table 64f for Setting 6, which is referenced when the pachinko machine 10 is set to "Setting 6".

These low-probability win/loss tables 64a to 64f are set so that the probability of winning a jackpot increases with higher setting values. Specifically, when low-probability win/loss table 64a for setting 1 is referenced, the probability of winning a jackpot is approximately 1/320; when low-probability win/loss table 64b for setting 2 is referenced, the probability is approximately 1/310; when low-probability win/loss table 64c for setting 3 is referenced, the probability is approximately 1/300; when low-probability win/loss table 64d for setting 4 is referenced, the probability is approximately 1/290; when low-probability win/loss table 64e for setting 5 is referenced, the probability is approximately 1/280; and when low-probability win/loss table 64f for setting 6 is referenced, the probability is approximately 1/270. Therefore, a higher setting value for the pachinko machine 10 makes it easier to win a jackpot in low-probability mode, which is advantageous for the player.

On the other hand, the high-probability win/loss table 64g is provided in only one type, so that it is common to all settings from "Setting 1" to "Setting 6". The high-probability win/loss table 64g is set so that the probability of winning a jackpot is higher than that of the low-probability win/loss tables 64a to 64f, regardless of the setting. Specifically, when the high-probability win/loss table 64g is referenced, the probability of a jackpot is approximately 1/30. This makes it possible to make the high-probability mode more advantageous than the low-probability mode, regardless of the setting of the pachinko machine 10. Furthermore, even in the lowest setting state, "Setting 1," the probability of winning a jackpot is higher than in the low-probability mode of the highest setting state, "Setting 6." Additionally, this makes it possible to avoid any advantage or disadvantage based on the setting of the pachinko machine 10 in the high-probability mode, and reduces the memory capacity required to pre-store the high-probability win/loss table 64g in the main ROM 64.

The jackpot type counter C2 is configured to increment by 1 sequentially within the range of 0 to 29, and then return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically, and when a game ball enters the first or second operation opening 33, it is stored in the reserve storage area 65a.

This pachinko machine 10 has multiple jackpot outcomes. These multiple jackpot outcomes are set by differentiating three conditions: (1) the manner of opening and closing control of the special electric prize entry device 32 in the opening/closing execution mode, (2) the lottery mode in the win/loss lottery means after the opening/closing execution mode ends, and (3) the support mode in the regular electric prize mechanism 34a of the second operating port 34 after the opening/closing execution mode ends.

In the opening and closing execution mode, the opening and closing control of the special electric prize winning device 32 is configured such that the frequency of prize winnings to the special electric prize winning device 32 during the period from the start to the end of the opening and closing execution mode is relatively high or low. Specifically, in either the high-frequency or low-frequency winning mode, the game is executed up to a predetermined number of rounds.

A round game is a game that continues until either a predetermined maximum duration has elapsed, or a predetermined maximum number of game balls have entered the special electric prize winning device 32, is met. Furthermore, the number of round games in the opening/closing execution mode triggered by a jackpot result is fixed and the same regardless of the type of jackpot result that triggered the transition. Specifically, regardless of the jackpot result, the maximum number of round games is set to 15 rounds.

Furthermore, in this pachinko machine 10, the opening mode of the special electric prize winning device 32 is set in multiple ways, differing in the duration of the opening from the time the special electric prize winning device 32 is opened until it is closed. Specifically, there is a long-duration mode set to an extended opening duration of 29 seconds, and a short-duration mode set to a shorter duration of 0.06 seconds.

In this pachinko machine 10, when the launching device 28 is operated by the player, the game ball launching mechanism 27 is driven and controlled so that one game ball is launched towards the game area PA every 0.6 seconds. Furthermore, the maximum number of balls required to complete a round game is set to 9. Therefore, in the long-duration opening mode, the opening duration is set to be longer than the product of the game ball launching cycle and the duration of one round game. On the other hand, in the short-duration opening mode, the opening duration is set to be shorter than the product of the game ball launching cycle and the duration of one round game; more specifically, shorter than the game ball launching cycle. Therefore, if an opening occurs in the long-duration mode, it is expected that the special electric prize winning device 32 will receive the maximum number of balls required for one round game. If an opening occurs in the short-duration mode, it is expected that no balls will be received by the special electric prize winning device 32, or that only about one ball will be received.

In high-frequency winning mode, the special electric winning device 32 is opened once in a long-duration manner during each round of gameplay. Conversely, in low-frequency winning mode, the special electric winning device 32 is opened once in a short-duration manner during each round of gameplay.

Furthermore, the number of times the special electric prize winning device 32 opens and closes, the number of rounds played, the duration of each opening, and the maximum number of prizes per round in the high-frequency and low-frequency prize winning modes are not limited to the above values and are arbitrary, as long as the frequency of prize winnings to the special electric prize winning device 32 from the start to the end of the opening/closing execution mode is higher in the high-frequency prize winning mode than in the low-frequency prize winning mode.

The distribution of jackpot results for the jackpot type counter C2 is stored in the main ROM 64 as a distribution table 64h, as shown in Figure 8. In the distribution table 64h, the distribution destinations for jackpot results are set as low-probability jackpot results, low-scoring high-probability jackpot results, and most advantageous jackpot results.

A low-probability jackpot result is one in which the opening/closing execution mode becomes the high-frequency winning mode, and after the opening/closing execution mode ends, the win/loss lottery mode becomes the low-probability mode, and the support mode becomes the high-frequency support mode. However, this high-frequency support mode will revert to the low-frequency support mode if the number of games played after the transition reaches the termination threshold (specifically, 100 games).

A low-payout, high-probability jackpot result is one in which the opening/closing execution mode becomes the low-frequency payout mode, and after the opening/closing execution mode ends, the win/loss lottery mode becomes the high-probability mode, and the support mode becomes the high-frequency support mode. These high-probability and high-frequency support modes continue until the lottery result in a jackpot state is achieved, and the game transitions to the jackpot state.

The most advantageous jackpot result is one in which the opening/closing execution mode becomes a high-frequency winning mode, and after the opening/closing execution mode ends, the win/fail lottery mode becomes a high-probability mode, and the support mode becomes a high-frequency support mode. These high-probability and high-frequency support modes continue until the lottery result in a jackpot state is achieved, and the game transitions to the jackpot state.

Furthermore, in relation to the above game states, the "normal game state" refers to a state where the opening/closing execution mode is not active, and the win/loss lottery mode is in low probability mode, and the support mode is in low-frequency support mode. Additionally, the game may be configured so that a low-winning, high-probability jackpot result is not set. Also, in the opening/closing execution mode for a low-winning, high-probability jackpot result, the number of rounds played may be fewer than in the cases of low-probability jackpot results and most advantageous jackpot results.

In the distribution table 64h, among the values of the jackpot type counter C2 from "0 to 29", "0 to 9" correspond to low-probability jackpot results, "10 to 14" correspond to low-winning, high-probability jackpot results, and "15 to 29" correspond to the most advantageous jackpot results.

The distribution table 64h is provided in only one form, so that it is common regardless of whether the setting is "Setting 1" through "Setting 6". This makes it possible to prevent any advantage or disadvantage in the distribution of jackpot results based on the setting of the pachinko machine 10, and also reduces the storage capacity required to pre-store the distribution table 64h in the main ROM 64.

Furthermore, the distribution of jackpot results may differ depending on the settings of the pachinko machine 10. For example, the configuration may be such that higher settings result in a higher probability of being allocated to the most advantageous jackpot result, or that higher settings result in a higher probability of being allocated to either the most advantageous jackpot result or a low-entry, high-probability jackpot result. In this case, higher settings make it possible to increase the probability of entering a high-probability mode after a jackpot result. Alternatively, the configuration may be such that higher settings result in a lower probability of being allocated to a low-entry, high-probability jackpot result, or that high settings do not result in a low-entry, high-probability jackpot result, while low settings may result in a low-entry, high-probability jackpot result. In this case, higher settings make it possible to increase the probability of the high-frequency entry mode opening and closing execution mode occurring.

Next, the reach random number counter C3 will be explained. The reach random number counter C3 is configured to increment by 1 sequentially within a range of, for example, 0 to 238, and then return to "0" after reaching the maximum value. This pachinko machine 10 has an expectation effect set as a type of display effect in the symbol display device 41. An expectation effect refers to a display state in a game machine equipped with a symbol display device 41 capable of displaying changing symbols, where the final stop result in a game round resulting in a predetermined jackpot is the corresponding assigned result. This state is designed to make the player believe that the changing symbol display state is likely to result in the corresponding assigned result, from the start of the symbol changing display on the symbol display device 41 until the stop result is displayed. Specifically, the corresponding assigned result is displayed when a combination of symbols with the same number on any of the active lines is stopped.

There are two types of anticipation-based effects: a "reach" display and a pre-announcement display that anticipates the occurrence of a reach display or the corresponding outcome, especially in the stages preceding the reach display.

The reach display includes a display state in which, by stopping the symbols in some of the multiple symbol sequences displayed on the display surface 41a of the symbol display device 41, a combination of reach symbols is displayed, and then the remaining symbol sequences are displayed in a variable pattern. Furthermore, this includes a reach effect where, while the combination of reach symbols is displayed as described above, the remaining symbol sequences are displayed in a variable pattern, and a predetermined character or other element is displayed as an animation on the background screen. Alternatively, the combination of reach symbols may be reduced in size or hidden, and then a predetermined character or other element is displayed as an animation across approximately the entire display surface 41a to create a reach effect.

The notification display includes a mode in which a character is displayed separately from the symbols on the symbol rows when the symbol variation display has started on the display surface 41a of the symbol display device 41, and when the symbols are varying in all symbol rows, or when the symbols are varying in some symbol rows but multiple symbol rows are varying. It also includes modes in which the background screen is changed to a predetermined mode different from the previous mode, or when the symbols on the symbol rows are changed to a predetermined mode different from the previous mode. Such notification displays can occur in both game rounds where a reach display occurs and when a reach display does not occur, but they are set to occur with a higher probability when a reach display occurs than when a reach display does not occur.

The "Reach" display is executed regardless of the value of the Reach Random Number Counter C3 in game rounds where the same combination of symbols ultimately stops and is displayed. Furthermore, it is not executed regardless of the value of the Reach Random Number Counter C3 in game rounds corresponding to a jackpot result where the same combination of symbols does not stop and is not displayed. In game rounds corresponding to a losing result, the display is executed only if the Reach Random Number Counter C3, obtained at a predetermined timing by referring to the Reach table stored in the main ROM 64, corresponds to the occurrence of a Reach display.

On the other hand, the decision of whether or not to display a notification is made not by the main control device 60, but by the sound and light emission control device 81. In this case, the sound and light emission control device 81 executes a lottery process for displaying notifications so that at least one of the following conditions is met: that the notification is more likely to occur in the game round corresponding to a jackpot result compared to the game round corresponding to a losing result, and that notifications with a low appearance rate are more likely to occur. Incidentally, the result of this lottery is reflected when the game round's effects are executed on the symbol display device 41.

Here, the probability of a "reach" display occurring in a game round that results in a loss is the same regardless of the setting state, from "Setting 1" to "Setting 6". This ensures that there is no advantage or disadvantage based on the setting state of the pachinko machine 10 regarding the probability of a reach display occurring in a game round that results in a loss. However, this is not the only option; a configuration where the probability of a reach display occurring in a game round that results in a loss increases with higher setting values is also possible.

Next, the variation type counter CS will be explained. The variation type counter CS is configured to increment by 1 sequentially within a range of, for example, 0 to 198, and then return to "0" after reaching the maximum value. The variation type counter CS is used by the main CPU 63 to determine the display duration in the special display unit 37a and the display duration of the symbols in the symbol display device 41. The variation type counter CS is updated once each time the timer interrupt processing described later is executed, and is repeatedly updated within the remaining time until the next timer interrupt processing is executed. The buffer value of the variation type counter CS is acquired when determining the variation pattern at the start of the variation display in the special display unit 37a and at the start of the symbol variation by the symbol display device 41.

<Regarding the processing configuration of the main CPU 63>
Next, we will explain the processes executed by the main CPU 63 to advance the game. These processes of the main CPU 63 can be broadly divided into the main process, which is started when the power is turned on, and the timer interrupt process, which is started periodically (at a 4-millisecond cycle in this embodiment).

<Main Processing>
First, the main process will be explained while referring to the flowchart in Figure 9.

First, a power-on wait process is executed (step S101). During this power-on wait process, for example, the system waits for a predetermined waiting time (specifically, 1 second) after the main process has started, without proceeding to the next process. During this power-on wait process, the operation start and initial setup of the graphic display device 41 are completed. Afterward, access to the main RAM 65 is permitted (step S102).

Subsequently, it is determined whether the setting key insertion unit 68a is turned ON (step S103). If the setting key insertion unit 68a is not turned ON (step S103: NO), it is determined whether the reset button 68c is pressed (step S104). If the reset button 68c is pressed (step S104: YES), each area of the main RAM 65 is cleared to "0" except for the area where setting value information indicating the setting state of the pachinko machine 10 is set, and initial settings are performed on the areas that have been cleared to "0" (step S105). In other words, if the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed without turning ON the setting key insertion unit 68a, the setting value information is maintained in the state before the supply of operating power to the pachinko machine 10 was stopped, and the clearing process of the main RAM 65 is performed, and initial settings are performed on the memory areas where the clearing process was performed. This makes it possible to initialize other areas of the main RAM 65 without requiring a change in the setting value. In step S105, the various registers of the main CPU 63 are also cleared to "0" before initializing them.

If the reset button 68c is not pressed (step S104: NO), it is determined whether the power outage flag is set to "1" (step S106). The power outage flag is located in the main RAM 65. When the power supply to the main CPU 63 is cut off, if the predetermined power outage processing is executed successfully, the power outage flag is set to "1". If the power outage flag is set to "1", it is determined whether the checksum calculation result matches the checksum stored at the time of power cut-off, i.e., the validity of the stored data (step S107). If the process in step S105 is executed, or if a positive determination is made in step S107, it is determined whether the settings of the pachinko machine 10 are normal by checking the main RAM 65 (step S108). Specifically, it is determined that the settings are normal if they are any of "setting 1" to "setting 6", and abnormal if they are "0" or 7 or higher.

If a negative result is obtained in any of steps S106 to S108, the operation prohibition process is executed. The operation prohibition process executes an error notification process (step S109) to inform the hall manager or other relevant parties of the error, after which an infinite loop occurs. This operation prohibition process is released when the all-clear process (step S117), described later, is executed.

If all of steps S106 to S108 result in a positive determination, the power-on setting process is executed (step S110). In the power-on setting process, predetermined areas of the main RAM 65, such as the power outage flag, are set to their initial values, and commands corresponding to the current game state are sent to the audio/light-emitting control device 81. After executing the process in step S110, a recognition process (step S111) is performed to allow the management IC 66 to recognize various information, and a data output process (step S112) is performed to output various data to an external device connected to the reading terminal 68d of the MPU 62. Details of these recognition and data output processes will be explained later.

The main CPU 63 is configured to periodically execute timer interrupt processing, but the generation of timer interrupt processing is prohibited when the main processing starts. This prohibition on timer interrupt processing is lifted after the processing in step S112 is completed and before the processing in step S113 is executed, at which point the execution of timer interrupt processing is permitted. Therefore, once power is supplied to the main CPU 63, the timer interrupt processing will not be executed until the data output processing in step S112 is completed and before the processing in step S113 begins. Consequently, the processing necessary to advance the game will not start in the main CPU 63 until this situation occurs.

Subsequently, the process proceeds to the residual processing steps S113 to S116. In other words, although the main CPU 63 is configured to periodically execute timer interrupt processing, residual time occurs between one timer interrupt processing and the next. This residual time varies depending on the processing completion time of each timer interrupt processing, and the residual processing steps S113 to S116 are repeatedly executed using this irregular time. In this respect, the residual processing steps S113 to S116 can be considered an irregular process that is executed irregularly.

In the remaining processing, first, in step S113, the interrupt disable setting is performed to prevent the occurrence of timer interrupt processing. In the following step S114, a random number initial value update process is executed to update the random number initial value counter CINI, and in step S115, a variation counter update process is executed to update the variation type counter CS. These update processes read the current numerical information from the corresponding counter in the main RAM 65, increment the read numerical information by 1, and then overwrite the original counter. In this case, if the counter value exceeds the maximum value, it is cleared to "0". Then, in step S116, the interrupt enable setting is performed to switch from a state where timer interrupt processing is prohibited to a state where it is enabled. If the process in step S116 is executed, the process returns to step S113, and steps S113 to S116 are repeated.

On the other hand, if the setting key insertion unit 68a is turned ON (step S103: YES), all areas of the main RAM 65, including the area where setting value information indicating the setting state of the pachinko machine 10 is set, are cleared to "0," and initial settings are performed on the areas that were cleared to "0" (step S117). In other words, if an operation to change the setting state of the pachinko machine 10 is being performed, even if the reset button 68c is not pressed, all areas of the main RAM 65 are cleared to "0," and initial settings are performed on the memory areas where the clearing process was executed. Furthermore, in step S117, various registers of the main CPU 63 are also cleared to "0" before initial settings are performed. However, this is not the only configuration; even if an operation to change the setting state of the pachinko machine 10 is being performed, if the reset button 68c is not pressed, the entire clear process of the main RAM 65 is not executed. The entire clear process is executed only when an operation to change the setting state of the pachinko machine 10 is being performed and the reset button 68c is pressed.

Subsequently, the setting value update process is executed in step S118, and the setting value update signal output process is executed in step S119, after which the process proceeds to step S110. The setting value update process will be described below. The setting value update signal output process will be explained in detail later. Figure 10 is a flowchart of the setting value update process.

First, the setting value counter in the main RAM 65 is set to "1" (step S201). The setting value counter is used by the main CPU 63 to determine which setting value the pachinko machine 10 is currently using. When "1" is set in the setting value counter, the setting value becomes "Setting 1" regardless of the previous setting value when the setting value update process is executed.

Subsequently, the process for starting the display of the set value is executed (step S202). During this process, the display control of the third notification display device 69c is performed so that the number "1" corresponding to "Setting 1" is displayed. The administrator of the amusement hall can understand the current setting status of the pachinko machine 10 by checking the third notification display device 69c when changing the set value.

Subsequently, assuming that the setting key insertion unit 68a is not in the OFF position (step S203: NO), it is determined whether the update button 68b has been pressed once (step S204). Specifically, it is determined whether the signal from the sensor detecting the press operation of the update button 68b has switched from a LOW level to a HI level. If a negative result is obtained in step S204, the process returns to step S203, and it is determined whether the setting key insertion unit 68a is in the OFF position.

If the update button 68b is pressed once (step S204: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S205). Furthermore, if the value of the setting value counter exceeds "6" after the increment (step S206: YES), the setting value counter is set to "1" (step S207). As a result, each time the update button 68b is pressed, the setting value is updated to the next higher level, and if the update button 68b is pressed once while the setting is "6", it returns to "1".

If a negative result is obtained in step S206, or if the process in step S207 is executed, the setting value display update process is executed (step S208). In the setting value display update process, the third notification display device 69c is controlled to display a number corresponding to the value of the setting value counter in the main RAM 65. The administrator of the amusement hall can understand the setting status of the pachinko machine 10 after pressing the update button 68b by checking the third notification display device 69c.

After executing the process in step S208, the process returns to step S203 to determine whether the setting key insertion unit 68a is in the OFF position. If it is not in the OFF position (step S203: NO), the processes from step S204 onwards are executed again. If it is in the OFF position (step S203: YES), the setting value display termination process is executed (step S209). In the setting value display termination process, the display of the setting value on the third notification display device 69c is terminated.

<Timer interrupt handling>
Next, the timer interrupt handling process will be explained with reference to the flowchart in Figure 11. The timer interrupt handling process is executed periodically (for example, every 4 milliseconds).

First, the power outage information storage process is executed (step S301). During the power outage information storage process, the system monitors whether a power outage signal corresponding to a power interruption has been received from the power outage monitoring board 67. If a power outage is detected, the system executes the power outage processing, which then enters an infinite loop. During the power outage processing, the power outage flag in the main RAM 65 is set to "1," a checksum is calculated, and the calculated checksum is saved.

Subsequently, the random number generation update process for the lottery is executed (step S302). This process updates the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal electric device release counter C4. Specifically, the current numerical information is sequentially read from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal electric device release counter C4. After incrementing each of these read values by 1, the original counters are overwritten. In this case, if the counter value exceeds the maximum value, it is cleared to "0". Then, in step S303, the random number initial value update process is executed similarly to step S114, and in step S304, the variable counter update process is executed similarly to step S115.

Subsequently, a fraud detection process is executed (step S305) to monitor whether a predetermined event, which is set as a target for monitoring fraud, has occurred. This fraud detection process monitors for the occurrence of multiple types of events and, upon confirming that a predetermined event has occurred, sets the game stop flag in the main RAM 65 to "1". In the following step S306, it is determined whether the game has stopped by checking whether the game stop flag is set to "1". If the determination in step S306 is negative, the processes from step S307 onwards are executed.

In step S307, port output processing is executed. During port output processing, if output information was set in the previous timer interrupt processing, processing is performed to output the corresponding information to the various drive units 32b and 34b. For example, if information is set to switch the special electric prize device 32 to the open state, the output of a drive signal to the special electric drive unit 32b is started; if information is set to switch it to the closed state, the output of the drive signal is stopped. Similarly, if information is set to switch the regular electric mechanism 34a of the second operating port 34 to the open state, the output of a drive signal to the regular electric drive unit 34b is started; if information is set to switch it to the closed state, the output of the drive signal is stopped.

Subsequently, a reading process is performed (step S308). During the reading process, signals other than the power outage signal and the winning signal are read, and the read information is stored for use in subsequent processing.

Subsequently, the ball entry detection process is executed (step S309). In this ball entry detection process, signals received from each ball entry detection sensor 42a to 49a are read, and based on the reading results, the presence or absence of a ball entering the out gate 24a, general prize gate 31, special electric prize device 32, first operation gate 33, second operation gate 34, and through gate 35 is determined. Details of the ball entry detection process will be explained later.

Subsequently, a timer update process is executed to update the numerical information of multiple types of timer counters located in the main RAM 65 (step S310). In this case, the configuration aggregates and handles timer counters whose stored numerical information is updated by subtraction; however, a configuration that aggregates and performs updates for both subtraction-type and addition-type timer counters is also possible.

Subsequently, a launch control process is executed to control the launch of the game balls (step S311). While the launch operation to the launch control device 28 is ongoing, one game ball is launched every 0.6 seconds, which is a predetermined launch cycle. In the following step S312, as an input state monitoring process, based on the information read in the reading process of step S308, the system checks for disconnections in each ball entry detection sensor 42a to 49a and confirms that the game machine body 12 and the front door frame 14 are open.

Subsequently, a special feature and special electrical control process is executed to control the execution of the game rounds and the opening/closing execution mode (step S313). The special feature and special electrical control process will be explained in detail later.

Subsequently, the regular power control process is executed (step S314). In the regular power control process, if a prize is awarded at the through gate 35, a process is executed to acquire the regular power reserve information. If the regular power reserve information is stored, an opening determination is made for that reserve information. Furthermore, a process is executed to perform a regular power effect triggered by this opening determination. Also, based on the result of the opening determination, a process is executed to open and close the regular power mechanism 34a of the second operation port 34. In this case, if the support mode is low-frequency support mode, the corresponding process is executed; if the support mode is high-frequency support mode, the corresponding process is executed. Also, if the opening/closing execution mode is selected, the support mode becomes low-frequency support mode even if the previous support mode was high-frequency support mode.

In the subsequent step S315, based on the processing results of the preceding steps S313 and S314, output information is set to reflect the increase or decrease in the number of reserved items related to the special figure display unit 37a in the special figure reserved display unit 37b, and output information is set to reflect the increase or decrease in the number of reserved items related to the general figure display unit 38a in the general figure reserved display unit 38b. Furthermore, in step S315, based on the processing results of the preceding steps S313 and S314, output information is set to update the display content of the special figure display unit 37a, and output information is set to update the display content of the general figure display unit 38a.

Subsequently, the system checks the contents of the commands and signals received from the payout control device 77 and executes a payout status reception process to perform processing corresponding to the confirmation results (step S316). It also executes a payout output process to set the prize ball command as the output target (step S317). Furthermore, it executes an external information setting process to control the start and end of the output of external signals according to the processing results of the various processes executed in this timer interrupt process (step S318). Finally, it executes a management output process to output information corresponding to the ball entry results in the game area PA to the management IC 66 (step S319). Details of the management output process will be explained later.

Next, the special electrical control process in step S313 will be explained with reference to the flowchart in Figure 12.

First, the process for acquiring pending information is executed (step S401). In the process for acquiring pending information, it is determined whether or not a prize has been won in the first operation port 33 or the second operation port 34. If a prize has been won, it is determined whether or not the number of pending items in the pending storage area 65a is less than the upper limit (in this embodiment, "4"). If the number of pending items is less than the upper limit, the number of pending items is increased by 1, and the numerical information of the winning random number counter C1, the big win type counter C2, and the reach random number counter C3, which were updated in the previous step S302, is stored in the first pending area among the empty pending areas RE1 to RE4 of the pending area RE. If prizes are won in both the first operation port 33 and the second operation port 34 simultaneously, the process for acquiring the pending information is executed multiple times within the time frame in which the process for acquiring pending information is executed once. In addition, if new pending information is acquired, the corresponding acquisition command is transmitted to the voice and light emission control device 81. When the audio and light emission control device 81 receives the command, it updates the image displayed on the pattern display device 41, which shows the number of pending information items, to reflect the increase in pending information.

Subsequently, the information from the special-function counter located in the main RAM 65 is read (step S402), and the special-function address table located in the main ROM 64 is read (step S403). Then, the starting address corresponding to the information from the special-function counter is obtained from the special-function address table (step S404), and the system jumps to the process indicated by the obtained starting address among the processes in steps S406 to S412 (step S405). The special-function counter is a counter used by the main CPU 63 to determine which of the various processes in steps S406 to S412 should be executed, and the special-function address table contains the starting addresses of the programs for executing the processes in steps S406 to S412, corresponding to the numerical information from the special-function counter.

Step S406 executes the special feature variation start process. Figure 13 is a flowchart of the special feature variation start process.

In the special feature variation start process, the data setting process is executed (step S502) on the condition that the number of reserved information stored in the reserved area RE is 1 or more (step S501: YES). In the data setting process, first the number of reserved items is deducted by 1, and the data stored in the first reserved area RE1 of the reserved area RE is moved to the execution area AE. After that, a process is executed to shift the data stored in each reserved area RE1 to RE4 of the reserved area RE. This data shift process shifts the data stored in the first reserved area RE1 to the fourth reserved area RE4 sequentially to the lower areas. Specifically, the data in each area is shifted as follows: second reserved area RE2 → first reserved area RE1, third reserved area RE3 → second reserved area RE2, fourth reserved area RE4 → third reserved area RE3, and so on, before clearing the fourth reserved area RE4 to "0". At this time, a shift command is sent to the voice light emission control device 81 to recognize that the data in the reserved areas has been shifted. When the audio and light emission control device 81 receives the command, it updates the image displayed on the pattern display device 41, which shows the number of pending information items, to reflect the decrease in pending information.

After executing the data setting process, the win/loss tables are read from the main ROM 64 (step S503). Specifically, the current win/loss lottery mode is first determined by reading the information indicating the win/loss lottery mode from the main RAM 65. If it is the high probability mode, the high probability win/loss table 64g is read from the main ROM 64. On the other hand, if it is the low probability mode, the setting status of the pachinko machine 10 is determined by reading the value of the setting value counter in the main RAM 65. Then, the low probability win/loss tables 64a to 64f corresponding to the determined setting value are read from the main ROM 64.

Subsequently, the system executes a win/failure determination process (step S504) by referring to the win/failure tables 64a to 64g read in step S503. In the win/failure determination process, it is determined whether the information used for win/failure determination, i.e., the numerical information related to the winning random number counter C1, stored in the execution area AE, matches the jackpot numerical information set in the win/failure tables 64a to 64g read in step S503.

If the result of the win/loss determination process is a jackpot win (Step S505: YES), the distribution determination process is executed (Step S506). In the distribution determination process, the information for distribution determination, specifically the numerical information related to the jackpot type counter C2, is read from the information stored in the execution area AE. Then, by referring to the distribution table 64h provided in the main ROM 64, it is determined which jackpot result the read numerical information related to the jackpot type counter C2 corresponds to. Specifically, it is determined which jackpot result corresponds to: a low-probability jackpot result, a low-winning high-probability jackpot result, or a most advantageous jackpot result.

Subsequently, the process for setting the stop result for the jackpot is executed (step S507). Specifically, the information regarding the pattern of symbols to be ultimately displayed on the special symbol display unit 37a during the current game round is identified from the jackpot result stop result table pre-stored in the main ROM 64, and this identified information is written to the main RAM 65. This jackpot result stop result table contains information on the pattern of symbols to be displayed on the special symbol display unit 37a, with different settings for each type of jackpot result.

Subsequently, a flag setting process corresponding to the distribution determination result is executed (step S508). Specifically, the main RAM 65 is equipped with flags corresponding to each type of jackpot result, and in step S508, the flag corresponding to the result of the distribution determination process in step S506 is set to "1".

On the other hand, if it is determined in step S505 that the result is not a jackpot, the stop result setting process for a losing result is executed (step S509). Specifically, the information of the pattern of symbols to be ultimately displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from the stop result table for losing results that is pre-stored in the main ROM 64, and this identified information is written to the main RAM 65. The information of the pattern of symbols selected in this case is different from the information of the pattern of symbols selected in the case of a jackpot.

After executing either step S508 or step S509, the process for determining the duration of the game round is executed (step S510). This process acquires the numerical information of the variation type counter CS. It also determines whether a reach display occurs on the symbol display device 41 during the current game round. Specifically, if the game round related to the start of the variation results in a low-probability jackpot or a most advantageous jackpot, it is determined that a reach display will occur. Furthermore, if neither jackpot result occurs, and the numerical information related to the reach random number counter C3 stored in the execution area AE corresponds to the occurrence of a reach, it is determined that a reach display will occur.

If it is determined that a "reach" (winning combination) display will occur, the duration of the game rounds corresponding to the numerical information of the current variation type counter CS is obtained by referring to the "reach occurrence duration table" stored in the main ROM 64. On the other hand, if it is determined that a "reach" display will not occur, the duration of the game rounds corresponding to the numerical information of the current variation type counter CS is obtained by referring to the "non-reach occurrence duration table" stored in the main ROM 64. Incidentally, the duration of the game rounds that can be obtained by referring to the non-reach occurrence duration table is different from the duration of the game rounds that can be obtained by referring to the reach occurrence duration table.

Furthermore, the duration of game rounds when a reach does not occur is set so that the more reserve information stored in the reserve area RE, the shorter the duration of game rounds. Also, in the case of high-frequency support mode, the duration of game rounds when the number of reserve information is the same is selected, compared to the case of low-frequency support mode, and the duration of game rounds when a reach does not occur is set to select a shorter duration. However, this is not limited to this; the duration of game rounds may not change depending on the number of reserve information or the support mode, and the relationship may be reversed. Furthermore, the above configuration may also be applied to the duration of game rounds when a reach occurs. Additionally, separate duration tables may be set for each type of jackpot result, including cases of a losing reach and cases of a losing result where a reach does not occur. In this case, the duration of game rounds will be distributed according to each game result.

Subsequently, the information on the duration of the game round acquired in step S510 is set in the special symbol timer counter provided in the main RAM 65 (step S511). The numerical information set in the special symbol timer counter is updated in the timer update process (step S310). Incidentally, as part of the game round's presentation, the special symbol display unit 37a displays the changing symbols, and the symbol display device 41 displays the changing symbols. When each of these changing symbol displays finishes, the game round's stop result is displayed (in the symbol display device 41, a predetermined combination of symbols is waiting on the active line) for a final stop period (for example, 0.5 seconds). In this case, the duration of the game round acquired in step S510 is the total time for one game round.

Subsequently, the variation command and the type command are transmitted to the voice and light emission control device 81 (step S512). The variation command includes information on the duration of the game round. Here, as described above, the duration of the game round obtained by referring to the non-reach duration table differs from the duration of the game round obtained by referring to the reach duration table. Therefore, even if the variation command does not include information on whether a reach occurred, the voice and light emission control device 81 can determine whether a reach occurred from the game round duration information. In this respect, it can be said that the variation command contains information indicating whether a reach occurred. Note that the variation command may also directly include information indicating whether a reach occurred. Furthermore, the type command includes information on the game result.

When the audio and light emission control device 81 receives a variation command and a type command from the main CPU 63, it causes the display light emission unit 53, the speaker unit 54, and the symbol display device 41 to execute a game-specific animation. In this case, the game-specific animation is performed in a manner corresponding to the content of the variation command and the type command. Furthermore, the symbol display device 41 displays a variation of symbols as part of the game-specific animation, and when the game-specific animation ends, the combination of symbols corresponding to the results of the win/fail judgment process and the distribution judgment process is displayed in a stopped state.

Subsequently, the display of the changing symbols in the special symbol display unit 37a is started (step S513). Then, the special symbol special electric counter is incremented by 1 (step S514). In this case, since the numerical information of the special symbol special electric counter is "0" when the special symbol variation start process is executed, the numerical information of the special symbol special electric counter becomes "1". After that, the 11th output flag provided in the main side RAM 65 is set to "1" (step S515). The 11th output flag is a flag used by the main side CPU 63 to specify that the management IC 66 should output information indicating that a game round has started.

Returning to the explanation of the special symbol and special electric control processing (Figure 52), step S407 executes the special symbol variation processing. During the special symbol variation processing, it is determined whether the timing is within the duration of the game round but before the final stop display. If it is before the final stop display, processing is executed to regularly change the display pattern of the symbols on the special symbol display unit 37a. When it is time to display the final stop, the numerical information of the special symbol and special electric counter is incremented by 1, updating the counter's numerical information from that corresponding to the special symbol variation processing to that corresponding to the special symbol confirmation processing. In this embodiment, the final stop command is not transmitted from the main CPU 63 to the sound and light emission control device 81.

In step S408, the special symbol confirmation process is executed. During this process, the display mode of the symbols on the special symbol display unit 37a is changed to the display mode corresponding to the lottery result of the current game round. Furthermore, the special symbol confirmation process determines whether the final stop period has elapsed. If it has, it determines whether a transition to the opening/closing execution mode occurs. If a transition to the opening/closing execution mode does not occur, the numerical information of the special symbol special electric counter is cleared to "0". If a transition to the opening/closing execution mode occurs, the numerical information of the special symbol special electric counter is incremented by 1, updating the counter's numerical information from that corresponding to the special symbol confirmation process to that corresponding to the special electric start process.

In step S409, the special electric start process is executed. If the process for starting the opening period in the current opening/closing execution mode has not yet been executed, the opening period setting process is executed. An opening command is also transmitted to the sound and light emission control device 81. Upon receiving the opening command, the sound and light emission control device 81 causes the opening animation to be executed on the display and light emission unit 53, the speaker unit 54, and the symbol display device 41. If the opening period has elapsed, a start process is executed to begin the first round of gameplay. This start process opens the special electric prize winning device 32 and sets the end conditions for the round of gameplay. When setting these end conditions, the maximum duration for keeping the special electric prize winning device 32 open during the first round of gameplay is set, and the maximum number of game balls that can be awarded to the special electric prize winning device 32 during the first round of gameplay is set in the prize count counter provided in the main RAM 65.

In step S410, the special electric current open processing is executed. This processing determines whether the round game termination conditions have been met. If the termination conditions are met, the special electric current prize entry device 32 is closed. If the round game that has just finished is not the last round game executed, the value of the special electric current counter is incremented by 1, updating the counter's value from that corresponding to the special electric current open processing to that corresponding to the special electric current closed processing. If the round game that has just finished is the last round game executed, the value of the special electric current counter is incremented by 2, updating the counter's value from that corresponding to the special electric current open processing to that corresponding to the special electric current termination processing.

In step S411, the special electric mode closure process is executed. This process determines whether the interval period between round games has elapsed. The interval period is set when the previous round game ends. If the interval period has elapsed, the special electric mode entry device 32 is opened, and the round game termination conditions are set. Then, by subtracting 1 from the numerical information of the special electric mode counter, the numerical information of the counter is updated from the one corresponding to the special electric mode closure process to the one corresponding to the special electric mode open process.

In step S412, the special operation termination process is executed. If the process to initiate the ending period for the current opening/closing execution mode has not yet been performed, the ending period (e.g., 5 seconds) is set, and an ending command is transmitted to the sound and light emission control device 81. Upon receiving the ending command, the sound and light emission control device 81 causes the ending sequence to be executed on the display and light emission unit 53, the speaker unit 54, and the symbol display device 41. Once the ending period has elapsed, the win/loss lottery mode and support mode after the end of the opening/closing execution mode are set to the modes corresponding to the jackpot result that triggered the start of the current opening/closing execution mode.

Next, we will explain the configuration for the main CPU 63 to determine whether or not a game ball has entered the out gate 24a, the general prize gate 31, the special electric prize device 32, the first operation gate 33, the second operation gate 34, and the through gate 35, based on the detection results of each ball entry detection sensor 42a to 49a. Figure 14 is an explanatory diagram illustrating the configuration in which the detection results of the ball entry detection sensors 42a to 49a are input to the main CPU 63.

The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface to handle eight types of signals simultaneously. Each terminal has a corresponding area where information ("0" or "1") is stored according to the voltage of each signal. Specifically, this area comprises bits D0 through D7. Although more than eight types of signals may be input to the input port 63a, the group of signals input to the input port 63a is switched via switching control by a driver IC to limit the number of signals simultaneously input to eight.

In the timer interrupt processing (Figure 11), during the ball entry detection processing (step S309), the group of signals to be input to the input port 63a is set to the group of signals from each ball entry detection sensor 42a to 49a. In this setting, the 0th bit D0 stores information corresponding to the detection signal from the 1st prize entry detection sensor 42a, the 1st bit D1 stores information corresponding to the detection signal from the 2nd prize entry detection sensor 43a, the 2nd bit D2 stores information corresponding to the detection signal from the 3rd prize entry detection sensor 44a, the 3rd bit D3 stores information corresponding to the detection signal from the special electric detection sensor 45a, the 4th bit D4 stores information corresponding to the detection signal from the 1st operation entry detection sensor 46a, the 5th bit D5 stores information corresponding to the detection signal from the 2nd operation entry detection sensor 47a, the 6th bit D6 stores information corresponding to the detection signal from the out entry detection sensor 48a, and the 7th bit D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

Each of the ball entry detection sensors 42a to 49a outputs a LOW level signal indicating no detection when it does not detect the passage of a game ball, and a HI level signal indicating detection when it does detect the passage of a game ball. The input port 63a stores "0" information in the corresponding bit when it receives a LOW level signal, and "1" information in the corresponding bit when it receives a HI level signal. In other words, when the ball entry detection sensors 42a to 49a do not detect the passage of a game ball, "0" information corresponding to the no detection information is stored in the corresponding bit, and when the passage of a game ball is detected, "1" information corresponding to the detection information is stored in the corresponding bit.

Figure 15 is a flowchart showing the ball entry detection process executed in step S309 of the timer interrupt processing (Figure 11).

When it is confirmed that the state in the 0th bit D0 has switched from storing the information "0" to storing the information "1", the first prize-winning slot detection sensor 42a determines that one game ball has been detected (step S601: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S602), and the value of the 10-ball payout counter provided in the main RAM 65 is incremented by 1 (step S603). The first output flag is a flag used by the main CPU 63 to determine that the management IC 66 should output information indicating that one game ball has been detected by the first prize-winning slot detection sensor 42a. The 10-ball payout counter is a counter used by the main CPU 63 to determine the number of times the payout of 10 game balls should be performed. If the value of the 10-prize ball counter is 1 or greater, the payout output process in step S317 of the timer interrupt processing (Figure 11) outputs a 10-prize ball command to the payout control device 77, and the value of the 10-prize ball counter is decremented by 1 each time the 10-prize ball command is output. Upon receiving the 10-prize ball command, the payout control device 77 drives and controls the payout device 76 to dispense 10 game balls.

When it is confirmed that the information stored in the first bit D1 has switched from "0" to "1", the second prize-winning slot detection sensor 43a determines that one game ball has been detected (step S604: YES). In this case, the second output flag provided in the main RAM 65 is set to "1" (step S605), and the value of the 10-ball prize counter provided in the main RAM 65 is incremented by 1 (step S606). The second output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the second prize-winning slot detection sensor 43a.

When it is confirmed that the second bit D2 has switched from storing "0" to storing "1", the third prize-winning slot detection sensor 44a determines that one game ball has been detected (step S607: YES). In this case, the third output flag provided in the main RAM 65 is set to "1" (step S608), and the value of the 10-ball prize counter provided in the main RAM 65 is incremented by 1 (step S609). The third output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the third prize-winning slot detection sensor 44a.

When it is confirmed that the third bit D3 has switched from storing the information "0" to storing the information "1", the special electric detection sensor 45a determines that one game ball has been detected (step S610: YES). In this case, the special electric prize flag provided in the main RAM 65 is set to "1" (step S611), the fourth output flag provided in the main RAM 65 is set to "1" (step S612), and the value of the 15-ball prize counter provided in the main RAM 65 is incremented by 1 (step S613). The special electric prize flag is a flag used by the main CPU 63 to identify that one game ball has entered the special electric prize device 32 during a round game in the opening/closing execution mode. In the timer interrupt processing (Figure 11), the special electric control processing (step S313) confirms that the special electric prize entry flag is set to "1", thereby identifying that one game ball has entered the special electric prize entry device 32, and the remaining number of balls that can enter the special electric prize entry device 32 in a round of play is reduced by 1. When this process of reducing the number of balls that can enter by 1 is executed, the special electric prize entry flag is cleared to "0". The fourth output flag is a flag used by the main CPU 63 to identify that the management IC 66 should output information indicating that one game ball has been detected by the special electric detection sensor 45a. The 15-ball prize counter is a counter used by the main CPU 63 to identify the number of times that 15 game balls should be dispensed. If the value of the 15-prize ball counter is 1 or greater, the payout output process in step S317 of the timer interrupt processing (Figure 11) outputs a 15-prize ball command to the payout control device 77, and the value of the 15-prize ball counter is decremented by 1 each time the 15-prize ball command is output. Upon receiving the 15-prize ball command, the payout control device 77 drives and controls the payout device 76 to dispense 15 game balls.

When it is confirmed that the information stored in the fourth bit D4 has switched from "0" to "1", the first operation port detection sensor 46a determines that one game ball has been detected (step S614: YES). In this case, the first operation entry flag provided in the main RAM 65 is set to "1" (step S615), the fifth output flag provided in the main RAM 65 is set to "1" (step S616), and the value of the one-ball prize counter provided in the main RAM 65 is incremented by 1 (step S617). The first operation entry flag is a flag used by the main CPU 63 to identify that one game ball has entered the first operation port 33. In the timer interrupt processing (Figure 11), the special feature special electric control processing (step S313) confirms that the first operation prize flag is set to "1", and if the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of 4, the processing to newly store reserved information is executed. In the special electric electric control processing (step S313), if it is confirmed that the first operation prize flag is set to "1" and the processing corresponding to that confirmation is executed, the first operation prize flag is cleared to "0". The fifth output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the first operation port detection sensor 46a. The single prize ball counter is a counter used by the main CPU 63 to specify the number of times that one game ball should be dispensed. If the value of the single-prize ball counter is 1 or greater, the payout output process in step S317 of the timer interrupt processing (Figure 11) outputs a single-prize ball command to the payout control device 77, and the value of the single-prize ball counter is decremented by 1 each time the single-prize ball command is output. Upon receiving the single-prize ball command, the payout control device 77 drives and controls the payout device 76 to dispense one game ball.

When it is confirmed that the information stored in the 5th bit D5 has switched from "0" to "1", the second operation port detection sensor 47a determines that one game ball has been detected (step S618: YES). In this case, the second operation entry flag provided in the main RAM 65 is set to "1" (step S619), the 6th output flag provided in the main RAM 65 is set to "1" (step S620), and the value of the one-ball prize counter provided in the main RAM 65 is incremented by 1 (step S621). The second operation entry flag is a flag used by the main CPU 63 to identify that one game ball has entered the second operation port 34. In the timer interrupt processing (Figure 11), the special feature control processing (step S313) confirms that the second operation winning flag is set to "1". This confirms that the number of reserved information items stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of 4. Based on this condition, the process of storing new reserved information is executed. In the special electric control processing (step S313), if the second operation winning flag is confirmed to be set to "1" and the corresponding processing is executed, the second operation winning flag is cleared to "0". The sixth output flag is used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the second operation port detection sensor 47a.

When it is confirmed that the state in the 6th bit D6 has switched from storing "0" to storing "1", the out-port detection sensor 48a determines that one game ball has been detected (step S622: YES). In this case, the 7th output flag provided in the main RAM 65 is set to "1" (step S623). The 7th output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the out-port detection sensor 48a.

When it is confirmed that the information stored in the 7th bit D7 has switched from "0" to "1", the gate detection sensor 49a determines that one game ball has been detected (step S624: YES). In this case, the gate entry flag provided in the main RAM 65 is set to "1" (step S625). The gate entry flag is a flag used by the main CPU 63 to identify that one game ball has entered the through gate 35. In the regular power control processing (step S314) of the timer interrupt processing (Figure 11), by confirming that the gate entry flag is set to "1", and provided that the number of regular-side reserve information stored in the regular power reserve area 65c is less than the upper limit of 4, the current numerical information of the regular power mechanism release counter C4 is stored in the regular power reserve area 65c as regular-side reserve information. In the general power control process (step S314), it is confirmed that the gate entry flag is set to "1". If the process corresponding to this confirmation is executed, the gate entry flag is cleared to "0".

As explained earlier, the timer interrupt processing (Figure 11) is activated at a 4-millisecond cycle. Therefore, when one ball detection sensor 42a-49a starts detecting one game ball, the main CPU 63 identifies that one game ball has been detected by that sensor while it continues to detect that single game ball. Thus, it is sufficient to have one of each of the first to seventh output flags.

Next, we will explain the processing performed by the dispensing control device 77. First, we will explain the electrical configuration of the dispensing control device 77 and the various devices that communicate with it, referring to the block diagram in Figure 16.

The dispensing control device 77 is equipped with an MPU 91. The MPU 91 includes a dispensing-side CPU 92, which is an arithmetic processing unit including a control unit and an arithmetic unit, as well as a dispensing-side ROM 93, dispensing-side RAM 94, interrupt circuits, timer circuits, data input/output circuits, and other components.

The dispensing-side ROM 93 is a memory (i.e., a non-volatile storage means) that does not require external power supply for storage, such as NOR-type flash memory and NAND-type flash memory, and is used in read-only mode. The dispensing-side ROM 93 stores various control programs and fixed value data executed by the dispensing-side CPU 92.

The dispensing-side RAM 94 is a memory (i.e., volatile memory) that requires external power supply for storage, such as SRAM and DRAM, and is used for both reading and writing. The dispensing-side RAM 94 allows random access and, when compared with the same data capacity, has a faster read time than the dispensing-side ROM 93. The dispensing-side RAM 94 temporarily stores various data for the execution of the control program stored in the dispensing-side ROM 93.

The payout-side CPU 92 is capable of bidirectional communication with the main-side CPU 63. Upon receiving a prize ball command from the main-side CPU 63, the payout-side CPU 92 drives and controls the payout device 76 to dispense the number of game balls corresponding to that prize ball command. The payout-side CPU 92 also monitors whether it is possible to dispense game balls normally, and if it determines that it is not possible, it stops the payout device 76, even if the payout-side RAM 94 stores information about the number of undispensed prize balls. Furthermore, the payout-side CPU 92 sends a payout restriction command to the main-side CPU 63 indicating that it is not possible to dispense game balls normally. Upon receiving this payout restriction command, the main-side CPU 63 sends a notification command to the sound and light emission control device 81 so that a notification indicating that it is not possible to dispense game balls normally is executed by the symbol display device 41, the display light emission unit 53, and the speaker unit 54. The following states make it impossible to dispense game balls normally: a full state where the lower tray 56a is completely filled with game balls; a state where the tank 75 is empty and no game balls have been replenished; a payout abnormal state where the payout device 76 does not operate normally; a state where the game machine body 12 is detached from the outer frame 11; and a state where the front door frame 14 is detached from the inner frame 13.

A full-tank detection sensor (not shown) is installed at an intermediate position in the game ball passage leading from the payout device 76 to the lower tray 56a. The detection result from this full-tank detection sensor is input to the payout-side CPU 92. The payout-side CPU 92 identifies the machine as full when the full-tank detection sensor continuously detects game balls, and identifies the machine as no longer full when the full-tank detection sensor stops continuously detecting game balls.

A ball-less detection sensor (not shown) is installed at an intermediate position in the game ball passage leading from tank 75 to the payout device 76. The detection result from this ball-less detection sensor is input to the payout-side CPU 92. The payout-side CPU 92 identifies a ball-less state when no game balls are continuously detected by the ball-less detection sensor, and identifies the ball-less state as being resolved when the ball-less detection sensor no longer detects any game balls.

The dispensing device 76 is equipped with a dispensing detection sensor (not shown) for detecting game balls dispensed from the dispensing device 76, and the detection result of the dispensing detection sensor is input to the dispensing-side CPU 92. The dispensing-side CPU 92 determines that one game ball has been dispensed from the dispensing device 76 when a game ball is detected by the dispensing detection sensor. Furthermore, the dispensing-side CPU 92 determines that a dispensing abnormality is occurring if the dispensing device 76 is being driven and controlled to dispense game balls, but no game balls are continuously detected by the dispensing detection sensor. The dispensing abnormality is determined to have been resolved when the state of continuous non-detection of game balls by the dispensing detection sensor is resolved.

A front door open sensor 95 is provided on the front of the inner frame 13 (see Figure 2), and the detection result of the front door open sensor 95 is input to the dispensing side CPU 92. In this case, if the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 sends a closed detection signal to the dispensing side CPU 92, and if the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 sends an open detection signal to the dispensing side CPU 92. The dispensing side CPU 92 identifies the front door frame 14 as closed when it receives a closed detection signal from the front door open sensor 95, and identifies the front door frame 14 as open when it receives an open detection signal from the front door open sensor 95. Furthermore, the dispensing side CPU 92 sends a front door open command to the main side CPU 63 at the timing when it identifies that the front door frame 14 has changed from a closed state to an open state, and sends a front door closed command to the main side CPU 63 at the timing when it identifies that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in an open state when it receives a front door open command, and determines that the front door frame 14 is in a closed state when it receives a front door close command.

A main unit open sensor 96 is provided on the front of the back pack unit 15 (see Figure 2), and the detection result of the main unit open sensor 96 is input to the payout side CPU 92. In this case, when the gaming machine main unit 12 is closed relative to the outer frame 11, the main unit open sensor 96 transmits a closed detection signal to the payout side CPU 92, and when the gaming machine main unit 12 is open relative to the outer frame 11, the main unit open sensor 96 transmits an open detection signal to the payout side CPU 92. The payout side CPU 92 identifies the gaming machine main unit 12 as being in a closed state when it receives a closed detection signal from the main unit open sensor 96, and identifies the gaming machine main unit 12 as being in an open state when it receives an open detection signal from the main unit open sensor 96. Furthermore, when the payout side CPU 92 identifies that the gaming machine main unit 12 has changed from a closed state to an open state, it transmits a main unit open command to the main side CPU 63, and when it identifies that the gaming machine main unit 12 has changed from an open state to a closed state, it transmits a main unit closed command to the main side CPU 63. The main CPU 63 determines that the gaming machine body 12 is in an open state when it receives a body open command, and determines that the gaming machine body 12 is in a closed state when it receives a body close command.

Referring to the flowchart in Figure 17, the timer interrupt processing executed by the payout-side CPU 92 will be explained. The timer interrupt processing is repeatedly activated at a predetermined interval (for example, 2 milliseconds).

First, the full tank processing is executed (step S701). In the full tank processing, as already explained, the system determines whether the tank is full based on the detection result of the full tank detection sensor. If the tank is full, processing is executed to stop the payout of game balls, and a command indicating that the tank is full is sent to the main CPU 63. Furthermore, if the full tank state is released, processing is executed to enable the payout of game balls, and a command indicating that the full tank state has been released is sent to the main CPU 63.

Subsequently, the "no balls" processing is executed (step S702). In the "no balls" processing, as already explained, the system determines whether or not there are no balls based on the detection result of the ball detection sensor. If there are no balls, processing is performed to stop the payout of game balls, and a command indicating that there are no balls is sent to the main CPU 63. Furthermore, if the "no balls" state is resolved, processing is performed to enable the payout of game balls, and a command indicating that the "no balls" state has been resolved is sent to the main CPU 63.

Subsequently, the payout abnormality monitoring process is executed (step S703). In the payout abnormality monitoring process, as already explained, the system determines whether a payout abnormality is occurring based on the detection result of the payout detection sensor. If a payout abnormality is detected, the system executes a process to stop the payout of game balls and sends a command indicating the payout abnormality to the main CPU 63. Furthermore, if the payout abnormality is resolved, the system executes a process to enable the payout of game balls and sends a command indicating the payout abnormality has been resolved to the main CPU 63.

Subsequently, the front door open monitoring process is executed (step S704). In the front door open monitoring process, as already explained, the system determines whether the front door frame 14 is open based on the detection result of the front door open sensor 95. If the front door frame 14 is open, the system executes a process to stop the payout of game balls and sends a front door open command to the main CPU 63. If the front door frame 14 is closed, the system executes a process to enable the payout of game balls and sends a front door closed command to the main CPU 63.

Subsequently, the main unit open monitoring process is executed (step S705). In the main unit open monitoring process, as already explained, the system determines whether the gaming machine main unit 12 is in an open state based on the detection result of the main unit open sensor 96. If the gaming machine main unit 12 is in an open state, the system executes a process to stop the payout of game balls and sends a main unit open command to the main CPU 63. Furthermore, if the gaming machine main unit 12 is closed, the system executes a process to enable the payout of game balls and sends a main unit closed command to the main CPU 63.

Subsequently, a command reading process is executed (step S706). In this command reading process, a process is executed to read the prize ball command transmitted by the main CPU 63, and the prize ball command is stored in the payout RAM 94. Then, a prize ball setting process is executed to add the number corresponding to the received prize ball command to the unpaid prize ball count information in the payout RAM 94 (step S707), and then a payout control process is executed to control the execution of the payout of game balls by the payout device 76 (step S708). In the payout control process, if the unpaid prize ball count information stored in the payout RAM 94 is a value of 1 or more, the drive control of the payout device 76 is performed, and when one game ball is detected by the payout detection sensor, the value of the prize ball count information is deducted by 1. Then, when the value of the prize ball count information becomes "0", the drive control of the payout device 76 is stopped. Subsequently, an external information setting process is executed to control the start and end of the output of external signals according to the processing results of the various processes performed in this timer interrupt (step S709).

Next, we will explain the configuration for outputting information from the pachinko machine 10 to the hall computer HC installed in the gaming hall.

As shown in Figure 2, the back pack unit 15 is provided with an external terminal board 97. The external terminal board 97 has numerous external terminals; some of these terminals are electrically connected to the main CPU 63, and some of these terminals are electrically connected to the payout CPU 92. Because both the main CPU 63 and the payout CPU 92 are electrically connected to the external terminal board 97, as shown in Figure 16, the main CPU 63 and the payout CPU 92 can output information to the hall computer HC.

One external terminal on the external terminal board 97 is electrically connected to the front door open sensor 95, and another external terminal on the external terminal board 97 is electrically connected to the main unit open sensor 96. In detail regarding the configuration of this electrical connection, a signal relay board 98 is provided at an intermediate position in the signal path from the front door open sensor 95 to the payout-side CPU 92. This signal relay board 98 has a branch path SL2 that branches off from the signal path SL1 from the front door open sensor 95 to the payout-side CPU 92. This branch path SL2 is connected to the external terminal for front door opening on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result from the front door open sensor 95 is input not only to the payout-side CPU 92, but also to the external terminal for front door opening on the external terminal board 97. This makes it possible to output a signal indicating whether the front door frame 14 is open or not to the hall computer HC without control by the payout-side CPU 92.

Regarding the main unit opening sensor 96, the signal relay board 98 is provided with a branch path SL4 that branches off from the signal path SL3, which runs from the main unit opening sensor 96 to the payout-side CPU 92. This branch path SL4 is connected to the external terminal for main unit opening on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result from the main unit opening sensor 96 is input not only to the payout-side CPU 92 but also to the external terminal for main unit opening on the external terminal board 97. This makes it possible to output a signal indicating whether the gaming machine main unit 12 is in an open state to the hall computer HC without requiring control from the payout-side CPU 92.

Next, we will explain the content of the information output externally from the main CPU 63 and the payout CPU 92 to the hall computer HC. First, we will explain the content of the information output externally from the main CPU 63 to the hall computer HC.

The main CPU 63, in the external information setting process (step S318) of the timer interrupt processing (Figure 11), sets the output of information to each external terminal assigned to the main CPU 63 on the external terminal board 97. The information output from the main CPU 63 to the external terminal board 97 includes information indicating that the system is in open/close execution mode, information indicating that the support mode is in high-frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number of game balls (e.g., 100) have been ejected from the game area PA through one of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, or second operation port 34, information indicating that a game ball has entered the first operation port 33, and information indicating that a game ball has entered the second operation port 34.

In the timer interrupt processing (Figure 17), the payout-side CPU 92 performs external information setting processing (step S709) to configure the output settings for each external terminal assigned to the payout-side CPU 92 on the external terminal board 97. The information output from the payout-side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been dispensed.

The hall computer HC can understand the execution method of dispensing game balls in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example,
- The payout rate is the ratio of the number of game balls dispensed until 100 game balls are dispensed from the game area PA of the pachinko machine 10. - The payout rate in normal gameplay mode, excluding the opening/closing execution mode and high-frequency support mode (hereinafter, this payout rate will be referred to as "B").
- Payout rate in opening/closing execution mode - Payout rate in high-frequency support mode - Number of game rounds played until 100 game balls are dispensed from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S")
• B-S × "Number of prize balls awarded for winning in the first operating port 33 and the second operating port 34"
- The number of game balls that enter the first operating port 33 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S1").
- The number of game balls that enter the second operating port 34 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S2").
B - (S1 × "Number of prize balls awarded for winning in the first operating port 33" + S2 × "Number of prize balls awarded for winning in the second operating port 34")
- The probability of the opening/closing execution mode occurring per unit of game rounds, the probability of the high-frequency support mode occurring per unit of game rounds, etc. are calculated. This makes it possible for the hall computer HC to manage the way game balls enter the game area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls that are dispensed when one game ball enters the corresponding ball entry section.

<Configuration for managing the winning patterns of game balls>
Next, we will explain the configuration for managing game history using the management IC 66. First, we will explain the electrical configuration of the management IC 66, referring to the block diagram in Figure 18.

As already explained, the MPU 62 of the main control unit 60 includes a main CPU 63, main ROM 64, main RAM 65, and management IC 66. In addition, the MPU 62 also includes an I/F 101 and the read terminal 68d, as previously described.

The I/F 101 is an interface for sending and receiving signals between the MPU 62 and external devices. The I/F 101 is electrically connected to the main CPU 63 via the internal bus 103. Detection results from sensors such as the ball entry detection sensors 42a to 49a, and commands from the payout CPU 92 are input to the MPU 62 through the input port of the I/F 101. Based on the input detection results and commands, the main CPU 63 executes various processes as previously described. Furthermore, if the main CPU 63 executes various processes and outputs a signal to devices such as the special electric drive unit 32b, this signal output is performed through the output port of the I/F 101. Similarly, if the main CPU 63 executes various processes and outputs commands to the payout CPU 92 and the sound and light emission control device 81, these command outputs are also performed through the output port of the I/F 101.

The management IC 66 includes a management interface 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a correspondence memory 116, a history memory 117, and a calculation result memory 131. These devices are connected bidirectionally via an internal bus 66a provided on the management IC 66.

The management interface 111 receives various signals from the main CPU 63 via a unidirectional communication signal path group 118 built into the MPU 62, and transmits various signals to the read terminal 68d via a unidirectional communication signal path group 119 built into the MPU 62. The various signals from the main CPU 63 are input to the input port of the management interface 111, and the various signals to the read terminal 68d are output from the output port of the management interface 111. The main CPU 63 is electrically connected to the read terminal 68d via a bidirectional communication signal path group 120 built into the MPU 62.

The management CPU 112 is an arithmetic processing unit including a control unit and an arithmetic unit. The management ROM 113 is a memory (i.e., non-volatile storage means) such as NOR-type flash memory and NAND-type flash memory that does not require external power supply for storage, and is used for read-only purposes. The management ROM 113 stores various control programs and fixed value data executed by the management CPU 112. The management RAM 114 is a memory (i.e., volatile storage means) such as SRAM and DRAM that requires external power supply for storage, and is used for both read and write operations. The management RAM 114 allows random access and, when compared with the management ROM 113 for the same data capacity, has a faster read time. The management RAM 114 temporarily stores various data for the execution of control programs stored in the management ROM 113.

The RTC115 is a real-time clock that continuously measures date and time information and, in accordance with instructions from the management CPU 112, can output the measured date and time information (hereinafter also referred to as date and time information). The RTC115 is equipped with a backup power supply, allowing it to measure date and time information even when the power to the pachinko machine 10 is cut off.

The correspondence memory 116 is a memory (i.e., volatile memory) that requires external power supply for storage, such as SRAM and DRAM, and is used for both reading and writing. The correspondence memory 116 is used to store information regarding the correspondence between each buffer 122a to 122p provided at the input port 121 of the management interface 111 and the types of signals input to those buffers 122a to 122p. Details of the contents of the correspondence memory 116 will be explained later.

The history memory 117 is a memory (i.e., a non-volatile storage means) that does not require an external power supply for storage, such as NOR-type flash memory and NAND-type flash memory, and is used for both reading and writing. The history memory 117 is used to store information regarding the game history received from the main CPU 63 via the management interface 111. Details of the contents of the history memory 117 will be explained later.

The calculation result memory 131 is a memory (i.e., a non-volatile storage means) that does not require an external power supply for storage, such as NOR-type flash memory and NAND-type flash memory, and is used for both reading and writing. The calculation result memory 131 is used to sequentially store various parameters calculated by the management CPU 112 using the history information stored in the history memory 117. The contents of the various parameters stored in the calculation result memory 131 are sequentially displayed on the first to third notification display devices 69a to 69c and output to an external device connected to the reading terminal 68d.

Next, the configuration of the input port 121 provided on the management interface 111 will be described. Figure 19 is an explanatory diagram illustrating the configuration of the input port 121 of the management interface 111.

The input port 121 is provided with multiple buffers 122a to 122p. Specifically, the first to sixteenth buffers 122a to 122p are provided. Each of the first to sixteenth buffers 122a to 122p can receive one type of signal through signal paths 118a to 118p. Each of the first to sixteenth buffers 122a to 122p stores "0" as the first data when the input signal is at a LOW level, and "1" as the second data when the input signal is at a HI level. Note that the relationship between LOW and HI and the first and second data may be reversed.

The first buffer 122a receives a first signal corresponding to the detection result of the first prize-winning slot detection sensor 42a. In this case, the main CPU 63 outputs a LOW-level first signal when no new game balls are detected by the first prize-winning slot detection sensor 42a, and outputs a HI-level first signal for a specific period when one game ball is detected by the first prize-winning slot detection sensor 42a. This specific period is sufficient for the management CPU 112 to determine that a HI-level first signal has been input to the first buffer 122a.

The second buffer 122b receives a second signal corresponding to the detection result of the second prize-winning slot detection sensor 43a. In this case, the main CPU 63 outputs a LOW level second signal when no new game balls are detected by the second prize-winning slot detection sensor 43a, and outputs a HI level second signal for a specific period when one game ball is detected by the second prize-winning slot detection sensor 43a. This specific period is sufficient for the management CPU 112 to determine that a HI level second signal has been input to the second buffer 122b.

The third buffer 122c receives a third signal corresponding to the detection result of the third prize-winning slot detection sensor 44a. In this case, the main CPU 63 outputs a LOW-level third signal when no new game balls are detected by the third prize-winning slot detection sensor 44a, and outputs a HI-level third signal for a specific period when one game ball is detected by the third prize-winning slot detection sensor 44a. This specific period is sufficient for the management CPU 112 to determine that a HI-level third signal has been input to the third buffer 122c.

The fourth buffer 122d receives a fourth signal corresponding to the detection result of the special electric detection sensor 45a. In this case, the main CPU 63 outputs a LOW level fourth signal when no new game balls are detected by the special electric detection sensor 45a, and outputs a HI level fourth signal for a specific period when one game ball is detected by the special electric detection sensor 45a. This specific period is sufficient for the management CPU 112 to determine that a HI level fourth signal has been input to the fourth buffer 122d.

The fifth buffer 122e receives a fifth signal corresponding to the detection result of the first operation port detection sensor 46a. In this case, the main CPU 63 outputs a LOW level fifth signal when no new game balls are detected by the first operation port detection sensor 46a, and outputs a HI level fifth signal for a specific period when one game ball is detected by the first operation port detection sensor 46a. This specific period is sufficient for the management CPU 112 to determine that a HI level fifth signal has been input to the fifth buffer 122e.

The sixth buffer 122f receives the sixth signal corresponding to the detection result of the second operation port detection sensor 47a. In this case, the main CPU 63 outputs a LOW level sixth signal when no new game balls are detected by the second operation port detection sensor 47a, and outputs a HI level sixth signal for a specific period when one game ball is detected by the second operation port detection sensor 47a. This specific period is sufficient for the management CPU 112 to determine that a HI level sixth signal has been input to the sixth buffer 122f.

The seventh buffer 122g receives the seventh signal corresponding to the detection result of the out-port detection sensor 48a. In this case, the main CPU 63 outputs a LOW level seventh signal when no new game balls are detected by the out-port detection sensor 48a, and outputs a HI level seventh signal for a specific period when one game ball is detected by the out-port detection sensor 48a. This specific period is sufficient for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

The eighth buffer 122h receives the eighth signal, which corresponds to whether or not the system is in the open/close execution mode. In this case, the main CPU 63 continuously outputs the eighth signal at a LOW level when the system is not in the open/close execution mode, and continuously outputs the eighth signal at a HI level when the system is in the open/close execution mode.

The ninth buffer 122i receives the ninth signal, which indicates whether or not the system is in high-frequency support mode. In this case, the main CPU 63 continuously outputs a LOW level of the ninth signal when the system is not in high-frequency support mode, and continuously outputs a HI level of the ninth signal when the system is in high-frequency support mode.

The tenth buffer 122j receives a tenth signal corresponding to whether or not the front door frame 14 is open. In this case, the main CPU 63 continuously outputs a LOW level tenth signal when the front door frame 14 is closed, and continuously outputs a HI level tenth signal when the front door frame 14 is open.

The 11th buffer 122k receives the 11th signal, which corresponds to whether or not a game round has started. In this case, the main CPU 63 continuously outputs a LOW level 11th signal until the game round starts, and then outputs a HI level 11th signal for a specific period once the game round has started. This specific period is sufficient for the management CPU 112 to determine that a HI level 11th signal has been input to the 11th buffer 122k.

The 15th buffer 122o receives a setting value update signal from the main CPU 63 to inform the management CPU 112 that a new setting has been made for the pachinko machine 10. In this case, the main CPU 63 outputs a LOW-level setting value update signal if no new setting has been made for the pachinko machine 10. If a new setting has been made for the pachinko machine 10, the main CPU 63 outputs a pulse signal that maintains a HI-level setting value update signal for a specific period, corresponding to the newly set setting value. This specific period is sufficient for the management CPU 112 to determine that a HI-level setting value update signal has been input to the 15th buffer 122o.

The 16th buffer 122p receives an output instruction signal to the management CPU 112, which is used to signal the timing for outputting history information stored in the history memory 117 and various parameters stored in the calculation result memory 131 to the read terminal 68d. In this case, the main CPU 63 outputs a LOW-level output instruction signal when there is no need to output history information, and outputs a HI-level output instruction signal for a specific period when there is a need to output history information. This specific period is sufficient for the management CPU 112 to determine that a HI-level output instruction signal has been input to the 16th buffer 122p.

The 12th buffer 122l, the 13th buffer 122m, and the 14th buffer 122n are capable of receiving signals from the main CPU 63, but in this pachinko machine 10, they are blank and do not receive normal signals. In this way, more buffers 122a to 122p are provided as input ports 121 of the management I/F 111 than the number of signals output from the main CPU 63 to the management IC 66 in this pachinko machine 10, making it possible to reuse the management IC 66 in models other than this pachinko machine 10. This increases the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the main CPU 63 and each of the first to sixteenth buffers 122a to 122p, with a one-to-one correspondence between them. However, this is not limited to this configuration; a configuration where signal paths 118l to 118n are not formed between the CPU 63 and the buffers to be blanked (122l to 122n) is also possible.

The fact that a setting value update signal is input to the 15th buffer 122o and an output instruction signal is input to the 16th buffer 122p is determined during the design phase of the management IC 66. Therefore, the management CPU 112 can determine that a setting value update signal is input to the 15th buffer 122o and an output instruction signal is input to the 16th buffer 122p without receiving instructions from the main CPU 63. On the other hand, the types of signals input to the 1st to 14th buffers 122a to 122n are not determined during the design phase of the management IC 66. These signal types are determined by the management CPU 112 upon receiving instructions from the main CPU 63. The determination of these signal types in the management CPU 112 is performed, in detail later, by sending a signal type identification command from the main CPU 63 to the management CPU 112 when control is initiated in both the main CPU 63 and the management CPU 112 following the start of power supply to the MPU 62. In this case, the information on the types of signals provided by the type identification command is stored in the correspondence memory 116. When the management CPU 112 identifies the types of signals while operating power is supplied, the information stored in the correspondence memory 116 is referenced.

Figure 20 is an explanatory diagram illustrating the configuration of the correspondence memory 116. The correspondence memory 116 contains the first to 14 correspondence areas 123a to 123n, which are arranged in a one-to-one correspondence with the first to 14th buffers 122a to 122n provided at the input port 121 of the management interface 111.

The first correspondence area 123a stores information indicating that the signal input to the first buffer 122a is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal. In addition, the first correspondence area 123a also stores information (10 balls) indicating the number of game balls that will be dispensed when one game ball enters the general prize slot 31. The second correspondence area 123b stores information indicating that the signal input to the second buffer 122b is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal. In addition, the second correspondence area 123b also stores information (10 balls) indicating that the signal is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal input to the second buffer 122b. The third correspondence area 123c stores information indicating that the signal input to the third buffer 122c is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal. In addition, the third correspondence area 123c also stores information (10 balls) indicating the number of game balls dispensed when one game ball enters the general prize slot 31.

The fourth correspondence area 123d stores information indicating that the signal input to the fourth buffer 122d is the special electric prize winning device 32, which is used by the management CPU 112 to identify the type of signal. In addition, the fourth correspondence area 123d also stores information (15) indicating the number of game balls that will be dispensed when one game ball enters the special electric prize winning device 32. The fifth correspondence area 123e stores information indicating that the signal input to the fifth buffer 122e is the first operation port 33, which is used by the management CPU 112 to identify the type of signal. In addition, the fifth correspondence area 123e also stores information (1) indicating the number of game balls that will be dispensed when one game ball enters the first operation port 33. The sixth correspondence area 123f stores information indicating that the signal input to the sixth buffer 122f is the second operation port 34, which is used by the management CPU 112 to identify the type of signal. The sixth correspondence area 123f also stores information indicating that the signal is the second operation port 34, along with the number of game balls dispensed (1) when one game ball enters the second operation port 34. The seventh correspondence area 123g stores information indicating that the signal input to the seventh buffer 122g is the output port 24a, which is used by the management CPU 112 to identify the type of signal.

The eighth correspondence area 123h stores information indicating the open/close execution mode, which is used by the management CPU 112 to identify the type of signal input to the eighth buffer 122h. The ninth correspondence area 123i stores information indicating the high-frequency support mode, which is used by the management CPU 112 to identify the type of signal input to the ninth buffer 122i. The tenth correspondence area 123j stores information indicating the front door frame 14, which is used by the management CPU 112 to identify the type of signal input to the tenth buffer 122j. The eleventh correspondence area 123k stores information indicating the start of a game round, which is used by the management CPU 112 to identify the type of signal input to the eleventh buffer 122k.

The 12th correspondence area 123l stores information indicating that the signal input to the 12th buffer 122l is a blank, which is used by the management CPU 112 to identify the type of signal input to the 12th buffer 122l. The 13th correspondence area 123m stores information indicating that the signal input to the 13th buffer 122m is a blank, which is used by the management CPU 112 to identify the type of signal input to the 14th buffer 122n. The 14th correspondence area 123n stores information indicating that the signal input to the 14th buffer 122n is a blank, which is used by the management CPU 112 to identify the type of signal input to the 14th buffer 122n.

As described above, by configuring the system so that the type of signal input to the first to fourteenth buffers 122a to 122n is determined by the management CPU 112 based on instructions from the main CPU 63, the management IC 66 can be reused in models other than this pachinko machine 10. This increases the versatility of the management IC 66.

Furthermore, instead of outputting information to recognize the type of signal each time a signal corresponding to the storage of history information is output to the first to fourteenth buffers 122a to 122n, this configuration outputs information to recognize the type of signal in advance, and based on that output information, information for the management CPU 112 to identify the type of signal input to the first to fourteenth buffers 122a to 122n is stored in the correspondence memory 116. This reduces the amount of information output from the main CPU 63 to the management CPU 112 each time a signal corresponding to the storage of history information is output to the first to fourteenth buffers 122a to 122n.

Furthermore, the output of information for identifying the types of signals input to the first to fourteenth buffers 122a to 122n by the management CPU 112 is performed when the power supply for operation begins. This allows the management CPU 112 to identify the types of signals input to the first to fourteenth buffers 122a to 122n when gameplay begins on the pachinko machine 10.

Furthermore, the information setting for the input of a setting value update signal to the 15th buffer 122o and the information setting for the input of an output instruction signal to the 16th buffer 122p are performed during the design phase of the management IC 66. This makes it possible to omit the processing required to identify the type of signal input to the 15th buffer 122o and the 16th buffer 122p for setting value update signals and output instruction signals that are reliably used not only in this pachinko machine 10 but also in other pachinko machines that utilize the management IC 66. Therefore, the processing load for identifying such signal types can be reduced.

Next, we will describe the history memory 117 of the management IC 66. Figure 21 is an explanatory diagram illustrating the configuration of the history memory 117.

The history memory 117 is provided with a history area 124 for sequentially storing history information. The history area 124 contains multiple pointer information entries numbered sequentially, and a history information storage area 125 is set up to correspond one-to-one with each pointer information entry. The history information storage area 125 can store combinations of RTC information and correspondence information. In this case, each history information storage area 125 has a data capacity of 2 bytes, with 1 byte allocated for storing RTC information and 1 byte allocated for storing correspondence information. When it becomes necessary to store correspondence information in response to signals input to the first to 14th buffers 122a to 122n (actually the first to 11th buffers 122a to 122k in the case of this pachinko machine 10), the date and time information currently measured by the RTC 115 is first stored in the RTC information storage area of the history information storage area 125 corresponding to the pointer information currently being written. Subsequently, the correspondence information corresponding to buffers 122a to 122n, which triggered the current information storage, is read from the correspondence areas 123a to 123n in the correspondence memory 116, and this read correspondence information is stored in the area of the history information storage area 125 that stores correspondence information corresponding to the currently written pointer information.

Specifically, regarding the correspondence information stored in the history information storage area 125, as already explained, the first to seventh buffers 122a to 122g receive signals corresponding to the detection results of the ball entry detection sensors 42a to 48a. Therefore, the first to seventh correspondence areas 123a to 123g in the correspondence memory 116 store information corresponding to the types of ball entry detection sensors 42a to 48a. More specifically, information corresponding to the type of ball entry section corresponding to each of the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g. In this pachinko machine 10, as already explained, the first to third prize entry detection sensors 42a to 44a all detect game balls that have entered the general prize entry area 31. Therefore, the first to third correspondence areas 123a to 123c corresponding to these first to third prize entry detection sensors 42a to 44a all store information indicating that it is the general prize entry area 31. Furthermore, the fourth correspondence area 123d stores information indicating that it is the special electric prize winning device 32, the fifth correspondence area 123e stores information indicating that it is the first operating port 33, the sixth correspondence area 123f stores information indicating that it is the second operating port 34, and the seventh correspondence area 123g stores information indicating that it is the out port 24a. If the buffers 122a to 122n that triggered the information storage in this case are any of the first to seventh buffers 122a to 122g, then the information on the type of ball entry area corresponding to that buffer 122a to 122g is read from one of the first to seventh correspondence areas 123a to 123g, and this read information on the type of ball entry area is stored directly in the area for storing correspondence information in the history information storage area 125.

On the other hand, the eighth buffer 122h receives a signal indicating whether or not it is in the opening/closing execution mode, the ninth buffer 122i receives a signal indicating whether or not it is in the high-frequency support mode, the tenth buffer 122j receives a signal indicating whether or not the front door frame 14 is open, and the eleventh buffer 122k receives a signal indicating whether or not a game round has started. Therefore, the eighth corresponding area 123h stores information indicating that it is in the opening/closing execution mode, the ninth corresponding area 123i stores information indicating that it is in the high-frequency support mode, the tenth corresponding area 123j stores information indicating that it is the front door frame 14, and the eleventh corresponding area 123k stores information indicating that it is a game round.

As previously explained, the main CPU 63 continuously outputs a LOW level 8th signal when not in open/close execution mode, and a HI level 8th signal when in open/close execution mode. Therefore, the management CPU 112 can determine that the open/close execution mode has started when the 8th signal changes from LOW to HI, and that the open/close execution mode has ended when the 8th signal changes from HI to LOW. In both cases, the management CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the 8th signal changes from LOW to HI, not only the information indicating that it is in open/close execution mode, read from the 8th correspondence area 123h, but also the start information is stored together in the area for storing correspondence information in the history information storage area 125. Furthermore, when the eighth signal changes from a HI level to a LOW level, not only the information indicating the opening/closing execution mode read from the eighth correspondence area 123h, but also the termination information is stored together in the area for storing correspondence information in the history information storage area 125.

As previously explained, the main CPU 63 continuously outputs the 9th signal at a LOW level when not in high-frequency support mode, and continuously outputs the 9th signal at a HI level when in high-frequency support mode. Therefore, the management CPU 112 can identify that high-frequency support mode has started when the 9th signal changes from a LOW level to a HI level, and that high-frequency support mode has ended when the 9th signal changes from a HI level to a LOW level. Furthermore, in both cases, when the 9th signal changes from a LOW level to a HI level, and when it changes from a HI level to a LOW level, the management CPU 112 identifies that an opportunity has arisen to store correspondence relationship information in the history information storage area 125. In other words, when the 9th signal changes from a LOW level to a HI level, not only the information indicating that it is in high-frequency support mode, read from the 9th correspondence relationship area 123i, but also the start information is stored together in the area for storing correspondence relationship information in the history information storage area 125. Furthermore, when the ninth signal changes from a HI level to a LOW level, not only the information indicating that it is in high-frequency support mode, read from the ninth correspondence area 123i, but also the termination information is stored together in the area for storing correspondence information in the history information storage area 125.

As previously explained, the main CPU 63 continuously outputs a LOW level 10th signal when the front door frame 14 is closed, and continuously outputs a HI level 10th signal when the front door frame 14 is open. Therefore, the management CPU 112 can determine that the front door frame 14 has been opened when the 10th signal changes from a LOW level to a HI level, and that the front door frame 14 has been closed when the 10th signal changes from a HI level to a LOW level. In both cases, the management CPU 112 determines that an event has occurred that triggers the storage of corresponding relationship information in the history information storage area 125. In other words, when the 10th signal changes from a LOW level to a HI level, not only the information indicating that it is the front door frame 14, read from the 10th correspondence area 123j, but also the opening start information is stored together in the area for storing correspondence information in the history information storage area 125. Similarly, when the 10th signal changes from a HI level to a LOW level, not only the information indicating that it is the front door frame 14, read from the 10th correspondence area 123j, but also the opening end information is stored together in the area for storing correspondence information in the history information storage area 125.

As previously explained, the main CPU 63 continuously outputs a LOW level 11th signal until the start of a game round, and then outputs a HI level 11th signal for a specific period of time once the game round has started. Therefore, the management CPU 112 identifies that a game round has started when the 11th signal changes from a LOW level to a HI level. In other words, when the 11th signal changes from a LOW level to a HI level, the information indicating that it is a game round, read from the 11th correspondence area 123k, is stored in the area of the history information storage area 125 used to store correspondence information.

The history information storage area 125 is designed to store all history information generated during a 10-day continuous business day, even if the pachinko machine 10 were to continuously fire game balls from opening to closing. For example, if 60,000 history entries are generated per day, then more than 600,000 history information storage areas 125 are provided. This ensures that all history information can be stored in the history memory 117 for at least 10 days.

The history memory 117 has a pointer area 126 separate from the history area 124. The pointer area 126 stores information for the management CPU 112 to identify the pointer information currently being written to in the history memory 117. Specifically, at the time of shipment of the pachinko machine 10, the pointer area 126 is set to specify "0" as the pointer information to be written to. Each time a new piece of history information is stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information to be written is incremented by 1. When the last pointer information in the sequence becomes the target of writing and history information is stored in the history information storage area 125 corresponding to that last pointer information, the information in the pointer area 126 is updated so that "0" is the pointer information to be written to. Therefore, if the number of history information items that can be stored exceeds the number of history information items that need to be stored, the new history information will overwrite the oldest history information in the history information storage area 125 first.

Furthermore, if an external device reads history information from the history memory 117, the history information storage area 125 is completely cleared to "0," and the information in the pointer area 126 is updated so that the "0" pointer information becomes the target for writing. This prevents history information that has already been read from becoming the target for reading again.

Next, we will explain the specific processing configuration for managing game history using the management IC 66. First, we will describe the processing configuration for storing information regarding the correspondence between the first to 14th buffers 122a to 122n, provided at the input port 121 of the management interface 111, and the signal types in the correspondence memory 116. Figure 22 is a flowchart showing the recognition process executed by the main CPU 63. The recognition process is executed in step S111 of the main process (Figure 9).

First, the recognition output counter in the main RAM 65 is set to "14" (step S801). The recognition output counter is used by the main CPU 63 to determine the remaining number of information outputs required to allow the management CPU 112 to recognize which type of signal each of the first to 14 buffers 122a to 122n of the input port 121 in the management I/F 111 corresponds to. As already explained, the 14 buffers 122a to 122n are the targets for signal type recognition, so the recognition output counter is set to "14".

Subsequently, the output processing of the identification start command is executed (step S802). The main CPU 63 outputs various commands to the management CPU 112 in order to make the management CPU 112 recognize which type of signal corresponds to the first to 14th buffers 122a to 122n. The first to 8th signals input to the first to 8th buffers 122a to 122h are used in outputting these commands. In other words, the first to 8th signals (i.e., the first to 8th signal paths 118a to 118h) used to instruct the management CPU 112 on the trigger for storing history information are used to output commands in order to make the management CPU 112 recognize which type of signal corresponds to the first to 14th buffers 122a to 122n. This makes it possible to reduce the number of signal paths and simplify the configuration compared to a configuration in which a separate signal path for outputting these commands is provided in addition to the signal paths 118a to 118p for outputting signals to the first to 16th buffers 122a to 122p. The identification start command has an 8-bit data capacity, and the data of each bit is input as the first to eighth signals to the first to eighth buffers 122a to 122h. Furthermore, in the output processing of the identification start command, the output state of the ninth signal is switched to a HI level at the timing of the start of the identification start command output, so that the management CPU 112 recognizes that a new command has been sent. The output period of the identification start command and the period during which the output state of the ninth signal is maintained at a HI level are set to be sufficient for the management CPU 112 to recognize these identification start commands and the output state of the ninth signal. Upon receiving the identification start command, the management CPU 112 determines that it should start processing to store information on the correspondence between the first to fourteenth buffers 122a to 122n and the signal types in the correspondence memory 116.

Subsequently, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S803). In this case, the first buffer 122a is the first to be set as the signal type, and then the n+1 buffer is set as the signal type after the nth buffer, so that the recognition setting of the signal types corresponding to the first to 14th buffers 122a to 122n is performed. Therefore, if the recognition output counter is "14" to "12", a type identification command indicating that it is a general prize entry port 31 and the number of prize balls is read; if the recognition output counter is "11", a type identification command indicating that it is a special electric prize entry device 32 and the number of prize balls is read; if the recognition output counter is "10", a type identification command indicating that it is a first operation port 33 and the number of prize balls is read; if the recognition output counter is "9", a type identification command indicating that it is a second operation port 34 and the number of prize balls is read; and if the recognition output counter is "8", an out port is read. The system reads a type identification command indicating that it is 24a. If the recognition output counter is "7", it reads a type identification command indicating that it is in opening/closing execution mode. If the recognition output counter is "6", it reads a type identification command indicating that it is in high-frequency support mode. If the recognition output counter is "5", it reads a type identification command indicating that it is the front door frame 14. If the recognition output counter is "4", it reads a type identification command indicating that it is a game round. If the recognition output counter is "3" to "1", it reads a type identification command indicating that it is blank.

Subsequently, the output processing of the read type identification command is executed (step S804). The type identification command, like the identification start command, has an 8-bit data capacity, and the data of each bit is input as the first to eighth signals to the first to eighth buffers 122a to 122h. Furthermore, in the output processing of the identification type command, the output state of the ninth signal is switched to a HI level at the timing of the start of outputting the identification type command, so that the management CPU 112 recognizes that a new command has been sent. The output period of the identification type command and the period during which the output state of the ninth signal is maintained at a HI level are set to be sufficient for the management CPU 112 to recognize these identification type commands and the output state of the ninth signal. Upon receiving the identification type command, the management CPU 112 stores the information corresponding to that identification type command in the corresponding relationship areas 123a to 123n of the first to fourteenth buffers 122a to 122n that are the target of this configuration.

Subsequently, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S805), and it is determined whether the value of the recognition output counter after the 1-decrement is "0" or not (step S806). If the value of the recognition output counter is 1 or greater (step S806: NO), processing is performed to output a type identification command corresponding to the value of the recognition output counter after the 1-decrement (steps S803 and S804).

On the other hand, if the value of the recognition output counter is "0" (step S806: YES), the output processing of the identification completion command is executed (step S807). The identification completion command has an 8-bit data capacity, and the data of each bit is input as the 1st to 8th signals to the 1st to 8th buffers 122a to 122h. Furthermore, in the output processing of the identification completion command, the output state of the 9th signal is switched to a HI level at the timing of the start of the identification completion command output, in order to allow the management CPU 112 to recognize that a new command has been sent. The output period of the identification completion command and the period during which the output state of the 9th signal is maintained at a HI level are set to be sufficient for the management CPU 112 to recognize these identification completion commands and the output state of the 9th signal. Upon receiving the identification completion command, the management CPU 112 determines that the processing for storing information on the correspondence between the 1st to 14th buffers 122a to 122n and the signal types in the correspondence memory 116 has been completed.

Next, the management process executed by the management CPU 112 will be explained with reference to the flowchart in Figure 23. The management process begins when power is supplied to the management CPU 112. The management CPU 112 is configured to have a faster processing speed than the main CPU 63. Therefore, between the start of one timer interrupt process (Figure 11) on the main CPU 63 and the start of the next timer interrupt process (Figure 11), the combination of processes from step S908 onwards in the management process is executed 16 or more times.

First, it is determined whether or not an identification start command has been received from the main CPU 63 (step S901). If the identification start command has not been received (step S901: NO), the setting update recognition process is executed (step S902), and then the process returns to step S901. In the setting update recognition process, as will be described in detail later, if a new setting has been made in the setting state of the pachinko machine 10 by the main CPU 63, the corresponding process is executed.

When the system receives an identification start command from the main CPU 63 (step S901: YES), the value of the setting target counter in the management RAM 114 is cleared to "0" (step S903). The setting target counter is used by the management CPU 112 to identify the types of buffers 122a to 122n that are subject to signal type setting. The first buffer 122a is the first to be subject to signal type setting, followed by the nth buffer, and then the (n+1)th buffer.

Subsequently, conditional on receiving a type identification command from the main CPU 63 (step S904: YES), the correspondence relationship setting process is executed (step S905). In the correspondence relationship setting process, the signal type information set in the received type identification command is stored in the correspondence relationship area corresponding to the current value of the setting target counter in the management RAM 114, among the first to fourteenth correspondence relationship areas 123a to 123n of the correspondence relationship memory 116. Then, the value of the setting target counter in the management RAM 114 is incremented by 1 (step S906).

If a negative determination is made in step S904, or if the process in step S906 is executed, it is determined whether or not an identification completion command has been received from the main CPU 63 (step S907). If an identification completion command has not been received (step S907: NO), the process returns to step S904, and, conditional on receiving a new type identification command from the main CPU 63 (step S904: YES), the processes in steps S905 and S906 are executed again.

If the identification completion command is received from the main CPU 63 (step S907: YES), the processes in steps S908 to S910 are repeatedly executed. Step S908, as will be described in detail later, executes a history setting process to store history information corresponding to the type of signal received from the main CPU 63 in the history memory 117. Step S909, as will be described in detail later, calculates various parameters using the history information stored in the history memory 117 and executes a display output process to announce the calculation results on the first to third notification display devices 69a to 69c. Step S910, as will be described in detail later, executes an external output process to output the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d.

Figure 24 is a time chart showing how information regarding the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n is stored in the correspondence memory 116. Figure 24(a) shows the period during which commands are output from the main CPU 63 to the management CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h). Figure 24(b) shows the period during which the output state of the ninth signal is at a HI level. Figure 24(c) shows the execution period of the identification state during which processing is performed to identify the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n. Figure 24(d) shows the timing when the correspondence setting process (step S905) is executed in the management CPU 112.

When power is supplied to the main CPU 63 and the management CPU 112, at timing t1, the output of an identification start command using the first to eighth signals begins, as shown in Figure 24(a). Also at timing t1, the output state of the ninth signal is changed from LOW to HI, as shown in Figure 24(b). Subsequently, at timing t2, while the output of the identification start command is continuing, the output state of the ninth signal is changed again from HI to LOW, as shown in Figure 24(b). The management CPU 112 confirms that a command has been sent from the main CPU 63 by checking that the output state of the ninth signal has changed from HI to LOW, and understands the content of the command received from the main CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since an identification start command has been received, the management CPU 112 enters the identified state by making an affirmative judgment in step S901 of the management process (Figure 23). Subsequently, at timing t3, the output of the identification start command is stopped, as shown in Figure 24(a).

Subsequently, at time t4, the output of the first type identification command using the first to eighth signals begins, as shown in Figure 24(a). Also at time t4, the output state of the ninth signal is changed from LOW to HI, as shown in Figure 24(b). Then, at time t5, while the output of the type identification command is still continuing, the output state of the ninth signal is changed again from HI to LOW, as shown in Figure 24(b). The management CPU 112 confirms that a command has been sent from the main CPU 63 by checking that the output state of the ninth signal has changed from HI to LOW, and understands the content of the command received from the main CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the first type identification command has been received, the management CPU 112 executes the correspondence setting process at time t5, as shown in Figure 24(d). In this correspondence setting process, information indicating that it is a general prize slot 31 and information on the number of prize balls awarded are stored in the first correspondence area 123a of the correspondence memory 116. Then, at timing t6, the output of the type identification command is stopped as shown in Figure 24(a).

Subsequently, at timings t7-t9, t10-t12, t13-t15, and t16-t18, the management CPU 112 executes the correspondence relationship setting process corresponding to the type identification command output from the main CPU 63, similar to the timings t4-t6. In this case, the correspondence relationship setting process corresponding to the 14th type identification command is completed at timings t16-t18.

Subsequently, at timing t19, the output of an identification completion command using the first to eighth signals begins, as shown in Figure 24(a). Also at timing t19, the output state of the ninth signal changes from LOW to HI, as shown in Figure 24(b). Then, at timing t20, while the output of the identification completion command is still continuing, the output state of the ninth signal changes again from HI to LOW, as shown in Figure 24(b). The management CPU 112 confirms that a command has been sent from the main CPU 63 by checking the information in the first to eighth buffers 122a to 122h, and understands the content of the command received from the main CPU 63. In this case, since an identification completion command has been received, the identification state of the management CPU 112 ends at timing t20, as shown in Figure 24(c). Then, at timing t21, the output of the identification completion command stops, as shown in Figure 24(a).

As described above, by using the ninth signal to allow the management CPU 112 to recognize whether or not a command is being output, it becomes possible to clearly recognize that a command is being output, even in a configuration where command output is performed using the first to eighth signals (i.e., the first to eighth signal paths) used to instruct the management CPU 112 on the trigger for storing history information.

Next, we will describe the processing configuration for storing history information in the history memory 117. Figure 25 is a flowchart showing the management output processing executed by the main CPU 63. The management output processing is executed in step S319 of the timer interrupt processing (Figure 11).

First, the managed object counter in the main RAM 65 is set to "11" (step S1001). The managed object counter is used by the main CPU 63 to determine whether there are any managed objects that are not currently being identified as requiring a change in the signal output state to the management CPU 112 during this management output processing. It also allows the main CPU 63 to determine whether the signal output state to the management CPU 112 should be changed for each managed object. In a single management output processing cycle, the main CPU 63 identifies 11 managed objects for which it is necessary to determine whether the signal output state to the management CPU 112 should be changed: the seven ball entry detection sensors 42a to 48a, the execution status of the opening/closing mode, the execution status of the high-frequency support mode, the opening/closing status of the front door frame 14, and the start status of the game round. Therefore, the managed object counter is initially set to "11".

Subsequently, it is determined whether the signal output status to the management CPU 112 for the managed object corresponding to the current managed object's counter value is at a HI level (step S1002). If it is not at a HI level (step S1002: NO), it is determined whether the managed object corresponding to the counter value is 5 or greater, thereby identifying whether it is one of the seven ball entry detection sensors 42a to 48a (step S1003).

If a positive determination is made in step S1003, it is determined whether or not "1" is set in the output flag of the main RAM 65 corresponding to the value of the managed counter (step S1004). Specifically, if the value of the managed counter is "11" and corresponds to the first prize-winning slot detection sensor 42a, it is determined whether or not "1" is set in the first output flag; if the value of the managed counter is "10" and corresponds to the second prize-winning slot detection sensor 43a, it is determined whether or not "1" is set in the second output flag; if the value of the managed counter is "9" and corresponds to the third prize-winning slot detection sensor 44a, it is determined whether or not "1" is set in the third output flag; and if the value of the managed counter is "8" and corresponds to the special electric detection sensor 45 If it corresponds to 'a', it is determined whether the fourth output flag is set to "1". If the value of the managed counter is "7" and it corresponds to the first operation port detection sensor 46a, it is determined whether the fifth output flag is set to "1". If the value of the managed counter is "6" and it corresponds to the second operation port detection sensor 47a, it is determined whether the sixth output flag is set to "1". If the value of the managed counter is "5" and it corresponds to the out port 24a, it is determined whether the seventh output flag is set to "1". As previously explained, these first to seventh output flags are set to "1" during the ball entry detection process (Figure 15).

If the output flag corresponding to the value of the managed counter is set to "1" (step S1004: YES), the output state of the signal corresponding to the value of the managed counter among the first to seventh signals is set to HI level (step S1005). Then, the output flag corresponding to the value of the managed counter is cleared to "0" (step S1006).

If a negative result is obtained in step S1003, it is determined whether an event has occurred that triggers switching the output state of the signal corresponding to the value of the managed counter to the HI level (step S1007). Specifically, if the value of the managed counter is "4", it is determined whether a transition to the opening/closing execution mode has occurred; if the value of the managed counter is "3", it is determined whether a transition to the high-frequency support mode has occurred; if the value of the managed counter is "2", it is determined whether the front door frame 14 is in the open state; and if the value of the managed counter is "1", it is determined whether the 11th output flag is set to "1" to determine whether a game round has started. If a positive result is obtained in step S1007, the output state of the signal corresponding to the value of the managed counter is set to the HI level (step S1008). Note that if the value of the managed counter is "1" and the process in step S1008 is executed, the 11th output flag is cleared to "0".

If a positive determination is made in step S1002, it is determined whether an event has occurred that triggers a switch to a LOW level for the output state of the signal corresponding to the value of the managed counter (step S1009). Specifically, if the value of the managed counter is 5 or greater or "1" and the current managed object is one of the ball entry detection sensors 42a to 48a or the start of a game round, it is determined whether a HI output duration period (specifically 10 milliseconds) has elapsed since the output state of the signal corresponding to the value of the managed counter among the 1st to 7th signals and the 11th signal was switched from a LOW level to a HI level. This HI output duration period is set in the management CPU 112 to be longer than the longest processing interval of the history setting process (step S908) of the management process (Figure 23), and is a period during which the management CPU 112 can reliably identify the output state of the signal that has switched from a LOW level to a HI level. Furthermore, if the value of the managed counter is "4" and the current managed object is in the opening/closing execution mode, it is determined whether the opening/closing execution mode has ended. If the value of the managed counter is "3" and the current managed object is in the high-frequency support mode, it is determined whether the high-frequency support mode has ended. If the value of the managed counter is "2" and the current managed object is the front door frame 14, it is determined whether the front door frame 14 is in the closed state. If an event occurs that triggers switching the output state of the signal corresponding to the value of the managed counter to the LOW level (step S1009: YES), the output state of the signal corresponding to the value of the managed counter is set to the LOW level (step S1010).

If a negative result is obtained in step S1004, if the process in step S1006 is executed, if a negative result is obtained in step S1007, if the process in step S1008 is executed, if a negative result is obtained in step S1009, or if the process in step S1010 is executed, the value of the managed counter in the main RAM 65 is decremented by 1 (step S1011). Then, it is determined whether the value of the managed counter after the decrement is "0" (step S1012). If the value of the managed counter is 1 or greater (step S1012: NO), the process from step S1002 onwards is executed for the managed object corresponding to the new managed counter value.

Next, the history setting process executed by the management CPU 112 will be explained with reference to the flowchart in Figure 26. The history setting process is executed in step S908 of the management process (Figure 23).

First, the number of buffers to be checked by the management CPU 112 from among the first to 14th buffers 122a to 122n is set in the verification target counter provided in the management RAM 114 (step S1101). Specifically, the number of correspondence relationship areas 123a to 123n in the correspondence relationship memory 116 that store information other than information indicating that they are blank is identified, and this identified number of items is set in the verification target counter. In this pachinko machine 10, as already explained, information other than information indicating that they are blank is stored in the first to 11th correspondence relationship areas 123a to 123k, so in step S1101, "11" is set in the verification target counter.

Subsequently, by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fourteenth buffers 122a to 122n has changed from "0" to "1", it is determined whether the output state of the input signal from the main CPU 63 to that buffer has switched from a LOW level to a HI level (step S1102). Note that if the value of the counter to be checked is "n", then the nth buffer 122a to 122n becomes the target of numerical information check. For example, if the value of the counter to be checked is "11", then the eleventh buffer 122k becomes the target of numerical information check, and if the value of the counter to be checked is "5", then the fifth buffer 122e becomes the target of numerical information check.

If a positive determination is made in step S1102, the RTC information, which consists of date and time information, is read from the RTC 115 (step S1103). Then, the write process to the history memory 117 is executed (step S1104). In this write process, the pointer information of the history area 124 currently being written to is identified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S1103 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. In addition, correspondence information is read from the correspondence areas 123a to 123n corresponding to the current value of the counter to be checked, and this correspondence information is written to the history information storage area 125 corresponding to the pointer information being written to. Furthermore, if the correspondence information is any of the following: information indicating the opening/closing execution mode, information indicating the high-frequency support mode, or information indicating the front door frame 14, then not only the correspondence information but also the start information is written to the history information storage area 125 corresponding to the pointer information being written. Note that if the value of the counter to be checked is "n", then the nth correspondence area 123a to 123n become the target for reading the correspondence information. For example, if the value of the counter to be checked is "11", then the 11th correspondence area 123k becomes the target for reading the correspondence information, and if the value of the counter to be checked is "5", then the 5th correspondence area 123e becomes the target for reading the correspondence information.

As described above, when the write process is executed, if the value of the counter to be checked is one of the following: the out-port 24a, the general prize-winning port 31, the special electric prize-winning device 32, the first operation port 33, the second operation port 34, or the number of game rounds, then the history information storage area 125 corresponding to the pointer information being written will store a combination of RTC information and correspondence information indicating that it is one of the following: the out-port 24a, the general prize-winning port 31, the special electric prize-winning device 32, the first operation port 33, the second operation port 34, or the number of game rounds, as history information. Furthermore, if the value of the counter to be checked is one of the following: the open/close execution mode, the high-frequency support mode, or the front door frame 14, then the history information storage area 125 corresponding to the pointer information being written will store a combination of RTC information, correspondence information indicating that it is one of the open/close execution mode, the high-frequency support mode, or the front door frame 14, and start information as history information.

Subsequently, the update process for the target pointer is executed (step S1105). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. It is then determined whether the pointer information after the increment exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

If a negative determination is made in step S1102, or if the process in step S1105 is executed, it is determined whether the corresponding relationship information for checking whether the signal output has been switched to the LOW level is stored in the corresponding relationship areas 123a to 123n that correspond to the current value of the target counter (step S1106). Specifically, if the current value of the target counter is "8" to "10", then one of the following information is stored in the corresponding relationship areas 123h to 123j: information indicating that it is in opening/closing execution mode, information indicating that it is in high-frequency support mode, or information indicating that it is the front door frame 14. Therefore, a positive determination is made in step S1106.

If a positive determination is made in step S1106, it is determined whether the output state of the input signal from the main CPU 63 to the buffer has been switched from a HI level to a LOW level by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fourteenth buffers 122a to 122n has been changed from "1" to "0" (step S1107). If a positive determination is made in step S1107, the RTC information is read in the same way as in step S1103 (step S1108), and then the write process to the history memory 117 is executed (step S1109). In this write process, the RTC information read in step S1108 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. In addition, the correspondence information is read from the correspondence area 123a to 123n corresponding to the current value of the counter to be checked, and this correspondence information is written to the history information storage area 125 corresponding to the pointer information to be written. Furthermore, in addition to the correspondence information, termination information is also written to the history information storage area 125 corresponding to the pointer information being written. When this writing process is executed, if the value of the counter being checked is either the opening/closing execution mode, the high-frequency support mode, or the front door frame 14, then the history information storage area 125 corresponding to the pointer information being written will store a combination of RTC information, correspondence information indicating that it is one of the opening/closing execution mode, the high-frequency support mode, or the front door frame 14, and termination information as history information. Afterward, the target pointer update process is executed in the same manner as in step S1105 (step S1110).

If a negative result is obtained in step S1106, step S1107, or step S1110, the value of the verification target counter in the management RAM 114 is decremented by 1 (step S1111). Then, it is determined whether the value of the verification target counter after the decrement is "0" (step S1112). If the value of the verification target counter is 1 or greater (step S1112: NO), the processing from step S1102 onwards is executed for the verification target corresponding to the new verification target counter value.

Next, the process by which history information is stored in the history memory 117 will be explained with reference to the time chart in Figure 27. Figure 27(a) shows the period during which a HI level signal is input to any of the first to seventh or eleventh buffers 122a to 122g or 122k; Figure 27(b) shows the period during which a HI level signal is input to the eighth buffer 122h; Figure 27(c) shows the period during which a HI level signal is input to the ninth buffer 122i; Figure 27(d) shows the period during which a HI level signal is input to the tenth buffer 122j; and Figure 27(e) shows the timing of writing history information to the history memory 117.

At timing t1, as shown in Figure 27(a), the output state of the signal input to one of the first to seventh or eleventh buffers 122a to 122g or 122k is switched from a LOW level to a HI level. Therefore, at timing t1, history information is written to the history memory 117 as shown in Figure 27(e). Subsequently, at timing t2, as shown in Figure 27(a), the signal that was switched to a HI level at timing t1 is switched back to a LOW level. However, since this signal is input to one of the first to seventh or eleventh buffers 122a to 122g or 122k, and the LOW level switch is not subject to history information storage, the writing of history information is not performed at timing t2 as shown in Figure 27(e).

Subsequently, at timings t3, t5, t6, t9, t10, t13, and t14, the output state of the signal input to one of the first to seventh and eleventh buffers 122a to 122g and 122k is switched from a LOW level to a HI level, as shown in Figure 27(a). Therefore, at each of these timings, history information is written, as shown in Figure 27(e).

As shown in Figure 27(b), the output state of the signal input to the eighth buffer 122h is at a HI level from timing t4 to timing t7. This eighth buffer 122h corresponds to the presence or absence of the opening/closing execution mode. Therefore, as shown in Figure 27(e), history information is written at timing t4, when the output state of the signal input to the eighth buffer 122h switches to a HI level, and at timing t7, when the output state of the signal switches to a LOW level. In this case, the history information written at timing t4 includes start information, and the history information written at timing t7 includes end information. This makes it possible to understand the execution period of the opening/closing execution mode by checking the history information in the history memory 117.

Furthermore, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether the history information indicating a ball entry into any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred during the opening/closing execution mode. Additionally, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating a ball entry into any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred during the opening/closing execution mode by comparing it with the RTC information.

As shown in Figure 27(c), the output state of the signal input to the ninth buffer 122i is at a HI level from timing t8 to timing t11. This ninth buffer 122i corresponds to the presence or absence of the high-frequency support mode. Therefore, as shown in Figure 27(e), history information is written at timing t8, when the output state of the signal input to the ninth buffer 122i switches to a HI level, and at timing t11, when the output state of the signal switches to a LOW level. In this case, the history information written at timing t8 includes start information, and the history information written at timing t11 includes end information. This makes it possible to understand the execution period of the high-frequency support mode by checking the history information in the history memory 117.

Furthermore, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether the history information indicating a ball entry into any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred during high-frequency support mode. Additionally, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating a ball entry into any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred during high-frequency support mode by comparing it with the RTC information.

As shown in Figure 27(d), the output state of the signal input to the 10th buffer 122j is at a HI level from timing t12 to timing t15. This 10th buffer 122j corresponds to whether the front door frame 14 is open or closed. Therefore, as shown in Figure 27(e), history information is written at timing t12, when the output state of the signal input to the 10th buffer 122j switches to a HI level, and at timing t15, when the output state of the signal switches to a LOW level. In this case, the history information written at timing t12 includes start information, and the history information written at timing t15 includes end information. This makes it possible to determine the period during which the front door frame 14 is in an open state by checking the history information in the history memory 117.

Furthermore, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether the history information indicating a ball entry into any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred while the front door frame 14 was open. Additionally, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating a ball entry into any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred while the front door frame 14 was open by comparing it with this RTC information.

Next, we will explain the output process for the setting value update signal, which is executed when the setting state of the pachinko machine 10 is set by the main CPU 63. Figure 28 is a flowchart showing the output process for the setting value update signal executed by the main CPU 63. Note that the output process for the setting value update signal is executed in step S119 of the main process (Figure 9).

The pulse counter in the main RAM 65 is set to a value corresponding to the setting value of the pachinko machine 10 that has been set (step S1201). Specifically, the value of the setting value counter in the main RAM 65 is set to the pulse counter. Then, it is determined whether or not the setting value update signal directed to the management CPU 112 is at a HI level (step S1202). As already explained, the setting value update signal is input to the 15th buffer 122o of the input port 121 of the management IC 66. Here, the output processing of the setting value update signal is performed at a timing before the recognition processing, which is the processing to cause the management CPU 112 to identify the type of signal input to the 1st to 14th buffers 122a to 122n of the input port 121 in the main processing (Figure 9). In contrast, since the setting value update signal is input to the 15th buffer 122o, as configured in the management IC 66 during the design phase of the pachinko machine 10, even if the output processing of the setting value update signal is executed before the recognition processing, the management CPU 112 can identify the signal input to the 15th buffer 122o as a setting value update signal.

If a negative result is obtained in step S1202, the value of the LOW level counter in the main RAM 65 is decremented by 1 (step S1203), and it is determined whether the value of the LOW level counter after the decrement is "0" (step S1204). The LOW level counter is a counter used by the main CPU 63 to determine whether the setting value update signal has been maintained at a LOW level for a predetermined period while the setting value update signal outputs multiple pulses that make the setting value update signal HI. If the value of the LOW level counter is "0" (step S1204: YES), it means that it is time to set the setting value update signal to a HI level, so the setting value update signal is set to a HI level (step S1205).

Subsequently, the HI-level counter in the main RAM 65 is set to "20" (step S1206). The HI-level counter is used by the main CPU 63 to determine the period during which the setting value update signal is maintained at a HI level. Since the value set in the HI-level counter is decremented by 1 approximately every 10 microseconds, the setting value update signal is maintained at a HI level for 200 microseconds with each pulse output. This period of maintaining the HI level is sufficient for the management CPU 112 to determine that the setting value update signal has changed from a LOW level to a HI level.

If the setting value update signal is at the HI level (step S1202: YES), the value of the HI level counter in the main RAM 65 is decremented by 1 (step S1207), and it is determined whether the value of the HI level counter after the decrement is "0" (step S1208). If the value of the HI level counter is "0" (step S1208: YES), it means that it is time to set the setting value update signal to the LOW level, so the setting value update signal is set to the LOW level (step S1209).

Subsequently, the pulse counter value in the main RAM 65 is decremented by 1 (step S1210), and it is determined whether the pulse counter value after the decrement is "0" (step S1211). If the pulse counter value is not "0" (step S1211: NO), it means that the output of pulse signals due to the setting value update signal corresponding to the setting value of the pachinko machine 10 has not been completed. Therefore, the LOW level counter in the main RAM 65 is set to "20" (step S1212). Since the value set in the LOW level counter is decremented by 1 approximately every 10 microseconds, it is maintained at the LOW level for 200 microseconds between multiple pulse outputs due to the setting value update signal. This period of maintaining the LOW level is sufficient for the management CPU 112 to determine that the setting value update signal has changed from the HI level to the LOW level.

If the pulse count counter value is "0" (step S1211: YES), it means that the output of pulse signals corresponding to the setting value of the currently set pachinko machine 10 has been completed, and the output process of the setting value identification completion command is executed (step S1213). The setting value identification completion command is a command to inform the management CPU 112 that the output of setting value update signals for recognizing the currently set setting value of the pachinko machine 10 has been completed. When outputting the setting value identification completion command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used, similar to the identification start command, type identification command, and identification completion command. However, the signal pattern of the setting value identification completion command is different from that of the identification start command, type identification command, and identification completion command.

As described above, in the output processing of the setting value update signal, the management IC 66 outputs pulse signals corresponding to the setting value of the pachinko machine 10 set at the start of the current power supply, for a number of minutes. The management CPU 112 executes a setting update recognition process to determine the number of pulse signals from the setting value update signal and, based on that, determines the setting value of the pachinko machine 10 that was set this time.

Figure 29 is a flowchart showing the configuration update recognition process executed by the management CPU 112. Note that the configuration update recognition process is executed in step S902 of the management process (Figure 23).

The system determines whether the setting value update signal input to the 15th buffer 122o of input port 121 has switched from a LOW level to a HI level (step S1301). If the determination in step S1301 is positive, the value of the setting value recognition counter in the management-side RAM 114 is set to "1" (step S1302). The setting value recognition counter is a counter used by the management-side CPU 112 to identify the setting value of the pachinko machine 10. For example, a value of "1" in the setting value recognition counter means "setting 1," and a value of "6" means "setting 6."

Subsequently, it is determined whether the setting value update signal input to the 15th buffer 122o of input port 121 has switched back from the LOW level to the HI level (step S1303). If the determination in step S1303 is positive, the value of the setting value recognition counter in the management-side RAM 114 is incremented by 1 (step S1304). As a result, the setting value of the pachinko machine 10 identified by the management-side CPU 112 increases by one level.

If a negative result is obtained in step S1303, or if the process in step S1304 is executed, it is determined whether or not a setting value identification completion command has been received from the main CPU 63, based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1305). If a negative result is obtained in step S1305, the process returns to step S1303.

If a positive result is obtained in step S1305, the RTC information, which includes the date and time, is read from the RTC 115 (step S1306). Then, the write process to the history memory 117 is executed (step S1307). In this write process, the pointer information of the history area 124 currently being written to is identified by referring to the pointer area 126 of the history memory 117. The RTC information read in step S1306 is then written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. Furthermore, both information to identify that it is a set value and information about the value of the set value recognition counter are written to the history information storage area 125 corresponding to the pointer information being written to. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time the setting was made, and information about the setting value when the setting was made is stored as history information.

Subsequently, the update process for the target pointer is executed (step S1308). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. It is then determined whether the pointer information after the increment exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

As described above, when the setting update recognition process is executed and the setting state of the pachinko machine 10 is newly set, the fact that the setting was made, the date and time the setting was made, and the combination of the setting value at the time the setting was made are stored as history information in the history area 124. This makes it possible to read and analyze the information stored in the history memory 117 using an external device connected to the reading terminal 68d, thereby determining the date and time the setting state of the pachinko machine 10 was newly set and the content of the setting value at the time the setting was made.

Here, even if the settings of the pachinko machine 10 are newly set, the information stored in the history memory 117 remains unchanged. This prevents the history information in the history memory 117 from being erased even when the settings of the pachinko machine 10 are newly set, and the various parameters described later are calculated using the history information that exists before and after the timing of the change in the settings of the pachinko machine 10. In this case, as described above, the date and time when the settings of the pachinko machine 10 were newly set are stored in the history memory 117. Therefore, by connecting an external device to the reading terminal 68d and reading the information stored in the history memory 117, it becomes possible to calculate various parameters for the period after the timing of the new setting of the pachinko machine 10 and while that setting is maintained.

Next, the display output processing performed by the management CPU 112 will be explained with reference to the flowchart in Figure 30. Note that the display output processing is performed in step S909 of the management processing (Figure 23).

First, it is determined whether or not it is the timing for calculation (step S1401). If 51 seconds have elapsed since the supply of operating power to the management CPU 112 began, or if 51 seconds have elapsed since the previous affirmative determination in step S1401, an affirmative determination is made in step S1401. If an affirmative determination is made in step S1401, the number of balls that enter each category under normal circumstances is calculated (step S1402). Specifically, first, the number of balls that enter the exit port 24a is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that it is the exit port 24a is stored. Also, the number of balls that enter the general prize port 31 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that it is the general prize port 31 is stored. Furthermore, the number of balls entering the special electric prize winning device 32 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store corresponding relationship information indicating that it is the special electric prize winning device 32. Similarly, the number of balls entering the first operating port 33 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store corresponding relationship information indicating that it is the first operating port 33. Finally, the number of balls entering the second operating port 34 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store corresponding relationship information indicating that it is the second operating port 34.

Subsequently, by referring to the history information storage area 125 that exists during the period between the history information storage area 125 in the history area 124 of the history memory 117, where correspondence relationship information and start information indicating that it is the front door frame 14 are stored, and the history information storage area 125 in which correspondence relationship information and end information indicating that it is the front door frame 14 are stored, the number of balls that entered each of the out opening 24a, general prize opening 31, special electric prize device 32, first operation opening 33, and second operation opening 34 when the front door frame 14 was in the open state is calculated (step S1403). The period between the history information storage area 125 in the history area 124 of the history memory 117, where correspondence relationship information and start information indicating that it is the front door frame 14 are stored, and the history information storage area 125 in which correspondence relationship information and end information indicating that it is the front door frame 14 are stored, is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if, within the entire sequence of pointer information, there are multiple intervals between the history information storage area 125 containing correspondence information and start information indicating that it is the front door frame 14, and the history information storage area 125 containing correspondence information and end information indicating that it is the front door frame 14, the total number of balls entered for each interval is calculated. Also, if a history information storage area 125 containing correspondence information and start information indicating that it is the front door frame 14 exists, but the history information storage area 125 containing RTC information corresponding to a later time than that history information storage area 125 does not contain correspondence information and end information indicating that it is the front door frame 14, then the history information in the history information storage area 125 containing RTC information corresponding to a later time than that history information storage area 125 containing correspondence information and start information indicating that it is the front door frame 14 is treated as if it were in an open state.

Subsequently, various parameters are calculated using the calculation results from steps S1402 and S1403 (step S1404). Specifically, first, the number of balls that entered while the front door frame 14 was open, calculated in step S1403, is subtracted from the number of balls that entered each way, calculated in step S1402. Then, the following 1st to 8th parameters are calculated using the number of balls that entered each way after this subtraction. Note that the difference between the number of balls that entered the out-out opening 24a calculated in step S1402 and the number of balls that entered the out-out opening 24a calculated in step S1403 is defined as the number of balls that entered, and the difference between the number of balls that entered the general prize-winning opening 31 calculated in step S1402 and the number of balls that entered the general prize-winning opening 31 calculated in step S1403 is defined as the number of balls that entered, and the difference between the number of balls that entered the special electric prize-winning device 32 calculated in step S1402 is defined as the number of balls that entered, calculated in step S1402. The difference in the number of balls that enter the special electric prize device 32 calculated in step S1403 is defined as the number of balls entered K3, the difference in the number of balls that enter the first operating port 33 calculated in step S1403 compared to the number of balls that enter the first operating port 33 calculated in step S1402 is defined as the number of balls entered K4, and the difference in the number of balls that enter the second operating port 34 calculated in step S1403 compared to the number of balls that enter the second operating port 34 calculated in step S1402 is defined as the number of balls entered K5.
• Parameter 1: Total number of game balls dispensed (K2 × "number of prize balls for entry into general prize slot 31" + K3 × "number of prize balls for entry into special electric prize device 32" + K4 × "number of prize balls for entry into first operation slot 33" + K5 × "number of prize balls for entry into second operation slot 34") / ratio of the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D1")
- Second parameter: The ratio of the total number of game balls entered into the general prize slot 31 (K2) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5). - Third parameter: The ratio of the total number of game balls entered into the special electric prize slot 32 (K3) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5). - Fourth parameter: The ratio of the total number of game balls entered into the first operating slot 33 (K4) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D2").
• Fifth parameter: The ratio of the total number of game balls entered into the second operating port 34 (K5) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D3").
• Sixth parameter: D1 - (D2 × "Number of prize balls awarded for winning in the first operating opening 33" + D3 × "Number of prize balls awarded for winning in the second operating opening 34")
・Parameter 7: (K3 × "Number of prize balls for winning into the special electric prize device 32" + K5 × "Number of prize balls for winning into the second operating port 34") / Total number of game balls dispensed (K2 × "Number of prize balls for winning into the general prize port 31" + K3 × "Number of prize balls for winning into the special electric prize device 32" + K4 × "Number of prize balls for winning into the first operating port 33" + K5 × "Number of prize balls for winning into the second operating port 34") The ratio of the number of prize balls awarded for each prize awarded is the 8th parameter: K3 × "Number of prize balls awarded for winning in the special electric prize winning device 32" / the ratio of the total number of game balls dispensed (K2 × "Number of prize balls awarded for winning in the general prize winning opening 31" + K3 × "Number of prize balls awarded for winning in the special electric prize winning device 32" + K4 × "Number of prize balls awarded for winning in the first operating opening 33" + K5 × "Number of prize balls awarded for winning in the second operating opening 34"). In step S1404, the calculation results of the above 1st to 8th parameters are stored in the normal operation storage area of the calculation result memory 131. The above 1st to 8th parameters stored in the normal operation storage area are retained until the next step S1404 is executed. In other words, when the next step S1404 is executed and the first to eighth parameters are calculated, the newly calculated first to eighth parameters are stored in the normal operation storage area, overwriting the previous calculation results of the first to eighth parameters that were stored in the normal operation storage area up to that point.

Subsequently, by referring to the history information storage area 125 that exists during the period between the history information storage area 125 in the history area 124 of the history memory 117, which stores correspondence relationship information and start information indicating that it is in the open/close execution mode, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in the open/close execution mode, the number of balls that entered each of the out gate 24a, general prize gate 31, special electric prize device 32, first operation gate 33, and second operation gate 34 when it was in the open/close execution mode is calculated (step S1405). The period between the history information storage area 125 in the history area 124 of the history memory 117, which stores correspondence relationship information and start information indicating that it is in the open/close execution mode, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in the open/close execution mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple intervals within the entire sequence of pointer information between the history information storage area 125 containing correspondence relationship information and start information indicating the open/close execution mode, and the history information storage area 125 containing correspondence relationship information and end information indicating the open/close execution mode, the total number of balls entered for each interval is calculated. Also, if a history information storage area 125 containing correspondence relationship information and start information indicating the open/close execution mode exists, but the history information storage area 125 containing RTC information corresponding to a later time than that history information storage area 125 does not contain correspondence relationship information and end information indicating the open/close execution mode, then the history information in the history information storage area 125 containing RTC information corresponding to a later time than that history information storage area 125 containing correspondence relationship information and start information indicating the open/close execution mode is treated as being in the open/close execution mode.

Subsequently, during the period of the opening/closing execution mode identified in step S1405, the number of balls that entered each of the out-port 24a, general prize-winning port 31, special electric prize-winning device 32, first operating port 33, and second operating port 34 while the front door frame 14 was in the open state is calculated (step S1406). The method for calculating these ball entry numbers is the same as in step S1403, except that it assumes the period of the opening/closing execution mode identified in step S1405.

Subsequently, various parameters are calculated using the calculation results from steps S1405 and S1406 (step S1407). Specifically, first, the number of balls that entered while the front door frame 14 was open, calculated in step S1406, is subtracted from the number of balls that entered each way, calculated in step S1405. Then, the following 11th to 18th parameters are calculated using the number of balls that entered each way after this subtraction. Note that the difference between the number of balls that entered the out-out opening 24a calculated in step S1405 and the number of balls that entered the out-out opening 24a calculated in step S1406 is defined as the number of balls that entered, K11, the difference between the number of balls that entered the general prize-winning opening 31 calculated in step S1405 and the number of balls that entered the general prize-winning opening 31 calculated in step S1406 is defined as the number of balls that entered, K12, and the difference between the number of balls that entered the special electric prize-winning device 32 calculated in step S1405 is defined as the number of balls that entered The difference in the number of balls that enter the special electric prize device 32 calculated in step S1406 is defined as the number of balls that enter K13, the difference in the number of balls that enter the first operating port 33 calculated in step S1406 compared to the number of balls that enter the first operating port 33 calculated in step S1405 is defined as the number of balls that enter K14, and the difference in the number of balls that enter the second operating port 34 calculated in step S1406 compared to the number of balls that enter the second operating port 34 calculated in step S1405 is defined as the number of balls that enter K15.
Parameter 11: Total number of game balls dispensed (K12 × "number of prize balls for entry into general prize slot 31" + K13 × "number of prize balls for entry into special electric prize device 32" + K14 × "number of prize balls for entry into first operation slot 33" + K15 × "number of prize balls for entry into second operation slot 34") / ratio of the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D11")
- Parameter 12: The ratio of the total number of game balls entered into the general prize slot 31 (K12) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) - Parameter 13: The ratio of the total number of game balls entered into the special electric prize slot 32 (K13) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) - Parameter 14: The ratio of the total number of game balls entered into the first operating slot 33 (K14) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (Hereafter, this ratio will be referred to as "D12")
Parameter 15: The ratio of the total number of game balls entered into the second operating port 34 (K15) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D13").
Parameter 16: D11 - (D12 × "Number of prize balls awarded for winning in the first operating port 33" + D13 × "Number of prize balls awarded for winning in the second operating port 34")
Parameter 17: (K13 × "Number of prize balls for winning into the special electric prize device 32" + K15 × "Number of prize balls for winning into the second operating port 34") / Total number of game balls dispensed (K12 × "Number of prize balls for winning into the general prize port 31" + K13 × "Number of prize balls for winning into the special electric prize device 32" + K14 × "Number of prize balls for winning into the first operating port 33" + K15 × "Number of prize balls for winning into the second operating port 34") The ratio of the number of prize balls awarded for each prize awarded is K13 × "number of prize balls awarded for each prize awarded to the special electric prize award device 32" / the ratio of the total number of game balls dispensed (K12 × "number of prize balls awarded for each prize awarded to the general prize award opening 31" + K13 × "number of prize balls awarded for each prize awarded to the special electric prize award device 32" + K14 × "number of prize balls awarded for each prize awarded to the first operating opening 33" + K15 × "number of prize balls awarded for each prize awarded to the second operating opening 34"). In step S1407, the calculation results of the above 11th to 18th parameters are stored in the storage area for the opening/closing execution mode in the calculation result memory 131. The above 11th to 18th parameters stored in the storage area for the opening/closing execution mode are retained until the next step S1407 is executed. In other words, when the next step S1407 is executed and the 11th to 18th parameters are calculated, the newly calculated 11th to 18th parameters are stored in the storage area for the opening/closing execution mode, overwriting the previous calculation results of the 11th to 18th parameters that were stored in the storage area for the opening/closing execution mode.

Subsequently, the number of balls that entered each of the out-port 24a, general-purpose-entry-port 31, special-electric-entry-device 32, first-operation-port 33, and second-operation-port 34 during the high-frequency-support mode is calculated by referring to the history information storage area 125 that exists during the period between the history information storage area 125 in the history area 124 of the history memory 117, which stores correspondence relationship information and start information indicating that it is in high-frequency-support mode, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in high-frequency-support mode (step S1408). The period between the history information storage area 125 in the history area 124 of the history memory 117, which stores correspondence relationship information and start information indicating that it is in high-frequency-support mode, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in high-frequency-support mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple intervals within the entire sequence of pointer information between the history information storage area 125 containing correspondence relationship information and start information indicating high-frequency support mode, and the history information storage area 125 containing correspondence relationship information and end information indicating high-frequency support mode, the total number of balls entered for each interval is calculated. Also, if a history information storage area 125 containing correspondence relationship information and start information indicating high-frequency support mode exists, but the history information storage area 125 containing RTC information corresponding to a later time than that history information storage area 125 does not contain correspondence relationship information and end information indicating high-frequency support mode, then all history information in the history information storage area 125 containing RTC information corresponding to a later time than that history information storage area 125 containing correspondence relationship information and start information indicating high-frequency support mode is treated as being in high-frequency support mode.

Subsequently, during the period of high-frequency support mode identified in step S1408, the number of balls entering each of the out-port 24a, general-purpose entry port 31, special-electric entry device 32, first-operation port 33, and second-operation port 34 while the front door frame 14 was open is calculated (step S1409). The method for calculating these ball entry numbers is the same as in step S1403, except that it assumes the period of high-frequency support mode identified in step S1408.

Subsequently, various parameters are calculated using the calculation results from steps S1408 and S1409 (step S1410). Specifically, first, the number of balls that entered while the front door frame 14 was open, calculated in step S1409, is subtracted from the number of balls that entered each way, calculated in step S1408. Then, the following 21st to 26th parameters are calculated using the number of balls that entered each way after this subtraction. Note that the difference between the number of balls that entered the out-out opening 24a calculated in step S1408 and the number of balls that entered the out-out opening 24a calculated in step S1409 is defined as the number of balls that entered, K21; the difference between the number of balls that entered the general prize-winning opening 31 calculated in step S1408 and the number of balls that entered the general prize-winning opening 31 calculated in step S1409 is defined as the number of balls that entered, K22; and the step of the number of balls that entered the special electric prize-winning device 32 calculated in step S1408 is defined as the number of balls that entered. The difference in the number of balls that enter the special electric prize device 32 calculated in step S1409 is defined as the number of balls that enter the first operating port 33 calculated in step S1409 compared to the number of balls that enter the first operating port 33 calculated in step S1408 is defined as the number of balls that enter the first operating port 33 is defined as the number of balls that enter the first operating port 33 is defined as the number of balls that enter the second operating port 34 calculated in step S1409 compared to the number of balls that enter the second operating port 34 calculated in step S1408 is defined as the number of balls that enter the second operating port 34 calculated in step S1409.
Parameter 21: Total number of game balls dispensed (K22 × "number of prize balls for winning into general prize slot 31" + K23 × "number of prize balls for winning into special electric prize device 32" + K24 × "number of prize balls for winning into first operation slot 33" + K25 × "number of prize balls for winning into second operation slot 34") / ratio of the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D11")
Parameter 22: The ratio of the total number of game balls entered into the general prize slot 31 (K22) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25). Parameter 23: The ratio of the total number of game balls entered into the special electric prize slot 32 (K23) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25). Parameter 24: The ratio of the total number of game balls entered into the first operating slot 33 (K24) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D22").
Parameter 25: The ratio of the total number of game balls entered into the second operating port 34 (K25) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D23").
Parameter 26: D21 - (D22 × "Number of prize balls awarded for winning in the first operating port 33" + D23 × "Number of prize balls awarded for winning in the second operating port 34")
In step S1410, the calculation results of the 21st to 26th parameters are stored in the high-frequency support mode storage area of the calculation result memory 131. The 21st to 26th parameters stored in the high-frequency support mode storage area are retained until the next step S1410 is executed. In other words, when the next step S1410 is executed and the 21st to 26th parameters are calculated, the newly calculated 21st to 26th parameters are stored in the high-frequency support mode storage area, overwriting the previous calculation results of the 21st to 26th parameters that were previously stored in the high-frequency support mode storage area.

Subsequently, the frequency of the opening/closing execution mode is calculated and stored (step S1411). Specifically, the number of times the opening/closing execution mode occurs is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that the opening/closing execution mode is in operation and start information are stored. The number of times a game round occurs is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that a game round has started is stored. Then, the number of times the opening/closing execution mode occurs per unit game round is calculated. The number of times the opening/closing execution mode occurs is denoted as the occurrence count K31, and the number of times a game round occurs is denoted as the occurrence count K32.
31st parameter: K31/K32
In step S1411, the calculation result of the 31st parameter is stored in the opening/closing execution mode frequency storage area in the calculation result memory 131. The 31st parameter stored in the opening/closing execution mode frequency storage area is retained until the next step S1411 is executed. In other words, when the next step S1411 is executed and the 31st parameter is calculated, the newly calculated 31st parameter is stored in the opening/closing execution mode frequency storage area, overwriting the previous calculation result of the 31st parameter that was stored in the opening/closing execution mode frequency storage area.

Subsequently, the frequency of occurrence of the high-frequency support mode is calculated and stored (step S1412). Specifically, the number of times the high-frequency support mode occurs is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that it is the high-frequency support mode and start information are stored. The number of times a game round occurs is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117, where correspondence information indicating that it is the start of a game round is stored. Then, the number of times the high-frequency support mode occurs per unit game round, and the ratio of the number of times the high-frequency support mode occurs to the number of times the open/close execution mode occurs are calculated. The number of times the high-frequency support mode occurs is denoted as the occurrence count K41, the number of times a game round occurs as the occurrence count K42, and the number of times the open/close execution mode occurs calculated in step S1411 as the occurrence count K43.
Parameter 41: K41/K42
Parameter 42: K41/K43
In step S1412, the calculation results of the 41st to 42nd parameters are stored in the high-frequency support mode frequency storage area of the calculation result memory 131. The 41st to 42nd parameters stored in the high-frequency support mode frequency storage area are retained until the next step S1412 is executed. In other words, when the next step S1412 is executed and the 41st to 42nd parameters are calculated, the newly calculated 41st to 42nd parameters are stored in the high-frequency support mode frequency storage area, overwriting the previous calculation results of the 41st to 42nd parameters that were previously stored in the high-frequency support mode frequency storage area.

If a negative result is obtained in step S1401, or if the process in step S1412 is executed, the display process is executed (step S1413). Figure 31 is a flowchart of the display process.

First, the value of the update timing counter provided in the management RAM 114 is decremented by 1 (step S1501). The update timing counter is a counter used by the management CPU 112 to identify that it is time to update the display content of the game history management results in the first to third notification display devices 69a to 69c. The management CPU 112 controls the display of the first to third notification display devices 69a to 69c to report the calculation results of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirtieth parameter, and the fortieth to fortieth parameters. In this case, the first notification display device 69a displays information corresponding to the type of parameter to be reported. In addition, of the value obtained by multiplying the parameter to be reported by 100, the digit corresponding to the tens place is displayed in the second notification display device 69b, and the digit corresponding to the ones place is displayed in the third notification display device 69c. In the first to third notification display devices 69a to 69c, the displays corresponding to the calculation results of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-two parameters are sequentially switched according to a predetermined order. After the calculation result of the forty-second parameter, which is the last parameter to be displayed, is shown, the calculation result of the first parameter, which is the first parameter to be displayed, is displayed. In this case, the period during which the calculation result of a single parameter is continuously displayed is two seconds.

Here, the calculation cycle for the various parameters in the management CPU 112 is 51 seconds. In contrast, there are 25 parameters, and the period during which the calculation result of a single parameter is continuously displayed is 2 seconds. Therefore, the various parameters calculated by the management CPU 112 are displayed at least once on the first to third notification display devices 69a to 69c.

If the process in step S1501 is executed, it is determined whether it is time to update the display content of the first to third notification display devices 69a to 69c by checking whether the value of the update timing counter after subtracting 1 is "0" (step S1502). If the determination in step S1502 is positive, the value of the display target counter provided in the management RAM 114 is incremented by 1 (step S1503). Then, if the value of the display target counter after incrementing by 1 exceeds the maximum value of "24" (step S1504: YES), the value of the display target counter is cleared to "0" (step S1505).

The display target counter is a counter used by the management CPU 112 to identify the type of parameter being displayed in the first to third notification display devices 69a to 69c. There is a one-to-one correspondence between the first to eighth parameters, eleventh to eighteenth parameters, twenty-two sixth parameters, thirty-oneth parameter, and forty-fourth to forty-two fourth parameters, and the possible values of the display target counter from "0" to "24". For example, if the value of the display target counter is "0", the first parameter, which is the first display target, becomes the display target of the first to third notification display devices 69a to 69c. If the value of the display target counter is "24", the forty-two parameter, which is the last display target, becomes the display target of the first to third notification display devices 69a to 69c.

If a negative determination is made in step S1504, or if the process in step S1505 is executed, the first notification display device 69a is controlled to display information corresponding to the type of parameter corresponding to the value of the target counter (step S1506). Furthermore, the parameter corresponding to the value of the target counter is read from the calculation result memory 131, and the read parameter is multiplied by 100. The digit corresponding to the tens place is displayed on the second notification display device 69b, and the digit corresponding to the units place is displayed on the third notification display device 69c (step S1507). The content displayed on the first to third notification display devices 69a to 69c in steps S1506 and S1507 is retained until the next update timing, or until the power supply to the management CPU 112 is stopped. Afterward, the update timing counter in the management RAM 114 is set to a value corresponding to 2 seconds as the value corresponding to the next update timing (step S1508).

As described above, once the display processing is executed and power is supplied to the management CPU 112, the game history management results are displayed on the first to third notification display devices 69a to 69c. This display of the game history management results is performed regardless of whether the game is continuing or not, and regardless of whether the game machine body 12 is opened from the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By performing display control on the first to third notification display devices 69a to 69c regardless of the game status or the state of the pachinko machine 10, the processing configuration for controlling the display of the first to third notification display devices 69a to 69c can be simplified.

The display of the game history management results in the first to third notification display devices 69a to 69c begins after the supply of operating power to the management CPU 112 has started and after the identification completion command has been received from the main CPU 63. In this case, the information stored in the calculation result memory 131 is retained even when the supply of operating power to the pachinko machine 10 is stopped, similar to the information stored in the history memory 117. Therefore, when the supply of operating power to the management CPU 112 is started, the game history management results calculated before the supply of operating power to the management CPU 112 was stopped are displayed.

When the setting state of the pachinko machine 10 is set when power is supplied to the main CPU 63, information corresponding to the setting value being changed is displayed on the third notification display device 69c. However, the display of this information corresponds to the setting value occurs before the identification completion command is sent from the main CPU 63, whereas the display of the game history management results on the first to third notification display devices 69a to 69c begins after the identification completion command is sent from the main CPU 63. This ensures that even if the third notification display device 69c is used for both displaying information corresponding to the setting value and displaying the game history management results, the display periods for these displays do not overlap.

Furthermore, when information corresponding to the set value is displayed, the first notification display device 69a and the second notification display device 69b are hidden. Conversely, when the game history management results are displayed, the first notification display device 69a and the second notification display device 69b remain visible. This allows the third notification display device 69c to identify whether information corresponding to the set value or the game history management results are being displayed.

Next, we will describe the processing configuration for outputting history information stored in the history memory 117 and various parameters stored in the calculation result memory 131 to an external device electrically connected to the read terminal 68d of the MPU 62. Figure 32(a) is a flowchart showing the data output processing executed by the main CPU 63. Note that the data output processing is executed in step S112 of the main processing (Figure 9).

In the data output process, it is first determined whether or not a connection signal indicating that an external device is electrically connected to the reading terminal 68d has been received from the reading terminal 68d (step S1601). If a negative determination is made in step S1601, the data output process is terminated. In this case, in order for the data output process to be executed, it is necessary to restart the supply of operating power to the main CPU 63. In order for the history information and various parameters to be output externally, it is necessary to restart the supply of operating power to the main CPU 63 with the external device electrically connected to the reading terminal 68d. The power switch for stopping and starting the supply of operating power to the main CPU 63 is provided in the payout mechanism 73 mounted on the back of the back pack unit 15. Therefore, in order to perform these stopping and starting operations, it is necessary to open the game machine body 12 against the outer frame 11 and expose the back of the back pack unit 15. In this context, in order to enable the external output of history information and various parameters, the system must be configured such that the supply of operating power to the main CPU 63 begins only when an external device is electrically connected to the reading terminal 68d. This configuration makes it difficult for anyone other than the gaming hall administrator to read the history information and various parameters.

If a positive result is obtained in step S1601, it is determined whether a signal for confirming control information is received from the reading terminal 68d, thereby determining whether the current connection of the external device to the reading terminal 68d corresponds to the confirmation of control information (program and data) of the main ROM 64 (step S1602). The external device is configured to perform both confirmation of control information and confirmation of history information and various parameters. If confirmation of control information is selected by manual operation of the external device, a signal for confirming control information is transmitted from the external device. If confirmation of history information and various parameters is selected by manual operation of the external device, a signal for confirming history is transmitted from the external device. However, this is not limited to this configuration, and the external device for confirming control information and the external device for confirming history may be separate. In this case, if the external device for confirming control information is electrically connected to the reading terminal 68d, a signal for confirming control information is transmitted from that external device. If the external device for confirming history is electrically connected to the reading terminal 68d, a signal for confirming history is transmitted from that external device.

If a positive result is obtained in step S1602, output processing for confirming control information is executed (step S1603). In this output processing, the program and data are read from the main ROM 64 as control information, and the read control information is output to the reading terminal 68d. This makes it possible to read the control information using an external device electrically connected to the reading terminal 68d, allowing verification of whether the control information is legitimate or normal.

If a negative determination is made in step S1602, an output instruction signal is sent to the management CPU 112 (step S1604). Specifically, the output state of the output instruction signal is switched from LOW level to HI level. This HI level output state continues for a specific period. This specific period is sufficient for the management CPU 112 to determine that a HI level output instruction signal has been input to the 16th buffer 122p. When the output state of the output instruction signal is switched to HI level, the management CPU 112 executes processing to output history information.

Specifically, as shown in the flowchart of Figure 32(b), when the output state of the output instruction signal input to the 16th buffer 122p of the input port 121 switches from a LOW level to a HI level (step S1701: YES), the management CPU 112 reads the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131, and outputs the read history information and various parameters to the reading terminal 68d (step S1702). This makes it possible for an external device electrically connected to the reading terminal 68d to read the history information and various parameters, enabling analysis of the game history management results. Furthermore, when the management CPU 112 outputs the history information to the reading terminal 68d, it clears the history memory 117 to "0" (step S1703). The history information in the history memory 117 is erased only when the history information is read by an external device.

Returning to the explanation of the data output process (Figure 32(a)), if the process in step S1603 or step S1604 is executed, it is determined whether the electrical connection of the external device to the reading terminal 68d is still active (step S1605). If it is still active (step S1605: YES), the process remains in wait at step S1605. This prevents processes scheduled for execution after the data output process from being executed until the connection of the external device to the reading terminal 68d is disconnected. If the connection of the external device to the reading terminal 68d is disconnected (step S1605: NO), the data output process terminates.

The embodiment described in detail above provides the following excellent effects.

Since game balls are dispensed when they enter any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, and the second operation slot 34, players play the game expecting game balls to enter one of these entry slots. In this configuration, when a game ball enters any of the out slot 24a, the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, and the second operation slot 34 (hereinafter also referred to as the history target entry slots), the corresponding history information is stored in the history memory 117 of the management IC 66. This makes it possible for the pachinko machine 10 to store information for managing the number of game balls entered or the frequency of entry into each history target entry slot, and by using this managed information, it becomes possible to appropriately manage the manner in which game balls enter each history target entry slot. Furthermore, since the history information is stored in the pachinko machine 10 itself, it is possible to prevent unauthorized access to or modification of the history information.

All ball entry points that eject game balls from the game area PA are subject to history information storage processing and management using that history information. This makes it possible to manage the ball entry frequency for any designated ball entry point using the history information. Furthermore, it becomes possible to manage the ratio of game balls entered into each designated ball entry point to the total number of game balls ejected from the game area PA, using the history information.

The history information includes RTC (Real-Time Clock) information, which corresponds to the timing when a game ball entered the designated ball entry area that triggered the recording of that history information. This allows for a detailed understanding of the game ball entry history into the designated ball entry area by utilizing the history information.

The history memory 117 stores not only history information corresponding to the entry of a game ball into the history target ball entry section, but also history information indicating whether or not the system is in opening/closing execution mode, whether or not it is in high-frequency support mode, and whether or not the front door frame 14 is open. This allows for the management of game ball entry patterns into the history target ball entry section by distinguishing between these various situations.

The history information stored in the history memory 117 can be output to an external device, which is an external device to the pachinko machine 10. This allows the external device to read the history information and use that information to analyze the pattern of game ball entry into the history target ball entry section.

The MPU 62 is provided with a read terminal 68d, allowing an external device electrically connected to this terminal to read the program from the main ROM 64. This makes it possible to verify whether the program is functioning correctly. In this configuration, the read terminal 68d, used for external program output, is used to output history information stored in the history memory 117. This allows for the external output of history information while preventing the configuration from becoming overly complex.

The system identifies whether the information to be output from the reading terminal 68d is program information or history information, and the information corresponding to that identification result is output externally through the reading terminal 68d. This allows the pachinko machine 10 to identify whether the information to be output externally is program information or history information, even in a configuration where the reading terminal 68d is used for both program and history information output. Therefore, even in a configuration where the reading terminal 68d is used for both, it becomes possible to read only the necessary information.

Based on information received from an external device electrically connected to the reading terminal 68d, it is determined whether the information to be output from the reading terminal 68d is program information or history information. This prevents the configuration for selecting the information to be output externally from becoming overly complex.

The MPU 62, which has a main ROM 64 for pre-storing programs, also has a management IC 66 and a read terminal 68d. This allows the signal path to the read terminal 68d to be consolidated within the MPU 62. Therefore, it becomes difficult to perform unauthorized access to the signal path to the read terminal 68d while achieving the excellent effects already described.

In addition to the main CPU 63, which executes processing to ensure that game balls are dispensed based on their entry into any of the general prize entry slot 31, special electric prize entry device 32, first operation slot 33, and second operation slot 34, a separate management CPU 112 is provided. This management CPU 112 executes processing to store history information in the history memory 117. This makes it possible to manage the entry patterns of game balls into each history target entry slot without excessively increasing the processing load of the main CPU 63.

The main CPU 63 and the management CPU 112 are provided on the same chip as the MPU 62. This makes it possible to prevent unauthorized access to the communication path between the main CPU 63 and the management CPU 112.

The main CPU 63 transmits information corresponding to the detection results of each ball entry detection sensor 42a to 48a to the respective buffers 122a to 122g of the input port 121 of the management IC 66, using the signal paths corresponding to each of the ball entry detection sensors 42a to 48a. This ensures that the type of information transmitted from the main CPU 63 corresponds to each buffer 122a to 122g (i.e., each signal path), simplifying the configuration required for the management CPU 112 to distinguish between different types of information.

The main CPU 63 transmits information corresponding to whether or not the system is in opening/closing execution mode, whether or not it is in high-frequency support mode, whether or not the front door frame 14 is open, and information corresponding to the start of a game round to the respective buffers 122h to 122k of the input port 121 of the management IC 66, using the signal paths corresponding to each of these conditions. This ensures that the type of information corresponding to each of these conditions corresponds to each buffer 122h to 122k (i.e., each signal path), simplifying the configuration for distinguishing the types of information in the management CPU 112.

The main CPU 63 transmits correspondence information to the management CPU 112 indicating which type of information each buffer 122a to 122k (i.e., each signal path 118a to 118k) corresponds to. This eliminates the need for the management IC 66 to pre-store this correspondence information. Therefore, the versatility of the management IC 66 can be increased.

When power is supplied to the main CPU 63, correspondence information is transmitted from the main CPU 63 to the management IC 66. This allows the management IC 66 to identify the correspondence between the information transmitted from the main CPU 63 and the ball entry section in situations where a game ball may be entered into the ball entry section.

Correspondence information is transmitted from the main CPU 63 to the management IC 66 using signal paths 118a to 118g, which are used to transmit information indicating whether or not a game ball has entered the ball entry section of the history target. This simplifies the communication configuration compared to a configuration with a dedicated signal path for transmitting correspondence information.

The management IC 66 is equipped with a correspondence memory 116, and the correspondence information transmitted from the main CPU 63 to the management IC 66 is stored in the correspondence memory 116. This eliminates the need for the main CPU 63 to provide information that would allow the management IC 66 to identify the corresponding ball entry point in the history, each time it transmits detection result information from each ball entry detection sensor 42a to 48a. Therefore, the amount of information transmitted from the main CPU 63 regarding the detection results of each ball entry detection sensor 42a to 48a can be reduced.

When the output state of the output instruction signal output from the main CPU 63 to the management IC 66 switches from a LOW level to a HI level, information is output from the management IC 66 to the read terminal 68d. In this case, the management CPU 112 can determine that the signal path corresponding to the 16th buffer 122p corresponds to the output instruction signal without receiving correspondence information from the main CPU 63. This makes it possible to prevent the configuration for transmitting correspondence information from becoming excessively complex.

The management IC 66 is equipped with buffers 122a to 122p capable of receiving information from the main CPU 63, with a number of buffers greater than the number of types of information that need to be transmitted from the main CPU 63 to the management IC 66. This allows the system to handle variations in the number of information types depending on the model of the pachinko machine 10 without changing the configuration of buffers 122a to 122p. Therefore, the versatility of the management IC 66 is enhanced.

When history information is transmitted from the management IC 66 to the reading terminal 68d, each history entry contains correspondence information indicating the type of ball entry section corresponding to that history entry information. This makes it possible to identify the method of ball entry into each history entry section using the read history information.

In the management IC 66, various parameters (parameters 1 to 8, parameters 11 to 18, parameters 21 to 26, parameter 31, and parameters 41 to 42) corresponding to the ball entry patterns in the game area PA during a predetermined period are calculated using the history information stored in the history memory 117. These calculated parameters are then sequentially displayed on the first to third notification display devices 69a to 69c. This makes it possible to notify the pachinko machine 10 of the parameters calculated using the history information.

Various parameters are calculated while excluding historical information corresponding to the situation where the front door frame 14 is open. This makes it possible to derive various parameters for the normal situation where the front door frame 14 is closed. Furthermore, various parameters corresponding to the open/close execution mode and the high-frequency support mode are calculated. This allows game hall managers and others to understand the ball entry patterns according to each situation.

When history information from the history memory 117 is output to an external device, the history memory 117 is initialized by executing a clear process. This makes it less likely that history information exceeding the storage capacity of the history memory 117 will be overwritten and erased, thus preventing the occurrence of such an event.

In a configuration where an external output is generated via the external terminal board 97 when a game ball enters the first or second operation port 33 or 34, history information is stored in the history memory 117. This allows for a simple understanding of the number and frequency of game balls entering the first and second operation ports 33 and 34 by utilizing the information output externally via the external terminal board 97, while simultaneously enabling accurate determination of the number and frequency of game balls entering the target ball entry points by utilizing the history information stored in the history memory 117.

In low-probability mode, the probability of hitting a jackpot varies depending on the setting of the pachinko machine 10, from "Setting 1" to "Setting 6". This makes it possible to create situations where the probability of hitting a jackpot is favorable or unfavorable even within a single pachinko machine 10. Therefore, it is possible to enhance the enjoyment of the game.

In low-probability mode, the probability of hitting a jackpot varies depending on the setting of the pachinko machine 10 ("Setting 1" to "Setting 6"), while in high-probability mode, the probability of hitting a jackpot does not vary depending on the setting of the pachinko machine 10. This makes it possible to limit the influence of the setting of the pachinko machine 10 on the probability of hitting a jackpot to the situation in low-probability mode. Furthermore, since the high-probability win/loss table 64g referenced in high-probability mode can be common regardless of the setting of the pachinko machine 10, it becomes possible to suppress the increase in storage capacity required to pre-store win/loss tables 64a to 64g in the main ROM 64.

In low-probability mode, the probability of achieving a jackpot varies depending on the setting of the pachinko machine 10 ("Setting 1" to "Setting 6"), while the distribution pattern of jackpot types does not vary depending on the setting of the pachinko machine 10. This makes it possible to limit the influence of the pachinko machine 10's setting to the situation in low-probability mode. Furthermore, since the distribution table 64h, which is referenced when distributing jackpot types, can be common regardless of the setting of the pachinko machine 10, it becomes possible to suppress the increase in storage capacity required to pre-store the distribution table 64h in the main ROM 64.

Even if the settings of the pachinko machine 10 are changed, the history information stored in the history memory 117 is not erased and is retained. This allows the history information to be continuously stored in the history memory 117 even after the settings of the pachinko machine 10 are changed, making it possible to identify the results of game history management using the history information accumulated in the history memory 117 over a long period.

In a configuration where the history information stored in the history memory 117 is retained even when the settings of the pachinko machine 10 are changed, the corresponding history information is stored in the history memory 117 when the settings of the pachinko machine 10 are changed. This makes it possible to distinguish between the history information before and after the settings of the pachinko machine 10 are changed.

When a new setting is made to the settings state of the pachinko machine 10, and the corresponding history information is stored in the history memory 117, the information corresponding to that setting value is included in that history information. This makes it possible to identify the content of previously set settings by referring to the history information.

Furthermore, when calculating various parameters at the calculation timing, the system may be configured to use the history information stored later in the history memory 117, based on the history information corresponding to the new setting of the pachinko machine 10's configuration state, to calculate the various parameters. In this case, it becomes possible to derive the management results of the game history at the timing after the new setting of the pachinko machine 10's configuration state has been made as various parameters.

Furthermore, when calculating various parameters at the calculation timing, the history memory 117 may be configured to use the history information corresponding to the new setting of the pachinko machine 10's settings, specifically the history information corresponding to the change in the setting value, as a reference, and then use the history information stored after that to calculate the various parameters. In this case, it becomes possible to derive the management results of the game history at the timing after the setting state of the pachinko machine 10 has been changed as various parameters.

Furthermore, while the main control device 60's circuit board box 60a is configured to have an opening for exposing the reading terminal 68d, it is also possible to have a configuration where this opening is not provided and the reading terminal 69d is covered by the opposing wall portion 60b. In this case, it would be necessary to open the circuit board box 60a in order to connect an external device to the reading terminal 68d.

<Second Embodiment>
In this embodiment, the contents of the win/loss table corresponding to the setting state of the pachinko machine 10 differ from those of the first embodiment. The configurations that differ from the first embodiment will be described below. Configurations that are the same as those of the first embodiment will generally not be described.

Figure 33 is an explanatory diagram illustrating the various tables stored in the main ROM 64 in this embodiment.

As shown in Figure 33, the main ROM 64 is provided with an area 161 for setting 1, an area 162 for setting 2, an area 163 for setting 3, an area 164 for setting 4, an area 165 for setting 5, and an area 166 for setting 6. The area 1 for setting 1 stores a low probability win/loss table 161a for setting 1, which is referenced when the setting state of the pachinko machine 10 is "setting 1" and the win/loss lottery mode is the low probability mode, and a high probability win/loss table 161b for setting 1, which is referenced when the setting state of the pachinko machine 10 is "setting 1" and the win/loss lottery mode is the high probability mode. Area 162 for setting 2 stores a low probability win/loss table 162a for setting 2, which is referenced when the setting state of the pachinko machine 10 is "setting 2" and the win/loss lottery mode is the low probability mode, and a high probability win/loss table 162b for setting 2, which is referenced when the setting state of the pachinko machine 10 is "setting 2" and the win/loss lottery mode is the high probability mode. Area 163 for setting 3 stores a low probability win/loss table 163a for setting 3, which is referenced when the setting state of the pachinko machine 10 is "setting 3" and the win/loss lottery mode is the low probability mode, and a high probability win/loss table 163b for setting 3, which is referenced when the setting state of the pachinko machine 10 is "setting 3" and the win/loss lottery mode is the high probability mode.

Area 164 for setting 4 stores a low probability win/loss table 164a for setting 4, which is referenced when the setting state of the pachinko machine 10 is "setting 4" and the win/loss lottery mode is the low probability mode, and a high probability win/loss table 164b for setting 4, which is referenced when the setting state of the pachinko machine 10 is "setting 4" and the win/loss lottery mode is the high probability mode. Area 165 for setting 5 stores a low probability win/loss table 165a for setting 5, which is referenced when the setting state of the pachinko machine 10 is "setting 5" and the win/loss lottery mode is the low probability mode, and a high probability win/loss table 165b for setting 5, which is referenced when the setting state of the pachinko machine 10 is "setting 5" and the win/loss lottery mode is the high probability mode. Area 166 for setting 6 stores a low-probability win/loss table 166a for setting 6, which is referenced when the setting state of the pachinko machine 10 is "setting 6" and the win/loss lottery mode is the low-probability mode, and a high-probability win/loss table 166b for setting 6, which is referenced when the setting state of the pachinko machine 10 is "setting 6" and the win/loss lottery mode is the high-probability mode.

The probability of winning a jackpot in each of the low-probability win/loss tables 161a to 166a differs from one another. Specifically, when low-probability win/loss table 161a for setting 1 is referenced, the probability of winning a jackpot is approximately 1/320; when low-probability win/loss table 162a for setting 2 is referenced, the probability is approximately 1/310; when low-probability win/loss table 163a for setting 3 is referenced, the probability is approximately 1/300; when low-probability win/loss table 164a for setting 4 is referenced, the probability is approximately 1/290; when low-probability win/loss table 165a for setting 5 is referenced, the probability is approximately 1/280; and when low-probability win/loss table 166a for setting 6 is referenced, the probability is approximately 1/270. This means that a higher setting for the pachinko machine 10 makes it easier to win a jackpot in low-probability mode, which is advantageous for the player.

The probability of winning a jackpot in each of the high-probability win/loss tables 161b to 166b differs from one another. Specifically, when high-probability win/loss table 161b for setting 1 is referenced, the probability of winning a jackpot is approximately 1/45; when high-probability win/loss table 162b for setting 2 is referenced, the probability is approximately 1/40; when high-probability win/loss table 163b for setting 3 is referenced, the probability is approximately 1/35; when high-probability win/loss table 164b for setting 4 is referenced, the probability is approximately 1/30; when high-probability win/loss table 165b for setting 5 is referenced, the probability is approximately 1/25; and when high-probability win/loss table 166b for setting 6 is referenced, the probability is approximately 1/20. Therefore, a higher setting value for the pachinko machine 10 makes it easier to win a jackpot in high-probability mode, which is advantageous for the player.

In other words, in the first embodiment described above, the probability of winning a jackpot in low probability mode increased as the setting value of the pachinko machine 10 increased, while the probability of winning a jackpot in high probability mode remained the same regardless of the setting value from "Setting 1" to "Setting 6". However, in this embodiment, both the probability of winning a jackpot in low probability mode and the probability of winning a jackpot in high probability mode increase as the setting value of the pachinko machine 10 increases. This makes it possible to increase the advantage for the player when a high setting value is set.

Furthermore, even the probability of winning a jackpot in the low-probability mode when the highest setting is "Setting 6" is set lower than the probability of winning a jackpot in the high-probability mode when the lowest setting is "Setting 1". This prevents the player's advantage from becoming extremely low when the pachinko machine 10 is set to "Setting 1," and also prevents the player's advantage from becoming extremely high when the pachinko machine 10 is set to "Setting 6."

On the other hand, similar to the first embodiment described above, only one distribution table 64h is provided so that it is common regardless of which setting state is "Setting 1" to "Setting 6". This makes it possible to prevent any advantage or disadvantage in the distribution of jackpot results depending on the setting state of the pachinko machine 10, and also reduces the storage capacity required to pre-store the distribution table 64h in the main ROM 64.

Furthermore, the probability of winning a jackpot in low-probability mode is higher when the settings of the pachinko machine 10 are higher, while the probability of winning a jackpot in high-probability mode is lower when the settings of the pachinko machine 10 are higher. In this case, in low-probability mode, a higher setting of the pachinko machine 10 is more advantageous for the player, and in high-probability mode, a lower setting of the pachinko machine 10 is more advantageous for the player.

Furthermore, the probability of winning a jackpot in high-probability mode is higher when the setting of the pachinko machine 10 is higher, while the probability of winning a jackpot in low-probability mode may be set to be constant across settings "Setting 1" to "Setting 6". In this case, in high-probability mode, a higher setting of the pachinko machine 10 is more advantageous for the player, while in low-probability mode, it becomes possible to ensure that there is no advantage or disadvantage based on the setting of the pachinko machine 10.

<Third Embodiment>
In this embodiment, the handling of the game history management results when the settings state of the pachinko machine 10 is newly set differs from that of the first embodiment. The configurations that differ from those of the first embodiment will be described below. Configurations that are the same as those of the first embodiment will generally not be described.

The management IC 66 is provided with a separate storage memory 171 in addition to the memories described in the first embodiment, for storing information. Figure 34 is an explanatory diagram illustrating the separate storage memory 171. The separate storage memory 171 is a memory that does not require external power supply for storage (i.e., a non-volatile storage means), such as a NOR-type flash memory or a NAND-type flash memory, and is used for both reading and writing.

The separate storage memory 171 is provided with a first separate storage area 172, a second separate storage area 173, a third separate storage area 174, a fourth separate storage area 175, and a fifth separate storage area 176. These first to fifth separate storage areas 172 to 176 sequentially store information on the management results of the game history calculated when the settings state of the pachinko machine 10 is newly set, more specifically, the various parameters (first to eighth parameters, eleventh to eighteenth parameters, twenty-first to twenty-sixth parameters, thirty-first parameter, and forty-first to forty-second parameters) described in the first embodiment above. In this case, when the settings state of the pachinko machine 10 is newly set, the various parameters are first stored in the first separate storage area 172, and thereafter, each time the settings state of the pachinko machine 10 is newly set, the storage area is switched from the nth separate storage area 172 to 176 to the n+1th separate storage area 172 to 176. Then, after the various parameters have been stored in the fifth separate storage area 176, if the settings of the pachinko machine 10 are newly set, the various parameters are stored again in the first separate storage area 172. At this time, the various parameters already stored in the first separate storage area 172 are erased. As a result, the various parameters up to five new settings of the pachinko machine 10 are stored in the separate storage memory 171. For settings exceeding five, the oldest parameters are erased before storage.

The various parameters stored in the first to fifth separate storage areas 172 to 176 can be read by an external device connected to the reading terminal 68d. This makes it possible to understand the management results of the game history before a new setting is made in the pachinko machine 10.

Next, the configuration update recognition process in this embodiment, executed by the management CPU 112, will be explained with reference to the flowchart in Figure 35.

When the setting value update signal input to the 15th buffer 122o of input port 121 switches from a LOW level to a HI level (step S1801: YES), the value of the setting value recognition counter in the management-side RAM 114 is set to "1" (step S1802). The setting value recognition counter is a counter used by the management-side CPU 112 to identify the setting value of the pachinko machine 10. For example, a value of "1" in the setting value recognition counter means "setting 1," and a value of "6" means "setting 6."

Subsequently, it is determined whether the setting value update signal input to the 15th buffer 122o of input port 121 has switched back from the LOW level to the HI level (step S1803). If the determination in step S1803 is positive, the value of the setting value recognition counter in the management-side RAM 114 is incremented by 1 (step S1804). As a result, the setting value of the pachinko machine 10 identified by the management-side CPU 112 increases by one level.

If a negative result is obtained in step S1803, or if the process in step S1804 is executed, it is determined whether or not a setting value identification completion command has been received from the main CPU 63, based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1805). If a negative result is obtained in step S1805, the process returns to step S1803.

If a positive result is obtained in step S1805, the repeated change monitoring process is executed (step S1806). The repeated change monitoring process, as detailed later, executes a process to notify the system if the settings of the pachinko machine 10 are repeatedly changed in a short period of time. In a configuration where various parameters are stored in a separate storage memory 171 each time the settings of the pachinko machine 10 are changed, it is anticipated that the settings of the pachinko machine 10 will be repeatedly changed in a short period of time in order to intentionally erase the management results of the game history when the game has been played for a predetermined period. The repeated change monitoring process ensures that a notification is issued when such an action occurs.

Subsequently, various calculation processes are executed (step S1807). These calculation processes execute the processes of steps S1402 to S1412 of the display output process (Figure 30) in the first embodiment described above. This allows various parameters (parameters 1 to 8, parameters 11 to 18, parameters 21 to 26, parameter 31, and parameters 41 to 42) to be calculated using the history information stored in the history memory 117 at that point.

Subsequently, the various parameters calculated in step S1807 are stored in the area designated for storage in the first to fifth separate storage areas 172 to 176 of the separate storage memory 171 (step S1808). The separate storage memory 171 contains a pointer information area that allows the management CPU 112 to identify the area to be stored among the first to fifth separate storage areas 172 to 176. The information in this pointer information area is updated so that when various parameters are stored in the area designated for storage among the first to fifth separate storage areas 172 to 176, the storage target changes to the next area in order. As a result of the execution of step S1808, the various parameters at that time for the new setting of the pachinko machine 10 are stored in the separate storage memory 171.

Subsequently, the history memory 117 is cleared to "0" (step S1809). In other words, in this embodiment, the history information in the history memory 117 is erased not only when the history information is read by an external device connected to the reading terminal 68d, but also when the settings of the pachinko machine 10 are newly set.

Subsequently, the RTC information, which includes date and time information, is read from the RTC 115 (step S1810). Then, a write operation to the history memory 117 is performed (step S1811). In this write operation, the pointer information of the history area 124 currently being written to is identified by referring to the pointer area 126 of the history memory 117. The RTC information read in step S1810 is then written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. Furthermore, both information to identify that it is a set value and information about the value of the set value recognition counter are written to the history information storage area 125 corresponding to the pointer information being written to. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, the RTC information corresponding to the date and time the setting was made, and the setting value information when the setting was made is stored as history information.

Subsequently, the update process for the target pointer is executed (step S1812). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. It is then determined whether the pointer information after the increment exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

Next, the monitoring process for repeated changes, which is performed in step S1806, will be explained with reference to the flowchart in Figure 36.

First, it is determined whether the number of game rounds played since the last setting of the pachinko machine 10 was determined is within a certain limit (specifically, 100 rounds) (step S1901). Specifically, the number of game rounds played since the last setting of the pachinko machine 10 was determined by counting the number of corresponding relationship information stored in the history area 124 of the history memory 117, which indicates the start of a game round. Furthermore, it is determined whether the determined number of game rounds is within a certain limit (specifically, 100 rounds).

If a positive result is obtained in step S1901, the value of the repeat change counter in the separate storage memory 171 is incremented by 1 (step S1902). As explained earlier, the separate storage memory 171 does not require external power supply for memory retention; therefore, the repeat change counter value also does not require external power supply for memory retention.

Subsequently, it is determined whether the value of the repeat change counter after the increment exceeds the notification threshold value of "5" (step S1903). The notification threshold value corresponds to the number of separate storage areas 172 to 176 provided in the separate storage memory 171. Therefore, in step S1903, it is determined whether the number of times the setting state of the pachinko machine 10 has been repeatedly changed without any intervening game play exceeding the threshold number exceeds the number of separate storage areas 172 to 176.

If a positive determination is made in step S1903, the recurring change display process is executed (step S1904). In the recurring change display process, the display content of the first to third notification display devices 69a to 69c is set to the recurring change display content corresponding to the fact that a new setting of the setting state of the pachinko machine 10 has been repeated more times than the notification standard value in a short period of time. The display content of this recurring change is to display "E" in all of the first to third notification display devices 69a to 69c, and this display content does not occur in other situations. Furthermore, the state in which the recurring change display content is displayed in the first to third notification display devices 69a to 69c continues until the recurring change flag set in the separate storage memory 171 is cleared to "0". The recurring change flag is a flag used by the management CPU 112 to identify that the situation is such that the recurring change display content should be displayed in the first to third notification display devices 69a to 69c. Furthermore, if the repeat change flag is set to "1" and the content of the repeat change is displayed on the first to third notification display devices 69a to 69c, the display processing in the first embodiment (Figure 31) is not executed. Subsequently, the repeat change flag in the separate storage memory 171 is set to "1" (step S1905).

If a negative result is obtained in step S1901, the value of the repeat change counter in the separate storage memory 171 is cleared to "0" (step S1906). Then, provided that the repeat change flag in the separate storage memory 171 is set to "1" (step S1907: YES), the display of the repeat change information on the first to third notification display devices 69a to 69c is terminated (step S1908), and the repeat change flag is cleared to "0" (step S1909).

The embodiment described in detail above provides the following excellent effects.

When the settings of the pachinko machine 10 are changed, the history information stored in the history memory 117 is erased. This allows the history information of games played after the settings of the pachinko machine 10 have been changed to be retained in the history memory 117.

When a new setting is made to the pachinko machine 10, various parameters are calculated as a result of game history management using the history information in the history memory 117 at that time. This makes it possible to understand the game history management results in the state before the new setting was made to the pachinko machine 10. Furthermore, even if the history information in the history memory 117 is erased when a new setting is made to the pachinko machine 10, it is still possible to understand the game history management results based on the history information that was erased.

In a configuration where, when a new setting is made in the pachinko machine 10, various parameters are calculated using the history information in the history memory 117 at that time, these calculated parameters are stored in a separate storage memory 171. This makes it possible to understand the game history management results from before the new setting was made, even if a new setting is made in the pachinko machine 10, at any subsequent time.

By providing multiple separate storage areas 172-176 in the separate storage memory 171, it becomes possible to store various parameters corresponding to the timing of setting multiple times. This makes it possible to understand the management results of game history over multiple periods, based on the timing of new setting changes. Furthermore, even if the setting state of the pachinko machine 10 is repeatedly changed while no game is being played, it becomes possible to increase the likelihood that various parameters calculated using history information from situations where gameplay is actually taking place will remain in the separate storage memory 171.

The various parameters stored in the first to fifth separate storage areas 172 to 176 can be read by an external device connected to the reading terminal 68d. This makes it possible to understand the management results of the game history before a new setting is made in the pachinko machine 10.

In a configuration where various parameters are stored in a separate storage memory 171 each time the settings of the pachinko machine 10 are changed, it is anticipated that the settings of the pachinko machine 10 will be repeatedly changed in a short period of time in order to intentionally erase the management results of the game history when the game has been played for a predetermined period of time. In response to this, a monitoring process for repeated changes is executed, and if such an action occurs, a corresponding notification is issued. This makes it possible to notify administrators and others that the settings of the pachinko machine 10 have been repeatedly changed in a short period of time.

Notification of repeated changes to the settings of the pachinko machine 10 within a short period of time is provided by the first to third notification display devices 69a to 69c. This allows notification of repeated changes to the settings of the pachinko machine 10 within a short period of time to be provided using the first to third notification display devices 69a to 69c, which are used to notify the results of game history management.

In situations where notification should be given that the settings of the pachinko machine 10 have been repeatedly changed in a short period of time, the first to third notification display devices 69a to 69c will continuously display the content of the repeated changes, and the notification of the management results of the normal game history will not be provided by the first to third notification display devices 69a to 69c. This makes it possible to emphasize the notification that the settings of the pachinko machine 10 have been repeatedly changed in a short period of time.

Furthermore, while the system is configured to issue a notification if the number of times a new setting is performed after a new setting of the pachinko machine 10 has been made exceeds a notification threshold, and the number of times such a new setting is performed consecutively exceeds a notification threshold, the system is not limited to this configuration. Alternatively, the system may be configured to issue a notification if the number of times a new setting is performed after a new setting of the pachinko machine 10 has been made exceeds a notification threshold, and the total number of game balls discharged from the game area PA after a new setting of the pachinko machine 10 has been made is within a standard number. Also, the system may be configured to issue a notification if the number of times a new setting is performed after a new setting of the pachinko machine 10 has been made exceeds a notification threshold, and the total number of game balls discharged from a predetermined ball entry point (for example, one of the out-out opening 24a, general prize entry opening 31, first operation opening 33, and second operation opening 34, or a predetermined combination thereof) is within a standard number. Furthermore, the system may be configured such that if the number of newly stored history information entries in the history memory 117 after a new setting of the pachinko machine 10 has been made exceeds a notification threshold, and the number of such new setting events exceeds a notification threshold, a corresponding notification may be issued.

Furthermore, the system may be configured to issue a notification if a new setting of the pachinko machine 10 exceeds a notification threshold value within the monitoring period (e.g., 600 seconds).

Furthermore, while the system is configured to issue a notification if the number of game spins performed after a new setting of the pachinko machine 10 is performed exceeds a standard number, and the occurrence of such new settings exceeds a notification threshold, it may also be configured to issue a notification if the number of game spins performed after a new setting of the pachinko machine 10 is performed exceeds a standard number, and the occurrence of setting value changes exceeds a notification threshold.

Furthermore, while the system is configured to issue a notification if the number of game spins performed after a new setting of the pachinko machine 10 is performed exceeds a notification threshold, and the number of events in which such a new setting is performed exceeds a notification threshold, it may also be configured to issue a notification if the number of events in which various parameters are calculated triggered by the new setting exceeds a notification threshold, and the number of game spins performed after a new setting of the pachinko machine 10 is performed exceeds a threshold.

Furthermore, while the system is configured to issue a notification if the number of game spins performed after a new setting of the pachinko machine 10 is within a certain limit, and the number of times such new settings are performed consecutively exceeds a notification threshold, the system may also, in addition to or instead of this, restrict the progress of the game for a predetermined period (e.g., one hour).

<Fourth Embodiment>
This embodiment differs from the third embodiment in that the monitoring process for repeated changes is executed by the main CPU 63. The configurations that differ from the third embodiment will be described below. Configurations that are the same as those in the third embodiment will generally not be described.

Figure 37 is a flowchart showing the recurring change monitoring process executed by the main CPU 63. The recurring change monitoring process is executed when the setting value update process (step S118) is performed in the main process (Figure 9). In other words, the recurring change monitoring process is executed when the setting state of the pachinko machine 10 is newly set. However, this is not the only configuration; the recurring change monitoring process may be executed whenever the setting value is changed.

First, it is determined whether the number of game spins performed since the last setting of the pachinko machine 10 is within a certain limit (specifically, 100 spins) (step S2001). The main RAM 65 is equipped with a game spin counter to measure the number of game spins performed since the pachinko machine 10 was newly set. The main CPU 63 increments the game spin counter value by 1 each time a new game spin is performed. This game spin counter is excluded from being reset to "0" even when the main RAM 65 is cleared (steps S105, S117).

If a positive result is obtained in step S2001, the value of the repeat change counter in the main RAM 65 is incremented by 1 (step S2002). This repeat change counter is excluded from being reset to "0" even when the main RAM 65 is cleared (steps S105, S117).

Subsequently, it is determined whether the value of the repeat change counter after the increment exceeds the notification threshold value of "5" (step S2003). The notification threshold value corresponds to the number of the first to fifth separate storage areas 172 to 176 provided in the separate storage memory 171. Therefore, in step S2003, it is determined whether the number of times the setting state of the pachinko machine 10 has been repeatedly changed without any intervening game executions exceeding the threshold number exceeds the number of the first to fifth separate storage areas 172 to 176.

If a positive result is obtained in step S2003, the repeat change flag in the main RAM 65 is set to "1" (step S2004). The repeat change flag is used by the main CPU 63 to identify a situation where a repeat change notification should be issued. This repeat change flag is excluded from being cleared to "0" even when the main RAM 65 is cleared (steps S105 and S117).

If a negative result is obtained in step S2001, the value of the repeat change counter in the main RAM 65 is cleared to "0" (step S2005). Then, provided that the repeat change flag in the main RAM 65 is set to "1" (step S2006: YES), the repeat change flag is cleared to "0" (step S2007).

In the recurring change monitoring process, if the recurring change flag in the main RAM 65 is set to "1" (step S2008: YES), a recurring change notification command is sent to the audio/light emission control device 81 (step S2009). Upon receiving the recurring change notification command, the audio/light emission control device 81 causes the pattern display device 41, the display/light emission unit 53, and the speaker unit 54 to announce the recurring change. This announcement of the recurring change continues until the power supply to the audio/light emission control device 81 is cut off.

According to the above configuration, it becomes possible to notify the user of repeated changes to the settings of the pachinko machine 10 in a short period of time, based on control by the main CPU 63. Furthermore, since this notification is performed by the symbol display device 41, the display light-emitting unit 53, and the speaker unit 54, it is possible to inform the administrator that the settings of the pachinko machine 10 have been repeatedly changed in a short period of time, even without opening the game machine body 12 forward relative to the outer frame 11.

Furthermore, if the settings of the pachinko machine 10 are repeatedly changed in a short period of time, in addition to or instead of a configuration in which a notification command for repeated changes is sent from the main CPU 63 to the sound and light emission control device 81, a corresponding external output may be provided.

Furthermore, the system may be configured such that the monitoring process for repeated changes in this embodiment is executed on the main CPU 63, and the monitoring process for repeated changes in this third embodiment is executed on the management CPU 112. This makes it possible to strictly monitor whether or not the settings of the pachinko machine 10 are repeatedly changed in a short period of time.

<Fifth Embodiment>
In this embodiment, the processing configuration for setting update recognition in the management CPU 112 differs from that of the third embodiment. The configurations that differ from those of the third embodiment will be described below. Configurations that are the same as those of the third embodiment will generally not be described.

Figure 38 is a flowchart showing the configuration update recognition process executed by the management CPU 112 in this embodiment.

When the setting value update signal input to the 15th buffer 122o of input port 121 switches from a LOW level to a HI level (step S2101: YES), the value of the setting value recognition counter in the management-side RAM 114 is set to "1" (step S2102). The setting value recognition counter is a counter used by the management-side CPU 112 to identify the setting value of the pachinko machine 10. For example, a value of "1" in the setting value recognition counter means "setting 1," and a value of "6" means "setting 6."

Subsequently, it is determined whether the setting value update signal input to the 15th buffer 122o of input port 121 has switched back from the LOW level to the HI level (step S2103). If the determination in step S2103 is positive, the value of the setting value recognition counter in the management-side RAM 114 is incremented by 1 (step S2104). As a result, the setting value of the pachinko machine 10 identified by the management-side CPU 112 increases by one level.

If a negative result is obtained in step S2103, or if the process in step S2104 is executed, it is determined whether or not a setting value identification completion command has been received from the main CPU 63, based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2105). If a negative result is obtained in step S2105, the process returns to step S2103.

If a positive determination is made in step S2105, it is determined whether a predetermined number or more of predetermined history information exists in the history memory 117 (step S2106). Specifically, the number of history information storage areas 125, which store correspondence relationship information indicating the start of a game round in the history area 124 of the history memory 117, is counted to determine the number of game rounds that have been played since the setting state of the pachinko machine 10 was last set, and it is further determined whether the determined number of game rounds exceeds a standard number (specifically 100 times). However, it is not limited to this, and the configuration may also be such that in step S2106, it is determined whether the number of history information storage areas 125, which store correspondence relationship information indicating that a game ball has been ejected from the game area PA, exceeds a standard number (specifically 1000). Furthermore, the system may be configured to determine in step S2106 whether the number of entries in the history information storage area 125, which stores correspondence information indicating that a game ball has entered a predetermined ball entry point (for example, one of the out entry point 24a, the general prize entry point 31, the first operation point 33, and the second operation point 34, or a predetermined combination thereof), exceeds a standard number (specifically, 1000 entries). Alternatively, the system may be configured to determine in step S2106 whether the total number of history information entries stored in the history memory 117 exceeds a standard number (specifically, 1000 entries).

Furthermore, while the system is configured to issue a notification if the number of times a new setting is performed after a new setting of the pachinko machine 10 has been made exceeds a notification threshold, and the number of times such a new setting is performed consecutively exceeds a notification threshold, the system is not limited to this configuration. Alternatively, the system may be configured to issue a notification if the number of times a new setting is performed after a new setting of the pachinko machine 10 has been made exceeds a notification threshold, and the total number of game balls discharged from the game area PA after a new setting of the pachinko machine 10 has been made is within a standard number. Also, the system may be configured to issue a notification if the number of times a new setting is performed after a new setting of the pachinko machine 10 has been made exceeds a notification threshold, and the total number of game balls discharged from a predetermined ball entry point (for example, one of the out-out opening 24a, general prize entry opening 31, first operation opening 33, and second operation opening 34, or a predetermined combination thereof) is within a standard number. Furthermore, the system may be configured such that if the number of newly stored history information entries in the history memory 117 after a new setting of the pachinko machine 10 has been made exceeds a notification threshold, and the number of such new setting events exceeds a notification threshold, a corresponding notification may be issued.

If a positive result is obtained in step S2106, various calculation processes are executed (step S2107). These calculation processes execute the processes from steps S1402 to S1412 of the display output process (Figure 30) in the first embodiment described above. This allows various parameters (parameters 1 to 8, parameters 11 to 18, parameters 21 to 26, parameter 31, and parameters 41 to 42) to be calculated using the history information stored in the history memory 117 at that point.

Subsequently, the various parameters calculated in step S2107 are stored in the area designated for storage in the separate storage memory 171, specifically in the first to fifth separate storage areas 172 to 176 (step S2108). The separate storage memory 171 contains a pointer information area that allows the management CPU 112 to identify the area to be stored among the first to fifth separate storage areas 172 to 176. The information in this pointer information area is updated so that when various parameters are stored in the area designated for storage among the first to fifth separate storage areas 172 to 176, the storage target changes to the next area in order. As a result of the execution of step S2108, the various parameters at that time are stored in the separate storage memory 171 for the new settings of the current pachinko machine 10.

If a negative determination is made in step S2106, or if the process in step S2108 is executed, the history memory 117 is cleared to "0" (step S2109). In other words, in this embodiment, the history information in the history memory 117 is erased not only when the history information is read by an external device connected to the reading terminal 68d, but also when the settings of the pachinko machine 10 are newly set.

Subsequently, the RTC information, which includes date and time information, is read from the RTC 115 (step S2110). Then, a write operation to the history memory 117 is performed (step S2111). In this write operation, the pointer information of the history area 124 currently being written to is identified by referring to the pointer area 126 of the history memory 117. The RTC information read in step S2110 is then written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. Furthermore, both information to identify that it is a set value and information about the value of the set value recognition counter are written to the history information storage area 125 corresponding to the pointer information being written to. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, the RTC information corresponding to the date and time the setting was made, and the setting value information when the setting was made is stored as history information.

Subsequently, the update process for the target pointer is executed (step S2112). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. It is then determined whether the pointer information after the increment exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

According to the above configuration, when the settings of the pachinko machine 10 are newly set, provided that a predetermined number of history entries are stored in the history memory 117, various parameters are calculated using the history information stored in the history memory 117, and these parameters are stored in the separate storage memory 171. This makes it possible to store information regarding the management results of the game history, which is essentially the result of actual gameplay, in the separate storage memory 171, even if the settings of the pachinko machine 10 are repeatedly changed in a short period of time.

Furthermore, the process in step S2109 may be configured to be executed only if the processes in steps S2107 and S2108 have been executed. In other words, the history information stored in the history memory 117 is erased only if a predetermined number of history entries or more are stored in the history memory 117. This prevents the history information in the history memory 117 from being erased even if the settings of the pachinko machine 10 are repeatedly changed in a short period of time.

<Sixth Embodiment>
In this embodiment, the configuration of the history memory 117 differs from that of the first embodiment. The configuration that differs from that of the first embodiment will be described below. Configurations that are the same as those of the first embodiment will generally not be described.

Figure 39 is an explanatory diagram illustrating the configuration of the history memory 117 in this embodiment.

The history memory 117 is provided with a total area 141, a first state area 142, a second state area 143, and a third state area 144. Each of these areas 141 to 144 is provided with first to fourteenth counters 141a to 141n, 142a to 142n, 143a to 143n, and 144a to 144n. The first counters 141a to 144a in each area 141 to 144 store information on the number of times the output state of the first signal input to the first buffer 122a has been changed from a LOW level to a HI level. The second counters 141b to 144b in each area 141 to 144 store information on the number of times the output state of the second signal input to the second buffer 122b has been changed from a LOW level to a HI level. The third counters 141c to 144c in each area 141 to 144 store information on the number of times the output state of the third signal input to the third buffer 122c has been changed from a LOW level to a HI level. The fourth counters 141d to 144d in each area 141 to 144 store information on the number of times the output state of the fourth signal input to the fourth buffer 122d has been changed from a LOW level to a HI level. The fifth counters 141e to 144e in each area 141 to 144 store information on the number of times the output state of the fifth signal input to the fifth buffer 122e has been changed from a LOW level to a HI level. The sixth counters 141f to 144f in each area 141 to 144 store information on the number of times the output state of the sixth signal input to the sixth buffer 122f has been changed from a LOW level to a HI level. In each area 141 to 144, the 7th counters 141g to 144g store information on the number of times the output state of the 7th signal input to the 7th buffer 122g has changed from a LOW level to a HI level. In each area 141 to 144, the 8th counters 141h to 144h store information on the number of times the output state of the 8th signal input to the 8th buffer 122h has changed from a LOW level to a HI level. In each area 141 to 144, the 9th counters 141i to 144i store information on the number of times the output state of the 9th signal input to the 9th buffer 122i has changed from a LOW level to a HI level. In each area 141 to 144, the 10th counters 141j to 144j store information on the number of times the output state of the 10th signal input to the 10th buffer 122j has changed from a LOW level to a HI level. In each area 141-144, the 11th counters 141k-144k store information on the number of times the output state of the 11th signal input to the 11th buffer 122k changed from a LOW level to a HI level. In each area 141-144, the 12th counters 141l-144l store information on the number of times the output state of the 12th signal input to the 12th buffer 122l changed from a LOW level to a HI level. In each area 141-144, the 13th counters 141m-144m store information on the number of times the output state of the 13th signal input to the 13th buffer 122m changed from a LOW level to a HI level. In each area 141-144, the 14th counters 141n-144n store information on the number of times the output state of the 14th signal input to the 14th buffer 122n changed from a LOW level to a HI level.

Figure 40 is a flowchart showing the history setting process in this embodiment, which is executed by the management CPU 112.

First, the number of buffers to be checked by the management CPU 112 from among the first to 14th buffers 122a to 122n is set in the verification target counter of the management RAM 114 (step S2201). Specifically, the number of correspondence areas in the correspondence memory 116 that contain information other than information indicating a blank state is identified, and this identified number of items is set in the verification target counter. In this pachinko machine 10, information other than information indicating a blank state is stored in the first to 11th correspondence areas 123a to 123k, so in step S2201, "11" is set in the verification target counter.

Subsequently, it is determined whether buffers 122a to 122n, which correspond to the current counter to be checked, are buffers into which status information signals are input (step S2202). Specifically, it is determined whether any of the following information is stored as correspondence information in the correspondence relationship areas 123a to 123n, which correspond to the current value of the counter to be checked: information indicating that it is in opening/closing execution mode, information indicating that it is in high-frequency support mode, or information indicating that it is the front door frame 14.

If a positive determination is made in step S2202, the state information setting process is executed (step S2203). In this setting process, if the output state of the 8th signal, which indicates whether or not the switch is in open/close execution mode, switches from a LOW level to a HI level, the information of the first state indicating that the switch is in open/close execution mode is stored in the management RAM 114. If the output state of the 8th signal switches from a HI level to a LOW level, the information of the first state is deleted from the management RAM 114. Also, if the output state of the 9th signal, which indicates whether or not the switch is in high-frequency support mode, switches from a LOW level to a HI level, the information of the second state indicating that the switch is in high-frequency support mode is stored in the management RAM 114. If the output state of the 9th signal switches from a HI level to a LOW level, the information of the second state is deleted from the management RAM 114. Furthermore, when the output state of the 10th signal, which indicates whether the front door frame 14 is open or closed, switches from a LOW level to a HI level, information indicating the 3rd state, which indicates that the front door frame 14 is open, is stored in the management RAM 114. When the output state of the 10th signal switches from a HI level to a LOW level, the information indicating the 3rd state is erased from the management RAM 114.

If a negative determination is made in step S2202, or if the process in step S2203 is executed, it is determined whether the output state of the input signal from the main CPU 63 to the buffer has been switched from a LOW level to a HI level by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fourteenth buffers 122a to 122n has been changed from "0" to "1" (step S2204). If the current value of the counter to be checked corresponds to the value of the eighth buffer 122h, and the numerical information stored in the eighth buffer 122h has been changed from "0" to "1", then in step S2203, the information of the first state is stored in the management RAM 114, and in step S2204, an affirmative determination is made. Furthermore, if the current value of the counter being checked corresponds to the value of the 9th buffer 122i, and the numerical information stored in the 9th buffer 122i changes from "0" to "1", then in step S2203, the information of the second state is stored in the management RAM 114, and in step S2204, a positive determination is made. Similarly, if the current value of the counter being checked corresponds to the value of the 10th buffer 122j, and the numerical information stored in the 10th buffer 122j changes from "0" to "1", then in step S2203, the information of the third state is stored in the management RAM 114, and in step S2204, a positive determination is made.

If a positive result is obtained in step S2204, the corresponding summation counter is incremented (step S2205). In this incrementing process, the value of the counter corresponding to the current value of the target counter is incremented by 1 among the first to fourteenth summation counters 141a to 141n in the summation area 141 of the history memory 117. For example, if the value of the target counter is "11", the eleventh summation counter 141k is incremented; if the value of the target counter is "5", the fifth summation counter 141e is incremented; and if the value of the target counter is "1", the first summation counter 141a is incremented.

Subsequently, the system determines whether it is in the first state, i.e., in the open/close execution mode, by referring to the state information of the management RAM 114 (step S2206). If it is in the first state (step S2206: YES), the system performs an increment process for the corresponding first state counter (step S2207). In this increment process, the value of the counter corresponding to the current value of the target counter among the first to 14 counters 142a to 142n for the first state in the first state area 142 of the history memory 117 is incremented by 1. For example, if the value of the target counter is "11", the 11th counter 142k for the first state is incremented; if the value of the target counter is "5", the 5th counter 142e for the first state is incremented; and if the value of the target counter is "1", the 1st counter 142a for the first state is incremented.

Subsequently, the system determines whether it is in the second state, i.e., in high-frequency support mode, by referring to the state information of the management RAM 114 (step S2208). If it is in the second state (step S2208: YES), the system performs an increment process for the corresponding second state counter (step S2209). In this increment process, the value of the counter corresponding to the current value of the target counter among the first to fourteenth counters 143a to 143n for the second state in the second state area 143 of the history memory 117 is incremented by 1. For example, if the value of the target counter is "11", the eleventh counter 143k for the second state is incremented; if the value of the target counter is "5", the fifth counter 143e for the second state is incremented; and if the value of the target counter is "1", the first counter 143a for the second state is incremented.

Subsequently, by referring to the state information of the management RAM 114, it is determined whether or not the third state is in place, that is, whether or not the front door frame 14 is open (step S2210). If the third state is in place (step S2210: YES), the corresponding counter for the third state is incremented (step S2211). In this incrementing process, the value of the counter corresponding to the current value of the target counter among the first to fourteenth counters 144a to 144n for the third state in the third state area 144 of the history memory 117 is incremented by 1. For example, if the value of the target counter is "11", the eleventh counter 144k for the third state is incremented; if the value of the target counter is "5", the fifth counter 144e for the third state is incremented; and if the value of the target counter is "1", the first counter 144a for the third state is incremented.

If a negative result is obtained in step S2204, step S2210, or step S2211, the value of the verification target counter in the management RAM 114 is decremented by 1 (step S2212). Then, it is determined whether the value of the verification target counter after the decrement is "0" (step S2213). If the value of the verification target counter is 1 or greater (step S2213: NO), the processing from step S2202 onwards is executed for the verification target corresponding to the new value of the verification target counter.

As described above, the history setting process is executed, and the number of times game balls enter the out port 24a, general prize port 31, special electric prize device 32, first operation port 33, and second operation port 34, the number of times the opening/closing execution mode occurs, the number of times the high-frequency support mode occurs, and the number of game rounds occur are stored as count information, rather than as history information as in the first embodiment. This makes it possible to reduce the required storage capacity in the history memory 117 compared to a configuration where each piece of history information is stored individually.

Because the information is stored as count data rather than historical data, there is no need to derive count data from historical data when calculating various parameters. This reduces the processing load required to calculate various parameters.

Next, the configuration update recognition process in this embodiment, executed by the management CPU 112, will be explained with reference to the flowchart in Figure 41.

When the setting value update signal input to the 15th buffer 122o of input port 121 switches from a LOW level to a HI level (step S2301: YES), the value of the setting value recognition counter in the management-side RAM 114 is set to "1" (step S2302). The setting value recognition counter is a counter used by the management-side CPU 112 to identify the setting value of the pachinko machine 10. For example, a value of "1" in the setting value recognition counter means "setting 1," and a value of "6" means "setting 6."

Subsequently, it is determined whether the setting value update signal input to the 15th buffer 122o of input port 121 has switched back from the LOW level to the HI level (step S2303). If the determination in step S2303 is positive, the value of the setting value recognition counter in the management-side RAM 114 is incremented by 1 (step S2304). As a result, the setting value of the pachinko machine 10 identified by the management-side CPU 112 increases by one level.

If a negative result is obtained in step S2303, or if the process in step S2304 is executed, it is determined whether or not a setting value identification completion command has been received from the main CPU 63, based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2305). If a negative result is obtained in step S2305, the process returns to step S2303.

If a positive determination is made in step S2305, the total counter 141k, which measures the number of game rounds in the total area 141 of the history memory 117, the total counter 141h, which measures the number of times the opening/closing execution mode occurs in the total area 141 of the history memory 117, and the total counter 9, which measures the number of times the high-frequency support mode occurs in the total area 141 of the history memory 117 are all cleared to "0" (steps S2306 to S2308). As a result, the count information for the number of game rounds, the number of times the opening/closing execution mode occurs, and the number of times the high-frequency support mode occurs are cleared to "0" when a new setting is made in the settings state of the pachinko machine 10. Therefore, the calculation results of the 31st parameter, which indicates the number of occurrences of the opening/closing execution mode per unit game round; the 41st parameter, which indicates the number of occurrences of the high-frequency support mode per unit game round; and the 42nd parameter, which indicates the ratio of the number of occurrences of the high-frequency support mode to the number of occurrences of the opening/closing execution mode, correspond to the game content after a new setting has been made to the settings of the pachinko machine 10. In a configuration where the probability of winning a jackpot changes when the settings of the pachinko machine 10 are changed, by making the calculation results of the 31st, 41st, and 42nd parameters correspond to the game content after a new setting has been made to the settings of the pachinko machine 10, as described above, it becomes possible to determine whether the calculation results of the 31st, 41st, and 42nd parameters are appropriate based on the current settings.

On the other hand, even if the settings of the pachinko machine 10 are changed, the counters in the history memory 117 other than the eighth counter 141h, the ninth counter 141i, and the eleventh counter 141k for totals are not reset to "0". This allows the management of the number or frequency of game balls entered into each history target ball entry section to be performed based on long-term game history, without being affected by new settings of the pachinko machine 10.

According to the above configuration, the number of times game balls enter the out port 24a, general prize port 31, special electric prize device 32, first operation port 33, and second operation port 34, the number of times the opening/closing execution mode occurs, the number of times the high-frequency support mode occurs, and the number of game rounds occur are stored as count information, rather than as history information as in the first embodiment. This makes it possible to reduce the required storage capacity in the history memory 117 compared to a configuration where each piece of history information is stored individually.

Furthermore, because the data is stored as count information rather than historical information, there is no need to derive count information from historical information when calculating various parameters. This reduces the processing load required for calculating various parameters.

The count information for the number of game rounds, the number of times the open/close execution mode occurs, and the number of times the high-frequency support mode occurs is reset to "0" when the settings of the pachinko machine 10 are changed. Therefore, the calculation results of the 31st parameter, which indicates the number of times the open/close execution mode occurs per unit game round; the 41st parameter, which indicates the number of times the high-frequency support mode occurs per unit game round; and the 42nd parameter, which indicates the ratio of the number of times the high-frequency support mode occurs to the number of times the open/close execution mode occurs, correspond to the game content after the settings of the pachinko machine 10 are changed. In a configuration where the probability of winning a jackpot changes when the settings of the pachinko machine 10 are changed, by ensuring that the calculation results of the 31st, 41st, and 42nd parameters correspond to the game content after the settings of the pachinko machine 10 are changed, it becomes possible to determine whether the calculation results of the 31st, 41st, and 42nd parameters are appropriate based on the current settings.

On the other hand, even if the settings of the pachinko machine 10 are changed, the counters in the history memory 117 other than the eighth counter 141h, the ninth counter 141i, and the eleventh counter 141k for totals are not reset to "0". This allows the management of the number or frequency of game balls entered into each history target ball entry section to be performed based on long-term game history, without being affected by new settings of the pachinko machine 10.

Furthermore, the configuration of the history memory 117 as in this embodiment may be applied to the first to fifth embodiments described above, as well as to embodiments described after this embodiment. For example, when applied to the first embodiment, the information in the history memory 117 is maintained even if a new setting is made to the settings state of the pachinko machine 10. Also, when applied to the third embodiment, if a new setting is made to the settings state of the pachinko machine 10, the entire history memory 117 is cleared to "0".

Furthermore, the system may be configured such that when the settings of the pachinko machine 10 are changed, the settings update recognition process (Figure 41) executes steps S2306 to S2308. This ensures that even if a new setting is made for the pachinko machine 10, if the settings remain unchanged before and after the change, the information regarding the number of game rounds, the number of times the open/close execution mode occurred, and the number of times the high-frequency support mode occurred will not be cleared to "0". Conversely, if the settings of the pachinko machine 10 are changed, the information regarding the number of game rounds, the number of times the open/close execution mode occurred, and the number of times the high-frequency support mode occurred will be cleared to "0".

Furthermore, in the setting update recognition process (Figure 41), before the processing of steps S2306 to S2308 is executed, various parameters may be calculated using the counters 141 to 144 in the history memory 117, and these calculated parameters may be stored in the calculation result memory 131.

<Seventh Embodiment>
In this embodiment, the configuration of the history memory 117 differs from that of the first embodiment. The configuration that differs from that of the first embodiment will be described below. Configurations that are the same as those of the first embodiment will generally not be described.

Figure 42 is an explanatory diagram illustrating the configuration of the history memory 117 in this embodiment.

The history memory 117 is provided with history memories 181 to 186, each corresponding to one of the settings of the pachinko machine 10, from "Setting 1" to "Setting 6". Specifically, history memory 181 is provided for "Setting 1", history memory 182 is provided for "Setting 2", history memory 183 is provided for "Setting 3", history memory 184 is provided for "Setting 4", history memory 185 is provided for "Setting 5", and history memory 186 is provided for "Setting 6".

Each of the history memories 181 to 186 for settings 1 to 6 is provided with a combination of the history area 124 and pointer area 126 of the history memory 117 in the first embodiment described above. This makes it possible to store history information corresponding to each of the setting states of the pachinko machine 10, from "Setting 1" to "Setting 6". In this case, when a new setting state of the pachinko machine 10 is set, the history memories 181 to 186 corresponding to the newly set setting value become the target for storing history information. Therefore, it is possible to store history information separately for each setting value without erasing the history information when a new setting state of the pachinko machine 10 is set. Furthermore, since various parameters are calculated using the history information corresponding to the currently set setting state of the pachinko machine 10, it becomes possible to appropriately derive various parameters corresponding to each setting value.

Furthermore, the history memories 181 to 186 for settings 1 to 6 may be configured to contain combinations of the total area 141, the first state area 142, the second state area 143, and the third state area 144 as described in the sixth embodiment above.

Next, the configuration update recognition process in this embodiment, executed by the management CPU 112, will be explained with reference to the flowchart in Figure 43.

When the setting value update signal input to the 15th buffer 122o of input port 121 switches from a LOW level to a HI level (step S2401: YES), the value of the setting value recognition counter provided in the calculation result memory 131 is set to "1" (step S2402). The setting value recognition counter is a counter used by the management CPU 112 to identify the setting value of the pachinko machine 10. For example, if the value of the setting value recognition counter is "1", it means "setting 1", and if the value of the setting value recognition counter is "6", it means "setting 6". Furthermore, in this embodiment, since the setting value recognition counter is provided in the calculation result memory 131, which is a memory that does not require an external power supply for memory retention, the value stored in the setting value recognition counter is retained even if the power supply to the management IC 66 is stopped.

Subsequently, it is determined whether the setting value update signal input to the 15th buffer 122o of input port 121 has switched back from the LOW level to the HI level (step S2403). If the determination in step S2403 is positive, the value of the setting value recognition counter in the calculation result memory 131 is incremented by 1 (step S2404). As a result, the setting value of the pachinko machine 10 identified by the management CPU 112 increases by one level.

If a negative result is obtained in step S2403, or if the process in step S2404 is executed, it is determined whether or not a setting value identification completion command has been received from the main CPU 63, based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2405). If a negative result is obtained in step S2405, the process returns to step S2403.

If a positive determination is made in step S2405, the history memories 181 to 186 corresponding to the value of the setting value recognition counter in the calculation result memory 131 are set as the storage target for history information and the reference target when calculating various parameters (step S2406). Specifically, if the value of the setting value recognition counter is "1", it means that "Setting 1" has been set, so the history memory 181 for Setting 1 is set as the storage target for history information and the reference target when calculating various parameters. Also, if the value of the setting value recognition counter is "2", it means that "Setting 2" has been set, so the history memory 182 for Setting 2 is set as the storage target for history information and the reference target when calculating various parameters. Also, if the value of the setting value recognition counter is "3", it means that "Setting 3" has been set, so the history memory 183 for Setting 3 is set as the storage target for history information and the reference target when calculating various parameters. Furthermore, if the value of the setting value counter is "4," it means that "Setting 4" has been set, so the history memory 184 for Setting 4 is set as the target for storing history information and as the reference target when calculating various parameters. Similarly, if the value of the setting value counter is "5," it means that "Setting 5" has been set, so the history memory 185 for Setting 5 is set as the target for storing history information and as the reference target when calculating various parameters. Furthermore, if the value of the setting value counter is "6," it means that "Setting 6" has been set, so the history memory 186 for Setting 6 is set as the target for storing history information and as the reference target when calculating various parameters.

Subsequently, the RTC information, which consists of date and time information, is read from the RTC 115 (step S2407). Then, the write process to the history memory 117 is executed (step S2408). In this write process, the history memories 181 to 186, which were set as the target for storing history information in step S2406, are selected from the history memories 181 to 186 for settings 1 to 6. Then, by referring to the pointer area 126 in the history memories 181 to 186 that are the target for storage, the pointer information of the history area 124 that is currently being written to is identified, and the RTC information read in step S2407 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. In addition, information to identify that it is a setting value is written to the history information storage area 125 corresponding to the pointer information being written to. As a result, the combination of information indicating that the setting state of the pachinko machine 10 has been newly set and the RTC information corresponding to the date and time when the setting was made is stored as history information.

Subsequently, the update process for the target pointer is executed (step S2409). In this update process, the history memories 181-186, selected from the history memories 181-186 for settings 1-6 and set as the target for storing history information in step S2406, are selected. The numerical information stored in the pointer area 126 of these history memories 181-186 is read and incremented by 1. It is then determined whether the pointer information after the increment exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

According to the above configuration, history memories 181 to 186 are provided as history memories 117, corresponding to "Setting 1" to "Setting 6," respectively. This makes it possible to store game history corresponding to each of the setting states of the pachinko machine 10, from "Setting 1" to "Setting 6." In this case, when a new setting state of the pachinko machine 10 is set, the history memories 181 to 186 corresponding to the newly set setting value become the target for storing history information. Therefore, it is possible to store history information separately for each setting value without erasing the history information when a new setting state of the pachinko machine 10 is set. Furthermore, since various parameters are calculated using the history information corresponding to the currently set setting state of the pachinko machine 10, it becomes possible to appropriately derive various parameters corresponding to each setting value.

Furthermore, the configuration of the history memory 117 is not limited to having six history memories 181 to 186 for settings 1 to 6. It may also be configured so that a single memory contains areas corresponding to history memory 181 for setting 1, area corresponding to history memory 182 for setting 2, area corresponding to history memory 183 for setting 3, area corresponding to history memory 184 for setting 4, area corresponding to history memory 185 for setting 5, and area corresponding to history memory 186 for setting 6.

<Eighth Embodiment>
In this embodiment, the configuration of the history memory 117 differs from that of the first embodiment. The configuration that differs from that of the first embodiment will be described below. Configurations that are the same as those of the first embodiment will generally not be described.

Figure 44 is an explanatory diagram illustrating the configuration of the history memory 117 in this embodiment.

The history memory 117 is provided with a first history memory 191 and a second history memory 192. Each of the first and second history memories 191 is provided with the combination of the history area 124 and pointer area 126 of the history memory 117 in the first embodiment. In this case, if a new setting is made to the settings state of the pachinko machine 10 while history information is being stored using one of the history memories 191 or 192, the history information in the first history memory 191 or 192 can be retained without being erased until a predetermined number of history entries are stored in the other history memory 191 or 192. Furthermore, until a predetermined number of history entries are stored in the other history memory 191 or 192, new history information can be stored in both history memories 191 or 192.

Next, the configuration update recognition process in this embodiment, executed by the management CPU 112, will be explained with reference to the flowchart in Figure 45.

When the setting value update signal input to the 15th buffer 122o of input port 121 switches from a LOW level to a HI level (step S2501: YES), the value of the setting value recognition counter provided in the management-side RAM 114 is set to "1" (step S2502). The setting value recognition counter is a counter used by the management-side CPU 112 to identify the setting value of the pachinko machine 10. For example, a value of "1" in the setting value recognition counter means "setting 1," and a value of "6" means "setting 6."

Subsequently, it is determined whether the setting value update signal input to the 15th buffer 122o of input port 121 has switched back from the LOW level to the HI level (step S2503). If the determination in step S2503 is positive, the value of the setting value recognition counter in the management-side RAM 114 is incremented by 1 (step S2504). As a result, the setting value of the pachinko machine 10 identified by the management-side CPU 112 increases by one level.

If a negative result is obtained in step S2503, or if the process in step S2504 is executed, it is determined whether or not a setting value identification completion command has been received from the main CPU 63, based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2505). If a negative result is obtained in step S2505, the process returns to step S2503.

If a positive determination is made in step S2505, the setting change occurrence flag in the calculation result memory 131 is set to "1" (step S2506). The setting change occurrence flag is used by the management CPU 112 to determine whether, after a new setting of the pachinko machine 10's configuration is made, both the first and second history memories 191 and 192 (which were previously set as targets for storing history information) should now be used for storing history information. Furthermore, because the calculation result memory 131, which does not require external power supply for memory retention, has the setting change occurrence flag, the value stored in the setting change occurrence flag is retained even if the power supply to the management IC 66 is stopped.

Subsequently, the RTC information, which consists of date and time information, is read from the RTC 115 (step S2507). Then, the write process to the respective history memories 191 and 192 is executed (step S2508). In this write process, the pointer information of the history area 124 currently being written to is first identified by referring to the pointer area 126 of the first history memory 191, and the RTC information read in step S2507 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. In addition, both information to identify that it is a set value and information about the value of the set value recognition counter are written to the history information storage area 125 corresponding to the pointer information being written to. As a result, the combination of information indicating that the setting state of the pachinko machine 10 has been newly set, the RTC information corresponding to the date and time the setting was made, and the setting value information when the setting was made is stored in the first history memory 191 as history information. Furthermore, during this writing process, the pointer information of the history area 124 currently being written to is identified by referring to the pointer area 126 of the second history memory 192. The RTC information read in step S2507 is then written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. Additionally, information identifying that it is a set value and information about the value of the set value recognition counter are both written to the history information storage area 125 corresponding to the pointer information being written to. As a result, the combination of information indicating that the setting state of the pachinko machine 10 has been newly set, the RTC information corresponding to the date and time the setting was made, and the setting value information when the setting was made is stored as history information in the second history memory 192.

Subsequently, the update process for each target pointer is executed (step S2509). In this update process, first, the numerical information stored in the pointer area 126 of the first history memory 191 is read and incremented by 1. It is then determined whether the pointer information after the increment exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information. Furthermore, in this update process, the numerical information stored in the pointer area 126 of the second history memory 192 is read and incremented by 1. It is then determined whether the pointer information after the increment exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

Next, the history setting process in this embodiment, which is executed by the management CPU 112, will be explained with reference to the flowchart in Figure 46.

If the setting change occurrence flag for the calculation result memory 131 is not set to "1" (step S2601: NO), it means that the history information should only be stored in the memory designated for storage among the first history memory 191 and the second history memory 192. In this case, the currently designated history memories 191 and 192 are first identified (step S2602). The calculation result memory 131 is provided with a storage target flag. If the value of the storage target flag is "0", the first history memory 191 becomes the storage target; if the value of the storage target flag is "1", the second history memory 192 becomes the storage target. Since the storage target flag is provided in the calculation result memory 131, which does not require external power supply for storage, the value of the storage target flag is retained even if the power supply to the management IC 66 is stopped.

Subsequently, the history setting process is executed for the history memories 191 and 192 that are to be stored (step S2603). Specifically, steps S1101 to S1112 of the history setting process in the first embodiment (Figure 26) are executed for one of the history memories 191 and 192 that are to be stored. As a result, history information is stored in the history memory 191 and 192 that are to be stored.

On the other hand, if the setting change occurrence flag in the calculation result memory 131 is set to "1" (step S2601: YES), it means that history information should be stored not only in the first history memory 191 and the second history memory 192 that are being stored, but also in the other. In this case, the history setting execution process is performed for both history memories 191 and 192 (step S2604). Specifically, first, the processes of steps S1101 to S1112 of the history setting process in the first embodiment (Figure 26) are executed for the first history memory 191. As a result, history information is stored in the first history memory 191. After that, the processes of steps S1101 to S1112 of the history setting process in the first embodiment (Figure 26) are executed for the second history memory 192. As a result, history information is stored in the second history memory 192.

If the process in step S2603 or step S2604 is executed, it is determined whether the setting change occurrence flag in the calculation result memory 131 is set to "1" (step S2605). If the determination in step S2605 is positive, it is determined whether a predetermined number or more of ball discharge history exists in the non-storage history memories 191 and 192 (step S2606). Specifically, if the value of the storage target flag in the calculation result memory 131 is "0", the first history memory 191 is the storage target, so it is determined whether a predetermined number (specifically "1000") or more of history information indicating that game balls were discharged from the game area PA is stored in the second history memory 192. Furthermore, if the value of the storage target flag in the calculation result memory 131 is "1", the second history memory 192 is designated as the storage target. Therefore, it is determined whether a predetermined number (specifically, "1000") or more history information indicating that a game ball was ejected from the game area PA is stored in the first history memory 191. Alternatively, instead of determining whether a predetermined number (specifically, "1000") or more history information indicating that a game round was executed is stored, the system may determine whether a predetermined number (specifically, "100") or more history information indicating that a game round was executed is stored.

If a positive determination is made in step S2606, the process of changing the memory target is executed (step S2607). In the process of changing the memory target, the memory target of the first history memory 191 and the second history memory 192 is changed by setting the value of the memory target flag in the calculation result memory 131 to a value different from the current value between two values. Specifically, if the value of the memory target flag is "0", the memory target flag is set to "1", changing the memory target from the first history memory 191 to the second history memory 192. Also, if the value of the memory target flag is "1", the memory target flag is cleared to "0", changing the memory target from the second history memory 192 to the first history memory 191. As a result, the history memories 191 and 192, which store only the history information from games played after a new setting of the pachinko machine 10's settings state has been made, are set as the memory targets. Furthermore, by using the history information from the newly added history memories 191 and 192 to be stored, various parameters can be calculated, making it possible to derive various parameters based on gameplay performed after a new setting of the pachinko machine 10's configuration state has been made.

Subsequently, the clearing process is performed on the memory that was previously being stored, either the first history memory 191 or the second history memory 192 (step S2608). Specifically, if the value of the storage target flag is "0", the second history memory 192 is cleared to "0", and if the value of the storage target flag is "1", the first history memory 191 is cleared to "0". Then, the setting change occurrence flag in the calculation result memory 131 is cleared to "0" (step S2609).

Next, the display output processing in this embodiment, which is executed by the management CPU 112, will be explained with reference to the flowchart in Figure 47.

If it is the calculation timing (step S2701: YES), the device identifies which of the first history memory 191 and the second history memory 192 is the target for storage (step S2702). Specifically, if the value of the storage target flag in the calculation result memory 131 is "0", the first history memory 191 is identified as the storage target, and if the value of the storage target flag is "1", the second history memory 192 is identified as the storage target. Then, using the history information stored in the history memories 191 and 192 identified as the storage targets in step S2702, steps S1402 to S1412 of the display output processing in the first embodiment (Figure 30) are executed to calculate various parameters (1st to 8th parameters, 11th to 18th parameters, 21st to 26th parameters, 31st parameter, 41st to 42nd parameters), and these calculated parameters are stored in the calculation result memory 131 (step S2703). In this case, even if the setting change occurrence flag in the calculation result memory 131 is set to "1," resulting in history information being stored in both the first history memory 191 and the second history memory 192, various parameters will be calculated using only one of the history memories 191 or 192 that is being stored.

If a negative result is obtained in step S2701, or if the process in step S2703 is executed, the display process is executed (step S2704). The content of the display process is the same as the display process in the first embodiment described above (Figure 31).

According to the above configuration, the history memory 117 is provided with a first history memory 191 and a second history memory 192. When a new setting is made to the settings state of the pachinko machine 10, the history memories 191 and 192 that were previously used for storage remain as storage memories, while history information is also stored in the other history memory 191 and 192 that were not previously used for storage. When a predetermined number of history information corresponding to the ejection of game balls from the game area PA is stored in the other history memory 191 and 192, the other history memory 191 and 192 become storage memories, and the previously used history memory 191 and 192 are cleared to "0". This makes it possible to calculate various parameters using only the history information of games played with the newly set settings state of the pachinko machine 10.

On the other hand, with the above configuration, even if the settings of the pachinko machine 10 are repeatedly changed in a short period of time to prevent the proper calculation of various parameters, the history memories 191 and 192, which are stored, remain unchanged. This makes it possible to properly derive the management results of the game history up to that point, even if the settings of the pachinko machine 10 are repeatedly changed in a short period of time.

Furthermore, the configuration of the history memory 117 is not limited to having two memories, a first history memory 191 and a second history memory 192. A configuration in which a first history area corresponding to the first history memory 191 and a second history area corresponding to the second history memory 192 are set within a single memory is also possible.

Alternatively, the system may be configured with only one history memory 117. In this case, when the total number of game balls dispensed from the game area PA exceeds a predetermined number after a new setting of the pachinko machine 10's settings is made, the history information prior to the timing of the new setting of the pachinko machine 10's settings is erased, while the history information after the timing of the setting is retained without being erased. This makes it possible to erase history information prior to the timing of the new setting of the pachinko machine 10's settings when a predetermined number of history information entries have been accumulated since the new setting of the pachinko machine 10's settings was made. Furthermore, by storing the corresponding history information in the history memory 117 at the time of the new setting of the pachinko machine 10's settings, it becomes possible to distinguish between history information before and after the timing of the new setting in the history memory 117.

Furthermore, the timing for erasing the history information is not limited to when the total number of game balls dispensed from the game area PA exceeds a predetermined number after a new setting of the pachinko machine 10's settings has been made. It may also be when the number of game rounds played since a new setting of the pachinko machine 10's settings has been made exceeds a predetermined number.

Furthermore, even if a new setting is made to the pachinko machine 10, if the setting value has not changed before or after the setting change, the above-described changes to the history memories 191 and 192 and the deletion of history information may be avoided. Conversely, if a new setting is made to the pachinko machine 10 and the setting value has changed before or after the setting change, the above-described changes to the history memories 191 and 192 and the deletion of history information may be performed.

<Ninth Embodiment>
In this embodiment, the type of buffer among the first to sixteenth buffers 122a to 122p of the input port 121 of the management I/F 111, in which the type of input signal is determined at the design stage of the management IC 66, differs from that of the first embodiment. Also, the processing configuration executed by the main CPU 63 to specify the type of input signal to the management CPU 112 differs from that of the first embodiment. The configurations that differ from those of the first embodiment will be described below. Configurations that are the same as those of the first embodiment will generally not be described.

Figure 48 is an explanatory diagram illustrating the configuration of the input port 121 of the management interface 111 in this embodiment.

The first to seventh buffers 122a to 122g and the sixteenth buffer 122p are input to the same type of signal as in the first embodiment described above. In detail, the first buffer 122a receives a first signal corresponding to the detection result of the first prize-winning slot detection sensor 42a, the second buffer 122b receives a second signal corresponding to the detection result of the second prize-winning slot detection sensor 43a, the third buffer 122c receives a third signal corresponding to the detection result of the third prize-winning slot detection sensor 44a, the fourth buffer 122d receives a fourth signal corresponding to the detection result of the special electric detection sensor 45a, the fifth buffer 122e receives a fifth signal corresponding to the detection result of the first operation slot detection sensor 46a, the sixth buffer 122f receives a sixth signal corresponding to the detection result of the second operation slot detection sensor 47a, the seventh buffer 122g receives a seventh signal corresponding to the detection result of the output slot detection sensor 48a, and the sixteenth buffer 122p receives an output instruction signal.

On the other hand, in the first embodiment described above, a signal corresponding to the opening/closing execution mode is input to the eighth buffer 122h as the eighth signal, a signal corresponding to the high-frequency support mode is input to the ninth buffer 122i as the ninth signal, a signal corresponding to the front door frame 14 is input to the tenth buffer 122j as the tenth signal, a signal corresponding to the start of a game round is input to the eleventh buffer 122k as the eleventh signal, and a setting value update signal is input to the fifteenth buffer 122o. However, in this embodiment, the buffers to which these signals are input are different. Specifically, the signal corresponding to the start of a game round is input to the 11th buffer 122k as a game round signal, the setting value update signal is input to the 12th buffer 122l, the signal corresponding to the opening/closing execution mode is input to the 13th buffer 122m as an opening/closing execution mode signal, the signal corresponding to the high-frequency support mode is input to the 14th buffer 122n as a high-frequency support mode signal, and the signal corresponding to the front door frame 14 is input to the 15th buffer 122o as a door open signal.

The fact that a game round signal is input to the 11th buffer 122k, a setting value update signal is input to the 12th buffer 122l, an open/close execution mode signal is input to the 13th buffer 122m, a high-frequency support mode signal is input to the 14th buffer 122n, a door open signal is input to the 15th buffer 122o, and an output instruction signal is input to the 16th buffer 122p is determined during the design phase of the management IC 66. Without receiving instructions from the main CPU 63, the management CPU 112 can determine that the above signals corresponding to the 11th to 16th buffers 122k to 122p are input to each of these buffers. On the other hand, the types of signals that are input to the 1st to 10th buffers 122a to 122j are not determined during the design phase of the management IC 66, and the types of these signals are determined by the management CPU 112 upon receiving instructions from the main CPU 63. The process for identifying the type of this signal is executed when power is supplied to the main CPU 63 and the management CPU 112, similar to the first embodiment described above.

Figure 49 is a flowchart showing the recognition process of this embodiment, which is executed by the main CPU 63. The recognition process is executed in step S111 of the main process (Figure 9), similar to the first embodiment described above.

First, the recognition output counter of the main RAM 65 is set to "10," which is the number of the first to tenth buffers 122a to 122j that are the targets for signal type recognition (step S2801). Then, the output processing for the identification start signal is executed (step S2802). In this output processing, the output state of the first signal input to the first buffer 122a, the open/close execution mode signal input to the thirteenth buffer 122m, and the high-frequency support mode signal input to the fourteenth buffer 122n are set to HI level, thereby initiating the output of the identification start signal. The period for maintaining these signals at HI level is set to a sufficient period for the management CPU 112 to recognize the output state of these signals.

Subsequently, the output count information corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64, and this read output count information is set in the output count counter provided in the main RAM 65 (step S2803). The output count counter is a counter used by the main CPU 63 to identify the number of outputs of the type identification signal.

In this embodiment, when the management CPU 112 is made to recognize the type of signal input to the first buffer 122a to the tenth buffer 122j, it outputs a type identification signal the same number of times as the number of prize balls set for the ball entry unit corresponding to that signal type. The management CPU 112 stores information corresponding to the number of times the type identification signal has been received for each of the first buffers 122a to the tenth buffer 122j in the first to tenth correspondence areas 123a to 123j of the correspondence memory 116. In other words, the type of signal input to the first buffer 122a to the tenth buffer 122j is understood as the number of prize balls set for the ball entry unit corresponding to that signal type.

In step S2803, if the value of the recognition output counter is "10", "9", or "8", the output count counter is set to "10", which corresponds to the number of prize balls awarded by the general prize slot 31. If the value of the recognition output counter is "7", the output count counter is set to "15", which corresponds to the number of prize balls awarded by the special electric prize device 32. If the value of the recognition output counter is "6", the output count counter is set to "1", which corresponds to the number of prize balls awarded by the first operation slot 33. If the value of the recognition output counter is "5", the output count counter is set to "1", which corresponds to the number of prize balls awarded by the second operation slot 34. If the value of the recognition output counter is "4", although it corresponds to the out slot 24a, the game balls will not be dispensed even if a game ball enters the out slot 24a, so the output count counter is set to "0". Furthermore, if the value of the recognition output counter is any of "3" to "1", it means that there is no corresponding ball entry point and it is blank, so the output count counter is set to "0".

Subsequently, the output processing of the start trigger signal is performed (step S2804). In this output processing, the output state of the first signal input to the first buffer 122a is set to a HI level, thereby initiating the output of the start trigger signal. The period for maintaining the first signal at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the first signal.

Subsequently, provided that the output count counter value in the main RAM 65 is not "0" (step S2805: YES), that is, provided that a value of 1 or greater was set in the output count counter in step S2803, the process proceeds to step S2806. In step S2806, the output processing for the type identification signal is executed. In this output processing, the output state of the second signal input to the second buffer 122b is set to a HI level, thereby initiating the output of the type identification signal. The period for maintaining the second signal at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the second signal.

Subsequently, the value of the output count counter in the main RAM 65 is decremented by 1 (step S2807), and it is determined whether the value of the output count counter after the decrement is "0" (step S2808). If the value of the output count counter is 1 or greater (step S2808: NO), the process returns to step S2806.

If a positive determination is made in step S2805, or in step S2808, the termination signal output process is executed (step S2809). In this output process, the output state of the third signal input to the third buffer 122c is set to a HI level, thereby initiating the output of the termination signal. The period for maintaining the third signal at a HI level is set to a sufficient period for the management CPU 112 to recognize the output state of the third signal.

Subsequently, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S2810), and it is determined whether the value of the recognition output counter after the decrement is "0" (step S2811). If the value of the recognition output counter is 1 or greater (step S2811: NO), the process returns to step S2803, and the process for recognizing the type of signal corresponding to the value of the recognition output counter after the decrement is executed.

On the other hand, if the value of the recognition output counter is "0" (step S2811: YES), the output processing of the identification completion signal is executed (step S2812). In this output processing, the output state of the third signal input to the third buffer 122c, the open/close execution mode signal input to the thirteenth buffer 122m, and the high-frequency support mode signal input to the fourteenth buffer 122n are set to HI level, thereby initiating the output of the identification completion signal. The period for which these signals are maintained at HI level is set to a period sufficient for the management CPU 112 to recognize the output state of these signals.

Next, the management process in this embodiment, which is executed by the management CPU 112, will be explained with reference to the flowchart in Figure 50. The management process begins when the supply of operating power to the management CPU 112 is initiated, similar to the first embodiment described above.

First, it is determined whether or not the reception of the identification start signal from the main CPU 63 has finished (step S2901). If the identification start signal has not been received, the setting update recognition process is executed in step S2902, and then the process in step S2901 is executed again. The processing content of the setting update recognition process is the same as in the first embodiment described above.

If the reception of the identification start signal from the main CPU 63 is complete (step S2901: YES), the value of the setting target counter in the management RAM 114 is cleared to "0" (step S2903). Then, assuming that the start trigger signal has been received from the main CPU 63 (step S2904: YES), the process proceeds to step S2905. In step S2905, it is determined whether or not a type identification signal has been received from the main CPU 63. If a type identification signal has been received (step S2905: YES), the value of the reception count counter in the management RAM 114 is incremented by 1 (step S2906). The reception count counter is used by the management CPU 112 to determine the number of times the type identification signal has been received from the main CPU 63. Note that the value of the reception count counter is cleared to "0" if a positive determination is made in step S2904.

If a negative determination is made in step S2905, or if the process in step S2906 is executed, it is determined whether or not a termination trigger signal has been received from the main CPU 63 (step S2907). If a termination trigger signal has not been received (step S2907: NO), the process returns to step S2905. If a termination trigger signal has been received (step S2907: YES), the correspondence relationship setting process is executed (step S2908). In the correspondence relationship setting process, the value set in the reception count counter is stored in the correspondence relationship area corresponding to the current value of the setting target counter in the management RAM 114, among the first to tenth correspondence relationship areas 123a to 123j of the correspondence relationship memory 116. In this case, the first correspondence area 123a, the second correspondence area 123b, and the third correspondence area 123c are set to "10," corresponding to the number of prize balls awarded by the general prize slot 31; the fourth correspondence area 123d is set to "15," corresponding to the number of prize balls awarded by the special electric prize device 32; the fifth correspondence area 123e is set to "1," corresponding to the number of prize balls awarded by the first operation slot 33; and the sixth correspondence area 123f is set to "1," corresponding to the number of prize balls awarded by the second operation slot 34. Furthermore, the seventh to twelfth correspondence areas 123g to 123l are set to "0." Afterward, the value of the setting target counter in the management-side RAM 114 is incremented by 1 (step S2909).

If a negative result is obtained in step S2904, or if the process in step S2909 is executed, it is determined whether the reception of the identification completion signal from the main CPU 63 has finished (step S2910). If the reception of the identification completion signal has not finished (step S2910: NO), the process returns to step S2904, and if the start trigger signal is received from the main CPU 63 (step S2904: YES), the processes from step S2905 onwards are executed. If the reception of the identification completion signal from the main CPU 63 has finished (step S2910: YES), the history setting process in step S2911, the display output process in step S2912, and the external output process in step S2913 are repeatedly executed.

Figure 51 is a time chart showing how information regarding the correspondence between the first to tenth buffers 122a to 122j and the types of signals input to these buffers 122a to 122j is stored in the correspondence memory 116. Figure 51(a) shows the period during which the output state of the first signal is at a HI level, Figure 51(b) shows the period during which the output state of the second signal is at a HI level, Figure 51(c) shows the period during which the output state of the third signal is at a HI level, Figure 51(d) shows the period during which the output state of the signal during the opening/closing execution mode is at a HI level, Figure 51(e) shows the period during which the output state of the signal during the high-frequency support mode is at a HI level, Figure 51(f) shows the execution period of the identification state during which processing is performed to identify the correspondence between the first to tenth buffers 122a to 122j and the types of signals input to these buffers 122a to 122j, Figure 51(g) shows the timing when the value of the reception count counter in the management side RAM 114 is incremented by 1, and Figure 51(h) shows the timing when the correspondence setting processing (step S2908) is executed in the management side CPU 112.

When power is supplied to the main CPU 63 and the management CPU 112, at timing t1, the output states of the first signal, the switching execution mode signal, and the high-frequency support mode signal are changed from LOW to HI levels, as shown in Figures 51(a), 51(d), and 51(e). This initiates the output of the identification start signal from the main CPU 63 to the management CPU 112. Then, at timing t2, the output states of the first signal, the switching execution mode signal, and the high-frequency support mode signal are changed from HI to LOW levels. This stops the output of the identification start signal from the main CPU 63 to the management CPU 112. At timing t2, the management CPU 112 makes an affirmative determination in step S2901 of the management process (Figure 50), resulting in the identification state as shown in Figure 51(f).

Subsequently, from timing t3 to t4, the output state of the first signal is maintained at a HI level, as shown in Figure 51(a). This results in the management CPU 112 receiving the start trigger signal. Then, from timing t5 to t7, the output state of the second signal is maintained at a HI level, as shown in Figure 51(b). This results in the management CPU 112 receiving the type identification signal once. In this case, at timing t6, the value of the reception count counter in the management RAM 114 is incremented by 1, as shown in Figure 51(g).

Subsequently, from timing t8 to t10, the output state of the third signal is maintained at a HI level, as shown in Figure 51(c). This results in the termination signal being output to the management CPU 112. In this case, at timing t9, the management CPU 112 executes the correspondence relationship setting process, as shown in Figure 51(h). Since the reception count counter value is "1" at the time this correspondence relationship setting process is executed, the information "1" is stored as correspondence relationship information in the correspondence relationship areas 123a to 123j of the correspondence relationship memory 116 that are the target of this setting.

Subsequently, from timing t11 to t12, the output state of the first signal is maintained at a HI level, as shown in Figure 51(a). This results in the start trigger signal being output to the management CPU 112. Then, from timing t13 to t15, t16 to t18, t19 to t21, and t22 to t24, the output state of the second signal is maintained at a HI level, as shown in Figure 51(b). This results in the type identification signal being output once to the management CPU 112. In this case, at timings t14, t17, t20, and t23, the value of the reception count counter in the management RAM 114 is incremented by 1, as shown in Figure 51(g).

Subsequently, from timing t25 to t27, the output state of the third signal is maintained at a HI level, as shown in Figure 51(c). This results in the termination signal being output to the management CPU 112. In this case, at timing t26, the management CPU 112 executes the correspondence relationship setting process, as shown in Figure 51(h). Since the reception count counter value is "10" at the time this correspondence relationship setting process is executed, the information "10" is stored as correspondence relationship information in the correspondence relationship areas 123a to 123j of the correspondence relationship memory 116 that are the target of this setting.

Subsequently, at timing t28, as shown in Figures 51(c), 51(d), and 51(e), the output state of the third signal, the switch/open/close execution mode signal, and the high-frequency support mode signal is changed from LOW level to HI level. This initiates the output of the identification completion signal from the main CPU 63 to the management CPU 112. Then, at timing t29, the output state of the third signal, the switch/open/close execution mode signal, and the high-frequency support mode signal is changed from HI level to LOW level. This stops the output of the identification completion signal from the main CPU 63 to the management CPU 112. At timing t29, the management CPU 112 makes an affirmative judgment in step S2910 of the management process (Figure 50), and the identification state is released as shown in Figure 51(f).

In this embodiment, since the number of prize balls is stored as correspondence information, the history information stored in the history memory 117 includes the number of prize balls corresponding to the ball entry point that triggered the storage of that history information as correspondence information. In this configuration, if there are multiple types of ball entry points with the same number of prize balls, it is not possible to distinguish between them in the history information. Specifically, since both the first operation port 33 and the second operation port 34 have a prize ball count of 1, it is not possible to distinguish between the first operation port 33 and the second operation port 34 in the history information. In this case, the number of prize balls for the first operation port 33 and the second operation port 34 may be made different. This makes it possible to distinguish between the first operation port 33 and the second operation port 34 in the history information, even in a configuration where history information is stored as in this embodiment.

As described in detail above, according to this embodiment, not only the setting value update signal and output instruction signal, but also information corresponding to whether a game round has started, whether the system is in opening/closing execution mode, whether the system is in high-frequency support mode, and whether the front door frame 14 is open can be identified by the management CPU 112 without receiving correspondence relationship information from the main CPU 63. In this case, only the information corresponding to the detection results of each ball entry detection sensor 42a to 48a is information that requires the main CPU 63 to recognize the correspondence relationship between each piece of information and each signal path 118a to 118j from the management CPU 112. When the management CPU 112 recognizes the correspondence relationship information, the same number of pulse signals as the number of prize balls corresponding to each ball entry detection sensor 42a to 48a are output from the main CPU 63 to the management CPU 112 using the second signal. This simplifies the configuration for transmitting correspondence relationship information.

<Tenth Embodiment>
In this embodiment, the configuration for providing information on each ball entry result to the management IC 66 differs from that of the first embodiment. The configuration that differs from that of the first embodiment will be described below. Configurations that are the same as those in the first embodiment will generally not be described.

Figure 52 is an explanatory diagram illustrating the configuration of the signal path so that the detection results from each ball entry detection sensor 42a to 48a are input to the main CPU 63 and the management IC 66.

The detection result of the first prize-winning slot detection sensor 42a is input to the main CPU 63 via the first signal path SL11. The detection result of the second prize-winning slot detection sensor 43a is input to the main CPU 63 via the second signal path SL12. The detection result of the third prize-winning slot detection sensor 44a is input to the main CPU 63 via the third signal path SL13. The detection result of the special electric detection sensor 45a is input to the main CPU 63 via the fourth signal path SL14. The detection result of the first operation slot detection sensor 46a is input to the main CPU 63 via the fifth signal path SL15. The detection result of the second operation slot detection sensor 47a is input to the main CPU 63 via the sixth signal path SL16. The detection result of the output slot detection sensor 48a is input to the main CPU 63 via the seventh signal path SL17.

A first branch path SL21 is formed by branching off from an intermediate position in the first signal path SL11, and this first branch path SL21 is electrically connected to the management IC 66. A second branch path SL22 is formed by branching off from an intermediate position in the second signal path SL12, and this second branch path SL22 is electrically connected to the management IC 66. A third branch path SL23 is formed by branching off from an intermediate position in the third signal path SL13, and this third branch path SL23 is electrically connected to the management IC 66. A fourth branch path SL24 is formed by branching off from an intermediate position in the fourth signal path SL14, and this fourth branch path SL24 is electrically connected to the management IC 66. A fifth branch path SL25 is formed by branching off from an intermediate position in the fifth signal path SL15, and this fifth branch path SL25 is electrically connected to the management IC 66. Furthermore, a sixth branch path SL26 is formed by branching off from an intermediate point in the sixth signal path SL16, and this sixth branch path SL26 is electrically connected to the management IC 66. Also, a seventh branch path SL27 is formed by branching off from an intermediate point in the seventh signal path SL17, and this seventh branch path SL27 is electrically connected to the management IC 66.

With the above configuration, the detection results from each ball entry detection sensor 42a to 48a are input to the management IC 66 without the need for processing by the main CPU 63. This eliminates the need for the main CPU 63 to perform processing to allow the management CPU 112 to recognize the ball entry results from the out gate 24a, general prize gate 31, special electric prize device 32, first operation gate 33, and second operation gate 34, thereby reducing the processing load on the main CPU 63.

Furthermore, the branching points from each signal path SL11 to SL17 to each branch path SL21 to SL27 are located within the MPU 62. This makes it difficult to access these branching points and each branch path SL21 to SL27 from the outside, thus preventing fraudulent activity such as inputting abnormal ball entry results only into the management IC 66.

<11th Invention>
In this embodiment, the configuration of the display device for displaying the management results of the game history differs from that of the first embodiment. The configuration that differs from that of the first embodiment will be described below. Configurations that are the same as those of the first embodiment will generally not be described.

Figure 53 is a front view of the main control device 60 in this embodiment.

In the first embodiment described above, the main control device 60 was equipped with a first notification display device 69a, a second notification display device 69b, and a third notification display device 69c. However, in this embodiment, a first notification display device 201, a second notification display device 202, a third notification display device 203, and a fourth notification display device 204 are provided. These first to fourth notification display devices 201 to 204 are arranged side-by-side on the element mounting surface of the main control board 61.

The first to fourth notification display devices 201 to 204 are all segment displays with seven LED display segments arranged in a row, but are not limited to this; they may also be single multi-color light-emitting devices, liquid crystal displays, or organic EL displays. The first to fourth notification display devices 201 to 204 are all installed so that their display surfaces face the direction toward the element mounting surface of the main control board 61, and are covered by the opposing wall portion 60b of the board box 60a. In this case, because the board box 60a is made transparent, it is possible to visually inspect the display surfaces of the first to fourth notification display devices 201 to 204 housed inside the board box 60a from outside the board box 60a. Furthermore, since the main control device 60 is mounted on the back of the resin base 21 in the circuit board box 60a such that the opposing wall portion 60b facing the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10, when the game machine body 12 is opened in front of the pachinko machine 10 relative to the outer frame 11, and the back of the resin base 21 is exposed to the front of the pachinko machine 10, the display surfaces of the first to fourth notification display devices 201 to 204 can be visually inspected through the opposing wall portion 60b.

The display surface of the first notification display device 201 shows letters such as "A," "E," "H," "L," and "O." Meanwhile, the second notification display device 202, the third notification display device 203, and the fourth notification display device 204 display numbers in the range of "0" to "9." The results of game history management are reported using the first to fourth notification display devices 201 to 204. In this case, the first notification display device 201 and the second notification display device 202 display information corresponding to the type of game history management result being reported (parameters 1 to 8, 11 to 18, 21 to 26, 31, and 41 to 42 in the first embodiment described above), while the third notification display device 203 and the fourth notification display device 204 display information corresponding to the content of the game history management result of the type being reported.

In detail, the types of game history management results include the first to eighth parameters, eleventh to eighteen parameters, twenty-first to twenty-sixth parameters, thirty-first parameters, and forty-first to forty-second parameters in the first embodiment described above. The first notification display device 201 displays information corresponding to the type of parameter group being notified. Specifically, if any of the first to eighth parameters are being notified, "A" is displayed on the first notification display device 201; if any of the eleventh to eighth parameters are being notified, "E" is displayed; if any of the twenty-first to twenty-six parameters are being notified, "H" is displayed; if any of the thirty-first parameters are being notified, "L" is displayed; and if any of the forty-first to forty-second parameters are being notified, "O" is displayed.

The second notification display device 202 displays the order of the game history management results in the parameter group that is the subject of notification, in a sequence that corresponds to the type of game history management result that is the subject of notification. To explain using the parameter groups from the 1st to the 8th parameters as an example, if the 1st parameter is the target of notification, "1" will be displayed on the 2nd notification display device 202; if the 2nd parameter is the target of notification, "2" will be displayed on the 2nd notification display device 202; if the 3rd parameter is the target of notification, "3" will be displayed on the 2nd notification display device 202; if the 4th parameter is the target of notification, "4" will be displayed on the 2nd notification display device 202; if the 5th parameter is the target of notification, "5" will be displayed on the 2nd notification display device 202; if the 6th parameter is the target of notification, "6" will be displayed on the 2nd notification display device 202; if the 7th parameter is the target of notification, "7" will be displayed on the 2nd notification display device 202; and if the 8th parameter is the target of notification, "8" will be displayed on the 2nd notification display device 202. Furthermore, using the parameter groups 21 through 26 as an example, if parameter 21 is the target of notification, "1" will be displayed on the second notification display device 202; if parameter 22 is the target of notification, "2" will be displayed on the second notification display device 202; if parameter 23 is the target of notification, "3" will be displayed on the second notification display device 202; if parameter 24 is the target of notification, "4" will be displayed on the second notification display device 202; if parameter 25 is the target of notification, "5" will be displayed on the second notification display device 202; and if parameter 26 is the target of notification, "6" will be displayed on the second notification display device 202.

Regarding the display contents of the third notification display device 203 and the fourth notification display device 204, the third notification display device 203 displays the digit corresponding to the tens place of the value obtained by multiplying the parameter being notified by 100, and the fourth notification display device 204 displays the digit corresponding to the units place.

In the first to fourth notification display devices 201 to 204, the displays corresponding to the calculation results of the first to eighth parameters, the eleventh to eighteen parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the fortieth to fortieth parameters are sequentially switched according to a predetermined order. After the calculation result of the fortieth parameter, which is the last parameter to be displayed, is shown, the calculation result of the first parameter, which is the first parameter to be displayed, is displayed. In this case, the period during which the calculation result of one parameter is continuously displayed is two seconds. In contrast, the calculation cycle for the various parameters in the management CPU 112 is 51 seconds, and the number of various parameters is 25. Therefore, the various parameters calculated by the management CPU 112 are subject to notification at least once in the first to fourth notification display devices 201 to 202.

In the first to fourth notification display devices 201 to 204, similar to the first embodiment described above, not only are the results of the game history management notified, but in the changeable state in which the settings of the pachinko machine 10 can be changed, a value corresponding to the current setting is displayed. Specifically, in the changeable state, the first to third notification display devices 201 to 203 are turned off, while the fourth notification display device 204, located on the far right of the horizontally arranged first to fourth notification display devices 204, displays a value corresponding to the current setting. In other words, when "Setting 1" is selected in the changeable state, "1" is displayed on the fourth notification display device 204; when "Setting 2" is selected in the changeable state, "2" is displayed on the fourth notification display device 204; when "Setting 3" is selected in the changeable state, "3" is displayed on the fourth notification display device 204; when "Setting 4" is selected in the changeable state, "4" is displayed on the fourth notification display device 204; when "Setting 5" is selected in the changeable state, "5" is displayed on the fourth notification display device 204; and when "Setting 6" is selected in the changeable state, "6" is displayed on the fourth notification display device 204.

Next, the electrical configuration for displaying various information in the first to fourth notification display devices 201 to 204 based on the control of the MPU 62 will be described. Figure 54 is a block diagram illustrating the electrical configuration for displaying various information in the first to fourth notification display devices 201 to 204 based on the control of the MPU 62.

As already explained, the main control board 61 is equipped with an MPU 62 and first to fourth notification display devices 201 to 204. Furthermore, the main control board 61 is equipped with a first display IC 205, a second display IC 206, a third display IC 207, and a fourth display IC 208.

The first display IC 205 is provided in correspondence with the first notification display device 201 and is electrically connected to the MPU 62 by signal path SL31 and to the first notification display device 201 by signal path SL32. The first display IC 205 is provided with a storage buffer for storing display data received from the MPU 62, and controls the display of the first notification display device 201, that is, controls the illumination of each display segment, according to the display data stored in the storage buffer. When operating power is supplied to the first display IC 205, it can store and retain the display data stored in the storage buffer, and continuously displays the display content corresponding to the stored display data on the first notification display device 201. When the display data is changed by the MPU 62, the display on the first notification display device 201 is changed to the display content corresponding to the changed display data. Furthermore, in situations where power supply to the first display IC 205 has started but the display data has not yet been set by the MPU 62, the display data will be all "0". In this case, the first notification display device 201 will be in a non-display state, i.e., off state.

However, the configuration is not limited to this example. The first display IC 205 may be configured to store and retain display data even when the power supply to the pachinko machine 10 is stopped, by supplying backup power to the first display IC 205. In this case, when the power supply to the pachinko machine 10 is resumed, the display that was being shown on the first notification display device 201 immediately before the power supply to the pachinko machine 10 was stopped will be resumed on the first notification display device 201.

The second display IC 206 is provided in correspondence with the second notification display device 202, and is electrically connected to the MPU 62 by signal path SL33 and also electrically connected to the second notification display device 202 by signal path SL34. The second display IC 206 is provided with a storage buffer for storing display data received from the MPU 62, and controls the display of the second notification display device 202, that is, controls the illumination of each display segment, according to the display data stored in the storage buffer. When operating power is supplied to the second display IC 206, it can store and retain the display data stored in the storage buffer, and continuously displays the display content corresponding to the stored display data on the second notification display device 202. When the display data is changed by the MPU 62, the display on the second notification display device 202 is changed to the display content corresponding to the changed display data. Furthermore, in situations where power supply to the second display IC 206 has started but the display data has not yet been set by the MPU 62, the display data will be all "0". In this case, the second notification display device 202 will be in a non-display state, i.e., off state.

However, the configuration is not limited to this example. Backup power may be supplied to the second display IC 206, allowing the second display IC 206 to store and retain display data even when the power supply to the pachinko machine 10 is stopped. In this case, when the power supply to the pachinko machine 10 is resumed, the display that was being shown on the second notification display device 202 immediately before the power supply to the pachinko machine 10 was stopped will be resumed on the second notification display device 202.

The third display IC 207 is provided in correspondence with the third notification display device 203, and is electrically connected to the MPU 62 by signal path SL35 and to the third notification display device 203 by signal path SL36. The third display IC 207 is provided with a storage buffer for storing display data received from the MPU 62, and controls the display of the third notification display device 203, that is, controls the illumination of each display segment, according to the display data stored in the storage buffer. When operating power is supplied to the third display IC 207, it can store and retain the display data stored in the storage buffer, and continuously displays the display content corresponding to the stored display data on the third notification display device 203. When the display data is changed by the MPU 62, the display on the third notification display device 203 is changed to the display content corresponding to the changed display data. Furthermore, in situations where power supply to the third display IC 207 has started but the MPU 62 has not yet set the display data, the display data will be all "0". In this case, the third notification display device 203 will be in a non-display state, i.e., off state.

However, the configuration is not limited to this example. Backup power may be supplied to the third display IC 207, allowing the third display IC 207 to store and retain display data even when the power supply to the pachinko machine 10 is stopped. In this case, when the power supply to the pachinko machine 10 is resumed, the display that was being shown on the third notification display device 203 immediately before the power supply to the pachinko machine 10 was stopped will be resumed on the third notification display device 203.

The fourth display IC 208 is provided in correspondence with the fourth notification display device 204, and is electrically connected to the MPU 62 by signal path SL37 and to the fourth notification display device 204 by signal path SL38. The fourth display IC 208 is provided with a storage buffer for storing display data received from the MPU 62, and controls the display of the fourth notification display device 204, that is, controls the illumination of each display segment, according to the display data stored in the storage buffer. When operating power is supplied to the fourth display IC 208, it can store and retain the display data stored in the storage buffer, and continuously displays the display content corresponding to the stored display data on the fourth notification display device 204. When the display data is changed by the MPU 62, the display on the fourth notification display device 204 is changed to the display content corresponding to the changed display data. Furthermore, in situations where power supply to the fourth display IC 208 has started but the MPU 62 has not yet set the display data, the display data will be all "0". In this case, the fourth notification display device 204 will be in a non-display state, i.e., off state.

However, the configuration is not limited to this example. The fourth display IC 208 may be configured to store and retain display data even when the power supply to the pachinko machine 10 is stopped, by supplying backup power to the fourth display IC 208. In this case, when the power supply to the pachinko machine 10 is resumed, the display that was being shown on the fourth notification display device 204 immediately before the power supply to the pachinko machine 10 was stopped will be resumed on the fourth notification display device 204.

The output of display data to the first to fourth display ICs 205 to 208 is performed by the MPU 62, but the output settings for this display data are performed by both the main CPU 63 and the management CPU 112. In other words, the main CPU 63 executes display control for the first to fourth notification display devices 201 to 204, while the management CPU 112 also executes display control for the first to fourth notification display devices 201 to 204. In this case, the periods during which the output settings for the display data are performed are adjusted so that the main CPU 63 and the management CPU 112 do not perform the settings simultaneously. Specifically, after the supply of operating power to the MPU 62 begins, when the setting state of the pachinko machine 10 can be changed, the main CPU 63 performs the output settings for the display data, while the management CPU 112 does not. On the other hand, when the setting value cannot be changed, the management CPU 112 performs the output settings for the display data, while the main CPU 63 does not.

Furthermore, if the display data output settings by the main CPU 63 and the management CPU 112 are synchronized, the display data output settings by the main CPU 63 take precedence. However, this is not the only option; a configuration where the display data output settings by the management CPU 112 take precedence is also possible.

Next, the display processing in this embodiment, which is executed by the management CPU 112, will be explained with reference to the flowchart in Figure 55.

First, the value of the update timing counter in the management RAM 114 is decremented by 1 (step S3001). The update timing counter is used by the management CPU 112 to identify when it is time to update the display content of the game history management results in the first to fourth notification display devices 201 to 204. Then, by determining whether the value of the update timing counter after the decrement is "0", it is determined whether it is time to update the display content of the first to fourth notification display devices 201 to 204 (step S3002).

If a positive result is obtained in step S3002, the value of the display target counter in the management RAM 114 is incremented by 1 (step S3003). If the value of the display target counter after incrementing by 1 exceeds the maximum value of "24" (step S3004: YES), the value of the display target counter is cleared to "0" (step S3005). The display target counter is a counter used by the management CPU 112 to identify the type of parameter that is the target of display in the first to fourth notification display devices 201 to 204. There is a one-to-one correspondence between the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirtieth parameter, and the possible values of the display target counter from "0" to "24". For example, if the value of the display target counter is "0", the first parameter, which is the first display target, will be displayed on the first to fourth notification display devices 201 to 204. If the value of the display target counter is "24", the 42nd parameter, which is the last display target, will be displayed on the first to fourth notification display devices 201 to 204.

If a negative determination is made in step S3004, or if the process in step S3005 is executed, display data corresponding to the type of parameter corresponding to the value of the display target counter is read from the management ROM 113 (step S3006). Then, the setting process for the display data corresponding to the first notification display device 201 is executed (step S3007), and the setting process for the display data corresponding to the second notification display device 202 is executed (step S3008). For example, if the value of the display target counter is "0" and the first parameter is the display target, display data for displaying "A" on the first notification display device 201 is output to the first display IC 205, and display data for displaying "1" on the second notification display device 202 is output to the second display IC 206. Furthermore, if, for example, the value of the display target counter is "24" and the 42nd parameter is the display target, then display data for displaying "O" on the first notification display device 201 is output to the first display IC 205, and display data for displaying "2" on the second notification display device 202 is output to the second display IC 206.

Subsequently, the parameter corresponding to the value of the display target counter is read from the calculation result memory 131, and the display data corresponding to the tens digit and the units digit of the result obtained by multiplying the read parameter by 100 is read from the management ROM 113 (step S3009). Then, the display control of the third notification display device 203 is performed so that the digit corresponding to the tens digit of the result is displayed (step S3010), and the display control of the fourth notification display device 204 is performed so that the digit corresponding to the units digit is displayed (step S3011). For example, if the result of multiplying by 100 is "53", display data for displaying "5" on the third notification display device 203 is output to the third display IC 207, and display data for displaying "3" on the fourth notification display device 204 is output to the fourth display IC 208.

Subsequently, the update timing counter in the management RAM 114 is set to a value corresponding to 2 seconds as the value for the next update timing (step S3012).

As described above, the display processing is executed, and the game history management results are displayed on the first to fourth notification display devices 201 to 204. This display of the game history management results is performed regardless of whether the game is continuing or not, and regardless of whether the game machine body 12 is opened from the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By performing display control on the first to fourth notification display devices 201 to 204 regardless of the game status or the state of the pachinko machine 10, the processing configuration for controlling the display on the first to fourth notification display devices 201 to 204 can be simplified.

The display of the game history management results in the first to fourth notification display devices 201 to 204 begins after the supply of operating power to the management CPU 112 has started and after the identification completion command has been received from the main CPU 63. In this case, the information stored in the calculation result memory 131 is retained even when the supply of operating power to the pachinko machine 10 is stopped, similar to the information stored in the history memory 117. Therefore, when the supply of operating power to the management CPU 112 is started, the game history management results calculated before the supply of operating power to the management CPU 112 was stopped are displayed.

The first to fourth display ICs 205 to 208 store and retain the display data output from the MPU 62 while power is supplied, and control the display of the corresponding first to fourth notification display devices 201 to 204 according to that display data. Therefore, after the display of the game history management results begins, the first to fourth notification display devices 201 to 204 never turn off (i.e., remain hidden), but remain lit (i.e., displaying) in a state corresponding to some kind of display.

Next, the setting value update process in this embodiment, which is executed by the main CPU 63, will be explained with reference to the flowchart in Figure 56.

First, the process of turning off the lights of the first to third notification display devices 201 to 203 is executed (step S3101). Specifically, display data consisting of all "0"s is output to the first to third display ICs 205 to 207. As a result, all display segments of the first to third notification display devices 201 to 203 are turned off, and the first to third notification display devices 201 to 203 become non-displayed. Immediately after the supply of operating power to the pachinko machine 10 is started, all display segments of the first to fourth notification display devices 201 to 204 are turned off, and the first to fourth notification display devices 201 to 204 are non-displayed. Therefore, step S3101 is a process to maintain the first to third notification display devices 201 to 203 in a non-displayed state, and if any of the first to third notification display devices 201 to 203 were in a display state due to some influence, it is a process to turn them non-displayed.

Subsequently, the setting value counter in the main RAM 65 is set to "1" (step S3102). The setting value counter is used by the main CPU 63 to determine which setting value the pachinko machine 10 is currently using. When "1" is set in the setting value counter, the setting value becomes "Setting 1" regardless of the previous setting value when the setting value update process is executed.

Subsequently, the display start process for the set value is executed in the fourth display notification device 204 (step S3103). During the set value display start process, display data for displaying "1" is output to the fourth display IC 208. As a result, the number "1" corresponding to "Setting 1" is displayed on the fourth notification display device 204.

Subsequently, assuming that the setting key insertion unit 68a is not in the OFF position (step S3104: NO), it is determined whether the update button 68b has been pressed once (step S3105). Specifically, it is determined whether the signal from the sensor detecting the press operation of the update button 68b has switched from a LOW level to a HI level. If a negative result is obtained in step S3105, the process returns to step S3104, and it is determined whether the setting key insertion unit 68a is in the OFF position.

If the update button 68b is pressed once (step S3105: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S3106). Furthermore, if the value of the setting value counter exceeds "6" after the increment (step S3107: YES), the setting value counter is set to "1" (step S3108). As a result, each time the update button 68b is pressed, the setting is updated to the next higher level, and if the update button 68b is pressed once while the setting is "6", it returns to "1".

If a negative determination is made in step S3107, or if the process in step S3108 is executed, the setting value display update process is performed on the fourth notification display device 204 (step S3109). In the setting value display update process, display data corresponding to the value of the setting value counter in the main RAM 65 is output to the fourth display IC 208. As a result, the number corresponding to the current setting value is displayed on the fourth notification display device 204. The manager of the amusement hall can then understand the setting status of the pachinko machine 10 after pressing the update button 68b by checking the fourth notification display device 204.

After executing the process in step S3109, the process returns to step S3104 to determine whether the setting key insertion unit 68a is in the OFF position. If it is not in the OFF position (step S3104: NO), the processes from step S3105 onwards are executed again. If it is in the OFF position (step S3104: YES), the process to start displaying the management results in the first to fourth notification display devices 201 to 204 is executed (step S3110).

In this display start process, a command to start displaying the management results is sent from the main CPU 63 to the management CPU 112. Upon receiving this command, the management CPU 112 executes a process to display the first parameter among the various parameters stored in the calculation result memory 131. The processing in this case is the same as steps S3006 to S3012 in the display processing (Figure 55). As a result, the display corresponding to the first parameter calculated immediately before the operating power of the pachinko machine 10 was last stopped is displayed on the first to fourth notification display devices 201 to 204.

Next, the display modes of the first to fourth notification display devices 201 to 204 in the cases where the game history management results are displayed and when the settings of the pachinko machine 10 are updated will be described. Figure 57(a) is an explanatory diagram illustrating the display modes of the first to fourth notification display devices 201 to 204 when the game history management results are displayed, and Figure 57(b) is an explanatory diagram illustrating the display modes of the first to fourth notification display devices 201 to 204 when the settings of the pachinko machine 10 are changed.

When the game history management results are displayed, at least one display segment in each of the first to fourth notification display devices 201 to 204 illuminates, as shown in Figure 57(a). In other words, each of the first to fourth notification display devices 201 to 204 becomes visible. This is the same regardless of whether the first to eighth parameters, eleventh to eighteen parameters, twenty-first to twenty-sixth parameters, thirty-first parameter, or forty-fourth parameters are the ones being notified. This allows the manager of the gaming hall to visually confirm that the game history management results are being displayed on the first to fourth notification display devices 201 to 204 by visually observing that all of them are visible.

On the other hand, when the settings of the pachinko machine 10 are changed, all display segments on each of the first to third notification display devices 201 to 203 are turned off, as shown in Figure 57(b). In other words, each of the first to third notification display devices 201 to 203 becomes invisible. Furthermore, one of the numbers "1" to "6" is displayed on the fourth notification display device 204. In this way, when one of the numbers "1" to "6" is displayed on the fourth notification display device 204 and the first to third notification display devices 201 to 203 become invisible, the manager of the amusement hall can understand that the display corresponding to the setting value is being shown on the first to fourth notification display devices 201 to 204, and can clearly understand the current setting value.

Next, we will explain how the first to fourth notification display devices 201 to 204 enter their display states, referring to the time charts in Figures 58(a) to 58(h). Figure 58(a) shows the period during which the settings of the pachinko machine 10 can be changed; Figure 58(b) shows the update timing of the setting displays in the first to fourth notification display devices 201 to 204; Figure 58(c) shows the period during which the game history management results are displayed in the first to fourth notification display devices 201 to 204; Figure 58(d) shows the update timing of the displays corresponding to the game history management results in the first to fourth notification display devices 201 to 204; Figure 58(e) shows the period during which the first notification display device 201 is in a display state; Figure 58(f) shows the period during which the second notification display device 202 is in a display state; Figure 58(g) shows the period during which the third notification display device 203 is in a display state; and Figure 58(h) shows the period during which the fourth notification display device 204 is in a display state.

When the setting key insertion unit 68a is turned ON, power is supplied to the pachinko machine 10, and as shown in Figure 58(a), at timing t1, the setting state of the pachinko machine 10 becomes changeable. At timing t1, as shown in Figure 58(b), the setting display is updated, and as shown in Figure 58(h), the fourth notification display device 204 enters a display state, which continues. In this case, since "Setting 1" is selected, "1" is displayed on the fourth notification display device 204. On the other hand, at timing t1, as shown in Figures 58(e) to 58(g), the first to third notification display devices 201 to 203 remain in a non-display state, meaning all display segments are turned off.

Subsequently, at timings t2, t3, t4, and t5, the update button 68b is operated to change the setting value, resulting in an update timing for the setting value display, as shown in Figure 58(b). In this case, as shown in Figure 58(h), the fourth notification display device 204 switches its display content to the number corresponding to the changed setting value at each of these timings. The fourth notification display device 204 remains in the display state, including at each timing in which this display content switch occurs. On the other hand, as shown in Figures 58(e) to 58(g), the first to third notification display devices 201 to 203 remain in a non-display state, meaning all display segments are turned off, at each of these setting value display update timings.

Subsequently, at timing t6, the setting key insertion unit 68a is turned OFF, ending the changeable state as shown in Figure 58(a). In this case, at timing t6, the display period for the game history management results begins as shown in Figure 58(c). Specifically, the display of the first parameter stored in the calculation result memory 131 begins. Therefore, at timing t6, as shown in Figures 58(e) to 58(g), the first to third notification display devices 201 to 203 are switched from the hidden state to the displayed state, and the fourth notification display device 204 remains in the displayed state, although the displayed content is changed.

Subsequently, at timings t7, t8, t9, t10, t11, and t12, the display of the game history management results is updated, as shown in Figure 58(d). In this case, as shown in Figures 58(e) to 58(h), the first to fourth notification display devices 201 to 204 switch to display content corresponding to the updated game history management results at each of these timings. However, the first to fourth notification display devices 201 to 204 are all maintained in their display state, including at each timing when the display content is switched.

The embodiment described in detail above provides the following excellent effects.

In a configuration where the results of game history management are displayed on the first to fourth notification display devices 201 to 204, when the settings of the pachinko machine 10 can be changed (a changeable state), the corresponding display is shown on the first to fourth notification display devices 201 to 204. This allows the first to fourth notification display devices 201 to 204 to be used not only for displaying the results of game history management but also for displaying corresponding information when the settings are changeable.

The period during which the game history management results are displayed in the first to fourth notification display devices 201 to 204 is distinguished from the period during which the first to fourth notification display devices 201 to 204 display an indication that the setting value can be changed. This allows for the identification of which indication is being displayed in each of the first to fourth notification display devices 201 to 204 by understanding the display status.

When a display corresponding to the changeable setting is shown, the first to fourth notification display devices 201 to 204 are controlled to display in a different manner than when the game history management results are displayed. This makes it possible to identify which display is being shown on the first to fourth notification display devices 201 to 204 by understanding their respective display modes.

Multiple notification display devices 201-204 are provided. This allows for a wide variety of displays corresponding to the game history management results. Furthermore, the presence of multiple notification display devices 201-204 allows for significant differences in display patterns between when game history management results are displayed and when displays corresponding to the changeable setting status are shown.

When a display corresponding to the changeable setting status is shown, the first to third notification display devices 201 to 203, which are not hidden when displaying the game history management results, will be hidden. This makes it possible to clearly identify whether the display of game history management results or the display corresponding to the changeable setting status is being performed by the first to fourth notification display devices 201 to 204 simply by checking whether the first to third notification display devices 201 to 203 are hidden or not.

When a display corresponding to the changeable setting state is shown, the fourth notification display device 204 enters a display state, and its display content is the same as the content that can be displayed on the fourth notification display device 204 when displaying the game history management results. By allowing the display content of the fourth notification display device 204 to overlap in this way, it becomes possible to avoid restricting the display content when the game history management results are displayed and when a display corresponding to the changeable setting state is shown. Furthermore, even with this configuration where the display content of the fourth notification display device 204 overlaps, when a display corresponding to the changeable setting state is shown, the first to third notification display devices 201 to 203 are hidden, making it possible to identify which display is being shown on the first to fourth notification display devices 201 to 204.

When the game history management results are displayed, each of the first to fourth notification display devices 201 to 204 will enter a display state. This makes it possible to clearly differentiate the display modes of the first to fourth notification display devices 201 to 204 depending on whether the game history management results are displayed or whether a display corresponding to the changeable setting status is shown.

When the game history management results are displayed, the first to fourth notification display devices 201 to 204 will not remain hidden even if the type of game history management results being displayed changes. This makes it possible to identify the game history management results regardless of when the first to fourth notification display devices 201 to 204 were checked while the game history management results were displayed. Furthermore, regardless of when the first to fourth notification display devices 201 to 204 were checked, it becomes possible to determine whether the first to fourth notification display devices 201 to 204 are displaying either the game history management results or the changeable setting status.

When a display corresponding to the changeable setting is shown, only one of the fourth notification display devices 204 will be displayed. This makes it easier to determine whether or not a display corresponding to the changeable setting is being shown.

In a configuration where the first to fourth notification display devices 201 to 204 are arranged horizontally, only the fourth notification display device 204, located at the far right, is used to display the status corresponding to the changeable setting value. This makes it easier to determine whether or not the display corresponding to the changeable setting value is being shown.

When the game history management results are displayed, the first notification display device 201 and the second notification display device 202 are used to display the type of game history management result to be displayed, and the third notification display device 203 and the fourth notification display device 204 are used to display the content of the game history management result. This makes it easier to understand the game history management results. In this case, when the setting value can be changed, both the first notification display device 201 and the second notification display device 202, which display the type of game history management result, are hidden. This means that the state in which the first and second notification display devices 201 and 202 for displaying the type are hidden corresponds to the state in which the setting value can be changed, making it easier to understand that a display corresponding to the state in which the setting value can be changed is being shown.

Furthermore, when a display corresponding to the changeable setting is shown, not only the first and second notification display devices 201 and 202, which display the type of game history management result, but also the third notification display device 203, which displays the content of the game history management result, will be hidden. This makes it easier to understand that a display corresponding to the changeable setting is being shown.

In a configuration where display data is output from the MPU 62 to the first to fourth display ICs 205 to 208, and the first to fourth display ICs 205 to 208 cause the first to fourth notification display devices 201 to 204 to display predetermined information according to that display data, the display data is stored and retained in the first to fourth display ICs 205 to 208. This allows the display of the game history management results on the first to fourth notification display devices 201 to 204 to be maintained even if, for example, a radio wave detection anomaly or vibration detection anomaly occurs and the execution of the processing necessary to continue the game in the main CPU 63 is stopped (when a positive determination is made in step S306).

Furthermore, the targets of the first to fourth notification display devices 201 to 204 that are in a changeable state where the settings of the pachinko machine 10 can be changed are not limited to the first to third notification display devices 201 to 203, but may also be the first and second notification display devices 201 and 202. In this case, the third notification display device 203 may display a predetermined display different from the content of the current setting value (for example, a display of "5"), and the fourth notification display device 204 may display a number corresponding to the current setting value. Furthermore, the system may be configured such that the first notification display device 201 and the third notification display device 203 are in a non-display state (all lights off) while the second notification display device 202 and the fourth notification display device 204 are in a display state; or the first notification display device 201 and the fourth notification display device 204 are in a non-display state (all lights off) while the second notification display device 202 and the third notification display device 203 are in a display state; or the second notification display device 202 and the fourth notification display device 204 are in a non-display state (all lights off) while the first notification display device 201 and the third notification display device 203 are in a display state.

Furthermore, in the changeable state where the settings of the pachinko machine 10 can be changed, the configuration may be such that only the first notification display device 201 is hidden (all lights off), only the second notification display device 202 is hidden (all lights off), only the third notification display device 203 is hidden (all lights off), or only the fourth notification display device 204 is hidden (all lights off).

Furthermore, in the changeable state where the settings of the pachinko machine 10 can be changed, the configuration may be such that only the first notification display device 201 is displayed, or only the second notification display device 202 is displayed, or only the third notification display device 203 is displayed.

<Embodiment 12>
In this embodiment, the display contents of the first notification display device 201 and the second notification display device 202 when the set value can be changed differ from those of the 11th embodiment described above. The configurations that differ from the 11th embodiment will be described below. Configurations that are the same as those in the 11th embodiment will generally not be described.

Figure 59(a) is an explanatory diagram illustrating the configuration of the first notification display device 201, and Figure 59(b) is an explanatory diagram illustrating the configuration of the second notification display device 202.

As shown in Figure 59(a), the first notification display device 201 is equipped with seven first to seventh display segments 201a to 201g. Each of the first to seventh display segments 201a to 201g is formed in a rod shape and contains a light-emitting element such as an LED. These seven first to seventh display segments 201a to 201g are arranged so that the first notification display device 201 functions as a so-called seven-segment display.

As shown in Figure 59(b), the second notification display device 202 is equipped with seven first to seventh display segments 202a to 202g. Each of the first to seventh display segments 202a to 202g is formed in a rod shape and contains a light-emitting element such as an LED. These seven first to seventh display segments 202a to 202g are arranged so that the second notification display device 202 functions as a so-called seven-segment display.

Figure 60 is an explanatory diagram illustrating the display contents of the first notification display device 201 and the second notification display device 202 when displaying the management results of the game history on the first to fourth notification display devices 201 to 204, and when indicating that the setting state of the pachinko machine 10 is in a changeable state where it is possible to change the setting state.

The display content of the first notification display device 201 and the second notification display device 202 when displaying the management results of the game history is the same as in the 11th embodiment described above. Therefore, the first notification display device 201 will display one of "A", "E", "H", "L", or "O", and the second notification display device 202 will display one of "1" through "8".

In this case, each of the first to seventh display segments 201a to 201g of the first notification display device 201 will be illuminated when displaying at least one of the "A," "E," "H," "L," or "O" characters on the first notification display device 201. In other words, there are no display segments 201a to 201g that are not illuminated when displaying any of the "A," "E," "H," "L," or "O" characters on the first notification display device 201.

Similarly, for the second notification display device 202, each of the first to seventh display segments 202a to 202g of the second notification display device 202 is subject to illumination for at least one of the displays "1" to "8" on the second notification display device 202. In other words, there are no display segments 202a to 202g that are not subject to illumination regardless of which of "1" to "8" is displayed on the second notification display device 202.

In the changeable state where the settings of the pachinko machine 10 can be changed, the second display segment 201b and the fifth display segment 201e of the first notification display device 201 become illuminated. As already explained, these second display segment 201b and fifth display segment 201e may become illuminated when the first notification display device 201 displays the results of the game history management. Furthermore, the second display segment 201b and fifth display segment 201e become illuminated in any case when the first notification display device 201 displays the results of the game history management. On the other hand, there is no display content of the first notification display device 201 in which only the second display segment 201b and the fifth display segment 201e of the first to seventh display segments 201a to 201g become illuminated when displaying the results of the game history management. This makes it possible to display a display mode on the first notification display device 201 that is not displayed when the game history management results are displayed, while utilizing display segments 201b and 201e, which can become illuminated when the game history management results are displayed, when the setting value is changeable. Therefore, it becomes possible to display a display corresponding to the changeable setting value state on the first notification display device 201 while also using display segments 201a to 201g, which are used when displaying the game history management results.

When the setting value can be changed, the third display segment 202c of the second notification display device 202 illuminates. As previously explained, the third display segment 202c may illuminate when the second notification display device 202 displays the game history management results. On the other hand, the display content of the second notification display device 202 where only the third display segment 202c among the first to seventh display segments 202a to 202g is illuminated does not exist when displaying the game history management results. Therefore, when the setting value can be changed, it is possible to use the display segment 202c, which may illuminate when displaying the game history management results, while simultaneously displaying a display mode on the second notification display device 202 that is not displayed when displaying the game history management results. Thus, it is possible to use the display segments 202a to 202g, which are used when displaying the game history management results, while simultaneously displaying information corresponding to the setting value changeable state on the second notification display device 202.

Next, the setting value update process in this embodiment, which is executed by the main CPU 63, will be explained with reference to the flowchart in Figure 61.

First, the process to start displaying the setting value in the first and second notification display devices 201 and 202 is executed (step S3201). Specifically, for the first notification display device 201, display data is output to the first display IC 205 such that the second display segment 201b and the fifth display segment 201e become illuminated, and the other display segments 201a, 201c, 201d, 201f, and 201g become unlit. Similarly, for the second notification display device 202, display data is output to the second display IC 206 such that the third display segment 202c becomes illuminated, and the other display segments 202a, 202b, 202d-202g become unlit. This initiates a display on the first notification display device 201 and the second notification display device 202 indicating that the setting state of the pachinko machine 10 is changeable.

Subsequently, the process of turning off the third notification display device 203 is executed (step S3202). Specifically, display data consisting of all "0"s is output to the third display IC 207. As a result, all display segments of the third notification display device 203 turn off, and the third notification display device 203 becomes invisible.

Subsequently, the setting value counter in the main RAM 65 is set to "1" (step S3203). The setting value counter is used by the main CPU 63 to determine which setting value the pachinko machine 10 is currently using. When "1" is set in the setting value counter, the setting value becomes "Setting 1" regardless of the previous setting value when the setting value update process is executed.

Subsequently, the process for starting the display of the set value in the fourth notification display device 204 is executed (step S3204). During this process, display data for displaying "1" is output to the fourth display IC 208. As a result, the number "1" corresponding to "Setting 1" is displayed on the fourth notification display device 204.

Subsequently, assuming that the setting key insertion unit 68a is not in the OFF position (step S3205: NO), it is determined whether the update button 68b has been pressed once (step S3206). Specifically, it is determined whether the signal from the sensor detecting the press operation of the update button 68b has switched from a LOW level to a HI level. If a negative determination is made in step S3206, the process returns to step S3205, and it is determined whether the setting key insertion unit 68a is in the OFF position.

If the update button 68b is pressed once (step S3206: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S3207). Furthermore, if the value of the setting value counter exceeds "6" after the increment (step S3208: YES), the setting value counter is set to "1" (step S3209). As a result, each time the update button 68b is pressed, the setting is updated to the next higher level, and if the update button 68b is pressed once while the setting is "6", it returns to "1".

If a negative determination is made in step S3208, or if the process in step S3209 is executed, the setting value display update process is executed on the fourth notification display device 204 (step S3210). In the setting value display update process, display data corresponding to the value of the setting value counter in the main RAM 65 is output to the fourth display IC 208. As a result, the number corresponding to the current setting value is displayed on the fourth notification display device 204. The manager of the amusement hall can then check the fourth notification display device 204 to understand the setting status of the pachinko machine 10 after pressing the update button 68b.

After executing the process in step S3210, the process returns to step S3205 to determine whether the setting key insertion unit 68a is in the OFF position. If it is not in the OFF position (step S3205: NO), the processes from step S3206 onwards are executed again. If it is in the OFF position (step S3205: YES), the process to start displaying the management results in the first to fourth notification display devices 201 to 204 is executed (step S3211).

In this display start process, a command to start displaying the management results is sent from the main CPU 63 to the management CPU 112. Upon receiving this command, the management CPU 112 executes a process to display the first parameter among the various parameters stored in the calculation result memory 131. The processing in this case is the same as steps S3006 to S3012 in the display processing (Figure 55). As a result, the display corresponding to the first parameter calculated immediately before the operating power of the pachinko machine 10 was last stopped is displayed on the first to fourth notification display devices 201 to 204.

The embodiment described in detail above provides the following excellent effects.

When the results of game history management are displayed, the display segments 201a-201g and 202a-202g of the first and second notification display devices 201 and 202, which can become illuminated, are illuminated to display the status corresponding to the changeable setting value. This makes it possible to diversify the display of game history management results while minimizing restrictions on the content of the display corresponding to the game history management results. On the other hand, for each of the first notification display device 201 and the second notification display device 202, the combinations of display segments 201a-201g and 202a-202g that become illuminated when the display corresponding to the changeable setting value is displayed do not exist when the game history management results are displayed. As a result, by knowing the combinations of display segments 201a-201g and 202a-202g that become illuminated for each of the first notification display device 201 and the second notification display device 202, it becomes possible to know whether the display of game history management results or the display corresponding to the changeable setting value is being displayed.

For both the first notification display device 201 and the second notification display device 202, there are no display segments 201a-201g and 202a-202g that do not illuminate even when all patterns of game history management results are displayed. This makes it possible to diversify the display corresponding to game history management results while minimizing restrictions on the display content of the game history management results.

When a display corresponding to the changeable setting status is shown, the third notification display device 203, which is not hidden when displaying the game history management results, becomes hidden. This allows for clear identification of whether the display of game history management results or the display corresponding to the changeable setting status is being performed by the first to fourth notification display devices 201 to 204, by checking not only the display content of the first and second notification display devices 201 and 202, but also whether the third notification display device 203 is hidden.

Furthermore, the configuration in which the first and second notification display devices 201 and 202 can change the setting state of the pachinko machine 10 is not limited to having only one type of display content set for each changeable state; multiple types may be set. In this case, the display order of these multiple types of display content may be predetermined, and the display content to be displayed may be changed according to that display order each time the changeable state is newly executed. Even when there are multiple types of display content corresponding to the changeable state of the setting value, these display contents are displayed using display segments 201a to 201g and 202a to 202g, which become illuminated when displaying the game history management results, and are not displayed when displaying the game history management results.

Furthermore, in one case, when displaying the results of game history management, or when displaying a changeable state where the settings of the pachinko machine 10 can be changed, the first and second notification display devices 201 and 202 may be configured to flash, while in the other case, they may be configured to maintain a steady light. In this case, the administrator of the gaming hall can identify whether the display is for the results of game history management or a changeable state based on whether it is a flashing or steady light display. Therefore, the combination of display segments 201a to 201g and 202a to 202g that are illuminated in the display corresponding to the changeable state may be the same combination used when displaying the results of game history management, or it may be a combination not used when displaying the results of game history management. Also, the lighting period and the off period in the flashing display may be configured to coincide with each other in the first notification display device 201 and the second notification display device 202, or they may be completely out of sync, or they may partially overlap.

<Embodiment 13>
In this embodiment, a difference from the 11th embodiment is that when an abnormal condition occurs in the pachinko machine 10, a corresponding display is provided using the first to fourth notification display devices 201 to 204. The configurations that differ from the 11th embodiment will be described below. Configurations that are the same as those in the 11th embodiment will generally not be described.

Figure 62 is an explanatory diagram illustrating the configuration of the error display area 211 provided in the main RAM 65.

The abnormality display area 211 is an area for storing information about abnormal states to be displayed on the first to fourth notification display devices 201 to 204. The abnormality display area 211 is provided with multiple unit areas 211a to 211d. Specifically, it includes a first unit area 211a, a second unit area 211b, a third unit area 211c, and a fourth unit area 211d. Each of these first to fourth unit areas 211a to 211d can store one piece of information about an abnormal state of the pachinko machine 10. In other words, the abnormality display area 211 can store and hold up to four pieces of information about abnormal states of the pachinko machine 10.

In this embodiment, all information regarding abnormal conditions occurring in the pachinko machine 10 is identified by the main CPU 63. For example, if an abnormality related to the payout of game balls occurs (e.g., the lower tray 56a is full, the tank 75 is empty, or there is a payout abnormality by the payout device 76), a command corresponding to the abnormality is transmitted from the payout CPU 92 to the main CPU 63. The pachinko machine 10 is also equipped with a radio wave detection sensor and a vibration detection sensor (not shown). If the radio wave detection sensor detects an unauthorized radio wave, a corresponding abnormality signal is transmitted to the main CPU 63. If the vibration detection sensor detects an abnormal vibration, a corresponding abnormality signal is transmitted to the main CPU 63. Furthermore, based on the identification of the discontinuation of normal signal transmission from each ball entry detection sensor 42a to 49a, the occurrence of a disconnection abnormality in these ball entry detection sensors 42a to 49a is identified.

The number of abnormal conditions identified by the main CPU 63 is greater than the maximum number of abnormal condition information that can be stored in the abnormal condition display area 211. Therefore, if many abnormal conditions occur simultaneously, it is anticipated that new abnormal information will occur even though the abnormal condition display area 211 already stores the maximum number of abnormal condition information. To address this, a storage priority is set for the abnormal condition information during the setup of the pachinko machine 10. If a new abnormal condition occurs when the abnormal condition display area 211 already stores the maximum number of abnormal condition information, the information of the abnormal condition with the higher storage priority will remain in the abnormal condition display area 211. This allows for the notification of abnormal conditions with higher storage priority to be prioritized.

Next, the error setting process executed by the main CPU 63 will be explained with reference to the flowchart in Figure 63. Note that the error setting process is executed as the first step in the timer interrupt processing (Figure 11).

First, it is determined whether or not an abnormality requiring display has occurred (step S3301). The types of abnormalities requiring display include a full lower tray 56a, no balls in the tank 75, a payout abnormality by the payout device 76, a radio wave detection abnormality, a vibration detection abnormality, and a broken wire in each of the ball entry detection sensors 42a to 49a. The number of these types of abnormalities requiring display is greater than the number of first to fourth unit areas 211a to 211d located in the abnormality display area 211.

If a positive result is obtained in step S3301, it is determined whether the information of the abnormal state corresponding to the abnormal display target that occurred this time is already stored in one of the first to fourth unit areas 211a to 211d of the abnormal display area 211 (step S3302). If it is already stored, the information of the abnormal state corresponding to the abnormal display target that occurred this time will not be stored in the abnormal display area 211. This makes it possible to prevent duplicate storage of information of the same type of abnormal state in the abnormal display area 211.

If a negative determination is made in step S3302, it is determined whether the value of the abnormality target counter provided in the main RAM 65 is the maximum value (specifically, "4") (step S3303). The abnormality target counter is a counter used by the main CPU 63 to identify the number of areas among the first to fourth unit areas 211a to 211d in the abnormality display area 211 where information about the abnormal state is stored.

If the value of the abnormality target counter is at its maximum (step S3303: YES), a priority comparison process is executed (step S3304). In the priority comparison process, the information of the abnormality with the lowest memory priority is first identified from the information of abnormalities stored in the first to fourth unit areas 211a to 211d of the abnormality display area 211. The memory priority is predetermined during the design phase of the pachinko machine 10, specifically in the following order of increasing priority: full lower tray 56a → no balls in tank 75 → vibration detection abnormality → payout abnormality by payout device 76 → disconnection abnormality of ball entry detection sensors 42a to 49a → radio wave detection abnormality. In the priority comparison process, the information of the abnormality with the lowest memory priority stored in the first to fourth unit areas 211a to 211d is compared with the memory priority of the abnormality display target that occurred this time to determine which has a higher memory priority.

If the memory priority of the currently occurring anomaly display target is lower (step S3305: NO), the information of the anomaly state corresponding to the currently occurring anomaly display target is not stored in the anomaly display area 211. This makes it possible to retain information of anomaly states with higher memory priority in the anomaly display area 211 in configurations where the number of types of anomaly display targets is greater than the number of the first to fourth unit areas 211a to 211d provided in the anomaly display area 211.

If the memory priority of the abnormality display target that occurred this time is higher (step S3305: YES), the abnormality display area 211 setting process is executed (step S3306). In the abnormality display area 211 setting process executed when a positive determination is made in step S3305, the information of the abnormal state corresponding to the abnormality display target that occurred this time is overwritten in the unit areas 211a to 211d, which are identified as containing the information of the abnormal state with the lowest memory priority.

On the other hand, if the value of the abnormality target counter in the main RAM 65 has not reached its maximum value (step S3303: NO), the value of the abnormality target counter is incremented by 1 (step S3307), and then the setting process for the abnormality display area 211 is executed (step S3306). In this setting process, one area is selected from the unit areas 211a to 211d in the abnormality display area 211 that do not currently contain abnormality information, and the abnormality information corresponding to the abnormality target that occurred is stored in the selected area.

In step S3306, if there is only one abnormal state information stored in the abnormal display area 211, that abnormal state information is stored in the first unit area 211a. If there are multiple abnormal state information stored in the abnormal display area 211, the abnormal state information is stored in the nth unit areas 211a to 211b in order from the area with the smallest value of "n".

In the abnormal setting process, it is determined whether or not a clearing event for the abnormal display target has occurred (step S3308). For example, it is determined whether a command indicating that the full state of the lower tray 56a has been cleared, that the empty state of the tank 75 has been cleared, or that a clearing abnormality by the dispensing device 76 has been cleared has been received from the dispensing-side CPU 92. It is also determined whether or not an abnormality clearing operation has been performed for a radio wave detection abnormality, a vibration detection abnormality, or a wire break abnormality.

If a positive result is obtained in step S3308, the error display area 211 is cleared (step S3309). In this clearing process, it is determined whether the information of the abnormal state corresponding to the error display target that was cleared is stored in any of the first to fourth unit areas 211a to 211d of the error display area 211. If it is stored, the area containing the information is cleared to "0" to erase the information. In this case, if only one piece of information about an abnormal state remains in the error display area 211 after clearing, that information is stored in the first unit area 211a. If multiple pieces of information about abnormal states remain in the error display area 211 after clearing, the information is stored in the nth unit areas 211a to 211b in order from the area with the smallest value of "n". Also, the value of the error target counter in the main RAM 65 is decremented by 1 (step S3310).

In the abnormal setting process, it is determined whether or not the operation to initiate the abnormal display has occurred (step S3311). The operation to initiate the abnormal display is performed by pressing the update button 68b while the game machine body 12 is open forward relative to the outer frame 11, in a situation where the setting state of the pachinko machine 10 is not in a changeable state where it is possible to change the setting state.

If a positive result is obtained in step S3311, it is determined whether or not one or more abnormal state information is stored in the abnormal display area 211 (step S3312). If no abnormal state information is stored, the abnormal display on the first to fourth notification display devices 201 to 204 will not start. This prevents the abnormal display from starting even when there is no abnormal state information to report.

If a positive result is obtained in step S3312, the "Abnormal Display In Progress" flag in the main RAM 65 is set to "1" (step S3313). The "Abnormal Display In Progress" flag is used by the main CPU 63 to identify a situation where the display corresponding to the game history management result should be stopped, and the display corresponding to the abnormal state information stored in the abnormal display area 211 should be displayed on the first to fourth notification display devices 201 to 204. Even if the abnormal display start operation is performed while the "Abnormal Display In Progress" flag is already set to "1," a negative result is obtained in step S3311.

Subsequently, the process for stopping the display of management results is executed (step S3314). This stopping process sends a display stop command to the management CPU 112, temporarily halting the updating of the game history management results displayed on the first to fourth notification display devices 201 to 204. Upon receiving this display stop command, the management CPU 112 stops the execution of the display processing (Figure 55). However, even if the management CPU 112 receives the display stop command, it does not set display data consisting of all "0"s to the first to fourth display ICs 205 to 208. Therefore, the display of the game history management results at that point in time continues on the first to fourth notification display devices 201 to 204 until display data is transmitted from the main CPU 63 to the first to fourth display ICs 205 to 208.

In the abnormal setting processing, it is determined whether or not an operation to terminate the abnormal display has occurred (step S3315). The operation to terminate the abnormal display is performed by pressing the reset button 68c while the game machine body 12 is open forward relative to the outer frame 11, in a situation where the setting state of the pachinko machine 10 is not in a changeable state where it is possible to change the setting state. If a positive determination is made in step S3315, the abnormal display flag in the main RAM 65 is cleared to "0" (step S3316). Even if the abnormal display termination operation is performed while the abnormal display flag value is already "0", a negative determination is made in step S3315.

Subsequently, the process of canceling the display of the management results is executed (step S3317). In this cancellation cancellation process, a cancellation cancellation command is sent to the management CPU 112, thereby canceling the state in which the updating of the game history management results display on the first to fourth notification display devices 201 to 204 is suspended. Upon receiving the cancellation cancellation command, the management CPU 112 resumes the execution of the display processing (Figure 55). However, even if the management CPU 112 receives the cancellation cancellation command, it does not set display data of all "0" data on the first to fourth display ICs 205 to 208. Therefore, until display data is transmitted from the management CPU 112 to the first to fourth display ICs 205 to 208, the abnormal display at that time continues on the first to fourth notification display devices 201 to 204. In addition, even when the updating of the game history management results display is suspended, the management CPU 112 continues to store history information and calculate various parameters, and the results of the calculations of various parameters are stored in the calculation result memory 131. Therefore, when the suspension of updating the display of the game history management results is lifted, the display of the most recent game history management results will immediately resume on the first to fourth notification display devices 201 to 204.

In the error setting process, if the error display flag in the main RAM 65 is set to "1" (step S3318: YES), the error display process is executed (step S3319). Figure 64 is a flowchart showing the error display process.

First, the process of turning off the lights on the first and second notification display devices 201 and 202 is executed (step S3401). Specifically, display data consisting of all "0"s is output to the first and second display ICs 205 and 206. As a result, all display segments on both the first and second notification display devices 201 and 202 are turned off, and the first and second notification display devices 201 and 202 become invisible.

Subsequently, the value of the update timing counter in the main RAM 65 is decremented by 1 (step S3402). The update timing counter is used by the main CPU 63 to identify when it is time to update the display content of the abnormality indication in the first to fourth notification display devices 201 to 204. If the value of the update timing counter is already "0", that state is maintained. Then, by determining whether the value of the update timing counter is "0", it is determined whether it is time to update the display content of the first to fourth notification display devices 201 to 204 (step S3403).

If a positive result is obtained in step S3403, the update process for the display target counter in the main RAM 65 is executed (step S3404). In this update process, if this is the first error display process since the error display flag in the main RAM 65 was set to "1", the display target counter is set to "0". The value of the display target counter corresponds to the first to fourth unit areas 211a to 211d of the error display area 211. Specifically, a value of "0" corresponds to the first unit area 211a, a value of "1" corresponds to the second unit area 211b, a value of "2" corresponds to the third unit area 211c, and a value of "3" corresponds to the fourth unit area 211d. In the update process, if this is not the first error display process since the error display flag in the main RAM 65 was set to "1", the value of the display target counter is incremented by 1.

Subsequently, it is determined whether or not abnormal state information is stored in the area corresponding to the current value of the display target counter among the first to fourth unit areas 211a to 211d (step S3405). As already explained, if only one abnormal state information is stored, that information is stored in the first unit area 211a. If multiple abnormal state information is stored, the information is stored in the nth unit areas 211a to 211b in order from the area with the smallest value of "n". Therefore, if abnormal state information is not stored in the area corresponding to the current value of the display target counter, it means that abnormal state information is also not stored in the area corresponding to a value greater than that of the display target counter. Furthermore, if the value of the display target counter after incrementing by 1 exceeds the maximum value of "3", there is no corresponding area, and therefore, abnormal state information is treated as not being stored.

If a positive result is obtained in step S3405, the value of the display target counter in the main RAM 65 is cleared to "0" (step S3406). At this point, it is assumed that all abnormal states that were the target of the abnormal display are cleared. In this case, even if the abnormal display processing is being executed, the abnormal state information will not be stored in the abnormal display area 211. In such a situation, the third and fourth notification display devices 203 and 204 will display an indication that the abnormal state information is not stored.

If a negative determination is made in step S3405, or if the process in step S3406 is executed, the display data corresponding to the value of the display target counter in the main RAM 65 is read from the main ROM 64 (step S3407). Specifically, the information stored in the area corresponding to the value of the display target counter in the main RAM 65 among the first to fourth unit areas 211a to 211d of the abnormality display area 211 is read. Then, the display data corresponding to that information is read from the main ROM 64. The display data is set to correspond one-to-one with the information of the abnormal state, and the display content of the third and fourth notification display devices 203 and 204 differs depending on the type of information of the abnormal state. In addition, there is display data corresponding to the absence of information of an abnormal state, and this display data differs from the display data corresponding to the information of an abnormal state. Therefore, if there is no information of an abnormal state, the display content of the third and fourth notification display devices 203 and 204 will be different from the display content when information of an abnormal state is present.

On the other hand, the display content corresponding to abnormal state information and the display content corresponding to the absence of abnormal state information in the third and fourth notification display devices 203 and 204 overlap with the display content when the game history management results are displayed in the third and fourth notification display devices 203 and 204, and the display content of the setting values in the fourth notification display device 204. In contrast, when displaying the game history management results, all of the first to fourth notification display devices 201 to 204 are displayed; in a changeable state where the settings of the pachinko machine 10 can be changed, the first to third notification display devices 201 to 203 are hidden and the fourth notification display device 204 is displayed; and when an abnormality is displayed, the first and second notification display devices 201 and 202 are hidden and the third and fourth notification display devices 203 and 204 are displayed. Therefore, even though the display content overlaps as described above, the manager of the gaming hall can understand which situation each display corresponds to.

Subsequently, the display control of the third notification display device 203 is performed according to the display data read in step S3407 (step S3408), and the display control of the fourth notification display device 204 is performed (step S3409). In this case, whether the display corresponds to information about an abnormal state or to the absence of information about an abnormal state, neither the third notification display device 203 nor the fourth notification display device 204 will ever be completely off (i.e., they will never be completely off), but will always be in some display state.

Subsequently, the update timing counter of the main RAM 65 is set to a value corresponding to 2 seconds as the value corresponding to the next update timing (step S3410).

The embodiment described in detail above provides the following excellent effects.

In a configuration where the results of game history management are displayed on the first to fourth notification display devices 201 to 204, the first to fourth notification display devices 201 to 204 also display information corresponding to abnormal states of the pachinko machine 10. This allows the first to fourth notification display devices 201 to 204 to be used not only for displaying game history management results but also for displaying information corresponding to abnormal states.

When no abnormal condition occurs in the pachinko machine 10, and the first to fourth notification display devices 201 to 204 are instructed to display an indication corresponding to an abnormal condition, the first to fourth notification display devices 201 to 204 will display an indication that no abnormal condition has occurred. This makes it possible to clearly determine whether or not an abnormal condition has occurred in the pachinko machine 10 by checking the first to fourth notification display devices 201 to 204.

The period during which the game history management results are displayed in the first to fourth notification display devices 201 to 204 is distinct from the period during which the first to fourth notification display devices 201 to 204 display information corresponding to the abnormal state of the pachinko machine 10. This allows for the identification of which display is being shown in each of the first to fourth notification display devices 201 to 204 by understanding the current display status.

When an abnormal state of the pachinko machine 10 is displayed, the first to fourth notification display devices 201 to 204 are controlled to display in a different manner than when the game history management results are displayed. This makes it possible to identify which display is being shown by the first to fourth notification display devices 201 to 204 by understanding their respective display modes.

Multiple notification display devices 201 to 204 are provided. This allows for a wide variety of displays corresponding to the game history management results. Furthermore, the presence of multiple notification display devices 201 to 204 makes it possible to significantly differentiate the display format between when game history management results are displayed and when displays corresponding to abnormal states of the pachinko machine 10 are shown.

When a display corresponding to an abnormal state of the pachinko machine 10 is shown, the first and second notification display devices 201 and 202, which do not normally become hidden when displaying the game history management results, become hidden. This makes it possible to clearly identify whether the display of game history management results or the display corresponding to the abnormal state of the pachinko machine 10 is being shown by the first to fourth notification display devices 201 to 204 simply by checking whether the first and second notification display devices 201 and 202 are hidden or not.

When a display corresponding to an abnormal state of the pachinko machine 10 is shown, the third and fourth notification display devices 203 and 204 are activated, and the displayed content is the same as the content that can be displayed on the third and fourth notification display devices 203 and 204 when displaying the game history management results. By allowing the display content of the third and fourth notification display devices 203 and 204 to overlap in this way, it is possible to avoid restricting the display content when the game history management results are displayed and when a display corresponding to an abnormal state of the pachinko machine 10 is shown. Furthermore, even with this configuration where the display content of the third and fourth notification display devices 203 and 204 can overlap, when a display corresponding to an abnormal state of the pachinko machine 10 is shown, the first and second notification display devices 201 and 202 are turned off, making it possible to identify which display is being shown on the first to fourth notification display devices 201 to 204.

Furthermore, if the abnormality display start operation is performed when no abnormality information is stored in the abnormality display area 211, the first to fourth notification display devices 201 to 204 may be configured to display a message indicating that no abnormality information is stored at that time.

<14th Embodiment>
In this embodiment, the processing configuration of the management output processing executed by the main CPU 63 differs from that of the first embodiment. The configurations that differ from those of the first embodiment will be described below. Configurations that are the same as those of the first embodiment will generally not be described.

Figure 65 is a flowchart showing the management output processing in this embodiment, which is executed by the main CPU 63.

First, it is determined whether the management start flag in the main RAM 65 is set to "1" (step S3501). The management start flag is a flag used by the main CPU 63 to determine whether or not it is appropriate to store history information in the history memory 117. In this embodiment, after the supply of operating power to the pachinko machine 10 is started (i.e., after the supply of operating power to the MPU 62 is started), history information is not stored in the history memory 117 until the total number of game balls discharged from the game area PA is equal to or greater than the number corresponding to the management start reference value. When the total number of game balls discharged from the game area PA is equal to or greater than the number corresponding to the management start reference value, the storage of history information in the history memory 117 is started. At the stage of shipping the pachinko machine 10, an operational check of the pachinko machine 10 may be performed before shipment, and at that time, game balls are placed in each ball entry section and the subsequent operation is checked. In contrast, by preventing the history information from being stored in the history memory 117 until the total number of game balls discharged from the game area PA after the start of power supply to the pachinko machine 10 exceeds the management start threshold value, it becomes possible to prevent the results of ball entry during the operation check described above from being stored as history information.

If a negative determination is made in step S3501, the start-up management counter in the main RAM 65 is set to "7" (step S3502). The start-up management counter is used by the main CPU 63 to determine which of the seven ball detection sensors 42a to 48a is in a state where the detection status of a game ball should be determined, given that the management start flag is not set to "1".

Subsequently, it is determined whether the output flag of the main RAM 65 corresponding to the value of the startup management counter is set to "1" (step S3503). Specifically, if the value of the startup management counter is "7" and corresponds to the first prize-winning slot detection sensor 42a, it is determined whether the first output flag is set to "1"; if the value of the startup management counter is "6" and corresponds to the second prize-winning slot detection sensor 43a, it is determined whether the second output flag is set to "1"; if the value of the startup management counter is "5" and corresponds to the third prize-winning slot detection sensor 44a, it is determined whether the third output flag is set to "1"; and if the value of the startup management counter is "4" and corresponds to the special electric detection sensor 45a If it corresponds to the first operation port detection sensor 46a, it is determined whether the fourth output flag is set to "1". If the value of the initial management counter is "3" and it corresponds to the first operation port detection sensor 46a, it is determined whether the fifth output flag is set to "1". If the value of the initial management counter is "2" and it corresponds to the second operation port detection sensor 47a, it is determined whether the sixth output flag is set to "1". If the value of the initial management counter is "1" and it corresponds to the out port 24a, it is determined whether the seventh output flag is set to "1". As previously explained, these first to seventh output flags are set to "1" during the ball entry detection process (Figure 15).

If a positive result is obtained in step S3503, the output flag corresponding to the value of the start management counter is cleared to "0" (step S3504). Then, the value of the ejection counter in the main RAM 65 is incremented by 1 (step S3505). The ejection counter is a counter used by the main CPU 63 to determine the total number of game balls ejected from the game area PA when the management start flag in the main RAM 65 is not set to "1".

Subsequently, it is determined whether the value of the discharge count counter is equal to or greater than the management start threshold (step S3506). While the management start threshold is set to "300," it is not limited to this value; it may be set to a number less than "300," or to a number greater than "300."

If a negative result is obtained in step S3503, or in step S3506, the value of the initial management counter in the main RAM 65 is decremented by 1 (step S3507). Then, it is determined whether the value of the initial management counter after the decrement is "0" (step S3508). If a negative result is obtained in step S3508, the process returns to step S3503. If a positive result is obtained in step S3508, the main management output processing ends immediately.

On the other hand, if the value of the ejection counter in the main RAM 65 is equal to or greater than the management start threshold value (step S3506: YES), the management start flag in the main RAM 65 is set to "1" (step S3509). Then, the management process is executed (step S3510). Furthermore, if the management start flag is set to "1" and a positive determination is made in step S3501, the management process is also executed (step S3510). The processing content of the management process is the same as steps S1001 to S1012 of the management output process (Figure 25) in the first embodiment described above.

According to the above configuration, after the supply of operating power to the pachinko machine 10 begins (i.e., after the supply of operating power to the MPU 62 begins), history information is not stored in the history memory 117 until the total number of game balls discharged from the game area PA exceeds the number corresponding to the management start reference value. When the total number of game balls discharged from the game area PA exceeds the number corresponding to the management start reference value, the storage of history information in the history memory 117 begins. At the shipping stage of the pachinko machine 10, an operational check of the pachinko machine 10 may be performed before shipment. During this check, game balls are inserted into each ball entry point, and subsequent operation is checked. In contrast, by preventing the storage of history information in the history memory 117 until the total number of game balls discharged from the game area PA exceeds the management start reference value after the supply of operating power to the pachinko machine 10 begins, it is possible to prevent the ball entry results during such operational checks from being stored as history information.

In this configuration, where history information is not stored in the history memory 117 until the total number of game balls discharged from the game area PA after the supply of operating power to the pachinko machine 10 has started equal to or greater than the number corresponding to the management start reference value, it is not possible to calculate the management results of the game history during that period. Therefore, in such situations, the first to fourth notification display devices 201 to 204 may be configured to display a corresponding indication. For example, all display segments of each of the first to fourth notification display devices 201 to 204 may be set to illuminate. Since the display content is not shown whether it is displaying the management results of the game history or indicating that the settings of the pachinko machine 10 can be changed, it is possible to determine whether the situation described above, where history information is not stored, is occurring by checking the first to fourth notification display devices 201 to 204.

Furthermore, the configuration may differ in how the information of the management start flag in the main RAM 65 is set depending on whether or not the setting state of the pachinko machine 10 becomes changeable after the supply of operating power to the pachinko machine 10 has started. Figure 66 is a flowchart showing the main processing in this alternative configuration executed by the main CPU 63. Steps S3601 to S3609 execute the same processing as steps S101 to S109 of the main processing in the first embodiment (Figure 9), and steps S3611 to S3620 execute the same processing as steps S110 to S119 of the main processing in the first embodiment (Figure 9). On the other hand, in this alternative configuration, if an affirmative determination is made in step S3608, the management start flag in the main RAM 65 is cleared to "0" (step S3610), and after executing the processing in step S3620, the management start flag in the main RAM 65 is set to "1" (step S3621). According to this configuration, if the process for setting a new state of the pachinko machine 10 is not executed, history information is not stored in the history memory 117 until the total number of game balls dispensed from the game area PA after the start of power supply to the pachinko machine 10 exceeds the management start threshold value. If the process for setting a new state of the pachinko machine 10 is executed, history information is stored in the history memory 117 regardless of the number of game balls dispensed after the start of power supply to the pachinko machine 10. This makes it possible to manage the game history immediately after the start of power supply to the pachinko machine 10 in situations that are unlikely to trigger the operational check at the time of shipment of the pachinko machine 10.

Alternatively, instead of a configuration where history information is not stored in the history memory 117 until the total number of game balls discharged from the game area PA exceeds a management start threshold after the start of power supply to the pachinko machine 10, a separate area may be provided for storing history information until the total number of game balls exceeds a management start threshold. This makes it possible to identify the management results of the game history in that situation.

Furthermore, a condition may be added to the configuration under which history information is not stored in the history memory 117 until the total number of game balls discharged from the game area PA exceeds the management start threshold value after the start of power supply to the pachinko machine 10. This condition is: when power supply to the pachinko machine 10 is started while no history information is stored in the history memory 117. In this case, if power supply to the pachinko machine 10 is started while history information is already stored in the history memory 117, history information will be stored in the history memory 117 from the beginning, regardless of whether the total number of game balls discharged from the game area PA exceeds the management start threshold value.

Furthermore, in addition to the configuration in which history information is not stored in the history memory 117 until the total number of game balls discharged from the game area PA exceeds a management start threshold value after the start of power supply to the pachinko machine 10, or alternatively, if an abnormal condition such as a radio wave detection abnormality or vibration detection abnormality occurs, history information may not be stored in the history memory 117 until the abnormal condition is resolved. This makes it possible to prevent history information from being stored for events that occur under abnormal conditions.

Furthermore, in addition to the configuration in which history information is not stored in the history memory 117 until the total number of game balls discharged from the game area PA exceeds a management start threshold value after the start of power supply to the pachinko machine 10, or alternatively, history information may be prevented from being stored in the history memory 117 when the game machine body 12 or the front door frame 14 is open. This makes it possible to prevent history information from being stored for events that occur when the game machine body 12 or the front door frame 14 is open.

<Embodiment 15>
In this embodiment, the entity executing the process for managing the game history differs from that of the first embodiment. The configurations that differ from the first embodiment will be described below. Configurations identical to those in the first embodiment will generally not be described.

In the first embodiment described above, the MPU 62 was configured to include a management IC 66. However, in this embodiment, the MPU 62 does not have a management IC 66. Instead of a management IC 66, in this embodiment, the processing for managing the game history is executed by the main CPU 63. Furthermore, in this embodiment, the main CPU 63 executes various controls by distinguishing between specific controls and non-specific controls. Specifically, controls related to the management of the game history are considered non-specific controls, while controls other than non-specific controls, including controls for advancing the game based on the player's game operations, are considered specific controls.

Regarding specific control, all control performed by the main process (Figure 9), which is executed when the supply of operating power to the main CPU 63 begins, is included in specific control. In this embodiment, the recognition process (step S111), data output process (step S112), and setting value update signal output process (step S119) of the main process (Figure 9) in the first embodiment are not executed. Furthermore, even in this embodiment, timer interrupt processing is periodically executed by interrupting the processing in steps S113 to S116 of the main process (Figure 9). Of the various processes in this timer interrupt processing, all processes except the management process described later are included in specific control. Also, some of the management process is included in specific control.

Figure 67 is an explanatory diagram illustrating the configuration of programs and data in the main ROM 64. Corresponding to the distinction between specific and non-specific controls performed by the main CPU 63, as shown in Figure 67, the addresses of the areas where programs and data for specific controls and programs and data for non-specific controls are stored are clearly distinguished in the main ROM 64.

Specifically, the areas of consecutive addresses within the range of addresses X(1) to X(k+2) are where specific control programs are stored. Furthermore, the addresses X(k+3) to X(k+5), which are consecutive to addresses X(1) to X(k+2), are unused areas where no data is stored. Following these, the areas of consecutive addresses within the range of addresses X(k+6) to X(m+2) are where specific control data is stored. Similarly, the addresses X(m+3) to X(m+5), which are consecutive to addresses X(k+6) to X(m+2), are unused areas where no data is stored. Following these, the areas of consecutive addresses within the range of addresses X(m+6) to X(n+2) are where non-specific control programs are stored. Furthermore, addresses X(n+3) to X(n+5), which are consecutive addresses from X(m+6) to X(n+2), represent unused areas where no data is stored. Subsequently, data for non-specific control is aggregated and stored in the consecutive address areas within the range of X(n+6) to X(p+2). The relationship between the program, data, and addresses described above is established in both the physical addresses in the main ROM 64 and the logical addresses on the memory map recognized by the main CPU 63.

As described above, because the programs and data for specific control and the programs and data for non-specific control are stored in different address ranges, regardless of the execution order of the processes for executing the corresponding control, for example, when checking only the programs and data for specific control, only the address range where these programs and data are stored needs to be checked. Similarly, when checking only the programs and data for non-specific control, only the address range where these programs and data are stored needs to be checked. Therefore, it becomes possible to efficiently perform the task of checking programs and data separately for specific and non-specific control. Furthermore, it becomes possible to efficiently perform the task of modifying programs and data separately for specific and non-specific control.

By setting an address range for an unused area where no data is stored between the address range of the area where the specific control program and data for specific control are stored and the address range of the area where the non-specific control program and data for non-specific control are stored, it becomes easier to identify the boundary between the specific control address range and the non-specific control address range during the checking process.

In the address ranges for specific control and the address range for non-specific control, programs and data are stored in different address ranges, regardless of the execution order of the processes required to perform the corresponding control. This allows for efficient checking of programs and data separately. Furthermore, the presence of an unused address range between the program storage area and the data storage area makes it easier to identify the boundary between the program and data address ranges during checking.

Figure 68 is an explanatory diagram illustrating the configuration of each area in the main RAM 65. Corresponding to the distinction between specific and non-specific controls performed by the main CPU 63, as shown in Figure 68, the address ranges of the work area 221 and stack area 222 for specific controls, and the address ranges of the work area 223 and stack area 224 for non-specific controls are clearly distinguished in the main RAM 65.

Specifically, the area of each consecutive address within the range of addresses Y(1) to Y(r+2) is set as a work area 221 for specific control. Furthermore, the addresses Y(r+3) to Y(r+5), which are consecutive to addresses Y(1) to Y(r+2), are unused area addresses, and subsequently, the area of each consecutive address within the range of addresses Y(r+6) to Y(s+2) is set as a stack area 222 for specific control. Also, the addresses Y(s+3) to Y(s+5), which are consecutive to addresses Y(r+6) to Y(s+2), are unused area addresses, and subsequently, the area of each consecutive address within the range of addresses Y(s+6) to Y(t+2) is set as a work area 223 for non-specific control. Furthermore, addresses Y(t+3) to Y(t+5), which are consecutive addresses from Y(s+6) to Y(t+2), are in an unused area. Following these, the consecutive address areas within the range Y(t+6) to Y(u+2) are set as a non-specific control stack area 224. Note that the relationship between each area and address described above is set in both the physical address in the main RAM 65 and the logical address on the memory map recognized by the main CPU 63.

As described above, by distinguishing between the work area 221 for specific control and the work area 223 for non-specific control, different areas of the main RAM 65 are used when the main CPU 63 executes specific control and when it executes non-specific control, resulting in various calculations being performed in different areas. This makes it less likely that information in the main RAM 65 required for one type of control will be erased when one type of control is executed. Incidentally, load instructions are issued by the main CPU 63 when writing information to and reading information from each work area 221 and 223.

The separate stack area 222 for specific control and the stack area 224 for non-specific control ensure that different areas of the main RAM 65 are used when saving information stored in the main CPU 63's registers and when storing program return address information, depending on whether the main CPU 63 is executing specific control or non-specific control. This makes it less likely that information used in the other operation will be erased when saving information stored in the main CPU 63's registers and storing program return address information while one of the two operations is being performed. Incidentally, a push instruction is used by the main CPU 63 when writing information to each stack area 222 and 224, and a pop instruction is used by the main CPU 63 when reading information from each stack area 222 and 224. Furthermore, when reading information from each stack area 222 and 224, the information written to the stack area 222 and 224 later is read first.

Here, when the main CPU 63 executes processing corresponding to specific control, the main CPU 63 can write information to the work area 221 and the stack area 222 for specific control, and can also read information from the work area 221 and the stack area 222 for specific control. On the other hand, when the main CPU 63 executes processing corresponding to specific control, the main CPU 63 can read information from the work area 223 and the stack area 224 for non-specific control, but cannot write information to the work area 223 and the stack area 224 for non-specific control. This makes it possible to prevent accidentally erasing information used in processing corresponding to non-specific control when processing corresponding to specific control is being executed.

Furthermore, when the main CPU 63 executes processing corresponding to non-specific control, the main CPU 63 can write information to the work area 223 and stack area 224 for non-specific control, and can also read information from the work area 223 and stack area 224 for non-specific control. On the other hand, when the main CPU 63 executes processing corresponding to non-specific control, the main CPU 63 can read information from the work area 221 and stack area 222 for specific control, but cannot write information to the work area 221 and stack area 222 for specific control. This makes it possible to prevent accidentally erasing information used in processing corresponding to specific control when processing corresponding to non-specific control is being executed.

Furthermore, the main RAM 65 will receive backup power even after the pachinko machine 10's power is cut off. This backup power is supplied to all of the following areas: the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control. As a result, the information stored in these work areas 221, 222, 223, and 224 will be retained as long as backup power is supplied, even after the pachinko machine 10's power is cut off.

Next, the timer interrupt processing in this embodiment, which is executed by the main CPU 63, will be explained with reference to the flowchart in Figure 69. Similar to the first embodiment described above, the timer interrupt processing is executed periodically (for example, every 4 milliseconds) while steps S113 to S116 are being executed in the main processing (Figure 9). The program corresponding to the timer interrupt processing is set in the specific control program.

Steps S3701 to S3718 execute the same processes as steps S301 to S318 of the timer interrupt processing in the first embodiment (Figure 11). These processes are executed by the main CPU 63 using a specific control program and specific control data. Step S3719 in the timer interrupt processing executes management processing. When the management processing is executed, the program of the subroutine corresponding to the management processing set in the specific control program is executed. When the program of this subroutine is executed, information to identify the return address of the timer interrupt processing after the execution of the management processing is written to the specific control stack area 222 by a push instruction. Then, when the management processing is completed, the information to identify the return address is read by a pop instruction, and the program returns to the timer interrupt processing program indicated by that return address.

Figure 70 is a flowchart showing the management process. Note that steps S3801 to S3805 in the management process are executed by the main CPU 63 using a specific control program and specific control data.

First, to prevent the timer interrupt process (Figure 69) from occurring, the interrupt disable setting is configured (step S3801). This prevents the timer interrupt process (Figure 69), which corresponds to specific control, from being interrupted and activated during the management execution process (described later), which corresponds to non-specific control.

Subsequently, using the "PUSH PSW" instruction, the information in the flag register of the main CPU 63 is saved to the specific control stack area 222 (step S3802). The flag register includes the carry flag, zero flag, P/V flag, sign flag, and half-carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. By saving this flag register information before the program of the subroutine corresponding to the management execution process starts, it is possible to save the flag register information in the specific control stack area 222 before it changes after the subroutine is called or after the subroutine starts. The amount of information in the flag register is 1 byte.

Subsequently, the program for the subroutine corresponding to the management execution process set in the non-specific control program is read, and the management execution process is started (step S3803). In this case, information for identifying the return address of the management process after the execution of the management execution process is written to the specific control stack area 222 by a push instruction. Then, when the management execution process is completed, the information for identifying the return address is read by a pop instruction, and the program returns to the management process indicated by that return address.

After the execution of the management process, when the program returns to the management process, the "POP PSW" instruction is used to restore the information in the flag register that was saved in the specific control stack area 222 in step S3802 to the flag register of the main CPU 63 (step S3804). This restores the information in the flag register of the main CPU 63 to the information it had at the time step S3802 was executed. In other words, the information in the flag register of the main CPU 63 is restored to the information necessary to execute the specific control.

Subsequently, the interrupt enable setting is performed (step S3805) to switch from a state where timer interrupt processing (Figure 69) is prohibited to a state where it is enabled. This makes it possible to execute a new timer interrupt process.

Figure 71 is a flowchart showing the management execution process. Note that steps S3901 to S3915 in the management execution process are executed by the main CPU 63 using a program and data for non-specific control.

First, the load instruction "LD SP, Y(u+2)" sets Y(u+2) as the fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S3901). The stack pointer is an area in stack areas 222 and 224 where address information is set for the main CPU 63 to identify the memory area to be written to by the push instruction. Each time a push instruction is performed, the information in the stack pointer is updated with the address information of the next memory area to be written to, and each time a pop instruction is performed, the information in the stack pointer is updated with the address information of the previous memory area to be written to. Furthermore, when using the stack area 224 for non-specific control, the information to be stored is stored from the memory area at the last address in the stack area 224 for non-specific control, and each time information to be stored is added, the storage area to be stored is changed toward the first address in the stack area 224 for non-specific control. Therefore, in step S3901, the information of the last address in the stack area 224 for non-specific control is set in the stack pointer. This process of storing information from the last address's memory area to the first address's memory area also applies to the specific control stack area 222.

Incidentally, in both the specific control stack area 222 and the non-specific control stack area 224, if an additional push command is executed even though information has already been set in all memory areas, an error in the memory processing will occur, and all areas of the main RAM 65 will be cleared to "0". This prevents the game from continuing even if an error has occurred in the memory processing.

Subsequently, the load instruction "LD (_WABUF), WA" saves the information in the WA register of the main CPU 63 to the WA buffer set in the work area 223 for unspecified control (step S3902). Also, the load instruction "LD (_BCBUF), BC" saves the information in the BC register of the main CPU 63 to the BC buffer set in the work area 223 for unspecified control (step S3903). Also, "LD
The load instruction, "(_DEBUF), DE", saves the information in the DE register of the main CPU 63 to the DE buffer set in the work area 223 for unspecified control (step S3904). Also, the load instruction, "LD (_HLBUF), HL", saves the information in the HL register of the main CPU 63 to the HL buffer set in the work area 223 for unspecified control (step S3905). Also, the load instruction, "LD (_IXBUF), IX", saves the information in the IX register of the main CPU 63 to the IX buffer set in the work area 223 for unspecified control (step S3906). Also, the load instruction, "LD (_IYBUF), IY", saves the information in the IY register of the main CPU 63 to the IY buffer set in the work area 223 for unspecified control (step S3907).

In addition to the flag register already described, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, steps S3902 to S3907 save the information from some of these general-purpose registers, auxiliary registers, and index registers—specifically, the WA register, BC register, DE register, HL register, IX register, and IY register—to the corresponding buffers in the non-specific control work area 223. Note that the information size of each of the WA register, BC register, DE register, HL register, IX register, and IY register is 2 bytes.

The WA, BC, DE, HL, IX, and IY registers are used in the check process (step S3908), which corresponds to non-specific control. By saving the information set in these registers to the non-specific control work area 223 prior to the execution of the check process (step S3908), it becomes possible to save the information in these registers that was used during specific control before the non-specific control begins. Therefore, even if these registers are overwritten during non-specific control, when the non-specific control ends, the information saved in the non-specific control work area 223 can be restored to these registers, thereby restoring the state of these registers to the state corresponding to specific control before the non-specific control was executed.

Furthermore, instead of saving all information from various general-purpose registers, auxiliary registers, and index registers to the work area 223 for non-specific control, by selectively saving information from the WA, BC, DE, HL, IX, and IY registers—which are used in the check process corresponding to non-specific control—to the work area 223 for non-specific control, it is possible to reduce the capacity reserved in the work area 223 for saving register information. Therefore, it is possible to save the register information as described above while ensuring a large capacity in the work area 223 for non-specific control that is available during the check process. Naturally, for the various general-purpose registers, auxiliary registers, and index registers in the main CPU 63, the information set before the start of the process corresponding to non-specific control is retained until the process corresponding to specific control finishes and the process corresponding to specific control resumes.

Furthermore, by saving the register information to the non-specific control work area 223 instead of the non-specific control stack area 224, the capacity of the non-specific control stack area 224 can be kept relatively small. Also, when using the non-specific control stack area 224, as already explained, the information is written in an order that later information is read first. Therefore, if the reading order of the information is shifted due to noise or other reasons, all subsequent read information will be returned to the wrong register. The probability of such an event occurring increases as the amount of information saved to the non-specific control stack area 224 increases. In contrast, by saving the register information to the non-specific control work area 223, it is possible to prevent the above-mentioned event from occurring even when there is a large amount of information to be saved.

After executing steps S3902 to S3907, a check process is executed (step S3908). During the execution of the check process, a subroutine program corresponding to the check process, set in the non-specific control program, is executed. During the execution of this subroutine program, information to identify the return address of the management execution process after the check process is written to the non-specific control stack area 224 by a push instruction. Then, when the check process is completed, the information to identify the return address is read by a pop instruction, and the program returns to the management execution process indicated by that return address. Details of the check process will be explained later.

After the check process is executed, the load instruction "LD SP, Y(r+α)" sets Y(r+α) as the fixed address for return to specific control in the stack pointer of the main CPU 63 (step S3909). The address of Y(r+α) is set as the address between Y(r+8) and Y(s) in the stack area 222 for specific control.

At step S3803 of the management process (Figure 70), immediately before the subroutine of the management execution process is executed, the amount of information stored in the specific control stack area 222 is always constant, and accordingly, the information of the main CPU 63's stack pointer (i.e., the value of the stack pointer) at that timing is also constant. In this case, the information stored in the specific control stack area 222 includes, for example, the information of the return address of the management process (Figure 70) after the management execution process (Figure 71) has finished, and the information of the return address of the timer interrupt process (Figure 69) after the management process (Figure 70) has finished. The above constant information of the stack pointer is Y(r+α). Therefore, when the check process, which is a process corresponding to non-specific control, finishes and returns to the process corresponding to specific control, by setting the constant information Y(r+α) to the main CPU 63's stack pointer, it is possible to restore the information of the stack pointer to the information immediately before the process corresponding to non-specific control started. By setting fixed information to the stack pointer in this way, and configuring the stack pointer to revert to the information immediately before the processing corresponding to the non-specific control begins, it becomes unnecessary to save the stack pointer information of the main CPU 63 corresponding to the specific control to the main RAM 65 before starting the processing corresponding to the non-specific control. Therefore, the processing load can be reduced, and the need to allocate memory in the main RAM 65 for this saving is eliminated.

Subsequently, the load instruction "LD WA, (_WABUF)" overwrites the information saved in the WA buffer of the work area 223 for non-specific control into the WA register of the main CPU 63 (step S3910). Then, the load instruction "LD BC, (_BCBUF)" overwrites the information saved in the BC buffer of the work area 223 for non-specific control into the BC register of the main CPU 63 (step S3911). Furthermore, the load instruction "LD DE, (_DEBUF)" overwrites the information saved in the DE buffer of the work area 223 for non-specific control into the DE register of the main CPU 63 (step S3912). Finally, the load instruction "LD HL, (_HLBUF)" overwrites the information saved in the HL buffer of the work area 223 for non-specific control into the HL register of the main CPU 63 (step S3913). Furthermore, the load instruction "LD IX, (_IXBUF)" overwrites the information saved in the IX buffer of the work area 223 for non-specific control into the IX register of the main CPU 63 (step S3914). Similarly, the load instruction "LD IY, (_IYBUF)" overwrites the information saved in the IY buffer of the work area 223 for non-specific control into the IY register of the main CPU 63 (step S3915). The execution of steps S3910 to S3915 makes it possible to restore the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 to the information corresponding to specific control immediately before the processing corresponding to non-specific control begins.

Here, when processing corresponding to non-specific control is executed, the information stored in the flag register and various registers of the main CPU 63 is not saved to the main RAM 65 when processing corresponding to specific control is resumed. This eliminates the need to reserve storage areas in the work area 221 and stack area 222 for specific control to save the above information.

Furthermore, when a process corresponding to non-specific control is executed, the information stored in the flag register and various registers of the main CPU 63 is not used when the process corresponding to non-specific control is restarted after returning to the process corresponding to specific control. In other words, the information necessary for multiple execution iterations of the process corresponding to non-specific control, which is performed with the process corresponding to specific control in between, is stored in the work area 223 or stack area 224 for non-specific control, and is not stored in the flag register and various registers of the main CPU 63. Therefore, even if the information stored in the flag register and various registers of the main CPU 63 when a process corresponding to non-specific control is executed is not saved to the main RAM 65, no problems arise in executing the process corresponding to non-specific control.

Next, we will explain the check process executed when the subroutine program is called in step S3908. This check process executes the following: collecting game history information, deriving the game history management results, and reporting those management results. In other words, the processes for collecting game history information, deriving the game history management results, and reporting those management results are executed as processes corresponding to non-specific control.

Prior to explaining the check process, the contents of the various areas 231 to 234 of the non-specific control work area 223 used for managing game history will be described. Figure 72 is an explanatory diagram illustrating the various areas 231 to 234 of the non-specific control work area 223 used for managing game history.

The work area 223 for non-specific control is provided with a normal counter area 231, a counter area 232 for opening/closing execution mode, and a counter area 233 for high-frequency support mode. Each of these areas 231 to 233 is provided with general prize counters 231a, 232a, 233a, special electric prize counters 231b, 232b, 233b, first operation counters 231c, 232c, 233c, second operation counters 231d, 232d, 233d, and out counters 231e, 232e, 233e. The general prize counters 231a, 232a, 233a are counters for measuring the number of game balls that enter the general prize opening 31 from a predetermined measurement start trigger. The special electric prize entry counters 231b, 232b, and 233b are counters for measuring the number of game balls that enter the special electric prize entry device 32 from a predetermined measurement start trigger. The first operation counters 231c, 232c, and 233c are counters for measuring the number of game balls that enter the first operation opening 33 from a predetermined measurement start trigger. The second operation counters 231d, 232d, and 233d are counters for measuring the number of game balls that enter the second operation opening 34 from a predetermined measurement start trigger. The out counters 231e, 232e, and 233e are counters for measuring the number of game balls that enter the out opening 24a from a predetermined measurement start trigger.

The counters 231a to 231e in the normal counter area 231 are used to measure the number of game balls that enter the target ball entry sections 24a, 31-34 when the front door frame 14 is closed and neither the opening/closing execution mode nor the high-frequency support mode is active. The counters 232a to 232e in the opening/closing execution mode counter area 232 are used to measure the number of game balls that enter the target ball entry sections 24a, 31-34 when the front door frame 14 is closed and the machine is in opening/closing execution mode. The counters 233a to 233e in the high-frequency support mode counter area 233 are used to measure the number of game balls that enter the target ball entry sections 24a, 31-34 when the front door frame 14 is closed and the machine is in high-frequency support mode.

The reason why the situation where the front door frame 14 is open is excluded from measurement is to exclude the number of game balls that are manually inserted into the ball entry sections 24a, 31-34 when the front door frame 14 is open. However, this is not the only option, and the system may be configured to include the situation where the front door frame 14 is open in the measurement, just like the situation where the front door frame 14 is closed.

In addition to the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233, the non-specific control work area 223 is also provided with a calculation result storage area 234. The calculation result storage area 234 is an area for storing information on the game history management results calculated using the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233. The game history management result information stored in the calculation result storage area 234 is retained until new game history management result information is calculated and overwritten by the newly calculated information.

Figure 73 is a flowchart showing the check process executed when the subroutine program is called in step S3908. The processes in steps S4001 to S4008 of the check process, including the subroutine processing, are executed by the main CPU 63 using a non-specific control program and non-specific control data. When executing the subroutine, the return address information after the subroutine's execution is written to the memory area corresponding to the current stack pointer value of the main CPU 63 in the non-specific control stack area 224, and the stack pointer value is updated with the address information of the next memory area to be stored. When the subroutine processing is completed, the return address information is read from the memory area corresponding to the previous value relative to the current stack pointer value of the main CPU 63, and the program corresponding to that return address information is returned to, and the stack pointer value is updated with the address information of the memory area from which the return address information was read.

In the check process, if the front door frame 14 is in an open state (step S4001: YES), the normal ball entry management process (step S4004), the ball entry management process in the opening/closing execution mode (step S4005), and the ball entry management process in the high-frequency support mode (step S4006) are not executed, and the result calculation process (step S4007) and display process (step S4008), which will be described later, are executed. Since the game area PA is formed by the space partitioned front to back by the back surface of the window panel 52 provided on the front door frame 14 and the front surface of the game board 24, when the front door frame 14 is in an open state, the game area PA is opened forward, and even if a game ball is launched towards the game area PA in that situation, the game ball cannot flow down the game area PA normally. Furthermore, when the front door frame 14 is open, game balls may enter the ball entry sections 24a, 31-34. This occurs when the front door frame 14 is opened by the gaming hall manager for maintenance or troubleshooting, resulting in game balls entering during such work. Since such game ball entry is not considered game ball entry during normal gameplay, it does not need to be managed. Therefore, in the check process, if the front door frame 14 is open as described above, none of the processes in steps S4004 to S4006 are executed.

If the front door frame 14 is in a closed state and neither the opening/closing execution mode nor the high-frequency support mode is active (steps S4001 to S4003: NO), the normal ball entry management process is executed (step S4004). Furthermore, if the front door frame 14 is in a closed state and in the opening/closing execution mode (step S4001: NO, step S4002: YES), the ball entry management process in the opening/closing execution mode is executed (step S4005). Furthermore, if the front door frame 14 is in a closed state and in the high-frequency support mode (step S4001: NO, step S4003: YES), the ball entry management process in the high-frequency support mode is executed (step S4006).

Figure 74 is a flowchart showing the normal ball entry management process in step S4004.

If the first prize-winning slot detection sensor 42a determines that one game ball has been detected (step S4101: YES), that is, if it is confirmed that the signal received from the first prize-winning slot detection sensor 42a has switched from a LOW level to a HI level, or if the second prize-winning slot detection sensor 43a determines that one game ball has been detected (step S4103: YES), that is, if it is confirmed that the signal received from the second prize-winning slot detection sensor 43a has switched from a LOW level to a HI level, or if the third prize-winning slot detection sensor 44a determines that one game ball has been detected (step S4105: YES), that is, if it is confirmed that the signal received from the third prize-winning slot detection sensor 44a has switched from a LOW level to a HI level, then the value of the normal general prize-winning counter 231a is incremented by 1 (steps S4102, S4104, and S4106).

Furthermore, if the ball entry management process is in the opening/closing execution mode, the value of the general prize counter 232a for the opening/closing execution mode is incremented by 1 as the process corresponding to steps S4102, S4104, and S4106. If the ball entry management process is in the high-frequency support mode, the value of the general prize counter 233a for the high-frequency support mode is incremented by 1 as the process corresponding to steps S4102, S4104, and S4106. Also, in the ball entry detection process (step S3709) of the timer interrupt process (Figure 69) executed as a process corresponding to specific control, the detection results of the first to third prize slot detection sensors 42a to 44a are monitored, and if it is determined that one game ball has been detected by any of the first to third prize slot detection sensors 42a to 44a, a process is executed to dispense the number of game balls corresponding to the general prize slot 31.

If the special electric detection sensor 45a determines that one game ball has been detected (step S4107: YES), that is, if it is confirmed that the signal received from the special electric detection sensor 45a has switched from a LOW level to a HI level, the value of the normal special electric prize counter 231b is incremented by 1 (step S4108).

Furthermore, if the ball entry management process is in the opening/closing execution mode, the value of the special electric prize counter 232b for the opening/closing execution mode is incremented by 1 as the process corresponding to step S4108. If the ball entry management process is in the high-frequency support mode, the value of the special electric prize counter 233b for the high-frequency support mode is incremented by 1 as the process corresponding to step S4108. In addition, in the ball entry detection process (step S3709) of the timer interrupt process (Figure 69) executed as a process corresponding to specific control, the detection result of the special electric detection sensor 45a is monitored. If it is determined that one game ball has been detected by the special electric detection sensor 45a, a process is executed to dispense a number of game balls corresponding to the special electric prize device 32, and a process is executed to identify the trigger for the end of the round game.

If the first operation port detection sensor 46a determines that one game ball has been detected (step S4109: YES), that is, if it is confirmed that the signal received from the first operation port detection sensor 46a has switched from a LOW level to a HI level, the value of the normal first operation counter 231c is incremented by 1 (step S4110).

Furthermore, if the ball entry management process is in the opening/closing execution mode, the value of the first operation counter 232c for the opening/closing execution mode is incremented by 1 as the process corresponding to step S4110. If the ball entry management process is in the high-frequency support mode, the value of the first operation counter 233c for the high-frequency support mode is incremented by 1 as the process corresponding to step S4110. Also, in the ball entry detection process (step S3709) of the timer interrupt process (Figure 69) executed as a process corresponding to specific control, the detection result of the first operation port detection sensor 46a is monitored. If it is determined that one game ball has been detected by the first operation port detection sensor 46a, a process is executed to dispense the number of game balls corresponding to the first operation port 33, and a process is executed to identify the trigger for acquiring the hold information for special symbols.

If the second operation port detection sensor 47a determines that one game ball has been detected (step S4111: YES), that is, if it is confirmed that the signal received from the second operation port detection sensor 47a has switched from a LOW level to a HI level, the value of the normal second operation counter 231d is incremented by 1 (step S4112).

Furthermore, if the ball entry management process is in the opening/closing execution mode, the value of the second operation counter 232d for the opening/closing execution mode is incremented by 1 as the process corresponding to step S4112. If the ball entry management process is in the high-frequency support mode, the value of the second operation counter 233d for the high-frequency support mode is incremented by 1 as the process corresponding to step S4112. Also, in the ball entry detection process (step S3709) of the timer interrupt process (Figure 69) executed as a process corresponding to specific control, the detection result of the second operation port detection sensor 47a is monitored. If it is determined that one game ball has been detected by the second operation port detection sensor 47a, a process is executed to dispense the number of game balls corresponding to the second operation port 34, and a process is executed to identify the trigger for acquiring the hold information for special symbols.

If the out-port detection sensor 48a determines that one game ball has been detected (step S4113: YES), that is, if it is confirmed that the signal received from the out-port detection sensor 48a has switched from a LOW level to a HI level, the value of the normal out counter 231e is incremented by 1 (step S4114).

Furthermore, if the ball entry management process is in the opening/closing execution mode, the value of the out counter 232e for the opening/closing execution mode is incremented by 1 as the process corresponding to step S4114. If the ball entry management process is in the high-frequency support mode, the value of the out counter 233e for the high-frequency support mode is incremented by 1 as the process corresponding to step S4114. Also, in the ball entry detection process (step S3709) of the timer interrupt process (Figure 69) executed as a process corresponding to specific control, the detection result of the out exit detection sensor 48a is not monitored.

As described above, when the processing in steps S4004 to S4006 is executed, the number of game balls that enter the general prize entry port 31 is measured using the general prize entry counters 231a, 232a, and 233a, the number of game balls that enter the special electric prize entry device 32 is measured using the special electric prize entry counters 231b, 232b, and 233b, the number of game balls that enter the first operation port 33 is measured using the first operation counters 231c, 232c, and 233c, the number of game balls that enter the second operation port 34 is measured using the second operation counters 231d, 232d, and 233d, and the number of game balls that enter the out port 24a is measured using the out counters 231e, 232e, and 233e. This makes it possible for the main CPU 63 to grasp the history of game balls that enter each entry port 24a, 31 to 34. Furthermore, by providing separate counter areas for normal use (231), opening/closing execution mode (232), and high-frequency support mode (233), the main CPU (63) can distinguish between situations where neither opening/closing execution mode nor high-frequency support mode is active, situations where opening/closing execution mode is active, and situations where high-frequency support mode is active, allowing the main CPU (63) to track the ball entry history for each ball entry unit (24a, 31-34).

Returning to the explanation of the check process (Figure 73), if a positive result is obtained in step S4001, if the process in step S4004 is executed, if the process in step S4005 is executed, or if the process in step S4006 is executed, the result calculation process is executed in step S4007, and the display process is executed in step S4008.

Figure 75 is a flowchart showing the result calculation process in step S4007.

First, it is determined whether the management start flag provided in the work area 223 for non-specific control is set to "1" (step S4201). The management start flag is a flag used by the main CPU 63 to determine whether or not it is time to collect game history in order to calculate the management result of the game history. In this embodiment, when the supply of operating power to the pachinko machine 10 is started for the first time after the manufacture of the pachinko machine 10 (i.e., when the supply of operating power to the MPU 62 is started), the collection of game history in order to calculate the management result of the game history is not performed until the total number of game balls discharged from the game area PA is equal to or greater than the number corresponding to the management start reference value. The collection of game history in order to calculate the management result of the game history is performed when the total number of game balls discharged from the game area PA is equal to or greater than the number corresponding to the management start reference value. At the stage of shipment of the pachinko machine 10, the operation of the pachinko machine 10 may be checked before shipment, and at that time, game balls are placed in each ball entry section and the subsequent operation is checked. In contrast, by preventing the collection of game history data for calculating the game history management results until the total number of game balls discharged from the game area PA exceeds a management start threshold value after the start of power supply to the pachinko machine 10, it becomes possible to prevent the ball entry results during the operation check described above from being collected as game history data for calculating the game history management results.

Here, if the supply of operating power to the pachinko machine 10 is started for the first time after the manufacture of the pachinko machine 10 (i.e., when the supply of operating power to the MPU 62 is started), the value of the management start flag is "0". In this case, the values of each counter 231a to 231e in the normal counter area 231, the values of each counter 232a to 232e in the open/close execution mode counter area 232, and the values of each counter 233a to 233e in the high-frequency support mode counter area 233 are also "0". On the other hand, if the supply of operating power to the pachinko machine 10 is stopped while the value of the management start flag is "1", and then the supply of operating power to the pachinko machine 10 is started while backup power is being supplied to the main RAM 65, the value of the management start flag remains "1". In this case, the values of each counter 231a to 231e in the normal counter area 231, the values of each counter 232a to 232e in the open/close execution mode counter area 232, and the values of each counter 233a to 233e in the high-frequency support mode counter area 233 are maintained at the state before the power supply to the pachinko machine 10 was stopped. With the above configuration, if the value of the management start flag is "0", the values of each counter 231a to 231e in the normal counter area 231, the values of each counter 232a to 232e in the open/close execution mode counter area 232, and the values of each counter 233a to 233e in the high-frequency support mode counter area 233 will also be "0".

Incidentally, when the clearing process for the main RAM 65 is executed in step S105 or step S117 of the main processing (Figure 9), the clearing process targets the work area 221 and the stack area 222 for specific control, while the work area 223 and the stack area 224 for non-specific control are excluded from the clearing process. This configuration prevents the administrator of the gaming hall from intentionally clearing the work area 223 and the stack area 224 for non-specific control to "0".

Furthermore, the main CPU 63 may be configured to check whether or not an abnormality has occurred in the work area 223 and the stack area 224 for non-specific control in the timer interrupt processing (Figure 69) described later, and if an abnormality is confirmed, the work area 223 and the stack area 224 for non-specific control may be cleared to "0". This makes it possible to initialize the work area 223 and the stack area 224 for non-specific control if an abnormality occurs. In addition, in this configuration, if an abnormality occurs in the work area 223 for non-specific control, the work area 223 for non-specific control may be cleared to "0" without clearing the stack area 224 for non-specific control to "0", and if an abnormality occurs in the stack area 224 for non-specific control, the stack area 224 for non-specific control may be cleared to "0" without clearing the work area 223 for non-specific control to "0". Furthermore, even if an abnormality occurs in the work area 223 for non-specific control or the stack area 224 for non-specific control, the calculation result storage area 234 may be excluded from being cleared to "0".

If a negative determination is made in step S4201, the total number is calculated by summing the values of each counter 231a to 231e in the normal counter area 231, the values of each counter 232a to 232e in the open/close execution mode counter area 232, and the values of each counter 233a to 233e in the high-frequency support mode counter area 233 (step S4202). Then, it is determined whether the calculated total number is greater than the management start threshold value of "300" (step S4203).

If a positive determination is made in step S4203, the management start flag in the work area 223 for non-specific control is set to "1" (step S4204). Furthermore, all counters 231a to 231e in the normal counter area 231, counters 232a to 232e in the open/close execution mode counter area 232, and counters 233a to 233e in the high-frequency support mode counter area 233 are cleared to "0" (step S4205). This erases all game history information collected after the start of power supply to the pachinko machine 10 (i.e., after the start of power supply to the MPU 62) until the total number of game balls discharged from the game area PA exceeds the management start threshold. Therefore, it is possible to prevent the collection of game history for calculating the game history management result until the total number of game balls discharged from the game area PA exceeds the management start threshold after the start of power supply to the pachinko machine 10.

If a positive result is obtained in step S4201, the calculation process for the total number is performed in the same manner as in step S4202 (step S4206). Specifically, the total number is calculated by summing the values of each counter 231a to 231e in the normal counter area 231, the values of each counter 232a to 232e in the open/close execution mode counter area 232, and the values of each counter 233a to 233e in the high-frequency support mode counter area 233. Then, it is determined whether the calculated total number is greater than or equal to the calculation base number of "6000" (step S4207).

If a positive determination is made in step S4207, the calculation process for various parameters is executed (step S4208). Specifically, when the values of the various counters 231a to 231e in the normal counter area 231 are set to K61 to K65, the values of the various counters 232a to 232e in the open/close execution mode counter area 232 are set to K71 to K75, and the values of the various counters 233a to 233e in the high-frequency support mode counter area 233 are set to K81 to K85, the following 61st to 68th parameters are calculated.
Parameter 61: Total number of game balls dispensed ("K61 + K71 + K81" × "Number of prize balls for winning into general prize slot 31" + "K62 + K72 + K82" × "Number of prize balls for winning into special electric prize device 32" + "K63 + K73 + K83" × "Number of prize balls for winning into first operation slot 33" + "K64 + K74 + K84" × "Number of prize balls for winning into second operation slot 34") / Total number of game balls discharged from game area PA (K61 The ratio of +K62+K63+K64+K65+K71+K72+K73+K74+K75+K81+K82+K83+K84+K85 - Parameter 62: Total number of game balls dispensed during normal operation (K61 x "Number of prize balls for entry into general prize slot 31" + K62 x "Number of prize balls for entry into special electric prize device 32" + K63 x "Number of prize balls for entry into first operation slot 33" + K64 x "Number of prize balls for entry into second operation slot 34") )/ The ratio of the total number of game balls discharged from the skill area PA during normal operation (K61 + K62 + K63 + K64 + K65) / Parameter 63: Total number of game balls dispensed during opening/closing execution mode (K71 x "Number of prize balls for entry into general prize slot 31" + K72 x "Number of prize balls for entry into special electric prize device 32" + K73 x "Number of prize balls for entry into first operation slot 33" + K74 x "Number of prize balls for entry into second operation slot 34") / The ratio of the total number of game balls (K71 + K72 + K73 + K74 + K75) discharged from the skill area PA during opening/closing execution mode. Parameter 64: The total number of game balls dispensed during high-frequency support mode (K81 x "number of prize balls for entry into general prize slot 31" + K82 x "number of prize balls for entry into special electric prize device 32" + K83 x "number of prize balls for entry into first operation slot 33" + K84 x "number of prize balls for entry into second operation slot 34"). Number of balls) / Ratio of the total number of game balls (K81 + K82 + K83 + K84 + K85) discharged from the skill area PA during high-frequency support mode. Parameter 65: Total number of game balls entered into the general prize slot 31 (K61 + K71 + K81) / Ratio of the total number of game balls (K61 + K62 + K63 + K64 + K65 + K71 + K72 + K73 + K74 + K75 + K81 + K82 + K83 + K84 + K85) Parameter 66: The ratio of the total number of game balls that enter the first operating port 33 (K63 + K73 + K83) / the total number of game balls that are discharged from the game area PA (K61 + K62 + K63 + K64 + K65 + K71 + K72 + K73 + K74 + K75 + K81 + K82 + K83 + K84 + K85) Parameter 67: ("K62 + K72 + K82" × "Number of prize balls awarded for winning into the special electric prize device 32" + "K64 + K74 + K84" × "2 The ratio of the number of prize balls awarded for winning at the operating port 34 / the total number of game balls dispensed ("K61 + K71 + K81" × "Number of prize balls awarded for winning at the general prize port 31" + "K62 + K72 + K82" × "Number of prize balls awarded for winning at the special electric prize device 32" + "K63 + K73 + K83" × "Number of prize balls awarded for winning at the first operating port 33" + "K64 + K74 + K84" × "Number of prize balls awarded for winning at the second operating port 34") - Parameter 68: "K6 The ratio of "2 + K72 + K82" × "Number of prize balls awarded for winning into the special electric prize winning device 32" / Total number of game balls dispensed ("K61 + K71 + K81" × "Number of prize balls awarded for winning into the general prize winning opening 31" + "K62 + K72 + K82" × "Number of prize balls awarded for winning into the special electric prize winning device 32" + "K63 + K73 + K83" × "Number of prize balls awarded for winning into the first operating opening 33" + "K64 + K74 + K84" × "Number of prize balls awarded for winning into the second operating opening 34") is then calculated in step S4208 and the calculation result storage area 234 is overwritten (step S4209). In this case, the calculation result parameters 61 to 68 from the previous processing run that were already stored in the calculation result storage area 234 are erased. Furthermore, even when the power supply to the pachinko machine 10 is stopped, backup power is supplied to the main RAM 65. Therefore, if this backup power is supplied, the calculation result storage area 234 will contain information on the 61st to 68th parameters that were calculated before the power supply to the pachinko machine 10 was stopped, even immediately after the power supply to the pachinko machine 10 is started.

Subsequently, all counters 231a to 231e in the normal counter area 231, counters 232a to 232e in the open/close execution mode counter area 232, and counters 233a to 233e in the high-frequency support mode counter area 233 are cleared to "0" (step S4210). This allows the game history information to be temporarily erased at the point when parameters 61 to 68 have been calculated.

Furthermore, immediately after the management start flag is set to "1", the process in steps S4208 to S4210 may be executed if the total number of game balls discharged from the game area PA becomes equal to or greater than the calculation base number minus the management start base value. After that, the process in steps S4208 to S4210 may be executed if the total number of game balls discharged from the game area PA becomes equal to or greater than the calculation base number.

Figure 76 is a flowchart showing the display processing in step S4008 of the check process (Figure 73).

First, the value of the update timing counter provided in the work area 223 for non-specific control is decremented by 1 (step S4301). The update timing counter is a counter used by the main CPU 63 to identify that it is time to update the display content of the game history management results in the first to third notification display devices 69a to 69c. The main CPU 63 notifies the calculation results of the 61st to 68th parameters by controlling the display of the first to third notification display devices 69a to 69c. In this case, the first notification display device 69a displays information corresponding to the type of parameter to be notified. In addition, of the value obtained by multiplying the parameter to be notified by 100, the digit corresponding to the tens place is displayed in the second notification display device 69b, and the digit corresponding to the units place is displayed in the third notification display device 69c. In the first to third notification display devices 69a to 69c, the displays corresponding to the calculation results of the 61st to 68th parameters are sequentially switched according to a predetermined order. After the calculation result of the 68th parameter, which is the last parameter to be displayed, is shown, the calculation result of the 61st parameter, which is the first parameter to be displayed, is displayed. In this case, the period during which the calculation result of a single parameter is continuously displayed is 10 seconds.

Here, the calculation cycle for the 61st to 68th parameters in the main CPU 63 is at least 60 minutes. In contrast, there are eight parameters (61st to 68th), and the period during which the calculation result of a single parameter is continuously displayed is 10 seconds. Therefore, the 61st to 68th parameters calculated by the main CPU 63 are displayed at least once on the first to third notification display devices 69a to 69c.

If the process in step S4301 is executed, it is determined whether it is time to update the display content of the first to third notification display devices 69a to 69c by checking whether the value of the update timing counter after subtracting 1 is "0" (step S4302). If the determination in step S4302 is positive, the value of the display target counter provided in the non-specific control work area 223 is incremented by 1 (step S4303). Then, if the value of the display target counter after incrementing by 1 exceeds the maximum value of "7" (step S4304: YES), the value of the display target counter is cleared to "0" (step S4305).

The display target counter is a counter used by the main CPU 63 to identify the type of parameter being displayed in the first to third notification display devices 69a to 69c. There is a one-to-one correspondence between the 61st to 68th parameters and the possible values of the display target counter, ranging from "0" to "7". For example, if the value of the display target counter is "0", the first parameter to be displayed, the 61st parameter, becomes the display target for the first to third notification display devices 69a to 69c. If the value of the display target counter is "7", the last parameter to be displayed, the 68th parameter, becomes the display target for the first to third notification display devices 69a to 69c.

If a negative determination is made in step S4304, or if the process in step S4305 is executed, the first notification display device 69a is controlled to display information corresponding to the type of parameter corresponding to the value of the target counter (step S4306). Furthermore, the parameter corresponding to the value of the target counter is read from the calculation result storage area 234, and the read parameter is multiplied by 100. The digit corresponding to the tens place is displayed on the second notification display device 69b, and the digit corresponding to the units place is displayed on the third notification display device 69c (step S4307).

Here, display ICs are provided corresponding to the first to third notification display devices 69a to 69c. In step S4306, the main CPU 63 outputs display data to the display IC corresponding to the first notification display device 69a, and in step S4307, the main CPU 63 outputs display data to the display IC corresponding to the second notification display device 69b and the display IC corresponding to the third notification display device 69c. These display ICs can store and retain display data when power is supplied, and continuously display the display content corresponding to the stored display data on the corresponding notification display devices 69a to 69c. When the display data is changed by the main CPU 63, the display on the notification display devices 69a to 69c is changed to the display content corresponding to the changed display data. As a result, even after the management execution process (Figure 71), which corresponds to the non-specific control process, has finished and the system has returned to the process corresponding to the specific control process, the display corresponding to the display data set in the execution status of the non-specific control process will continue to be displayed on the first to third notification display devices 69a to 69c.

Subsequently, the update timing counter in the work area 223 for non-specific control is set to a value corresponding to 10 seconds as the value corresponding to the next update timing (step S4308).

As described above, once the display processing is executed and power is supplied to the main CPU 63, the game history management results are displayed on the first to third notification display devices 69a to 69c. This display of the game history management results is performed regardless of whether the game is continuing or not, and regardless of whether the game machine body 12 is opened from the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By performing display control on the first to third notification display devices 69a to 69c regardless of the game status or the state of the pachinko machine 10, the processing configuration for controlling the display of the first to third notification display devices 69a to 69c can be simplified.

The embodiment described in detail above provides the following excellent effects.

The main RAM 65 is provided with a work area 221 and a stack area 222 for specific control, and a work area 223 and a stack area 224 for non-specific control. The work area 221 and the stack area 222 for specific control allow for the storage and retrieval of information when processing corresponding to specific control is executed by the main CPU 63 using the specific control program and specific control data. However, when processing corresponding to non-specific control is executed by the main CPU 63 using the non-specific control program and non-specific control data, information can be read, but information cannot be stored. Similarly, the work area 223 and the stack area 224 for non-specific control allow for the storage and retrieval of information when processing corresponding to non-specific control is executed by the main CPU 63. However, when processing corresponding to specific control is executed by the main CPU 63, information can be read, but information cannot be stored. This allows the work area 221 and stack area 222 for specific control to be treated as dedicated storage areas for processing corresponding to specific control, while the work area 223 and stack area 224 for non-specific control to be treated as dedicated storage areas for processing corresponding to non-specific control. Therefore, it becomes possible to clearly differentiate the storage locations of information in the main RAM 65 for processing corresponding to specific control and processing corresponding to non-specific control. Thus, it becomes possible to prevent information used in one of the processing methods from being erased when one of the processing methods is executed.

The processing corresponding to specific control includes processing to control the progress of the game, while the processing corresponding to non-specific control includes processing to manage the game history. As described above, the work area 221 and the stack area 222 for specific control are treated as dedicated storage areas for the processing corresponding to specific control, while the work area 223 and the stack area 224 for non-specific control are treated as dedicated storage areas for the processing corresponding to non-specific control. This makes it possible to prevent the information used in the processing for managing the game history—for example, the information stored in the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, and the calculation result storage area 234—from being overwritten when the processing for controlling the progress of the game is executed.

The main RAM 65 is equipped with a normal counter area 231 for storing information for managing game history, a counter area 232 for the open/close execution mode, a counter area 233 for the high-frequency support mode, and a calculation result storage area 234. This allows the main CPU 63 to complete the processing for managing game history. Furthermore, it prevents unauthorized access to or modification of game history information and information on various parameters calculated using that game history information.

When the system transitions from executing a process corresponding to a specific control to executing a process corresponding to a non-specific control, or when the system is already executing a process corresponding to a non-specific control, the information in the various registers of the main CPU 63 is saved to the main RAM 65. This prevents the information stored in the main CPU 63's registers from being overwritten when the process corresponding to the specific control is executed. Furthermore, when the process corresponding to the non-specific control is completed, or after completion, the information saved in the main RAM 65 is restored to the main CPU 63's registers. This allows the system to execute the process corresponding to the specific control from the state of the main CPU 63's registers before the execution of the process corresponding to the non-specific control.

When the system transitions from executing a process corresponding to a specific control to executing a process corresponding to a non-specific control, or when the system is already executing a process corresponding to a non-specific control, information from some of the registers of the main CPU 63 is saved to the main RAM 65. This reduces the amount of memory required in the main RAM 65 to save the information from the main CPU 63's registers.

When the system transitions from executing a process corresponding to a specific control to executing a process corresponding to a non-specific control, or when the system is already executing a process corresponding to a non-specific control, the information of the registers in the main CPU 63 that are used for information storage in the process corresponding to the non-specific control is saved to the main RAM 65. This allows the system to resume the process corresponding to the specific control from the state of the main CPU 63's registers before the execution of the non-specific control process, while simultaneously reducing the storage capacity required in the main RAM 65 to save the information of the main CPU 63's registers.

When processing corresponding to non-specific control is initiated, the information in the flag register of the main CPU 63 is saved to the specific control stack area 222 during the processing corresponding to specific control, and the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the non-specific control work area 223 during the processing corresponding to non-specific control. This makes it possible to save the information stored in the various registers of the main CPU 63 at a favorable timing, and also allows for the distribution of the information saving process between the processing corresponding to specific control and the processing corresponding to non-specific control.

The flag register includes the carry flag, zero flag, P/V flag, sign flag, and half-carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. In this case, the information in the flag register is saved to the specific control stack area 222 by the specific control processing before the processing corresponding to non-specific control begins. This makes it possible to save the flag register information in the specific control stack area 222 before it changes after the call of the subroutine corresponding to non-specific control or after the start of the said subroutine.

By saving the information of the WA, BC, DE, HL, IX, and IY registers to the non-specific control work area 223 instead of the non-specific control stack area 224, the capacity of the non-specific control stack area 224 can be significantly reduced. Furthermore, when using the non-specific control stack area 224, the information is read in reverse order of write order. Therefore, if the read order is disrupted due to noise or other reasons, all subsequent read information will be returned to the wrong register. The probability of this occurring increases as the amount of information saved to the non-specific control stack area 224 increases. In contrast, by saving the register information to the non-specific control work area 223, it is possible to prevent the above-mentioned issue from occurring even when there is a large amount of information to be saved.

In this configuration, when the system transitions from executing a process corresponding to a specific control to executing a process corresponding to a non-specific control, or when the system begins executing a process corresponding to a non-specific control, the stack pointer information of the main CPU 63 becomes fixed. This stack pointer information is not saved to the main RAM 65 when the process corresponding to the non-specific control begins. As a result, there is no need to allocate capacity in the main RAM 65 to save the stack pointer information, thus reducing the storage capacity of the main RAM 65. Furthermore, even with this configuration where the stack pointer information is not saved, when the system transitions from executing a process corresponding to a specific control to executing a process corresponding to a non-specific control, or when the system begins executing a process corresponding to a non-specific control, the stack pointer information of the main CPU 63 becomes fixed. Therefore, even without saving the stack pointer information as described above, when the process corresponding to the non-specific control finishes, it is possible to restore the stack pointer information to what it was before the process corresponding to the non-specific control began.

Furthermore, while the configuration is such that the information in the flag register of the main CPU 63 is saved to the main RAM 65 during the process corresponding to the specific control when a process corresponding to non-specific control is executed, this is not limited to this configuration. The information in the flag register may also be saved to the main RAM 65 during the process corresponding to the non-specific control. Also, while the configuration is such that the information in the flag register of the main CPU 63 is restored during the process corresponding to the specific control after the process corresponding to the non-specific control has finished, this is not limited to this configuration. The information in the flag register may also be restored during the process corresponding to the non-specific control.

Furthermore, while the configuration is such that the information in the WA, BC, DE, HL, IX, and IY registers of the main CPU 63 is saved to the main RAM 65 after the processing corresponding to the non-specific control has started, this configuration is not limited to this, and the information in these registers may be saved to the main RAM 65 during the processing corresponding to the specific control. Also, while the configuration is such that the information in each of the above registers is restored during the processing corresponding to the non-specific control when the processing corresponding to the non-specific control finishes, this configuration is not limited to this, and the information in each of the above registers may be restored during the processing corresponding to the specific control after the processing corresponding to the non-specific control has finished.

<Embodiment 16>
In this embodiment, the processing configuration for the management process differs from that of the 15th embodiment described above. The configurations that differ from those of the 15th embodiment will be described below. Configurations that are identical to those of the 15th embodiment will generally not be described.

Figure 77 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that steps S4401 to S4405 in the management process are executed by the main CPU 63 using a specific control program and specific control data.

First, to prevent the timer interrupt process (Figure 69) from occurring, the interrupt disable setting is configured (step S4401). This prevents the timer interrupt process (Figure 69), which corresponds to specific control, from being interrupted and activated during the management execution process (described later), which corresponds to non-specific control.

Subsequently, the load instruction "LD (_PSWBUF), PSW" saves the information in the flag register of the main CPU 63 to the PSW buffer set in the work area 221 for specific control (step S4402). The flag register includes the carry flag, zero flag, P/V flag, sign flag, and half-carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotation instructions, and input/output instructions. By saving this flag register information before the program of the subroutine corresponding to the management execution process starts, it is possible to save the flag register information in the work area 221 for specific control before it changes during the subroutine call or after the subroutine starts.

Subsequently, the program for the subroutine corresponding to the management execution process set in the non-specific control program is read, and the management execution process is started (step S4403). In this case, information for identifying the return address of the management process after the execution of the management execution process is written to the specific control stack area 222 by a push instruction. Then, when the management execution process finishes, the information for identifying the return address is read by a pop instruction, and the program returns to the management process indicated by that return address.

After the management execution process is completed and the program returns to the management process, the load instruction "LD PSW, (_PSWBUF)" is used to restore the information in the flag register that was saved in the PSW buffer in the work area 221 for specific control in step S4402 back to the flag register of the main CPU 63 (step S4404). This restores the information in the flag register of the main CPU 63 to the information it had when step S4402 was last executed. In other words, the information in the flag register of the main CPU 63 is restored to the information necessary for executing the specific control.

Subsequently, the interrupt enable setting is performed (step S4405) to switch from a state where timer interrupt processing (Figure 69) is prohibited to a state where it is enabled. This makes it possible to execute a new timer interrupt process.

According to the above configuration, the information in the flag register of the main CPU 63 immediately before switching from specific control to non-specific control is saved to the work area 221 for specific control, rather than the stack area 222 for specific control. This makes it possible to save the flag register information while reducing the capacity of the stack area 222 for specific control.

Furthermore, while the PSW buffer in the work area 221 for specific control is reserved as a dedicated area, it is not limited to this, and it may be configured as a shared area where other information can also be written. In other words, since there is no need to save the flag register information of the main CPU 63 corresponding to the specific control when the management process is not executed, a configuration may be used that utilizes a shared area that also functions as a PSW buffer when a predetermined arithmetic process is executed in the process corresponding to the specific control when the management process is not executed. In this case, since the shared area will be reliably used to save the flag register information when the management process is executed, it is necessary to configure the system so that information other than the flag register information, which becomes unnecessary before the management process is executed, is written to the shared area.

<Embodiment 17>
In this embodiment, the processing configuration of the management execution process differs from that of the 15th embodiment described above. The configuration that differs from that of the 15th embodiment will be described below. Configurations that are the same as those of the 15th embodiment will generally not be described.

Figure 78 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S4501 to S4515 of the management execution process are executed by the main CPU 63 using a program and data for non-specific control.

First, similar to step S3901 of the management execution process in the 15th embodiment described above (Figure 71), the load instruction "LD SP, Y(u+2)" sets Y(u+2) as the fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S4501).

Subsequently, using the "PUSH WA" instruction, the information in the WA register of the main CPU 63 is saved to a memory area corresponding to the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 (step S4502). In this case, the information in the WA register is saved to a memory area corresponding to the fixed address set for the main CPU 63's stack pointer in step S4501. Furthermore, the information in the main CPU 63's stack pointer is updated to the address information of the memory area to be written to in the next order.

Subsequently, using the "PUSH BC" instruction, the information in the BC register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 (step S4503). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area to be written to in the next order.

Subsequently, using the "PUSH DE" instruction, the information in the DE register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 (step S4504). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area to be written to in the next order.

Subsequently, using the "PUSH HL" instruction, the information in the HL register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 (step S4505). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area to be written to in the next order.

Subsequently, using the "PUSH IX" instruction, the information in the IX register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 (step S4506). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area to be written to in the next order.

Subsequently, using the "PUSH IY" instruction, the information in the IY register of the main CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63 (step S4507). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area to be written to in the next order.

After executing steps S4502 to S4507, a check process is executed (step S4508). During the execution of the check process, a subroutine program corresponding to the check process, set in the non-specific control program, is executed. During the execution of this subroutine program, information for identifying the return address of the management execution process after the check process is written to a memory area corresponding to the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 using a push instruction. Then, when the check process is completed, the information for identifying the return address is read using a pop instruction, and the program returns to the management execution process indicated by that return address. The content of the check process is the same as in the 15th embodiment described above.

Subsequently, similar to step S3909 of the management execution process in the 15th embodiment (Figure 71), a load instruction, "LD SP, Y(r+α)", is used to set Y(r+α) as the fixed address for return to specific control in the stack pointer of the main CPU 63 (step S4509). The address of Y(r+α) is set as the address between Y(r+8) and Y(s) in the stack area 222 for specific control.

Subsequently, using the "POP IY" instruction, the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 is overwritten in the IY register of the main CPU 63 with the information saved in the memory area corresponding to the previous sequence of information (step S4510). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area targeted for writing in the previous sequence.

Subsequently, using the "POP IX" instruction, the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 is overwritten in the IX register of the main CPU 63 with the information saved in the memory area corresponding to the previous sequence of information (step S4511). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area targeted for writing in the previous sequence.

Subsequently, using the "POP HL" instruction, the HL register of the main CPU 63 overwrites the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 with the information saved in the memory area corresponding to the previous sequence of information (step S4512). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area targeted for writing in the previous sequence.

Subsequently, using the "POP DE" instruction, the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 is overwritten in the DE register of the main CPU 63 with the information saved in the memory area corresponding to the previous sequence of information (step S4513). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area targeted for writing in the previous sequence.

Subsequently, using the "POP BC" instruction, the BC register of the main CPU 63 overwrites the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 with the information saved in the memory area corresponding to the previous sequence of information (step S4514). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area targeted for writing in the previous sequence.

Subsequently, using the "POP WA" instruction, the current stack pointer information of the main CPU 63 in the non-specific control stack area 224 is overwritten in the WA register of the main CPU 63 with the information saved in the memory area corresponding to the previous sequence of information (step S4515). Furthermore, the stack pointer information of the main CPU 63 is updated with the address information of the memory area targeted for writing in the previous sequence.

The execution of steps S4510 to S4515 makes it possible to restore the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 to the information corresponding to the specific control immediately before the start of the processing corresponding to the non-specific control.

In addition to the flag register, the main CPU 63 has various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S4502 to S4507, the information of some of these general-purpose registers, auxiliary registers, and index registers, namely the WA register, BC register, DE register, HL register, IX register, and IY register, is saved to the stack area 224 for non-specific control. These WA register, BC register, DE register, HL register, IX register, and IY register are registers used in the check process (step S4508), which is a process corresponding to non-specific control. By saving the information set in such registers to the stack area 224 for non-specific control prior to the execution of the check process (step S4508), it becomes possible to save the information of these registers that were used during specific control before non-specific control begins. Therefore, even if these registers are overwritten during non-specific control, when the non-specific control is terminated, the information saved in the non-specific control stack area 224 is restored to these registers, thereby restoring the state of these registers to the state corresponding to the specific control before the non-specific control was executed.

Furthermore, instead of saving all information from various general-purpose registers, auxiliary registers, and index registers to the non-specific control stack area 224, selectively saving information from the WA, BC, DE, HL, IX, and IY registers—which are used in the check process corresponding to non-specific control—to the non-specific control stack area 224 reduces the capacity required to save register information in the non-specific control stack area 224. Therefore, it becomes possible to save register information in the manner described above while ensuring a large capacity in the non-specific control stack area 224 available for use during the check process.

<Embodiment 18>
In this embodiment, the processing configuration of the management execution process differs from that of the 15th embodiment described above. The configuration that differs from that of the 15th embodiment will be described below. Configurations that are the same as those of the 15th embodiment will generally not be described.

Figure 79 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S4601 to S4605 in the management execution process are executed by the main CPU 63 using a program and data for non-specific control.

First, similar to step S3901 of the management execution process in the 15th embodiment described above (Figure 71), the load instruction "LD SP, Y(u+2)" sets Y(u+2) as the fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S4601).

Subsequently, the load instruction "LD (_ALLBUF), ALL" saves the information of all registers of the main CPU 63 to the ALL buffer set in the work area 223 for non-specific control (step S4602). This ensures that information from all registers, including not only the WA, BC, DE, HL, IX, and IY registers used in the check process (which corresponds to non-specific control), but also other registers, is saved together to the ALL buffer in the work area 223 for non-specific control. By saving all registers of the main CPU 63 to the work area 223 for non-specific control in this way, the need to selectively save the information of the main CPU 63's registers is eliminated.

Here, the registers to be saved include the flag register. While the flag register information is saved to the specific control stack area 222 in step S3802 of the management process (Figure 70), in step S4602, the flag register information is saved to the non-specific control work area 223. This eliminates the need to selectively save the register information of the main CPU 63, including the flag register information. Furthermore, even if the flag register information is saved redundantly in this way, after the completion of the management execution process, the information is restored from the specific control stack area 222 to the flag register of the main CPU 63 in step S3804 of the management process (Figure 70). Therefore, when returning to the process corresponding to specific control, it is possible to restore the flag register information of the main CPU 63 to the state it was in immediately before the management execution process was executed.

Subsequently, a check process is executed (step S4603). During the execution of the check process, the program of the subroutine corresponding to the check process, which is set in the non-specific control program, is executed. During the execution of this subroutine, information for identifying the return address of the management execution process after the check process is written by a push instruction to the memory area corresponding to the current stack pointer information of the main CPU 63 in the non-specific control stack area 224. Then, when the check process is completed, the information for identifying the return address is read by a pop instruction, and the program returns to the management execution process indicated by that return address. The content of the check process is the same as in the 15th embodiment described above.

Subsequently, similar to step S3909 of the management execution process in the 15th embodiment (Figure 71), a load instruction, "LD SP, Y(r+α)", is used to set Y(r+α) as the fixed address for return to specific control in the stack pointer of the main CPU 63 (step S4604). The address of Y(r+α) is set as the address between Y(r+8) and Y(s) in the stack area 222 for specific control.

Subsequently, the load instruction "LD ALL, (_ALLBUF)" overwrites the corresponding registers in the main CPU 63 with the information saved in the ALL buffer of the work area 223 for non-specific control (step S4605). This makes it possible to restore the information in all registers of the main CPU 63 to the information corresponding to the specific control immediately before the processing corresponding to the non-specific control begins.

According to the above configuration, by saving the register information of the main CPU 63 to the work area 223 for non-specific control, rather than to the stack area 224 for non-specific control, the capacity of the stack area 224 for non-specific control can be kept relatively small. Furthermore, when using the stack area 224 for non-specific control, the information is read in reverse order of write order. Therefore, if the reading order of information is disrupted due to noise or other reasons, all subsequent read information will be returned to the wrong registers. The probability of such an event occurring increases as the amount of information saved to the stack area 224 for non-specific control increases. In contrast, by saving the register information to the work area 223 for non-specific control, it is possible to prevent such an event from occurring even when there is a large amount of information to be saved.

Furthermore, when saving the register information of the main CPU 63 to the work area 223 for non-specific control, not only the WA, BC, DE, HL, IX, and IY registers used in the check process, which is a process corresponding to non-specific control, but also all other registers, will have their information saved together to the ALL buffer of the work area 223 for non-specific control. By saving all the registers of the main CPU 63 to the work area 223 for non-specific control in this way, the need to selectively save the register information of the main CPU 63 becomes unnecessary.

Furthermore, while the configuration is such that the information of all registers in the main CPU 63 is saved to the main RAM 65 during the process corresponding to the non-specific control after the process corresponding to the non-specific control has started, this is not limited to this configuration. The information of all registers may also be saved to the main RAM 65 during the process corresponding to the specific control. Also, while the configuration is such that the information is restored to all registers during the process corresponding to the non-specific control when the process corresponding to the non-specific control finishes, this is not limited to this configuration. The information is also to be restored to all registers during the process corresponding to the specific control after the process corresponding to the non-specific control has finished.

<19th Embodiment>
In this embodiment, the processing configuration of the management execution process differs from that of the 15th embodiment described above. The configuration that differs from that of the 15th embodiment will be described below. Configurations that are the same as those of the 15th embodiment will generally not be described.

Figure 80 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S4701 to S4706 in the management execution process are executed by the main CPU 63 using a program and data for non-specific control.

First, the load instruction "LD (_SPBUF), SP" saves the stack pointer information of the main CPU 63 to the SP buffer set in the work area 223 for non-specific control (step S4701). This ensures that the stack pointer information corresponding to the specific control immediately before the processing corresponding to the non-specific control begins is saved in the work area 223 for non-specific control.

Subsequently, similar to step S3901 of the management execution process in the 15th embodiment (Figure 71), the load instruction "LD SP, Y(u+2)" sets Y(u+2) as the fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S4702).

Subsequently, using the "PUSH ALL" instruction, the information of all registers of the main CPU 63 is saved to the storage area corresponding to the current stack pointer information of the main CPU 63 in the non-specific control stack area 224, and to storage areas adjacent to that storage area (step S4703). In this case, since it is not possible to store the information of all registers of the main CPU 63 in a single storage area in the non-specific control stack area 224, the storage area corresponding to the current stack pointer information of the main CPU 63 in the non-specific control stack area 224, and storage areas adjacent to that storage area, are used as the destinations for saving the register information, as described above. Furthermore, when saving the information of all registers, the information of the main CPU 63's stack pointer is updated in the storage area where the last information was stored to reflect the address of the next storage area to be written to.

Subsequently, a check process is executed (step S4704). During the execution of the check process, the program of the subroutine corresponding to the check process, which is set in the non-specific control program, is executed. During the execution of this subroutine, information for identifying the return address of the management execution process after the check process is written by a push instruction to the memory area corresponding to the current stack pointer information of the main CPU 63 in the non-specific control stack area 224. Then, when the check process is completed, the information for identifying the return address is read by a pop instruction, and the program returns to the management execution process indicated by that return address. The content of the check process is the same as in the 15th embodiment described above.

Subsequently, using the "POP ALL" instruction, the current stack pointer information of the main CPU 63 in the stack area 224 for non-specific control is overwritten in the corresponding registers of the main CPU 63, including the information saved in the storage area and the storage area adjacent to that storage area (step S4705). This makes it possible to restore the information in all registers of the main CPU 63 to the information corresponding to the specific control immediately before the processing corresponding to the non-specific control begins.

Subsequently, the load instruction "LD SP, (_SPBUF)" overwrites the information saved in the SP buffer of the work area 223 for non-specific control with the stack pointer of the main CPU 63 (step S4706). This restores the information in the main CPU 63's stack pointer to the information corresponding to the specific control immediately before the processing corresponding to the non-specific control began.

According to the above configuration, when saving the register information of the main CPU 63 to the non-specific control stack area 224, not only the WA, BC, DE, HL, IX, and IY registers used in the check process, which is a process corresponding to non-specific control, but also all other registers, will have their information saved together to the non-specific control stack area 224. By saving all the registers of the main CPU 63 to the non-specific control stack area 224 in this way, there is no need to selectively save the register information of the main CPU 63.

The stack pointer information corresponding to the specific control, immediately before the processing corresponding to the non-specific control begins, is saved to the work area 223 for the non-specific control. This allows the stack pointer information corresponding to the specific control to change even if the configuration allows it to change immediately before the processing corresponding to the non-specific control begins. When the processing corresponding to the non-specific control finishes and returns to the processing corresponding to the specific control, the stack pointer information of the main CPU 63 can be restored to the information corresponding to the specific control immediately before the processing corresponding to the non-specific control began.

Furthermore, while the configuration is such that the information of all registers in the main CPU 63 is saved to the main RAM 65 during the process corresponding to the non-specific control after the process corresponding to the non-specific control has started, this is not limited to this configuration. The information of all registers may also be saved to the main RAM 65 during the process corresponding to the specific control. Also, while the configuration is such that the information is restored to all registers during the process corresponding to the non-specific control when the process corresponding to the non-specific control finishes, this is not limited to this configuration. The information is also to be restored to all registers during the process corresponding to the specific control after the process corresponding to the non-specific control has finished.

<20th Embodiment>
In this embodiment, the processing configuration of the management processing and the management execution processing differs from that of the 15th embodiment described above. The configurations that differ from those of the 15th embodiment will be described below. Configurations that are the same as those of the 15th embodiment will generally not be described.

Figure 81 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that steps S4801 to S4811 of the management process are executed by the main CPU 63 using a specific control program and specific control data.

First, to prevent the timer interrupt process (Figure 69) from occurring, the interrupt disable setting is configured (step S4801). This prevents the timer interrupt process (Figure 69), which corresponds to specific control, from being interrupted and activated during the management execution process (described later), which corresponds to non-specific control.

Subsequently, using the "PUSH PSW" instruction, the information in the flag register of the main CPU 63 is saved to the specific control stack area 222 (step S4802). The flag register includes the carry flag, zero flag, P/V flag, sign flag, and half-carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotation instructions, and input/output instructions. By saving this flag register information before the program of the subroutine corresponding to the management execution process starts, it is possible to save the flag register information in the specific control stack area 222 before it changes during the subroutine call or after the subroutine starts.

Subsequently, the WA register of the main CPU 63 is cleared to "0" by the load instruction "LD WA, 0" (step S4803). Then, the BC register of the main CPU 63 is cleared to "0" by the load instruction "LD BC, 0" (step S4804). Furthermore, the DE register of the main CPU 63 is cleared to "0" by the load instruction "LD DE, 0" (step S4805). Furthermore, the HL register of the main CPU 63 is cleared to "0" by the load instruction "LD HL, 0" (step S4806). Furthermore, the IX register of the main CPU 63 is cleared to "0" by the load instruction "LD IX, 0" (step S4807). Finally, the IY register of the main CPU 63 is cleared to "0" by the load instruction "LD IY, 0" (step S4808).

The main CPU 63 has various general-purpose registers, auxiliary registers, and index registers in addition to the flag register. In this case, steps S4803 to S4808 clear some of these general-purpose registers, auxiliary registers, and index registers—specifically, the WA register, BC register, DE register, HL register, IX register, and IY register—to "0". These WA, BC, DE, HL, IX, and IY registers are used in the check process (step S4902), which is a process corresponding to non-specific control. By clearing these registers to "0" prior to the execution of the management execution process (step S4809), which is a process corresponding to non-specific control, it is possible to return the state of these registers to the state immediately after the power supply to the main CPU 63 begins, before the process corresponding to non-specific control starts.

Furthermore, the information in the WA, BC, DE, HL, IX, and IY registers before the start of processing corresponding to non-specific control is unnecessary for processing corresponding to specific control after the processing corresponding to the non-specific control has finished. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will arise in the processing corresponding to specific control that resumes after the processing corresponding to non-specific control has finished.

After executing steps S4803 to S4808, the program for the subroutine corresponding to the management execution process set in the non-specific control program is read, and the management execution process is started (step S4809). In this case, information for identifying the return address of the management process after the execution of the management execution process is written to the specific control stack area 222 by a push instruction. Then, when the management execution process finishes, the information for identifying the return address is read by a pop instruction, and the program returns to the management process indicated by that return address.

When the program returns to the management processing program after the execution of the management execution process, the "POP PSW" instruction restores the information in the flag register that was saved in the specific control stack area 222 in step S4802 back to the flag register of the main CPU 63 (step S4810). This restores the information in the flag register of the main CPU 63 to the information it had when step S4802 was last executed. In other words, the information in the flag register of the main CPU 63 is restored to the information necessary to execute the specific control.

Subsequently, the interrupt enable setting is performed (step S4811) to switch from a state where timer interrupt processing (Figure 69) is prohibited to a state where it is enabled. This makes it possible to execute a new timer interrupt process.

Figure 82 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S4901 to S4909 in the management execution process are executed by the main CPU 63 using a program and data for non-specific control.

First, similar to step S3901 of the management execution process in the 15th embodiment described above (Figure 71), the load instruction "LD SP, Y(u+2)" sets Y(u+2) as the fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S4901).

Subsequently, a check process is executed (step S4902). During the execution of the check process, a subroutine program corresponding to the check process, which is set in the non-specific control program, is executed. During the execution of this subroutine program, information for identifying the return address of the management execution process after the check process is written to the non-specific control stack area 224 by a push instruction. Then, when the check process is completed, the information for identifying the return address is read out by a pop instruction, and the program returns to the management execution process indicated by that return address. The content of the check process is the same as in the 15th embodiment described above.

Subsequently, the WA register of the main CPU 63 is cleared to "0" by the load instruction "LD WA, 0" (step S4903). Then, the BC register of the main CPU 63 is cleared to "0" by the load instruction "LD BC, 0" (step S4904). Furthermore, the DE register of the main CPU 63 is cleared to "0" by the load instruction "LD DE, 0" (step S4905). Also, the HL register of the main CPU 63 is cleared to "0" by the load instruction "LD HL, 0" (step S4906). Furthermore, the IX register of the main CPU 63 is cleared to "0" by the load instruction "LD IX, 0" (step S4907). Finally, the IY register of the main CPU 63 is cleared to "0" by the load instruction "LD IY, 0" (step S4908).

As previously explained, the WA, BC, DE, HL, IX, and IY registers are used in the check process (step S4902), which is a process corresponding to non-specific control. By clearing these registers to "0" prior to returning from the non-specific control process to the specific control process, it becomes possible to return the state of these registers to the state immediately after the power supply to the main CPU 63 begins, before returning to the specific control process.

Furthermore, the information in the WA, BC, DE, HL, IX, and IY registers before the start of the processing corresponding to the specific control is unnecessary for the processing corresponding to the non-specific control after the processing corresponding to the specific control has finished. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will arise in the processing corresponding to the non-specific control that resumes after the processing corresponding to the specific control has finished.

Subsequently, similar to step S3909 of the management execution process in the 15th embodiment (Figure 71), a load instruction, "LD SP, Y(r+α)", is used to set Y(r+α) as the fixed address for return to specific control in the stack pointer of the main CPU 63 (step S4909). The address of Y(r+α) is set as the address between Y(r+8) and Y(s) in the stack area 222 for specific control.

According to the above configuration, when processing corresponding to a specific control is initiated from a situation where processing corresponding to a specific control is being executed, the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 are cleared to "0". This eliminates the need to save the information in each of these registers to the main RAM 65. Therefore, there is no need to allocate capacity for saving this information.

Furthermore, when returning to a process corresponding to a specific control from a state where a process corresponding to a non-specific control is being executed, the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 are cleared to "0". This makes it possible to restore the state of each of these registers to the state immediately before the non-specific control process began when returning to a process corresponding to a specific control.

The state in which each of the above registers is cleared to "0" is the state when power supply to the MPU 62 is started. This simplifies the processing configuration for setting each of the above registers to a predetermined state when starting processing corresponding to non-specific control and when returning to processing corresponding to specific control.

When starting a process corresponding to non-specific control and when returning to a process corresponding to specific control, the registers subject to "0" clearing are a subset of the various registers of the main CPU 63. This reduces the processing load required to set each of these registers to a predetermined state when starting a process corresponding to non-specific control and when returning to a process corresponding to specific control.

In a configuration where the WA, BC, DE, HL, IX, and IY registers are cleared to "0" when starting a process corresponding to non-specific control and when returning to a process corresponding to specific control, other registers are not cleared to "0". This prevents the erasure of information necessary for the process corresponding to specific control when starting a process corresponding to non-specific control.

Furthermore, information from registers other than the WA, BC, DE, HL, IX, and IY registers is not saved to the main RAM 65 when processing corresponding to non-specific control begins. This eliminates the need to allocate memory in the main RAM 65 for saving this information.

The information in the WA, BC, DE, HL, IX, and IY registers of the main CPU 63 before the start of processing corresponding to non-specific control is information that is not used in processing corresponding to specific control after the processing corresponding to non-specific control has finished. This ensures that even if the above registers are cleared to "0" when processing corresponding to non-specific control begins, it does not affect the processing corresponding to specific control after the processing corresponding to non-specific control has finished.

Furthermore, instead of clearing the WA, BC, DE, HL, IX, and IY registers of the main CPU 63 to "0" in steps S4803 to S4808 of the management process (Figure 81), these registers may be initialized instead. That is, when power supply to the MPU 62 begins, these registers of the main CPU 63 are initially cleared to "0," and then their information is set to their initial state. Steps S4803 to S4808 may be configured to set each register to this initial state. In this case, by configuring steps S4903 to S4908 to also set each register to the initial state, it becomes possible to restore the state of these registers to the state immediately before the start of the non-specific control process when returning to the process corresponding to a specific control.

Furthermore, instead of clearing the WA, BC, DE, HL, IX, and IY registers of the main CPU 63 to "0" in steps S4803 to S4808 of the management process (Figure 81), it is also possible to set all of these registers to "1". In this case, by setting all of the above registers to "1" in steps S4903 to S4908, it becomes possible to restore the state of these registers to the state immediately before the start of the process corresponding to the non-specific control when returning to the process corresponding to the specific control.

Furthermore, while the configuration is such that the information in the flag register of the main CPU 63 is saved to the main RAM 65 during the process corresponding to the specific control when a process corresponding to non-specific control is executed, the configuration is not limited to this, and the information in the flag register may be saved to the main RAM 65 during the process corresponding to the non-specific control. Also, while the configuration is such that the information in the flag register of the main CPU 63 is restored during the process corresponding to the specific control after the process corresponding to the non-specific control has finished, the configuration is not limited to this, and the information in the flag register may be restored during the process corresponding to the non-specific control.

Furthermore, while the configuration is such that the process of clearing the WA, BC, DE, HL, IX, and IY registers of the main CPU 63 to "0" is performed in the process corresponding to the specific control before the process corresponding to the non-specific control begins, this configuration is not limited to this, and the process of clearing these registers to "0" may also be performed in the process corresponding to the non-specific control. Also, while the configuration is such that the process of clearing each of the above registers to "0" when the process corresponding to the non-specific control ends is performed in the process corresponding to the non-specific control, this configuration is not limited to this, and the process of clearing each of the above registers to "0" may also be performed in the process corresponding to the specific control after the process corresponding to the non-specific control has finished.

Furthermore, in the management process (Figure 81), the "PUSH PSW" process in step S4802 is executed before setting each register to "0" in steps S4803 to S4808. Alternatively, the "PUSH PSW" process in step S4802 may be executed after setting each register to "0" in steps S4803 to S4808, but before the program for the subroutine corresponding to the management execution process is read in step S4809. This makes it possible to save the information in the flag registers after they have been changed by the load instructions in steps S4803 to S4808 to the specific control stack area 222.

<Embodiment 21>
In this embodiment, the configuration for collecting game history information differs from that of the 15th embodiment. The configuration that differs from that of the 15th embodiment will be described below. Configurations that are the same as those in the 15th embodiment will generally not be described.

Figure 83 is an explanatory diagram illustrating the electrical configuration in this embodiment.

The MPU 62 is equipped with a main CPU 63, main ROM 64, and main RAM 65, similar to the 15th embodiment described above. However, unlike the 15th embodiment, the MPU 62 also has a management RAM 241 electrically connected to it. In other words, the management RAM 241 is provided separately from the main RAM 65 built into the MPU 62, and this management RAM 241 is externally connected to the MPU 62.

The main RAM 65 is provided with a work area 221 for specific control, a stack area 222 for specific control, a work area 223 for non-specific control, and a stack area 224 for non-specific control, similar to the 15th embodiment described above. Therefore, when the main CPU 63 executes processing corresponding to specific control using the specific control program and data in the main ROM 64, it utilizes the specific control work area 221 and the specific control stack area 222 in the main RAM 65. When the main CPU 63 executes processing corresponding to non-specific control using the non-specific control program and data in the main ROM 64, it utilizes the non-specific control work area 223 and the non-specific control stack area 224 in the main RAM 65.

The management RAM 241 is provided with a normal counter area 231, a counter area 232 for the opening/closing execution mode, a counter area 233 for the high-frequency support mode, and a calculation result storage area 234. The contents of these areas 231 to 234 are the same as in the 15th embodiment described above. In this embodiment as well, a management execution process, including a check process, is executed as a process corresponding to non-specific control in the main CPU 63. In this check process, similar to the 15th embodiment, game history is collected through updates to the normal counter area 231, the opening/closing execution mode counter area 232, and the high-frequency support mode counter area 233. The 61st to 68th parameters, calculated using the collected game history, are written to the calculation result storage area 234. In other words, since the management RAM 241 is used when the main CPU 63 executes a process corresponding to non-specific control, the management RAM 241 is used as a work area for non-specific control.

Furthermore, when collecting game history and calculating parameters 61 to 68 using the collected history information, the work area 223 and stack area 224 for non-specific control of the main RAM 65 are used as appropriate.

According to the above configuration, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, and the calculation result storage area 234 are provided in the management RAM 241 externally attached to the MPU 62. This makes it possible to store collected game history information without increasing the required storage capacity in the non-specific control work area 223 of the main RAM 65, and also to store the 61st to 68th parameters calculated using the game history. Furthermore, it becomes possible to increase the storage capacity for storing game history information while utilizing the general-purpose MPU 62.

When collecting game history and calculating parameters 61 to 68 using the collected history information, the non-specific control work area 223 and non-specific control stack area 224 of the main RAM 65 are used as appropriate. This prevents a drastic decrease in processing speed when performing processing related to history information.

In addition to the configuration in which the management RAM 241 is provided with a normal counter area 231, a counter area 232 for the open/close execution mode, a counter area 233 for the high-frequency support mode, and a calculation result storage area 234, a configuration in which a storage area corresponding to the history memory 117 in the first embodiment described above is also provided may be used. In this case, it is necessary to increase the storage capacity required to store the history information, but since the management RAM 241, which is externally attached to the MPU 62, is used as the storage means for storing the history information, it is possible to flexibly accommodate the increase in storage capacity.

<Embodiment 22>
In this embodiment, the processing configuration executed by the main CPU 63 differs from that of the 15th embodiment described above. The configurations that differ from those of the 15th embodiment will be described below. Configurations that are the same as those of the 15th embodiment will generally not be described.

Figure 84 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S5001 to S5019 in the main processing are executed by the main CPU 63 using a specific control program and specific control data.

First, a power-on wait process is executed (step S5001). During this power-on wait process, for example, the system waits for a predetermined waiting time (specifically, 1 second) after the main process has started, without proceeding to the next process. During this power-on wait process, the operation start and initial setup of the graphic display device 41 are completed. Afterward, access to the main RAM 65 is permitted (step S5002).

Subsequently, it is determined whether the reset button 68c is pressed (step S5003), whether the setting key insertion part 68a is turned ON using the setting key (step S5004), whether the front door frame 14 is open relative to the inner frame 13 (step S5005), and whether the game machine body 12 is open relative to the outer frame 11 (step S5006).

In this embodiment, a front door open sensor 95 is electrically connected to the main CPU 63 to detect whether the front door frame 14 is open relative to the inner frame 13. The detection result of the front door open sensor 95 is input to the main CPU 63. In this case, if the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the main CPU 63. If the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the main CPU 63. The main CPU 63 identifies the front door frame 14 as closed when it receives a closed detection signal from the front door open sensor 95, and identifies the front door frame 14 as open when it receives an open detection signal from the front door open sensor 95.

Furthermore, in this embodiment, a main unit opening sensor 96 for detecting whether the gaming machine body 12 is open relative to the outer frame 11 is electrically connected to the main CPU 63, and the detection result of the main unit opening sensor 96 is input to the main CPU 63. In this case, if the gaming machine body 12 is closed relative to the outer frame 11, the main unit opening sensor 96 transmits a closing detection signal to the main CPU 63, and if the gaming machine body 12 is open relative to the outer frame 11, the main unit opening sensor 96 transmits an opening detection signal to the main CPU 63. The main CPU 63 identifies the gaming machine body 12 as being in a closed state when it receives a closing detection signal from the main unit opening sensor 96, and identifies the gaming machine body 12 as being in an open state when it receives an opening detection signal from the main unit opening sensor 96.

If the reset button 68c is pressed (step S5003: YES), and a negative determination is made in any of steps S5004 to S5006, the clear process for non-setting updates is executed (step S5007). In the clear process for non-setting updates, the work area 221 for specific control is cleared to "0" except for the area where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, the setting value counter), and initial settings are performed on the area that has been cleared to "0". As a result, the area indicating whether the win/fail lottery mode is in high probability mode is cleared to "0", so the win/fail lottery mode becomes low probability mode regardless of the win/fail lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the situation becomes one in which no game rounds are being played, the opening/closing execution mode is not being executed, the general display unit 38a is not showing a change, and the general electric mechanism 34a is in a closed state. Furthermore, the hold storage area 65a and the general-purpose hold area 65c, both located in the work area 221 for specific control, are also cleared to "0". This clears the hold information for both the special display unit 37a and the general-purpose display unit 38a. Additionally, during the clear process for non-setting updates, the stack area 222 for specific control is cleared to "0". Furthermore, during the clear process for non-setting updates, the various registers of the main CPU 63 are also cleared to "0" before initial settings are performed.

During the clear process when a setting update is not performed, the work area 223 and stack area 224 for non-specific control are not cleared to "0". This prevents the work area 223 and stack area 224 for non-specific control from being cleared to "0" even if power is supplied to the pachinko machine 10 while the reset button 68c is pressed.

If the reset button 68c is not pressed (step S5003: NO), it is determined whether the power outage flag is set to "1" (step S5008). The power outage flag is located in the work area 221 for specific control. When the power supply to the main CPU 63 is stopped, if the predetermined power outage processing is executed successfully, the power outage flag is set to "1". If the power outage flag is set to "1", it is determined whether the checksum calculation result matches the checksum saved at the time of power cut-off, i.e., the validity of the stored data (step S5009). If the clear process for non-setting updates is executed in step S5007, or if an affirmative determination is made in step S5009, it is determined whether the setting value of the pachinko machine 10 is normal by checking the value of the setting value counter in the work area 221 for specific control (step S5010). Specifically, it is determined to be normal if the setting value set in the setting value counter is one of "setting 1" to "setting 6", and abnormal if it is "0" or 7 or higher.

If a negative result is obtained in any of steps S5008 to S5010, the operation prohibition process is executed. The operation prohibition process executes an error notification process (step S5011) to inform the hall manager or other relevant personnel of the error, after which an infinite loop occurs. This operation prohibition process is released when the clear process during setting updates (step S5018), described later, is executed.

If a positive result is obtained in all steps S5008 to S5010, the power-on setting process is executed (step S5012). In the power-on setting process, predetermined areas of the work area 221 for specific control, such as the power outage flag, are set to their initial values, and commands corresponding to the current game state are transmitted to the voice and light emission control device 81.

The main CPU 63 is configured to periodically execute timer interrupt processing, but the generation of timer interrupt processing is prohibited when the main processing starts. This prohibition on timer interrupt processing is lifted after the processing in step S5012 is completed and before the processing in step S5013 is executed, at which point the execution of timer interrupt processing is permitted. Therefore, once power is supplied to the main CPU 63, the timer interrupt processing will not be executed until the power-on setting process in step S5012 is completed and before the processing in step S5013 begins. Consequently, the processing necessary to advance the game will not start in the main CPU 63 until this situation occurs.

Subsequently, the process proceeds to the residual processing steps S5013 to S5016. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but residual time occurs between one timer interrupt processing and the next. This residual time varies depending on the processing completion time of each timer interrupt processing, and the residual processing steps S5013 to S5016 are repeatedly executed using this irregular time. In this respect, the residual processing steps S5013 to S5016 can be considered an irregular process that is executed irregularly. Steps S5013 to S5016 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

On the other hand, if the reset button 68c is pressed (step S5003: YES), and affirmative judgments are made in all of steps S5004 to S5006, a process for updating the setting value is executed. Specifically, a setting value copy process is first executed (step S5017). In this copy process, the information of the setting value counter, which is used to identify the setting value of the pachinko machine 10 in the work area 221 for specific control, is stored in a copy area provided in the work area 221 for specific control. This makes it possible to determine the setting value of the pachinko machine 10 before the clear process for setting updates (step S5018) is executed (i.e., the setting value of the pachinko machine 10 before the supply of operating power to the pachinko machine 10 is stopped), even if the setting value counter information is cleared to "0" during the clear process for setting updates that is executed later.

Subsequently, the clear process for setting updates is executed (step S5018). In the clear process for setting updates, the work area 221 for specific control is cleared to "0", except for the area indicating whether the win/loss lottery mode in the work area 221 is in high probability mode and the copy area mentioned above, and initial settings are performed on the area that has been cleared to "0". As a result, the game rounds are not being executed, the opening/closing execution mode is not being executed, the general display unit 38a is not showing a change, and the general electric mechanism 34a is in a closed state. In addition, the hold storage area 65a and the general electric hold area 65c provided in the work area 221 for specific control are also cleared to "0", so the hold information for the special display unit 37a and the hold information for the general display unit 38a are erased. Furthermore, in the clear process for setting updates, the stack area 222 for specific control is cleared to "0", and initial settings are performed on the area that has been cleared to "0". Furthermore, during the clearing process when updating settings, the setting value counter used to identify the setting value of the pachinko machine 10 is cleared to "0". Also, during the clearing process when updating settings, various registers of the main CPU 63 are cleared to "0" before initial settings are performed.

On the other hand, the clear process during setting updates does not clear the area indicating whether the win/loss lottery mode is in high probability mode to "0". Therefore, even if the setting value update process (step S5019) is executed, it is possible to maintain the win/loss lottery mode in the mode it was in before the power supply to the pachinko machine 10 was stopped. Furthermore, since the clear process during setting updates does not clear the copy area to "0", it is possible to identify the setting value that was set before the clear process during setting updates was executed.

During the clearing process when updating settings, the work area 223 and stack area 224 for non-specific control are not cleared to "0". This ensures that even if a setting update process that allows changing the settings of the pachinko machine 10 is executed, the work area 223 and stack area 224 for non-specific control are not cleared to "0".

Subsequently, after the setting value update process is executed in step S5019, the process proceeds to step S5012. The setting value update process is described below. Figure 85 is a flowchart of the setting value update process. Note that steps S5101 to S5114 in the setting value update process are executed by the main CPU 63 using a specific control program and specific control data.

First, the setting value counter located in the work area 221 for specific control is set to "1" (step S5101). The setting value counter is used by the main CPU 63 to determine which setting value the pachinko machine 10 is currently using. When "1" is set in the setting value counter, the setting value becomes "Setting 1" regardless of the previous setting value when the setting value update process is executed.

Subsequently, the process for starting the display of the set value is executed (step S5102). During this process, the display control of the third notification display device 69c is performed so that the number "1" corresponding to "Setting 1" is displayed. The administrator of the amusement hall can understand the current setting status of the pachinko machine 10 by checking the third notification display device 69c when changing the set value.

Subsequently, it is determined whether or not one game ball has been detected by the out-port detection sensor 48a (step S5103). Specifically, it is determined whether or not the signal received from the out-port detection sensor 48a has switched from a LOW level to a HI level. If the determination in step S5103 is negative, it is determined whether or not the update button 68b has been pressed once (step S5104). Specifically, it is determined whether or not the signal from the sensor that detects the press operation of the update button 68b has switched from a LOW level to a HI level. If the determination in step S5104 is negative, the process returns to step S5103, and it is determined whether or not one game ball has been detected by the out-port detection sensor 48a.

If the update button 68b is pressed once (step S5104: YES), the value of the set value counter in the work area 221 for specific control is incremented by 1 (step S5105). Furthermore, if the value of the set value counter exceeds "6" after the increment (step S5106: YES), the set value counter is set to "1" (step S5107). As a result, each time the update button 68b is pressed, the setting value is updated to the next higher level, and if the update button 68b is pressed once while the setting is "6", it returns to "1".

If a negative result is obtained in step S5106, or if the process in step S5107 is executed, the setting value display update process is executed (step S5108). In the setting value display update process, the third notification display device 69c is controlled to display a number corresponding to the value of the setting value counter in the specific control work area 221. The administrator of the amusement hall can understand the setting status of the pachinko machine 10 after pressing the update button 68b by checking the third notification display device 69c.

After executing the process in step S5108, the process returns to step S5103 to determine whether or not one game ball was detected by the out-port detection sensor 48a. If no game ball was detected by the out-port detection sensor 48a (step S5103: NO), the process from step S5104 onwards is executed again. If one game ball was detected by the out-port detection sensor 48a (step S5103: YES), it is determined whether or not the setting key insertion unit 68a switched from the ON state to the OFF state (step S5109). In this case, it is not determined whether or not the setting key insertion unit 68a is in the OFF state, but rather whether or not a switch from the ON state to the OFF state has occurred, and if it is determined that such a switch has occurred, an affirmative determination is made in step S5109.

If the device is not switched to the OFF state (step S5109: NO), the process in step S5109 is executed again. This causes the process to wait until the setting key insertion unit 68a is turned OFF. If the device is switched to the OFF state (step S5109: YES), the process for ending the display of the setting value is executed (step S5110). In the process for ending the display of the setting value, the display of the setting value on the third notification display device 69c is terminated. In this case, the display of information on various parameters stored in the calculation result storage area 234 provided in the non-specific control work area 223 is started on the first to third notification display devices 69a to 69c.

Subsequently, a setting value comparison process is performed (step S5111). This process determines whether the information from the setting value counter in the specific control work area 221 matches the information stored in the copy area of the specific control work area 221. In other words, it determines whether the setting value set before the power supply to the pachinko machine 10 was stopped is the same as the setting value set in this setting value update process.

If the setting value set before the power supply to the pachinko machine 10 was stopped is the same as the setting value set during this setting value update process (step S5112: NO), the notification process for no change is executed (step S5113). In the notification process for no change, a setting maintenance command indicating that the setting value was not changed is sent to the voice and light emission control device 81. Upon receiving this setting maintenance command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to setting maintenance, and outputs the voice message "Settings maintained." from the speaker unit 54. Furthermore, the text image "Settings maintained." is displayed on the symbol display device 41.

These notifications are maintained from the time the setting maintenance command is sent until the notification execution period (e.g., 10 seconds) has elapsed, at which point they terminate. However, the system is not limited to this, and the notifications may be terminated when the notification termination operation is performed by the administrator of the gaming hall. The notification termination operation may include, for example, pressing the update button 68b or pressing the reset button 68c. By confirming these notifications, the administrator of the gaming hall can understand that the setting value has been maintained. Furthermore, in the notification process for non-change, the system may be configured to notify that the setting value has been maintained by setting the display content of at least one of the first to third notification display devices 69a to 69c to content corresponding to setting maintenance, or it may be configured to provide an external output indicating that the setting value has been maintained.

If the setting value set before the power supply to the pachinko machine 10 was stopped is not the same as the setting value set during this setting value update process (step S5112: YES), a notification process for the change is executed (step S5114). In the notification process, a setting change command indicating that the setting value has been changed is sent to the voice and light emission control device 81. Upon receiving this setting change command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the setting change and outputs the voice message "Settings have been changed." from the speaker unit 54. Furthermore, the text image "Settings have been changed." is displayed on the symbol display device 41.

These notifications are maintained from the time the setting change command is sent until the notification execution period (e.g., 10 seconds) has elapsed, at which point they terminate. However, the system is not limited to this; the notifications may also be terminated when the administrator of the gaming hall performs a notification termination operation. The notification termination operation may include, for example, pressing the update button 68b or pressing the reset button 68c. By confirming these notifications, the administrator of the gaming hall can understand that the setting value has been changed. Furthermore, in the notification process upon change, the system may be configured to notify that the setting value has been changed by displaying content corresponding to the setting change on at least one of the first to third notification display devices 69a to 69c, or it may be configured to output an external output indicating that the setting value has been changed.

As described above, in this embodiment, for the setting value update process to be executed, it is necessary not only that the setting key insertion part 68a is turned ON, but also that the reset button 68c is pressed, the front door frame 14 is in an open state, and the gaming machine body 12 is in an open state. This makes it difficult to perform the setting value update process fraudulently.

Furthermore, for the setting value update process to be executed, the front door frame 14 and the gaming machine body 12 must be in an open state. This means that even if someone attempts to fraudulently execute the setting value update process, the open state of the front door frame 14 and the gaming machine body 12 will make such fraudulent activity conspicuous, making it easier for the gaming hall manager to detect it.

In particular, for the setting value update process to be executed, it is necessary not only to open the main body of the gaming machine 12 to expose the main control device 60, but also to open the front door frame 14. This makes the process of the aforementioned fraudulent activity more complicated and also makes the fraudulent activity more conspicuous.

Furthermore, in a configuration where the game does not resume if the setting value update process is not completed, in order to confirm the selected setting value during the setting value update process and terminate the process, it is necessary to insert a game ball into the output port 24a, have the output port detection sensor 48a detect the game ball, and then turn OFF the setting key insertion unit 68a. This makes it difficult to terminate the setting value update process and resume the game even if the setting value update process is executed fraudulently.

Furthermore, the setting value that was set before the power supply to the pachinko machine 10 was cut off is compared with the setting value selected during the setting value update process, and a notification is issued depending on whether the two setting values are the same or not. This makes it easy for the administrator of the amusement hall to determine whether or not the setting value was successfully changed through the setting value update process.

Figure 86 is a flowchart showing the timer interrupt processing in this embodiment, which is executed by the main CPU 63. The timer interrupt processing is executed periodically (for example, every 4 milliseconds) while steps S5013 to S5016 are being executed in the main processing (Figure 84). The program corresponding to the timer interrupt processing is set in the specific control program.

Steps S5201 to S5205 execute the same processes as steps S301 to S305 of the timer interrupt processing (Figure 11) in the first embodiment described above. These processes are executed by the main CPU 63 using a specific control program and specific control data.

Subsequently, a configuration verification process is executed (step S5206). During the execution of the configuration verification process, the program of the subroutine corresponding to the configuration verification process, which is set in the specific control program, is executed. During the execution of this subroutine, information to identify the return address of the timer interrupt process after the configuration verification process is written to the specific control stack area 222 via a push instruction. Then, when the configuration verification process is completed, the information to identify the return address is read out via a pop instruction, and the program returns to the timer interrupt process indicated by that return address.

Figure 87 is a flowchart showing the setting verification process. Note that steps S5301 to S5312 in the setting verification process are executed by the main CPU 63 using a specific control program and specific control data.

First, the third notification display device 69c determines whether or not the setting value corresponding to the information in the setting value counter in the work area 221 for specific control is being displayed (step S5301). If a negative determination is made in step S5301, it is determined whether or not it is neither a game round nor an opening/closing execution mode (step S5302), whether or not it is neither a pattern variation display round in the regular diagram display unit 38a nor a regular open state in which the regular electric mechanism 34a can be in an open state (step S5303), whether or not the front door frame 14 is in an open state relative to the inner frame 13 (step S5304), whether or not the game machine body 12 is in an open state relative to the outer frame 11 (step S5305), and whether or not the setting key insertion unit 68a is turned ON (step S5306). The determination of whether the front door frame 14 is in an open state is performed based on the detection result of the front door open sensor 95, similar to step S5005 in the main process (Figure 84). The determination of whether the gaming machine body 12 is in an open state is performed based on the detection result of the body open sensor 96, similar to step S5006 in the main process (Figure 84).

If a negative result is obtained in any of steps S5302 to S5306, the setting confirmation process is terminated without executing steps S5307 to S5309. If a positive result is obtained in all of steps S5302 to S5306, the setting value display start process is executed (step S5307). In the setting value display start process, the third notification display device 69c is controlled to display the setting value corresponding to the information of the setting value counter in the specific control work area 221. When confirming the setting value, the manager of the amusement hall can understand the current setting status of the pachinko machine 10 by visually checking the third notification display device 69c.

Subsequently, the game stop flag provided in the work area 221 for specific control is set to "1" (step S5308). The game stop flag is a flag used by the main CPU 63 to determine whether or not the execution of the processes in steps S5208 to S5221 should be stopped in the timer interrupt processing (Figure 86) by making a positive determination in step S5207. By setting the game stop flag to "1", the execution of the processes in steps S5208 to S5221 is stopped by making a positive determination in step S5207 of the timer interrupt processing (Figure 86). As a result, the setting value is checked in a situation where the execution of the processes to advance the game is stopped. However, even when the game stop flag is set to "1", the processes in steps S5201 to S5205 of the timer interrupt processing (Figure 86) are executed. Therefore, even when the setting value is being checked, power outage monitoring is performed, and the random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and further fraud detection is performed.

Subsequently, a confirmation notification start command is sent to the audio/light emission control device 81 (step S5309). Upon receiving this confirmation notification start command, the audio/light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the setting confirmation process, and outputs the voice message "Setting confirmation in progress." from the speaker unit 54. Furthermore, the text image "Setting confirmation in progress." is displayed on the graphic display device 41. These notifications continue until a confirmation notification end command is received from the main CPU 63. Alternatively, an external output indicating that the setting value is being confirmed may be provided.

As described above, under the conditions that neither the game round nor the opening/closing execution mode is active, and furthermore, neither the pattern variation display round on the regular display unit 38a nor the regular power opening state where the regular power mechanism 34a can be opened is enabled, the display for confirming the set value is shown on the third notification display device 69c, thereby preventing the setting value confirmation process from being performed while the game is in progress.

Furthermore, in order for the setting value to be displayed on the third notification display device 69c, it is necessary not only that the setting key insertion unit 68a is turned ON, but also that the front door frame 14 is in an open state and the gaming machine body 12 is in an open state. This makes it difficult to fraudulently display the setting value confirmation.

Furthermore, in order for the setting value to be displayed on the third notification display device 69c, the front door frame 14 and the gaming machine body 12 must be in an open state. This ensures that even if someone attempts to fraudulently display the setting value, the open state of the front door frame 14 and the gaming machine body 12 makes such fraudulent activity conspicuous, making it easier for the gaming hall manager to detect it.

In particular, in order for the setting value to be displayed on the third notification display device 69c, it is necessary not only to open the main body of the gaming machine 12, which is required to expose the main control device 60, but also to open the front door frame 14. This makes the process of the aforementioned fraudulent activity more complicated and also makes the fraudulent activity more conspicuous.

If a positive result is obtained in step S5301, it is determined whether the setting key insertion unit 68a is in the OFF position (step S5310). If it is in the OFF position (step S5310: YES), the game stop flag in the work area 221 for specific control is cleared to "0" (step S5311). As a result, a negative result is obtained in step S5207 of the timer interrupt processing (Figure 86), leading to the execution of steps S5208 to S5221. This releases the state in which the execution of the processing necessary to advance the game has been stopped.

Subsequently, a confirmation notification termination command is transmitted to the audio and light emission control device 81 (step S5312). Upon receiving this confirmation notification termination command, the audio and light emission control device 81 terminates the notification indicating that the set values in the pattern display device 41, display light emission unit 53, and speaker unit 54 are being verified.

Returning to the explanation of the timer interrupt processing (Figure 86), after completing the setting confirmation process in step S5206, it is determined whether or not the game is stopped (step S5207). In this case, if the game stop flag in the work area 221 for specific control is set to "1" in the setting confirmation process in step S5206, a positive determination is made in step S5207 and the processes in steps S5208 to S5221 are not executed. Also, if the fraud detection process in step S5205 detects the occurrence of fraud, a positive determination is made in step S5207 and the processes in steps S5208 to S5221 are not executed.

Steps S5208 to S5219 execute the same processes as steps S307 to S318 of the timer interrupt processing in the first embodiment (Figure 11). These processes are executed by the main CPU 63 using a specific control program and specific control data. Furthermore, step S5221 executes the same process as step S3719 of the timer interrupt processing in the fifteenth embodiment (Figure 69).

Meanwhile, in step S5220, the RAM monitoring process is executed. During the execution of the RAM monitoring process, the program of the subroutine corresponding to the RAM monitoring process, which is set in the specific control program, is executed. During the execution of this subroutine, information to identify the return address of the timer interrupt process after the RAM monitoring process is written to the specific control stack area 222 by a push instruction. Then, when the RAM monitoring process is completed, the information to identify the return address is read out by a pop instruction, and the program returns to the timer interrupt process indicated by that return address.

Figure 88 is a flowchart of the RAM monitoring process. Note that steps S5401 to S5412 in the RAM monitoring process are executed by the main CPU 63 using a specific control program and specific control data.

First, a monitoring process for the work area 221 for specific control is executed (step S5401). This monitoring process checks whether an abnormality has occurred in the information stored in the work area 221 for specific control due to noise or other causes. While the monitoring method is arbitrary, one method involves monitoring whether the state of a storage area in the work area 221 where information is not written by various controls in the main CPU 63 is different from its initial state, and determining that an abnormality has occurred if the state is different from the initial state. In this case, if the initial state of the storage area is set to "0", an abnormality is determined if "1" is stored in that storage area; if the initial state of the storage area is set to "1", an abnormality is determined if the storage area is set to "0". Alternatively, a configuration may be used where an abnormality is determined if the value of a predetermined byte is different from a value that can be set under normal conditions.

If an abnormality is detected in step S5401 (step S5402: YES), the processes in steps S5409 to S5412 are executed. If no abnormality is detected in step S5401 (step S5402: NO), the process proceeds to step S5403.

In step S5403, a monitoring process for the specific control stack area 222 is executed. This monitoring process checks whether an abnormality has occurred in the information stored in the specific control stack area 222 due to noise or other causes. While the monitoring method is arbitrary, one possible method is to monitor whether the state of a storage area in the specific control stack area 222, where information is not written by various controls in the main CPU 63, is different from its initial state, and determine that an abnormality has occurred if it is different from the initial state. In this case, if the initial state of the storage area is set to "0", an abnormality is determined if "1" is stored in that storage area; if the initial state of the storage area is set to "1", an abnormality is determined if the storage area has a value of "0". Alternatively, a configuration may be used where an abnormality is determined if the value of a predetermined byte is different from a value that can be set under normal conditions.

If an abnormality is detected in step S5403 (step S5404: YES), the processes in steps S5409 to S5412 are executed. If no abnormality is detected in step S5403 (step S5404: NO), the process proceeds to step S5405.

In step S5405, a monitoring process for the work area 223 for non-specific control is executed. This monitoring process checks whether an abnormality has occurred in the information stored in the work area 223 for non-specific control due to noise or other causes. While the monitoring method is arbitrary, one method involves monitoring whether the state of a storage area in the work area 223 for non-specific control, where information is not written by various controls in the main CPU 63, is different from its initial state. If it is different from the initial state, an abnormality is determined. In this case, if the initial state of the storage area is set to "0", an abnormality is determined if "1" is stored in that storage area. If the initial state of the storage area is set to "1", an abnormality is determined if the storage area has a value of "0". Alternatively, a configuration may be used where an abnormality is determined if the value of a predetermined byte is different from a value that can be set under normal conditions.

If an abnormality is detected in step S5405 (step S5406: YES), the processes in steps S5409 to S5412 are executed. If no abnormality is detected in step S5405 (step S5406: NO), the process proceeds to step S5407.

In step S5407, a monitoring process for the non-specific control stack area 224 is executed. This monitoring process checks whether an abnormality has occurred in the information stored in the non-specific control stack area 224 due to noise or other causes. While the monitoring method is arbitrary, one method involves monitoring whether the state of a storage area in the non-specific control stack area 224, where information is not written by various controls in the main CPU 63, is different from its initial state. If it is different from the initial state, an abnormality is determined. In this case, if the initial state of the storage area is set to "0", an abnormality is determined if "1" is stored in that storage area. If the initial state of the storage area is set to "1", an abnormality is determined if the storage area has a value of "0". Alternatively, a configuration may be used where an abnormality is determined if the value of a predetermined byte is different from a value that can be set under normal conditions.

If an abnormality is detected in step S5407 (step S5408: YES), the processes in steps S5409 to S5412 are executed. Specifically, the setting value copy process is performed first (step S5409). In this copy process, the information of the setting value counter, which is used to identify the setting value of the pachinko machine 10 in the work area 221 for specific control, is stored in a copy area provided in the work area 221 for specific control. This makes it possible to know the setting value of the pachinko machine 10 before the execution of the abnormality clear process (step S5410), even if the setting value counter information is cleared to "0" in the subsequent abnormality clear process.

Subsequently, an error clearing process is executed (step S5410). In this error clearing process, the work area 221 for specific control is cleared to "0" (excluding the copy area), and the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control are also cleared to "0". Initial settings are then performed after the "0" clearing. In other words, if the RAM monitoring process identifies an error in any one of the following: the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, or the stack area 224 for non-specific control, then the work area 221 for specific control is cleared to "0" (excluding the copy area), and the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control are also cleared to "0". This prevents the execution of either the specific control processing or the non-specific control processing if there is a possibility of some kind of information error in the main RAM 65.

Furthermore, if the specific control stack area 222 is cleared to "0", the return address information after the RAM monitoring process is also erased. Therefore, if the specific control stack area 222 is cleared to "0", the system returns uniquely to a predetermined program after completing the process in step S5412. Specifically, the system is configured to return uniquely to the process in step S5013 of the main process (Figure 22). However, the program to which the system returns uniquely is not limited to step S5013; it could also be step S5221 in the timer interrupt process (Figure 86). Also, if the specific control stack area 222 is cleared to "0", the stack pointer of the main CPU 63 is set to the address of the first storage area in the storage order of the specific control stack area 222.

Subsequently, an abnormality command indicating that an abnormal clear process has occurred is transmitted to the audio and light emission control device 81 (step S5411). Upon receiving this abnormality command, the audio and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to a forced clear, and outputs the voice message "Forced clear performed." from the speaker unit 54. Furthermore, the text image "Forced clear performed." is displayed on the pattern display device 41. These notifications are maintained until the power supply to the pachinko machine 10 is stopped, at which point they terminate. However, this is not limited to this configuration; the notifications may also be terminated when the administrator of the gaming hall performs a notification termination operation. For example, the notification termination operation may involve pressing the update button 68b or the reset button 68c. By confirming these notifications, the administrator of the gaming hall can understand that the main RAM 65 has been forcibly cleared.

Subsequently, the setting value update process is executed (step S5412). In other words, if an abnormality clear process occurs, the setting value counter in the specific control work area 221 is also cleared to "0". Therefore, the setting value update process is executed to reset the setting value of the pachinko machine 10. The processing content of the setting value update process is the same as step S5019 of the main process (Figure 84). Therefore, each time the update button 68b is pressed, the setting value is updated by one level, and the selected setting value is confirmed by detecting a game ball with the out-out detection sensor 48a. The setting value during the update and the confirmed setting value are displayed on the third notification display device 69c. Subsequently, when the setting key insertion unit 68a switches from the ON state to the OFF state, it is determined that the termination condition of the setting value update process has been met.

Here, the termination condition is not determined to be met simply by the setting key insertion unit 68a being in the OFF state; the termination condition is determined to be met only when the setting key insertion unit 68a switches from the ON state to the OFF state. When the setting value update process is executed in the RAM monitoring process (Figure 88), the setting key insertion unit 68a is in the OFF state at the start of the setting value update process. Therefore, in order to satisfy the termination condition for the setting value update process, it is necessary to insert a setting key into the setting key insertion unit 68a, perform an ON operation, and then perform an OFF operation. This prevents the setting value update process from terminating prematurely even if the administrator of the gaming hall has not performed a legitimate operation.

When the setting key insertion unit 68a switches from the ON state to the OFF state and the termination condition for the setting value update process is met, step S5111 in the setting value update process (Figure 85) is executed to compare whether the setting value stored in the copy area of the work area 221 for specific control is the same as the setting value currently set in the setting value counter of the work area 221 for specific control. In other words, it is determined whether the setting value set before the error clear process (step S5410) was executed is the same as the setting value set in the current setting value update process. If both setting values are the same (step S5112: NO), the notification process for no change (step S5113) is executed to provide the setting maintenance notification described earlier. On the other hand, if both setting values are different (step S5112: YES), the notification process for change (step S5114) is executed to provide the setting change notification described earlier.

The embodiment described in detail above provides the following excellent effects.

For the setting value update process to be executed when power is supplied to the pachinko machine 10, it is necessary not only that the setting key insertion unit 68a is turned ON, but also that the reset button 68c is pressed, the front door frame 14 is open, and the game machine body 12 is open. This makes it difficult to fraudulently execute the setting value update process.

For the setting value update process to be executed, the front door frame 14 and the gaming machine body 12 must be in an open state. This means that even if someone attempts to fraudulently execute the setting value update process, the open state of the front door frame 14 and the gaming machine body 12 will make such fraudulent activity conspicuous, making it easier for the gaming hall manager to detect it.

In particular, for the setting value update process to be executed, it is necessary not only to open the main body of the gaming machine 12 to expose the main control device 60, but also to open the front door frame 14. This makes the process of the aforementioned fraudulent activity more complicated and also makes the fraudulent activity more conspicuous.

In a configuration where the game does not resume if the setting value update process is not completed, in order to confirm the selected setting value during the setting value update process and terminate the process, it is necessary to insert a game ball into the output port 24a, have the output port detection sensor 48a detect the game ball, and then turn OFF the setting key insertion unit 68a. This makes it difficult to terminate the setting value update process and resume the game even if the setting value update process is executed fraudulently.

The setting value that was set before the power supply to the pachinko machine 10 was cut off is compared with the setting value selected during the setting value update process, and a notification is issued depending on whether the two setting values are the same or not. This makes it easy for the administrator of the amusement hall to determine whether or not the setting value was successfully changed through the setting value update process.

By ensuring that the setting value is displayed on the third notification display device 69c under the conditions that neither the game round nor the opening/closing execution mode is active, and furthermore, neither the pattern variation display round on the regular diagram display unit 38a nor the regular power opening state where the regular power mechanism 34a can be opened, it becomes possible to prevent the setting value confirmation process from being performed while the game is in progress.

For the setting value to be displayed on the third notification display device 69c, it is necessary not only that the setting key insertion unit 68a is turned ON, but also that the front door frame 14 is in an open state and the gaming machine body 12 is in an open state. This makes it difficult to fraudulently display the setting value confirmation.

For the display of the setting value to be shown on the third notification display device 69c, the front door frame 14 and the gaming machine body 12 must be in an open state. This ensures that even if someone attempts to fraudulently display the setting value, the open state of the front door frame 14 and the gaming machine body 12 makes such fraudulent activity conspicuous, making it easier for the gaming hall manager to detect it.

In particular, in order for the setting value to be displayed on the third notification display device 69c, it is necessary not only to open the main body of the gaming machine 12, which is required to expose the main control device 60, but also to open the front door frame 14. This makes the process of the aforementioned fraudulent activity more complicated and also makes the fraudulent activity more conspicuous.

If an abnormality is detected in any one of the following areas: the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, or the stack area 224 for non-specific control, the work area 221 for specific control is cleared to "0" (excluding the copy area), and the stack areas 222, 223, and 224 are also cleared to "0". This prevents the execution of either the specific control-related or non-specific control-related processes if there is a possibility of some kind of information abnormality in the main RAM 65.

In the processing corresponding to specific control, not only the work area 221 and stack area 222 for specific control are monitored, but also the work area 223 and stack area 224 for non-specific control to check for information anomalies. This simplifies the processing configuration compared to a configuration where information anomalies are monitored separately for processing corresponding to specific control and processing corresponding to non-specific control.

If an abnormality is detected in any one of the following: the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, or the stack area 224 for non-specific control, the processing corresponding to the specific control will clear not only the work area 221 and the stack area 222, but also the work area 223 and the stack area 224 for non-specific control to "0". This simplifies the processing configuration compared to a configuration where the "0" clearing is performed separately for the processing corresponding to specific control and the processing corresponding to non-specific control.

If an information anomaly occurs and the anomaly clear process is executed, the setting value update process is performed. This prevents the game from continuing even if the setting value is not set. In this case, if the setting value set before the anomaly clear process is executed is the same as the setting value set during the setting value update process after the anomaly clear process is executed, a setting maintenance notification is issued. This means that even if the anomaly clear process is executed, the setting value set in the previous situation is reset, and the setting maintenance notification is issued, clearly indicating to the player that the setting value has not changed even after the anomaly clear process is executed. Incidentally, since it is common practice in amusement halls to record the setting values of each installed pachinko machine, it is possible to perform the setting value update process after the anomaly clear process is executed so that the setting value matches the recorded setting value.

Furthermore, the conditions for executing the setting value update process when the supply of operating power to the pachinko machine 10 is started may be different from those in the above embodiment. Figure 89 is a flowchart of a main process in a different form. In this main process, steps S5501 to S5506 and steps S5508 to S5520 execute the same processes as steps S5001 to S5019 of the main process in the above embodiment (Figure 84). On the other hand, in this main process, step S5507 determines whether the operating handle of the launching device 28, which is operated to launch game balls into the game area PA, has been rotated from its initial rotation position. Then, if the reset button 68c is pressed (step S5503: YES), the setting key insertion part 68a is turned ON (step S5504: YES), the front door frame 14 is open relative to the inner frame 13 (step S5505: YES), the game machine body 12 is open relative to the outer frame 11 (step S5506: YES), and the operating handle of the launching device 28 is rotated from its initial rotation position (step S5507: YES), the setting value update process (step S5520) is executed. As a result, in order for the setting value update process to be executed when the supply of operating power to the pachinko machine 10 is started, it is not only necessary to insert the setting key into the setting key insertion part 68a and turn it ON, but also to rotate the operating handle of the launching device 28 while the supply of operating power to the pachinko machine 10 is started. Furthermore, instead of determining in step S5507 whether the operating handle of the launching device 28 has been rotated from its initial rotation position, the system may be configured to determine whether the launching device 28 has been touched by the player.

Furthermore, as a condition for executing the setting value update process when power is supplied to the pachinko machine 10, both the front door frame 14 being open relative to the inner frame 13 and the game machine body 12 being open relative to the outer frame 11 are set. However, a configuration where only one of these conditions is set is also acceptable.

Furthermore, while the configuration includes a condition that the reset button 68c must be pressed for the setting value update process to be executed when power is supplied to the pachinko machine 10, the configuration may also be configured without this condition.

Furthermore, the system may be configured such that, as a condition for executing the setting value update process when power is supplied to the pachinko machine 10, the supply of power to the pachinko machine 10 is initiated while a game ball is detected by the gate detection sensor 49a. This means that, in order for the setting value update process to be executed when power is supplied to the pachinko machine 10, it is not enough to simply insert the setting key into the setting key insertion unit 68a and turn it ON; it is also necessary to ensure that game balls remain in the through gate 35 when power is supplied to the pachinko machine 10. Therefore, it becomes more difficult to attempt to illegally change the setting value.

Furthermore, the content of the operation to confirm the setting value in the setting value update process may differ from that of the above embodiment. Figure 90 is a flowchart of a setting value update process in a different form. In this setting value update process, steps S5601 to S5602 and steps S5604 to S5614 execute the same processes as steps S5101 to S5102 and steps S5104 to S5114 of the setting value update process in the above embodiment (Figure 85). On the other hand, in this setting value update process, in step S5603, instead of determining whether or not a game ball has been detected by the out-port detection sensor 48a, it is determined whether or not the ON duration for which an ON signal has been continuously output from the gate detection sensor 49a is longer than or equal to the termination reference period (specifically, 5 seconds). Then, if a positive determination is made in step S5603, the selected setting value is confirmed and the process proceeds to step S5609. According to this configuration, in order to confirm the selected setting value, it is necessary to intentionally leave the game ball in the through gate 35 for longer than the termination reference period. Under normal gameplay conditions, game balls will not remain in the through gate 35 for longer than the termination period. This makes it possible to ensure that the conditions for confirming the selected setting value are not met, or are difficult to meet, under normal gameplay conditions. Furthermore, even if a setting value update process is initiated fraudulently, it becomes difficult to perform the operation to confirm the selected setting value during that update process.

Furthermore, in the setting value update process, the selected setting value may be confirmed when the operating handle of the firing control device 28 is rotated from its initial rotation position, or the selected setting value may be confirmed when the firing control device 28 is touched by the player.

Furthermore, in the setting value update process, the selected setting value may be confirmed when the special electric ball detection sensor 45a detects that a game ball has entered the special electric ball entry device 32, which is equipped with an opening/closing member. Alternatively, the selected setting value may be confirmed when the second operation port detection sensor 47a detects that a game ball has entered the second operation port 34, which is also equipped with an opening/closing member. In this case, confirming the selected setting value requires manually opening the target ball entry port and then inserting the game ball, thus making it more difficult to fraudulently change the setting value.

Furthermore, in the setting value update process, the selected setting value may be determined based on the detection of a game ball entering the second ball entry point after the detection of a game ball entering the first ball entry point. In this case, determining the selected setting value requires manually inserting game balls into multiple ball entry points in a predetermined order, making it difficult to illegally change the setting value. In this case, by making both the first and second ball entry points ball entry points without opening/closing members, it is possible to prevent a drastic decrease in the efficiency of legitimate operations.

Furthermore, the setting value update process may be configured such that the selected setting value is confirmed and the termination condition for the setting value update process is met by switching the setting key insertion unit 68a from the ON state to the OFF state.

Furthermore, the configuration for updating the setting value by one step is not limited to pressing the update button 68b; the setting value may also be updated by pressing the reset button 68c.

Furthermore, when the reset button 68c is pressed and the setting key insertion section 68a is turned ON by the setting key, and power is supplied to the pachinko machine 10, and the front door frame 14 is not open relative to the inner frame 13, or the game machine body 12 is not open relative to the outer frame 11, the configuration is not limited to executing the clear process for non-setting updates (step S5007). The clear process for non-setting updates may not be executed. This prevents the clear process for non-setting updates from being executed against the wishes of the game hall administrator.

Furthermore, when the reset button 68c is pressed and the setting key insertion section 68a is not turned ON by the setting key, and power is supplied to the pachinko machine 10, and the front door frame 14 is not open relative to the inner frame 13, or the game machine body 12 is not open relative to the outer frame 11, the configuration is not limited to executing the clear process for non-setting updates (step S5007). The clear process for non-setting updates may not be executed. This makes it more difficult to fraudulently execute the clear process for non-setting updates.

<Embodiment 23>
In this embodiment, the processing configuration of the main process differs from that of the 22nd embodiment described above. The configuration that differs from that of the 22nd embodiment will be described below. Configurations that are the same as those in the 22nd embodiment will generally not be described.

Figure 91 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that the processing in steps S5701 to S5720 of the main processing is executed by the main CPU 63 using a specific control program and specific control data.

First, a power-on wait process is executed (step S5701). During this power-on wait process, for example, the system waits for a predetermined waiting time (specifically, 1 second) after the main process has started, without proceeding to the next process. During this power-on wait process, the operation start and initial setup of the graphic display device 41 are completed. Afterward, access to the main RAM 65 is permitted (step S5702).

Subsequently, based on the detection result of the front door open sensor 95, it is determined whether the front door frame 14 is open relative to the inner frame 13 (step S5703). Based on the detection result of the main body open sensor 96, it is determined whether the gaming machine main body 12 is open relative to the outer frame 11 (step S5704). It is also determined whether the reset button 68c is pressed (step S5705). If a negative determination is made in any of steps S5703 to S5705, the processes in steps S5706 to S5714 are executed. These processes in steps S5706 to S5714 are the same as steps S5008 to S5016 of the main process in the 22nd embodiment (Figure 84).

If a positive result is obtained in all of steps S5703 to S5705, a selection process is executed (step S5715). In the selection process, a process is executed to determine, based on a selection operation by the administrator of the gaming hall, whether to perform a clear process when there is no setting update and not perform the setting value update process, or to perform a clear process when there is a setting update and also perform the setting value update process. Specifically, each time the update button 68b is pressed, the system switches from a state in which one of the above states is selected to a state in which the other state is selected. Note that this selection operation may be performed by operating the reset button 68c, or by operating another control unit. Furthermore, if the system selects to perform a clear process during non-setting updates and not perform a setting value update process, the first notification display device 69a displays "O" and the second notification display device 69b and the third notification display device 69c are turned off. If the system selects to perform both a clear process during setting updates and a setting value update process, the second notification display device 69b displays "O" and the first notification display device 69a and the third notification display device 69c are turned off. Additionally, if the reset button 68c is continuously pressed for a period exceeding the confirmation selection period (specifically, 10 seconds), the selected state from the above conditions is confirmed as the current selection target.

Furthermore, the system may be configured to confirm the selected state among the above conditions as the current selection target when the update button 68b is continuously pressed for a confirmation selection period (specifically, 10 seconds) or longer. Alternatively, the system may be configured to confirm the selected state among the above conditions as the current selection target when another operating part is continuously pressed for a confirmation selection period (specifically, 10 seconds) or longer. In addition, the system may be configured to confirm the selected state among the above conditions as the current selection target when the operating handle of the firing operation device 28 is rotated.

In the selection process, if the situation where a clear process for non-setting updates is performed and a setting value update process is not performed is determined to be the target of selection (step S5716: NO), the clear process for non-setting updates is performed (step S5717). The processing content of the clear process for non-setting updates is the same as step S5007 of the main process (Figure 84) in the 22nd embodiment described above.

In the selection process, if the situation is determined to require both a clear process upon setting update and a setting value update process (step S5716: YES), the setting value copy process is executed (step S5718), the clear process upon setting update is executed (step S5719), and the setting value update process is executed (step S5720). The processing content of steps S5718 to S5720 is identical to steps S5017 to S5019 of the main process (Figure 84) in the 22nd embodiment described above.

According to the above configuration, even in a configuration where the setting key insertion section 68a is not provided, the administrator of the gaming hall can choose between two situations: one where a clear process is performed and the setting value update process is not executed when the setting is not updated, and another where a clear process is performed and the setting value update process is executed when the setting is updated.

Furthermore, not only when performing a setting update process, but also when performing a clear process in the case of no setting update, it is necessary not only to start supplying operating power to the pachinko machine 10 while the reset button 68c is pressed, but also to open the front door frame 14 relative to the inner frame 13 and open the game machine body 12 relative to the outer frame 11. This makes it difficult to fraudulently perform a clear process in the case of no setting update.

Furthermore, as a condition for the selection process to be executed when the power supply to the pachinko machine 10 is started, both the front door frame 14 being open relative to the inner frame 13 and the game machine body 12 being open relative to the outer frame 11 are set. However, a configuration where only one of these conditions is set is also acceptable.

Furthermore, the system may be configured to include additional conditions for the selection process to be executed when power is supplied to the pachinko machine 10, such as the firing handle of the firing control device 28 being rotated, the firing control device 28 being touched, or the gate detection sensor 49a detecting a game ball.

<Embodiment 24>
In this embodiment, the processing configuration of the RAM monitoring process differs from that of the 22nd embodiment described above. The configuration that differs from that of the 22nd embodiment will be described below. Configurations that are the same as those in the 22nd embodiment will generally not be described.

Figure 92 is a flowchart showing the RAM monitoring process in this embodiment, which is executed by the main CPU 63. Note that steps S5801 to S5814 of the RAM monitoring process are executed by the main CPU 63 using a specific control program and specific control data.

First, a monitoring process for the work area 221 for specific control is executed (step S5801). The content of this monitoring process is the same as step S5401 of the RAM monitoring process in the 22nd embodiment (Figure 88). If an abnormality is determined in step S5801 (step S5802: YES), the processes in steps S5805 to S5808 are executed.

If no abnormality is detected in step S5801 (step S5802: NO), the monitoring process for the specific control stack area 222 is executed (step S5803). The content of this monitoring process is the same as step S5403 of the RAM monitoring process in the 22nd embodiment (Figure 88). If an abnormality is detected in step S5803 (step S5804: YES), the processes in steps S5805 to S5808 are executed.

Regarding the processing in steps S5805 to S5808, first, a setting value copy process is performed (step S5805). In this copy process, the information from the setting value counter, used to identify the setting value of the pachinko machine 10 in the specific control work area 221, is stored in a copy area provided in the specific control work area 221. This makes it possible to determine the setting value of the pachinko machine 10 before the error clear process (step S5806) was executed, even if the setting value counter information is cleared to "0" during the subsequent error clear process.

Subsequently, an error clearing process is executed (step S5806). In the error clearing process, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is also cleared to "0". After clearing to "0", initial settings are performed. On the other hand, the work area 223 and the stack area 224 for non-specific control are not cleared to "0". In other words, in the RAM monitoring process in this embodiment, if it is determined that an error has occurred in either the work area 221 for specific control or the stack area 222 for specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is also cleared to "0". This makes it possible to prevent the processing corresponding to specific control from being executed in that state if there is a possibility that some kind of information error has occurred in the work area 221 or the stack area 222 for specific control. Furthermore, even if an information anomaly occurs in the specific control work area 221 or the specific control stack area 222, the non-specific control work area 223 and the non-specific control stack area 224 will not be cleared to "0". This prevents the non-specific control work area 223 and the non-specific control stack area 224 from being cleared to "0" as a result of an information anomaly in the specific control work area 221 or the specific control stack area 222.

Furthermore, if the specific control stack area 222 is cleared to "0", the return address information after the RAM monitoring process is also erased. Therefore, if the specific control stack area 222 is cleared to "0", the system returns uniquely to a predetermined program after completing the process in step S5808. Specifically, the system returns uniquely to the process in step S5013 of the main process (Figure 22). However, the program to which the system returns uniquely is not limited to step S5013; it could also be step S5221 in the timer interrupt process (Figure 86). Also, if the specific control stack area 222 is cleared to "0", the stack pointer of the main CPU 63 is set to the address of the first storage area in the storage order of the specific control stack area 222.

Subsequently, an abnormality command indicating that an abnormal clear process has occurred is transmitted to the audio and light emission control device 81 (step S5807). Upon receiving this abnormality command, the audio and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to a forced clear, and outputs the voice message "Forced clear performed." from the speaker unit 54. Furthermore, the text image "Forced clear performed." is displayed on the pattern display device 41. These notifications are maintained until the power supply to the pachinko machine 10 is stopped, at which point they terminate. However, this is not limited to this configuration; the notifications may also be terminated when the notification termination operation is performed by the administrator of the gaming hall. The notification termination operation may include, for example, pressing the update button 68b or pressing the reset button 68c. By confirming these notifications, the administrator of the gaming hall can understand that the work area 221 and the stack area 222 for specific control have been forcibly cleared.

Subsequently, the setting value update process is executed (step S5808). The processing content of the setting value update process is the same as step S5412 in the RAM monitoring process (Figure 88) in the 22nd embodiment described above.

If no abnormality is detected in both steps S5801 and S5803 (steps S5802 and S5804: NO), monitoring processing for the non-specific control work area 223 is executed (step S5809). The content of this monitoring processing is the same as step S5405 of the RAM monitoring processing in the 22nd embodiment (Figure 88). If an abnormality is detected in step S5809 (step S5810: YES), the non-specific control work area 223 is cleared to "0" and initial settings are performed (step S5811). In this case, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, the calculation result storage area 234, and the management start flag are all cleared to "0". This makes it possible to resolve information abnormalities in the non-specific control work area 223.

On the other hand, in step S5811, the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control are not cleared to "0". This prevents the work area 221, the stack area 222, and the stack area 224 from being cleared to "0" even if an information anomaly occurs in the work area 223 for non-specific control.

Furthermore, in step S5811, the normal counter area 231, the counter area 232 for opening/closing execution mode, the counter area 233 for high-frequency support mode, and the calculation result storage area 234 may be cleared to "0," but the management start flag may not be cleared to "0." Also, in step S5811, the normal counter area 231, the counter area 232 for opening/closing execution mode, the counter area 233 for high-frequency support mode, and the management start flag may be cleared to "0," but the calculation result storage area 234 may not be cleared to "0." Also, in step S5811, the normal counter area 231, the counter area 232 for opening/closing execution mode, and the counter area 233 for high-frequency support mode may be cleared to "0," but the calculation result storage area 234 and the management start flag may not be cleared to "0."

If a negative determination is made in step S5810 or the process in step S5811 is executed, the monitoring process for the non-specific control stack area 224 is executed (step S5812). The content of this monitoring process is the same as step S5407 of the RAM monitoring process in the 22nd embodiment (Figure 88). If an abnormality is determined in step S5812 (step S5813: YES), the non-specific control stack area 224 is cleared to "0" and initialized (step S5814). This makes it possible to resolve the information abnormality in the non-specific control stack area 224.

On the other hand, in step S5814, the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control are not cleared to "0". This prevents the work area 221, the stack area 222, and the work area 223 for non-specific control from being cleared to "0" even if an information anomaly occurs in the stack area 224 for non-specific control.

According to the above configuration, if an abnormality is detected in either the work area 221 for specific control or the stack area 222 for specific control, the work area 221 for specific control is cleared to "0" (excluding the copy area), and the stack area 222 for specific control is also cleared to "0". This prevents the execution of processing corresponding to specific control from proceeding if there is a possibility of some kind of information abnormality in the work area 221 or the stack area 222 for specific control.

Even if an information anomaly occurs in the work area 221 or the stack area 222 for specific control, the work area 223 and the stack area 224 for non-specific control will not be cleared to "0". This prevents the work area 223 and the stack area 224 from being cleared to "0" as a result of an information anomaly in the work area 221 or the stack area 222 for specific control.

Even if an information anomaly occurs in the work area 223 for non-specific control, the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control will not be cleared to "0". This prevents the work area 221, the stack area 222, and the stack area 224 from being cleared to "0" as a result of an information anomaly in the work area 223 for non-specific control.

Even if an information anomaly occurs in the non-specific control stack area 224, the specific control work area 221, the specific control stack area 222, and the non-specific control work area 223 will not be cleared to "0". This prevents the specific control work area 221, the specific control stack area 222, and the non-specific control work area 223 from being cleared to "0" as a result of an information anomaly in the non-specific control stack area 224.

Furthermore, if an information anomaly occurs in the work area 221 for specific control, the work area 221 for specific control may be cleared to "0" except for the copy area, while the stack area 222 for specific control may not be cleared to "0".

Furthermore, if an information anomaly occurs in the specific control stack area 222, the specific control stack area 222 may be cleared to "0," while the specific control work area 221 may not be cleared to "0." In this case, even if the specific control stack area 222 is cleared to "0," the processing in steps S5805 to S5808 may not be executed.

<25th Embodiment>
In this embodiment, the processing configuration for monitoring whether or not an information anomaly has occurred in each area 221 to 224 of the main RAM 65 differs from that of the 22nd embodiment described above. The configurations that differ from those of the 22nd embodiment will be described below. Configurations that are the same as those of the 22nd embodiment will generally not be described.

Figure 93 is a flowchart showing the RAM monitoring process in this embodiment, which is executed by the main CPU 63. Note that steps S5901 to S5908 in the RAM monitoring process are executed by the main CPU 63 using a specific control program and specific control data.

First, a monitoring process for the work area 221 for specific control is executed (step S5901). The content of this monitoring process is the same as step S5401 of the RAM monitoring process in the 22nd embodiment (Figure 88). If an abnormality is determined in step S5901 (step S5902: YES), the processes in steps S5905 to S5908 are executed.

If no abnormality is detected in step S5901 (step S5902: NO), the monitoring process for the specific control stack area 222 is executed (step S5903). The content of this monitoring process is the same as step S5403 of the RAM monitoring process in the 22nd embodiment (Figure 88). If an abnormality is detected in step S5903 (step S5904: YES), the processes in steps S5905 to S5908 are executed.

Regarding the processing in steps S5905 to S5908, first, a setting value copy process is performed (step S5905). In this copy process, the information of the setting value counter, used to identify the setting value of the pachinko machine 10 in the specific control work area 221, is stored in a copy area provided in the specific control work area 221. This makes it possible to determine the setting value of the pachinko machine 10 before the abnormality clear process (step S5906) was executed, even if the setting value counter information is cleared to "0" during the subsequent abnormality clear process.

Subsequently, an error clearing process is executed (step S5906). In the error clearing process, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is also cleared to "0". After clearing to "0", initial settings are performed. On the other hand, the work area 223 and the stack area 224 for non-specific control are not cleared to "0". In other words, in the RAM monitoring process in this embodiment, if it is determined that an error has occurred in either the work area 221 for specific control or the stack area 222 for specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is also cleared to "0". This makes it possible to prevent the processing corresponding to specific control from being executed in that state if there is a possibility that some kind of information error has occurred in the work area 221 or the stack area 222 for specific control. Furthermore, even if an information anomaly occurs in the specific control work area 221 or the specific control stack area 222, the non-specific control work area 223 and the non-specific control stack area 224 will not be cleared to "0". This prevents the non-specific control work area 223 and the non-specific control stack area 224 from being cleared to "0" as a result of an information anomaly in the specific control work area 221 or the specific control stack area 222.

Subsequently, an abnormality command indicating that an abnormality clear process has occurred is sent to the voice and light emission control device 81 (step S5907). Upon receiving the abnormality command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the forced clear of the work area 221 and the stack area 222 for specific control, and outputs the voice message "A forced clear has been performed regarding specific control." from the speaker unit 54. In addition, the character display device 41 displays the text image "A forced clear has been performed regarding specific control." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, at which point they terminate. However, the system is not limited to this, and the notifications may be terminated when the notification termination operation is performed by the administrator of the gaming hall. The notification termination operation may be, for example, pressing the update button 68b or pressing the reset button 68c. By checking the above notification, the administrator of the gaming hall can understand that the work area 221 and the stack area 222 for specific control have been forcibly cleared.

Subsequently, the setting value update process is executed (step S5908). The processing content of the setting value update process is the same as step S5412 in the RAM monitoring process (Figure 88) in the 22nd embodiment described above.

As described above, in the RAM monitoring process executed using the program and data for specific control, information anomalies are monitored for the work area 221 and stack area 222 for specific control, but not for the work area 223 and stack area 224 for non-specific control. Information anomaly monitoring for these non-specific control work areas 223 and stack area 224 is performed in the processing corresponding to the non-specific control where the program and data for non-specific control are used.

Figure 94 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. The management execution process is executed by reading the subroutine program in the management process (Figure 70), similar to the 15th embodiment described above. Furthermore, steps S6001 to S6016 of the management execution process are executed by the main CPU 63 using a program and data for non-specific control.

Steps S6001 to S6008 and S6010 to S6016 execute the same processes as steps S3901 to S3915 of the management execution process (Figure 71) in the 15th embodiment described above. Step S6009 executes a separate monitoring process. During the execution of this separate monitoring process, a subroutine program corresponding to the separate monitoring process, set in the non-specific control program, is executed. During the execution of this subroutine program, information for identifying the return address of the management execution process after the separate monitoring process is written to the non-specific control stack area 224 by a push instruction. When the separate monitoring process finishes, the information for identifying the return address is read out by a pop instruction, and the program returns to the management execution process indicated by that return address.

Figure 95 is a flowchart of the separate monitoring process. Note that steps S6101 to S6108 in the separate monitoring process are executed by the main CPU 63 using a program and data for non-specific control.

First, a monitoring process for the work area 223 for non-specific control is performed (step S6101). The content of this monitoring process is the same as step S5405 of the RAM monitoring process in the 22nd embodiment (Figure 88). If an abnormality is determined in step S6101 (step S6102: YES), the work area 223 for non-specific control is cleared to "0" and initial settings are performed (step S6103). In this case, the normal counter area 231, the counter area 232 for opening/closing execution mode, the counter area 233 for high-frequency support mode, the calculation result storage area 234, and the management start flag are all cleared to "0". This makes it possible to resolve information abnormalities in the work area 223 for non-specific control.

On the other hand, in step S6103, the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control are not cleared to "0". This prevents the work area 221, the stack area 222, and the stack area 224 from being cleared to "0" even if an information anomaly occurs in the work area 223 for non-specific control.

Furthermore, in step S6103, the normal counter area 231, the counter area 232 for opening/closing execution mode, the counter area 233 for high-frequency support mode, and the calculation result storage area 234 may be cleared to "0," but the management start flag may not be cleared to "0." Also, in step S6103, the normal counter area 231, the counter area 232 for opening/closing execution mode, the counter area 233 for high-frequency support mode, and the management start flag may be cleared to "0," but the calculation result storage area 234 may not be cleared to "0." Also, in step S6103, the normal counter area 231, the counter area 232 for opening/closing execution mode, and the counter area 233 for high-frequency support mode may be cleared to "0," but the calculation result storage area 234 and the management start flag may not be cleared to "0."

Subsequently, a clear notification process is executed (step S6104). In the clear notification process, a command indicating that the work area 223 for non-specific control has been cleared to "0" is sent to the voice and light emission control device 81. Upon receiving this command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the forced clearing of the work area 223 for non-specific control, and outputs the voice message "History information has been forcibly cleared." from the speaker unit 54. In addition, the character display device 41 displays the text image "History information has been forcibly cleared." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, at which point they terminate. However, the system is not limited to this, and the notifications may be terminated when the notification termination operation is performed by the administrator of the gaming hall. The notification termination operation may be, for example, pressing the update button 68b or pressing the reset button 68c. By confirming the above notification, the administrator of the gaming hall can understand that the work area 223 for non-specific control has been forcibly cleared.

If a negative determination is made in step S6102 or the process in step S6104 is executed, monitoring of the non-specific control stack area 224 is performed (step S6105). The content of this monitoring process is the same as step S5407 of the RAM monitoring process in the 22nd embodiment (Figure 88). If an abnormality is determined in step S6105 (step S6106: YES), the non-specific control stack area 224 is cleared to "0" and initialized (step S6107). This makes it possible to resolve the information abnormality in the non-specific control stack area 224.

On the other hand, in step S6107, the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control are not cleared to "0". This prevents the work area 221, the stack area 222, and the work area 223 for non-specific control from being cleared to "0" even if an information anomaly occurs in the stack area 224 for non-specific control.

Subsequently, a clear notification process is executed (step S6108). In the clear notification process, a command indicating that the stack area 224 for non-specific control has been cleared to "0" is sent to the voice and light emission control device 81. Upon receiving this command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the forced clearing of the stack area 224 for non-specific control, and outputs the voice message "The stack for non-specific control has been forcibly cleared." from the speaker unit 54. In addition, the character display device 41 displays the text image "The stack for non-specific control has been forcibly cleared." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, at which point they terminate. However, the system is not limited to this, and the notifications may be terminated when the notification termination operation is performed by the administrator of the gaming hall. As an operation to terminate the notification, for example, the update button 68b may be pressed, or the reset button 68c may be pressed. By checking the above notification, the administrator of the gaming hall can understand that the non-specific control stack area 224 has been forcibly cleared.

Furthermore, if the non-specific control stack area 224 is forcibly cleared, the program address in step S6010 of the management execution process (Figure 94) is uniquely set as the return address information after the execution of a separate monitoring process. This allows the management execution process to return to the program it should originally return to, even if the non-specific control stack area 224 is forcibly cleared. Also, if the non-specific control stack area 224 is forcibly cleared, the stack pointer of the main CPU 63 is also set to the address of the first storage area in the storage order of the non-specific control stack area 224.

According to the above configuration, monitoring for information anomalies in the work area 221 and stack area 222 for specific control is performed by the processing corresponding to specific control in the main CPU 63, while monitoring for information anomalies in the work area 223 and stack area 224 for non-specific control is performed by the processing corresponding to non-specific control in the main CPU 63. This not only clearly distinguishes between the areas 221-224 of the main RAM 65 used by the processing corresponding to specific control and the processing corresponding to non-specific control, but also clearly distinguishes between the areas 221-224 of the main RAM 65 that are monitored.

Furthermore, if the work area 223 for non-specific control is cleared to "0", the information of various registers of the main CPU 63 used in the processing corresponding to specific control, which has been saved in the work area 223 for non-specific control, will also be cleared to "0". In this case, even if the processing corresponding to non-specific control finishes and returns to the processing corresponding to specific control, there is a risk that it may not be possible to return to the state before the processing corresponding to non-specific control started. Therefore, if the work area 2223 for non-specific control is cleared to "0", the work area 221 for specific control and the stack area 222 for specific control may also be cleared to "0". In addition, in this configuration, the setting value counter in the work area 221 for specific control will also be cleared to "0", so when returning from the processing corresponding to non-specific control to the processing corresponding to specific control, the setting value update processing may be executed first as the processing corresponding to specific control.

<Embodiment 26>
In this embodiment, the processing configuration for the management process differs from that of the 20th embodiment described above. The configurations that differ from the 20th embodiment will be described below. Configurations identical to those in the 20th embodiment will generally not be described.

Figure 96 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that steps S6201 to S6219 of the management process are executed by the main CPU 63 using a specific control program and specific control data.

First, to prevent the timer interrupt process (Figure 69) from occurring, the interrupt disable setting is configured (step S6201). This prevents the timer interrupt process (Figure 69), which corresponds to specific control, from being interrupted and activated during the management execution process (described later), which corresponds to non-specific control.

Subsequently, the load instruction "LD HL, SP" overwrites the information of the stack pointer of the main CPU 63 in the HL register of the main CPU 63 (step S6202). In this case, since the stack pointer has 16 bits of information and the H and L registers each have 8 bits of information, the 8 consecutive bits from the upper end of the stack pointer information are overwritten in the H register, and the 8 consecutive bits from the lower end of the stack pointer information are overwritten in the L register.

Subsequently, the load instruction "LD (HL), 0" clears the 1-byte storage area corresponding to the stack pointer information stored in the HL register of the main CPU 63 in the specific control stack area 222 to "0" (step S6203). Note that the HL register of the main CPU 63 has been overwritten with the information of the main CPU 63's stack pointer in step S6202, and the main CPU 63's stack pointer information has not been updated until the processing in step S6203 is executed. Therefore, in step S6203, the 1-byte storage area corresponding to the information of the main CPU 63's stack pointer in the specific control stack area 222 is cleared to "0".

Subsequently, the load instruction "LD SP, SP-1" updates the stack pointer information of the main CPU 63 to the address information of the next memory area to be written to in the specific control stack area 222 (step S6204). When using the specific control stack area 222, the information to be stored is stored starting from the memory area at the last address in the specific control stack area 222, and each time information to be stored is added, the storage area to be stored is changed toward the first address in the specific control stack area 222. Therefore, in step S6204, the stack pointer information of the main CPU 63 is updated to the address information corresponding to the memory area with an address one less than the current address in the specific control stack area 222. By executing the process in step S6204, the memory area that was cleared to "0" in step S6203 is set as the next memory area to be stored by the next push instruction, and the memory area that was cleared to "0" in step S6203 is set as the memory area to be read by the next pop instruction.

Subsequently, the WA register of the main CPU 63 is cleared to "0" by the load instruction "LD WA, 0" (step S6205). Then, the BC register of the main CPU 63 is cleared to "0" by the load instruction "LD BC, 0" (step S6206). Furthermore, the DE register of the main CPU 63 is cleared to "0" by the load instruction "LD DE, 0" (step S6207). Also, the HL register of the main CPU 63 is cleared to "0" by the load instruction "LD HL, 0" (step S6208). Finally, the IX register of the main CPU 63 is cleared to "0" by the load instruction "LD IX, 0" (step S6209). And finally, the IY register of the main CPU 63 is cleared to "0" by the load instruction "LD IY, 0" (step S6210).

The main CPU 63 has various general-purpose registers, auxiliary registers, and index registers in addition to the flag register. In this case, steps S6205 to S6210 clear some of these general-purpose registers, auxiliary registers, and index registers—specifically, the WA register, BC register, DE register, HL register, IX register, and IY register—to "0". These WA register, BC register, DE register, HL register, IX register, and IY register are used in the management execution process (step S6212), which is a process corresponding to non-specific control. By clearing these registers to "0" prior to the execution of the management execution process (step S6212), it is possible to return the state of these registers to the state immediately after the power supply to the main CPU 63 begins, before the non-specific control process starts.

Furthermore, the information in the WA, BC, DE, HL, IX, and IY registers before the start of processing corresponding to non-specific control is unnecessary for processing corresponding to specific control after the processing corresponding to the non-specific control has finished. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will arise in the processing corresponding to specific control that resumes after the processing corresponding to non-specific control has finished.

Subsequently, using the "POP PSW" instruction, information is read from the storage area corresponding to the previous write order for the storage area corresponding to the stack pointer information of the main CPU 63 in the specific control stack area 222, and the read information is overwritten in the flag register of the main CPU 63 (step S6211). Immediately before the execution of the pop instruction in step S6211, the information of the stack pointer of the main CPU 63 corresponds to the storage area corresponding to the next write order for the storage area in the specific control stack area 222 that was cleared to "0" in step S6203. Therefore, the storage area corresponding to the previous write order for the storage area corresponding to the stack pointer information of the main CPU 63 in the specific control stack area 222 is the storage area that was cleared to "0" in step S6203. Then, by overwriting the flag register of the main CPU 63 with the information read from this storage area, the flag register is cleared to "0". Furthermore, each memory area in the stack area 222 for specific control has an information capacity of 8 bits (1 byte), and the flag register of the main CPU 63 also has an information capacity of 8 bits (1 byte). By clearing the flag register to "0" prior to the execution of the management execution process (step S6212), which is a process corresponding to non-specific control, it is possible to set the state of the flag register to the state immediately after the supply of operating power to the main CPU 63 begins, before the process corresponding to non-specific control starts.

Subsequently, the program for the subroutine corresponding to the management execution process set in the non-specific control program is read, and the management execution process is started (step S6212). In this case, information for identifying the return address of the management process after the execution of the management execution process is written to the specific control stack area 222 by a push instruction. Then, when the management execution process is completed, the information for identifying the return address is read by a pop instruction, and the program returns to the management process indicated by that return address.

The processing content of the management execution process is the same as that of the management execution process in the 20th embodiment described above (Figure 82). Therefore, after the check process is completed in the management execution process, the WA register, BC register, DE register, HL register, IX register, and IY register are cleared to "0". This ensures that these registers are cleared to "0" prior to the return from the processing corresponding to non-specific control to the processing corresponding to specific control. This makes it possible to set the state of these registers to the state immediately after the supply of operating power to the main CPU 63 begins, before returning to the processing corresponding to specific control.

After the management execution process is completed and the program returns to the management process, a process is executed to clear the flag register of the main CPU 63 to "0". Specifically, first, a "PUSH HL" instruction is used to save the information of the HL register of the main CPU 63 to the specific control stack area 222 (step S6213). After the execution of this instruction, the information in the main CPU 63's stack pointer corresponds to the information in the next write order to the storage area where the HL register information was saved in the specific control stack area 222.

Subsequently, the load instruction "LD HL, SP" overwrites the information of the stack pointer of the main CPU 63 in the HL register of the main CPU 63 (step S6214). In this case, since the stack pointer has 16 bits of information and the H and L registers each have 8 bits of information, the 8 consecutive bits from the upper end of the stack pointer information are overwritten in the H register, and the 8 consecutive bits from the lower end of the stack pointer information are overwritten in the L register.

Subsequently, the load instruction "LD (HL), 0" clears the 1-byte storage area corresponding to the stack pointer information stored in the HL register of the main CPU 63 in the specific control stack area 222 to "0" (step S6215). Note that the HL register of the main CPU 63 has been overwritten with the information of the main CPU 63's stack pointer in step S6214, and the main CPU 63's stack pointer information has not been updated by the time the processing in step S6215 is executed. Therefore, in step S6215, the 1-byte storage area corresponding to the information of the main CPU 63's stack pointer in the specific control stack area 222 is cleared to "0".

Subsequently, the load instruction "LD SP, SP-1" updates the stack pointer information of the main CPU 63 to the address information of the next memory area to be written to in the specific control stack area 222 (step S6216). When using the specific control stack area 222, the information to be stored is stored starting from the memory area at the last address in the specific control stack area 222, and each time information to be stored is added, the storage area to be stored is changed toward the first address in the specific control stack area 222. Therefore, in step S6216, the stack pointer information of the main CPU 63 is updated to the address information corresponding to the memory area with an address one less than the current address in the specific control stack area 222. By executing the process in step S6216, the memory area that was cleared to "0" in step S6215 is set as the next memory area to be stored by the next push instruction, and the memory area that was cleared to "0" in step S6215 is set as the memory area to be read by the next pop instruction.

Subsequently, using the "POP PSW" instruction, information is read from the storage area corresponding to the previous write order for the storage area in the specific control stack area 222, and the read information is overwritten in the flag register of the main CPU 63 (step S6217). Immediately before the execution of the pop instruction in step S6217, the information of the main CPU 63's stack pointer corresponds to the information of the next write order for the storage area in the specific control stack area 222 that was cleared to "0" in step S6215. Therefore, the storage area corresponding to the previous write order for the storage area in the specific control stack area 222 that corresponds to the storage area in the specific control stack area 222 that was cleared to "0" in step S6215 is the storage area in the specific control stack area 222. Then, by overwriting the flag register of the main CPU 63 with the information read from this storage area, the flag register is cleared to "0". Furthermore, each memory area in the specific control stack area 222 holds 8 bits (1 byte) of information, and the flag register of the main CPU 63 also holds 8 bits (1 byte) of information. By clearing the flag register to "0" after the execution of the management execution process (step S6212), which is a process corresponding to non-specific control, the state of the flag register can be restored to the state immediately after the non-specific control process is completed and power supply to the main CPU 63 begins. Also, when the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the previous memory area in the write order of the specific control stack area 222.

Subsequently, the "POP HL" instruction restores the information from the HL register, which was saved in the specific control stack area 222 in step S6213, to the HL register of the main CPU 63 (step S6218). Since the HL register is cleared to "0" just before the management execution process (step S6212) ends, in step S6213, this "0" cleared information is saved in the specific control stack area 222, and in step S6218, this "0" cleared information is restored to the HL register of the main CPU 63. As a result, the HL register of the main CPU 63 is also cleared to "0". Furthermore, when the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the memory area two entries prior in the write order in the specific control stack area 222.

Subsequently, the system switches from a state where timer interrupt processing (Figure 69) is prohibited to a state where it is permitted by setting the interrupt permission (step S6219). This enables the execution of a new timer interrupt process.

According to the above configuration, in addition to the effects described in the 20th embodiment, the following effects can be achieved.

This configuration clears the flag register of the main CPU 63 to "0" when a process corresponding to a specific control is initiated from a situation where a process corresponding to a specific control is being executed. This eliminates the need to save the flag register information used by the process corresponding to the specific control in the main RAM 65 while the process corresponding to the non-specific control is being executed. Therefore, there is no need to allocate capacity for saving this information.

Furthermore, the configuration also clears the flag register of the main CPU 63 to "0" when returning to a process corresponding to a specific control from a process corresponding to a non-specific control. This makes it possible to restore the state of the flag register to the state it was in immediately before the non-specific control process began when returning to a process corresponding to a specific control.

The state in which the flag register is cleared to "0" indicates that power supply to the MPU 62 has started. This simplifies the processing configuration for setting the flag register to a predetermined state when starting processing corresponding to non-specific control and when returning to processing corresponding to specific control.

The information in the flag register of the main CPU 63 before the start of processing corresponding to non-specific control is information that is not used in the processing corresponding to specific control after the processing corresponding to non-specific control has finished. This makes it possible to ensure that even if the flag register is cleared to "0" when processing corresponding to non-specific control starts, it does not affect the processing corresponding to specific control after the processing corresponding to non-specific control has finished.

This configuration clears a predetermined memory area in the specific control stack area 222 to "0," and then overwrites the information of that "0"-cleared memory area in the flag register using a pop instruction, thereby clearing the flag register to "0." This makes it possible to clear the flag register to "0" even in configurations where directly clearing the flag register to "0" using a load instruction is restricted.

Alternatively, instead of clearing the flag register to "0," the flag register may be initialized. That is, when power is supplied to the MPU 62, the flag register of the main CPU 63 is initially cleared to "0," and then the information is set to its initial state. Steps S6202 to S6204 and S6211 may be configured to set the flag register to this initial state. In this case, by configuring steps S6213 to S6218 to also set the flag register to the initial state, it becomes possible to restore the state of the flag register to the state immediately before the start of the non-specific control processing when returning to processing corresponding to specific control.

Furthermore, in steps S6202 to S6204 and S6211, instead of clearing the flag register of the main CPU 63 to "0", the flag register may be set to "1". In this case, by setting all flag registers to "1" in steps S6213 to S6218, it becomes possible to restore the state of the flag register to the state immediately before the start of the non-specific control processing when returning to the processing corresponding to the specific control.

Alternatively, instead of the processing in steps S6202 to S6204 and S6211, the flag register of the main CPU 63 may be directly cleared to "0" by a load instruction, "LD PSW, 0". Also, instead of the processing in steps S6213 to S6218, the flag register of the main CPU 63 may be directly cleared to "0" by a load instruction, "LD PSW, 0".

Alternatively, instead of executing the processes in steps S6213 and S6218, the HL register may be cleared to "0" by a load instruction, "LD HL, 0". Even in this case, it is possible to restore the state of the HL register to the state immediately before the management execution process, which corresponds to non-specific control, is executed.

Furthermore, instead of the configuration in which the flag register clearing process is performed by a process corresponding to a specific control, it may be configured in which it is performed by a process corresponding to a non-specific control.

<Embodiment 27>
In this embodiment, the processing configuration for the management process differs from that of the 20th embodiment described above. The configurations that differ from the 20th embodiment will be described below. Configurations identical to those in the 20th embodiment will generally not be described.

Figure 97 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that steps S6301 to S6323 of the management process are executed by the main CPU 63 using a specific control program and specific control data.

First, to prevent the timer interrupt process (Figure 69) from occurring, the interrupt disable setting is configured (step S6301). This prevents the timer interrupt process (Figure 69), which corresponds to specific control, from being interrupted and activated during the management execution process (described later), which corresponds to non-specific control.

Subsequently, using the "PUSH AF" instruction, the information in the A register and flag register of the main CPU 63 is saved to the memory area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the memory area in the next write order relative to that memory area (step S6302). Since the A register and flag register of the main CPU 63 each contain 8 bits (1 byte) of information, the information in the A register and flag register are saved individually to two memory areas with consecutive addresses. When the above push instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the memory area two write orders later in the specific control stack area 222.

Subsequently, using the "POP HL" instruction, the information of the A register and the flag register, which were saved in the specific control stack area 222 in step S6302, is overwritten in the HL register of the main CPU 63 (step S6303). In this case, the information of the A register saved in the specific control stack area 222 is overwritten in the H register of the main CPU 63, and the information of the flag register saved in the specific control stack area 222 is overwritten in the L register of the main CPU 63. The H register and L register of the main CPU 63 each hold 8 bits (1 byte) of information. When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the memory area two entries prior in the write order in the specific control stack area 222.

Subsequently, the load instruction "LD A, 0" clears the A register of the main CPU 63 to "0" (step S6304). Then, the load instruction "LD L, A" overwrites the information in the A register of the main CPU 63 with the L register of the main CPU 63 (step S6305), and the load instruction "LD H, A" overwrites the information in the A register of the main CPU 63 with the H register of the main CPU 63 (step S6306). Since the A register was cleared to "0" in step S6304, overwriting the information in the L register and H register respectively results in both the L register and H register being cleared to "0".

Subsequently, the "PUSH HL" instruction is used to save the information in the HL register (i.e., the H register and L register) of the main CPU 63 to the storage area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the storage area corresponding to the next write order (step S6307). Since the H register and L register of the main CPU 63 each contain 8 bits (1 byte) of information, the information in the H register and L register are saved individually to two consecutively addressed storage areas. When the above push instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the storage area two write orders later in the specific control stack area 222.

Subsequently, the BC register of the main CPU 63 is cleared to "0" by the load instruction "LD BC, 0" (step S6308). Then, the DE register of the main CPU 63 is cleared to "0" by the load instruction "LD DE, 0" (step S6309). Furthermore, the IX register of the main CPU 63 is cleared to "0" by the load instruction "LD IX, 0" (step S6310). Finally, the IY register of the main CPU 63 is cleared to "0" by the load instruction "LD IY, 0" (step S6311).

The main CPU 63 has various general-purpose registers, auxiliary registers, and index registers in addition to the flag register. In this case, steps S6308 to S6311 clear some of these general-purpose registers, auxiliary registers, and index registers—specifically the BC register, DE register, IX register, and IY register—to "0". Also, in steps S6305 and S6306, the HL register is cleared to "0". These BC register, DE register, HL register, IX register, and IY register are used in the management execution process (step S6313), which is a process corresponding to non-specific control. By clearing these registers to "0" prior to the execution of the management execution process (step S6313), it is possible to return the state of these registers to the state immediately after the power supply to the main CPU 63 begins, before the non-specific control process starts.

Furthermore, the information in the BC, DE, HL, IX, and IY registers before the start of processing corresponding to non-specific control is unnecessary for processing corresponding to specific control after the processing corresponding to the non-specific control has finished. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will arise in the processing corresponding to specific control that resumes after the processing corresponding to non-specific control has finished.

Subsequently, using the "POP AF" command, the information from the H register and L register, which were saved in the specific control stack area 222 in step S6307, is overwritten in the A register and flag register of the main CPU 63 (step S6312). In this case, the information from the H register saved in the specific control stack area 222 is overwritten in the A register of the main CPU 63, and the information from the L register saved in the specific control stack area 222 is overwritten in the flag register of the main CPU 63. Since the information from the H register and L register saved in the specific control stack area 222 is all "0", the execution of the process in step S6312 clears the A register of the main CPU 63 to "0", and also clears the flag register of the main CPU 63 to "0". This makes it possible to set the state of the flag register to the state immediately after the supply of operating power to the main CPU 63 begins, before the processing corresponding to non-specific control begins. Furthermore, when the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the second-to-last memory area in the specific control stack area 222.

Subsequently, the program for the subroutine corresponding to the management execution process set in the non-specific control program is read, and the management execution process is started (step S6313). In this case, information for identifying the return address of the management process after the execution of the management execution process is written to the specific control stack area 222 by a push instruction. Then, when the management execution process finishes, the information for identifying the return address is read by a pop instruction, and the program returns to the management process indicated by that return address.

Furthermore, after the check process is completed during the management execution process, the BC register, DE register, HL register, IX register, and IY register are cleared to "0". This ensures that these registers are cleared to "0" prior to the return from a process corresponding to non-specific control to a process corresponding to specific control. This allows the state of these registers to be the same as immediately after the power supply to the main CPU 63 begins, before returning to the process corresponding to specific control.

After the management execution process is completed and the program returns to the management process, a process is executed to clear the flag register of the main CPU 63 to "0". Specifically, first, a "PUSH HL" instruction is used to save the information of the HL register of the main CPU 63 to the specific control stack area 222 (step S6314). After the execution of this push instruction, the information in the main CPU 63's stack pointer corresponds to the information in the next write order to the storage area where the HL register information was saved in the specific control stack area 222.

Subsequently, using the "PUSH AF" instruction, the information in the A register and flag register of the main CPU 63 is saved to the memory area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the memory area in the next write order relative to that memory area (step S6315). Since the A register and flag register of the main CPU 63 each contain 8 bits (1 byte) of information, the information in the A register and flag register are saved individually to two memory areas with consecutive addresses. When the above push instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the memory area two write orders later in the specific control stack area 222.

Subsequently, using the "POP HL" instruction, the information of the A register and the flag register, which were saved in the specific control stack area 222 in step S6315, is overwritten in the HL register of the main CPU 63 (step S6316). In this case, the information of the A register saved in the specific control stack area 222 is overwritten in the H register of the main CPU 63, and the information of the flag register saved in the specific control stack area 222 is overwritten in the L register of the main CPU 63. The H register and L register of the main CPU 63 each hold 8 bits (1 byte) of information. When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the memory area two entries prior in the write order in the specific control stack area 222.

Subsequently, the load instruction "LD A, 0" clears the A register of the main CPU 63 to "0" (step S6317). Then, the load instruction "LD L, A" overwrites the information in the A register of the main CPU 63 with the L register of the main CPU 63 (step S6318), and the load instruction "LD H, A" overwrites the information in the A register of the main CPU 63 with the H register of the main CPU 63 (step S6319). Since the A register was cleared to "0" in step S6317, overwriting the information in the L register and H register respectively results in both the L register and H register being cleared to "0".

Subsequently, the "PUSH HL" instruction is used to save the information in the HL register (i.e., the H register and L register) of the main CPU 63 to the storage area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the storage area corresponding to the next write order (step S6320). Since the H register and L register of the main CPU 63 each contain 8 bits (1 byte) of information, the information in the H register and L register are saved individually to two consecutive storage areas. When the above push instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the storage area two write orders later in the specific control stack area 222.

Subsequently, using the "POP AF" command, the information from the H register and L register, which were saved in the special control stack area 222 in step S6320, is overwritten in the A register and flag register of the main CPU 63 (step S6321). In this case, the information from the H register saved in the special control stack area 222 is overwritten in the A register of the main CPU 63, and the information from the L register saved in the special control stack area 222 is overwritten in the flag register of the main CPU 63. Since the information from the H register and L register saved in the special control stack area 222 is all "0", the execution of the process in step S6321 results in the A register of the main CPU 63 being cleared to "0", and the flag register of the main CPU 63 being cleared to "0". By clearing the flag register to "0" after the execution of the management execution process (step S6313), which is a process corresponding to non-specific control, the state of the flag register can be restored to the state immediately after the non-specific control process is completed and power supply to the main CPU 63 is started. When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the memory area two entries prior in the write order of the stack area 222 for specific control.

Subsequently, the "POP HL" instruction restores the information from the HL register, which was saved in the specific control stack area 222 in step S6314, to the HL register of the main CPU 63 (step S6322). Since the HL register is cleared to "0" just before the management execution process (step S6313) ends, in step S6314, this "0" cleared information is saved in the specific control stack area 222, and in step S6322, this "0" cleared information is restored to the HL register of the main CPU 63. As a result, the HL register of the main CPU 63 is also cleared to "0". Furthermore, when the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the memory area two entries prior in the write order in the specific control stack area 222.

Subsequently, the interrupt enable setting is performed (step S6323) to switch from a state where timer interrupt processing (Figure 69) is prohibited to a state where it is enabled. This makes it possible to execute a new timer interrupt process.

According to the above configuration, it becomes possible to clear the flag register of the main CPU 63 to "0" without executing the process of clearing a predetermined memory area in the specific control stack area 222 to "0" using a load instruction. This makes it possible to clear the flag register of the main CPU 63 to "0" even in configurations where clearing a predetermined memory area in the specific control stack area 222 to "0" using a load instruction is restricted.

Alternatively, instead of clearing the flag register to "0", the flag register may be initialized. That is, when power is supplied to the MPU 62, the flag register of the main CPU 63 is initially cleared to "0" and then configured to return to its initial state. Steps S6302 to S6307 and S6312 may be configured to set the flag register to this initial state. In this case, by configuring steps S6314 to S6322 to also set the flag register to the initial state, it becomes possible to restore the flag register to the state immediately before the start of the non-specific control processing when returning to the processing corresponding to the specific control.

Furthermore, in steps S6302 to S6307 and S6312, instead of clearing the flag register of the main CPU 63 to "0", the flag register may be set to "1". In this case, by setting all flag registers to "1" in steps S6314 to S6322 as well, it becomes possible to restore the state of the flag registers to the state immediately before the start of the non-specific control process when returning to the process corresponding to the specific control.

Furthermore, the process may be configured so that steps S6302 and S6303 are not executed. In this case, the processing configuration can be simplified.

Furthermore, the process in steps S6315 and S6316 may be omitted. In this case, the processing configuration can be simplified.

Alternatively, instead of executing the processing in steps S6302 to S6306, the flag register of the main CPU 63 may be cleared to "0" by a load instruction using "LD HL, 0". This is done by first clearing the HL register to "0" using a push instruction, then saving the cleared HL register to the specific control stack area 222 using a push instruction, and finally restoring the saved information to the AF register using a pop instruction.

Furthermore, instead of the configuration in which the flag register clearing process is performed by a process corresponding to a specific control, it may be configured in which it is performed by a process corresponding to a non-specific control.

<28th Embodiment>
In this embodiment, the processing configuration for the management process differs from that of the 15th embodiment described above. The configurations that differ from those of the 15th embodiment will be described below. Configurations that are identical to those of the 15th embodiment will generally not be described.

Figure 98 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that steps S6401 to S6416 of the management process are executed by the main CPU 63 using a specific control program and specific control data.

First, to prevent the timer interrupt process (Figure 69) from occurring, the interrupt disable setting is configured (step S6401). This prevents the timer interrupt process (Figure 69), which corresponds to specific control, from being interrupted and activated during the management execution process (described later), which corresponds to non-specific control.

Subsequently, using the "PUSH WA" instruction, the information in the WA register (i.e., the W register and A register) of the main CPU 63 is saved to the storage area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the storage area corresponding to the next write order (step S6402). Since the W register and A register of the main CPU 63 each contain 8 bits (1 byte) of information, the information in the W register and A register is saved individually to two consecutive storage areas. When the above push instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the storage area two write orders later in the specific control stack area 222.

Subsequently, the load instruction "LD A, PSW" overwrites the information in the flag register of the main CPU 63 with the A register of the main CPU 63 (step S6403). In this case, both the flag register and the A register have an information capacity of 8 bits (1 byte). Then, the load instruction "LD (_FGBUF), A" saves the information in the A register of the main CPU 63 to the FG buffer set in the work area 221 for specific control (step S6404). Since the A register was overwritten with the information from the flag register in step S6403, when step S6404 is executed, the information from the flag register is saved in the work area 221 for specific control.

Subsequently, using the "POP WA" instruction, the information of the WA register, which was saved in the specific control stack area 222 in step S6402, is restored to the WA register of the main CPU 63 (step S6405). This makes it possible to restore the state of the A register to its state before the save, even if the A register was used to save the flag register information to the specific control work area 221. When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the memory area two entries prior in the write order in the specific control stack area 222.

Subsequently, the program for the subroutine corresponding to the management execution process set in the non-specific control program is read, and the management execution process is started (step S6406). In this case, information for identifying the return address of the management process after the execution of the management execution process is written to the specific control stack area 222 by a push instruction. Then, when the management execution process finishes, the information for identifying the return address is read by a pop instruction, and the program returns to the management process indicated by that return address.

The processing content of the management execution process is the same as that of the management execution process in the 15th embodiment described above (Figure 71). Therefore, before the check process begins in the management execution process, the information from the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the non-specific control work area 223. After the check process is completed in the management execution process, the information saved in the non-specific control work area 223 is restored to the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63. This makes it possible to maintain the same state for the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 before and after the check process.

However, the configuration is not limited to this. The processing content of the management execution process may be the same as that of the management execution process in the 17th embodiment (Figure 78), the same as that of the management execution process in the 18th embodiment (Figure 79), or the same as that of the management execution process in the 19th embodiment (Figure 80).

After the management execution process is completed and the program returns to the management processing program, a process is executed to restore the flag register information of the main CPU 63 to its state before the management execution process was performed. Specifically, first, a "PUSH HL" instruction is used to save the information of the HL register of the main CPU 63 to the specific control stack area 222 (step S6407). After the execution of this push instruction, the stack pointer information of the main CPU 63 becomes the information corresponding to the next write order in the storage area where the HL register information was saved in the specific control stack area 222.

Subsequently, a "PUSH WA" instruction is used to save the information in the WA register of the main CPU 63 to the specific control stack area 222 (step S6408). After the execution of this push instruction, the information in the main CPU 63's stack pointer corresponds to the information in the next write order to the storage area where the WA register information was saved in the specific control stack area 222.

Subsequently, the load instruction "LD HL, SP" overwrites the information of the stack pointer of the main CPU 63 in the HL register of the main CPU 63 (step S6409). In this case, since the stack pointer has 16 bits of information and the H and L registers each have 8 bits of information, the 8 consecutive bits from the upper end of the stack pointer information are overwritten in the H register, and the 8 consecutive bits from the lower end of the stack pointer information are overwritten in the L register.

Subsequently, the load instruction "LD A, (_FGBUF)" overwrites the information of the flag register saved in the FG buffer in the specific control work area 221 in step S6406 with the A register of the main CPU 63 (step S6410). Then, the load instruction "LD (HL), A" stores the information of the A register of the main CPU 63 in a 1-byte storage area corresponding to the stack pointer information stored in the HL register of the main CPU 63 in the specific control stack area 222 (step S6411). As a result, the information of the flag register saved in the FG buffer in the specific control work area 221 in step S6404 is saved in the specific control stack area 222.

Subsequently, the load instruction "LD SP, SP-1" updates the stack pointer information of the main CPU 63 to the address information of the next memory area to be written to in the specific control stack area 222 (step S6412). When using the specific control stack area 222, the information to be stored is stored starting from the memory area at the last address in the specific control stack area 222, and each time information to be stored is added, the storage area to be stored is changed toward the first address in the specific control stack area 222. Therefore, in step S6412, the stack pointer information of the main CPU 63 is updated to the address information corresponding to the memory area with an address one less than the current address in the specific control stack area 222. By executing the process in step S6412, the memory area where the A register information was saved in step S6411 is set as the next memory area to be stored by the next push instruction, and the memory area where the A register information was saved in step S6411 is set as the memory area to be read by the next pop instruction.

Subsequently, using the "POP PSW" instruction, information is read from the storage area corresponding to the previous write order in the stack area 222 for specific control, and the read information is overwritten in the flag register of the main CPU 63 (step S6413). Immediately before the execution of the pop instruction in step S6413, the information of the main CPU 63's stack pointer corresponds to the storage area corresponding to the next write order in the storage area where the A register information was saved in step S6411. Therefore, the storage area corresponding to the previous write order in the storage area corresponding to the stack pointer information of the main CPU 63 in the stack area 222 for specific control is the storage area where the A register information was saved in step S6411. Then, by overwriting the flag register of the main CPU 63 with the information read from this storage area, the flag register information saved in the FG buffer in the work area 221 for specific control in step S6404 is restored to the flag register of the main CPU 63. When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the previous memory area in the specific control stack area 222.

Subsequently, using the "POP WA" instruction, the information in the WA register, which was saved in the specific control stack area 222 in step S6408, is restored to the WA register of the main CPU 63 (step S6414). When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the second-to-last memory area in the specific control stack area 222's write order. Furthermore, using the "POP HL" instruction, the information in the HL register, which was saved in the specific control stack area 222 in step S6407, is restored to the HL register of the main CPU 63 (step S6415). When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the second-to-last memory area in the specific control stack area 222's write order.

Subsequently, the interrupt enable setting is performed (step S6416) to switch from a state where timer interrupt processing (Figure 69) is prohibited to a state where it is enabled. This makes it possible to execute a new timer interrupt process.

According to the above configuration, when a process corresponding to a specific control is initiated from a situation where a process corresponding to a specific control is being executed, the information in the flag register of the main CPU 63 can be saved to the work area 221 for the specific control, rather than the stack area 222 for the specific control. Then, when the process returns to the process corresponding to the specific control from a situation where a process corresponding to a non-specific control is being executed, the information in the flag register saved in the work area 221 for the specific control is restored to the flag register of the main CPU 63. This means that the information can be restored to the flag register of the main CPU 63 from the storage area of the work area 221 specified in the program, without needing to refer to the stack pointer information of the main CPU 63. Therefore, even if the stack pointer information of the main CPU 63 is overwritten due to noise or other reasons, the information can still be restored to the flag register of the main CPU 63.

Furthermore, the process of saving the flag register information to the main RAM 65 may be performed by a process corresponding to a specific control, instead of being performed by a process corresponding to a specific control. Also, the process of restoring the flag register information saved in the main RAM 65 to the flag register of the main CPU 63 may be performed by a process corresponding to a specific control, instead of being performed by a process corresponding to a specific control.

<Embodiment 29>
In this embodiment, the processing configuration for the management process differs from that of the 15th embodiment described above. The configurations that differ from those of the 15th embodiment will be described below. Configurations that are identical to those of the 15th embodiment will generally not be described.

Figure 99 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that steps S6501 to S6519 of the management process are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt disabling is performed to prevent the timer interrupt process (Figure 69) from occurring (step S6501). This prevents the timer interrupt process (Figure 69), which corresponds to specific control, from being interrupted and activated during the management execution process (described later), which corresponds to non-specific control.

Subsequently, the "PUSH HL" instruction is used to save the information in the HL register (i.e., the H register and L register) of the main CPU 63 to the storage area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the storage area corresponding to the next write order (step S6502). Since the H register and L register of the main CPU 63 each contain 8 bits (1 byte) of information, the information in the H register and L register is saved individually to two consecutive storage areas. When the above push instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the storage area two write orders later in the specific control stack area 222.

Subsequently, using the "PUSH AF" instruction, the information in the A register and flag register of the main CPU 63 is saved to the memory area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the memory area in the next write order relative to that memory area (step S6503). Since the A register and flag register of the main CPU 63 each contain 8 bits (1 byte) of information, the information in the A register and flag register are saved individually to two memory areas with consecutive addresses. When the above push instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the memory area two write orders later in the specific control stack area 222.

Subsequently, using the "POP HL" instruction, the information of the A register and the flag register, which were saved in the specific control stack area 222 in step S6503, is overwritten in the HL register of the main CPU 63 (step S6504). In this case, the information of the A register saved in the specific control stack area 222 is overwritten in the H register of the main CPU 63, and the information of the flag register saved in the specific control stack area 222 is overwritten in the L register of the main CPU 63. When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the memory area two entries prior in the write order in the specific control stack area 222.

Subsequently, the load instruction "LD A, L" overwrites the information in the L register of the main CPU 63 with the A register of the main CPU 63 (step S6505). Since the L register was overwritten with the flag register information of the main CPU 63 in step S6504, overwriting the A register with the L register information results in the A register being overwritten with the flag register information. Then, the load instruction "LD (_FGBUF), A" saves the information in the A register of the main CPU 63 to the FG buffer set in the specific control work area 221 (step S6506). Since the A register was overwritten with the flag register information in step S6505, the execution of step S6506 results in the flag register information being saved in the specific control work area 221.

Subsequently, the "PUSH HL" instruction is used to save the information in the HL register (i.e., the H register and L register) of the main CPU 63 to the storage area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the storage area corresponding to the next write order (step S6507). In this case, since the information of the A register and the flag register has been overwritten in step S6504, step S6507 saves the information of the A register and the flag register to the specific control stack area 222. Note that when the above push instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the storage area two write orders later in the specific control stack area 222.

Subsequently, using the "POP AF" instruction, the information of the H register and L register, which were saved in the special control stack area 222 in step S6507, is overwritten in the A register and flag register of the main CPU 63 (step S6508). In this case, the information of the H register saved in the special control stack area 222 is overwritten in the A register of the main CPU 63, and the information of the L register saved in the special control stack area 222 is overwritten in the flag register of the main CPU 63. The information of the H register saved in the special control stack area 222 is the information of the A register at the time of step S6503, and the information of the L register saved in the special control stack area 222 is the information of the flag register at the time of step S6503. Therefore, when the process in step S6508 is executed, the state of the A register and flag register of the main CPU 63 is restored to the state at the time of step S6503. Furthermore, when the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the two previous memory areas in the specific control stack area 222.

Subsequently, using the "POP HL" instruction, the information of the HL register, which was saved in the specific control stack area 222 in step S6502, is restored to the HL register of the main CPU 63 (step S6509). This restores the state of the HL register of the main CPU 63 to the state it was in at step S6502. When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the memory area two entries prior in the write order in the specific control stack area 222.

Subsequently, the program for the subroutine corresponding to the management execution process set in the non-specific control program is read, and the management execution process is started (step S6510). In this case, information for identifying the return address of the management process after the execution of the management execution process is written to the specific control stack area 222 by a push instruction. Then, when the management execution process is completed, the information for identifying the return address is read by a pop instruction, and the program returns to the management process indicated by that return address.

Furthermore, during the management execution process, before the check process begins, the information from the BC, DE, HL, IX, and IY registers of the main CPU 63 is saved to the non-specific control work area 223. After the check process is completed during the management execution process, the information saved in the non-specific control work area 223 is restored to the BC, DE, HL, IX, and IY registers of the main CPU 63. This makes it possible to maintain the same state for the BC, DE, HL, IX, and IY registers of the main CPU 63 before and after the check process.

However, the configuration is not limited to this. The processing content of the management execution process may be the same as that of the management execution process in the 17th embodiment (Figure 78), the same as that of the management execution process in the 18th embodiment (Figure 79), or the same as that of the management execution process in the 19th embodiment (Figure 80).

After the management execution process is completed and the program returns to the management process, a process is executed to restore the flag register information of the main CPU 63 to its state before the management execution process was performed. Specifically, first, a "PUSH HL" instruction is used to save the information of the HL register of the main CPU 63 to the specific control stack area 222 (step S6511). After the execution of this instruction, the stack pointer information of the main CPU 63 becomes the information corresponding to the next write order in the storage area where the HL register information was saved in the specific control stack area 222.

Subsequently, using the "PUSH AF" instruction, the information in the A register and flag register of the main CPU 63 is saved to the memory area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the memory area in the next write order relative to that memory area (step S6512). Since the A register and flag register of the main CPU 63 each contain 8 bits (1 byte) of information, the information in the A register and flag register are saved individually to two memory areas with consecutive addresses. When the above push instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the memory area two write orders later in the specific control stack area 222.

Subsequently, using the "POP HL" instruction, the information of the A register and the flag register, which were saved in the specific control stack area 222 in step S6512, is overwritten in the HL register of the main CPU 63 (step S6513). In this case, the information of the A register saved in the specific control stack area 222 is overwritten in the H register of the main CPU 63, and the information of the flag register saved in the specific control stack area 222 is overwritten in the L register of the main CPU 63. When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to the information corresponding to the memory area two entries prior in the write order in the specific control stack area 222.

Subsequently, the load instruction "LD A, (_FGBUF)" overwrites the flag register information from step S6503, which was saved in the FG buffer in the specific control work area 221 in step S6506, into the A register of the main CPU 63 (step S6514). Then, the load instruction "LD L, A" overwrites the L register of the main CPU 63 with the information from the A register (step S6515). Since the flag register information of the main CPU 63 from step S6503 was restored to the A register in step S6514, overwriting the L register with the A register information results in the L register being overwritten with the flag register information from step S6503.

Subsequently, using the "PUSH HL" instruction, the information of the HL register (i.e., the H register and L register) of the main CPU 63 is saved to the storage area corresponding to the current stack pointer information of the main CPU 63 in the specific control stack area 222, and to the storage area corresponding to the next write order (step S6516). In this case, since the information of the A register at the time of step S6512 was overwritten in step S6513, step S6516 saves the information of the A register to the specific control stack area 222. Also, since the information of the flag register at the time of step S6503 was overwritten in step S6515, step S6516 saves the information of the flag register to the specific control stack area 222.

Subsequently, using the "POP AF" instruction, the information from the H register and L register, which were saved in the specific control stack area 222 in step S6516, is overwritten in the A register and flag register of the main CPU 63 (step S6517). In this case, the information from the H register saved in the specific control stack area 222 is overwritten in the A register of the main CPU 63, and the information from the L register saved in the specific control stack area 222 is overwritten in the flag register of the main CPU 63. The information from the H register saved in the specific control stack area 222 is the information from the A register at the time of step S6512, and the information from the L register saved in the specific control stack area 222 is the information from the flag register at the time of step S6503. Therefore, when the process in step S6517 is executed, the state of the A register of the main CPU 63 returns to the state at step S6512, and the state of the flag register returns to the state at the time of step S6503.

Incidentally, the A register of the main CPU 63 is not used in the management execution process. Therefore, the state of the A register at step S6512 is the same as the state of the A register at step S6508, and the state of the A register at step S6508 is the same as the state of the A register at step S6503. Therefore, when the process in step S6517 is executed, the state of the A register and flag register of the main CPU 63 returns to the state at step S6503. Furthermore, when the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the two previous memory areas in the write order of the specific control stack area 222.

Subsequently, using the "POP HL" instruction, the information of the HL register, which was saved in the specific control stack area 222 in step S6511, is restored to the HL register of the main CPU 63 (step S6518). This restores the state of the main CPU 63's HL register to the state it was in at step S6511. When the above pop instruction is executed, the stack pointer information of the main CPU 63 is updated to reflect the information corresponding to the memory area two entries prior in the write order in the specific control stack area 222.

Subsequently, the system switches from a state where timer interrupt processing (Figure 69) is prohibited to a state where it is permitted by setting the interrupt permission (step S6519). This enables the execution of a new timer interrupt process.

According to the above configuration, a load instruction makes it possible to save the information in the flag register of the main CPU 63 to the work area 221 for specific control without directly overwriting the information in the flag register of the main CPU 63 with the information in the flag register of the main CPU 63.

Alternatively, instead of executing steps S6505 to S6508, the information in the L register, which has been overwritten by the flag register information, may be saved to the FG buffer by executing the process in step S6504, and then using the load instruction "LD (_FGBUF), L". This configuration also allows the flag register information to be saved to the work area 221 for specific control.

Alternatively, instead of executing steps S6514 and S6515, the configuration may be such that after executing step S6513, the information in the flag register saved in the work area 221 for specific control is overwritten in the L register by a load instruction, "LD L, (_FGBUF)".

Furthermore, the process of saving the flag register information to the main RAM 65 may be performed by a process corresponding to a specific control, instead of being performed by a process corresponding to a specific control. Also, the process of restoring the flag register information saved in the main RAM 65 to the flag register of the main CPU 63 may be performed by a process corresponding to a specific control, instead of being performed by a process corresponding to a specific control.

<30th Embodiment>
In this embodiment, the processing configuration executed by the main CPU 63 differs from that of the 15th embodiment described above. The configurations that differ from those of the 15th embodiment will be described below. Configurations that are the same as those of the 15th embodiment will generally not be described.

Figure 100 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S6601 to S6621 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, a power-on wait process is executed (step S6601). During this power-on wait process, for example, the system waits for a predetermined waiting time (specifically, 1 second) after the main process has started, without proceeding to the next process. During this power-on wait process, the operation start and initial setup of the graphic display device 41 are completed. Afterward, access to the main RAM 65 is permitted (step S6602).

Subsequently, it is determined whether the power failure flag in the work area 221 for specific control in the main RAM 65 is set to "1" (step S6603). If the power failure flag is set to "1" (step S6603: YES), a checksum is calculated for the work area 221 for specific control and the stack area 222 for specific control (step S6604).

The method for calculating the checksum is arbitrary, but one example is to add up all the values in the memory areas that are subject to the checksum calculation. This checksum calculation method is the same as the one used in the power outage processing described later. The checksum calculated in the power outage processing described later will be stored in the work area 221 for specific control, but the memory area of the work area 221 where this checksum is stored is excluded from the memory areas used in the checksum calculation.

In other words, when calculating the checksum, some memory areas in the specific control work area 221 and the specific control stack area 222 are subject to calculation. These memory areas subject to calculation are memory areas where, in principle, the information is not rewritten if power supply, such as backup power, continues to be supplied to the specific control work area 221 and the specific control stack area 222 from the time the checksum is calculated in the power outage processing when the supply of operating power to the MPU 62 is stopped until the power supply to the MPU 62 is resumed and the processing of step S6604 is executed. Therefore, if the information in the specific control work area 221 and the specific control stack area 222 has not been changed between the time the supply of operating power to the MPU 62 is stopped and the time the supply of operating power to the MPU 62 is resumed, the checksum for the specific control work area 221 and the specific control stack area 222 will be the same as immediately before the power supply to the MPU 62 was stopped. Furthermore, the memory area used for calculating this checksum includes the area (specifically, the setting value counter) in the work area 221 for specific control where setting value information indicating the setting status of the pachinko machine 10 is stored.

Subsequently, the checksums for the specific control work area 221 and the specific control stack area 222, which were calculated and stored in the power outage processing performed immediately before the power supply to the MPU 62 was stopped, are read from the specific control work area 221. These read checksums are then compared with the checksum calculated in step S6604 (step S6605). Finally, it is determined whether the checksums match (step S6606).

Here, the power outage information storage process executed by the main CPU 63 will be explained, referring to the flowchart in Figure 101. Note that the power outage information storage process is executed in step S6801 of the timer interrupt processing (Figure 103), which will be described later.

In the power outage information storage process, first, the information "10," which represents the number of repetitions for the power outage signal, is set in the repeat counter provided in the work area 221 for specific control (step S6701), and the power outage detection counter provided in the work area 221 for specific control is cleared to "0" (step S6702).

Subsequently, the MPU 62 executes a process to read the received power outage signal information into its input port (step S6703). In this case, if a power outage signal corresponding to no power interruption (LOW level power outage signal) is received, the input port stores "0" as non-power outage information. If a power outage signal corresponding to a power interruption (HI level power outage signal) is received, the input port stores "1" as power interruption information. Step S6703 executes a process to read this power outage signal information into the registers of the main CPU 63.

If the power outage signal information read in step S6703 corresponds to a power outage (power interruption) (step S6704: YES), the numerical value of the power outage detection counter is incremented by 1 (step S6705). If a negative result is obtained in step S6704 or if the process in step S6705 is executed, the numerical value of the repeating counter is decremented by 1 (step S6706). Then, it is determined whether the numerical value of the repeating counter after the decrement is "0" (step S6707). If a negative result is obtained in step S6707, the process returns to step S6703 and steps S6703 to S6706 are repeated. On the other hand, if a positive result is obtained in step S6707, the process proceeds to step S6708.

In step S6708, it is determined whether the current numerical value of the power outage detection counter is equal to or greater than the trigger threshold number corresponding to a power outage. If it is less than the trigger threshold number, the power outage information storage process is terminated. On the other hand, if it is equal to or greater than the trigger threshold number, the power outage processing in steps S6709 to S6712 is executed.

Specifically, first, the power outage flag in the work area 221 for specific control is set to "1" (step S6709). As a result, if the power outage processing is executed normally and the information is properly stored in the main RAM 65, the power outage flag in the work area 221 for specific control will be set to "1" when the power supply to the main CPU 63 is restarted.

Subsequently, checksums are calculated for the specific control work area 221 and the specific control stack area 222 (step S6710). In this case, the storage areas in the specific control work area 221 and the specific control stack area 222 that are subject to calculation during checksum calculation are the same as the storage areas in the specific control work area 221 and the specific control stack area 222 that are subject to checksum calculation in step S6604 of the main process (Figure 100). Furthermore, the storage areas subject to calculation during checksum calculation include an area in the specific control work area 221 where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, a setting value counter). The calculated checksum is then stored in a storage area in the specific control work area 221 that is excluded from the checksum calculation target, specifically for storing the checksum.

Subsequently, all output port information in the registers of the main CPU 63 is set to "0" (step S6711), and access to the main RAM 65 is prohibited (step S6712). Then, an infinite loop continues until the power supply is completely cut off and processing can no longer be performed.

Furthermore, by implementing power outage information storage processing as the first step in timer interrupt processing, it becomes unnecessary to resume execution from the middle of the timer interrupt process after power is restored. This eliminates the need to store the addresses of the processes running at the time of the power outage as stack information in the main RAM 65, thereby reducing the processing load on processes during power outages.

Returning to the explanation of the main process (Figure 100), if a negative determination is made in step S6603 or step S6606, the clear process for non-setting updates is executed (step S6607). In the clear process for non-setting updates, the work area 221 for specific control is cleared to "0" and initial settings are executed, except for the area where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, the setting value counter). As a result, the area indicating whether the win/fail lottery mode is in high probability mode is cleared to "0", so the win/fail lottery mode becomes low probability mode regardless of the win/fail lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the situation becomes one in which no game rounds are being played, the opening/closing execution mode is not being executed, the general display unit 38a is not showing a change, and the general electric mechanism 34a is in a closed state. Furthermore, the hold storage area 65a and the general-purpose hold area 65c, both located in the work area 221 for specific control, are also cleared to "0". This clears the hold information for both the special display unit 37a and the general-purpose display unit 38a. Additionally, during the clear process for non-setting updates, the stack area 222 for specific control is cleared to "0" and initial settings are executed. Furthermore, during the clear process for non-setting updates, various registers of the main CPU 63 are also cleared to "0" before initial settings are executed.

On the other hand, during the clear process when settings are not updated, the work area 223 and stack area 224 for non-specific control are not cleared to "0". This prevents the work area 223 and stack area 224 for non-specific control from being cleared to "0" even if the power outage flag is not set to "1" due to a failure in the power outage processing. Furthermore, even if an error occurs in the checksum for the work area 221 and stack area 222 for specific control, the work area 223 and stack area 224 for non-specific control are not cleared to "0".

If a negative determination is made in step S6603 or step S6606, after executing the clear process for non-setting updates in step S6607, the system determines whether the setting value of the pachinko machine 10 is normal by checking the value of the setting value counter in the specific control work area 221 (step S6608). Specifically, it is determined to be normal if the setting value set in the setting value counter is one of "Setting 1" to "Setting 6," and abnormal if it is "0" or 7 or greater. If the setting value is abnormal (step S6608: NO), the process for setting a new setting value (steps S6619 to S6621), described later, is executed. This makes it possible to monitor whether the setting value is normal even when a negative determination is made in step S6603 or step S6606 and the clear process for non-setting updates (step S6607) is executed, and also makes it possible to reset the setting value if it is abnormal.

If the settings are correct (step S6608: YES), the power-on setting process is executed (step S6609). During the power-on setting process, predetermined areas of the work area 221 for specific control, such as the power outage flag, are set to their initial values, and commands corresponding to the current game state are sent to the voice and light emission control device 81.

The main CPU 63 is configured to periodically execute timer interrupt processing, but the generation of timer interrupt processing is prohibited when the main processing starts. This prohibition on timer interrupt processing is lifted after the processing in step S6609 is completed and before the processing in step S6610 is executed, at which point the execution of timer interrupt processing is permitted. Therefore, once power is supplied to the main CPU 63, the timer interrupt processing will not be executed until the power-on setting process in step S6609 is completed and before the processing in step S6610 begins. Consequently, the processing necessary to advance the game will not start in the main CPU 63 until this situation occurs.

Subsequently, the process proceeds to the residual processing steps S6610 to S6613. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but residual time occurs between one timer interrupt processing and the next. This residual time varies depending on the processing completion time of each timer interrupt processing, and the residual processing steps S6610 to S6613 are repeatedly executed using this irregular time. In this respect, the residual processing steps S6610 to S6613 can be considered an irregular process that is executed irregularly. Steps S6610 to S6613 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

As described above, in this embodiment, when the supply of operating power to the main CPU 63 is started, if the power outage flag in the specific control work area 221 is not set to "1", or if the checksum does not match, after executing the clear process for non-setting updates, if the setting value is normal (step S6608: YES), the process proceeds to advance the game. This eliminates the need to turn the power ON/OFF again after the supply of operating power to the main CPU 63 is started, even if the power outage flag is not set to "1" due to a failure in the power outage processing. Furthermore, even if an abnormality occurs regarding the checksum of the specific control work area 221 and the specific control stack area 222, there is no need to turn the power ON/OFF again after the supply of operating power to the main CPU 63 is started.

If both steps S6603 and S6606 result in a positive determination, the value of the setting value counter in the specific control work area 221 is checked to determine whether the setting value of the pachinko machine 10 is normal or not (step S6614). Specifically, if the setting value set in the setting value counter is one of "Setting 1" to "Setting 6", it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal. If the setting value is abnormal (step S6614: NO), the process for setting a new setting value (steps S6619 to S6621), described later, is executed.

If the setting value is normal (step S6614: YES), it is determined whether the reset button 68c is pressed (step S6615), whether the setting key insertion part 68a is turned ON using the setting key (step S6616), whether the front door frame 14 is open relative to the inner frame 13 (step S6617), and whether the gaming machine body 12 is open relative to the outer frame 11 (step S6618).

In this embodiment, a front door open sensor 95 is electrically connected to the main CPU 63 to detect whether the front door frame 14 is open relative to the inner frame 13. The detection result of the front door open sensor 95 is input to the main CPU 63. In this case, if the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the main CPU 63. If the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the main CPU 63. The main CPU 63 identifies the front door frame 14 as closed when it receives a closed detection signal from the front door open sensor 95, and identifies the front door frame 14 as open when it receives an open detection signal from the front door open sensor 95.

Furthermore, in this embodiment, a main unit opening sensor 96 for detecting whether the gaming machine body 12 is open relative to the outer frame 11 is electrically connected to the main CPU 63, and the detection result of the main unit opening sensor 96 is input to the main CPU 63. In this case, if the gaming machine body 12 is closed relative to the outer frame 11, the main unit opening sensor 96 transmits a closing detection signal to the main CPU 63, and if the gaming machine body 12 is open relative to the outer frame 11, the main unit opening sensor 96 transmits an opening detection signal to the main CPU 63. The main CPU 63 identifies the gaming machine body 12 as being in a closed state when it receives a closing detection signal from the main unit opening sensor 96, and identifies the gaming machine body 12 as being in an open state when it receives an opening detection signal from the main unit opening sensor 96.

If the reset button 68c is not pressed (step S6615: NO), the power-on setting process is executed in step S6609, and then the remaining processing in steps S6610 to S6613 is repeated. In other words, if the reset button 68c is not pressed, the process to control the game progress is initiated without clearing the work area 221 and the stack area 222 for specific control.

If the reset button 68c is pressed (step S6615: YES), and a negative determination is made in any of steps S6616 to S6618, the clear process for non-setting updates is executed (step S6607). Then, provided that the setting value is normal (step S6608: YES), the process proceeds to control the game's progress from step S6609 onwards. The details of the clear process for non-setting updates have already been explained.

If the reset button 68c is pressed (step S6615: YES), and all steps S6616 to S6618 result in a positive determination, the process for updating the setting value is executed. Furthermore, if it is determined in step S6608 or step S6614 that the setting value is abnormal, the process for updating the setting value is also executed.

Specifically, the first step is to perform a copy process of the setting values (step S6619). In this copy process, the information from the setting value counter, which is used to identify the setting value of the pachinko machine 10 in the specific control work area 221, is stored in a copy area provided in the specific control work area 221. This makes it possible to determine the setting value of the pachinko machine 10 before the clear process during setting updates (step S6620), even if the setting value counter information is cleared to "0" during the clear process during setting updates (i.e., the setting value of the pachinko machine 10 before the supply of operating power to the pachinko machine 10 was stopped).

Subsequently, the clear process for setting updates is executed (step S6620). In the clear process for setting updates, the work area 221 for specific control is cleared to "0" and initial settings are executed, except for the area indicating whether the win/loss lottery mode in the work area 221 for specific control is in high probability mode and the copy area mentioned above. As a result, the game rounds are not executed, the opening/closing execution mode is not executed, the general display unit 38a is not showing a change, and the general electric mechanism 34a is in a closed state. In addition, the hold storage area 65a and the general electric hold area 65c provided in the work area 221 for specific control are also cleared to "0", so the hold information for the special display unit 37a and the hold information for the general display unit 38a are erased. Furthermore, in the clear process for setting updates, the stack area 222 for specific control is cleared to "0" and initial settings are executed. In addition, in the clear process for setting updates, the setting value counter used to identify the setting value of the pachinko machine 10 is cleared to "0". Furthermore, during the clearing process when updating settings, the various registers of the main CPU 63 are also cleared to "0" before the initial settings are executed.

On the other hand, since the clear process during setting updates does not clear the area indicating whether the win/loss lottery mode is in high probability mode to "0", even if the setting value update process (step S6621) is executed, it is possible to maintain the win/loss lottery mode in the mode it was in before the power supply to the pachinko machine 10 was stopped. Furthermore, since the clear process during setting updates does not clear the copy area to "0", it is possible to identify the setting value that was set before the clear process during setting updates was executed. Note that the configuration is not limited to the above; the clear process during setting updates may also be configured not to clear the setting value counter used to identify the setting value of the pachinko machine 10 to "0", and the clear process during setting updates may also be configured to clear the area indicating whether the win/loss lottery mode is in high probability mode to "0".

During the clearing process when updating settings, the work area 223 and stack area 224 for non-specific control are not cleared to "0". This ensures that even if a setting update process that allows changing the settings of the pachinko machine 10 is executed, the work area 223 and stack area 224 for non-specific control are not cleared to "0".

Subsequently, in step S6621, the setting value update process is executed. The processing content of the setting value update process is the same as the setting value update process in the 22nd embodiment described above (Figure 85). After executing the setting value update process, the process proceeds to control the progress of the game from step S6609 onwards.

According to the above configuration, if the setting value is abnormal, the setting value update process will start without requiring any special operation from the gaming hall administrator. Once the setting value update process is complete, the system will move to a process to control the progress of the game. This ensures that the game is played with the correct setting value. On the other hand, since completing the setting value update process requires an OFF operation using the setting key on the setting key insertion unit 68a, it is possible to prevent situations where someone other than the gaming hall administrator arbitrarily sets the setting value and starts the game.

Next, we will explain the configuration for forcibly stopping the game's progress when the main CPU 63 is unable to perform various processes normally. Figure 102(a) is a block diagram illustrating the configuration of the MPU 62.

As shown in Figure 102(a), the MPU 62 is equipped with a main CPU 63, a main ROM 64, and a main RAM 65, as well as a reset signal output unit 251 and a program monitoring unit 252. The reset signal output unit 251 has the function of outputting a reset signal to the main CPU 63. Specifically, the reset signal output unit 251 outputs a reset signal as a HI level signal to the main CPU 63 when operating power is supplied from the power supply/launch control device 78 and the output disabling condition is not met, and does not output a reset signal to the main CPU 63 when operating power is not supplied from the power supply/launch control device 78 or when operating power is supplied but the output disabling condition is met. The main CPU 63 executes various processes when operating power is supplied from the power supply/launch control device 78 and it receives a reset signal from the reset signal output unit 251, and does not execute various processes when operating power is supplied from the power supply/launch control device 78 but it does not receive a reset signal from the reset signal output unit 251. Furthermore, when the main CPU 63 is supplied with operating power from the power supply/launch control device 78, and the system switches from not receiving a reset signal from the reset signal output unit 251 to receiving a reset signal, it starts the main processing (Figure 100).

The program monitoring unit 252 has the function of monitoring whether the main CPU 63 is in a state where various processes can be performed normally. Specifically, the program monitoring unit 252 monitors whether the value of the program counter provided in the main CPU 63 is an abnormal value. The program counter stores the address where the instruction to be executed is stored in the main CPU 63. The program counter has defined possible values, and the program monitoring unit 252 monitors whether the value of the program counter is a value other than the possible values. In addition, when information is written to the work area 221 for specific control by a load instruction, the program monitoring unit 252 monitors whether the address specified as the writing area is an abnormal address. Furthermore, the program monitoring unit 252 may also be configured to monitor whether the address specified as the area to be read when information is read from the work area 221 for specific control by a load instruction is an abnormal address.

The program monitoring unit 252 outputs a monitoring error signal to the reset signal output unit 251 if it determines that the program counter value is abnormal, or if it determines that the address specified when writing information via a load instruction is an abnormal address. When the reset signal output unit 251 receives a monitoring error signal from the program monitoring unit 252, it temporarily stops outputting the reset signal, even if operating power is being supplied from the power supply/launch control device 78. After the reset signal output is stopped for a specified period, it resumes outputting the reset signal. The suspension period is sufficient for the main CPU 63 to determine that the reset signal output has been stopped. As a result, if the program counter value becomes abnormal, or if the address specified when writing information via a load instruction becomes abnormal, the main processing is executed by the main CPU 63 through the OFF/ON switching of the reset signal.

Figure 102(b) is a time chart showing the output of the reset signal by the reset signal output unit 251. Figure 102(b1) shows the period during which operating power is supplied from the power supply/launch control device 78, Figure 102(b2) shows the period during which the reset signal is output from the reset signal output unit 251, and Figure 102(b3) shows the timing at which the monitoring abnormality signal is output from the program monitoring unit 252.

First, let's explain the case where no monitoring error signal is output from the program monitoring unit 252. At timing t1, as shown in Figure 102(b1), the power supply from the power/launch control device 78 to the MPU 62 begins, and at timing t2, as shown in Figure 102(b), the reset signal output unit 251 begins outputting a reset signal. Subsequently, at timing t3, as shown in Figure 102(b1), the power supply from the power/launch control device 78 to the MPU 62 stops, and at timing t4, as shown in Figure 102(b2), the reset signal output unit 251 stops outputting a reset signal.

Next, let's explain the case where a monitoring error signal is output from the program monitoring unit 252. At timing t5, as shown in Figure 102(b1), the supply of operating power from the power supply/launch control device 78 to the MPU 62 begins, and at timing t6, as shown in Figure 102(b), the reset signal output unit 251 begins outputting a reset signal. Subsequently, at timing t7, if the program counter value becomes an abnormal value or the address specified when writing information by a load instruction becomes an abnormal address, a monitoring error signal is output from the program monitoring unit 252 to the reset signal output unit 251, as shown in Figure 102(b3). As a result, as shown in Figure 102(b2), the output of the reset signal from the reset signal output unit 251 is temporarily stopped at timing t7 and then resumed at timing t8.

In this case, the main CPU 63 stops executing various processes at timing t7 and starts the main process (Figure 100) at timing t8, which is the timing when the rising edge of the reset signal is confirmed. However, since the power outage processing is not executed when the execution of various processes by the main CPU 63 is stopped, the main process (Figure 100) starts with the power outage flag in the work area 221 for specific control not set to "1", and the main process (Figure 100) starts without saving the checksums for the work area 221 for specific control and the stack area 222 for specific control. Therefore, in the main process (Figure 100), a negative determination is made in step S6603 or step S6606, and the clear process for non-setting updates (step S6607) is executed. This allows for a clear process to be executed during non-set update when a program monitoring unit 252 outputs a monitoring error signal due to an abnormal value in the program counter or an abnormal address specified when writing information via a load instruction. This process clears a predetermined storage area (either the work area 221 or the stack area 222) to "0".

However, during the clear process when updating settings, the work area 223 and stack area 224 for non-specific control are not cleared to "0". This prevents the work area 223 and stack area 224 from being cleared to "0" even if the program counter value becomes abnormal or the address specified when writing information via a load instruction becomes abnormal, causing a monitoring error signal to be output from the program monitoring unit 252.

Returning to the explanation in Figure 102(b), at timing t9, the supply of operating power from the power supply/launch control device 78 to the MPU 62 is stopped as shown in Figure 102(b1), and at timing t10, the output of the reset signal from the reset signal output unit 251 is stopped as shown in Figure 102(b2).

Next, the timer interrupt processing in this embodiment, which is executed by the main CPU 63, will be explained with reference to the flowchart in Figure 103. The timer interrupt processing is executed periodically (for example, every 4 milliseconds) while steps S6610 to S6613 are being executed in the main processing (Figure 100). The program corresponding to the timer interrupt processing is set in the specific control program.

Steps S6801 to S6819 execute the same processes as steps S5201 to S5219 of the timer interrupt processing (Figure 86) in the 22nd embodiment described above. These processes are executed by the main CPU 63 using a program and data for specific control. Afterward, the setting monitoring process is executed (step S6820). Figure 104 is a flowchart of the setting monitoring process.

The system determines whether the setting value of the pachinko machine 10 is normal or not by checking the value of the setting value counter in the work area 221 for specific control (step S6901). Specifically, it is determined to be normal if the setting value set in the setting value counter is one of "Setting 1" to "Setting 6," and abnormal if it is "0" or 7 or higher.

If the setting value is abnormal (step S6901: NO), the setting value copy process is performed first (step S6902). In this copy process, information from the setting value counter, used to identify the setting value of the pachinko machine 10 in the specific control work area 221, is stored in a copy area provided in the specific control work area 221. This makes it possible to determine the setting value of the pachinko machine 10 before the subsequent setting value update process is executed.

Subsequently, an error command indicating that an abnormality in the set value has occurred is transmitted to the voice and light emission control device 81 (step S6903). Upon receiving this error command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the abnormal set value, and outputs the voice message "An abnormality in the set value has been detected." from the speaker unit 54. Furthermore, the text image "An abnormality in the set value has been detected." is displayed on the pattern display device 41. These notifications are maintained until the power supply to the pachinko machine 10 is stopped, at which point they terminate. However, this is not limited to this configuration; the notifications may also be terminated when the administrator of the gaming hall performs a notification termination operation. For example, the notification termination operation may involve pressing the update button 68b or the reset button 68c. By confirming these notifications, the administrator of the gaming hall can understand that an abnormality in the set value has occurred.

Subsequently, the setting value update process is executed (step S6904). That is, each time the timer interrupt process (Figure 103) is executed, it is monitored whether or not an abnormality has occurred in the setting value. If an abnormality in the setting value is detected, the setting value update process is executed to reset the setting value of the pachinko machine 10. The processing content of the setting value update process is the same as the setting value update process in the 22nd embodiment (Figure 85). Therefore, each time the update button 68b is pressed, the setting value is updated one step at a time, and the selected setting value is confirmed by detecting a game ball with the out-out detection sensor 48a. The setting value during the update and the confirmed setting value are displayed on the third notification display device 69c. Subsequently, if the setting key insertion unit 68a switches from the ON state to the OFF state, it is determined that the termination condition of the setting value update process has been met. After executing the setting value update process, the process returns to the timer interrupt process (Figure 103).

In this setting value update process, the termination condition is not determined to be met simply by the setting key insertion unit 68a being in the OFF state. The termination condition is determined to be met only when the setting key insertion unit 68a switches from the ON state to the OFF state. When the setting value update process is executed during the setting monitoring process, the setting key insertion unit 68a is in the OFF state at the start of the setting value update process. Therefore, in order to meet the termination condition for the setting value update process, it is necessary to insert a setting key into the setting key insertion unit 68a, perform an ON operation, and then perform an OFF operation. This prevents the setting value update process from terminating prematurely without proper operation by the gaming hall administrator.

When the setting key insertion unit 68a switches from the ON state to the OFF state and the termination condition for the setting value update process is met, step S5111 in the setting value update process (Figure 85) is executed to compare whether the setting value stored in the copy area of the work area 221 for specific control is the same as the setting value currently set in the setting value counter of the work area 221 for specific control. In other words, it is determined whether the setting value set before the setting value update process (step S6904) was executed is the same as the setting value set in the current setting value update process. If both setting values are the same (step S5112: NO), the notification process for no change (step S5113) is executed to provide the setting maintenance notification described earlier. On the other hand, if both setting values are different (step S5112: YES), the notification process for change (step S5114) is executed to provide the setting change notification described earlier.

In a configuration where a setting value update process is executed when a setting value anomaly occurs, a setting maintenance notification is issued if the setting value set before the setting value update process is executed is the same as the setting value set during the update process. This ensures that even if a setting value update process is executed due to a setting value anomaly, the setting maintenance notification is issued by resetting the setting value to the value set before the update. This clearly indicates to the player that the setting value has not changed despite the setting value update process being executed due to the anomaly. Incidentally, since it is common practice in amusement halls to record the setting values of each installed pachinko machine 10, it is possible to execute the setting value update process due to a setting value anomaly so that the recorded setting value is used.

Returning to the explanation of the timer interrupt processing (Figure 103), after executing the setting monitoring process in step S6820, the management process is executed in step S6821. During the execution of the management process, the program of the subroutine corresponding to the management process set in the specific control program is executed. During the execution of this subroutine, information to identify the return address of the timer interrupt processing after the management process is written to the specific control stack area 222 by a push instruction. Then, when the management process is completed, the information to identify the return address is read out by a pop instruction, and the program returns to the timer interrupt processing program indicated by that return address.

Figure 105 is a flowchart showing the management process in this embodiment, which is executed by the main CPU 63. Note that steps S7001 to S7005 in the management process are executed by the main CPU 63 using a specific control program and specific control data.

First, to prevent the timer interrupt process (Figure 103) from occurring, the interrupt disable setting is configured (step S7001). This prevents the timer interrupt process (Figure 103), which corresponds to specific control, from being interrupted and activated during the management execution process (described later), which corresponds to non-specific control.

Subsequently, the load instruction "LD (_PSWBUF), PSW" saves the information in the flag register of the main CPU 63 to the PSW buffer set in the work area 221 for specific control (step S7002). The flag register includes the carry flag, zero flag, P/V flag, sign flag, and half-carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotation instructions, and input/output instructions. By saving this flag register information before the program of the subroutine corresponding to the management execution process starts, it is possible to save the flag register information in the work area 221 for specific control before it changes during the subroutine call or after the subroutine starts.

Subsequently, the program for the subroutine corresponding to the management execution process set in the non-specific control program is read, and the management execution process is started (step S7003). In this case, information for identifying the return address of the management process after the execution of the management execution process is written to the specific control stack area 222 by a push instruction. Then, when the management execution process finishes, the information for identifying the return address is read by a pop instruction, and the program returns to the management process indicated by that return address.

After the management execution process is completed and the program returns to the management process, the load instruction "LD PSW, (_PSWBUF)" is used to restore the information in the flag register that was saved in the PSW buffer in the work area 221 for specific control in step S7002 to the flag register of the main CPU 63 (step S7004). This restores the information in the flag register of the main CPU 63 to the information it had when step S7002 was last executed. In other words, the information in the flag register of the main CPU 63 is restored to the information necessary to execute the specific control.

Subsequently, the interrupt enable setting is performed (step S7005) to switch from a state where timer interrupt processing (Figure 103) is prohibited to a state where it is enabled. This makes it possible to execute a new timer interrupt process.

Figure 106 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S7101 to S7116 of the management execution process are executed by the main CPU 63 using a program and data for non-specific control.

Steps S7101 to S7108 and S7110 to S7116 execute the same processes as steps S4501 to S4515 of the management execution process (Figure 78) in the 17th embodiment described above. Step S7109 executes a separate monitoring process. During the execution of this separate monitoring process, a subroutine program corresponding to the separate monitoring process, set in the non-specific control program, is executed. During the execution of this subroutine program, information for identifying the return address of the management execution process after the separate monitoring process is written to the non-specific control stack area 224 by a push instruction. Then, when the separate monitoring process finishes, the information for identifying the return address is read by a pop instruction, and the program returns to the management execution process indicated by that return address.

Figure 107 is a flowchart of the separate monitoring process. Note that steps S7201 to S7206 in the separate monitoring process are executed by the main CPU 63 using a program and data for non-specific control.

In a separate monitoring process, it is determined whether the value of the pointer indicating the processing position of the process being executed in the non-specific control program exceeds the normal numerical range (step S7201). It is also determined whether the information stored in the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233, all located in the non-specific control work area 223, is clearly abnormal (step S7202). For example, if the value of the normal output counter 231e in the normal counter area 231 is "0" but the value of the normal general prize counter 231a is 1000 or more, it is determined to be abnormal. Furthermore, it is determined whether the information stored in the calculation result storage area 234, also located in the non-specific control work area 223, is clearly abnormal (step S7203). For example, if the 61st parameter is "0" but any of the 62nd to 64th parameters are not "0", it is determined to be abnormal.

If a positive determination is made in any of steps S7201 to S7203, it is determined that an information anomaly has occurred in the work area 223 for non-specific control, and a partial clearing process for the work area 223 for non-specific control is executed (step S7204). In this partial clearing process, all storage areas in the work area 223 for non-specific control, except for the management start flag, are cleared to "0". In this case, the normal counter area 231, the counter area 232 for the opening/closing execution mode, the counter area 233 for the high-frequency support mode, and the calculation result storage area 234 are all cleared to "0". This makes it possible to resolve the information anomaly in the work area 223 for non-specific control.

Furthermore, by not clearing the management start flag to "0," it is possible to maintain the state where the management start flag is already set to "1," thus preventing the collection of history information from being restricted at the time of shipment of the pachinko machine 10, even though the pachinko machine 10 is already being used continuously in the amusement hall. However, this is not the only option; in step S7204, the entire work area 223 for non-specific control, including the management start flag, may also be cleared to "0."

Furthermore, in step S7204, the stack area 224 for non-specific control is not cleared to "0". The stack area 224 for non-specific control stores information about various registers used in the processing corresponding to specific control in steps S7102 to S7107 of the management execution process (Figure 106). By not clearing the stack area 224 for non-specific control to "0", it is possible to prevent the deletion of information about the various registers used in the processing corresponding to this specific control, which is stored in the stack area 224 for non-specific control. Additionally, the stack area 224 for non-specific control stores information about the return address of the management execution process (Figure 106) after another monitoring process has finished. By not clearing the stack area 224 for non-specific control to "0", it is possible to prevent this return address information from being deleted.

Subsequently, the initial setup process is executed (step S7205). During the initial setup process, initial settings are performed on the memory areas in the non-specific control work area 223 that were targeted for "0" clearing in step S7204.

Subsequently, a clear notification process is executed (step S7206). In the clear notification process, a command indicating that the work area 223 for non-specific control has been cleared to "0" is sent to the voice and light emission control device 81. Upon receiving this command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the forced clearing of the work area 223 for non-specific control, and outputs the voice message "History information has been forcibly cleared." from the speaker unit 54. In addition, the character display device 41 displays the text image "History information has been forcibly cleared." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, at which point they terminate. However, the system is not limited to this, and the notifications may be terminated when the notification termination operation is performed by the administrator of the gaming hall. The notification termination operation may be, for example, pressing the update button 68b or pressing the reset button 68c. By confirming the above notification, the administrator of the gaming hall can understand that the work area 223 for non-specific control has been forcibly cleared.

If a negative result is obtained in all steps S7201 to S7203, or if the process in step S7206 is executed, the separate monitoring process terminates and the process returns to the monitoring execution process (Figure 106).

The embodiment described in detail above provides the following excellent effects.

When the program monitoring unit 252 determines that the address specified when writing information by a load instruction is an abnormal address, the reset signal output unit 251 switches the reset signal OFF→ON, causing the main CPU 63 to execute the main process (Figure 100) in the same way as when the supply of operating power is newly started. When the reset signal is switched OFF→ON, the power outage flag in the work area 221 for specific control is not set to "1", and the checksum during a power outage is not stored in the work area 221 for specific control, so the clear process for non-setting updates (step S6607) is forcibly executed. In the clear process for non-setting updates, the storage areas in the work area 221 for specific control other than the storage area where the setting values of the pachinko machine 10 are stored are cleared to "0", the stack area 222 for specific control is cleared to "0", and then the initial setting process for these areas is executed. This allows for the resolution of information anomalies in the work area 221 or stack area 222 for specific control purposes if such anomalies are suspected. These anomalies can be resolved by performing a "0" clearing process and an initial setup process on both the work area 221 and the stack area 222.

If the program monitoring unit 252 detects that the program counter value of the main CPU 63 is abnormal, the reset signal output unit 251 switches the reset signal OFF→ON, causing the main CPU 63 to execute the main processing (Figure 100) in the same way as when power supply is newly started. When the reset signal is switched OFF→ON, the power outage flag in the specific control work area 221 is not set to "1," and the checksum during the power outage is not stored in the specific control work area 221. Therefore, the clear processing for non-setting updates (step S6607) is forcibly executed. In the clear processing for non-setting updates, the internal memory area of the main CPU 63, including various registers, is cleared to "0," and initial setup processing is executed. This makes it possible to resolve information anomalies in the internal memory area of the main CPU 63 by performing a "0" clear and initial setup processing on the internal memory area of the main CPU 63 if there is a possibility of an information anomaly.

On the other hand, during the clear process when settings are not updated, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". This ensures that even if the program monitoring unit 252 identifies an information anomaly as described above, and a "0" clear and initial setup process are executed for the internal storage area of the main CPU 63, the work area 221 for specific control, and the stack area 222 for specific control, the game history information is not erased, and the information regarding the management results of the game history is not erased.

In a configuration where, in the main processing (Figure 100) when power supply to the main CPU 63 begins, if the power outage flag is not set to "1" or the checksum does not match, the clear processing for non-setting updates (step S6607) is executed. However, if the program monitoring unit 252 identifies an information anomaly, the reset signal is switched OFF→ON so that the main processing (Figure 100) is executed with the power outage flag not set to "1" and the checksum not stored. This allows the program monitoring unit 252 to resolve the information anomaly identified by the program monitoring unit 252 by utilizing the configuration for resolving information anomalies at the start of power supply.

In a configuration where the main processing (Figure 100) monitors whether the checksum is normal when power is supplied to the main CPU 63, the checksum calculation includes the work area 221 and stack area 222 for specific control, but excludes the work area 223 and stack area 224 for non-specific control. This makes it possible to determine whether an information anomaly has occurred only in the memory area corresponding to the specific control in the main RAM 65.

If the main processing (Figure 100) detects an abnormality in the checksum when power supply to the main CPU 63 is initiated, the clearing process for non-configuration updates (step S6607) is executed. However, in this clearing process for non-configuration updates, the work area 221 and stack area 222 for specific control are cleared to "0" and initialized, while the work area 223 and stack area 224 for non-specific control are not cleared to "0". This prevents the processing corresponding to specific control from continuing to execute even if an information abnormality occurs in the work area 221 and stack area 222. Furthermore, it prevents the storage area of the main RAM 65 corresponding to non-specific control from being cleared to "0" as a result of the information abnormality in the work area 221 and stack area 222.

In the power outage information storage processing (Figure 101), checksums are calculated for the work area 221 and the stack area 222 for specific control during power outage processing (steps S6709 to S6712), whereas checksums are not calculated for the storage area of the main RAM 65 corresponding to non-specific control. This prevents the processing time required to complete power outage processing from becoming excessively long.

If a separate monitoring process (Figure 107) executed by the process corresponding to non-specific control detects an anomaly in the information stored in the work area 223 for non-specific control, the said separate monitoring process (Figure 107), which is the process corresponding to non-specific control, clears the work area 223 for non-specific control to "0" and executes an initialization process. This prevents the process corresponding to non-specific control from being executed while the information in the work area 223 remains unchanged, even if some anomaly has occurred in the work area 223 for non-specific control. Furthermore, since the process of clearing the work area 223 for non-specific control to "0" and the initialization process are executed by the process corresponding to non-specific control, it is possible to prevent the process corresponding to specific control from intervening in the updating of the information in the work area 223 for non-specific control.

In a separate monitoring process (Figure 107) corresponding to non-specific control, monitoring is performed to determine whether an abnormality has occurred in the work area 223 for non-specific control. If an abnormality is detected, a process to clear the work area 223 to "0" and a process to initialize it are executed. This makes it possible to perform the monitoring of whether an abnormality has occurred in the work area 223 for non-specific control and the initialization of the work area 223 for non-specific control as a series of processes within the process corresponding to non-specific control.

If a separate monitoring process (Figure 107) executed in the process corresponding to non-specific control detects an anomaly in the information stored in the work area 223 for non-specific control, the work area 223 for non-specific control is cleared to "0" and initialized. However, the stack area 224 for non-specific control is not cleared to "0" or initialized. This allows for the resolution of information anomalies in the work area 223 for non-specific control while preventing the loss of information from various registers used in the process corresponding to specific control, which are saved in the stack area 224 for non-specific control, and the return address information after the separate management process is completed.

The process of clearing the work area 221 and the stack area 222 for specific control to "0" and initializing them is executed in the process corresponding to the specific control, while the process of clearing the work area 223 for non-specific control to "0" and initializing it is executed in the process corresponding to non-specific control. This makes it possible to treat the work area 221 and the stack area 222 for specific control as dedicated storage areas for the process corresponding to the specific control, and the work area 223 for non-specific control as a dedicated storage area for the process corresponding to non-specific control, even for such initialization processes.

In the main process (Figure 100), the configuration is such that the setting value is monitored in steps S6608 and S6614. However, it is also possible to configure the system so that this monitoring of the setting value is not performed. This reduces the processing load of the power supply start process, which is executed when the power supply to the main CPU 63 begins. Furthermore, even if the power supply start process does not monitor whether the setting value is normal, the timer interrupt process (Figure 103), which is executed after the power supply start process is completed, will monitor whether the setting value is normal in the setting monitoring process (step S6820). Therefore, if the setting value is abnormal, it is possible to take action.

Furthermore, the configuration in which the setting monitoring process (step S6820) is executed is not limited to each time the timer interrupt process (Figure 103) is triggered. For example, the configuration may be such that the setting monitoring process (step S6820) is executed each time the timer interrupt process (Figure 103) is executed a predetermined number of times (e.g., 10,000 times). In this case, it becomes possible to periodically monitor whether the setting value is normal while reducing the frequency of such monitoring.

Alternatively, the setting monitoring process (step S6820) may be executed in the residual processing (steps S6610 to S6613) of the main process (Figure 100). In this case, it becomes possible to monitor whether the setting value is correct by utilizing the idle time when timer interrupt processing is not being executed.

Furthermore, the system may be configured to execute the setting monitoring process (step S6820) when a new game round is started. More specifically, the system may be configured to execute the setting monitoring process (step S6820) before the win/failure determination process is executed when a new game round is started. This prevents the win/failure determination process from being executed when the setting value is abnormal.

Furthermore, if the setting monitoring process (step S6820) identifies that the setting value is abnormal, instead of proceeding to the setting value update process (step S6904), the system may be configured to set the game stop flag provided in the work area 221 for specific control to "1". In this case, since the timer interrupt process (Figure 103) makes an affirmative judgment in step S6807, the processes in steps S6808 to S6821 are not executed, and if the setting value is abnormal, the game will stop. However, the processes in steps S6801 to S6806 are executed, so power outage monitoring is performed, and the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the random number initial value counter CINI are updated, and fraud detection is also performed. In addition, if the game stop flag is set to "1", a notification indicating that the setting value should be updated may be executed to prompt the execution of the setting value update process. In this case, the administrator of the gaming hall, upon receiving the notification, will perform a power-off operation, followed by a power-on operation in a manner that executes the setting value update process. This will clear the game stop flag to "0," releasing the game from being stopped, and simultaneously execute the setting value update process, setting the correct values.

Furthermore, if the setting monitoring process (step S6820) identifies an abnormal setting value, the main process (Figure 100) may be started with the setting abnormality flag in the specific control work area 221 set to "1". The game may also be stopped with the setting abnormality flag set to "1", and the power may be turned OFF → ON to release the stopped state. In this case, even if no operation is performed in the main process (Figure 100) to initiate the setting value update process, if the setting abnormality flag is set to "1", the setting value update process is forcibly executed, making it possible to forcibly set a new setting value using the setting value update process set in the main process (Figure 100).

Furthermore, if the program monitoring unit 252 detects an information anomaly and the reset signal is forcibly switched OFF→ON, an initialization process may be executed on the work area 221 for specific control, thereby setting the pachinko machine 10 to "Setting 1". Alternatively, if the program monitoring unit 252 detects an information anomaly and the reset signal is forcibly switched OFF→ON, an initialization process may be executed on the work area 221 for specific control before a setting value update process is executed.

Furthermore, if the program monitoring unit 252 detects an information anomaly, the reset signal may not be forcibly switched OFF→ON, and the clear process for non-setting updates (step S6607) may be executed. Alternatively, the clear process for setting updates (step S6620) and the setting value update process (step S6621) may be executed.

Furthermore, in the clear process when the setting is not updated (step S6607), the setting value of the pachinko machine 10 may be configured to become "Setting 1" by initializing the storage area that stores the setting value information in the work area 221 for specific control, or it may be configured to become a predetermined setting value other than "Setting 1". This makes it possible to set the setting value to a predetermined value when the clear process when the setting is not updated is executed.

Furthermore, while the clear process during non-setting updates (step S6607) is configured so that the work area 223 and stack area 224 for non-specific control are not cleared to "0", it is also possible to configure them to be cleared to "0".

Furthermore, in step S7204 of the separate monitoring process (Figure 107), the management start flag is not cleared to "0," but it may also be configured to clear the management start flag to "0." Also, in step S7204 of the separate monitoring process (Figure 107), the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233 may not be cleared to "0," and the calculation result storage area 234 may not be cleared to "0."

Furthermore, in step S7204 of the separate monitoring process (Figure 107), the configuration may be such that the "0" clearing process and initial setup process are executed not only for the work area 223 for non-specific control but also for the stack area 224 for non-specific control. In this case, it is preferable not to erase the information of the return address of the management execution process after the completion of the separate monitoring process, and the information of various registers used in the process corresponding to the specific control that has been saved in the stack area 224 for non-specific control.

Furthermore, a separate monitoring process (Figure 107) may monitor whether an abnormality has occurred in the non-specific control stack area 224. If an abnormality is detected, the system may be configured to perform a "0" clearing process and an initial setup process for the non-specific control stack area 224. In this case, it is preferable not to erase the return address information of the management execution process after the completion of the separate monitoring process in the non-specific control stack area 224.

Furthermore, the configuration is not limited to one in which both the work area 221 for specific control and the stack area 222 for specific control are subject to checksum calculation. It is also possible to have a configuration in which only the work area 221 for specific control is subject to checksum calculation, or a configuration in which only the stack area 222 for specific control is subject to checksum calculation.

<Embodiment No. 31>
In this embodiment, the processing configuration of the main process executed by the primary CPU 63 differs from that of the 30th embodiment described above. The configurations that differ from those of the 30th embodiment will be described below. Configurations that are the same as those of the 30th embodiment will generally not be described.

Figure 108 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S7301 to S7322 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, a power-on wait process is executed (step S7301). During this power-on wait process, for example, the system waits for a predetermined waiting time (specifically, 1 second) after the main process has started, without proceeding to the next process. During this power-on wait process, the operation start and initial setup of the graphic display device 41 are completed. Afterward, access to the main RAM 65 is permitted (step S7302).

Subsequently, it is determined whether the power failure flag in the work area 221 for specific control in the main RAM 65 is set to "1" (step S7303). If the power failure flag is set to "1" (step S7303: YES), a checksum is calculated for the work area 221 for specific control and the stack area 222 for specific control (step S7304). The method for calculating the checksum is the same as step S6604 of the main processing in the 30th embodiment (Figure 100) described above.

Subsequently, the checksums for the specific control work area 221 and the specific control stack area 222, which were calculated and stored in the power outage processing performed immediately before the power supply to the MPU 62 was stopped, are read from the specific control work area 221. These read checksums are then compared with the checksum calculated in step S7304 (step S7305). Finally, it is determined whether the checksums match (step S7306).

If a positive result is obtained in step S7306, the processing in steps S7307 to S7320 is executed. In this case, the processing content of steps S7307 to S7314 is the same as steps S6614 to S6621 of the main processing (Figure 100) in the 30th embodiment, and steps S7316 to S7320 are the same as steps S6609 to S6613 of the main processing (Figure 100) in the 30th embodiment.

Furthermore, if the reset button 68c is pressed (step S7308: YES), and a negative determination is made in any of steps S7309 to S7311, the clear process for non-setting updates is executed (step S7315). The processing content of the clear process for non-setting updates is the same as step S6607 of the main process (Figure 100) in the 30th embodiment described above. However, in this embodiment, after executing the clear process for non-setting updates, the process proceeds to steps S7316 to S7320 without determining whether the setting value is normal or not. The clear process for non-setting updates (step S7315) is executed only if a negative determination is made in any of steps S7309 to S7311. However, since the determination of whether the setting value is normal or not is made in step S7307 before the processing of steps S7309 to S7311 is executed, it is not necessary to determine whether the setting value is normal or not after executing the clear process for non-setting updates.

If a negative determination is made in step S7303 or step S7306, that is, if the power outage flag in the work area 221 for specific control is not set to "1" or if a checksum error occurs, the error clearing process is executed (step S7321). Figure 109 is a flowchart of the error clearing process. Note that the processing in steps S7401 to S7405 of the error clearing process is executed by the main CPU 63 using the program and data for specific control.

First, a clearing process is performed on the work area 221 for specific control (step S7401). In this clearing process, the work area 221 for specific control is cleared to "0", except for the area where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, the setting value counter), and initial settings are performed on the area that has been cleared to "0". As a result, the area indicating whether the win/fail lottery mode is in high probability mode is cleared to "0", so the win/fail lottery mode becomes low probability mode regardless of the win/fail lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the situation becomes one in which no game rounds are being played, the opening/closing execution mode is not being executed, the general display unit 38a is not showing a change, and the general power mechanism 34a is in a closed state. Furthermore, the hold storage area 65a and the general-purpose hold area 65c, both located in the work area 221 for specific control, are also cleared to "0". This clears the hold information for both the special display unit 37a and the general-purpose display unit 38a.

Subsequently, a clearing process for the specific control stack area 222 is performed (step S7402). This clearing process clears the specific control stack area 222 to "0" and performs initial settings.

Subsequently, using the "PUSH PSW" instruction, the information in the flag register of the main CPU 63 is saved to the specific control stack area 222 (step S7403). The flag register includes the carry flag, zero flag, P/V flag, sign flag, and half-carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. By saving this flag register information before the program for the subroutine corresponding to the non-specific control clear process starts, it is possible to save the flag register information in the specific control stack area 222 before it changes after the subroutine is called or starts. The amount of information in the flag register is 1 byte.

Subsequently, the program for the non-specific control clear process, which is set in the non-specific control program, is read, and the non-specific control clear process is started (step S7404). In this case, information for identifying the return address of the clear process in case of an error after the execution of the non-specific control clear process is written to the specific control stack area 222 by a push instruction. Then, when the non-specific control clear process is completed, the information for identifying the return address is read by a pop instruction, and the program returns to the clear process in case of an error indicated by that return address.

If the program returns to the error clearing program after executing the clearing process for non-specific control, the "POP PSW" instruction restores the information in the flag register that was saved in the stack area 222 for specific control in step S7402 to the flag register of the main CPU 63 (step S7405). This restores the information in the flag register of the main CPU 63 to the information at the time step S7402 was executed. In other words, the information in the flag register of the main CPU 63 is restored to the information necessary to execute the specific control.

Figure 110 is a flowchart showing the clearing process for non-specific control. Note that steps S7501 to S7516 in the clearing process for non-specific control are executed by the main CPU 63 using the non-specific control program and non-specific control data.

First, the load instruction "LD SP, Y(u+2)" sets Y(u+2) as the fixed address at the start of non-specific control in the stack pointer of the main CPU 63 (step S7501). In this case, similar to step S3901 of the management execution process (Figure 71) in the 15th embodiment described above, the information of the last address in the stack area 224 for non-specific control is set in the stack pointer.

Subsequently, the load instruction "LD (_WABUF), WA" saves the information in the WA register of the main CPU 63 to the WA buffer set in the work area 223 for unspecified control (step S7502). Also, the load instruction "LD (_BCBUF), BC" saves the information in the BC register of the main CPU 63 to the BC buffer set in the work area 223 for unspecified control (step S7503). Also, "LD
The load instruction, "(_DEBUF), DE", saves the information in the DE register of the main CPU 63 to the DE buffer set in the work area 223 for unspecified control (step S7504). Also, the load instruction, "LD (_HLBUF), HL", saves the information in the HL register of the main CPU 63 to the HL buffer set in the work area 223 for unspecified control (step S7505). Also, the load instruction, "LD (_IXBUF), IX", saves the information in the IX register of the main CPU 63 to the IX buffer set in the work area 223 for unspecified control (step S7506). Also, the load instruction, "LD (_IYBUF), IY", saves the information in the IY register of the main CPU 63 to the IY buffer set in the work area 223 for unspecified control (step S7507).

In addition to the flag register already described, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, steps S7502 to S7507 save the information from some of these general-purpose registers, auxiliary registers, and index registers—specifically, the WA register, BC register, DE register, HL register, IX register, and IY register—to the corresponding buffers in the non-specific control work area 223. Note that the information size of each of the WA register, BC register, DE register, HL register, IX register, and IY register is 2 bytes.

The WA, BC, DE, HL, IX, and IY registers are used in the partial clearing (step S7508) and initial setup (step S7509) processes of the work area 223 for non-specific control, which are processes corresponding to non-specific control. By saving the information set in these registers to the work area 223 for non-specific control prior to the execution of the partial clearing (step S7508) and initial setup (step S7509) processes, it becomes possible to save the information in these registers that was used during specific control before non-specific control begins. Therefore, even if these registers are overwritten during non-specific control, when non-specific control ends, the information saved in the work area 223 for non-specific control can be restored to these registers, thereby restoring the state of these registers to the state corresponding to specific control before non-specific control was executed.

Furthermore, instead of saving all information from various general-purpose registers, auxiliary registers, and index registers to the work area 223 for non-specific control, by selectively saving information from the WA register, BC register, DE register, HL register, IX register, and IY register, which are used in the partial clearing process (step S7508) and initial setup process (step S7509) of the work area 223 for non-specific control, it is possible to reduce the capacity reserved in the work area 223 for saving register information. Therefore, it is possible to save the register information as described above while securing a large capacity in the work area 223 for non-specific control that is available during the partial clearing process (step S7508) and initial setup process (step S7509) of the work area 223 for non-specific control. Naturally, among the various general-purpose registers, auxiliary registers, and index registers in the main CPU 63, the information set before the start of the processing corresponding to the non-specific control is retained until the processing corresponding to the non-specific control is completed and the processing corresponding to the specific control is resumed.

Furthermore, by saving the register information to the non-specific control work area 223 instead of the non-specific control stack area 224, the capacity of the non-specific control stack area 224 can be kept relatively small. Also, when using the non-specific control stack area 224, as already explained, the information is written in an order that later information is read first. Therefore, if the reading order of the information is shifted due to noise or other reasons, all subsequent read information will be returned to the wrong register. The probability of such an event occurring increases as the amount of information saved to the non-specific control stack area 224 increases. In contrast, by saving the register information to the non-specific control work area 223, it is possible to prevent the above-mentioned event from occurring even when there is a large amount of information to be saved.

After executing steps S7502 to S7507, a partial clearing process is performed on the work area 223 for non-specific control (step S7508). In this partial clearing process, all memory areas in the work area 223 for non-specific control, except for the memory area where information on various registers of the main CPU 63 used in the specific control process is saved, are cleared to "0". Specifically, the WA buffer, BC buffer, DE buffer, HL buffer, IX buffer, and IY buffer in the work area 223 for non-specific control are not cleared to "0", while all other memory areas are cleared to "0".

In this case, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, the calculation result storage area 234, and the management start flag are all cleared to "0". This makes it possible to resolve information anomalies in the work area 223 for non-specific control. Furthermore, by not clearing the storage area where the information of various registers of the main CPU 63 used in the processing corresponding to specific control is saved to "0", it becomes possible to restore the information used in the processing corresponding to specific control to the various registers of the main CPU 63 when the processing corresponding to non-specific control ends and the system returns to the processing corresponding to specific control.

Furthermore, in step S7508, the stack area 224 for non-specific control is not cleared to "0". The stack area 224 for non-specific control stores information about the return address of the abnormal clear process (Figure 109) after the completion of the non-specific control clear process. By not clearing the stack area 224 for non-specific control to "0", it is possible to prevent this return address information from being erased.

Subsequently, the initial setup process is executed (step S7509). During the initial setup process, initial settings are performed on the memory areas in the non-specific control work area 223 that were targeted for "0" clearing in step S7508.

Subsequently, using the load instruction "LD SP, Y(r+α)", the stack pointer of the main CPU 63 is set to Y(r+α) as a fixed address upon return to specific control, similar to step S3909 of the management execution process (Figure 71) in the 15th embodiment (step S7510). The address of Y(r+α) is set as the address between Y(r+8) and Y(s) in the stack area 222 for specific control.

Subsequently, the load instruction "LD WA, (_WABUF)" overwrites the information saved in the WA buffer of the work area 223 for non-specific control into the WA register of the main CPU 63 (step S7511). Then, the load instruction "LD BC, (_BCBUF)" overwrites the information saved in the BC buffer of the work area 223 for non-specific control into the BC register of the main CPU 63 (step S7512). Furthermore, the load instruction "LD DE, (_DEBUF)" overwrites the information saved in the DE buffer of the work area 223 for non-specific control into the DE register of the main CPU 63 (step S7513). Finally, the load instruction "LD HL, (_HLBUF)" overwrites the information saved in the HL buffer of the work area 223 for non-specific control into the HL register of the main CPU 63 (step S7514). Furthermore, the load instruction "LD IX, (_IXBUF)" overwrites the information saved in the IX buffer of the work area 223 for non-specific control into the IX register of the main CPU 63 (step S7515). Similarly, the load instruction "LD IY, (_IYBUF)" overwrites the information saved in the IY buffer of the work area 223 for non-specific control into the IY register of the main CPU 63 (step S7516). The execution of steps S7511 to S7516 allows the main CPU 63 to restore the information in its WA register, BC register, DE register, HL register, IX register, and IY register to the information corresponding to the specific control immediately before the processing corresponding to the non-specific control began.

According to the above configuration, if the power failure flag is not set to "1" or the checksum is abnormal during the main processing (Figure 108) executed when power supply to the main CPU 63 begins, the abnormality clearing process (step S7321) is executed. This clears not only the work area 221 and stack area 222 for specific control, but also the work area 223 for non-specific control, to "0" and resets them to their initial settings. If an information anomaly occurs in the work area 221 for specific control, there is a possibility that an information anomaly also occurs in the work area 223 for non-specific control. However, because the non-specific control work area 223 is also initialized during the abnormality clearing process, it is possible to prevent the processing corresponding to non-specific control from being executed in a state where an information anomaly exists in the work area 223.

Even when the process of clearing the work area 223 for non-specific control and initializing it is executed during the error clearing process (step S7321), the information in the various registers used by the process corresponding to the specific control, which has been saved in the work area 223 for non-specific control, is not cleared to "0". This makes it possible to execute the process of clearing the work area 223 for non-specific control and initializing it to "0" while preventing the information used by the process corresponding to the specific control from being erased after the process corresponding to the non-specific control has finished.

Even if the work area 223 for non-specific control is cleared to "0" and initialized during the error clearing process (step S7321), the stack area 224 for non-specific control is not cleared to "0" and initialized. This prevents the return address information from being erased after the clearing process for non-specific control (Figure 110) is completed.

The processes for clearing the work area 221 and the stack area 222 for specific control to "0" and initializing them are executed by the process corresponding to the specific control, while the processes for clearing the work area 223 for non-specific control to "0" and initializing it are executed by the process corresponding to the non-specific control. This ensures that, for both the "0" clearing and initializing processes, the work area 221 and the stack area 222 for specific control are treated as dedicated storage areas for the process corresponding to the specific control, and the work area 223 for non-specific control is treated as a dedicated storage area for the process corresponding to the non-specific control.

Furthermore, the configuration is not limited to one in which both the work area 221 for specific control and the stack area 222 for specific control are subject to checksum calculation. It is also possible to have a configuration in which only the work area 221 for specific control is subject to checksum calculation, or a configuration in which only the stack area 222 for specific control is subject to checksum calculation.

Furthermore, the work area 223 for non-specific control may be configured to be subject to checksum calculation. In this case, the work area 221 for specific control and the work area 223 for non-specific control may be configured to be subject to checksum calculation, or the stack area 222 for specific control and the work area 223 for non-specific control may be configured to be subject to checksum calculation, or the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control may be configured to be subject to checksum calculation.

Furthermore, the stack area 224 for non-specific control may be configured to be subject to checksum calculation. In this case, the work area 221 for specific control and the stack area 224 for non-specific control may be configured to be subject to checksum calculation, or the stack area 222 for specific control and the stack area 224 for non-specific control may be configured to be subject to checksum calculation, or the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control may be configured to be subject to checksum calculation.

Furthermore, the configuration may include the work area 223 and stack area 224 for non-specific control as targets for checksum calculation. In this case, the configuration may include the work area 221 for specific control, the work area 223 and stack area 224 for non-specific control as targets for checksum calculation; or the stack area 222 for specific control, the work area 223 and stack area 224 for non-specific control as targets for checksum calculation; or the work area 221 for specific control, the stack area 222 for specific control, the work area 223 and stack area 224 for non-specific control as targets for checksum calculation.

Furthermore, in steps S7508 and S7509 of the clear process for non-specific control (Figure 110), the configuration may be such that the "0" clear process and initial setting process are executed not only for the work area 223 for non-specific control but also for the stack area 224 for non-specific control. In this case, it is preferable not to erase the return address information of the clear process in case of an error after the completion of the clear process for non-specific control.

Furthermore, in step S7508 of the clear process for non-specific control (Figure 110), the management start flag is cleared to "0," but it is also possible to configure it so that the management start flag is not cleared to "0." Also, in step S7508 of the clear process for non-specific control (Figure 110), the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233 may not be cleared to "0," and the calculation result storage area 234 may not be cleared to "0."

<Embodiment 32>
In this embodiment, the processing configuration for monitoring information anomalies in the main RAM 65 using checksums differs from that of the 30th embodiment. The configurations that differ from those of the 30th embodiment will be described below. Configurations that are the same as those of the 30th embodiment will generally not be described.

Figure 111 is a flowchart showing the power outage information storage process in this embodiment, which is executed by the main CPU 63. The power outage information storage process is executed in step S6801 of the timer interrupt processing (Figure 103). Furthermore, steps S7601 to S7613 of the power outage information storage process are executed by the main CPU 63 using a specific control program and specific control data.

In steps S7601 to S7608 of the power outage information storage process, the same processing as steps S6701 to S6708 of the power outage information storage process in the 30th embodiment (Figure 101) is executed. If a power outage is detected, a positive determination is made in step S7608, and the power outage processing in steps S7609 to S7613 is executed.

Specifically, first, the power outage flag in the work area 221 for specific control is set to "1" (step S7609). As a result, if the power outage processing is executed normally and the information is properly stored in the main RAM 65, the power outage flag in the work area 221 for specific control will be set to "1" when the power supply to the main CPU 63 is restarted.

Subsequently, checksums are calculated for the specific control work area 221 and the specific control stack area 222 (step S7610). In this case, the storage areas in the specific control work area 221 and the specific control stack area 222 that are subject to calculation when calculating the specific control checksum are the same as the storage areas in the specific control work area 221 and the specific control stack area 222 that are subject to calculation of the specific control checksum in step S7701 of the checksum monitoring process (Figure 112) described later. Furthermore, the storage areas subject to calculation when calculating the specific control checksum include an area in the specific control work area 221 where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, a setting value counter). The calculated specific control checksum is then stored in a storage area in the specific control work area 221 that is excluded from the calculation of the specific control checksum, specifically for storing the specific control checksum.

Subsequently, checksums are calculated for the work area 223 and stack area 224 for non-specific control (step S7611). In this case, the storage areas in the work area 223 and stack area 224 for non-specific control that are subject to calculation when calculating the checksum for non-specific control are the same as the storage areas in the work area 223 and stack area 224 for non-specific control that are subject to checksum calculation in step S7706 of the checksum monitoring process (Figure 112) described later. Then, the calculated checksum for non-specific control is stored in the storage area in the work area 221 for specific control that stores the checksum for non-specific control but is excluded from the calculation of the checksum for specific control.

Subsequently, all output port information in the registers of the main CPU 63 is set to "0" (step S7612), and access to the main RAM 65 is prohibited (step S7613). Then, an infinite loop continues until the power supply is completely cut off and processing can no longer be performed.

Next, the checksum monitoring process executed by the main CPU 63 will be explained, referring to the flowchart in Figure 112. Note that the checksum monitoring process is executed in place of steps S6604 to S6606 in the main process (Figure 100). Furthermore, steps S7701 to S7711 in the checksum monitoring process are executed by the main CPU 63 using a specific control program and specific control data.

First, a checksum for specific control is calculated for the work area 221 and the stack area 222 for specific control (step S7701). The method for calculating this checksum is the same as in step S7610 of the power outage information storage processing (Figure 111). Then, the checksum for specific control, calculated in step S7610 of the power outage processing executed immediately before the power supply to the MPU 62 was stopped and stored in the work area 221, is read from the work area 221, and this read checksum is compared with the checksum calculated in step S7701 (step S7702). Finally, it is determined whether the checksums match (step S7703).

If the checksum for specific control does not match (step S7703: NO), a clear process for the work area 221 for specific control is performed (step S7704). In this clear process, the work area 221 for specific control is cleared to "0" and initial settings are performed, except for the area (specifically, the setting value counter) where setting value information indicating the setting state of the pachinko machine 10 is set. As a result, the area indicating whether the win/fail lottery mode is in high probability mode is cleared to "0", so the win/fail lottery mode becomes low probability mode regardless of the win/fail lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the situation becomes one in which no game rounds are being played, the opening/closing execution mode is not being executed, the general display unit 38a is not showing a variable display, and the general power mechanism 34a is in a closed state. Furthermore, the hold storage area 65a and the general-purpose hold area 65c, both located in the work area 221 for specific control, are also cleared to "0". This clears the hold information for the special display unit 37a and the general-purpose display unit 38a. In this clearing process, the various registers of the main CPU 63 are also cleared to "0" before initial settings are executed. Additionally, the stack area 222 for specific control is cleared to "0" and initial settings are executed (step S7705).

If a positive determination is made in step S7703, or if the process in step S7705 is executed, a checksum for non-specific control is calculated for the non-specific control work area 223 and the non-specific control stack area 224 (step S7706). The method for calculating this non-specific control checksum is the same as in step S7611 in the power outage information storage process (Figure 111). Then, the non-specific control checksum calculated in step S7611 of the power outage processing executed immediately before the power supply to the MPU 62 was stopped and stored in the specific control work area 221 is read from the specific control work area 221, and the read non-specific control checksum is compared with the non-specific control checksum calculated in step S7706 (step S7707). Finally, it is determined whether the non-specific control checksums match (step S7708).

If the checksum for non-specific control does not match (step S7708: NO), the information in the flag register of the main CPU 63 is saved to the specific control stack area 222 by a push instruction, "PUSH PSW" (step S7709). The flag register includes the carry flag, zero flag, P/V flag, sign flag, and half-carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. By saving this flag register information before the program of the subroutine corresponding to the clearing process for non-specific control starts, it is possible to save the flag register information in the specific control stack area 222 before it changes after the subroutine is called or after the subroutine starts. The amount of information in the flag register is 1 byte.

Subsequently, the program for the non-specific control clear process, which is set in the non-specific control program, is read, and the non-specific control clear process is started (step S7710). In this case, information for identifying the return address of the checksum monitoring process after the execution of the non-specific control clear process is written to the specific control stack area 222 by a push instruction. Then, when the non-specific control clear process is completed, the information for identifying the return address is read by a pop instruction, and the program returns to the checksum monitoring process indicated by that return address.

If the program returns to the error clearing program after executing the clearing process for non-specific control, the "POP PSW" instruction restores the information in the flag register that was saved in the stack area 222 for specific control in step S7709 to the flag register of the main CPU 63 (step S7711). This restores the information in the flag register of the main CPU 63 to the information at the time step S7709 was executed. In other words, the information in the flag register of the main CPU 63 is restored to the information necessary to execute the specific control.

Figure 113 is a flowchart showing the clearing process for non-specific control. Note that steps S7801 to S7818 in the clearing process for non-specific control are executed by the main CPU 63 using the non-specific control program and non-specific control data.

In the clearing process for non-specific control, steps S7801 to S7807 execute the same process as steps S7501 to S7507 in the clearing process for non-specific control in the 31st embodiment (Figure 110).

Subsequently, a partial clearing process is performed on the work area 223 for non-specific control (step S7808). In this partial clearing process, among the storage areas of the work area 223 for non-specific control, all storage areas except those where information on various registers of the main CPU 63 used in the processing corresponding to specific control is saved are cleared to "0". Specifically, among the storage areas of the work area 223 for non-specific control, the WA buffer, BC buffer, DE buffer, HL buffer, IX buffer, and IY buffer are not cleared to "0", while all other storage areas are cleared to "0".

In this case, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, the calculation result storage area 234, and the management start flag are all cleared to "0". This makes it possible to resolve information anomalies in the work area 223 for non-specific control. Furthermore, by not clearing the storage area where the information of various registers of the main CPU 63 used in the processing corresponding to specific control is saved to "0", it becomes possible to restore the information used in the processing corresponding to specific control to the various registers of the main CPU 63 when the processing corresponding to non-specific control ends and the system returns to the processing corresponding to specific control.

Subsequently, the initial setup process is executed (step S7809). During the initial setup process, initial settings are performed on the memory areas in the non-specific control work area 223 that were targeted for "0" clearing in step S7808.

Subsequently, a partial clearing process is performed on the non-specific control stack area 224 (step S7810). In this partial clearing process, all storage areas of the non-specific control stack area 224, except for the storage area containing the return address information for the checksum monitoring process (Figure 112) after the non-specific control clearing process is completed, are cleared to "0". This allows for the resolution of information anomalies in the non-specific control stack area 224 while preventing the return address information for the checksum monitoring process (Figure 112) from being erased after the non-specific control clearing process is completed.

Subsequently, the initial setup process is executed (step S7811). During the initial setup process, the memory areas in the non-specific control stack area 224 that were targeted for "0" clearing in step S7810 are initialized.

Subsequently, steps S7812 to S7818 are executed. These steps S7812 to S7818 execute the same processes as steps S7510 to S7516 in the clearing process for non-specific control (Figure 110) in the 31st embodiment described above.

According to the above configuration, checksums for the work area 221 and stack area 222 for specific control, and checksums for the work area 223 and stack area 224 for non-specific control are calculated separately. This makes it possible to individually identify information anomalies in the storage area corresponding to specific control and the storage area corresponding to non-specific control in the main RAM 65.

If an abnormality is found in the checksum for specific control, a "0" clear process and initialization process are executed for the work area 221 and stack area 222 for specific control. If an abnormality is found in the checksum for non-specific control, a "0" clear process and initialization process are executed for the work area 223 and stack area 224 for non-specific control. This makes it possible to narrow down the targets for the "0" clear process and initialization process to the areas where the checksum abnormality has been identified.

The processes for clearing the work area 221 and the stack area 222 for specific control to "0" and initializing them are executed by the process corresponding to the specific control, while the processes for clearing the work area 223 for non-specific control to "0" and initializing it are executed by the process corresponding to the non-specific control. This makes it possible to treat the work area 221 and the stack area 222 for specific control as dedicated storage areas for the process corresponding to the specific control, and the work area 223 for non-specific control as a dedicated storage area for the process corresponding to the non-specific control, even for the "0" clearing and initialization processes.

In step S7808 of the clear process for non-specific control (Figure 113), the management start flag is cleared to "0," but it is also possible to configure it so that the management start flag is not cleared to "0." Furthermore, in step S7808 of the clear process for non-specific control (Figure 113), the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233 may not be cleared to "0," and the calculation result storage area 234 may not be cleared to "0."

<Embodiment 33>
In this embodiment, the processing configuration executed by the main CPU 63 differs from that of the 15th embodiment described above. The configurations that differ from those of the 15th embodiment will be described below. Configurations that are the same as those of the 15th embodiment will generally not be described.

Figure 114 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S7901 to S7924 in the main processing are executed using a specific control program and specific control data on the main CPU 63.

First, the power-on initial setup process is executed (step S7901). During this process, for example, after the main process starts, the system waits for a predetermined waiting period (specifically, 1 second) before proceeding to the next process. During this predetermined waiting period, the operation and initial setup of the graphic display device 41 are completed. Access to the main RAM 65 is also permitted.

Subsequently, the internal function register setting process is executed (step S7902). In this process, the interrupt period of the first timer interrupt process (Figure 117), which is periodically interrupted and activated by the main process, is set to the first interrupt period (specifically, 4 milliseconds). The interrupt period of the second timer interrupt process (Figure 123), which is also periodically interrupted and activated by the main process, is set to the second interrupt period (specifically, 2 milliseconds), which is shorter than the first interrupt period.

In other words, in this embodiment, there are two timer interrupt processes, a first timer interrupt process and a second timer interrupt process, with relatively long and short interrupt periods. Both the first and second timer interrupt processes are initiated by interrupting the main process. Furthermore, the second timer interrupt process is initiated by interrupting the first timer interrupt process. On the other hand, the first timer interrupt process is not initiated by interrupting the second timer interrupt process. Also, if both the first and second timer interrupt processes have elapsed while neither is being executed, the second timer interrupt process is initiated first, regardless of the order in which those periods have elapsed. In this respect, the second timer interrupt process can be said to have higher priority than the first timer interrupt process.

In the internal function register setting process, the first interrupt period of the first timer interrupt process is set to a predetermined register in the main CPU 63, and the second interrupt period of the second timer interrupt process is set to a specific register in the main CPU 63. In addition to setting the first and second interrupt periods, the internal function register setting process also performs other operations, such as setting the numerical ranges of various counters, including the numerical range of the random number counter C1.

Subsequently, the startup processing flag located in the work area 221 for specific control is set to "1" (step S7903). The startup processing flag is used by the main CPU 63 to identify that even if the first timer interrupt process is activated, the various processes set for that first timer interrupt process should be terminated without execution. By setting the startup processing flag to "1," even if the first timer interrupt process is activated, the various processes set for that first timer interrupt process will not be executed, and the first timer interrupt process will terminate.

Subsequently, the interrupt enable setting is configured (step S7904). This causes the first timer interrupt process (Figure 117) to interrupt and start at the first interrupt cycle, and the second timer interrupt process (Figure 123) to interrupt and start at the second interrupt cycle. However, because the startup process flag is set to "1" in step S7903, even if the first timer interrupt process is started, the various processes set for that first timer interrupt process are not executed, and the first timer interrupt process terminates.

Subsequently, it is determined whether the reset button 68c is pressed (step S7905). That is, it is determined whether the power-on operation of the pachinko machine 10 was performed and the supply of operating power to the MPU 62 began while the reset button 68c was pressed. In this embodiment, the main control device 60 is provided with a setting key insertion section 68a and a reset button 68c, but not with an update button 68b. Furthermore, the main control device 60 is provided with first to fourth notification display devices 201 to 204, similar to the eleventh embodiment, instead of first to third notification display devices 69a to 69c.

If the reset button 68c is not pressed (step S7905: NO), it is determined whether the power outage flag in the work area 221 for specific control is set to "1" (step S7906). The power outage flag is set to "1" if the power outage processing is executed during the power outage information storage processing (step S8202) of the first timer interrupt processing (Figure 117), which will be described later. The power outage flag is used by the main CPU 63 to determine whether the power outage processing was performed appropriately during the previous power outage.

If the power outage flag is set to "1" (step S7906: YES), checksums are calculated for the specific control work area 221 and the specific control stack area 222 (step S7907). The method for calculating the checksum is arbitrary, but it is the same method used when the checksum is calculated during the power outage processing in the power outage information storage processing (step S8202) of the first timer interrupt processing (Figure 117), which will be described later. The checksum calculated during this power outage processing is stored in the specific control work area 221; however, the storage area of the specific control work area 221 where this checksum is stored is excluded from the storage areas used in the checksum calculation.

In other words, when calculating the checksum, the calculation targets certain memory areas within the specific control work area 221 and the specific control stack area 222. These calculation targets memory areas are those in which the checksum is calculated during the power outage processing when the supply of operating power to the MPU 62 is stopped, and from the time the supply of operating power to the MPU 62 is resumed until the processing in step S7907 is executed, if power supply, such as backup power, continues to be supplied to the specific control work area 221 and the specific control stack area 222, the information in these memory areas is basically not rewritten. Therefore, if the information in the specific control work area 221 and the specific control stack area 222 has not been changed between the time the supply of operating power to the MPU 62 is stopped and the time the supply of operating power to the MPU 62 is resumed, the checksums for the specific control work area 221 and the specific control stack area 222 will be the same as those immediately before the supply of operating power to the MPU 62 was stopped. Furthermore, the memory area included in the calculation of this checksum is the area (specifically, the setting value counter) in the work area 221 for specific control where setting value information indicating the setting state of the pachinko machine 10 is stored. Note that the work area 223 and the stack area 224 for non-specific control are not included in the calculation of the checksum.

Subsequently, the checksums for the specific control work area 221 and the specific control stack area 222, which were calculated and stored in the power outage processing performed immediately before the power supply to the MPU 62 was stopped, are read from the specific control work area 221. These read checksums are then compared with the checksum calculated in step S7907 (step S7908). Finally, it is determined whether the checksums match (step S7909).

If a negative determination is made in step S7906 or step S7909, that is, if the power outage flag is not set to "1" or the checksum does not match, the game stop flag provided in the work area 221 for specific control is set to "1" (step S7910). The game stop flag is a flag used by the main CPU 63 to determine whether or not the process in steps S8208 to S8221 should be stopped, based on a positive determination made in step S8207 of the first timer interrupt processing (Figure 117) described later, i.e., whether or not the process for advancing the game should be stopped. When the game stop flag is set to "1", the process in steps S8208 to S8221 is not executed because a positive determination is made in step S8207 of the first timer interrupt processing (Figure 117) described later. As a result, if the power outage flag is not set to "1" due to improper handling during the previous power outage, the game will be stopped. Furthermore, if the checksum does not match due to a change in the information storage state of at least one of the specific control work area 221 and specific control stack area 222 since the previous power outage, the game will be stopped.

In this case, the memory area used for calculating the checksum includes the area (specifically, the setting value counter) in the work area 221 for specific control, where information indicating the setting status of the pachinko machine 10 is stored. Therefore, if a setting value anomaly occurs after the last power outage, the checksum will not match, and the game will be stopped.

On the other hand, even when the game stop flag is set to "1", the processing in steps S8202 to S8206 of the first timer interrupt processing (Figure 117) is executed. Therefore, even when the game is stopped, power outage monitoring is performed, and the random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and further fraud detection is performed.

Subsequently, an abnormality command indicating that an abnormality occurred regarding the power outage flag or checksum at the start of power supply is transmitted to the voice and light emission control device 81 (step S7911). Upon receiving this abnormality command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the information abnormality at the start of power supply, and outputs the voice message "Please change the settings." from the speaker unit 54. Furthermore, the text image "Please change the settings." is displayed on the pattern display device 41. These notifications are maintained until the power supply to the pachinko machine 10 is stopped, at which point they terminate. However, even if the power supply to the pachinko machine 10 is temporarily stopped, the above notifications may be continued until the power supply to the pachinko machine 10 is resumed and the setting value update process (step S7918) is executed.

When the game has stopped, the administrator of the gaming hall who receives the above notification will temporarily stop the power supply to the pachinko machine 10, and then perform an operation to ensure that the setting value update process (step S7918) is executed when the power supply to the pachinko machine 10 is resumed. This makes it possible to set a new setting value in the setting value update process (step S7918) if an abnormality occurs regarding the power outage flag or checksum when the power supply is restarted.

In particular, the memory area used for calculating the checksum includes the area (specifically, the setting value counter) in the work area 221 for specific control, where setting value information indicating the setting state of the pachinko machine 10 is stored. Therefore, if an abnormality occurs in the checksum, there is a possibility that an abnormality has occurred in the setting value. In response to this, if an abnormality occurs regarding the checksum as described above, the execution of the setting value update process (step S7918) is prompted, preventing the game from being played with an abnormal setting value.

If the power outage flag is set to "1" and the checksum is normal (steps S7906 and S7909: YES), it is determined whether the setting key insertion unit 68a is turned ON using the setting key (step S7912), and it is determined whether the front door frame 14 is open relative to the inner frame 13 and the game machine body 12 is open relative to the outer frame 11 (step S7913). The detection of whether the front door frame 14 is open relative to the inner frame 13 is performed using the front door open sensor 95, as in the 30th embodiment described above, and the detection of whether the game machine body 12 is open relative to the outer frame 11 is performed using the body open sensor 96, as in the 30th embodiment described above. If the setting key insertion section 68a is turned ON using the setting key (step S7912: YES), and the front door frame 14 is open relative to the inner frame 13, and the game machine body 12 is open relative to the outer frame 11 (step S7913: YES), then the setting confirmation process is executed (step S7914). In the setting confirmation process, the first to fourth notification display devices 201 to 204, which are used to display various parameters that are the results of managing the game history, are used to display an indication that the current setting value of the pachinko machine 10 is being checked, and to display an indication of the current setting value of the pachinko machine 10.

Figure 115 is a flowchart showing the setting verification process. Note that steps S8001 to S8003 in the setting verification process are executed using the specific control program and specific control data in the main CPU 63.

First, the setting confirmation display flag located in the work area 221 for specific control is set to "1" (step S8001). The setting confirmation display flag is used by the main CPU 63 to identify that the current setting value of the pachinko machine 10 is being checked. When the setting confirmation display flag is set to "1", the second timer interrupt processing (Figure 123), described later, performs corresponding display control on the first to fourth notification display devices 201 to 204. As a result, the first to fourth notification display devices 201 to 204 display an indication that the current setting value of the pachinko machine 10 is being checked, and also display the current setting value of the pachinko machine 10.

Subsequently, it is determined whether the setting key insertion unit 68a has been turned OFF using the setting key (step S8002). In this case, the configuration may determine whether the setting key insertion unit 68a has switched from the ON state to the OFF state, or whether the setting key insertion unit 68a is already in the OFF state. If the setting key insertion unit 68a is not turned OFF (step S8002: NO), the process in step S8002 is repeated.

If the setting key insertion unit 68a is turned OFF (step S8002: YES), the setting confirmation display flag in the specific control work area 221 is cleared to "0" (step S8003). This cancels the display on the first to fourth notification display devices 201 to 204 that indicates the current setting value of the pachinko machine 10 is being checked, and the display showing the current setting value of the pachinko machine 10. In this case, the first to fourth notification display devices 201 to 204 begin displaying the game history management results.

As described above, in this embodiment, the power-on operation of the pachinko machine 10 is performed with the setting key insertion unit 68a turned ON by the setting key without pressing the reset button 68c. This initiates the supply of operating power to the main CPU 63 and the start of the main processing. At this point, the reset button 68c is not pressed and the setting key insertion unit 68a is turned ON. Therefore, the setting confirmation process is executed while the power supply start process is running, before the process enabling gameplay is executed in the main processing. This makes it possible to confirm the setting value even when gameplay is not taking place.

If we consider a scenario where the setting value is checked while the game is in progress, for example, if the setting value is checked in the middle of a game round, there is a risk that the system may transition to the opening/closing execution mode while the setting value check is still in progress. In this case, even though the opening/closing execution mode has started, it may not be possible to launch the game ball towards the special electric prize winning device 32. Furthermore, if the setting value is checked while the opening/closing execution mode is in progress, the opening/closing execution mode will proceed while the setting value check is in progress, and in this case as well, there is a risk that the game ball may not be able to launch towards the special electric prize winning device 32.

If we assume that the game will be stopped when the setting values are checked, then if the setting value check is started while the game is in progress, the process of stopping the game midway may become complicated. For example, if the setting value check is started in the middle of a game round and the game is to be stopped midway, processing will be required to stop the game round midway. In this case, if the display of the changing symbols on the symbol display device 41 is to be stopped midway when the setting value check is started, and the display of the changing symbols on the symbol display device 41 is to be resumed when the setting value check is finished, it will require a correspondingly complex process. Also, for example, if the setting value check is started in the middle of the execution of the opening/closing execution mode and the game is to be stopped midway, processing will be required to stop the opening/closing execution mode midway. Furthermore, if the setting value check is started in the middle of the display of the changing symbols on the general display unit 38a and the game is to be stopped midway, processing will be required to stop the display of the changing symbols midway. Furthermore, if the setting value is checked while the opening state of the regular electric device 34a is in progress, and the game is to be stopped midway, processing is required to stop the opening state midway. On the other hand, a configuration where the setting value is checked only after all games have finished is also conceivable. However, in this case, it becomes necessary to wait until none of the following are occurring: the number of game rounds, the opening/closing execution mode, the display of changing symbols on the regular diagram display unit 38a, or the opening state of the regular electric device 34a. This could lead to a longer waiting time before the setting value check can begin.

In contrast, the setting confirmation process is executed during the power supply start process, which is performed before the process that enables gameplay is executed in the main process that runs when power supply to the main CPU 63 is started. Therefore, the setting value is confirmed while gameplay has already stopped. This prevents the setting value from being confirmed while gameplay is in progress, and eliminates the need to stop gameplay midway or wait for gameplay to stop before confirming the setting value. Thus, the setting value can be confirmed appropriately.

Returning to the explanation of the main process (Figure 114), if the reset button 68c is pressed (step S7905: YES), the RAM clear process is executed (step S7915). In the RAM clear process, the work area 221 for specific control is cleared to "0" and initial settings are executed, except for the area (specifically, the setting value counter) where setting value information indicating the setting state of the pachinko machine 10 is set in the work area 221 for specific control. As a result, the area indicating whether the win/fail lottery mode is in high probability mode is cleared to "0", so the win/fail lottery mode becomes low probability mode regardless of the win/fail lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the situation becomes one in which no game rounds are being played, the opening/closing execution mode is not being executed, the general display unit 38a is not showing a variable display, and the general electric mechanism 34a is in a closed state. Furthermore, the hold storage area 65a and the general-purpose hold area 65c, both located in the work area 221 for specific control, are also cleared to "0". This clears the hold information for both the special display unit 37a and the general-purpose display unit 38a. The RAM clear process also clears the stack area 222 for specific control to "0" and performs initial settings. Additionally, the RAM clear process clears the various registers of the main CPU 63 to "0" before performing initial settings. These initial settings perform the same processing as the internal function register setting process (step S7902).

On the other hand, the RAM clear process does not clear the work area 223 and the stack area 224 for non-specific control to "0". This makes it possible to prevent the work area 223 and the stack area 224 for non-specific control from being cleared to "0" by a clear operation performed by the administrator of the gaming hall.

Subsequently, it is determined whether the setting key insertion unit 68a is turned ON using the setting key (step S7916), and whether the front door frame 14 is open relative to the inner frame 13 and the game machine body 12 is open relative to the outer frame 11 (step S7917). The detection of whether the front door frame 14 is open relative to the inner frame 13 is performed using the front door open sensor 95, as in the 30th embodiment, and the detection of whether the game machine body 12 is open relative to the outer frame 11 is performed using the main body open sensor 96, as in the 30th embodiment. If the setting key insertion unit 68a is turned ON using the setting key (step S7916: YES), and further, the front door frame 14 is open relative to the inner frame 13 and the game machine body 12 is open relative to the outer frame 11 (step S7917: YES), then the setting value update process is executed (step S7918).

Figure 116 is a flowchart showing the setting value update process. Note that steps S8101 to S8107 in the setting value update process are executed using the specific control program and specific control data in the main CPU 63.

First, the setting update display flag located in the work area 221 for specific control is set to "1" (step S8101). The setting update display flag is used by the main CPU 63 to identify that the settings of the pachinko machine 10 are being updated. When the setting update display flag is set to "1", the second timer interrupt processing (Figure 123), described later, performs corresponding display control on the first to fourth notification display devices 201 to 204. As a result, the first to fourth notification display devices 201 to 204 display an indication that the settings of the pachinko machine 10 are being updated, and also display the current settings of the pachinko machine 10.

Subsequently, it is determined whether the value of the set value counter provided in the specific control work area 221 is 1 or greater, corresponding to "Setting 1," and 6 or less, corresponding to "Setting 6" (Step S8102). If the value of the set value counter is "0" or 7 or greater, a negative determination is made in Step S8102, and "1" is set in the set value counter (Step S8103). As a result, the setting value of the pachinko machine 10 becomes "Setting 1."

If a positive determination is made in step S8102 or the process in step S8103 is executed, it is determined whether the setting key insertion unit 68a is being turned OFF using the setting key (step S8104). In this case, the configuration may determine whether the setting key insertion unit 68a has switched from the ON state to the OFF state, or whether the configuration determines whether the setting key insertion unit 68a is in the OFF state.

If the setting key insertion section 68a is not in the OFF position (step S8104: NO), and provided that the reset button 68c is pressed (step S8105: YES), the value of the setting value counter in the work area 221 for specific control is incremented by 1 (step S8106). This means that each time the reset button 68c is pressed, the setting value is updated to one level higher. If the reset button 68c is not pressed (step S8105: NO) or if the setting value counter is incremented by 1, the process returns to step S8102. However, if it is determined in step S8102 that the setting value counter is 7 or greater, the setting value counter is set to "1" in step S8103. This means that if the reset button 68c is pressed once while in the "Setting 6" state, the system returns to "Setting 1".

If the setting key insertion unit 68a is turned OFF (step S8104: YES), the setting update display flag in the specific control work area 221 is cleared to "0" (step S8107). This cancels the display on the first to fourth notification display devices 201 to 204 that indicates the setting value of the pachinko machine 10 is being updated, and the display showing the current setting value of the pachinko machine 10. In this case, the first to fourth notification display devices 201 to 204 begin displaying the game history management results.

As described above, in this embodiment, when the reset button 68c is pressed while the power of the pachinko machine 10 is turned ON, the supply of operating power to the main CPU 63 begins and the main processing starts. At this point, the reset button 68c is pressed, and the RAM clear process (step S7915) is executed regardless of whether the setting key insertion unit 68a is turned ON or not. This ensures that the operation of pressing the reset button 68c while turning on the power of the pachinko machine 10 is uniquely linked to the execution of the RAM clear process (step S7915), making the operation required to trigger the RAM clear process (step S7915) easily understandable to the administrator of the gaming hall.

Even if the RAM clear process (step S7915) is executed, the setting value counter in the work area 221 for specific control is not cleared to "0," and the information in the setting value counter is not changed. This makes it possible to prevent the setting value from being changed even when the RAM clear process (step S7915) is executed.

When the reset button 68c is pressed while the power of the pachinko machine 10 is turned ON, and the setting key insertion unit 68a is also turned ON using the setting key while the power of the pachinko machine 10 is turned ON, not only is the RAM clear process (step S7915) executed, but the setting value update process (step S7918) is also executed. Furthermore, as already explained, when the setting key insertion unit 68a is turned ON using the setting key while the power of the pachinko machine 10 is turned ON without pressing the reset button 68c, the setting confirmation process (step S7914) is executed. This makes it possible to standardize the ON operation of the setting key insertion unit 68a as the operation required to execute the setting value-related processing. Therefore, the operation required to trigger the setting value-related processing can be made easily understandable to the administrator of the gaming hall.

Furthermore, when the setting key insertion unit 68a is turned ON using the setting key while the power of the pachinko machine 10 is turned ON, if the reset button 68c is not pressed, a setting confirmation process is executed. If the reset button 68c is pressed, a setting value update process is executed. This makes it possible to differentiate between the setting confirmation process and the setting value update process depending on whether the reset button 68c is pressed. Therefore, it becomes possible to make the operation content for executing the desired process among the setting confirmation process and the setting value update process easy for the administrator of the gaming hall to understand. Also, by making the operation content for executing the setting value update process more extensive than that for the setting confirmation process, it becomes particularly difficult to perform acts that fraudulently execute the setting value update process.

Returning to the explanation of the main process (Figure 114), if the process in step S7911 is executed, if a negative determination is made in step S7912 or step S7913, if the process in step S7914 is executed, if a negative determination is made in step S7916 or step S7917, or if the process in step S7918 is executed, the startup processing flag in the work area 221 for specific control is cleared to "0" (step S7919). Clearing the startup processing flag to "0" cancels the state in which various processes set in the first timer interrupt process are not executed even if the first timer interrupt process is activated. Note that in step S7919, the power outage flag in the work area 221 for specific control is also cleared to "0".

Subsequently, a recovery command is transmitted to the audio and light emission control device 81 (step S7920). The recovery command includes information indicating the number of reserved information for the special symbol display unit 37a, information indicating the current win/loss lottery mode, information indicating the current support mode, information indicating whether the opening/closing execution mode is in progress, and information indicating whether the game round is in progress. This information is set based on information stored in the work area 221 for specific control. Upon receiving the recovery command, the audio and light emission control device 81 sets the display content of the symbol display device 41, the light emission content of the display light emission unit 53, and the sound output content of the speaker unit 54 to correspond to the various information set in the recovery command.

In this case, when checking the settings of the pachinko machine 10, it is necessary to turn on the setting key insertion unit 68a using the setting key while simultaneously turning on the power of the pachinko machine 10. Therefore, if it becomes necessary to check the settings during a game, for example, the power of the pachinko machine 10 will be turned off during the game, and then the power of the pachinko machine 10 will be turned on again while simultaneously turning on the setting key insertion unit 68a using the setting key. In this case, since no backup power is supplied to the RAM in the sound and light emission control device 81, the information in the RAM of the sound and light emission control device 81 used to control the game's effects is erased when the power of the pachinko machine 10 is turned off. In contrast, the main RAM 65 is supplied with backup power, and the main RAM 65 is not cleared when the setting value is checked. Therefore, if the pachinko machine 10 is turned OFF during gameplay, and then the setting key insertion unit 68a is turned ON using the setting key while the pachinko machine 10 is turned ON again, the display of changing symbols will resume on the special symbol display unit 37a after the setting confirmation process is executed. This results in a situation where the display of changing symbols is shown on the special symbol display unit 37a, but not on the symbol display device 41.

In response to this, after the setting confirmation process is completed, a return command is sent to the sound and light emission control device 81, and this return command includes information indicating whether or not a game round is currently in progress. When the sound and light emission control device 81 receives the return command, it starts displaying the changing symbols on the symbol display device 41. This prevents a situation from occurring where the symbol changing symbols are displayed on the special symbol display unit 37a, but not on the symbol display device 41. The changing symbols are displayed at a relatively fast speed so that each symbol during the display is indistinguishable or difficult to distinguish for the player. Furthermore, the return command does not include the results of the win/loss determination process and the distribution determination process for the game round to be resumed, nor does it include information indicating the end timing of the game round to be resumed. Therefore, when the sound and light emission control device 81 starts displaying the changing symbols on the symbol display device 41 based on a return command, if the game round to be resumed corresponds to a losing result, it will terminate the display of the changing symbols based on the return command and start the display corresponding to the newly received command when it receives a command to start the next game round or a demo display on the symbol display device 41. If the game round to be resumed corresponds to a jackpot result, it will terminate the display of the changing symbols based on the return command and start the opening animation when it receives an opening command indicating the start of the opening/closing execution mode.

Furthermore, if the recovery command includes information indicating that the opening/closing execution mode is in progress, the sound and light emission control device 81 will initiate a display animation on the symbol display device 41 indicating that the opening/closing execution mode is in progress. This makes it possible to inform the player that the opening/closing execution mode is in progress.

Subsequently, the process proceeds to the residual processing steps S7921 to S7924. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt process (Figure 117) and the second timer interrupt process (Figure 123), but residual time occurs between one timer interrupt process and the next. This residual time varies depending on the processing completion time of each timer interrupt process, and the residual processing steps S7921 to S7924 are repeatedly executed using this irregular time. In this respect, the residual processing steps S7921 to S7924 can be considered an irregular process that is executed irregularly. Steps S7921 to S7924 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

Next, the first timer interrupt processing, executed by the main CPU 63, will be explained with reference to the flowchart in Figure 117. As previously explained, the first timer interrupt processing is activated periodically at a 4-millisecond interval, which is the first interrupt period. Furthermore, the program corresponding to the first timer interrupt processing is set as a specific control program.

First, it is determined whether the startup processing flag in the work area 221 for specific control is set to "1" (step S8201). As already explained, the startup processing flag is set to "1" in step S7903 of the main processing (Figure 114). If the startup processing flag is set to "1" (step S8201: YES), the first timer interrupt processing is terminated without executing the various processes in steps S8202 to S8221. This makes it possible to prevent the execution of various processes for controlling the progress of the game in the first timer interrupt processing, even if the execution of the first timer interrupt processing is permitted early when the supply of operating power to the pachinko machine 10 starts and the main processing (Figure 114) begins.

As already explained, the startup flag is cleared to "0" in step S7919 when the process for starting the supply of operating power in the main process (Figure 114) is completed. In the first timer interrupt process, if the startup flag is not set to "1" (step S8201: NO), the processes from step S8202 onwards are executed.

Steps S8202 to S8219 and S8221 execute the same processes as steps S3701 to S3719 of the timer interrupt processing (Figure 69) in the 15th embodiment described above. These processes are executed by the main CPU 63 using a program and data for specific control. In this case, as already explained, if the main processing (Figure 114) determines that the power outage flag is not set to "1" (step S7906: NO) or that the checksums do not match (step S7909: NO), the game stop flag in the work area 221 for specific control is set to "1" (step S7910). If the game stop flag is set to "1", the first timer interrupt processing executes the processes in steps S8201 to S8206, but does not execute the processes in steps S8208 to S8221 by making an affirmative determination in step S8207. As a result, if the power outage flag is not set to "1" due to improper handling during the previous power outage, the game will be stopped. Furthermore, if the checksum does not match due to a change in the information storage state of at least one of the specific control work area 221 and specific control stack area 222 since the previous power outage, the game will be stopped. For example, if the process in step S8212 is not executed, the launch of game balls is prohibited. Also, if the process in step S8214 is not executed, the execution of game rounds and the opening/closing execution mode is prohibited. Finally, if the process in step S8218 is not executed, the payout of game balls is prohibited.

On the other hand, even when the game is stopped in this manner, power outage monitoring is performed in step S8202, and the random number counter C1, jackpot type counter C2, reach random number counter C3, and initial random number counter CINI are updated in steps S8203 and S8204. Furthermore, fraud detection is performed in step S8206.

In the first timer interrupt processing, the setting monitoring process is executed in step S8220. Figure 118 is a flowchart of the setting monitoring process. Note that the processing in steps S8301 to S8303 of the setting monitoring process is executed using the specific control program and specific control data in the main CPU 63.

The system determines whether the setting value of the pachinko machine 10 is normal or not by checking the value of the setting value counter in the work area 221 for specific control (step S8301). Specifically, it is determined to be normal if the setting value set in the setting value counter is one of "Setting 1" to "Setting 6," and abnormal if it is "0" or 7 or higher.

If the setting value is abnormal (step S8301: NO), the game stop flag in the work area 221 for specific control is set to "1" (step S8302), similar to step S7910 in the main process (Figure 114). Setting the game stop flag to "1" results in a positive determination in step S8207 of the first timer interrupt process (Figure 117), preventing the execution of steps S8208 to S8221. This stops the game if an abnormal setting value is detected. However, even with the game stop flag set to "1," steps S8202 to S8206 of the first timer interrupt process (Figure 117) are still executed. Therefore, even with the game stopped, power outage monitoring is performed, and the winning random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and fraud detection is performed.

Subsequently, an error command indicating that the setting value is abnormal is sent to the voice and light emission control device 81 (step S8303). Upon receiving this error command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the abnormal setting value, and outputs the voice message "Please change the setting." from the speaker unit 54. Furthermore, the text image "Please change the setting." is displayed on the pattern display device 41. These notifications are maintained until the power supply to the pachinko machine 10 is stopped, at which point they terminate. However, even if the power supply to the pachinko machine 10 is temporarily stopped, the notifications may be configured to continue once the power supply to the pachinko machine 10 is resumed, until the setting value update process (step S7918) of the main process (Figure 114) is executed.

When the game has stopped, the administrator of the gaming hall who receives the above notification will temporarily stop the power supply to the pachinko machine 10, and then perform an operation to ensure that the setting value update process (step S7918) is executed when the power supply to the pachinko machine 10 is resumed. This makes it possible to set a new setting value via the setting value update process (step S7918) if an abnormal setting value occurs.

Here, a monitoring process to check whether the setting value is abnormal is executed by the first timer interrupt process (Figure 117), which is periodically triggered. This makes it possible to monitor whether the setting value is abnormal even while gameplay is in progress. Therefore, it is possible to prevent gameplay from continuing even if the setting value is abnormal. Furthermore, the monitoring of whether the setting value is abnormal is executed each time a monitoring trigger occurs. This allows for an increased frequency of monitoring whether the setting value is abnormal.

The main process (Figure 114) does not include any processing to monitor whether the set value is normal or not. If the main process (Figure 114) included processing to monitor whether the set value is normal or not during the power supply initiation process, it would become necessary to monitor not only the power outage flag and checksum but also whether the set value is normal or not, increasing the monitoring load. Furthermore, if the system were to execute a RAM clear process (step S7915) and a set value update process (step S7918) when an abnormal set value is identified during the power supply initiation process, the processing configuration would become more complex. In contrast, because the main process (Figure 114) does not include processing to monitor whether the set value is normal or not, it is possible to optimize the processing configuration for the power supply initiation process. Even without processing to monitor whether the set value is normal or not during the power supply initiation process, as described above, the first timer interrupt process (Figure 117) executes a setting monitoring process (step S8220), allowing for action to be taken if the set value is abnormal.

In the configuration in which the first timer interrupt processing is executed as described above, in this embodiment, as already explained, there is a second timer interrupt processing (Figure 123) separate from the first timer interrupt processing (Figure 117), and the second timer interrupt processing is started by interrupting the first timer interrupt processing even if the first timer interrupt processing is in progress. In this case, although not shown in the figures, the first timer interrupt processing prohibits and enables the timer interrupt processing before and after each of the processes in steps S8201 to S8221. For example, the timer interrupt processing is prohibited before executing the random number update processing for lottery (step S8203), and enabled after executing the random number update processing for lottery (step S8203). This makes it possible to prevent the second timer interrupt processing from being interrupted and started while the random number update processing for lottery is in progress. Furthermore, timer interrupt processing is prohibited before executing the special drawing and special electrical control processing (step S8214), and timer interrupt processing is enabled after executing the special drawing and special electrical control processing (step S8214). This prevents the second timer interrupt processing from being interrupted and activated while the special drawing and special electrical control processing is in progress.

Next, we will describe the configuration for controlling the display of various display units using the main CPU 63. Figure 119 is a block diagram illustrating the configuration for controlling the display of various display units using the main CPU 63.

The main CPU 63 controls the display of the following: the special feature display unit 37a, the special feature hold display unit 37b, the general feature display unit 38a, the general feature hold display unit 38b, and the first to fourth notification display devices 201 to 204. These are all segment display units, each consisting of multiple LED display segments arranged in a single array. These segment display units become illuminated when data corresponding to the illumination state (for example, the "1" data, one of the binary data) is set, and become unlit when data corresponding to the off state (for example, the "0" data, the other of the binary data) is set.

The main control board 61 is provided with a first display circuit 261 corresponding to the special drawing display unit 37a, a second display circuit 262 corresponding to the special drawing hold display unit 37b, a third display circuit 263 corresponding to the general drawing display unit 38a, a fourth display circuit 264 corresponding to the general drawing hold display unit 38b, and a fifth display circuit 265 corresponding to the first to fourth notification display devices 201 to 204. In the 11th embodiment described above, the main control board 61 was configured to have first to fourth display ICs 205 to 208 in a one-to-one correspondence with the first to fourth notification display devices 201 to 204; however, in this embodiment, these first to fourth display ICs 205 to 208 are not provided.

The first display circuit 261 provides data corresponding to the supplied display data to each of the multiple display segments of the special-vision display unit 37a. As a result, each display segment of the special-vision display unit 37a becomes either illuminated or unlit in a manner corresponding to the display data provided to the first display circuit 261. In this case, although the first display circuit 261 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), after the predetermined period has elapsed, the display data gradually approaches an all-zero state. Therefore, the display segments of the special-vision display unit 37a that are illuminated due to the display data provided to the first display circuit 261 gradually become unlit as the predetermined period elapses without new display data being provided to the first display circuit 261. Furthermore, with this configuration, the same display data as the previous display data output processing cycle is supplied to the first display circuit 261 not only when the display content of the special-vision display unit 37a is changed, but also when the display content of the special-vision display unit 37a is not changed.

The number of display segments provided in the special display unit 37a is eight. Therefore, eight-bit data is provided to the first display circuit 261 as display data for controlling the display of the special display unit 37a.

The second display circuit 262 provides data corresponding to the supplied display data to each of the multiple display segments of the special feature hold display unit 37b. As a result, each display segment of the special feature hold display unit 37b becomes either illuminated or unlit in a manner corresponding to the display data provided to the second display circuit 262. In this case, although the second display circuit 262 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), after the predetermined period has elapsed, the display data gradually approaches an all-zero state. Therefore, the display segments of the special feature hold display unit 37b that are illuminated due to the display data provided to the second display circuit 262 gradually become unlit as the predetermined period elapses without new display data being provided to the second display circuit 262. Furthermore, with this configuration, the same display data as the previous display data output processing cycle is supplied to the second display circuit 262 not only when the display content of the special feature hold display unit 37b changes, but also when the display content of the special feature hold display unit 37b does not change.

The number of display segments provided in the special feature hold display unit 37b is four. Therefore, four bits of data are provided to the second display circuit 262 as display data for controlling the display of the special feature hold display unit 37b. However, since the display data is provided in eight-bit units, eight bits of data are provided to the second display circuit 262, but four of these bits are used as display data for controlling the display of the special feature hold display unit 37b.

The third display circuit 263 provides data corresponding to the supplied display data to each of the multiple display segments of the general-purpose display unit 38a. As a result, each display segment of the general-purpose display unit 38a becomes either illuminated or unlit in a manner corresponding to the display data provided to the third display circuit 263. In this case, although the third display circuit 263 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), after the predetermined period has elapsed, the display data gradually approaches an all-zero state. Therefore, the display segments of the general-purpose display unit 38a that are illuminated due to the display data provided to the third display circuit 263 gradually become unlit as the predetermined period elapses without new display data being provided to the third display circuit 263. Furthermore, with this configuration, the same display data as the previous display data output processing cycle is supplied to the third display circuit 263 not only when the display content of the general-purpose display unit 38a changes, but also when the display content of the general-purpose display unit 38a does not change.

The number of display segments provided in the general diagram display unit 38a is eight. Therefore, eight bits of data are provided to the third display circuit 263 as display data for controlling the display of the general diagram display unit 38a.

The fourth display circuit 264 provides data corresponding to the supplied display data to each of the multiple display segments of the general display hold display unit 38b. As a result, each display segment of the general display hold display unit 38b becomes either illuminated or unlit in a manner corresponding to the display data provided to the fourth display circuit 264. In this case, although the fourth display circuit 264 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), after the predetermined period has elapsed, the display data gradually approaches an all-zero state. Therefore, the display segments of the general display hold display unit 38b that are illuminated due to the display data provided to the fourth display circuit 264 gradually become unlit as the predetermined period elapses without new display data being provided to the fourth display circuit 264. Furthermore, with this configuration, the same display data as the previous display data output processing cycle is supplied to the fourth display circuit 264, not only when the display content of the general display hold display unit 38b changes, but also when the display content of the general display hold display unit 38b does not change.

The number of display segments provided in the general display hold display unit 38b is four. Therefore, four bits of data are provided to the fourth display circuit 264 as display data for controlling the display of the general display hold display unit 38b. However, since the display data is provided in eight-bit units, eight bits of data are provided to the fourth display circuit 264 when display data is provided, but four of these bits are used as display data for controlling the display of the general display hold display unit 38b.

The fifth display circuit 265 provides data corresponding to the supplied display data to each of the multiple display segments provided in each of the first to fourth notification display devices 201 to 204. As a result, each display segment of the first to fourth notification display devices 201 to 204 becomes either illuminated or unlit in a manner corresponding to the display data provided to the fifth display circuit 265. In this case, although the fifth display circuit 265 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), after the predetermined period has elapsed, the display data will gradually approach a state of all "0". Therefore, the display segments of the first to fourth notification display devices 201 to 204 that are illuminated by the display data provided to the fifth display circuit 265 will gradually become unlit as the predetermined period elapses without new display data being provided to the fifth display circuit 265. Furthermore, with this configuration, the same display data as the previous display data output processing cycle is supplied to the fifth display circuit 265, not only when the display content of the first to fourth notification display devices 201 to 204 is changed, but also when the display content of the first to fourth notification display devices 201 to 204 is not changed.

Each of the first to fourth notification display devices 201 to 204 is provided with seven display segments. Display data is provided in 8-bit units. When display data for the first to fourth notification display devices 201 to 204 is provided to the fifth display circuit 265, the 7-bit display data corresponding to the first notification display device 201 is provided as an 8-bit unit, followed by the 7-bit display data corresponding to the second notification display device 202, then the 7-bit display data corresponding to the third notification display device 203, and finally the 7-bit display data corresponding to the fourth notification display device 204.

In the configuration described above, where the first to fifth display circuits 261 to 265 are provided, the main CPU 63 supplies display data to the display IC 266. That is, the display IC 266 is not provided on a one-to-one basis for each of the first to fifth display circuits 261 to 265; rather, a single display IC 266 is provided that is common to all five display circuits 261 to 265. Furthermore, when the main CPU 63 supplies display data to the display IC 266, it also supplies type data to the display IC 266 indicating which of the first to fifth display circuits 261 to 265 the display data corresponds to.

Regarding the electrical connection between the main CPU 63 and the display IC 266, the main CPU 63 and the display IC 266 are electrically connected using the type data signal line LN1, the type clock signal line LN2, the display data signal line LN3, and the display clock signal line LN4. These signal lines LN1 to LN4 are all signal lines for transmitting signals from the main CPU 63 to the display IC 266 in one-way communication.

Type data is transmitted serially from the main CPU 63 to the display IC 266 using the type data signal line LN1. In this case, the separation of each 1-bit of the type data transmitted serially is indicated by the type clock signal transmitted from the main CPU 63 to the display IC 266 using the type clock signal line LN2. The type data indicates which of the first to fifth display circuits 261 to 265 the display data being transmitted corresponds to. The type data is transmitted as 5-bit data consisting of bits 1 to 5. If the display data corresponds to the first display circuit 261, the first bit is set to HI level and the other bits are set to LOW level. If the display data corresponds to the second display circuit 262, the second bit is set to HI level and the other bits are set to LOW level. If the display data corresponds to the third display circuit 263, the third bit is set to HI level and the other bits are set to LOW level. If the display data corresponds to the fourth display circuit 264, the fourth bit is set to HI level and the other bits are set to LOW level. If the displayed data corresponds to the fifth display circuit 265, the fifth bit will be set to a HI level, while the other bits will be set to a LOW level.

Display data is transmitted serially from the main CPU 63 to the display IC 266 using the display data signal line LN3. In this case, the delimiter of each single bit of the display data transmitted serially is indicated by the display clock signal transmitted from the main CPU 63 to the display IC 266 using the display clock signal line LN4. The display data is transmitted in 8-bit units, consisting of bits 1 through 8.

The main CPU 63 transmits display data corresponding to each of the first to fifth display circuits 261 to 265 to the display IC 266 in the second timer interrupt processing (Figure 123), which will be described later. In this case, in one processing run of the second timer interrupt processing, display data is transmitted to one of the first to fifth display circuits 261 to 265, and each time a new processing run of the second timer interrupt processing occurs, the display circuits 261 to 265 to which the display data is transmitted are changed one by one in the order of nth display circuit → n+1th display circuit. Furthermore, in the second timer interrupt processing run following the processing run in which the display data corresponding to the fifth display circuit 265, which is the last in that order, is transmitted, the display data corresponding to the first display circuit 261, which is the first in that order, is transmitted. Furthermore, in the second timer interrupt process that transmits display data to one of the first to fourth display circuits 261 to 264, only one 8-bit unit of display data is transmitted. However, in the second timer interrupt process that transmits display data to the fifth display circuit 265, four 8-bit units of display data are transmitted, corresponding to the number of first to fourth notification display devices 201 to 204.

As described above, in the configuration where the main CPU 63 transmits display data, various storage areas are configured in the work area 221 for specific control and the work area 223 for non-specific control, which are referenced by the main CPU 63 for transmitting display data. Figure 120(a) is an explanatory diagram illustrating the various buffers 271 to 275 provided in the work area 221 for specific control, and Figure 120(b) is an explanatory diagram illustrating the various storage areas 234 and 276 provided in the work area 223 for non-specific control.

As shown in Figure 120(a), the work area 221 for specific control is provided with a first display data buffer 271, a second display data buffer 272, a third display data buffer 273, a fourth display data buffer 274, and a fifth display data buffer 275.

The first display data buffer 271 stores display data to be supplied to the first display circuit 261. As explained earlier, the first display circuit 261 is provided in correspondence with the special display unit 37a; therefore, the first display data buffer 271 stores display data necessary to cause the special display unit 37a to perform a predetermined display. In this case, the storage of display data in the first display data buffer 271 is performed in the display control process (step S8216) based on the contents of the special control process (step S8214) in the first timer interrupt process (Figure 117). Furthermore, when the second timer interrupt process (Figure 123), which transmits display data to the first display circuit 261, occurs, the display data stored in the first display data buffer 271 is transmitted to the display IC 266 not only if the display data stored in the first display data buffer 271 has been changed, but also if the display data has not been changed.

The second display data buffer 272 stores display data to be supplied to the second display circuit 262. As explained earlier, the second display circuit 262 is provided in correspondence with the special-print hold display unit 37b; therefore, the second display data buffer 272 stores display data necessary to cause the special-print hold display unit 37b to perform a predetermined display. In this case, the storage of display data in the second display data buffer 272 is performed in the display control process (step S8216) based on the contents of the special-print special-electric control process (step S8214) in the first timer interrupt process (Figure 117). Furthermore, when the second timer interrupt process (Figure 123), which transmits display data to the second display circuit 262, occurs, the display data stored in the second display data buffer 272 is transmitted to the display IC 266 not only if the display data stored in the second display data buffer 272 has been changed, but also if the display data has not been changed.

The third display data buffer 273 stores display data to be supplied to the third display circuit 263. As explained earlier, the third display circuit 263 is provided in correspondence with the general display unit 38a; therefore, the third display data buffer 273 stores display data necessary to cause the general display unit 38a to perform a predetermined display. In this case, the storage of display data in the third display data buffer 273 is performed in the display control process (step S8216) based on the contents of the general display control process (step S8215) in the first timer interrupt process (Figure 117). Furthermore, when the second timer interrupt process (Figure 123), which transmits display data to the third display circuit 263, occurs, the display data stored in the third display data buffer 273 is transmitted to the display IC 266 not only if the display data stored in the third display data buffer 273 has been changed, but also if the display data has not been changed.

The fourth display data buffer 274 stores display data to be supplied to the fourth display circuit 264. As explained earlier, the fourth display circuit 264 is provided in correspondence with the general display hold display unit 38b; therefore, the fourth display data buffer 274 stores display data necessary to cause the general display hold display unit 38b to perform a predetermined display. In this case, the storage of display data in the fourth display data buffer 274 is performed in the display control process (step S8216) based on the contents of the general display power control process (step S8215) in the first timer interrupt process (Figure 117). Furthermore, when the second timer interrupt process (Figure 123), which transmits display data to the fourth display circuit 264, occurs, the display data stored in the fourth display data buffer 274 is transmitted to the display IC 266 not only if the display data stored in the fourth display data buffer 274 has been changed, but also if the display data has not been changed.

The fifth display data buffer 275 stores display data to be supplied to the fifth display circuit 265. As previously explained, the fifth display circuit 265 is provided in correspondence with the first to fourth notification display devices 201 to 204. Therefore, the fifth display data buffer 275 stores display data necessary to cause the first to fourth notification display devices 201 to 204 to display a predetermined information. When the second timer interrupt process, which transmits display data to the fifth display circuit 265, occurs, the display data stored in the fifth display data buffer 275 is transmitted to the display IC 266 not only if the display data stored in the fifth display data buffer 275 has been changed, but also if the display data has not been changed.

Here, the first to fourth notification display devices 201 to 204 display the results corresponding to the game history management, and when a setting confirmation process (Figure 115) or a setting value update process (Figure 116) is executed, the current setting value is displayed. In this case, since the fifth display data buffer 275 is located in the work area 221 for specific control, the process of storing display data in the fifth display data buffer 275 is performed as a process corresponding to specific control. On the other hand, the process for deriving the game history management results is performed as a process corresponding to non-specific control, and the 61st to 68th parameters, which are the game history management results, are sequentially displayed on the first to fourth notification display devices 201 to 204.

Therefore, as shown in Figure 120(b), the work area 223 for non-specific control is provided not only with a calculation result storage area 234 for storing the 61st to 68th parameters, but also with a display target setting area 276 for storing the parameters from the 61st to 68th parameters that are to be displayed on the 1st to 4th notification display devices 201 to 204. In this embodiment as well, similar to the 15th embodiment described above, the period during which the calculation result of a single parameter is continuously displayed is 10 seconds. Therefore, in the processing corresponding to non-specific control, every 10 seconds, the calculation results of the parameters to be displayed are read from the calculation result storage area 234 according to a predetermined display order, and the calculation results of the read parameters are stored in the display target setting area 276. Furthermore, when the first to fourth notification display devices 201 to 204 are in a state where the game history management results are to be displayed, the second timer interrupt process (Figure 123), which is a process corresponding to specific control, reads the display data stored in the display target setting area 276, and the read display data is stored in the fifth display data buffer 275.

On the other hand, when the setting confirmation process (Figure 115) is being executed, the second timer interrupt process (Figure 123), which corresponds to the specific control, stores display data in the fifth display data buffer 275 to enable the first to fourth notification display devices 201 to 204 to display an indication that the current setting value of the pachinko machine 10 is being confirmed, and to display an indication that the current setting value of the pachinko machine 10 is being displayed. Furthermore, when the setting value update process (Figure 116) is being executed, the second timer interrupt process (Figure 123), which corresponds to the specific control, stores display data in the fifth display data buffer 275 to enable the first to fourth notification display devices 201 to 204 to display an indication that the setting value of the pachinko machine 10 is being updated, and to display an indication that the current setting value of the pachinko machine 10 is being displayed.

In the configuration described above, where the first to fifth display data buffers 271 to 275 are provided, the main CPU 63 reads display data from the display data buffers 271 to 275 corresponding to each processing round of the second timer interrupt processing (Figure 123), transmits the read display data to the display IC 266, and also transmits type data to the display IC 266 indicating which of the first to fifth display circuits 261 to 265 the display data corresponds to. Figure 121 is an explanatory diagram illustrating the electrical configuration of the display IC 266.

As shown in Figure 121, the display IC 266 comprises a type data buffer 281, a selection signal output unit 282, a display data buffer 283, and a display data output unit 284. The display data buffer 283 stores the display data received from the main CPU 63. The display data output unit 284 transmits the display data stored in the display data buffer 283 to the first to fifth display circuits 261 to 265. The type data buffer 281 stores the type data received from the main CPU 63. The selection signal output unit 282 outputs a selection signal to specify the display circuits 261 to 265 corresponding to the type data stored in the type data buffer 281 as the destination for receiving the display data.

As shown in detail in Figure 119, the display IC 266 and the first display circuit 261 are electrically connected using a display signal group 291. The display signal group 291 is designed to enable the transmission of 8 bits of display data at once, and this 8-bit display data is transmitted from the display IC 266 via parallel communication. Furthermore, a branch signal group 292 is provided, branched from the display signal group 291, and this branch signal group 292 is electrically connected to the second display circuit 262, the third display circuit 263, the fourth display circuit 264, and the fifth display circuit 265, respectively. Similar to the display signal group 291, the branch signal group 292 is designed to enable the transmission of 8 bits of display data at once, and this 8-bit display data is transmitted from the display IC 266 via parallel communication.

As described above, the display signal group 291 and branch signal group 292 are provided. Therefore, when display data stored in the display data buffer 283 is transmitted by the display data output unit 284, that display data is supplied to all of the first to fifth display circuits 261 to 265. In this case, the first to fifth selection signal lines 301 to 305 are provided to specify which display circuits 261 to 265 should receive and utilize the supplied display data.

The first selection signal line 301 is provided to electrically connect the display IC 266 and the first display circuit 261. When the type data buffer 281 contains type data corresponding to the first display circuit 261, the selection signal output unit 282 of the display IC 266 transmits a first selection signal to the first display circuit 261 via the first selection signal line 301 in order to have the display data supplied from the display data output unit 284 received and used by the first display circuit 261. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 via the display signal group 291 and the branch signal group 292 is received and used only by the first display circuit 261.

The second selection signal line 302 is provided to electrically connect the display IC 266 and the second display circuit 262. When the type data corresponding to the second display circuit 262 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 transmits a second selection signal to the second display circuit 262 via the second selection signal line 302 in order to have the display data supplied from the display data output unit 284 received and used by the second display circuit 262. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 via the display signal group 291 and the branch signal group 292 is received and used only by the second display circuit 262.

The third selection signal line 303 is provided to electrically connect the display IC 266 and the third display circuit 263. When the type data buffer 281 contains type data corresponding to the third display circuit 263, the selection signal output unit 282 of the display IC 266 transmits a third selection signal to the third display circuit 263 via the third selection signal line 303 in order to have the display data supplied from the display data output unit 284 received and used by the third display circuit 263. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 via the display signal group 291 and the branch signal group 292 is received and used only by the third display circuit 263.

The fourth selection signal line 304 is provided to electrically connect the display IC 266 and the fourth display circuit 264. When type data corresponding to the fourth display circuit 264 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 transmits a fourth selection signal to the fourth display circuit 264 via the fourth selection signal line 304 in order to have the display data supplied from the display data output unit 284 received and used by the fourth display circuit 264. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 via the display signal group 291 and the branch signal group 292 is received and used only by the fourth display circuit 264.

The fifth selection signal line 305 is provided to electrically connect the display IC 266 and the fifth display circuit 265. When type data corresponding to the fifth display circuit 265 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 transmits a fifth selection signal to the fifth display circuit 265 via the fifth selection signal line 305 in order to have the display data supplied from the display data output unit 284 received and used by the fifth display circuit 265. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 via the display signal group 291 and the branch signal group 292 is received and used only by the fifth display circuit 265.

Figure 122 is a time chart showing how type data and display data are transmitted from the main CPU 63 to the display IC 266, and how the display data transmitted from the display IC 266 is received by the first display circuit 261 or the second display circuit 262. Figure 122(a) shows the transmission period of the type data signal from the main CPU 63 to the display IC 266; Figure 122(b) shows the transmission period of the type clock signal from the main CPU 63 to the display IC 266; Figure 122(c) shows the transmission period of the display data signal from the main CPU 63 to the display IC 266; Figure 122(d) shows the transmission period of the display clock signal from the main CPU 63 to the display IC 266; Figure 122(e) shows the transmission period of the first selection signal from the display IC 266 to the first display circuit 261; Figure 122(f) shows the transmission period of the second selection signal from the display IC 266 to the second display circuit 262; and Figure 122(g) shows the transmission period of display data from the display IC 266 to the first to fifth display circuits 261 to 265. The same applies when display data is received in the third to fifth display circuits 263 to 265.

At timing t1, after the supply of operating power to the pachinko machine 10, including the main CPU 63, display IC 266, and the first to fifth display circuits 261 to 265, begins, the transmission of type data and display data from the main CPU 63 to the display IC 266 begins. Specifically, as shown in Figure 122(b), pulse-shaped type clock signals are transmitted at timings t1, t2, t3, t4, and t5, and as shown in Figure 122(a), pulse-shaped type data signals are transmitted in conjunction with the transmission of the pulse-shaped type clock signal at timing t1. As a result, the type data buffer 281 of the display IC 266 stores information corresponding to the first display circuit 261.

Furthermore, as shown in Figure 122(d), pulsed display clock signals are transmitted at timings t1, t2, t3, t4, t5, t6, t7, and t8, and pulsed display data signals are transmitted in conjunction with the transmission of pulsed display clock signals at timings t2, t3, t5, and t7, as shown in Figure 122(c). As a result, the display data buffer 283 of the display IC 266 stores display data corresponding to the above information format.

Then, at timing t9, as shown in Figure 122(d), the transmission of the 8th bit display clock signal is completed. At the same timing t9, as shown in Figure 122(e), the selection signal output unit 282 of the display IC 266 begins transmitting the first selection signal to the first display circuit 261 corresponding to the type data stored in the type data buffer 281. At the same timing t9, as shown in Figure 122(g), the display data output unit 284 of the display IC 266 begins transmitting the display data stored in the display data buffer 283. As a result, the display data is received and used by the first display circuit 261.

Subsequently, at timing t10, as shown in Figures 122(a) to 122(d), the transmission of type data and display data from the main CPU 63 to the display IC 266 is newly initiated. In this case, at timing t10, as shown in Figures 122(e) and 122(g), the transmission of the first selection signal from the display IC 266 to the first display circuit 261 is stopped, and the transmission of display data from the display IC 266 to the first to fifth display circuits 261 to 265 is also stopped.

Regarding the new transmission of type data and display data, as shown in Figure 122(b), pulse-shaped type clock signals are transmitted at timings t10, t11, t12, t13, and t14, respectively. Additionally, as shown in Figure 122(a), a pulse-shaped type data signal is transmitted in conjunction with the transmission of the pulse-shaped type clock signal at timing t11. As a result, the type data buffer 281 of the display IC 266 stores information corresponding to the second display circuit 262.

Furthermore, as shown in Figure 122(d), pulsed display clock signals are transmitted at timings t10, t11, t12, t13, t14, t15, t16, and t17, respectively. Simultaneously, as shown in Figure 122(c), pulsed display data signals are transmitted in conjunction with the transmission of pulsed display clock signals at timings t10, t11, t12, t15, t16, and t17. As a result, the display data buffer 283 of the display IC 266 stores display data corresponding to the above information format.

Then, at timing t18, as shown in Figure 122(d), the transmission of the 8th bit display clock signal is completed. At the same timing t18, as shown in Figure 122(f), the selection signal output unit 282 of the display IC 266 begins transmitting the second selection signal to the second display circuit 262 corresponding to the type data stored in the type data buffer 281. Simultaneously, at the same timing t18, as shown in Figure 122(g), the display data output unit 284 of the display IC 266 begins transmitting the display data stored in the display data buffer 283. As a result, the display data is received and used by the second display circuit 262.

Furthermore, for the first to fourth display circuits 261 to 264, only one display data is transmitted in the second timer interrupt process (Figure 123) that transmits the display data. However, for the fifth display circuit 265, four display data are transmitted in the second timer interrupt process (Figure 123) that transmits the display data, corresponding to the number of first to fourth notification display devices 201 to 204. As already explained, the second timer interrupt process (Figure 123) is activated at the second interrupt cycle (specifically, 2 milliseconds). However, even for the processing cycle that transmits four display data, the processing time for each cycle is set so that one processing cycle is completed in less than the second interrupt cycle.

With the above configuration, it is possible to transmit display data to multiple display circuits 261 to 265 using a single display IC 266. As already explained, each of the first to fifth display circuits 261 to 265 is capable of storing the provided display data for a predetermined period (for example, 16 milliseconds), but after the predetermined period has elapsed, the display data will gradually approach a state of all "0". In this case, if the reception of display data in each of the display circuits 261 to 265 exceeds the predetermined period, even if the display content has not been changed in the special figure display unit 37a, special figure hold display unit 37b, general figure display unit 38a, general figure hold display unit 38b, and the first to fourth notification display devices 201 to 204, the display segments that are in a luminous state will temporarily approach a state of being off, and as a result there is a risk that the light on the display segments will flicker. In contrast, in this embodiment, a second timer interrupt process (Figure 123) is set up that is activated at a shorter second interrupt period (specifically, 2 milliseconds) than the first interrupt period (Figure 117), in addition to the first timer interrupt process (Figure 117) which is activated at a first interrupt period (specifically, 4 milliseconds). The transmission of display data to the display IC 266 is consolidated and performed in this second timer interrupt process.

The second timer interrupt processing will be explained below with reference to the flowchart in Figure 123. Note that steps S8401 to S8413 in the second timer interrupt processing are executed using the specific control program and specific control data in the main CPU 63.

First, interrupt disabling is performed (step S8401) to prevent the occurrence of the first timer interrupt process (Figure 117) and the second timer interrupt process (Figure 123). By disabling the occurrence of the first timer interrupt process (Figure 117), it becomes possible to prevent the first timer interrupt process (Figure 117) from interrupting and activating the second timer interrupt process (Figure 123) even after the first interrupt cycle has elapsed. Furthermore, by disabling the occurrence of the second timer interrupt process (Figure 123), it becomes possible to prevent the second timer interrupt process (Figure 123) from being activated redundantly, even if the second interrupt cycle has elapsed during the execution of the second timer interrupt process (Figure 123).

Subsequently, it is determined whether the setting update display flag in the work area 221 for specific control is set to "1" (step S8402). The setting update display flag is used by the main CPU 63 to determine whether or not the main CPU 63 is executing the setting value update process (Figure 116). As already explained, the setting value update process (Figure 116) is executed when the main process (Figure 114) for the start of power supply to the main CPU 63 is running. However, the second timer interrupt process (Figure 123) is started by interrupting even when the power supply start process is running. Therefore, even if the main CPU 63 is executing the setting value update process (Figure 116), the second timer interrupt process (Figure 123) will also be started by interrupting.

The setting update display flag being set to "1" means that the current processing run of the second timer interrupt process (Figure 123) was triggered by an interrupt while the main CPU 63 was executing the setting value update process (Figure 116). If a positive determination is made in step S8402, the setting process for the fifth display data buffer 275 during the setting update is executed (step S8403). In this setting process, display data for indicating that the setting values of the pachinko machine 10 are being updated and for displaying the current setting values of the pachinko machine 10 is stored in the fifth display data buffer 275.

When the display data stored in the fifth display data buffer 275 is transmitted to the fifth display circuit 265 via the display IC 266, the first to fourth notification display devices 201 to 204 display the information shown in the explanatory diagram in Figure 124(a). Specifically, when the first to fourth notification display devices 201 to 204 display an information indicating that the set value is being updated, at least one display segment in each of the first to fourth notification display devices 201 to 204 illuminates. In other words, each of the first to fourth notification display devices 201 to 204 displays an information. This allows the manager of the amusement hall to know that the first to fourth notification display devices 201 to 204 are not malfunctioning, even when an information indicating that the set value is being updated is being displayed. Even when the game history management results are displayed, at least one display segment in each of the first to fourth notification display devices 201 to 204 will be illuminated, and each of the first to fourth notification display devices 201 to 204 will be in a display state.

Regarding the detailed display content of the first to fourth notification display devices 201 to 204, in the first notification display device 201, the central display segment illuminates while the remaining display segments are off. Even when the game history management results are displayed in the first to fourth notification display devices 201 to 204, the central display segment of the first notification display device 201 may illuminate. However, the display content of the first notification display device 201 when the game history management results are displayed does not include a display where the central display segment illuminates while the remaining display segments are off. This makes it possible to use display segments that can illuminate even when the game history management results are displayed, while simultaneously ensuring that the display content of the first notification display device 201 during setting value updates is not displayed in the game history management results.

In the second notification display device 202, similar to the first notification display device 201, the central display segment illuminates while the remaining display segments are turned off. Even when the game history management results are displayed in the first to fourth notification display devices 201 to 204, the central display segment of the second notification display device 202 may illuminate. However, the display content of the second notification display device 202 when the game history management results are displayed does not include a display where the central display segment illuminates while the remaining display segments are turned off. This makes it possible to utilize display segments that can illuminate even when the game history management results are displayed, while simultaneously ensuring that the display content of the second notification display device 202 during setting value updates is not displayed in the game history management results.

In the third notification display device 203, some display segments illuminate to display the letter "H," while the remaining display segments remain off. In this case, the illuminated display segments may remain illuminated even when the game history management results are displayed in the first to fourth notification display devices 201 to 204. However, the display content of the third notification display device 203 when the game history management results are displayed does not include the display of the letter "H." This allows for the use of display segments that can illuminate even when the game history management results are displayed, while ensuring that the display content of the third notification display device 203 during setting value updates is not displayed in the game history management results. Furthermore, the display content of the third notification display device 203 when the setting values are being checked also does not include the display of the letter "H." Therefore, by displaying "H" on the third notification display device 203, it is possible to notify the gaming hall administrator that the setting values are being updated.

In the fourth notification display device 204, some display segments illuminate while the remaining display segments remain off to display the current setting value. In the case of Figure 124(a), the current setting value is "Setting 2," so the fourth notification display device 204 displays "2," corresponding to "Setting 2." By checking the fourth notification display device 204, the manager of the gaming hall can understand the current setting value. Note that the display content of the fourth notification display device 204 during setting value updates can be displayed in both situations where the game history management results are displayed and situations where the setting value is being checked.

Returning to the explanation of the second timer interrupt process (Figure 123), if a negative determination is made in step S8402, it is determined whether the setting confirmation display flag in the specific control work area 221 is set to "1" (step S8404). The setting confirmation display flag is a flag used by the main CPU 63 to determine whether or not the setting confirmation process (Figure 115) is being executed by the main CPU 63. As already explained, the setting confirmation process (Figure 115) is executed when the main process (Figure 114) is running when the supply of operating power to the main CPU 63 begins, while the process for starting the supply of operating power is being executed. However, the second timer interrupt process (Figure 123) is started by interrupting even when the process for starting the supply of operating power is being executed. Therefore, even if the setting confirmation process (Figure 115) is being executed by the main CPU 63, the second timer interrupt process (Figure 123) will also be started by interrupting.

The setting confirmation display flag being set to "1" means that the current processing run of the second timer interrupt process (Figure 123) was triggered by an interrupt while the main CPU 63 was executing the setting confirmation process (Figure 115). If a positive determination is made in step S8404, the setting process for the fifth display data buffer 275 during setting confirmation is executed (step S8405). In this setting process, display data for indicating that the setting values of the pachinko machine 10 are being confirmed and for displaying the current setting values of the pachinko machine 10 is stored in the fifth display data buffer 275.

When the display data stored in the fifth display data buffer 275 is transmitted to the fifth display circuit 265 via the display IC 266, the first to fourth notification display devices 201 to 204 will display the information shown in the explanatory diagram in Figure 124(b). Specifically, when the first to fourth notification display devices 201 to 204 display an indication that the set value is being updated, at least one display segment in each of the first to fourth notification display devices 201 to 204 will illuminate. In other words, each of the first to fourth notification display devices 201 to 204 will display an information. This allows the manager of the amusement hall to understand that the first to fourth notification display devices 201 to 204 are not malfunctioning, even when an indication that the set value is being checked is being displayed.

Regarding the display content of the first to fourth notification display devices 201 to 204, in detail, the first notification display device 201 illuminates the central display segment while the remaining display segments are off. Even when the game history management results are displayed on the first to fourth notification display devices 201 to 204, the central display segment of the first notification display device 201 may illuminate. However, the display content of the first notification display device 201 when the game history management results are displayed does not include a display where the central display segment illuminates and the remaining display segments are off. This makes it possible to use a display segment that can illuminate even when the game history management results are displayed, while simultaneously ensuring that the display content of the first notification display device 201 when checking the setting values is not displayed in the game history management results.

In the second notification display device 202, similar to the first notification display device 201, the central display segment illuminates while the remaining display segments are turned off. Even when the game history management results are displayed in the first to fourth notification display devices 201 to 204, the central display segment of the second notification display device 202 may illuminate. However, the display content of the second notification display device 202 when the game history management results are displayed does not include a display where the central display segment illuminates while the remaining display segments are turned off. This makes it possible to utilize display segments that can illuminate even when the game history management results are displayed, while simultaneously ensuring that the display content of the second notification display device 202 when checking setting values is not displayed in the game history management results.

Here, the display content on the first notification display device 201 and the second notification display device 202 is the same regardless of whether the setting value is being updated or confirmed. This makes it possible to clearly inform the administrator of the gaming hall, through the displays on the first notification display device 201 and the second notification display device 202, that the display target on the first to fourth notification display devices 201 to 204 is related to the setting value and not the results of game history management.

In the third notification display device 203, some display segments illuminate to display the letter "k", while the remaining display segments remain unlit. In this case, the illuminated display segments may also illuminate when the game history management results are displayed in the first to fourth notification display devices 201 to 204. However, the display content of the third notification display device 203 when the game history management results are displayed does not include the display content that displays the letter "k". This makes it possible to use display segments that can illuminate even when the game history management results are displayed, while ensuring that the display content of the third notification display device 203 when checking the setting value is not displayed in the game history management results. Furthermore, "H" is displayed on the third notification display device 203 when the setting value is being updated, while "k" is displayed on the third notification display device 203 when checking the setting value. This allows the administrator of the gaming hall to be notified whether the setting value is being updated or checked by checking the display content of the third notification display device 203.

In the fourth notification display device 204, some display segments illuminate while the remaining display segments remain off, so that the current setting value is displayed. In the case of Figure 124(b), the current setting value is "Setting 2," so the fourth notification display device 204 displays "2," corresponding to "Setting 2." By checking the fourth notification display device 204, the manager of the gaming hall can understand the current setting value. The display content of the fourth notification display device 204 when checking the setting value can be displayed in both situations: when the gaming history management results are being displayed, and when the setting value is being updated.

Returning to the explanation of the second timer interrupt processing (Figure 123), if a negative determination is made in step S8404, the setting process for the fifth display data buffer 275 under normal conditions is executed (step S8406). In this case, information is read from the display target setting area 276 in the work area 223 for non-specific control, and display data for displaying the parameters corresponding to the read information is stored in the fifth display data buffer 275. This display data is transmitted to the fifth display circuit 265 via the display IC 266, causing the calculation results of the currently displayed parameters from the 61st to 68th parameters to be displayed on the first to fourth display devices 201 to 204.

If the processing in step S8403, step S8405, or step S8406 is executed, the transmission state of the signals through the type data signal line LN1 and the type clock signal line LN2 is turned OFF (step S8407), and the transmission state of the signals through the display data signal line LN3 and the display clock signal line LN4 is turned OFF (step S8408). Then, the update process for the type counter provided in the work area 221 for specific control is executed (step S8409).

The type counter is used by the main CPU 63 to identify which of the first to fifth display data buffers 271 to 275 will be used to transmit display data during the current execution cycle of the second timer interrupt process. When the type counter value is "1", the display data from the first display data buffer 271 is used; when the type counter value is "2", the display data from the second display data buffer 272 is used; when the type counter value is "3", the display data from the third display data buffer 273 is used; when the type counter value is "4", the display data from the fourth display data buffer 274 is used; and when the type counter value is "5", the display data from the fifth display data buffer 275 is used. The type counter update process increments the type counter value by 1, and if the value after the increment exceeds the upper limit of "5", the type counter value is set to "1". This sequentially changes the target of display data transmission in the first to fifth display data buffers 271 to 275 for each execution cycle of the second timer interrupt process.

Subsequently, the type data corresponding to the value of the type counter is read from the main ROM 64 (step S8410). Specifically, if the value of the type counter is "1", the type data corresponding to the first display circuit 261 is read from the main ROM 64; if the value of the type counter is "2", the type data corresponding to the second display circuit 262 is read from the main ROM 64; if the value of the type counter is "3", the type data corresponding to the third display circuit 263 is read from the main ROM 64; if the value of the type counter is "4", the type data corresponding to the fourth display circuit 264 is read from the main ROM 64; and if the value of the type counter is "5", the type data corresponding to the fifth display circuit 265 is read from the main ROM 64.

Subsequently, display data is read from display data buffers 271 to 275 corresponding to the value of the type counter (step S8411). Specifically, if the value of the type counter is "1", display data is read from the first display data buffer 271; if the value of the type counter is "2", display data is read from the second display data buffer 272; if the value of the type counter is "3", display data is read from the third display data buffer 273; if the value of the type counter is "4", display data is read from the fourth display data buffer 274; and if the value of the type counter is "5", display data is read from the fifth display data buffer 275.

Subsequently, the transmission process for various signals is executed (step S8412). During this transmission process, signal outputs are made to the type data signal line LN1 and the type clock signal line LN2 so that the type data read in step S8410 is transmitted to the display IC 266. Furthermore, during this transmission process, signal outputs are made to the display data signal line LN3 and the display clock signal line LN4 so that the display data read in step S8411 is transmitted to the display IC 266.

Subsequently, interrupt enablement is set to allow the first timer interrupt process (Figure 117) and the second timer interrupt process (Figure 123) to occur (step S8413).

The embodiment described in detail above provides the following excellent effects.

When the power to the pachinko machine 10 is turned ON with the setting key insertion section 68a activated by the setting key without pressing the reset button 68c, power is supplied to the main CPU 63 and the main processing (Figure 114) begins. In this state, the reset button 68c is not pressed and the setting key insertion section 68a is ON. Therefore, the setting confirmation process is executed while the power supply commencement process (before the main processing that enables gameplay) is running. This makes it difficult to attempt to fraudulently verify the setting values.

If we consider a scenario where the setting value is checked while the game is in progress, for example, if the setting value is checked in the middle of a game round, there is a risk that the system may transition to the opening/closing execution mode while the setting value check is still in progress. In this case, even though the opening/closing execution mode has started, it may not be possible to launch the game ball towards the special electric prize winning device 32. Furthermore, if the setting value is checked while the opening/closing execution mode is in progress, the opening/closing execution mode will proceed while the setting value check is in progress, and in this case as well, there is a risk that the game ball may not be able to launch towards the special electric prize winning device 32.

If we assume that the game will be stopped when the setting values are checked, then if the setting value check is started while the game is in progress, the process of stopping the game midway may become complicated. For example, if the setting value check is started in the middle of a game round and the game is to be stopped midway, processing will be required to stop the game round midway. In this case, if the display of the changing symbols on the symbol display device 41 is to be stopped midway when the setting value check is started, and the display of the changing symbols on the symbol display device 41 is to be resumed when the setting value check is finished, it will require a correspondingly complex process. Also, for example, if the setting value check is started in the middle of the execution of the opening/closing execution mode and the game is to be stopped midway, processing will be required to stop the opening/closing execution mode midway. Furthermore, if the setting value check is started in the middle of the display of the changing symbols on the general display unit 38a and the game is to be stopped midway, processing will be required to stop the display of the changing symbols midway. Furthermore, if the setting value is checked while the opening state of the regular electric device 34a is in progress, and the game is to be stopped midway, processing is required to stop the opening state midway. On the other hand, a configuration where the setting value is checked only after all games have finished is also conceivable. However, in this case, it becomes necessary to wait until none of the following are occurring: the number of game rounds, the opening/closing execution mode, the display of changing symbols on the regular diagram display unit 38a, or the opening state of the regular electric device 34a. This could lead to a longer waiting time before the setting value check can begin.

In contrast, the setting confirmation process is executed during the power supply start process, which is performed before the process that enables gameplay is executed in the main process that runs when power supply to the main CPU 63 is started. Therefore, the setting value is confirmed while gameplay has already stopped. This prevents the setting value from being confirmed while gameplay is in progress, and eliminates the need to stop gameplay midway or wait for gameplay to stop before confirming the setting value. Thus, the setting value can be confirmed appropriately.

When the reset button 68c is pressed while the power of the pachinko machine 10 is turned ON, the supply of operating power to the main CPU 63 begins, and the main processing (Figure 114) starts. In this state, the reset button 68c is pressed, and regardless of whether the setting key insertion unit 68a is turned ON or not, the RAM clear process (step S7915) is executed. This ensures that the operation of pressing the reset button 68c while turning on the power of the pachinko machine 10 is uniquely linked to the execution of the RAM clear process (step S7915), making the operation required to trigger the RAM clear process (step S7915) easily understandable to the administrator of the gaming hall.

Even if the RAM clear process (step S7915) is executed, the setting value counter in the work area 221 for specific control is not cleared to "0," and the information in the setting value counter is not changed. This makes it possible to prevent the setting value from being changed even when the RAM clear process (step S7915) is executed.

When the reset button 68c is pressed while the power of the pachinko machine 10 is turned ON, and the setting key insertion unit 68a is also turned ON using the setting key while the power of the pachinko machine 10 is turned ON, not only is the RAM clear process (step S7915) executed, but the setting value update process (step S7918) is also executed. Furthermore, as already explained, when the setting key insertion unit 68a is turned ON using the setting key while the power of the pachinko machine 10 is turned ON without pressing the reset button 68c, the setting confirmation process (step S7914) is executed. This makes it possible to standardize the ON operation of the setting key insertion unit 68a as the operation required to execute the setting value-related processing. Therefore, the operation required to trigger the setting value-related processing can be made easily understandable to the administrator of the gaming hall.

When the setting key insertion section 68a is turned ON using the setting key while the power of the pachinko machine 10 is turned ON, if the reset button 68c is not pressed, a setting confirmation process is executed. If the reset button 68c is pressed, a setting value update process is executed. This makes it possible to differentiate between the setting confirmation process and the setting value update process depending on whether the reset button 68c is pressed. Therefore, the operation content required to execute the desired process among the setting confirmation process and the setting value update process can be made easy for the administrator of the gaming hall to understand. Furthermore, by making the operation content required to execute the setting value update process more extensive than that required for the setting confirmation process, it becomes particularly difficult to perform fraudulent acts such as performing the setting value update process.

The monitoring process to check whether the set value is abnormal is performed by the first timer interrupt process (Figure 117), which is triggered periodically. This makes it possible to monitor whether the set value is abnormal even while gameplay is in progress. Therefore, it is possible to prevent gameplay from continuing even if the set value is abnormal.

Monitoring for whether the setting value is abnormal is performed each time a monitoring trigger occurs. More specifically, it is performed each time the first timer interrupt process (Figure 117) is activated. This makes it possible to increase the frequency of monitoring whether the setting value is abnormal.

The main process (Figure 114) does not include any processing to monitor whether the set value is normal or not. If the main process (Figure 114) included processing to monitor whether the set value is normal or not during the power supply initiation process, it would become necessary to monitor not only the power outage flag and checksum but also whether the set value is normal or not, increasing the monitoring load. Furthermore, if the system were to execute a RAM clear process (step S7915) and a set value update process (step S7918) when an abnormal set value is identified during the power supply initiation process, the processing configuration would become more complex. In contrast, because the main process (Figure 114) does not include processing to monitor whether the set value is normal or not, it is possible to optimize the processing configuration for the power supply initiation process. Moreover, even though there is no processing to monitor whether the set value is normal or not during the power supply initiation process, the first timer interrupt process (Figure 117) executes a setting monitoring process (step S8220), allowing for action to be taken if the set value is abnormal.

According to the display data transmitted from the main CPU 63, the display IC 266 sets the display for the first to fifth display circuits 261 to 265, and the special drawing display unit 37a, special drawing hold display unit 37b, general drawing display unit 38a, general drawing hold display unit 38b, and the first to fourth notification display devices 201 to 204 are controlled to display content corresponding to the display data. This makes it possible to reduce the processing load on the main CPU 63. In this case, in a configuration where multiple display units are provided, such as the special drawing display unit 37a, special drawing hold display unit 37b, general drawing display unit 38a, general drawing hold display unit 38b, and the first to fourth notification display devices 201 to 204, the display IC 266 is not provided in a one-to-one correspondence with these multiple display units, but rather one display IC 266 is used for multiple display units. This makes it possible to increase the number of display units subject to display control while keeping the number of display ICs 266 to a minimum. Furthermore, the transmission interval for display data from the main CPU 63 to the display IC 266 is set so that the display settings are performed by the display IC 266 to the display circuits 261-265 corresponding to each display unit before each display unit becomes unable to maintain the display corresponding to the display data. This ensures that even in a configuration where one display IC 266 is used for multiple display units, each display unit can properly display the data corresponding to the display.

When the main CPU 63 transmits display data to the display IC 266, it transmits type data to the display IC 266 that identifies the type of display circuit 261-265 to which the display data is to be set. Therefore, when the display IC 266 receives display data from the main CPU 63, it only needs to set the display data for the display circuits 261-265 corresponding to the type data transmitted from the main CPU 63. Thus, even in a configuration where one display IC 266 is used for multiple display units, the configuration of the display IC 266 can be simplified.

The main CPU 63 transmits display data so that the update cycle is repeated, assuming that each of the multiple display units is targeted for display data setting once in a predetermined order. This simplifies the processing configuration of the main CPU 63, as it only needs to change the display unit to which the display data is transmitted according to the predetermined order.

The main CPU 63 transmits the display data for a single display unit even if the content of the display data is the same as the content of the display data transmitted to that display unit in the previous transmission. This makes it possible to continuously display the same information on a given display unit, even in a configuration where a single display IC 266 is used for multiple display units.

The main CPU 63, upon reaching the second interrupt cycle, interrupts other processes to execute a second timer interrupt process (Figure 123) to send display data to the display IC 266. This makes it possible to set a predetermined cycle for setting display data to each display unit. Therefore, even in a configuration where one display IC 266 is used for multiple display units, it becomes possible to ensure that the display data is set by the display IC 266 for each display unit before it becomes impossible to maintain the corresponding display in each unit.

The process for transmitting display data to the first to fifth display circuits 261 to 265, which are the targets of display settings via the display IC 266, is consolidated into the second timer interrupt process (Figure 123). This makes it possible to set the period for setting display data to the first to fifth display circuits 261 to 265 to the same period.

The main CPU 63 interrupts other processes and executes the first timer interrupt process (Figure 117) when the first interrupt cycle occurs. In this case, the second interrupt cycle of the second timer interrupt process (Figure 123) is set to a shorter period than the first interrupt cycle of the first timer interrupt process (Figure 117). This makes it possible to transmit display data at a shorter cycle compared to a configuration where the process of transmitting display data to the display IC 266 is executed in the first timer interrupt process (Figure 117).

Furthermore, the second timer interrupt process (Figure 123), which has a shorter interrupt cycle than the first timer interrupt process (Figure 117) which is set to process the progression of the game, is configured to transmit display data to the display IC 266. This allows the first timer interrupt process (Figure 117) to be activated at an appropriate cycle for executing the process to progress the game, while simultaneously achieving the excellent effects already described.

The second timer interrupt handler (Figure 123) is triggered even when the first timer interrupt handler (Figure 117) is running. This makes it possible to set the transmission cycle of the display data to a predetermined period.

When the second timer interrupt handler (Figure 123) starts, the interrupt for the first timer interrupt handler (Figure 117) is prohibited, and when the second timer interrupt handler (Figure 123) finishes, the interrupt for the first timer interrupt handler (Figure 117) is permitted. This prevents the first timer interrupt handler (Figure 117) from interrupting and executing while the second timer interrupt handler (Figure 123) is running. Therefore, it becomes possible to prioritize the processing for transmitting display data.

The second timer interrupt handler (Figure 123) is activated even when the power supply start-up process (steps S7901 to S7918) is being executed in the main process (Figure 114). This makes it possible to control the display of multiple displays even when the power supply start-up process is being executed. Furthermore, because the second timer interrupt handler (Figure 123) is activated by interrupting the power supply start-up process, it is possible to control the display of multiple displays even when the power supply start-up process is being executed without complicating the processing configuration of the power supply start-up process.

Even when the setting value update process (step S7918) is being executed in the main process (Figure 114), the second timer interrupt process (Figure 123) is interrupted and activated. In this situation, the second timer interrupt process (Figure 123) transmits display data to display the current setting value on the fourth notification display device 204. This makes it possible to display the current setting value on the fourth notification display device 204 even when the setting value update process (step S7918) is being executed, without complicating the processing configuration of the main process (Figure 114).

Even after the main process (Figure 114) has executed the process for starting the supply of operating power, the second timer interrupt process (Figure 123) is triggered each time the second interrupt cycle elapses. This allows for the control of multiple display units, both during and after the process for starting the supply of operating power has been completed, by utilizing the second timer interrupt process (Figure 123).

Furthermore, similar to the first embodiment described above, an update button 68b may be provided, and in the setting value update process (Figure 116), the setting value may be updated one step each time the update button 68b is pressed, rather than each time the reset button 68c is pressed. Also, when a setting key is inserted into the setting key insertion section 68a and rotated, positions corresponding to "Setting 1" to "Setting 6" may be set, and the setting value corresponding to the rotation position of the setting key insertion section 68a may be set. Additionally, the setting key insertion section 68a may be configured to be rotated beyond the ON position, and each time a rotation beyond the ON position is performed, the setting value in the middle of the update process may be updated to the setting value in the next sequence.

Furthermore, in the setting value update process (Figure 116), the selected setting value is confirmed by turning OFF the setting key insertion part 68a, and the setting value update process may be terminated when the reset button 68c is pressed. Also, in a configuration where an update button 68b is provided, in the setting value update process (Figure 116), the selected setting value is confirmed by turning OFF the setting key insertion part 68a, and the setting value update process may be terminated when the update button 68b is pressed.

Furthermore, the configuration may not include the condition that the gaming machine body 12 is in an open state, nor the condition that the front door frame 14 is in an open state, nor the configuration may not include the condition that both the gaming machine body 12 and the front door frame 14 are in an open state.

Furthermore, the configuration may not include the condition that the gaming machine body 12 is in an open state as a condition for executing the setting confirmation process (Figure 115), nor may it include the condition that the front door frame 14 is in an open state, nor may it include the configuration that neither the gaming machine body 12 nor the front door frame 14 is in an open state.

Furthermore, if the main process (Figure 114), which is executed when power is supplied to the main CPU 63, determines that the power outage flag is not set to "1" or that the checksum is abnormal, a RAM clear process (step S7915) may be executed. In this case, after the RAM clear process (step S7915) is executed, a setting value update process (step S7918) may be executed, or a notification indicating that the setting value update process (step S7918) should be executed may be issued and the game may be stopped, or a process to control the game may be initiated.

Furthermore, in the main process (Figure 114), the configuration in which the setting confirmation process (step S7914) is executed before the process determining whether the power outage flag is set to "1" and the checksum comparison process may be changed. In this case, it becomes possible to prioritize the process for confirming the setting value.

Furthermore, the configuration in which the setting monitoring process (step S8220) is executed is not limited to each time the first timer interrupt process (Figure 117) is activated. For example, the configuration may be such that the setting monitoring process (step S8220) is executed each time the first timer interrupt process (Figure 117) is executed a predetermined number of times (e.g., 10,000 times). In this case, it becomes possible to periodically monitor whether the setting value is normal while reducing the frequency of such monitoring.

Alternatively, the setting monitoring process (step S8220) may be executed during the remaining processing (steps S7921 to S7924) of the main process (Figure 114). In this case, it becomes possible to monitor whether the setting value is correct by utilizing the idle time when the first timer interrupt process (Figure 117) and the second timer interrupt process (Figure 123) are not being executed.

Furthermore, the system may be configured to execute the setting monitoring process (step S8220) when a new game round is started. More specifically, the system may be configured to execute the setting monitoring process (step S8220) before the win/failure determination process is executed when a new game round is started. This prevents the win/failure determination process from being executed when the setting value is abnormal.

Furthermore, if the setting monitoring process (step S8220) identifies an abnormal setting value, the system may proceed to the setting value update process (step S7918).

Furthermore, if the setting monitoring process (step S8220) identifies an abnormal setting, the main process (Figure 114) may be started with the setting abnormality flag in the specific control work area 221 set to "1". The game may also be stopped with the setting abnormality flag set to "1", and the power may be turned OFF → ON to release the stopped state. In this case, even if no operation is performed in the main process (Figure 114) to initiate the setting value update process, if the setting abnormality flag is set to "1", the setting value update process is forcibly executed, making it possible to forcibly set a new setting value using the setting value update process set in the main process (Figure 114).

Furthermore, the system may be configured such that the reserved information acquired when a game ball enters the first operation port 33 and the reserved information acquired when a game ball enters the second operation port 34 are stored separately, and the special symbol display unit 37a is provided with a first special symbol display unit and a second special symbol display unit corresponding to this reserved information. In this case, the display of changing symbols in the first special symbol display unit and the display of changing symbols in the second special symbol display unit may be executed simultaneously, and when a predetermined game state is reached, the duration of the display of changing symbols in either special symbol display unit may be made extremely long. In this configuration, if the system tries to wait to confirm the setting value until the game is not being played, the waiting time becomes long. To address this, by having the setting confirmation process (step S7914) executed when the power supply to the main CPU 63 starts, it becomes possible to confirm the setting value without causing the above-mentioned waiting time.

Furthermore, in the low-frequency support mode, the duration of the pattern variation display in the general diagram display unit 38a may be configured to be extremely long. In this configuration, if the system waits to confirm the setting value until no game is being played, the waiting time becomes long. To address this, by executing a setting confirmation process (step S7914) during the power supply start process in the main CPU 63, it becomes possible to confirm the setting value without causing the aforementioned waiting time.

Furthermore, when the setting confirmation process (Figure 115) is executed, the display content of the first to fourth notification display devices 201 to 204 is not limited to the display content in the above embodiment. For example, instead of displaying the letter "k" in the third notification display device 203, it may be configured so that only the central display segment is illuminated, similar to the first notification display device 201 and the second notification display device 202. Alternatively, the first to third notification display devices 201 to 203 may be turned off, and the fourth notification display device 204 may display the current setting value.

Furthermore, when the setting value update process (Figure 116) is executed, the display content of the first to fourth notification display devices 201 to 204 is not limited to the display content in the above embodiment. For example, instead of displaying the letter "H" in the third notification display device 203, it may be configured so that only the central display segment is illuminated, similar to the first notification display device 201 and the second notification display device 202. Alternatively, the first to third notification display devices 201 to 203 may be turned off, and the fourth notification display device 204 may display the information corresponding to the current setting value.

Furthermore, instead of the main CPU 63 simultaneously transmitting type data and display data to the display IC 266, it may be configured to start transmitting display data after starting the transmission of type data. In this case, the transmission of display data may start during the transmission of type data, or after the transmission of type data is completed. Alternatively, the transmission of type data may start after the transmission of display data. In this case, the transmission of type data may start during the transmission of display data, or after the transmission of display data is completed.

Furthermore, the configuration in which the display IC 266 is provided as a single IC common to the first to fifth display circuits 261 to 265 is not limited to this configuration; it may also be configured so that each of the first to fifth display circuits 261 to 265 has a one-to-one correspondence with a display IC. In this configuration, if the period for storing and holding display data in each display IC provided in a one-to-one correspondence with the first to fifth display circuits 261 to 265 is short, there is a risk that unintended blinking may occur in each display unit depending on the frequency of providing display data to each display IC. In contrast, by consolidating the processing for transmitting display data into a second timer interrupt process (Figure 123), which has a relatively short interrupt period, similar to the above embodiment, it becomes possible to shorten the frequency of providing display data to each display IC, thereby preventing unintended blinking in each display unit.

Alternatively, instead of having the winning random number counter C1 located in the main RAM 65, a configuration may be provided in which a random number circuit is used to update the random numbers obtained in the win/failure determination process. In this case, the internal function register setting process in the main process (Figure 114) will be configured to associate the random numbers from the random number circuit with the random numbers obtained in the win/failure determination process.

Furthermore, while the first timer interrupt processing (Figure 117) is configured to disable and enable timer interrupt processing before and after each process from step S8201 to step S8221, this configuration may be changed. For example, some processes in the first timer interrupt processing (Figure 117) may be configured to disable and enable timer interrupt processing before and after them, while other processes in the first timer interrupt processing (Figure 117) may not be configured to disable and enable timer interrupt processing before and after them. Alternatively, the configuration may be such that timer interrupt processing is disabled and enabled between multiple processes included in the first timer interrupt processing (Figure 117).

Furthermore, the first timer interrupt handler (Figure 117) may not be configured to disable the interrupt of the second timer interrupt handler (Figure 123). In this case, the second timer interrupt handler (Figure 123) will be executed with priority over the first timer interrupt handler (Figure 117), making it possible to prioritize the display control of multiple display units. Also, in this configuration, the first timer interrupt handler (Figure 117) may be configured to disable the interrupt of the first timer interrupt handler (Figure 117) to prevent duplicate activation, while the interrupt of the second timer interrupt handler (Figure 123) may not be disabled.

Furthermore, if both the first timer interrupt process (Figure 117) and the second timer interrupt process (Figure 123) triggers occur, instead of a configuration where the execution of the second timer interrupt process (Figure 123) takes precedence over the execution of the first timer interrupt process (Figure 117), the execution of the first timer interrupt process (Figure 117) may take precedence over the execution of the second timer interrupt process (Figure 123). Alternatively, the timer interrupt process that triggered earlier may be initiated first.

Furthermore, instead of a configuration where the execution of the first timer interrupt process (Figure 117) is prohibited when the second timer interrupt process (Figure 123) is being executed, a configuration may be adopted where the first timer interrupt process (Figure 117) is interrupted and activated even when the second timer interrupt process (Figure 123) is being executed. This makes it possible to prioritize the execution of processes necessary to advance the game over the display control of multiple display units.

Furthermore, the second timer interrupt processing (Figure 123) may not be set, and the various processes of the second timer interrupt processing (Figure 123) may be distributed and executed in both the main processing (Figure 114) and the first timer interrupt processing (Figure 117). For example, the setting confirmation processing (step S7914) in the main processing (Figure 114) may be configured to include processing to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting is being confirmed and a display corresponding to the current setting value. Alternatively, the setting value update processing (step S7918) in the main processing (Figure 114) may be configured to include processing to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting is being updated and a display corresponding to the current setting value. Furthermore, the first timer interrupt processing (Figure 117) may be configured to include processing for displaying and controlling the special figure display unit 37a, the special figure hold display unit 37b, the general figure display unit 38a, the general figure hold display unit 38b, and the first to fourth notification display devices 201 to 204.

Furthermore, the second timer interrupt process (Figure 123) is not limited to a configuration in which only processing for controlling the display of multiple display units is executed. In addition to, or instead of, processing different from that for controlling the display of multiple display units may be executed. For example, a part of the processing for advancing the game may be executed in the first timer interrupt process (Figure 117), and the remainder may be executed in the second timer interrupt process (Figure 123). In this case, it is preferable to execute processing that is preferable to have a relatively short execution cycle in the second timer interrupt process (Figure 123), which has a relatively short interrupt cycle, and to execute processing that does not cause problems even if the execution cycle is relatively long in the first timer interrupt process (Figure 117), which has a relatively long interrupt cycle. Furthermore, in the first timer interrupt processing (Figure 117) of the above embodiment, the power outage information storage processing (step S8202) may be executed in the second timer interrupt processing (Figure 123), while the other processing may be executed in the first timer interrupt processing (Figure 117). In this case, power outage monitoring can be repeatedly performed at a relatively short cycle. Alternatively, in addition to or instead of this configuration, the fraud detection processing (step S8206) may be executed in the second timer interrupt processing (Figure 123), while the other processing may be executed in the first timer interrupt processing (Figure 117). In this case, fraud monitoring can be repeatedly performed at a relatively short cycle.

Furthermore, the number of display circuits 261-265, for which the display data display settings are performed by the display IC 266, is not limited to five; it may be two, three, four, or six or more. Also, the configuration is not limited to one where the first to fourth notification display devices 201-204 are associated with the fifth display circuit 265; a configuration in which the display circuits are provided with a one-to-one correspondence between the first to fourth notification display devices 201-204 is also possible.

<Embodiment 34>
In this embodiment, the processing configuration of the setting value update process executed by the main CPU 63 differs from that of the 33rd embodiment. The configurations that differ from those of the 33rd embodiment will be described below. Configurations that are the same as those of the 33rd embodiment will generally not be described. In addition, in this embodiment, the main control board 61 is provided with an update button 68b, similar to that of the first embodiment.

Figure 125 is a flowchart showing the setting value update process in this embodiment, which is executed by the main CPU 63. Note that steps S8501 to S8508 in the setting value update process are executed using the specific control program and specific control data in the main CPU 63.

First, the setting update display flag in the work area 221 for specific control is set to "1" (step S8501). Then, it is determined whether the value of the setting value counter in the work area 221 for specific control is 1 or greater (corresponding to "Setting 1") and 6 or less (corresponding to "Setting 6") (step S8502). If the value of the setting value counter is "0" or 7 or greater, a negative determination is made in step S8502, and the setting value counter is set to "1" (step S8503). As a result, the setting value of the pachinko machine 10 becomes "Setting 1".

If a positive determination is made in step S8502 or the process in step S8503 is executed, it is determined whether the reset button 68c has been pressed (step S8504). If the reset button 68c has not been pressed (step S8504: NO), and provided that the update button 68b has been pressed (step S8505: YES), the value of the set value counter in the work area 221 for specific control is incremented by 1 (step S8506). As a result, each time the update button 68b is pressed, the set value is updated to one level higher. If the update button 68b has not been pressed (step S8505: NO) or the value of the set value counter has been incremented by 1, the process returns to step S8502. However, if it is determined in step S8502 that the value of the set value counter is 7 or greater, the set value counter is set to "1" in step S8503. As a result, if the update button 68b is pressed once while in "Setting 6" mode, the setting will revert to "Setting 1".

If the reset button 68c is pressed (step S8504: YES), the current setting value is confirmed and the process proceeds to step S8507. In step S8507, it is determined whether the setting key insertion unit 68a is turned OFF using the setting key. In this case, the configuration may determine whether the setting key insertion unit 68a has switched from the ON state to the OFF state, or whether the setting key insertion unit 68a is in the OFF state. If the setting key insertion unit 68a is not turned OFF (step S8507: NO), the process in step S8507 is executed again.

If the setting key insertion section 68a is in the OFF position (step S8507: YES), the setting update display flag in the work area 221 for specific control is cleared to "0" (step S8508).

According to the above configuration, in a system where the setting value is updated when the update button 68b is pressed, the setting value is confirmed when the reset button 68c is pressed, and the setting value update process is terminated when the setting key insertion part 68a is turned OFF. In other words, in order to terminate the setting value update process after updating the setting value, it is necessary not only to turn OFF the setting key insertion part 68a but also to press the reset button 68c. This makes it difficult to attempt to play the game with a setting value that has been illegally updated.

<Embodiment 35>
In this embodiment, the processing configuration for display control of the first to fourth notification display devices 201 to 204, executed by the main CPU 63, differs from that of the 33rd embodiment. The configurations that differ from the 33rd embodiment will be described below. Configurations that are the same as those in the 33rd embodiment will generally not be described.

Figure 126 is an explanatory diagram illustrating the electrical configuration of the calculation result storage area 234 located in the work area 223 for non-specific control.

The calculation result storage area 234 stores information about the base value calculated by the main CPU 63. The base value is the ratio of the total number of game balls dispensed to the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) in situations that are neither the opening/closing execution mode based on a jackpot result nor the high-frequency support mode.

Regarding the calculation of the base value in detail, in this embodiment, although a normal counter area 231 is provided in the work area 223 for non-specific control, a counter area 232 for opening/closing execution mode and a counter area 233 for high-frequency support mode are not provided. The normal counter area 231 is provided with a normal general prize counter 231a, a normal special electric prize counter 231b, a normal first operation counter 231c, a normal second operation counter 231d, and a normal out counter 231e, similar to the 15th embodiment described above. In situations where neither the opening/closing execution mode based on a jackpot result nor the high-frequency support mode is active, if one game ball enters the general prize entry port 31, the value of the normal general prize entry counter 231a is increased by 1; if one game ball enters the special electric prize entry device 32, the value of the normal special electric prize entry counter 231b is increased by 1; if one game ball enters the first operation port 33, the value of the normal first operation counter 231c is increased by 1; if one game ball enters the second operation port 34, the value of the normal second operation counter 231d is increased by 1; and if one game ball enters the out port 24a, the value of the normal out counter 231e is increased by 1. When the values of the various counters 231a to 231e in the normal counter area 231 in situations where neither the opening/closing execution mode based on a jackpot result nor the high-frequency support mode is active, the base values are as follows.
Base value: The ratio of the total number of game balls dispensed (K91 × "number of prize balls for winning into the general prize slot 31" + K92 × "number of prize balls for winning into the special electric prize slot 32" + K93 × "number of prize balls for winning into the first operating slot 33" + K94 × "number of prize balls for winning into the second operating slot 34") to the total number of game balls discharged from the game area PA (K91 + K92 + K93 + K94 + K95).

The base value is calculated each time the result calculation process (Figure 130), described later, is executed in the management process (step S8920) of the first timer interrupt process (Figure 133), described later. However, the values of the various counters 231a to 231e in the normal counter area 231 are cleared to "0" when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) becomes the management start reference number, in situations where the management start flag in the non-specific control work area 223 is not set to "1" and neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode is active. Furthermore, when the management start flag is set to "1" and neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode is active, the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) becomes the shift reference number, and the values are cleared to "0".

The management start reference number is set to 300, which is less than the shift reference number, as in the 15th embodiment described above. At the stage of shipping the pachinko machine 10, the operation of the pachinko machine 10 may be checked before shipment, and at that time, game balls are loaded into each ball entry section and the subsequent operation is checked. The base value under such circumstances may be a different value from the situation when normal gameplay is performed. Therefore, when the management start flag is not set to "1" and neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode is in effect, when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) becomes the management start reference number, which is less than the shift reference number, the various counters 231a to 231e in the normal counter area 231 are cleared to "0", which reduces the influence of the operation check on the base value when normal gameplay is performed after the pachinko machine 10 has been shipped. Furthermore, the starting number for management is not limited to 300; any number is acceptable, and it may be set to fewer than 300 or more than 300.

The shift threshold is set to 60,000 balls. Since the pachinko machine 10 launches a maximum of 100 game balls per minute, 60,000 balls represents the maximum number of balls launched in 10 hours. In this case, a typical operating time for a gaming hall is approximately 13 hours, of which approximately 10 hours are spent playing in situations where neither the opening/closing execution mode (based on jackpot results) nor the high-frequency support mode is active. Therefore, the shift threshold is set based on the assumed maximum number of game balls launched in approximately one business day. Each time the shift threshold is reached, the various counters 231a to 231e in the normal counter area 231 are cleared to "0," allowing the calculation of a base value within the range of the shift threshold. Note that the shift threshold is not limited to 60,000 balls; any number is acceptable, and it may be set to a number less than or greater than 60,000.

The calculation result storage area 234 includes the current area 311, the first history area 312, the second history area 313, and the third history area 314 as storage areas for storing the base value information. These various areas 311 to 314 all have the same storage capacity, specifically 1 byte in size to accommodate the base value information.

The current area 311 stores the base value calculated in the most recent result calculation process (Figure 130). In other words, the current area 311 stores the most recent base value.

The first history area 312 stores the final base value for the previous calculation period. In this case, if the previous calculation period occurred after the management start flag was set to "1", the first history area 312 stores the base value at the time when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) became the shift reference number, under conditions neither of the jackpot-based opening/closing execution mode nor the high-frequency support mode during the previous calculation period. Furthermore, if the management start flag was set to "1" after the previous calculation period had elapsed, the first history area 312 stores the base value at the time when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) became the management start reference number, under conditions neither of the jackpot-based opening/closing execution mode nor the high-frequency support mode during the previous calculation period.

The second history area 313 stores the final base value from the calculation period two cycles prior. In this case, if the calculation period two cycles prior occurred after the management start flag was set to "1", the second history area 313 stores the base value at the time when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reached the shift reference number during the calculation period two cycles prior, under conditions neither of the jackpot-based opening/closing execution mode nor the high-frequency support mode. Furthermore, if the management start flag was set to "1" after the two cycles prior had elapsed, the second history area 313 stores the base value at the time when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reached the management start reference number during the calculation period two cycles prior, under conditions neither of the jackpot-based opening/closing execution mode nor the high-frequency support mode.

The third history area 314 stores the final base value from the calculation period three cycles prior. In this case, if the calculation period three cycles prior occurred after the management start flag was set to "1", the third history area 314 stores the base value at the time when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reached the shift reference number during the calculation period three cycles prior, under conditions neither of the jackpot-based opening/closing execution mode nor the high-frequency support mode. Furthermore, if the management start flag was set to "1" after the three cycles prior had elapsed, the third history area 314 stores the base value at the time when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reached the management start reference number during the calculation period three cycles prior, under conditions neither of the jackpot-based opening/closing execution mode nor the high-frequency support mode.

The base values stored in the current area 311, the first history area 312, the second history area 313, and the third history area 314 are sequentially reported by the first to fourth notification display devices 201 to 204. Specifically, each time the display duration (specifically 5 seconds) elapses, the base values to be reported are switched in a predetermined order: current area 311 → first history area 312 → second history area 313 → third history area 314. This switching of base values in the predetermined order is repeated.

Figures 127(a) to 127(d) are explanatory diagrams for explaining the display contents of the first to fourth notification display devices 201 to 204 when the base values stored in various areas 311 to 314 are notified while the management start flag is set to "1". Figure 127(a) shows an example of the display contents of the first to fourth notification display devices 201 to 204 when the base value stored in the current area 311 is notified, Figure 127(b) shows an example of the display contents of the first to fourth notification display devices 201 to 204 when the base value stored in the first history area 312 is notified, Figure 127(c) shows an example of the display contents of the first to fourth notification display devices 201 to 204 when the base value stored in the second history area 313 is notified, and Figure 127(d) shows an example of the display contents of the first to fourth notification display devices 201 to 204 when the base value stored in the third history area 314 is notified.

As shown in Figures 127(a) to 127(d), the first to fourth notification display devices 201 to 204 each have eight display segments 321 to 324. Seven of the eight display segments 321 to 324 are rod-shaped light-emitting regions of the same shape and size, arranged to form the shape of the number "8". On the other hand, one display segment 321 to 324 has a circular light-emitting region and is positioned to the lower right of the seven figure-eight-shaped display segments 321 to 324. Regardless of which base value of each of the areas 311 to 314 is being notified, at least one display segment 321 to 324 in each of the first to fourth notification display devices 201 to 204 will be illuminated.

The first notification display device 201 displays an indication that the base value is being reported in the first to fourth notification display devices 201 to 204. Specifically, the letter "b" is displayed on the first notification display device 201 regardless of which of the various areas 311 to 314 is reporting the base value. If information other than the base value is being reported in the first to fourth notification display devices 201 to 204, the letter "b" will not be displayed on the first notification display device 201. Therefore, by confirming that the letter "b" is displayed on the first notification display device 201, the manager of the amusement hall can understand that the base value is being reported in the first to fourth notification display devices 201 to 204.

The second notification display device 202 displays which of the various areas 311 to 314 is currently reporting the base value. Specifically, when the base value of area 311 is currently being reported, the second notification display device 202 displays the letter "L." as shown in Figure 127(a). When the base value of the first history area 312 is being reported, the second notification display device 202 displays the letter "1." as shown in Figure 127(b). When the base value of the second history area 313 is being reported, the second notification display device 202 displays the letter "2." as shown in Figure 127(c). When the base value of the third history area 314 is being reported, the second notification display device 202 displays the letter "3." as shown in Figure 127(d). This allows the administrator of the gaming hall to determine which calculation period the base values reported on the first to fourth notification displays 201 to 204 belong to by checking the characters displayed on the second notification display device 202.

In the second notification display device 202, the circular display segments 321 to 324 illuminate regardless of which of the various areas 311 to 314 is being notified as the base value. As will be described later, the third notification display device 203 and the fourth notification display device 204 will display one of the numbers from "0" to "9" as the display corresponding to the base value. In this case, if one of the numbers from "1" to "3" is displayed in the second notification display device 202, three numbers will be displayed in a row on the second to fourth notification display devices 202 to 204, making it difficult to grasp the base value. In contrast, when the circular display segments 321-324 located in the lower right of the second notification display device 202 illuminate, even if the second notification display device 202 displays one of the numbers "1" through "3," it becomes possible to distinguish and understand the number displayed on the second notification display device 202 from the numbers displayed on the third notification display device 203 and the fourth notification display device 204.

The third notification display device 203 and the fourth notification display device 204 display the base value that is to be notified. The base value is calculated as a decimal number with two decimal places, but the first decimal place of the base value is displayed on the third notification display device 203, and the second decimal place of the base value is displayed on the fourth notification display device 204. Here, if the base value is "1.00", the number "0" is displayed on both the third notification display device 203 and the fourth notification display device 204. On the other hand, if the base value has not yet been stored in the notification target areas 311 to 314, the character "-" is displayed on both the third notification display device 203 and the fourth notification display device 204, as shown in the explanatory diagram in Figure 128(a). This makes it possible to distinguish between cases where the base value is calculated as a decimal to two decimal places and where the base value is "1.00", and cases where the base value has not yet been stored in the notification areas 311-314, even when the base value is reported as a decimal to two decimal places on two separate display devices, the third notification display device 203 and the fourth notification display device 204.

Furthermore, the display content of the combination of the third notification display device 203 and the fourth notification display device 204 will be the same whether the base value is "1.00" or "0.00". Alternatively, to distinguish between the two, the display of "00" may be kept illuminated in one of the two displays, while the display of "00" may be made to blink in the other.

Next, referring to the time chart in Figure 129, we will explain how the base values of various areas 311 to 314 are reported on the first to fourth notification display devices 201 to 204 when the management start flag is set to "1". Figure 129(a) shows the period during which the base value stored in the current area 311 is reported on the first to fourth notification display devices 201 to 204, Figure 129(b) shows the period during which the base value stored in the first history area 312 is reported on the first to fourth notification display devices 201 to 204, Figure 129(c) shows the period during which the base value stored in the second history area 313 is reported on the first to fourth notification display devices 201 to 204, and Figure 129(d) shows the third history area Figure 129(e) shows the period during which the base value stored in the rear 314 is announced by the first to fourth notification display devices 201 to 204. Figure 129(e) shows the period from the start of the base value calculation period until the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the initial reference number (specifically, 6000 balls) in a situation that is neither the opening/closing execution mode based on a jackpot result nor the high-frequency support mode.

At timing t1, as shown in Figure 129(a), notification of the base value stored in the current area 311 is initiated on the first to fourth notification display devices 201 to 204. During this notification, as shown in Figure 127(a), the first notification display device 201 displays an indication that the base value is the target of notification, the second notification display device 202 displays an indication that the base value stored in the current area 311 is the target of notification, and the third notification display device 203 and the fourth notification display device 204 display an indication corresponding to the base value stored in the current area 311.

Here, as shown in Figure 129(e), an initial calculation display is performed from timing t1 to timing t2. Specifically, from the start of the base value calculation period until the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the initial reference number (specifically, 6000 balls) in situations that are neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode, the characters to be displayed on the first notification display device 201 and the second notification display device 202 are not kept lit, but instead the characters to be displayed are flashed as an initial calculation display. Immediately after the start of the calculation period, there is little information from the game history needed to calculate the base value, so the measured value of the base value may deviate significantly from the theoretical range of the base value. In contrast, by performing this initial calculation display immediately after the start of the calculation period, it is possible to make the manager of the game hall aware that the calculation period has just started.

Furthermore, in the initial calculation display, the third and fourth notification display devices 203 and 204, which display numbers corresponding to the base value, keep these numbers illuminated, while the characters to be displayed on the first and second notification display devices 201 and 202 blink. This makes it possible to notify that the calculation period has just begun without reducing the visibility of the base value. However, this is not limited to this configuration; even in the initial calculation display, blinking may be performed on at least one of the third and fourth notification display devices 203 and 204, or on both, or on only one of the first and second notification display devices 201 and 202. Also, the initial reference number is not limited to 6000; any number is acceptable, and it may be set to a number less than 6000 or a number more than 6000.

At timing t2, the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) since timing t1, under conditions neither of the opening/closing execution mode based on the jackpot result nor the high-frequency support mode, reaches the initial reference number (specifically, 6000 balls). As a result, the initial calculation display ends, as shown in Figure 129(e). This causes the illumination display to start not only on the third and fourth notification display devices 203 and 204, but also on the first and second notification display devices 201 and 202.

Subsequently, at timing t3, the display duration from timing t1 has elapsed, and as shown in Figure 129(a), the notification of the base value stored in the current area 311 ends, and as shown in Figure 129(b), the notification of the base value stored in the first history area 312 begins. In this case, since the base value stored in the first history area 312 is the final calculation result of the previous calculation period, no initial calculation display is performed.

Subsequently, at timing t4, the display duration from timing t3 has elapsed, and as shown in Figure 129(b), the notification of the base value stored in the first history area 312 ends, and as shown in Figure 129(c), the notification of the base value stored in the second history area 313 begins. In this case, since the base value stored in the second history area 313 is the final calculation result of the calculation period two calculation periods prior, no initial calculation display is performed.

Subsequently, at timing t5, the display duration from timing t4 has elapsed, and as shown in Figure 129(c), the notification of the base value stored in the second history area 313 ends, and as shown in Figure 129(d), the notification of the base value stored in the third history area 314 begins. In this case, since the base value stored in the third history area 314 is the final calculation result of the calculation period three calculations prior, the initial calculation display is not performed.

Subsequently, at timing t6, the display continuation period from timing t5 has elapsed, and as shown in Figure 129(d), the notification of the base value stored in the third history area 314 ends, and as shown in Figure 129(a), the notification of the base value stored in the current area 311 begins. In this case, to indicate that the base value calculation period has started anew and is in a state where neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode is active, the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the initial reference number (specifically, 6000 balls), an initial calculation display is performed from timing t6 to timing t7, as shown in Figure 129(e).

Subsequently, at timing t8, the display duration from timing t6 has elapsed, and as shown in Figure 129(a), the notification of the base value stored in the current area 311 ends, and as shown in Figure 129(b), the notification of the base value stored in the first history area 312 begins. In this case, since the base value stored in the first history area 312 is the final calculation result of the previous calculation period, no initial calculation display is performed.

Next, we will explain the processing configuration that enables the notification of the base value as described above.

In the management process (step S8920) of the first timer interrupt processing (Figure 133), described later, the program for the management execution process, which corresponds to non-specific control, is read in step S3803, similar to the management process in the 15th embodiment (Figure 70). Then, in this management execution process (Figure 71), a check process is executed in step S3908, similar to the 15th embodiment.

In the check process, when neither the opening/closing execution mode based on a jackpot result nor the high-frequency support mode is active, if one game ball is detected entering the general prize entry port 31, the value of the normal general prize entry counter 231a is incremented by 1. If one game ball is detected entering the special electric prize entry device 32, the value of the normal special electric prize entry counter 231b is incremented by 1. If one game ball is detected entering the first operation port 33, the value of the normal first operation counter 231c is incremented by 1. If one game ball is detected entering the second operation port 34, the value of the normal second operation counter 231d is incremented by 1. If one game ball is detected entering the out port 24a, the value of the normal out counter 231e is incremented by 1. Furthermore, the check process also performs result calculation and display processing.

Figure 130 is a flowchart showing the result calculation process. Note that steps S8601 to S8615 in the result calculation process are executed using the non-specific control program and non-specific control data in the main CPU 63.

First, the base value calculation process is performed (step S8601). This calculation process uses the values of the various counters 231a to 231e in the normal counter area 231 to calculate the base value. The method for calculating the base value is as already explained. Then, the calculated base value is overwritten in the current area 311 (step S8602).

Subsequently, it is determined whether the management start flag, provided in the work area 223 for non-specific control, is set to "1" (step S8603). The management start flag is set to "0" when the supply of operating power to the pachinko machine 10 is started for the first time after the pachinko machine 10 has been manufactured. Also, the value of the management start flag is "0" when the work area 223 for non-specific control, including the management start flag, is reset to "0" and initialized. When the management start flag is set to "0" and neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode is active, the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) becomes the management start reference number, and the management start flag is set to "1". Also, when the management start flag is set to "1", the values of the various counters 231a to 231e in the normal counter area 231 are cleared to "0" and a new calculation period begins. This makes it possible to minimize the impact of operational checks performed during the shipping stage of the pachinko machine 10 on the base value under normal gameplay conditions after the machine has been shipped.

If a negative result is obtained in step S8603, the total number is calculated by summing the values of all counters 231a to 231e in the normal counter area 231 (step S8604). Then, it is determined whether the calculated total number is greater than the management start threshold number of 300 (step S8605).

If a positive determination is made in step S8605, the management start flag is set to "1" (step S8606). Then, the data shift process is executed (step S8607). In the data shift process, the information stored in the current area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234 is shifted in the following order: second history area 313 → third history area 314, first history area 312 → second history area 313, current area 311 → first history area 312. As a result, the final base value from the calculation period two periods ago is stored in the third history area 314 as the final base value from the calculation period three periods ago, the final base value from the calculation period one period ago is stored in the second history area 313 as the final base value from the calculation period two periods ago, and the base value calculated last in the current calculation period is stored in the first history area 312 as the final base value from the calculation period one period ago. In data shifting operations, the LDIR instruction is used to perform the information shift described above. The LDIR instruction specifies the address of the source area and the address of the destination area, thereby shifting (copying) the information stored in the source area to the destination area.

However, when the management start flag is not set to "1", the base value information is basically not stored in the first to third history areas 312 to 314. Therefore, in step S8607, only the final base value for the calculation period when the management start flag is not set to "1" is shifted to the first history area 312. After that, all counters 231a to 231e in the normal counter area 231 are cleared to "0" (step S8608).

If a positive result is obtained in step S8603, the total number is calculated by summing the values of all counters 231a to 231e in the normal counter area 231 (step S8609). Then, it is determined whether the calculated total number is greater than the initial reference number of 6000 (step S8610). If a negative result is obtained in step S8610, the calculation initial flag provided in the non-specific control work area 223 is set to "1" (step S8611). If a positive result is obtained in step S8610, the calculation initial flag is cleared to "0" (step S8612). The calculation initial flag is used by the main CPU 63 to determine whether the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) has reached the initial reference number, under conditions other than the opening/closing execution mode due to a jackpot result or the high-frequency support mode, since the base value calculation period began.

If the processing in step S8611 or step S8612 is executed, it is determined in step S8609 whether the total number calculated is 60,000 or more, which is the shift reference number (step S8613). If the determination in step S8613 is positive, the data shift process is executed (step S8614). In the data shift process, the information stored in the current area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234 is shifted in the following order: second history area 313 → third history area 314, first history area 312 → second history area 313, and current area 311 → first history area 312. As a result, the final base value from the calculation period two periods ago is stored in the third history area 314 as the final base value from the calculation period three periods ago, the final base value from the calculation period one period ago is stored in the second history area 313 as the final base value from the calculation period two periods ago, and the base value calculated last in the current calculation period is stored in the first history area 312 as the final base value from the calculation period one period ago. In data shift processing, the LDIR instruction is used to perform the above-described information shift. The LDIR instruction specifies the address of the area where the information is stored and the address of the area where the information is stored, thereby shifting (copying) the information stored in the source area to the destination area. Afterward, all counters 231a to 231e in the normal counter area 231 are cleared to "0" (step S8615).

Figure 131 is a flowchart showing the display processing. Note that steps S8701 to S8714 in the display processing are executed using the non-specific control program and non-specific control data in the main CPU 63.

First, it is determined whether the management start flag provided in the work area 223 for non-specific control is set to "1" (step S8701). If the determination in step S8701 is positive, the value of the switching timing counter provided in the work area 223 for non-specific control is deducted by 1 (step S8702). The switching timing counter is a counter used by the main CPU 63 to identify that it is the timing to switch the base value that is the subject of notification in the first to fourth notification display devices 201 to 204, among the base values stored in the current area 311, first history area 312, second history area 313, and third history area 314 of the calculation result storage area 234. As already explained, each time the display period (specifically 5 seconds) elapses, the base value to be notified is switched in a predetermined order: current area 311 → first history area 312 → second history area 313 → third history area 314. This switching of the base value to be notified in this predetermined order is repeated.

If the process in step S8702 is executed, it is determined whether the value of the switching timing counter after subtracting 1 is "0" to determine whether the display duration has elapsed since the current base value became the target of the broadcast (step S8703). If the determination in step S8703 is positive, the value of the display target counter provided in the non-specific control work area 223 is incremented by 1 (step S8704). Then, if the value of the display target counter after incrementing by 1 exceeds the maximum value of "3" (step S8705: YES), the value of the display target counter is cleared to "0" (step S8706).

The display target counter is a counter used by the main CPU 63 to identify the base value to be reported in the first to fourth notification display devices 201 to 204 from among the base values stored in the current area 311, first history area 312, second history area 313, and third history area 314, respectively, within the calculation result storage area 234. Specifically, when the value of the display target counter is "0", the base value stored in the current area 311 is the target for reporting; when the value of the display target counter is "1", the base value stored in the first history area 312 is the target for reporting; when the value of the display target counter is "2", the base value stored in the second history area 313 is the target for reporting; and when the value of the display target counter is "3", the base value stored in the third history area 314 is the target for reporting.

If a negative determination is made in step S8705, or if the process in step S8706 is executed, the switching timing counter in the non-specific control work area 223 is set to a value corresponding to the display duration (specifically 5 seconds) as the value corresponding to the switching timing of the next notification target (step S8707).

If a negative determination is made in step S8703, or if the process in step S8707 is executed, a process is executed to set display data corresponding to the base value that is currently being notified in the display target setting area 276 provided in the work area 223 for non-specific control. Specifically, first, display type data corresponding to the value of the display target counter is set in the display target setting area 276 (step S8708). The display type data includes display data for causing the first notification display device 201 to display that the notification target of the first to fourth notification display devices 201 to 204 is the base value, and display data for causing the second notification display device 202 to display that the base value of the notification target corresponds to one of the current area 311, first history area 312, second history area 313, or third history area 314 in the calculation result storage area 234.

Subsequently, the base value is read from the area corresponding to the value of the display target counter among the current area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234. The calculation result data corresponding to the first decimal place and the second decimal place of the read base value is then set in the display target setting area 276 (step S8709). The calculation result data includes display data for causing the third notification display device 203 to display the value corresponding to the first decimal place of the base value to be notified, and display data for causing the fourth notification display device 204 to display the value corresponding to the second decimal place of the base value to be notified.

As described above, display data consisting of display type data and calculation result data is set in the display target setting area 276. This display data is transmitted to the display IC 266 during the second timer interrupt processing (Figure 134), which will be described later. The first to fourth notification display devices 201 to 204 then display the information corresponding to this data.

Furthermore, the process in step S8709 is executed each time the display process (Figure 131) is performed, regardless of the switching timing of the base value to be notified. As already explained, each time the calculation result storage process (Figure 130) is executed, the base value is calculated using the current values of each counter 231a to 231e in the normal counter area 231, and this calculated base value is stored in the current area 311 of the calculation result storage area 234. In this case, as described above, the process in step S8709 for setting the calculation result data in the display target setting area 276 is executed each time the display process (Figure 131) is performed, regardless of the switching timing of the base value to be notified. Therefore, if the base value in the current area 311 is changed while it is set to be notified, the changed base value can be notified.

Subsequently, based on the value of the display target counter, it is determined whether the current base value of area 311 is subject to notification (step S8710), and it is determined whether the calculation initial flag provided in the non-specific control work area 223 is set to "1" (step S8711). As already explained, the calculation initial flag is a flag used by the main CPU 63 to determine whether the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) has reached the initial reference number when neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode has started since the base value calculation period began. If a positive determination is made in both steps S8710 and S8711, the initial display flag provided in the non-specific control work area 223 is set to "1" (step S8712). If a negative determination is made in either step S8710 or S8711, the initial display flag is cleared to "0" (step S8713).

The initial display flag is a flag used by the main CPU 63 to identify a situation where, in the current state where the base value of area 311 is the target of notification, the first notification display device 201 and the second notification display device 202 should be flashed to indicate that the base value is the initial base value of the calculation after the start of the calculation period. When the second timer interrupt processing (Figure 134), described later, determines that the initial display flag is set to "1", it not only transmits the display data stored in the display target setting area 276 to the display IC 266, but also flashes the first notification display device 201 and the second notification display device 202, and lights up the third notification display device 203 and the fourth notification display device 204, when the first to fourth notification display devices 201 to 204 are to display the corresponding information. Furthermore, if the second timer interrupt processing (Figure 134), described later, determines that the initial display flag is not set to "1", then when the first to fourth notification display devices 201 to 204 are to display the display data stored in the display target setting area 276, all of the first to fourth notification display devices 201 to 204 will be illuminated.

On the other hand, if the management start flag in the non-specific control work area 223 is not set to "1" and a negative determination is made in step S8701, regardless of the value of the display target counter, the base value is read from the current area 311, and the calculation result data corresponding to the first decimal place and the second decimal place of the read base value is set in the display target setting area 276 (step S8714). When the display data corresponding to this calculation result data is transmitted to the display IC 266, the first decimal place of the base value in the current area 311 is displayed on the third notification display device 203, and the second decimal place of the base value in the current area 311 is displayed on the fourth notification display device 204. With this configuration, when the management start flag is not set to "1", the base values from past calculation periods are not reported; only the base value calculated in the current calculation period is reported.

When the management start flag is not set to "1", the calculation result data is set in the display target setting area 276, but the display type data is not set. As will be explained in detail later, when the base value is not reported when the management start flag is not set to "1", the display content of the first notification display device 201 and the second notification display device 202 will be different from when the base value is reported when the management start flag is set to "1".

Next, the main processing in this embodiment, which is executed by the main CPU 63, will be explained with reference to the flowchart in Figure 132. Note that steps S8801 to S8825 in the main processing are executed using the specific control program and specific control data in the main CPU 63.

First, the power-on initial setup process is executed (step S8801). During this process, for example, after the main process starts, the system waits for a predetermined waiting period (specifically, 1 second) before proceeding to the next process. During this predetermined waiting period, the operation and initial setup of the graphic display device 41 are completed. Access to the main RAM 65 is also permitted.

Subsequently, the internal function register setting process is executed (step S8802). In this process, the interrupt period of the first timer interrupt process (Figure 133), which is periodically interrupted and activated by the main process, is set to the first interrupt period (specifically, 4 milliseconds). The interrupt period of the second timer interrupt process (Figure 134), which is also periodically interrupted and activated by the main process, is set to the second interrupt period (specifically, 2 milliseconds), which is shorter than the first interrupt period.

In other words, in this embodiment, similar to the 33rd embodiment described above, there are two timer interrupt processes, a first timer interrupt process and a second timer interrupt process, with relatively long and short interrupt periods. Both the first and second timer interrupt processes are initiated by interrupting the main process. Furthermore, the second timer interrupt process is initiated by interrupting the first timer interrupt process. On the other hand, the first timer interrupt process is not initiated by interrupting the second timer interrupt process. Also, if both the first and second timer interrupt processes are not executed and both interrupt periods have elapsed, the second timer interrupt process is initiated first, regardless of the order in which those periods have elapsed. In this respect, the second timer interrupt process can be said to be a process that is initiated with higher priority than the first timer interrupt process. However, this is not limited to this, and a configuration in which the first timer interrupt process is initiated with higher priority than the second timer interrupt process is also possible.

In the internal function register setting process, the first interrupt period of the first timer interrupt process is set to a predetermined register in the main CPU 63, and the second interrupt period of the second timer interrupt process is set to a specific register in the main CPU 63. In addition to setting the first and second interrupt periods, the internal function register setting process also performs other operations, such as setting the numerical ranges of various counters, including the numerical range of the random number counter C1.

Subsequently, the startup processing flag located in the work area 221 for specific control is set to "1" (step S8803). The startup processing flag is used by the main CPU 63 to identify a situation where, even if the first timer interrupt process is activated, the processes for power outage monitoring, updating various counters, and fraud monitoring among the various processes set for the first timer interrupt process should be executed, but the processes for advancing the game should not be executed, and the first timer interrupt process should be terminated.

Figure 133 is a flowchart showing the first timer interrupt processing in this embodiment, which is executed by the main CPU 63. As previously explained, the first timer interrupt processing is activated periodically at a 4-millisecond interval, which is the first interrupt period. Furthermore, the program corresponding to the first timer interrupt processing is set as a specific control program.

Steps S8901 to S8905 execute the same process as steps S301 to S305 of the timer interrupt processing (Figure 11) in the first embodiment described above. That is, power outage monitoring is performed by executing power outage information storage processing in step S8901. Specifically, similar to the power outage information storage processing (Figure 101) in the 30th embodiment described above, the system monitors whether or not a power outage signal corresponding to the occurrence of a power interruption has been received from the power outage monitoring board 67, and if a power outage is identified, the system executes power outage processing and then enters an infinite loop. In the power outage processing, the power outage flag provided in the work area 221 for specific control is set to "1", and a checksum is calculated and stored in the work area 221 for specific control. Furthermore, in step S8902, the random number update process for the lottery is executed to update the numerical information of the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal electric device release counter C4. In step S8903, the random number initial value update process is executed to update the numerical information of the random number initial value counter CINI. In step S8904, the variation counter update process is executed to update the numerical information of the variation type counter CS. In addition, in step S8905, the fraud detection process is executed to monitor whether an event set as a target for fraud detection has occurred. This fraud detection process monitors the occurrence of multiple types of events, and if it is confirmed that any of these multiple types of events have occurred, the game stop flag provided in the specific control work area 221 is set to "1".

After executing the processes in steps S8901 to S8905, it is determined whether "1" is set in either the game stop flag or the startup processing flag provided in the work area 221 for specific control (step S8906). If "1" is not set in either the game stop flag or the startup processing flag (step S8906: NO), the processes in steps S8907 to S8920 are executed. Steps S8907 to S8919 execute the same processes as steps S8208 to S8220 of the first timer interrupt processing (Figure 117) in the 33rd embodiment described above. In addition, in step S8920, management processing is executed in the same way as step S8221 of the first timer interrupt processing (Figure 117) in the 33rd embodiment described above, but the content of the check processing of the management execution processing called in said management processing is the same as that already described. During this check process, the update process for each counter 231a to 231e in the normal counter area 231 is executed, and the result calculation process (Figure 130) and display process (Figure 131) are also executed.

On the other hand, if at least one of the game stop flag and the startup processing flag is set to "1" (step S8906: YES), the first timer interrupt process terminates without executing steps S8907 to S8920. In other words, not only when the game stop flag is set to "1", but also when the startup processing flag is set to "1", the first timer interrupt process executes steps S8901 to S8905, but does not execute steps S8907 to S8920.

The startup processing flag is set to "1" in the main processing (Figure 132) when the power supply start processing (steps S8801 to S8819) begins and before the interrupt is enabled (step S8805), similar to the 33rd embodiment described above. It is then cleared to "0" before the power supply start processing ends and the remaining processing (steps S8822 to S8825) begins. In this case, as described above, the first timer interrupt processing does not execute steps S8907 to S8920 if the startup processing flag is set to "1". This makes it possible to prevent the processing necessary to advance the game from being executed while the power supply start processing (steps S8801 to S8819) is being executed. On the other hand, as described above, even if the startup processing flag is set to "1" in the first timer interrupt processing, the processing in steps S8901 to S8905 is executed. This ensures that power outage monitoring is performed even while the power supply start-up processing (steps S8801 to S8819) is running. Furthermore, the random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the random number initial value counter CINI are updated, and fraud detection is performed.

In particular, even when the startup process flag is set to "1", the power outage information storage process (step S8901) is executed. This allows the system to execute power outage processing even if a power outage occurs while the power supply start process (steps S8801 to S8819) is being executed. As explained earlier, the power outage processing sets the power outage flag in the specific control work area 221 to "1", calculates a checksum, and stores the calculated checksum in the specific control work area 221. Therefore, when the power supply restarts, it is not identified as an abnormality in the main RAM 65. This allows the system to retain the currently selected setting value as the current setting value of the pachinko machine 10 even if a power outage occurs during the setting value update process (step S8819). Therefore, even if a power outage occurs during the execution of the setting value update process, it is not necessary to re-execute the setting value update process when the power supply restarts.

Incidentally, when the setting value update process is being executed, interrupts are not prohibited for either the first timer interrupt process (Figure 133) or the second timer interrupt process (Figure 134), and interrupts can occur at any time. In this case, if the first timer interrupt process (Figure 133) or the second timer interrupt process (Figure 134) is interrupted and activated in the main process (Figure 132), including the setting value update process, the return address information of the main process (Figure 132) for returning after the activated timer interrupt process has finished is saved in the specific control stack area 222. At the same time, information from various registers of the main CPU 63 immediately before the timer interrupt process is activated is also saved in the specific control stack area 222. Then, when the activated timer interrupt process has finished, the main process (Figure 132) returns to the processing corresponding to the return address information saved in the specific control stack area 222, and the information saved in the specific control stack area 222 is restored to the various registers of the main CPU 63.

Returning to the explanation of the main process (Figure 132), after setting the startup process flag to "1" in step S8803, a value corresponding to the initial check period (specifically 5 seconds) is set in the check counter provided in the work area 221 for specific control (step S8804). In this embodiment, when the supply of operating power to the main CPU 63 is started, a check display is performed on the first to fourth notification display devices 201 to 204 from the start of the process in step S8804 until the initial check period has elapsed, in order to allow the administrator of the gaming hall to confirm whether each display segment 321 to 324 provided in the first to fourth notification display devices 201 to 204 can normally illuminate. Specifically, as shown in the explanatory diagram in Figure 128(b), all display segments 321 to 324 of the first to fourth notification display devices 201 to 204 are maintained in an illuminated state. In step S8804, information corresponding to this initial check period is set in the check counter.

The initial check period is set to be longer than the maximum time required before the process to control the game's progress begins if none of the processes described in steps S8811, S8812, S8815, and S8819 are executed in the main process. Therefore, the game may start while the check display is being shown on the first to fourth notification display devices 201 to 204.

Subsequently, the interrupt permission setting is performed (step S8805). This causes the first timer interrupt process (Figure 133) to interrupt and start at the first interrupt cycle, and the second timer interrupt process (Figure 134) to interrupt and start at the second interrupt cycle. However, because the startup process flag is set to "1" in step S8803, even if the first timer interrupt process is started, the processes for power outage monitoring, updating various counters, and fraud monitoring are executed, but the processes for advancing the game are not executed, and the first timer interrupt process terminates.

Subsequently, steps S8806 to S8825 execute the same processing as steps S7905 to S7924 of the main processing (Figure 114) in the 33rd embodiment described above. Specifically, in step S8806, it is determined whether or not the reset button 68c is pressed. That is, it is determined whether or not the power ON operation of the pachinko machine 10 is performed and the supply of operating power to the MPU 62 begins while the reset button 68c is pressed. Here, in this embodiment, similar to the 33rd embodiment described above, the main control device 60 is provided with a setting key insertion unit 68a and a reset button 68c, but the update button 68b is not provided. Also, the main control device 60 is provided with first to fourth notification display devices 201 to 204, similar to the 11th embodiment, instead of first to third notification display devices 69a to 69c.

If the reset button 68c is not pressed (step S8806: NO), it is determined whether the power outage flag in the work area 221 for specific control is set to "1" (step S8807). The power outage flag is set to "1" if the power outage processing is executed during the power outage information storage processing (step S8901) of the first timer interrupt processing (Figure 133). The power outage flag is used by the main CPU 63 to determine whether the power outage processing was performed appropriately during the previous power outage.

If the power outage flag is set to "1" (step S8807: YES), checksums are calculated for the specific control work area 221 and the specific control stack area 222 (step S8808). The method for calculating the checksums is the same as in the 33rd embodiment described above. Then, the checksums for the specific control work area 221 and the specific control stack area 222, which were calculated and stored in the power outage processing executed immediately before the supply of operating power to the MPU 62 was stopped, are read from the specific control work area 221, and these read checksums are compared with the checksums calculated in step S8808 (step S8809). Finally, it is determined whether the checksums match (step S8810).

If a negative determination is made in step S8807 or step S8810, that is, if the power outage flag is not set to "1" or the checksum does not match, the game stop flag provided in the specific control work area 221 is set to "1" (step S8811). Setting the game stop flag to "1" allows the first timer interrupt processing (Figure 133) to execute steps S8901 to S8905, while the positive determination in step S8906 prevents the execution of steps S8907 to S8920. Therefore, if the power outage flag is not set to "1" because the power outage processing was not performed properly during the previous power outage, or if the checksum does not match due to a change in the information storage state in at least one of the specific control work area 221 and the specific control stack area 222 since the previous power outage, the processes for power outage monitoring, updating various counters, and fraud monitoring will be executed, but the processes for continuing the game will not be executed.

Subsequently, an abnormality command indicating that an abnormality occurred regarding the power outage flag or checksum at the start of power supply is transmitted to the voice-emitting control device 81 (step S8812). Upon receiving this abnormality command, the voice-emitting control device 81 illuminates the display light-emitting unit 53 in a manner corresponding to the information abnormality at the start of power supply, and outputs the voice message "Please change the settings." from the speaker unit 54. Furthermore, the text image "Please change the settings." is displayed on the pattern display device 41. These notifications are maintained until the power supply to the pachinko machine 10 is stopped, at which point they terminate. However, even if the power supply to the pachinko machine 10 is temporarily stopped, the above notifications may be continued until the power supply to the pachinko machine 10 is resumed and the setting value update process (step S8819) is executed.

If the power outage flag is set to "1" and the checksum is normal (steps S8807 and S8810: YES), it is determined whether the setting key insertion unit 68a is turned ON using the setting key (step S8813), and it is determined whether the front door frame 14 is open relative to the inner frame 13 and the game machine body 12 is open relative to the outer frame 11 (step S8814). The detection of whether the front door frame 14 is open relative to the inner frame 13 is performed using the front door open sensor 95, as in the 30th embodiment described above, and the detection of whether the game machine body 12 is open relative to the outer frame 11 is performed using the body open sensor 96, as in the 30th embodiment described above. If the setting key insertion section 68a is turned ON using the setting key (step S8813: YES), and furthermore, the front door frame 14 is open relative to the inner frame 13 and the gaming machine body 12 is open relative to the outer frame 11 (step S8814: YES), then the setting confirmation process is executed (step S8815). Details of the setting confirmation process will be explained later.

If the reset button 68c is pressed (step S8806: YES), a RAM clear process is executed (step S8816). The contents of the RAM clear process are the same as step S7915 of the main process in the 33rd embodiment (Figure 114). Subsequently, if the setting key insertion part 68a is turned ON using the setting key (step S8817: YES), and furthermore, if the front door frame 14 is open relative to the inner frame 13 and the game machine body 12 is open relative to the outer frame 11 (step S8818: YES), a setting value update process is executed (step S8819). Details of the setting value update process will be explained later.

If the process in step S8812 is executed, if a negative result is obtained in step S8813 or step S8814, if the process in step S8815 is executed, if a negative result is obtained in step S8817 or step S8818, or if the process in step S8819 is executed, the startup processing flag in the specific control work area 221 is cleared to "0" (step S8820). Clearing the startup processing flag to "0" releases the state in which the process necessary to advance the game is not executed even if the first timer interrupt process is activated. In addition, the power outage flag in the specific control work area 221 is also cleared to "0" in step S8820.

Subsequently, a recovery command is transmitted to the voice and light emission control device 81 (step S8821). The content of the information included in the recovery command and the processing performed by the voice and light emission control device 81 upon receiving the recovery command are the same as those in step S7920 of the main processing (Figure 114) in the 33rd embodiment described above.

Subsequently, the process proceeds to the residual processing steps S8822 to S8825. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt process (Figure 133) and the second timer interrupt process (Figure 134), but residual time occurs between one timer interrupt process and the next. This residual time varies depending on the processing completion time of each timer interrupt process, and the residual processing steps S8822 to S8825 are repeatedly executed using this irregular time. In this respect, the residual processing steps S8822 to S8825 can be considered an irregular process that is executed irregularly. Steps S8822 to S8825 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

Next, the second timer interrupt processing in this embodiment, which is executed by the main CPU 63, will be explained with reference to the flowchart in Figure 134. Note that steps S9001 to S9014 in the second timer interrupt processing are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt disabling is performed to prevent the occurrence of the first timer interrupt process (Figure 133) and the second timer interrupt process (Figure 134) (step S9001). By disabling the occurrence of the first timer interrupt process (Figure 133), it becomes possible to prevent the first timer interrupt process (Figure 133) from interrupting and activating the second timer interrupt process (Figure 134) even after the first interrupt cycle has elapsed. Furthermore, by disabling the occurrence of the second timer interrupt process (Figure 134), it becomes possible to prevent the second timer interrupt process (Figure 134) from being activated redundantly, even if the second interrupt cycle has elapsed during the execution of the second timer interrupt process (Figure 134).

Subsequently, the check counter update process is executed (step S9002). In the check counter update process, if the value of the check counter located in the specific control work area 221 is 1 or greater, the value of the check counter is decremented by 1. This ensures that, when the initial check period is being measured using the check counter, the value of the check counter is periodically decremented each time the second timer interrupt process (Figure 134) is activated.

Subsequently, it is determined whether the setting update display flag in the work area 221 for specific control is set to "1" (step S9003). The setting update display flag is used by the main CPU 63 to determine whether or not it is executing the setting value update process (Figure 137). As already explained, the setting value update process (Figure 137) is executed when the main process (Figure 132) for the start of power supply to the main CPU 63 is running. However, the second timer interrupt process (Figure 134) is started by interrupting even when the power supply start process is running. Therefore, even if the setting value update process (Figure 137) is running on the main CPU 63, the second timer interrupt process (Figure 134) is also started by interrupting.

The setting update display flag being set to "1" means that the current processing run of the second timer interrupt process (Figure 134) was triggered by an interrupt while the main CPU 63 was executing the setting value update process (Figure 137). If a positive determination is made in step S9003, the setting process for the fifth display data buffer 275 during the setting update is executed (step S9004). In this setting process, similar to step S8403 of the second timer interrupt process (Figure 123) in the 33rd embodiment, display data is stored in the fifth display data buffer 275 to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting value of the pachinko machine 10 is being updated and to display the current setting value of the pachinko machine 10. As a result, similar to the 33rd embodiment, the first to fourth notification display devices 201 to 204 will display an indication that the setting value is being updated and to display the current setting value.

If a negative determination is made in step S9003, it is determined whether the setting confirmation display flag in the specific control work area 221 is set to "1" (step S9005). The setting confirmation display flag is a flag used by the main CPU 63 to determine whether or not the main CPU 63 is executing the setting confirmation process (Figure 136). As already explained, the setting confirmation process (Figure 136) is executed when the main process (Figure 132) that starts supplying operating power to the main CPU 63 is executed. However, the second timer interrupt process (Figure 134) is started by interrupting even when the said power supply start process is being executed. Therefore, even if the main CPU 63 is executing the setting confirmation process (Figure 136), the second timer interrupt process (Figure 134) will also be started by interrupting.

The setting confirmation display flag being set to "1" means that the current execution of the second timer interrupt process (Figure 134) was triggered by an interrupt while the main CPU 63 was executing the setting confirmation process (Figure 137). If a positive determination is made in step S9005, the setting process for the fifth display data buffer 275 during setting confirmation is executed (step S9006). In this setting process, similar to step S8405 of the second timer interrupt process (Figure 123) in the 33rd embodiment, display data is stored in the fifth display data buffer 275 to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting value of the pachinko machine 10 is being confirmed and to display the current setting value of the pachinko machine 10. As a result, similar to the 33rd embodiment, the first to fourth notification display devices 201 to 204 will display an indication that the setting value is being confirmed and to display the current setting value.

If a negative result is obtained in step S9005, the normal setting process is executed (step S9007). The normal setting process will be explained in detail later.

If the processing in step S9004, step S9006, or step S9007 is executed, the processing in steps S9008 to S9014 is executed. The processing content of steps S9008 to S9014 is the same as steps S8407 to S8413 of the second timer interrupt processing (Figure 123) in the 33rd embodiment described above.

Specifically, the transmission state of the signals through the type data signal line LN1 and the type clock signal line LN2 is first turned OFF (step S9008), and the transmission state of the signals through the display data signal line LN3 and the display clock signal line LN4 is also turned OFF (step S9009). After that, the update process for the type counter located in the work area 221 for specific control is executed (step S9010).

The type counter is used by the main CPU 63 to identify which of the first to fifth display data buffers 271 to 275 will be used to transmit display data during the current execution cycle of the second timer interrupt process. When the type counter value is "1", the display data from the first display data buffer 271 is used; when the type counter value is "2", the display data from the second display data buffer 272 is used; when the type counter value is "3", the display data from the third display data buffer 273 is used; when the type counter value is "4", the display data from the fourth display data buffer 274 is used; and when the type counter value is "5", the display data from the fifth display data buffer 275 is used. The type counter update process increments the type counter value by 1, and if the value after the increment exceeds the upper limit of "5", the type counter value is set to "1". This sequentially changes the target of display data transmission in the first to fifth display data buffers 271 to 275 for each execution cycle of the second timer interrupt process.

Subsequently, the type data corresponding to the value of the type counter is read from the main ROM 64 (step S9011). Specifically, if the value of the type counter is "1", the type data corresponding to the first display circuit 261 is read from the main ROM 64; if the value of the type counter is "2", the type data corresponding to the second display circuit 262 is read from the main ROM 64; if the value of the type counter is "3", the type data corresponding to the third display circuit 263 is read from the main ROM 64; if the value of the type counter is "4", the type data corresponding to the fourth display circuit 264 is read from the main ROM 64; and if the value of the type counter is "5", the type data corresponding to the fifth display circuit 265 is read from the main ROM 64.

Subsequently, display data is read from display data buffers 271 to 275 corresponding to the value of the type counter (step S9012). Specifically, if the value of the type counter is "1", display data is read from the first display data buffer 271; if the value of the type counter is "2", display data is read from the second display data buffer 272; if the value of the type counter is "3", display data is read from the third display data buffer 273; if the value of the type counter is "4", display data is read from the fourth display data buffer 274; and if the value of the type counter is "5", display data is read from the fifth display data buffer 275.

Subsequently, the transmission process for various signals is executed (step S9013). During this transmission process, signals are output to the type data signal line LN1 and the type clock signal line LN2 so that the type data read in step S9011 is transmitted to the display IC 266. Furthermore, during this transmission process, signals are output to the display data signal line LN3 and the display clock signal line LN4 so that the display data read in step S9012 is transmitted to the display IC 266.

Subsequently, interrupt enablement is set to allow the first timer interrupt process (Figure 133) and the second timer interrupt process (Figure 134) to occur (step S9014).

Figure 135 is a flowchart showing the normal setting process in step S9007 of the second timer interrupt processing (Figure 134). Note that the processing in steps S9101 to S9109 of the normal setting process is executed by the main CPU 63 using a specific control program and specific control data.

First, it is determined whether the value of the check counter provided in the work area 221 for specific control is 1 or greater (step S9101). If the value of the check counter is 1 or greater (step S9101: YES), it means that the initial check period has begun. In this case, the data for the check display is set in the fifth display data buffer 275 in the work area 221 for specific control (step S9102). As already explained, the display data set in the fifth display data buffer 275 is display data for controlling the display of the first to fourth notification display devices 201 to 204. The data for the check display is display data for causing the first to fourth notification display devices 201 to 204 to display the check, that is, display data for setting all display segments 321 to 324 of each of the first to fourth notification display devices 201 to 204 to a lit state. When the data for the check display is supplied to the display IC 266, as shown in the explanatory diagram in Figure 128(b), all display segments 321 to 324 in each of the first to fourth notification display devices 201 to 204 illuminate as a check display. This allows the manager of the amusement hall to determine whether each of the display segments 321 to 324 in the first to fourth notification display devices 201 to 204 can illuminate normally.

Here, the initial check period is configured to be cancelable during setting confirmation or setting value update. This cancelable configuration will now be explained. Figure 136 is a flowchart showing the setting confirmation process executed in step S8815 of the main process (Figure 132). Note that the processing in steps S9201 to S9206 of the setting confirmation process is executed using the specific control program and specific control data in the main CPU 63.

First, an operation instruction command is transmitted to the voice and light emission control device 81 (step S9201). Upon receiving this operation instruction command, the voice and light emission control device 81 outputs the message "Please operate the reset button 68c" from the speaker unit 54. This notification continues until the reset button 68c is pressed.

Subsequently, it is determined whether the reset button 68c has been pressed (step S9202). If the reset button 68c has not been pressed, the system waits in step S9202. If the reset button 68c is pressed (step S9202: YES), the check counter provided in the work area 221 for specific control is cleared to "0" (step S9203). This cancels the initial check period.

Subsequently, the setting confirmation display flag provided in the work area 221 for specific control is set to "1" (step S9204). When the setting confirmation display flag is set to "1", the second timer interrupt processing (Figure 134) makes an affirmative judgment in step S9005, as already explained, and stores display data in the fifth display data buffer 275 to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting value of the pachinko machine 10 is being confirmed and to display the current setting value of the pachinko machine 10 (step S9006). As a result, similar to the 33rd embodiment described above, the first to fourth notification display devices 201 to 204 display an indication that the setting value is being confirmed and to display the current setting value.

Subsequently, provided that the setting key insertion unit 68a is turned OFF (step S9205: YES), the setting confirmation display flag in the work area 221 for specific control is cleared to "0" (step S9206). This cancels the display on the first to fourth notification display devices 201 to 204 that indicates the current setting value of the pachinko machine 10 is being checked, and the display showing the current setting value of the pachinko machine 10. In this case, the first to fourth notification display devices 201 to 204 begin displaying the base value.

As described above, when the setting confirmation process is initiated, and the reset button 68c is pressed, the initial check period is canceled midway, and the current setting value is reported on the first to fourth notification display devices 201 to 204. Therefore, even if the initial check period is configured to start and the check display is shown on the first to fourth notification display devices 201 to 204 while the power supply to the main CPU 63 is running and the main processing (Figure 132) is initiated, it becomes possible to cancel the initial check period and display the current setting value on the first to fourth notification display devices 201 to 204 when checking the setting value while the power supply to the main processing is running. Thus, it becomes possible to check the setting value without waiting for the initial check period to elapse.

Furthermore, even when the setting confirmation process (Figure 136) is executed during the main process (Figure 132), the initial check period starts first. This allows for verification of whether each display segment 321-324 in the first to fourth notification display devices 201-204 can illuminate correctly before confirming the setting value. This enables accurate verification of the setting value.

Figure 137 is a flowchart showing the setting value update process executed in step S8819 of the main process (Figure 132). Note that the processing in steps S9301 to S9310 of the setting value update process is executed using the specific control program and specific control data in the main CPU 63.

First, an update start command is sent to the voice and light emission control device 81 (step S9301). Upon receiving this update start command, the voice and light emission control device 81 outputs the message "Settings are being changed." from the speaker unit 54. This notification continues until the setting value update process is completed.

Subsequently, it is determined whether the value of the set value counter provided in the work area 221 for specific control is 1 or greater, corresponding to "Setting 1," and 6 or less, corresponding to "Setting 6" (step S9302). If the value of the set value counter is "0" or 7 or greater, a negative determination is made in step S9302, and "1" is set in the set value counter (step S9303). As a result, the setting value of the pachinko machine 10 becomes "Setting 1."

If a positive determination is made in step S9302 or the process in step S9303 is executed, it is determined whether the setting key insertion unit 68a is being turned OFF using the setting key (step S9304). In this case, the configuration may determine whether the setting key insertion unit 68a has switched from the ON state to the OFF state, or whether the configuration determines whether the setting key insertion unit 68a is in the OFF state.

If the setting key insertion section 68a is not in the OFF position (step S9304: NO), it is determined whether the reset button 68c is pressed (step S9305). If the reset button 68c is pressed (step S9305: YES), and provided that the setting update display flag in the work area 221 for specific control is not set to "1" (step S9306: NO), the setting update display flag is set to "1" (step S9307), and the check counter in the work area 221 for specific control is cleared to "0" (step S9308).

The initial check period is canceled when the check counter is cleared to "0". Furthermore, when the setting update display flag is set to "1", the second timer interrupt process (Figure 134) makes a positive determination in step S9003, as already explained, and stores display data in the fifth display data buffer 275 (step S9004) to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting values of the pachinko machine 10 are being updated and to display the current setting values of the pachinko machine 10. As a result, similar to the 33rd embodiment described above, the first to fourth notification display devices 201 to 204 display an indication that the setting values are being updated and to display the current setting values.

If a positive result is obtained in step S9306, or if the process in step S9308 is executed, the value of the set value counter in the specific control work area 221 is incremented by 1 (step S9309). This means that each time the reset button 68c is pressed, the set value is updated to one level higher. Furthermore, if the reset button 68c is not pressed (step S9305: NO) or if the set value counter is incremented by 1, the process returns to step S9302. However, if it is determined in step S9302 that the set value counter is 7 or greater, the set value counter is set to "1" in step S9303. This means that if the reset button 68c is pressed once while in the "Setting 6" state, the setting will return to "Setting 1".

If the setting key insertion unit 68a is turned OFF (step 9304: YES), the setting update display flag in the specific control work area 221 is cleared to "0" (step S9310). This cancels the display on the first to fourth notification display devices 201 to 204 that indicates the setting value of the pachinko machine 10 is being updated, and the display showing the current setting value of the pachinko machine 10. In this case, the first to fourth notification display devices 201 to 204 begin displaying the base value.

As described above, when the setting value update process is executed, and the reset button 68c is pressed, the initial check period is canceled midway, and the current setting value is displayed on the first to fourth notification display devices 201 to 204. Therefore, even if the initial check period is configured to start and the check display is shown on the first to fourth notification display devices 201 to 204 while the power supply to the main CPU 63 is running and the main processing (Figure 132) is initiated, if the setting value is to be updated while the power supply to the main processing is running, the initial check period can be canceled, and the current setting value can be displayed on the first to fourth notification display devices 201 to 204. Thus, it becomes possible to update the setting value while confirming the current setting value without waiting for the initial check period to elapse.

Furthermore, even when the setting value update process (Figure 137) is executed during the main process (Figure 132), the initial check period starts first. This allows the system to verify whether each display segment 321-324 in the first to fourth notification display devices 201-204 can illuminate correctly before updating the setting value. This ensures accurate setting value updates.

Furthermore, in the setting value update process (Figure 137), the initial check period is canceled when the reset button 68c is pressed to update the setting value. This means that pressing the reset button 68c to update the setting value cancels the initial check period, improving the ease of operation for canceling the initial check period.

Returning to the explanation of the normal setting process (Figure 135), if the value of the check counter is "0" and it is not the initial check period (step S9101: NO), it is determined whether or not the management start flag provided in the work area 223 for non-specific control is set to "1" (step S9103). If the management start flag is not set to "1" (step S9103: NO), the setting process for the pre-management start display is executed for the first and second notification display devices 201 and 202 (step S9104). In this setting process, display data for illuminating all display segments 321 and 322 of the first and second notification display devices 201 and 202 is set in the fifth display data buffer 275. Furthermore, the configuration is not limited to one in which all display segments 321 and 322 in the first and second notification display devices 201 and 202 are illuminated. A configuration in which all display segments 321 and 322 in the first and second notification display devices 201 and 202 are blinked is also possible.

Subsequently, the calculation result data set in the display target setting area 276 in the non-specific control work area 223 is read (step S9105), and the read calculation result data is set in the fifth display data buffer 275 as display data to be applied to the third and fourth notification display devices 203 and 204 (step S9106). As already explained, in the display processing (Figure 131), if the management start flag is not set to "1" (step S8701: NO), the base value is read from the current area 311, and the calculation result data corresponding to the first decimal place and the second decimal place of the read base value is set in the display target setting area 276 (step S8714). In step S9106, this calculation result data is set in the fifth display data buffer 275 as display data to be applied to the third and fourth notification display devices 203 and 204.

In steps S9104 and S9106, the display data set in the fifth display data buffer 275 is supplied to the display IC 266. As shown in the explanatory diagram in Figure 128(c), when all display segments 321 and 322 are illuminated in the first and second notification display devices 201 and 202, the third notification display device 203 displays the first decimal place of the base value calculated during the current calculation period, and the fourth notification display device 204 displays the second decimal place of the base value calculated during the current calculation period. By displaying the numbers corresponding to the base value in the third and fourth notification display devices 203 and 204 while all display segments 321 and 322 are illuminated in the first and second notification display devices 201 and 202, it becomes possible to make the administrator of the gaming hall aware that the currently reported base value is the base value when the management start flag is not set to "1".

Furthermore, when the management start flag is set to "1," as explained earlier, each time the display duration (specifically 5 seconds) elapses, the base value to be reported in the first to fourth notification display devices 201 to 204 switches in a predetermined order: current area 311 → first history area 312 → second history area 313 → third history area 314. However, when the management start flag is not set to "1," the base value in current area 311 remains the target for reporting. This allows the current base value to be checked at any time during the operational check of the pachinko machine 10 at the time of shipment.

If the management start flag is set to "1" (step S9103: YES), the display data set in the display target setting area 276 in the work area 223 for non-specific control is read, and the read display data is set in the fifth display data buffer 275 (step S9107). When the display data is supplied to the display IC 266, if the base value of the current area 311 is the target of the notification, the display shown in the explanatory diagram in Figure 127(a) will be displayed on the first to fourth notification display devices 201 to 204. If the base value of the first history area 312 is the target of the notification, the display shown in the explanatory diagram in Figure 127(b) will be displayed on the first to fourth notification display devices 201 to 204. If the base value of the second history area 313 is the target of the notification, the display shown in the explanatory diagram in Figure 127(c) will be displayed on the first to fourth notification display devices 201 to 204. If the base value of the third history area 314 is the target of the notification, the display shown in the explanatory diagram in Figure 127(d) will be displayed on the first to fourth notification display devices 201 to 204.

Subsequently, it is determined whether the initial display flag provided in the work area 223 for non-specific control is set to "1" (step S9108). As previously explained, the initial display flag is used by the main CPU 63 to identify a situation where the base value in area 311 is the base value at the beginning of the calculation period, and the first notification display device 201 and the second notification display device 202 should be flashed to indicate that this base value is the initial base value after the start of the calculation period. If the initial display flag is set to "1" (step S9108: YES), the flashing setting process is executed for the first and second notification display devices 201 and 202 (step S9109).

In this blinking setting process, when the display corresponding to the display data currently set in the fifth display data buffer 275 is displayed on the first and second notification display devices 201 and 202, settings are made to cause the display to blink. Specifically, for the transmission of display data to the first and second notification display devices 201 and 202, data corresponding to the display data currently set in the fifth display data buffer 275 is transmitted to the display IC 266 until a predetermined illumination period (e.g., 0.5 seconds) has elapsed. After that, data that turns off all display segments 321 and 322 of the first and second notification display devices 201 and 202 is transmitted to the display IC 266 until a predetermined blackout period (e.g., 0.5 seconds) has elapsed. After that, these predetermined illumination periods and predetermined blackout periods are repeated alternately. This means that if the current base value for area 311 becomes subject to notification immediately after a new calculation period for the base value begins, the first and second notification display devices 201 and 202 will display the initial calculation result. This allows the manager of the gaming hall to understand that the current base value displayed on the first to fourth notification display devices 201 to 204 is the value immediately after the start of the new calculation period.

Next, the display contents of the first to fourth notification display devices 201 to 204 when the supply of operating power to the main CPU 63 is started will be explained with reference to the time chart in Figure 138. Figure 138(a) shows the initial check period, Figure 138(b) shows the pre-management start display period when the base value is announced by the first to fourth notification display devices 201 to 204 when the management start flag is not set to "1", Figure 138(c) shows the normal display period when the base values stored in the various areas 311 to 314 of the calculation result storage area 234 are announced sequentially by the first to fourth notification display devices 201 to 204, and Figure 138(d) shows when the setting value of the pachinko machine 10 is updated. Figure 138(e) shows the display period during which the setting update is being performed, with displays indicating the current state and the current setting value of the pachinko machine 10 shown on the first to fourth notification display devices 201 to 204. Figure 138(f) shows the display period during which the setting confirmation is being performed, with displays indicating the current state and the current setting value of the pachinko machine 10 shown on the first to fourth notification display devices 201 to 204. Figure 138(f) shows the timing when the reset button 68c is pressed.

First, we will explain the case where the supply of operating power to the main CPU 63 is started when the management start flag is not set to "1," and the setting confirmation process (Figure 136) and the setting value update process (Figure 137) are not executed during the power supply start process.

At timing t1, the initial check period begins as shown in Figure 138(a). This triggers the start of check displays on the first to fourth notification display devices 201 to 204, as shown in the explanatory diagram in Figure 128(b).

Subsequently, at timing t2, the initial check period ends without being canceled midway, as shown in Figure 138(a). In this case, at timing t2, the pre-management display period begins, as shown in Figure 138(b). During the pre-management display period, as shown in the explanatory diagram in Figure 128(c), all display segments 321 and 322 on the first notification display device 201 and the second notification display device 202 become illuminated, and the numbers corresponding to the current base value are displayed on the third notification display device 203 and the fourth notification display device 204.

Subsequently, at timing t3, under conditions where the management start flag is not set to "1" and neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode is active, the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the management start reference number, which is less than the shift reference number. As a result, the management start flag is set to "1," and the pre-management start display period ends, as shown in Figure 138(b). In this case, the normal display period begins at timing t3, as shown in Figure 138(c). During the normal display period, the base values stored in various areas 311-314 of the calculation result storage area 234 are sequentially displayed on the first to fourth notification display devices 201-204, as shown in Figures 127(a) to 127(d).

Next, we will explain the case where, with the management start flag set to "1", power supply to the main CPU 63 is initiated, and the setting confirmation process (Figure 136) and the setting value update process (Figure 137) are not executed during the power supply initiation process.

At timing t4, the initial check period begins as shown in Figure 138(a). This triggers the start of check displays on the first to fourth notification display devices 201 to 204, as shown in the explanatory diagram in Figure 128(b).

Subsequently, at timing t5, the initial check period ends without being canceled midway, as shown in Figure 138(a). In this case, at timing t5, the normal display period begins, as shown in Figure 138(c). During the normal display period, the base values stored in various areas 311 to 314 of the calculation result storage area 234 are sequentially displayed on the first to fourth notification display devices 201 to 204, as shown in Figures 127(a) to 127(d).

Next, we will explain the case where the supply of operating power to the main CPU 63 is started when the management start flag is set to "1", and the setting value update process (Figure 137) is executed during the processing at the start of the operating power supply.

At timing t6, the initial check period begins as shown in Figure 138(a). This triggers the start of check displays on the first to fourth notification display devices 201 to 204, as shown in the explanatory diagram in Figure 128(b).

Subsequently, during the initial check period, the setting value update process (Figure 137) is initiated, and at timing t7, the reset button 68c is pressed as shown in Figure 138(f). As a result, at timing t7, the initial check period is terminated prematurely as shown in Figure 138(a), and at timing t7, the setting update display period begins as shown in Figure 138(d).

Subsequently, at timing t8, the setting update display period ends as shown in Figure 138(d). In this case, at timing t8, the normal display period begins as shown in Figure 138(c). During the normal display period, the base values stored in various areas 311 to 314 of the calculation result storage area 234 are sequentially announced on the first to fourth notification display devices 201 to 204, as shown in Figures 127(a) to 127(d).

Next, we will explain the case where the supply of operating power to the main CPU 63 is started when the management start flag is set to "1", and the setting confirmation process (Figure 136) is executed during the power supply start process.

At timing t9, the initial check period begins as shown in Figure 138(a). This triggers the start of check displays on the first to fourth notification display devices 201 to 204, as shown in the explanatory diagram in Figure 128(b).

Subsequently, during the initial check period, a setting confirmation process (Figure 136) is initiated, and at time t10, the reset button 68c is pressed as shown in Figure 138(f). As a result, at time t10, the initial check period is terminated prematurely as shown in Figure 138(a), and at time t10, the setting confirmation display period begins as shown in Figure 138(e).

Subsequently, at timing t11, the setting confirmation display period ends as shown in Figure 138(e). In this case, at timing t11, the normal display period begins as shown in Figure 138(c). During the normal display period, the base values stored in various areas 311 to 314 of the calculation result storage area 234 are sequentially announced on the first to fourth notification display devices 201 to 204, as shown in Figures 127(a) to 127(d).

Furthermore, if the power supply to the main CPU 63 is started while the management start flag is not set to "1," and the initial check period is canceled midway through the power supply start process due to the execution of a setting confirmation process (Figure 136) or a setting value update process (Figure 137), the pre-management start display period will begin after the setting update display period or setting confirmation display period has ended.

The embodiment described in detail above provides the following excellent effects.

As a check indicator, an initial check period may occur in which each of the display segments 321 to 324 in the first to fourth notification display devices 201 to 204 illuminates. This makes it possible to verify whether each of the display segments 321 to 324 illuminates, thereby confirming whether the first to fourth notification display devices 201 to 204 are functioning correctly.

When power is supplied to the main CPU 63, the initial check period for the first to fourth notification display devices 201 to 204 begins. This allows for early verification of whether the first to fourth notification display devices 201 to 204 are functioning correctly once power is supplied.

Each time power is supplied to the main CPU 63, an initial check period for the first to fourth notification display devices 201 to 204 begins. This allows for verification of whether the first to fourth notification display devices 201 to 204 are functioning correctly each time power is supplied.

When power is supplied to the main CPU 63, the initial check period for the first to fourth notification display devices 201 to 204 begins without requiring any special operation. This makes it easy to verify whether the first to fourth notification display devices 201 to 204 are functioning correctly.

Even if the initial check period has not elapsed, if a cancellation trigger occurs, the check display on the first to fourth notification display devices 201 to 204 will be terminated prematurely. This makes it possible to terminate the check display and display other information on the first to fourth notification display devices 201 to 204, even if the initial check period is still in progress.

When power is supplied to the main CPU 63, and before the processing to control the game's progress is executed, an initial check period begins, and the check display is initiated on the first to fourth notification display devices 201 to 204. This makes it possible to verify whether the first to fourth notification display devices 201 to 204 are functioning correctly before the game starts.

In a configuration where predetermined setting-related processes, such as a setting confirmation process (Figure 136) and a setting value update process (Figure 137), are executed while the power supply initiation process is running, the initial check period is initiated while the power supply initiation process is running. This makes it possible to consolidate not only the predetermined setting-related processes but also the process for initiating the initial check period into the power supply initiation process.

In the configuration where the setting confirmation process (Figure 136) and the setting value update process (Figure 137) display the current setting value on the first to fourth notification display devices 201 to 204, an initial check period is started before these predetermined setting-related processes are executed, and the check display is started on the first to fourth notification display devices 201 to 204. This allows the system to confirm whether the first to fourth notification display devices 201 to 204 are functioning correctly, and then use these devices to verify the current setting value. Therefore, accurate verification of the setting value becomes possible.

If the initial check period is still in progress, and the setting confirmation process (Figure 136) or setting value update process (Figure 137) is executed, the check display on the first to fourth notification display devices 201 to 204 will terminate prematurely, even if the initial check period has not yet elapsed. This allows the check process on the first to fourth notification display devices 201 to 204 to terminate and display the current setting value without waiting for the initial check period to expire, thus enabling early verification of the current setting value.

If the setting confirmation process (Figure 136) or the setting value update process (Figure 137) is executed during the initial check period, and the reset button 68c is pressed, the check display on the first to fourth notification display devices 201 to 204 will terminate prematurely, even if the initial check period has not yet elapsed. This makes it possible to terminate the initial check period at any time after the setting confirmation process (Figure 136) or setting value update process (Figure 137) has started. For example, after the setting confirmation process (Figure 136) or setting value update process (Figure 137) has started, the administrator of the gaming hall can sufficiently confirm that the first to fourth notification display devices 201 to 204 are functioning correctly, and then terminate the check display on the first to fourth notification display devices 201 to 204 and begin displaying the current setting value.

Furthermore, in the setting value update process (Figure 137), the setting value of the selected item is updated when the reset button 68c is pressed. In this case, by ensuring that the check display on the first to fourth notification display devices 201 to 204 ends and the display of the current setting value begins when the reset button 68c is pressed, as described above, a dedicated operation to end the check display and begin displaying the current setting value is eliminated. Therefore, the efficiency of the setting value update process can be improved.

The calculation result storage area 234 stores multiple base values derived using information from the normal counter area 231 over different periods. This allows for tracking base values over multiple periods, enabling accurate determination of the ratio of prize balls to the total number of game balls supplied to the game area PA.

The calculation result storage area 234 includes a current area 311 where the most recent base value is stored, and first to third history areas 312 to 314 where base values derived before that are stored. This makes it possible to understand not only the most recent but also past ratios of the number of prize balls to the number of game balls supplied to the game area PA.

The base value, which is repeatedly calculated at relatively short intervals before a calculation period has elapsed, is stored in the current area 311. The base value calculated after a calculation period has elapsed is stored in the first to third history areas 312 to 314. This makes it possible to grasp the most recent ratio of prize balls to the number of game balls supplied to the game area PA, and to grasp the above ratio in the past, on a calculation period basis. Furthermore, since the base value on a calculation period basis is stored in the first to third history areas 312 to 314, it is possible to reduce the number of base values stored in the first to third history areas 312 to 314.

Based on the completion of one calculation period, the various counters 231a to 231e in the normal counter area 231 are cleared to "0". This makes it possible to reduce the required memory capacity in the normal counter area 231. Furthermore, even with this configuration where the various counters 231a to 231e in the normal counter area 231 are cleared to "0", the base value calculated after the completion of one calculation period is stored in the first to third history areas 312 to 314. Therefore, it becomes possible to later determine the ratio of prize balls to the number of game balls supplied to the game area PA during past calculation periods.

Multiple history areas 312 to 314 are provided to store past base values. This makes it possible to compare base values across multiple past calculation periods.

The base values stored in the current area 311, the first history area 312, the second history area 313, and the third history area 314 are sequentially displayed on the first to fourth notification display devices 201 to 204. This allows for the individual tracking of base values for multiple calculation periods while keeping the number of notification devices 201 to 204 to a minimum.

Even while the power supply startup process is running, the power outage information storage process (step S8901) is executed to monitor for power outages, and if a power outage is detected, the power outage processing is executed. This allows for appropriate action to be taken if a power outage occurs while the power supply startup process is running.

In a configuration where the first timer interrupt process (Figure 133) includes power outage information storage processing (step S8901), the first timer interrupt process is triggered even when the power supply start-up process is being executed. This makes it possible to periodically monitor for power outages even when the power supply start-up process is being executed.

The first timer interrupt handler (Figure 133) is activated even if residual processing is being executed after the power supply start-up process has finished. This allows for periodic monitoring of power outages while power supply start-up processing is being performed, by utilizing the first timer interrupt handler, which is activated by interrupting residual processing.

If the first timer interrupt process (Figure 133) is triggered while the power supply start-up process is being executed, the startup process flag in the specific control work area 221 is set to "1," preventing the process for advancing the game from being executed. This makes it possible to prevent the game-advancing process from being executed while the power supply start-up process is running, even in a configuration where the first timer interrupt process is triggered to periodically monitor for power outages.

In a configuration where the setting value update process (Figure 137) is executed while the power supply start-up process is running, the power outage information storage process (step S8901) is executed even while the power supply start-up process is running. This allows for appropriate handling of power outages that occur while setting the target setting values.

Furthermore, the configuration in which the check displays of the first to fourth notification display devices 201 to 204 terminate after the initial check period has elapsed is not limited to this configuration. The check displays may continue until an operation is performed to terminate them. This termination operation could involve, for example, operating the reset button 68c regardless of whether either the setting confirmation process (Figure 136) or the setting value update process (Figure 137) is being executed, or operating an operation unit other than the reset button 68c. In this case, the check displays in the first to fourth notification display devices 201 to 204 will continue until it is time to check the base value or setting value in the first to fourth notification display devices 201 to 204. Therefore, it becomes possible to check the base value or setting value after confirming whether the first to fourth notification display devices 201 to 204 are functioning correctly. Also, since the check displays terminate based on the operation of the operation unit, it is possible to terminate the check displays at a desired timing.

Furthermore, the system may be configured so that the check display on the first to fourth notification display devices 201 to 204 is started when a predetermined operating unit, such as the update button 68b or the reset button 68c, is operated, regardless of whether or not power supply has started. In this case, the check display can be started at a desired timing when checking the base value or set value. Alternatively, the system may be configured so that the check display ends after a predetermined period (e.g., 5 seconds), or the check display ends when the predetermined operating unit used to start the check display, or another operating unit, is operated.

Furthermore, the system may be configured such that when a specific operating button other than the reset button 68c, such as the update button 68b, is operated and power is supplied to the main CPU 63, the check displays on the first to fourth notification display devices 201 to 204 are activated. Conversely, if power is supplied to the main CPU 63 without any operation of the specified operating button, the check displays are not activated. In this configuration, where the check displays are activated upon the activation of power supply, the administrator of the gaming hall can choose whether or not to activate the check displays.

Furthermore, the configuration is not limited to one where the base value is displayed on the first to fourth notification display devices 201 to 204 regardless of whether the gaming machine body 12 is in an open state or not. The configuration may also be such that the base value is displayed on the first to fourth notification display devices 201 to 204 only when it is determined, based on the detection result of the body open sensor 96, that the gaming machine body 12 is in an open state. In this case, when the gaming machine body 12 is in an open state, the check display on the first to fourth notification display devices 201 to 204 is started first, and then the base value is displayed on the first to fourth notification display devices 201 to 204. This makes it possible to check whether the first to fourth notification display devices 201 to 204 are functioning correctly before checking the base value. Also, in this configuration, the check display may be terminated after a predetermined period (e.g., 5 seconds), or the check display may be terminated when the predetermined operation unit used to start the check display, or another operation unit, is operated.

Furthermore, if the main process (Figure 132) starts while the conditions for executing the setting confirmation process (Figure 136) are met, the check displays on the first to fourth notification display devices 201 to 204 will not start. Conversely, if the main process starts while the conditions for executing the setting confirmation process are not met, the check displays will start. In this case, it becomes possible to prevent the check displays from being displayed if it is confirmed that the setting values will be checked.

Furthermore, if the main process (Figure 132) starts while the conditions for executing the setting value update process (Figure 137) are met, the check displays on the first to fourth notification display devices 201 to 204 may not start. Conversely, if the main process starts while the conditions for executing the setting value update process are not met, the check displays may start. In this case, it becomes possible to prevent the check displays from being shown when it is confirmed that the setting value will be updated.

Furthermore, the system may be configured such that if the main process (Figure 132) starts while either the conditions for executing the setting confirmation process (Figure 136) or the setting value update process (Figure 137) are met, the check displays on the first to fourth notification display devices 201 to 204 will not start. Conversely, if the main process starts while neither the conditions for executing the setting confirmation process nor the setting value update process are met, the check displays will start. In this case, it becomes possible to prevent the check displays from being displayed if it is confirmed that the setting values will be confirmed or updated.

Furthermore, the check display is not limited to a configuration where each display segment 321-324 in each of the first to fourth notification display devices 201-204 is kept illuminated. It may also be configured so that each display segment 321-324 in each of the first to fourth notification display devices 201-204 is blinking. Alternatively, the check display may be configured so that each display segment 321-324 in each of the first to fourth notification display devices 201-204 illuminates sequentially, either individually or in groups of several, so that each display segment 321-324 illuminates at least once within the initial check period.

Furthermore, the configuration in which the check display is performed on the first to fourth notification display devices 201 to 204 is not limited to a configuration in which it is performed as a process corresponding to a specific control; it may also be configured to be performed as a process corresponding to a non-specific control.

Furthermore, if a base value is not stored in any of the first to third history areas 312 to 314 of the calculation result storage area 234, the history areas 312 to 314 may be configured not to be included in the notification target of the first to fourth notification display devices 201 to 204. In this case, for example, if a base value is stored in the current area 311 and the first history area 312, but not in the second history area 313 and the third history area 314, the notification target in the first to fourth notification display devices 201 to 204 will switch between the current area 311 and the first history area 312 each time the display duration elapses, and the second history area 313 and the third history area 314 will not be included in the notification target.

Furthermore, the calculation result storage area 234 is configured to store a base value expressed as a decimal to two decimal places in the current area 311, first history area 312, second history area 313, and third history area 314. However, it is not limited to this configuration, and it may also be configured to store information on the combination of the first decimal place and the second decimal place of the base value. Alternatively, it may be configured to store information on the combination of the total number of game balls dispensed to enable the calculation of the base value (K91 × "number of prize balls for winning into the general prize slot 31" + K92 × "number of prize balls for winning into the special electric prize device 32" + K93 × "number of prize balls for winning into the first operation slot 33" + K94 × "number of prize balls for winning into the second operation slot 34") and the total number of game balls discharged from the skill area PA (K91 + K92 + K93 + K94 + K95). In the former case, the information from areas 311 to 314 can be directly set in the display target setting area 276. In the latter case, a base value is calculated using the information from areas 311 to 314, and then the information of the first decimal place and the second decimal place extracted from that base value is set in the display target setting area 276.

Furthermore, the calculation result storage area 234 may be configured to include only the current area 311 and the first history area 312 as areas for storing the base value, or it may be configured to include only the current area 311, the first history area 312, and the second history area 313. Alternatively, it may be configured to include four or more areas as history areas for storing past base value information.

Furthermore, the calculation result storage area 234 is not limited to a configuration where various areas 311 to 314 are fixed in address and the base value is shifted in these various areas 311 to 314 as needed; it may also be configured so that various areas 311 to 314 are provided as a ring buffer.

Furthermore, instead of a configuration in which a base value is calculated as aspect information, a configuration in which parameters 61 to 68 are calculated, as in the 15th embodiment described above, may be used. In this case, all parameters 61 to 68 may be stored in the current area 311, the first history area 312, the second history area 313, and the third history area 314 of the calculation result storage area 234, respectively. Alternatively, some parameters may be stored, such as parameters 61 to 68 being stored in the current area 311, but only parameter 61 being stored in the first to third history areas 312 to 314.

Furthermore, the system may be configured to store, in addition to or instead of the base value, the probability of a jackpot occurring as behavioral information, or to store the probability of a high-frequency support mode occurring.

Furthermore, the trigger for the base value shift in the various areas 311 to 314 of the calculation result storage area 234 is not limited to when the total number of game balls discharged from the game area PA exceeds the shift reference number. The system may also be configured to perform a shift after a predetermined period (e.g., 8 hours), when the power supply to the main CPU 63 is stopped, when the power supply to the main CPU 63 is started, or when the setting value of the pachinko machine 10 is changed. Additionally, there may be multiple triggers for the shift.

Furthermore, the configuration is not limited to the state in which the display segments 321 and 322 in the first and second notification display devices 202 are kept illuminated until the management start flag provided in the non-specific control work area 223 is set to "1". The display segments 321 and 322 in the first and second notification display devices 202 may be configured to blink. Also, the first to fourth notification display devices 201 to 204 may be configured to repeatedly display "bL.--" → "b1.--" → "b2.--" → "b3.--" until the management start flag is set to "1".

Furthermore, until the management start flag in the non-specific control work area 223 is set to "1", a check display is not performed where the display segments 321 to 324 in each of the first to fourth notification display devices 201 to 204 illuminate. Instead, the display segments 321 and 322 in each of the first and second notification display devices 201 and 202 illuminate or blink, and the third and fourth notification display devices 203 and 204 display the current base value. This configuration may indicate that the management start flag is not set to "1".

Furthermore, if the game stop flag is set to "1" due to the power outage flag not being set to "1" or the checksum not matching, and the game is stopped, the first to fourth notification display devices 201 to 204 may be configured to illuminate each display segment 321 to 324 in the same way as the check display, or each display segment 321 to 324 may be configured to blink.

Furthermore, the display control of the first to fourth notification display devices 201 to 204 is not limited to being performed by the main CPU 63. It may also be performed by a dedicated control means, by the audio/light emission control device 81, or by the display control device 82. In this case, when the first to fourth notification display devices 201 to 204 display a base value, the base value to be notified is transmitted from the main CPU 63 to the control means acting as the primary control unit. When the first to fourth notification display devices 201 to 204 display a set value, the set value to be notified is transmitted from the main CPU 63 to the control means acting as the primary control unit. Additionally, when the main CPU 63 executes the processing for the start of power supply, information corresponding to the start of the check display is transmitted from the main CPU 63 to the control means acting as the primary control unit, so that the check display starts on the first to fourth notification display devices 201 to 204 while the power supply start processing is being executed.

<36th Embodiment>
In this embodiment, the processing configuration of the main process executed by the primary CPU 63 differs from that of the 35th embodiment. The configurations that differ from those of the 35th embodiment will be described below. Configurations that are the same as those of the 35th embodiment will generally not be described.

Figure 139 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S9401 to S9426 in the main processing are executed using a specific control program and specific control data on the main CPU 63.

Steps S9401 to S9403 execute the same processes as steps S8801 to S8803 of the main process (Figure 132) in the 35th embodiment described above. Afterward, interrupt permission is set (step S9404). This causes the first timer interrupt process (Figure 133) to be started with an interrupt at the first interrupt cycle, and the second timer interrupt process (Figure 134) to be started with an interrupt at the second interrupt cycle. However, because the startup process flag is set to "1" in step S9403, even if the first timer interrupt process is started, the processes for power outage monitoring, updating various counters, and fraud monitoring are executed, while the processes for advancing the game are not executed, and the first timer interrupt process terminates.

Subsequently, information corresponding to the initial check period (specifically, 5 seconds) is set in the check counter provided in the work area 221 for specific control (step S9405). The value set in the check counter is decremented by 1 each time the second timer interrupt process (Figure 134) is activated, similar to the 35th embodiment described above. If a value of 1 or more is set in the check counter, a check indication is displayed on the first to fourth notification display devices 201 to 204, similar to the 35th embodiment described above.

Subsequently, it is determined whether the value of the check counter is "0" (step S9406). Then, the system waits in step S9406 until the value of the check counter becomes "0". As a result, the check displays on the first to fourth notification display devices 201 to 204 continue until the initial check period set in step S9405 has elapsed.

Subsequently, steps S9407 to S9426 are executed. The processing content of steps S9407 to S9426 is identical to steps S8806 to S8825 of the main processing (Figure 132) in the 35th embodiment described above.

According to the above configuration, when power supply to the main CPU 63 begins and the processing for power supply commencement starts in the main CPU 63, a check display is shown on the first to fourth notification display devices 201 to 204, and the processing for power supply commencement is stopped until the initial check period has elapsed. This prevents setting confirmation and setting value updates from being performed during the initial check period, thereby suppressing an increase in processing load. Furthermore, it prevents gameplay from starting during the initial check period.

<Embodiment 37>
In this embodiment, the processing configuration of the main process executed by the primary CPU 63 differs from that of the 35th embodiment described above. The configurations that differ from those of the 35th embodiment will be described below. Configurations that are the same as those of the 35th embodiment will generally not be described.

Figure 140 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S9501 to S9525 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

Steps S9501 to S9518 execute the same processes as steps S7901 to S7918 of the main processing (Figure 114) in the 33rd embodiment described above. Then, information corresponding to the initial check period (specifically 5 seconds) is set in the check counter provided in the work area 221 for specific control (step S9519). The value set in the check counter is decremented by 1 each time the second timer interrupt processing (Figure 134) is activated, similar to the 35th embodiment described above. If a value of 1 or more is set in the check counter, the check display continues on the first to fourth notification display devices 201 to 204, similar to the 35th embodiment described above.

Subsequently, the processing from step S9520 onward is executed. The processing content of steps S9520 to S9525 is identical to steps S7919 to S7924 of the main processing (Figure 114) in the 33rd embodiment described above.

According to the above configuration, when power supply to the main CPU 63 begins, the initial check period starts after the power supply start processing (steps S9501 to S9518) is completed in the main CPU 63, but before the remaining processing (steps S9522 to S9525) begins. This eliminates the need to control the initial check period while the power supply start processing is being executed, thus reducing the processing load during this time.

Furthermore, while the setting confirmation process (step S9514) and the setting value update process (step S9518) are executed as processes at the start of power supply, the initial check period begins after the power supply start process is completed. This makes it possible to ensure that even if check displays are shown on the first to fourth notification display devices 201 to 204 during the initial check period, it does not affect the display of setting values using the first to fourth notification display devices 201 to 204.

Furthermore, the system may be configured so that processing from step S9520 onward does not begin until the initial check period has elapsed. In this case, it becomes possible to prevent the game from starting while the check display is being shown on the first to fourth notification display devices 201 to 204.

<38th Embodiment>
In this embodiment, the processing configuration of the normal setting process executed by the main CPU 63 differs from that of the 35th embodiment. The configurations that differ from those of the 35th embodiment will be described below. Configurations that are the same as those of the 35th embodiment will generally not be described.

Figure 141 is a flowchart showing the normal setting process in this embodiment, which is executed by the main CPU 63. Note that steps S9601 to S9605 in the normal setting process are executed using the specific control program and specific control data in the main CPU 63.

First, it is determined whether the management start flag in the non-specific control work area 223 is set to "1" (step S9601). If the management start flag is not set to "1" (step S9601: NO), the data for the check display is set in the fifth display data buffer 275 in the specific control work area 221 (step S9602). When this check display data is supplied to the display IC 266, the check display is started on the first to fourth notification display devices 201 to 204. Specifically, all display segments 321 to 324 in each of the first to fourth notification display devices 201 to 204 become illuminated. This allows the manager of the amusement hall to determine whether each display segment 321 to 324 of the first to fourth notification display devices 201 to 204 can normally become illuminated.

If the management start flag is set to "1" (step S9601: YES), the processes in steps S9603 to S9605 are executed. The processing content of steps S9603 to S9605 is the same as steps S9107 to S9109 in the normal setting process (Figure 135) in the 35th embodiment described above. Upon execution of steps S9603 to S9605, the base values stored in the various areas 311 to 314 of the calculation result storage area 234 are sequentially reported on the first to fourth notification display devices 201 to 204. Furthermore, if the base value of the current area 311 is reported immediately after the start of a new calculation period, the first and second notification display devices 201 and 202 perform an initial calculation display.

According to the above configuration, if the management start flag is not set to "1", an initial check period is triggered in which the first to fourth notification display devices 201 to 204 show a check. This makes it possible to limit the situation in which the initial check period occurs when power is supplied to the main CPU 63 to situations where the management start flag is not set to "1", such as at the shipping stage of the pachinko machine 10.

<Embodiment No. 39>
In this embodiment, the configuration regarding the set values differs from that of the 33rd embodiment described above. The configuration that differs from that of the 33rd embodiment will be described below. Configurations that are the same as those in the 33rd embodiment will generally not be described.

Figures 142(a) to 142(d) are explanatory diagrams illustrating the setting-compatible storage area 325 provided in the main ROM 64.

The setting-compatible storage area 325 contains the win/loss tables for low probability mode and high probability mode, corresponding to the setting values of the pachinko machine 10, as well as display data for setting values used to display the current setting values on the first to fourth notification display devices 201 to 204 during the setting confirmation process (Figure 115) and the setting value update process (Figure 116). More specifically, the setting-compatible storage area 325 includes a first setting information storage area 325a, a second setting information storage area 325b, a third setting information storage area 325c, a fourth setting information storage area 325d, a fifth setting information storage area 325e, and a sixth setting information storage area 325f.

Each of the first to sixth setting information storage areas 325a to 325f is provided with a storage area for storing the win/fail table for the low probability mode, which is referenced when the win/fail lottery mode is the low probability mode; a storage area for storing the win/fail table for the high probability mode, which is referenced when the win/fail lottery mode is the high probability mode; and a storage area for storing display data of the setting value, which is used to display the current setting value on the first to fourth notification display devices 201 to 204 in the setting confirmation process (Figure 115) and the setting value update process (Figure 116). In each of the first to sixth setting information storage areas 325a to 325f, a predetermined area of multiple bytes is reserved as a storage area for storing the win/fail table for the low probability mode, a predetermined area of multiple bytes is reserved as a storage area for storing the win/fail table for the high probability mode, and a 1-byte area is reserved as a storage area for storing display data of the setting value. Therefore, each of the first to sixth configuration information storage areas 325a to 325f has a storage capacity of multiple bytes. In this case, the starting address of the first configuration information storage area 325a is A(1), the starting address of the second configuration information storage area 325b is A(2), the starting address of the third configuration information storage area 325c is A(3), the starting address of the fourth configuration information storage area 325d is A(4), the starting address of the fifth configuration information storage area 325e is A(5), and the starting address of the sixth configuration information storage area 325f is A(6).

In the configuration described above, the first embodiment of the pachinko machine 10 has six setting values, "Setting 1" to "Setting 6," set as the setting values for the pachinko machine 10, similar to the embodiment described in 33 above. In this case, the probability of getting a jackpot in the low probability mode differs for each of "Setting 1" to "Setting 6," while the probability of getting a jackpot in the high probability mode is the same for all of them. Therefore, as shown in Figure 142(a), the first setting information storage area 325a stores a first low probability win/loss table LT(1) corresponding to "Setting 1" in a storage area for storing the win/loss table for the low probability mode, a common high probability win/loss table HT common to "Setting 1" to "Setting 6" is stored in a storage area for storing the win/loss table for the high probability mode, and display data for displaying "1" is stored in a storage area for storing display data for the setting value. The second setting information storage area 325b stores the second low probability win/loss table LT(2) corresponding to "Setting 2" in the storage area for storing the win/loss table for low probability mode, the common high probability win/loss table HT common to "Setting 1" to "Setting 6" in the storage area for storing the win/loss table for high probability mode, and the display data for displaying "2" in the storage area for storing display data for setting values.

The third setting information storage area 325c stores the third low probability win/loss table LT(3) corresponding to "Setting 3" in the storage area for storing the win/loss table for low probability mode, the common high probability win/loss table HT common to "Setting 1" to "Setting 6" in the storage area for storing the win/loss table for high probability mode, and display data for displaying "3" in the storage area for storing display data for setting values. The fourth setting information storage area 325d stores the fourth low probability win/loss table LT(4) corresponding to "Setting 4" in the storage area for storing the win/loss table for low probability mode, the common high probability win/loss table HT common to "Setting 1" to "Setting 6" in the storage area for storing the win/loss table for high probability mode, and display data for displaying "4" in the storage area for storing display data for setting values.

The fifth setting information storage area 325e stores the fifth low probability win/loss table LT(5) corresponding to "Setting 5" in the storage area for storing the win/loss table for low probability mode, the common high probability win/loss table HT common to "Setting 1" to "Setting 6" in the storage area for storing the win/loss table for high probability mode, and display data for displaying "5" in the storage area for storing display data for setting values. The sixth setting information storage area 325f stores the sixth low probability win/loss table LT(6) corresponding to "Setting 6" in the storage area for storing the win/loss table for low probability mode, the common high probability win/loss table HT common to "Setting 1" to "Setting 6" in the storage area for storing the win/loss table for high probability mode, and display data for displaying "6" in the storage area for storing display data for setting values.

In the configuration of the first form described above, the probability of hitting the jackpot in low-probability mode increases with higher setting values. On the other hand, the probability of hitting the jackpot in high-probability mode remains the same regardless of the setting value. Since the probability of hitting the jackpot in high-probability mode is 1/30, even at "Setting 1," the probability of hitting the jackpot in high-probability mode is higher than the probability of hitting the jackpot in low-probability mode at "Setting 6."

In the first configuration, where "Setting 1" to "Setting 6" are set as the setting values, the process of reading the win/fail table, which is executed in step S503, in order to perform the win/fail judgment process in step S504 of the special feature variation start process (Figure 13), will be described. Figure 143 is a flowchart of the win/fail table reading process. Note that the processes in steps S9701 to S9705 of the win/fail table reading process are executed using the specific control program and specific control data in the main CPU 63.

First, the value of the setting value counter located in the work area 221 for specific control in the main RAM 65 is read (step S9701). The setting value counter is used by the main CPU 63 to determine which of the first to sixth setting information storage areas 325a to 325f in the setting-corresponding storage area 325 should be referenced when reading the success/failure table and when reading the display data of the setting value.

Subsequently, from the first to sixth setting information storage areas 325a to 325f in the setting-compatible storage area 325, the storage area corresponding to the value of the setting value counter read in step S9701 is selected (step S9702). The setting value counter is configured to take one of the values "1" to "6," similar to the 33rd embodiment described above. If the setting value counter is "1," the first setting information storage area 325a is selected; if the setting value counter is "2," the second setting information storage area 325b is selected; if the setting value counter is "3," the third setting information storage area 325c is selected; if the setting value counter is "4," the fourth setting information storage area 325d is selected; if the setting value counter is "5," the fifth setting information storage area 325e is selected; and if the setting value counter is "6," the sixth setting information storage area 325f is selected.

In making this selection, a correspondence table pre-stored in the main ROM 64 is referenced. This correspondence table defines the correspondence between the value of the setting value counter and the starting addresses of the first to sixth setting information storage areas 325a to 325f. Specifically, A(1), which is the starting address of the first setting information storage area 325a, is set to correspond to the value of "1" in the setting value counter; A(2), which is the starting address of the second setting information storage area 325b, is set to correspond to the value of "2" in the setting value counter; A(3), which is the starting address of the third setting information storage area 325c, is set to correspond to the value of "3" in the setting value counter; A(4), which is the starting address of the fourth setting information storage area 325d, is set to correspond to the value of "4" in the setting value counter; A(5), which is the starting address of the fifth setting information storage area 325e, is set to correspond to the value of "5" in the setting value counter; and A(6), which is the starting address of the sixth setting information storage area 325f, is set to correspond to the value of "6" in the setting value counter.

Subsequently, if the current win/loss lottery mode is the low probability mode (step S9703: NO), the win/loss table for the low probability mode is read from the setting information storage areas 325a to 325f selected in step S9702 (step S9704). On the other hand, if the current win/loss lottery mode is the high probability mode (step S9703: YES), the win/loss table for the high probability mode is read from the setting information storage areas 325a to 325f selected in step S9702 (step S9705).

As described above, when the read operation of the win/loss table is performed, the win/loss table corresponding to the current win/loss lottery mode is read from the setting information storage areas 325a to 325f, which correspond to the values of the setting value counters. Then, in the win/loss determination process (step S504) of the special symbol variation start process (Figure 13), the read win/loss table is used to determine whether the current game round corresponds to a jackpot result.

Next, we will explain the process when the second timer interrupt process (Figure 123) is triggered while the setting value update process (step S7918) is being executed in the main process (Figure 114) of the main CPU 63. In this case, the second timer interrupt process (Figure 123) executes the setting process for the fifth display data buffer 275 during the setting value update (step S8403). Figure 144 is a flowchart showing the setting process for the fifth display data buffer 275 during the setting update. Note that the processing in steps S9801 to S9805 in this setting process is executed using the specific control program and specific control data in the main CPU 63.

First, the value of the setting value counter provided in the work area 221 for specific control in the main RAM 65 is read (step S9801). Then, from the first to sixth setting information storage areas 325a to 325f in the setting-corresponding storage area 325, the storage area corresponding to the value of the setting value counter read in step S9801 is selected (step S9802). The setting value counter is configured to take one of the values from "1" to "6" as in the 33rd embodiment described above. If the value of the setting value counter is "1", the first setting information storage area 325a is selected; if the value of the setting value counter is "2", the second setting information storage area 325b is selected; if the value of the setting value counter is "3", the third setting information storage area 325c is selected; if the value of the setting value counter is "4", the fourth setting information storage area 325d is selected; if the value of the setting value counter is "5", the fifth setting information storage area 325e is selected; and if the value of the setting value counter is "6", the sixth setting information storage area 325f is selected. In this selection process, a correspondence table pre-stored in the main ROM 64 is referenced, similar to the read operation of the correct/incorrect table (Figure 143).

Subsequently, the display data of the setting values is read from the setting information storage areas 325a to 325f selected in step S9802 (step S9803). Then, the read display data of the setting values is set in the fifth display data buffer 275 in the specific control work area 221 as display data for application to the fourth notification display device 204 (step S9804). Furthermore, display data for displaying an indication on the first to third notification display devices 201 to 203 that the setting values of the pachinko machine 10 are being updated is set in the fifth display data buffer 275 (step S9805).

As described above, the setting process for the fifth display data buffer 275 is executed during the setting update. Therefore, in step S9805, the display corresponding to the display data set in the fifth display data buffer 275 is displayed on the first to third notification display devices 201 to 203, and in step S9804, the display corresponding to the display data set in the fifth display data buffer 275 is displayed on the fourth notification display device 204. As a result, for example, as shown in the explanatory diagram in Figure 124(a), the first to fourth notification display devices 201 to 204 display an indication that the settings of the pachinko machine 10 are being updated, and a display indicating the current settings of the pachinko machine 10 are shown.

Furthermore, in the setting confirmation process (step S7914) of the main processing (Figure 114) on the main CPU 63, when the second timer interrupt process (Figure 123) is interrupted and activated, the setting process for the fifth display data buffer 275 during setting confirmation (step S8405) is executed in the same way as the setting process for the fifth display data buffer 275 during setting update (Figure 144) regarding the setting of the display data of the setting value.

In the first form of the pachinko machine 10, six setting levels, from "Setting 1" to "Setting 6," were available. However, depending on the model and type of pachinko machine 10, fewer than six setting levels may be used. Specifically, in the second form of the pachinko machine 10 shown in the explanatory diagram of Figure 142(b), three setting levels, "Setting 1," "Setting 3," and "Setting 6," are available. In the third form of the pachinko machine 10 shown in the explanatory diagram of Figure 142(c), four setting levels, "Setting 1," "Setting 2," "Setting 3," and "Setting 4," are available. In the fourth form of the pachinko machine 10 shown in the explanatory diagram of Figure 142(d), only one setting level, "Setting 1," is available. In this case, regardless of whether it is the second to fourth form of the pachinko machine 10, a setting-compatible storage area 325 is used, which has first to sixth setting information storage areas 325a to 325f that enable the setting of six levels of setting values, just like the first form of the pachinko machine 10.

In the case where the setting-dependent storage area 325 is used in the second form of the pachinko machine 10, as shown in the explanatory diagram in Figure 142(b), various information corresponding to "Setting 1" is stored in the first setting information storage area 325a and the fourth setting information storage area 325d. Specifically, the first setting information storage area 325a and the fourth setting information storage area 325d store the first low-probability win/loss table LT(1) corresponding to "Setting 1" in the storage area for storing the win/loss table for the low-probability mode, the first high-probability win/loss table HT(1) corresponding to "Setting 1" in the storage area for storing the win/loss table for the high-probability mode, and display data for displaying "1" in the storage area for storing display data for the setting value.

The second setting information storage area 325b and the fifth setting information storage area 325e store various information corresponding to "Setting 3". Specifically, the second setting information storage area 325b and the fifth setting information storage area 325e store the third low probability win/loss table LT(3) corresponding to "Setting 3" in the storage area for storing the win/loss table for low probability mode, the third high probability win/loss table HT(3) corresponding to "Setting 3" in the storage area for storing the win/loss table for high probability mode, and display data for displaying "3" in the storage area for storing display data for setting values.

The third setting information storage area 325c and the sixth setting information storage area 325f store various information corresponding to "Setting 6". Specifically, the third setting information storage area 325c and the sixth setting information storage area 325f store the sixth low probability win/loss table LT(6) corresponding to "Setting 6" in the storage area for storing the win/loss table for low probability mode, the sixth high probability win/loss table HT(6) corresponding to "Setting 6" in the storage area for storing the win/loss table for high probability mode, and display data for displaying "6" in the storage area for storing display data for setting values.

In the configuration of the second form described above, even in a configuration where a setting-corresponding storage area 325 having the first to sixth setting information storage areas 325a to 325f is used, the number of setting values is set to fewer than the six values of these first to sixth setting information storage areas 325a to 325f. Furthermore, the probability of a jackpot in low-probability mode increases with higher setting values, and the probability of a jackpot in high-probability mode also increases with higher setting values. Note that the jackpot probability in high-probability mode at "Setting 1" is higher than the jackpot probability in low-probability mode at "Setting 6".

In the configuration of the second form described above, during the read operation of the success/failure table (Figure 143), the success/failure table corresponding to "Setting 1" is read regardless of whether the value of the setting value counter is "1" or "4". The success/failure table corresponding to "Setting 3" is read regardless of whether the value of the setting value counter is "2" or "5". The success/failure table corresponding to "Setting 6" is read regardless of whether the value of the setting value counter is "3" or "6".

In the read operation of the success/failure table (Figure 143), the success/failure table is read from the setting information storage area 325 corresponding to the value of the setting value counter, regardless of the number of setting levels. This makes it possible to use the same processing configuration for the read operation of the success/failure table (Figure 143) as when six setting levels are set, even when three setting levels are configured.

In the configuration of the second form described above, when a setting-compatible storage area 325 capable of setting six levels of values is used, three levels of settings are set. Therefore, the number of levels of settings that can be set in the setting-compatible storage area 325 can be divided by the number of levels of the setting value to be used. In other words, the number of levels of the setting value to be used is a divisor of the maximum number of levels of settings that can be set in the setting-compatible storage area 325, and is a different number from the maximum number of levels. In this case, the same number of setting information storage areas 325a to 325f are allocated to each of the setting values to be used, and the setting values are assigned to the first to sixth setting information storage areas 325a to 325f in such a way that a group is formed when one of the three-level setting values is arranged in ascending order. As a result, in the setting value update process (Figure 116), if the reset button 68c is repeatedly operated while the setting value counter is at "1", the setting values displayed on the first to fourth notification display devices 201 to 204 will change in the order of "1" → "3" → "6" → "1" → "3" → "6" → "1" → ... In other words, each operation of the reset button 68c changes the displayed setting value, and if one display cycle is defined as the display of each configurable setting value once, a certain pattern of display cycles will be repeated. Therefore, the setting value update operation becomes easier.

During the setting update process for the fifth display data buffer 275 (Figure 144), regardless of the number of setting levels, the display data of the setting value is read from the setting information storage area 325 corresponding to the value of the setting value counter. This makes it possible to use the same processing configuration for the setting process (Figure 144) as when six setting levels are set, even when three levels of setting values are configured.

Furthermore, in the second form of the pachinko machine 10, various information corresponding to "Setting 1" may be stored in the first setting information storage area 325a and the second setting information storage area 325b, various information corresponding to "Setting 3" may be stored in the third setting information storage area 325c and the fourth setting information storage area 325d, and various information corresponding to "Setting 6" may be stored in the fifth setting information storage area 325e and the sixth setting information storage area 325f. In other words, the same number of setting information storage areas 325a to 325f may be assigned to each setting value to be used, and the same setting value may be set in consecutive setting information storage areas 325a to 325f in relation to the value of the setting value counter. In this case, if the reset button 68c is repeatedly pressed during the setting value update process (Figure 116) while the setting value counter is at "1", the setting values displayed on the first to fourth notification display devices 201 to 204 will change in the following order: "1" → "1" → "3" → "3" → "6" → "6" → "1" → ...

In the third form of the pachinko machine 10, when the setting-dependent storage area 325 is used, as shown in the explanatory diagram in Figure 142(c), various information corresponding to "Setting 1" is stored in the first setting information storage area 325a and the second setting information storage area 325b. Specifically, the first setting information storage area 325a and the second setting information storage area 325b store the first low-probability win/loss table LT(1) corresponding to "Setting 1" in the storage area for storing the win/loss table of the low-probability mode, the common high-probability win/loss table HT common to "Setting 1" to "Setting 6" in the storage area for storing the win/loss table of the high-probability mode, and the display data for displaying "1" in the storage area for storing the display data of the setting value.

The third setting information storage area 325c and the fourth setting information storage area 325d store various information corresponding to "Setting 2". Specifically, the third setting information storage area 325c and the fourth setting information storage area 325d store the second low probability win/loss table LT(2) corresponding to "Setting 2" in the storage area for storing the win/loss table for low probability mode, the common high probability win/loss table HT common to "Setting 1" through "Setting 6" in the storage area for storing the win/loss table for high probability mode, and the display data for displaying "2" in the storage area for storing display data for setting values.

The fifth setting information storage area 325e stores various information corresponding to "Setting 3". Specifically, the fifth setting information storage area 325e stores the third low probability win/loss table LT(3) corresponding to "Setting 3" in the storage area for storing the win/loss table for low probability mode, the common high probability win/loss table HT common to "Setting 1" through "Setting 6" in the storage area for storing the win/loss table for high probability mode, and the display data for displaying "3" in the storage area for storing display data for setting values.

The sixth setting information storage area 325f stores various information corresponding to "Setting 4". Specifically, the sixth setting information storage area 325f stores the fourth low probability win/loss table LT (4) corresponding to "Setting 4" in the storage area for storing the win/loss table of the low probability mode, the common high probability win/loss table HT common to "Setting 1" through "Setting 6" in the storage area for storing the win/loss table of the high probability mode, and the display data for displaying "4" in the storage area for storing the display data of the setting value.

In the configuration of the third form described above, even if a setting-corresponding storage area 325 having the first to sixth setting information storage areas 325a to 325f is used, the number of setting values is set to fewer than the six values of these first to sixth setting information storage areas 325a to 325f. Furthermore, the probability of a jackpot in low-probability mode increases with higher setting values, while the probability of a jackpot in high-probability mode remains the same regardless of the setting value. Since the probability of a jackpot in high-probability mode is 1/30, even with "Setting 1," the probability of a jackpot in high-probability mode is higher than the jackpot probability in low-probability mode with "Setting 4."

In the configuration of the third form described above, during the read operation of the success/failure table (Figure 143), the success/failure table corresponding to "Setting 1" is read regardless of whether the value of the setting value counter is "1" or "2". The success/failure table corresponding to "Setting 2" is read regardless of whether the value of the setting value counter is "3" or "4". The success/failure table corresponding to "Setting 3" is read when the value of the setting value counter is "5", and the success/failure table corresponding to "Setting 4" is read when the value of the setting value counter is "6".

In the read operation of the success/failure table (Figure 143), the success/failure table is read from the setting information storage area 325 corresponding to the value of the setting value counter, regardless of the number of setting levels. This makes it possible to use the same processing configuration for the read operation of the success/failure table (Figure 143) as when six setting levels are set, even when four setting levels are configured.

In the configuration of the third form described above, when the setting-compatible storage area 325, which can be set to six setting values, is used, four setting values are set. Therefore, the number of setting value levels that can be set in the setting-compatible storage area 325 cannot be divided evenly by the number of setting value levels to be used. In this case, two consecutive setting information storage areas 325a to 325d are assigned to "Setting 1" and "Setting 2" respectively, in relation to the value of the setting value counter, while one setting information storage area 325e and 325f are assigned to "Setting 3" and "Setting 4" respectively. As a result, if the reset button 68c is repeatedly operated when the setting value counter value is "1" during the setting value update process (Figure 116), the setting values displayed on the first to fourth notification display devices 201 to 204 will change in the order of "1" → "1" → "2" → "2" → "3" → "4" → "1" → ...

During the setting update process for the fifth display data buffer 275 (Figure 144), the display data of the setting value is read from the setting information storage area 325 corresponding to the value of the setting value counter, regardless of the number of setting levels. This makes it possible to use the same processing configuration for the setting process (Figure 144) as when six setting levels are set, even when four levels of setting values are configured.

Furthermore, in order to change the display of the setting value on the first to fourth notification display devices 201 to 204 for each operation of the reset button 68c during the setting value update process (Figure 116), it is preferable that various information corresponding to the same setting value is not set in consecutive setting information storage areas 325a to 325f in relation to the value of the setting value counter. For example, a configuration in which various information corresponding to "Setting 1" is set in the first setting information storage area 325a, various information corresponding to "Setting 2" is set in the second setting information storage area 325b, various information corresponding to "Setting 3" is set in the third setting information storage area 325c, various information corresponding to "Setting 4" is set in the fourth setting information storage area 325d, various information corresponding to "Setting 1" is set in the fifth setting information storage area 325e, and various information corresponding to "Setting 2" is set in the sixth setting information storage area 325f is set. In this case, if the reset button 68c is repeatedly pressed during the setting value update process (Figure 116) while the setting value counter is at "1", the setting values displayed on the first to fourth notification display devices 201 to 204 will change in the following order: "1" → "2" → "3" → "4" → "1" → "2" → "1" → ...

In the fourth form of the pachinko machine 10, when the setting-dependent memory area 325 is used, as shown in the explanatory diagram in Figure 142(d), various information corresponding to "Setting 1" is stored in all of the first to sixth setting information memory areas 325a to 325f. Specifically, in the first to sixth setting information memory areas 325a to 325f, the first low-probability win/loss table LT(1) corresponding to "Setting 1" is stored in the memory area for storing the win/loss table for the low-probability mode, the common high-probability win/loss table HT common to "Setting 1" to "Setting 6" is stored in the memory area for storing the win/loss table for the high-probability mode, and the display data for displaying "1" is stored in the memory area for storing the display data of the setting value.

In the configuration of the fourth embodiment described above, even if a configuration is used in which a setting-corresponding storage area 325 having the first to sixth setting information storage areas 325a to 325f is used, only one type of setting value is set. Even in this configuration where only one type of setting value is set, the pass/fail table reading process (Figure 143) reads the pass/fail table from the setting information storage area 325 corresponding to the value of the setting value counter. This makes it possible to use the same processing configuration for the pass/fail table reading process (Figure 143) as when six levels of setting values are set, even when only one type of setting value is set.

In the configuration of the fourth form described above, there is no need to set a setting value, so basically there is no need to perform the setting value update process (Figure 116). However, if an abnormality occurs in the setting value, the setting value update process (Figure 116) may be performed. In this case, "Setting 1" is assigned to all of the first to sixth setting information storage areas 325a to 325f. Therefore, if the reset button 68c is repeatedly operated while the setting value counter value is "1" during the setting value update process (Figure 116), the setting values displayed on the first to fourth notification display devices 201 to 204 will continuously display "1" in the following order: "1" → "1" → "1" → "1" → "1" → "1" → "1" → ...

During the setting update process for the fifth display data buffer 275 (Figure 144), regardless of the number of setting value levels, the display data for the setting value is read from the setting information storage area 325 corresponding to the value of the setting value counter. This makes it possible to use the same processing configuration for the setting process (Figure 144) as when six setting values are set, even when only one type of setting value is set.

The embodiment described in detail above provides the following excellent effects.

Since the configuration allows for the selection of a setting value from multiple levels corresponding to the player's advantage, players expect the most advantageous setting value to be selected. In this case, in the second to fourth forms of the pachinko machine 10, while there are a first predetermined number (specifically six) of setting information storage areas 325a to 325f for storing win/loss tables corresponding to the setting values, the number of types of setting values to be used is less than the first predetermined number. This makes it possible to standardize the configuration of the setting-corresponding storage area 325 with the first form of the pachinko machine 10, where the number of types of setting values to be used is the first predetermined number, and simplifies the design work of the pachinko machine 10 when changing the number of types of setting values.

In the setting value update process (step S7918), each time the reset button 68c is operated, the numerical information of the setting value counter provided in the work area 221 for specific control is changed, thereby changing the setting value to be used. The correct/incorrect tables in the setting information storage areas 325a to 325f corresponding to the changed numerical information are used in the correct/incorrect judgment process, so that the correct/incorrect judgment process is executed in a manner corresponding to the setting value to be used. In this case, each correct/incorrect table for the setting value that can be set is stored in at least one setting information storage area 325a to 325f, and the same correct/incorrect table is stored in multiple setting information storage areas 325a to 325f, which are part of the first predetermined number. As a result, correct/incorrect tables are stored in all of the first predetermined number of setting information storage areas 325a to 325f. This makes it possible to use the first predetermined number of setting information storage areas 325a to 325f as they are, and to use the same configuration that uses the setting value counter to determine the setting value to be used, while keeping the number of types of setting values to be used smaller than the first predetermined number.

This configuration reads the pass/fail table from the setting information storage areas 325a to 325f corresponding to the numerical information of the setting value counter, and then uses the read pass/fail table to perform the pass/fail determination process. This allows the configuration for reading the pass/fail table to be used in the pass/fail determination process to be utilized even if the number of types of setting values used is less than the first predetermined number.

In the situation where the setting value update process (step S7918) is executed, the display data of the setting value is read from the setting information storage areas 325a to 325f corresponding to the numerical information of the setting value counter, and the display corresponding to the read setting value display data is displayed on the fourth notification display device 204. This allows the configuration for reading the setting value display data to be used to be used when displaying the setting value, even if the number of types of setting values to be used is less than the first predetermined number.

The number of levels in the setting value to be used is a divisor of the maximum number of levels in the setting-compatible storage area 325 that can be set, and is different from the maximum number of levels. In this case, the same number of setting information storage areas 325a to 325f are allocated to each of the setting values to be used, and the setting values are assigned to the first to sixth setting information storage areas 325a to 325f in such a way that a group is formed when three setting values arranged one by one in ascending order is considered one group. As a result, when the reset button 68c is repeatedly operated while the setting value counter value is "1" during the setting value update process (Figure 116), the setting values displayed on the first to fourth notification display devices 201 to 204 will change in the order of "1" → "3" → "6" → "1" → "3" → "6" → "1" → ... In other words, each operation of the reset button 68c changes the displayed setting value, and if we consider the display of each configurable setting value once as one display cycle, a certain pattern of display cycles is repeated. Therefore, updating the setting value becomes easier.

Furthermore, in configurations where the win/loss table for high probability mode does not change according to the setting value, the win/loss table for high probability mode may be stored in a different storage area in the main ROM 64 than the setting-corresponding storage area 325, rather than being stored in the first to sixth setting information storage areas 325a to 325f of the setting-corresponding storage area 325.

Furthermore, if there is only one setting value to be used, the correct/incorrect table corresponding to that setting value may be set in only one setting information storage area 325a to 325f, and the remaining setting information storage areas 325a to 325f may not have correct/incorrect tables set. Also, if there are multiple settings values to be used, but the number of these settings is less than the number of settings in the first to sixth setting information storage areas 325a to 325f, the correct/incorrect tables corresponding to each of these settings may be set in only the corresponding setting information storage area 325a to 325f, and the remaining setting information storage areas 325a to 325f may not have correct/incorrect tables set. In this configuration, by making the numerical information corresponding to the setting information storage areas 325a to 325 where no correct/incorrect tables are set numerical information that cannot be selected by the setting value counter, it becomes possible to prevent the setting information storage areas 325a to 325f where no correct/incorrect tables are set from being selected when reading the correct/incorrect tables or reading the display data of the setting values.

<40th Embodiment>
In the 39th embodiment described above, a setting-compatible storage area 325 capable of setting six levels of values was used, but in this embodiment, a setting-compatible storage area 326 capable of setting three levels of values was used.

Figures 145(a) to 145(c) are explanatory diagrams illustrating the setting-corresponding storage area 326 pre-stored in the main ROM 64.

The setting-compatible storage area 326 includes a first setting information storage area 326a, a second setting information storage area 326b, and a third setting information storage area 326c. In the first embodiment of the pachinko machine 10 shown in Figure 145(a), various information corresponding to "Setting 1" is set in the first setting information storage area 326a, various information corresponding to "Setting 2" is set in the second setting information storage area 326b, and various information corresponding to "Setting 3" is set in the third setting information storage area 326c. In other words, in the first embodiment of the pachinko machine 10, the maximum number of setting values that can be set are stored in the setting-compatible storage area 326.

In the second form of the pachinko machine 10 shown in Figure 145(b), various information corresponding to "Setting 1" is set in all of the first to third setting information storage areas 326a to 326c. In other words, in the second form of the pachinko machine 10, only one type of setting value is set, even though the setting-compatible storage area 326, which can accommodate three setting levels, is utilized.

In the third form of the pachinko machine 10 shown in Figure 145(c), various information corresponding to "Setting 1" is set in the first setting information storage area 326a and the second setting information storage area 326b, and various information corresponding to "Setting 3" is set in the third setting information storage area 326c. In other words, the third form of the pachinko machine 10 utilizes the setting-compatible storage area 326, which is capable of setting three levels of settings, to set two levels of settings.

According to the above configuration, the setting-compatible storage area 326, which allows for setting three levels of values, can be directly reused for the second and third forms of the pachinko machine 10, which use fewer setting levels than three. Furthermore, similar to the 39th embodiment described above, the processing configuration for reading the win/loss table (Figure 143) and the processing configuration for setting the fifth display data buffer 275 during setting updates (Figure 144) can be commonly used in the first to third forms of the pachinko machine 10.

<41st Embodiment>
This embodiment differs from the 33rd embodiment in that when a setting confirmation process (step S7914) or a setting value update process (step S7918) is executed in the main processing (Figure 114) of the main CPU 63, a predetermined notification is executed on a display unit visible from the front of the pachinko machine 10. The configurations that differ from the 33rd embodiment will be described below. Configurations that are the same as those in the 33rd embodiment will generally not be described.

Figure 146(a) is an explanatory diagram illustrating various display units located in an area visible from the front of the pachinko machine 10 through a window panel 52 that forms the front of the pachinko machine 10.

Various display units are provided, including a special feature display unit 37a, a special feature hold display unit 37b, a general feature display unit 38a, and a general feature hold display unit 38b. These functions are the same as those of the first embodiment described above. The special feature display unit 37a and the general feature display unit 38a are arranged side-by-side, and a round display unit 330 is provided side-by-side with respect to these special feature display unit 37a and general feature display unit 38a.

The round display unit 330, like the special drawing display unit 37a and the general drawing display unit 38a, has seven display segments 331 to 337. The seven display segments 331 to 337 are all rod-shaped light-emitting regions of the same shape and size, and are arranged to form the shape of the number "8". The seven display segments 331 to 337 are individually controlled for illumination.

The round display unit 330 notifies the number of round games that occur in the opening/closing execution mode triggered by a jackpot result. In this embodiment, when a jackpot is won in the win/failure determination process, there are two possible jackpot results: a first jackpot result that triggers a transition to an opening/closing execution mode with a relatively small number of round games, and a second jackpot result that triggers a transition to an opening/closing execution mode with a relatively large number of round games. Specifically, in the opening/closing execution mode triggered by the first jackpot result, two round games are executed, and in the opening/closing execution mode triggered by the second jackpot result, sixteen round games are executed.

Furthermore, the first jackpot result includes two possibilities: one where, after the opening/closing execution mode ends, the win/fail lottery mode becomes a low-probability mode and the support mode becomes a low-frequency support mode; and another where, after the opening/closing execution mode ends, the win/fail lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode. Similarly, the second jackpot result also includes two possibilities: one where, after the opening/closing execution mode ends, the win/fail lottery mode becomes a low-probability mode and the support mode becomes a low-frequency support mode; and another where, after the opening/closing execution mode ends, the win/fail lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode.

Figure 146(b) is an explanatory diagram illustrating the display content of the round display unit 330.

When the opening/closing execution mode is initiated by any jackpot result, the round display unit 330 changes from a non-display state, where all display segments 331-337 are off, to a display state, where at least some of the display segments 331-337 are illuminated. While the opening/closing execution mode continues, the display content shown on the round display unit 330 at the start of the mode is maintained. When the opening/closing execution mode ends, the round display unit 330 changes from a display state to a non-display state.

In the opening/closing execution mode, where two rounds of gameplay are performed, as shown in Figure 146(b), the first to fourth display segments 331 to 334 of the round display unit 330 are turned off, and the fifth to seventh display segments 335 to 337 are turned on. In the opening/closing execution mode, where sixteen rounds of gameplay are performed, as shown in Figure 146(b), the first to fourth display segments 331 to 334 of the round display unit 330 are turned on, and the fifth to seventh display segments 335 to 337 are turned off. This allows the manager of the gaming hall to determine which type of opening/closing execution mode is being performed on the pachinko machine 10 by checking the round display unit 330.

When the setting value update process (step S7918) is executed in the main processing (Figure 114) of the main CPU 63, the round display unit 330 displays the corresponding information. Specifically, when the setting value update process (step S7918) is executed, as shown in Figure 146(b), the first display segment 331, the third display segment 333, the fifth display segment 335, and the seventh display segment 337 of the round display unit 330 are turned off, and the second display segment 332, the fourth display segment 334, and the sixth display segment 336 are turned on.

The display on the round display unit 330 corresponding to the setting value update process (step S7918) starts when the setting value update process (step S7918) begins and ends when the setting value update process (step S7918) ends. This display content differs from the display content shown on the round display unit 330 when the opening/closing execution mode is executed, and also differs from the display content shown on the round display unit 330 when the setting confirmation process (step S7914), described later, is executed. This allows the manager of the gaming hall to easily determine whether or not the setting value update process (step S7918) is being executed by checking the round display unit 330. Furthermore, this determination can be made using the round display unit 330.

If the setting confirmation process (step S7914) is executed in the main processing (Figure 114) of the main CPU 63, the round display unit 330 will display the corresponding information. Specifically, when the setting confirmation process (step S7914) is executed, as shown in Figure 146(b), the first display segment 331, the third display segment 333, the fifth display segment 335, and the seventh display segment 337 of the round display unit 330 will be lit, while the second display segment 332, the fourth display segment 334, and the sixth display segment 336 will be off.

The display on the round display unit 330 corresponding to the setting confirmation process (step S7914) starts when the setting confirmation process (step S7914) is initiated and ends when the setting confirmation process (step S7914) is completed. This display content differs from the display content shown on the round display unit 330 when the opening/closing execution mode is executed, and also differs from the display content shown on the round display unit 330 when the setting value update process (step S7918) is executed. This allows the manager of the gaming hall to easily determine whether the setting confirmation process (step S7914) is being executed by checking the round display unit 330. Furthermore, this determination can be made using the round display unit 330.

In the main process (Figure 114), when the setting confirmation process (step S7914) and the setting value update process (step S7918) are executed, the process for advancing the game is not executed. Therefore, the setting confirmation process (step S7914) and the setting value update process (step S7918) are not executed when the opening/closing execution mode is in operation. Furthermore, when one of the setting confirmation process (step S7914) or the setting value update process (step S7918) is executed, the other is not executed. Therefore, even if the round display unit 330 is used as a display unit for each of these displays, the situations requiring each display will not overlap.

Furthermore, the display content of the round display unit 330 is not limited to the above-described content. Any display content is acceptable as long as it allows for distinction between the different situations. For example, one of the display corresponding to the setting confirmation process (step S7914) and the setting value update process (step S7918) may be configured so that all of the first to seventh display segments 331 to 337 are illuminated. Alternatively, one of the display corresponding to the setting confirmation process (step S7914) and the setting value update process (step S7918) may be configured so that all of the first to seventh display segments 331 to 337 are illuminated and maintained in that state, while the other may be configured so that all of the first to seventh display segments 331 to 337 are blinking.

Furthermore, instead of the configuration in which the round display unit 330 displays information corresponding to the setting confirmation process and the setting value update process, the special drawing display unit 37a may be used to display these information, or the general drawing display unit 38a may be used to display these information. Alternatively, the display unit may be configured such that the display corresponding to the setting confirmation process is displayed in one of the special drawing display unit 37a, the general drawing display unit 38a, or the round display unit 330, and the display corresponding to the setting value update process is displayed in the other display unit.

Furthermore, in a configuration where the reserved information acquired based on the entry of a game ball into the first operation port 33 and the reserved information acquired based on the entry of a game ball into the second operation port 34 are stored separately, and the special display unit 37a includes a first special display unit that executes a game round triggered by the reserved information corresponding to the first operation port 33, and a second special display unit that executes a game round triggered by the reserved information corresponding to the second operation port 34, the first special display unit may be configured to display a display corresponding to the setting confirmation process and a display corresponding to the setting value update process, or the second special display unit may be configured to display a display corresponding to the setting confirmation process and a display corresponding to the setting value update process, or the first special display unit may be configured to display a display corresponding to the setting confirmation process and the second special display unit may be configured to display a display corresponding to the setting value update process.

Furthermore, the system may be configured to include a dedicated display unit for indicating that a setting confirmation process is being executed, or a dedicated display unit for indicating that a setting value update process is being executed, or a dedicated display unit for indicating that either a setting confirmation process or a setting value update process is being executed. In this case, the dedicated display unit may be controlled by the main CPU 63, or it may be controlled by the sound and light emission control device 81 or the display control device 82.

<Embodiment 42>
In this embodiment, the processing configuration of the main processing and the first timer interrupt processing differs from that of the 33rd embodiment described above. The configurations that differ from those of the 33rd embodiment will be described below. Configurations that are the same as those of the 33rd embodiment will generally not be described.

Figure 147 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S9901 to S9923 in the main processing are executed using a specific control program and specific control data on the main CPU 63.

First, the power-on initial setup process is executed (step S9901). During this process, for example, after the main process starts, the system waits for a predetermined waiting period (specifically, 1 second) before proceeding to the next process. During this predetermined waiting period, the operation and initial setup of the graphic display device 41 are completed. Access to the main RAM 65 is also permitted.

Subsequently, the internal function register setting process is executed (step S9902). In the internal function register setting process, similar to step S7902 of the main process (Figure 114) in the 33rd embodiment described above, the interrupt period of the first timer interrupt process (Figure 148), which is a process that periodically interrupts and is initiated from the main process, is set to the first interrupt period (specifically, 4 milliseconds). At the same time, the interrupt period of the second timer interrupt process (Figure 123), which is a process that periodically interrupts and is initiated from the main process, is set to the second interrupt period (specifically, 2 milliseconds), which is a shorter period than the first interrupt period.

Subsequently, the interrupt enable setting is configured for the second timer interrupt handler (Figure 123) (step S9903). This causes the second timer interrupt handler (Figure 123) to be activated by an interrupt during the second interrupt cycle. On the other hand, the interrupt enable setting is not configured for the first timer interrupt handler (Figure 148). As a result, the first timer interrupt handler (Figure 148) remains in an interrupt-disabled state.

Subsequently, steps S9904 to S9917 are executed. The processing content of steps S9904 to S9917 is identical to steps S7905 to S7918 of the main processing (Figure 114) in the 33rd embodiment described above.

After completing steps S9904 to S9917, the interrupt enable setting for the first timer interrupt process (Figure 148) is performed (step S9918). This causes the first timer interrupt process (Figure 148) to be activated by an interrupt at the first interrupt cycle. In other words, the first timer interrupt process (Figure 117) is activated by an interrupt at the first interrupt cycle, and the second timer interrupt process (Figure 123) is activated by an interrupt at the second interrupt cycle. Subsequently, steps S9919 to S9923 execute the same process as steps S7920 to S7924 of the main process (Figure 114) in the 33rd embodiment described above.

Figure 148 is a flowchart showing the first timer interrupt processing in this embodiment, which is executed by the main CPU 63. As previously explained, the first timer interrupt processing is activated periodically at a 4-millisecond interval, which is the first interrupt period. Furthermore, the program corresponding to the first timer interrupt processing is set as a specific control program.

First, interrupt disabling is performed (step SA101) to prevent the occurrence of the first timer interrupt process (Figure 148) and the second timer interrupt process (Figure 123). By disabling the occurrence of the first timer interrupt process (Figure 148), it becomes possible to prevent the first timer interrupt process (Figure 148) from being triggered repeatedly, even if the first interrupt cycle has elapsed during the execution of the first timer interrupt process (Figure 148). Similarly, by disabling the occurrence of the second timer interrupt process (Figure 123), it becomes possible to prevent the second timer interrupt process (Figure 123) from interrupting and triggering the first timer interrupt process (Figure 148) even if the second interrupt cycle has elapsed.

Subsequently, steps SA102 to SA121 execute the same process as steps S8202 to S8221 of the first timer interrupt processing (Figure 117) in the 33rd embodiment described above. If a positive determination is made in step SA107, or if the process in step SA121 is executed, interrupt permission is set (step SA122) to allow the first timer interrupt processing (Figure 148) and the second timer interrupt processing (Figure 123) to occur.

According to the above configuration, when the power supply start process is being executed in the main process (Figure 147), the interrupt of the second timer interrupt process (Figure 123) is permitted, while the interrupt of the first timer interrupt process (Figure 148) is not permitted. This allows the display control of the first to fourth notification display devices 201 to 204 by the second timer interrupt process (Figure 123) to be performed even when the power supply start process is being executed, while preventing the execution of the process for controlling the progress of the game by the first timer interrupt process (Figure 148).

Furthermore, the first timer interrupt handler (Figure 148) does not interrupt the second timer interrupt handler (Figure 123), and the second timer interrupt handler (Figure 123) does not interrupt the first timer interrupt handler (Figure 148). This prevents the timer interrupt handlers from being triggered redundantly.

<Embodiment 43>
In this embodiment, the configuration for displaying the base value in the first to fourth notification display devices 201 to 204 differs from that of the 35th embodiment. The configurations that differ from those of the 35th embodiment will be described below. Configurations that are the same as those of the 35th embodiment will generally not be described.

In this embodiment as well, similar to the 35th embodiment described above, a normal counter area 231 is provided in the work area 223 for non-specific control. The normal counter area 231 is provided with a normal general prize counter 231a, a normal special electric prize counter 231b, a normal first operation counter 231c, a normal second operation counter 231d, and a normal out counter 231e, similar to the 15th embodiment described above. In situations where neither the opening/closing execution mode based on a jackpot result nor the high-frequency support mode is active, if one game ball enters the general prize entry port 31, the value of the normal general prize entry counter 231a is increased by 1; if one game ball enters the special electric prize entry device 32, the value of the normal special electric prize entry counter 231b is increased by 1; if one game ball enters the first operation port 33, the value of the normal first operation counter 231c is increased by 1; if one game ball enters the second operation port 34, the value of the normal second operation counter 231d is increased by 1; and if one game ball enters the out port 24a, the value of the normal out counter 231e is increased by 1. When the values of the various counters 231a to 231e in the normal counter area 231 in situations where neither the opening/closing execution mode based on a jackpot result nor the high-frequency support mode is active, the base values are as follows.
Base value: The ratio of the total number of game balls dispensed (K91 × "number of prize balls for winning into the general prize slot 31" + K92 × "number of prize balls for winning into the special electric prize slot 32" + K93 × "number of prize balls for winning into the first operating slot 33" + K94 × "number of prize balls for winning into the second operating slot 34") to the total number of game balls discharged from the game area PA (K91 + K92 + K93 + K94 + K95).

In addition to the normal counter area 231, the work area 223 for non-specific control is also provided with a calculation result storage area 234. Similar to the 35th embodiment described above, the calculation result storage area 234 includes a current area 311, a first history area 312, a second history area 313, and a third history area 314 as storage areas for base value information (see Figure 126). The current area 311 stores the most recent base value calculated in the result calculation process (Figure 149). The first history area 312 stores the final base value from the previous calculation period. The second history area 313 stores the final base value from the calculation period two periods prior. The third history area 314 stores the final base value from the calculation period three periods prior.

Figure 149 is a flowchart showing the result calculation process in this embodiment, which is executed by the main CPU 63. In the management process (step S8920) of the first timer interrupt process (Figure 133), the program for the management execution process, which corresponds to non-specific control, is read in step S3803, similar to the management process in the 15th embodiment (Figure 70). Then, in this management execution process (Figure 71), a check process is executed in step S3908, similar to the 15th embodiment. This check process executes the result calculation process and also executes the display process (Figure 150), which will be described later. Furthermore, the processes in steps SA201 to SA217 of the result calculation process are executed using the non-specific control program and non-specific control data in the main CPU 63.

First, the base value calculation process is performed (step SA201). In this calculation process, the base value is calculated using the values of the various counters 231a to 231e in the normal counter area 231, similar to the 35th embodiment described above. In this embodiment, the calculation of the base value is not completed in a single execution of the result calculation process, but rather is completed by executing the result calculation process a predetermined number of times.

Specifically, in a predetermined number of processing iterations of the result calculation process in which the calculation of a new base value is initiated, step SA201 calculates the following, assuming that the values of the various counters 231a to 231e in the normal counter area 231 are K91 to K95: K91 × "number of prize balls for winning into the general prize slot 31", K92 × "number of prize balls for winning into the special electric prize device 32", K93 × "number of prize balls for winning into the first operation slot 33", K94 × "number of prize balls for winning into the second operation slot 34", and the total number of game balls discharged from the skill area PA (K91 + K92 + K93 + K94 + K95). The results of these calculations are then stored in the calculation in-process storage area provided in the work area 223 for non-specific control. Subsequently, in step SA201 of the result calculation process for the processing run one run after the predetermined processing run, the total number of game balls dispensed (K91 × "number of prize balls for entry into general prize slot 31" + K92 × "number of prize balls for entry into special electric prize device 32" + K93 × "number of prize balls for entry into first operation slot 33" + K94 × "number of prize balls for entry into second operation slot 34") is calculated using the various information stored in the calculation storage area, and the calculation result is stored in the calculation storage area. Then, in step SA201 of the result calculation process for the processing run two runs after the predetermined processing run, the base value is calculated using the various information stored in the calculation storage area.

In other words, in this embodiment, the result calculation process needs to be executed three times to calculate the base value. In this case, the result calculation process is called and executed by the first timer interrupt process (Figure 133), and therefore is executed each time the first interrupt cycle (specifically, 4 milliseconds) elapses. Consequently, the base value is calculated approximately every 12 milliseconds. However, this is not limited to this; the period for calculating the base value may be shorter or longer than 12 milliseconds.

As described above, by configuring the system to calculate a single base value by executing the result calculation process multiple times, the processing load for calculating the base value can be reduced. In particular, since the result calculation process is executed as a process corresponding to non-specific control, executing the result calculation process requires not only reading the program and data for non-specific control, but also saving information from various registers of the main CPU 63 used in the process corresponding to specific control. In this case, reducing the processing load for calculating the base value reduces the processing load of the result calculation process, and consequently, reduces the processing load for executing the process corresponding to non-specific control.

Even in a configuration where the result calculation process is executed multiple times to calculate a single base value, the information regarding the calculation of the base value during each execution of the result calculation process is written to the work area 223 for non-specific control. This allows the information regarding the calculation of the base value to be retained even if the information in the various registers of the main CPU 63 used in the non-specific control process is erased when a process corresponding to specific control is executed between executions of the result calculation process.

Even in a configuration where the result calculation process is executed multiple times to calculate a single base value, in the first execution of the result calculation process to calculate a new base value, all values of the various counters 231a to 231e in the normal counter area 231 are extracted, and the base value for that calculation is calculated using these extracted values. This makes it possible to calculate a single base value without being affected by changes in the values of the various counters 231a to 231e in the normal counter area 231, even if those changes occur during the calculation of the single base value.

After performing the base value calculation in step SA201, it is determined whether the calculation of one base value has been completed in the result calculation process for this processing run (step SA202). If the calculation of one base value has not been completed (step SA202: NO), the processes in steps SA203 to SA205 are not executed, thereby preventing the overwriting of the base value in the current area 311 of the calculation result storage area 234.

If the calculation of a base value has been completed (step SA202: YES), the calculated base value is overwritten in the current area 311 (step SA203). Then, it is determined whether or not "1" is set in the shift trigger flag provided in the work area 223 for non-specific control (step SA204). In this embodiment, when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) in a situation that is neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode has reached the shift reference number (specifically 60,000 balls) and the calculation of a new base value has been completed, the data shift processing in the calculation result storage area 234 (step SA216) is executed. In this data shift process, the information stored in the current area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234 is shifted in the following order: second history area 313 → third history area 314, first history area 312 → second history area 313, current area 311 → first history area 312. After this shift, the current area 311 is cleared to "0". The shift trigger flag is a flag used by the main CPU 63 to identify that the total number of game balls has reached the shift reference number but the data shift process has not yet been executed.

If the shift trigger flag is set to "1" (step SA204: YES), the shift calculation completion flag provided in the non-specific control work area 223 is set to "1" (step SA205). The shift calculation completion flag is used by the main CPU 63 to identify that the calculation of a base value has been completed after the total number of game balls reaches the shift reference number.

If a negative determination is made in step SA202, step SA204, or step SA205, it is determined whether the management start flag in the non-specific control work area 223 is set to "1" (step SA206). If the management start flag is not set to "1" (step SA206: NO), the pre-management start processing is executed (step SA207). In the pre-management start processing, steps S8604 to S8608 of the result calculation processing (Figure 130) in the 35th embodiment are executed.

If the management start flag is set to "1" (step SA206: YES), it is determined whether the shift trigger flag in the non-specific control work area 223 is set to "1" (step SA208). If the shift trigger flag is not set to "1" (step SA208: NO), the total number is calculated by summing the values of all the counters 231a to 231e in the normal counter area 231 (step SA209). Then, it is determined whether the calculated total number is 60,000 or more, which is the shift reference number (step SA210).

If a positive result is obtained in step SA210, the shift trigger flag in the non-specific control work area 223 is set to "1" (step SA211). Also, the pre-shift display flag provided in the non-specific control work area 223 is set to "1" (step SA212). The pre-shift display flag is used by the main CPU 63 to identify that the situation is such that the pre-shift display corresponding to the total number of game balls reaching the shift reference number should be started on the first to fourth notification display devices 201 to 204.

If the shift trigger flag is set to "1" and a positive determination is made in step SA208, it is determined whether the shift calculation completion flag in the non-specific control work area 223 is set to "1" (step SA213). As previously explained, the shift calculation completion flag is set to "1" when the calculation of the base value is completed after the total number of game balls reaches the shift reference number. If a positive determination is made in step SA213, the shift trigger flag in the non-specific control work area 223 is cleared to "0" (step SA214). Also, the shift calculation completion flag in the non-specific control work area 223 is cleared to "0" (step SA215).

Subsequently, a data shift process is executed (step SA216). In the data shift process, the information stored in the current area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234 is shifted in the order of second history area 313 → third history area 314, first history area 312 → second history area 313, current area 311 → first history area 312, and then the current area 311 is cleared to "0". As a result, the final base value from the calculation period two cycles ago is stored in the third history area 314 as the final base value from the calculation period three cycles ago, the final base value from the calculation period one cycle ago is stored in the second history area 313 as the final base value from the calculation period two cycles ago, and the base value calculated after the total number of game balls in the current calculation period reaches the shift reference number is stored in the first history area 312 as the final base value from the calculation period one cycle ago. Furthermore, currently, area 311 has no base values stored in it. Note that when performing data shifts like the one described above, the LDIR instruction is used. The LDIR instruction specifies the address of the area where the information is stored and the address of the area where the information is stored, thereby shifting (copying) the information stored in the source area to the destination area. Afterward, all counters 231a to 231e in the normal counter area 231 are cleared to "0" (step SA217).

Figure 150 is a flowchart showing the display processing in this embodiment, which is executed by the main CPU 63. Note that the processing in steps SA301 to SA320 of the display processing is executed using the non-specific control program and non-specific control data in the main CPU 63.

First, it is determined whether the management start flag in the work area 223 for non-specific control is set to "1" (step SA301). If a negative determination is made in step SA301, the base value is read from the current area 311, similar to step S8714 of the display processing in the 35th embodiment (Figure 131), and calculation result data corresponding to the first decimal place and the second decimal place of the read base value is set in the display target setting area 276 (step SA302). When the display data corresponding to the calculation result data is transmitted to the display IC 266, the first decimal place of the base value in the current area 311 is displayed on the third notification display device 203, and the second decimal place of the base value in the current area 311 is displayed on the fourth notification display device 204. With the above configuration, when the management start flag is not set to "1", the base values in past calculation periods are not reported, and only the base value calculated in the current calculation period is reported. Furthermore, when the base value is reported while the management start flag is not set to "1", the display content of the first to fourth notification display devices 201 to 204 is the same as in the 35th embodiment described above.

If a positive determination is made in step SA301, the value of the switching timing counter provided in the non-specific control work area 223 is decremented by 1 (step SA303). The switching timing counter is a counter used by the main CPU 63 to determine the timing for switching the display content of the first to fourth notification display devices 201 to 204 when the base value is being displayed on the first to fourth notification display devices 201 to 204.

In this embodiment, when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) does not reach the shift reference number in a situation that is neither the opening/closing execution mode based on a jackpot result nor the high-frequency support mode, the base values stored in the current area 311, the first history area 312, the second history area 313, and the third history area 314 are notified for a display duration (specifically 5 seconds), and an interval blackout is performed for an interval duration (specifically 1 second) to notify that a switch in the base value to be notified occurs during the notification of these base values. Specifically, as an interval blackout, all display segments 321 to 324 in each of the first to fourth notification display devices 201 to 204 are turned off, causing the first to to fourth notification display devices 201 to 204 to be in a blackout state. By having the base value to be notified switch in a predetermined order—Current Area 311 → First History Area 312 → Second History Area 313 → Third History Area 314—interval hiding is performed before the switch, making it possible to clearly inform the administrator of the gaming hall that the base value to be notified is about to switch.

When the total number of game balls reaches the shift threshold, the first to fourth notification display devices 201 to 204 will display a corresponding pre-shift indication. Specifically, the pre-shift indication will display "A." on each of the first to fourth notification display devices 201 to 204. The content of the "A." display is not shown on the first to fourth notification display devices 201 to 204 during either the display duration of the display corresponding to the base value or the interval period during which it is not displayed. This makes it possible to make the overall display content of the first to fourth notification display devices 201 to 204 different from the display duration of the display corresponding to the base value or the interval period during which it is not displayed. Therefore, by confirming that the pre-shift indication is being displayed on the first to fourth notification display devices 201 to 204, the manager of the gaming hall can understand that the total number of game balls has reached the shift threshold and a shift in the base value is occurring.

The content displayed before the shift differs from the content displayed on the first to fourth notification display devices 201 to 204 when the check display is being performed, when the pre-management flag is not set to "1", when the setting confirmation process (Figure 136) is being executed, and when the setting value update process (Figure 137) is being executed. From this point of view, by confirming that the pre-shift display is being performed on the first to fourth notification display devices 201 to 204, the administrator of the gaming hall can understand that the total number of game balls has reached the shift threshold, and therefore a shift of the base value is occurring.

The duration of the pre-shift display is set to be longer than the interval period during which the display is hidden for the interval (specifically, 1 second). Furthermore, the duration of the pre-shift display is set to be longer than the display duration corresponding to the base value (specifically, 5 seconds). Specifically, the pre-shift display duration is set to 8 seconds. However, this is not the only possible configuration; the pre-shift display duration may be longer than the interval period and less than or equal to the display duration corresponding to the base value, or shorter than or equal to the interval period. However, to clearly ensure that the administrator of the gaming hall is aware that the pre-shift display is active, it is preferable that the pre-shift display duration be set to be longer than the interval period.

As already explained, the calculation of the base value requires multiple executions of the result calculation process (Figure 149). Specifically, the calculation period for the base value is 12 milliseconds. Furthermore, the data shift process (step SA216), which shifts the base value information between various areas 311-314 of the calculation result storage area 234 when the total number of game balls reaches the shift reference number, is executed after the base value is newly calculated following the shift reference number is reached. In this case, the execution period for the pre-shift display is set to be longer than the maximum period required from the point when the total number of game balls reaches the shift reference number until the data shift process (step SA216) is completed. This makes it possible to complete the new calculation of the base value and the base value data shift process (step SA216) while the pre-shift display is being shown on the first to fourth notification display devices 201-204.

Returning to the explanation of the display processing (Figure 150), when the process in step SA303 is executed, it is determined whether the value of the switching timing counter after the 1-unit decrement is "0" to determine whether the current measurement period has elapsed among the base value display duration, the interval period during which the display is hidden for the interval, and the pre-shift display execution period (step SA304). If the determination in step SA304 is positive, it is determined whether the pre-shift display should be started by checking whether the pre-shift display flag in the non-specific control work area 223 is set to "1" (step SA305). If the determination in step SA305 is negative, it is determined whether the interval flag provided in the non-specific control work area 223 is set to "1" (step SA306). The interval flag is a flag used by the main CPU 63 to determine whether the display should be started for the interval.

If a negative result is obtained in step SA306, it means that the target for which notification should be started at this switching timing by the first to fourth notification display devices 201 to 204 is the base value. In this case, the value of the display target counter provided in the non-specific control work area 223 is incremented by 1 (step SA307). Then, if the value of the display target counter after incrementing by 1 exceeds the maximum value of "3" (step SA308: YES), the value of the display target counter is cleared to "0" (step SA309).

The display target counter is a counter used by the main CPU 63 to identify the base value to be reported in the first to fourth notification display devices 201 to 204 from among the base values stored in the current area 311, first history area 312, second history area 313, and third history area 314, respectively, within the calculation result storage area 234. Specifically, when the value of the display target counter is "0", the base value stored in the current area 311 is the target for reporting; when the value of the display target counter is "1", the base value stored in the first history area 312 is the target for reporting; when the value of the display target counter is "2", the base value stored in the second history area 313 is the target for reporting; and when the value of the display target counter is "3", the base value stored in the third history area 314 is the target for reporting.

If a negative determination is made in step SA308, or if the process in step SA309 is executed, the switching timing counter of the non-specific control work area 223 is set to a value corresponding to the display duration for displaying the base value (specifically, 5 seconds) as the value corresponding to the next switching timing (step SA310). Then, the interval flag in the non-specific control work area 223 is set to "1" (step SA311). As a result, if the pre-shift display flag in the non-specific control work area 223 is not set to "1" by the next switching timing, the interval display will be hidden when the next switching timing arrives.

Subsequently, a process is executed to set display data corresponding to the base value being reported in the display target setting area 276, which is provided in the work area 223 for non-specific control. Specifically, similar to step S8708 of the display processing in the 35th embodiment (Figure 131), display type data corresponding to the value of the display target counter is set in the display target setting area 276 (step SA312). The display type data includes display data for causing the first notification display device 201 to display that the report target of the first to fourth notification display devices 201 to 204 is the base value, and display data for causing the second notification display device 202 to display that the base value of the report target corresponds to one of the current area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234.

Subsequently, similar to step S8709 of the display processing in the 35th embodiment (Figure 131), the base value is read from the area corresponding to the value of the display target counter among the current area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234, and the calculation result data corresponding to the first decimal place and the second decimal place of the read base value is set in the display target setting area 276 (step SA313). The calculation result data includes display data for causing the third notification display device 203 to display the digit corresponding to the first decimal place of the base value to be notified, and display data for causing the fourth notification display device 204 to display the digit corresponding to the second decimal place of the base value to be notified.

When display data consisting of display type data and calculation result data is set in the display target setting area 276, the display data is transmitted to the display IC 266 in the second timer interrupt processing (Figure 134), similar to the 35th embodiment described above, and the display corresponding to the display data is displayed on the first to fourth notification display devices 201 to 204. In other words, if the base value of area 311 is currently being reported, a display like the one shown in Figure 127(a) will be shown on the first to fourth notification display devices 201 to 204. If the base value of the first history area 312 is being reported, a display like the one shown in Figure 127(b) will be shown on the first to fourth notification display devices 201 to 204. If the base value of the second history area 313 is being reported, a display like the one shown in Figure 127(c) will be shown on the first to fourth notification display devices 201 to 204. If the base value of the third history area 314 is being reported, a display like the one shown in Figure 127(d) will be shown on the first to fourth notification display devices 201 to 204.

If the interval flag in the non-specific control work area 223 is set to "1", and a positive determination is made in step SA306, it means that the target for which notification should be started at the current switching timing in the first to fourth notification display devices 201 to 204 is the interval-only hidden display. In this case, the interval setting process is executed (step SA314). In this setting process, the switching timing counter in the non-specific control work area 223 is set to a value corresponding to the next switching timing, corresponding to the interval period (specifically, 1 second). After that, the interval flag in the non-specific control work area 223 is cleared to "0" (step SA315). As a result, if the pre-shift display flag in the non-specific control work area 223 is not set to "1" by the next switching timing, the base value will be displayed at the next switching timing.

Subsequently, interval data is set in the display target setting area 276 located in the non-specific control work area 223 (step SA316). The interval data is data for causing the first to fourth notification display devices 201-204 to disable the display during the interval. Specifically, it is data for turning off all display segments 321-324 on each of the first to fourth notification display devices 201-204. Once the interval data is set in the display target setting area 276 as display data, the second timer interrupt process (Figure 134) transmits this interval data to the display IC 266, causing all first to fourth notification display devices 201-204 to disable the display. The administrator of the gaming hall, upon confirming that the first to fourth notification display devices 201-204 are disabled, can understand that it is the interval period.

If the pre-shift display flag in the non-specific control work area 223 is set to "1," and a positive determination is made in step SA305, it means that the target to be notified by the current switching timing in the first to fourth notification display devices 201 to 204 is the pre-shift display. In this case, the setting process for the pre-shift display period is executed (step SA317). In this setting process, the switching timing counter in the non-specific control work area 223 is set to a value corresponding to the execution period of the pre-shift display (specifically, 8 seconds) as the value corresponding to the next switching timing.

Subsequently, the interval flag in the non-specific control work area 223 is cleared to "0," and the pre-shift display flag in the non-specific control work area 223 is also cleared to "0" (step SA318). Furthermore, the display target counter in the non-specific control work area 223 is set to its maximum value of "3" (step SA319). By clearing the interval flag to "0," if the execution period for pre-shift display has elapsed, the next notification target becomes the base value. Then, by setting the maximum value to the display target counter, if a negative determination is made in step SA306 to notify the base value, the value of the display target counter is incremented by 1 in step SA307. If the value of the display target counter exceeds the maximum value, a positive determination is made in step SA308, and the value of the display target counter is cleared to "0." As a result, if the execution period for pre-shift display has elapsed, the next notification target becomes the base value, and that base value becomes the base value of the current area 311 in the calculation result storage area 234.

In other words, when a pre-shift display is shown, regardless of whether the notification target before the pre-shift display was the base value or the interval-hidden value, the notification will start with the base value. This allows for checking the base value without waiting for the interval period to elapse after the pre-shift display ends. Furthermore, regardless of whether the last notified base value before the pre-shift display was in the current area 311, first history area 312, second history area 313, or third history area 314 of the calculation result storage area 234, the notification will start from the base value in the current area 311 after the pre-shift display ends. This makes it possible to return the notification order of base values in the current area 311, first history area 312, second history area 313, and third history area 314 to the initial notification order, making it easier for the gaming hall manager to recognize that a base value shift has just occurred.

Subsequently, pre-shift display data is set in the display target setting area 276 located in the non-specific control work area 223 (step SA320). The pre-shift display data is data for causing the first to fourth notification display devices 201 to 204 to display the pre-shift information; specifically, it is data for displaying "A." on each of the first to fourth notification display devices 201 to 204. Once the pre-shift display data is set in the display target setting area 276 as display data, the second timer interrupt process (Figure 134) transmits the pre-shift display data to the display IC 266, and "A." is displayed on each of the first to fourth notification display devices 201 to 204. The administrator of the gaming hall, upon confirming that the pre-shift display is being performed on the first to fourth notification display devices 201 to 204, can understand that the pre-shift display period is in effect.

Next, referring to the time chart in Figure 151, we will explain how the base values of various areas 311 to 314 are reported on the first to fourth notification display devices 201 to 204 when the management start flag is set to "1". Figure 151(a) shows the period during which the base value stored in the current area 311 is reported on the first to fourth notification display devices 201 to 204, Figure 151(b) shows the period during which the base value stored in the first history area 312 is reported on the first to fourth notification display devices 201 to 204, Figure 151(c) shows the period during which the base value stored in the second history area 313 is reported on the first to fourth notification display devices 201 to 204, and Figure 151(d) shows the period during which the base value stored in the third history area 314 is reported on the first to fourth notification display devices 201 to 204. Figure 151(e) indicates the period during which the first to fourth notification display devices 201 to 204 are not displayed for the interval; Figure 151(f) indicates the period during which the first to fourth notification display devices 201 to 204 are displayed before the shift; and Figure 151(g) indicates the timing when, after the base value calculation period has newly begun, the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the shift reference number (specifically, 60,000 balls) in a situation that is neither the opening/closing execution mode based on the jackpot result nor the high-frequency support mode.

At timing t1, as shown in Figure 151(a), the notification of the base value stored in the current area 311 is initiated on the first to fourth notification display devices 201 to 204. During this notification, as shown in Figure 127(a), the first notification display device 201 displays an indication that the base value is the target of notification, the second notification display device 202 displays an indication that the base value stored in the current area 311 is the target of notification, and the third notification display device 203 and the fourth notification display device 204 display an indication corresponding to the base value stored in the current area 311.

Subsequently, at timing t2, the display duration from timing t1 has elapsed, and as shown in Figure 151(a), the notification of the base value currently stored in area 311 ends. As shown in Figure 151(e), the interval-based display mode is then activated on the first to fourth notification display devices 201 to 204. This interval-based display mode ends at timing t3, which is the time when the interval period from timing t2 has elapsed, as shown in Figure 151(e).

At timing t3, as shown in Figure 151(b), the notification of the base value stored in the first history area 312 is started on the first to fourth notification display devices 201 to 204. During this notification, as shown in Figure 127(b), the first notification display device 201 displays an indication that the base value is the one to be notified, the second notification display device 202 displays an indication that the base value stored in the first history area 312 is the one to be notified, and the third notification display device 203 and the fourth notification display device 204 display an indication corresponding to the base value stored in the first history area 312.

Subsequently, at timing t4, the display duration from timing t3 has elapsed, and as shown in Figure 151(b), the notification of the base value stored in the first history area 312 ends. As shown in Figure 151(e), the interval-based display mode is then activated on the first to fourth notification display devices 201 to 204. This interval-based display mode ends at timing t5, which is the time when the interval period from timing t4 has elapsed, as shown in Figure 151(e).

At timing t5, as shown in Figure 151(c), the notification of the base value stored in the second history area 313 is started on the first to fourth notification display devices 201 to 204. During this notification, as shown in Figure 127(c), the first notification display device 201 displays an indication that the base value is the one to be notified, the second notification display device 202 displays an indication that the base value stored in the second history area 313 is the one to be notified, and the third notification display device 203 and the fourth notification display device 204 display an indication corresponding to the base value stored in the second history area 313.

Subsequently, at timing t6, the display duration from timing t5 has elapsed, and as shown in Figure 151(c), the notification of the base value stored in the second history area 313 ends. As shown in Figure 151(e), the interval-based display mode is then activated on the first to fourth notification display devices 201 to 204. This interval-based display mode ends at timing t7, which is the time when the interval period from timing t6 has elapsed, as shown in Figure 151(e).

At timing t7, as shown in Figure 151(d), the notification of the base value stored in the third history area 314 is initiated on the first to fourth notification display devices 201 to 204. During this notification, as shown in Figure 127(d), the first notification display device 201 displays an indication that the base value is the one to be notified, the second notification display device 202 displays an indication that the base value stored in the third history area 314 is the one to be notified, and the third notification display device 203 and the fourth notification display device 204 display an indication corresponding to the base value stored in the third history area 314.

Subsequently, at timing t8, the display duration from timing t7 has elapsed, and as shown in Figure 151(d), the notification of the base value stored in the third history area 314 ends. As shown in Figure 151(e), the interval-based display mode is then activated on the first to fourth notification display devices 201 to 204. This interval-based display mode ends at timing t9, which is the time when the interval period from timing t8 has elapsed, as shown in Figure 151(e).

Subsequently, from timing t9 to t10, similar to timings t1 to t2, the display corresponding to the base value stored in the current area 311 is performed on the first to fourth notification display devices 201 to 204, as shown in Figure 151(a). Furthermore, from timing t10 to t11, similar to timings t2 to t3, interval-based display is performed on the first to fourth notification display devices 201 to 204, as shown in Figure 151(e). Then, at timing t11, similar to timing t3, the display corresponding to the base value stored in the first history area 312 is started on the first to fourth notification display devices 201 to 204, as shown in Figure 151(b).

Subsequently, at timing t12, which is during the process of displaying the base value stored in the first history area 312, as shown in Figure 151(g), the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) since the start of the new base value calculation period, when neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode is active, reaches the shift reference number (specifically, 60,000 balls). However, at timing t12, since the display period has not elapsed since the display corresponding to the base value in the first history area 312 started at timing t11, the display corresponding to the base value in the first history area 312 continues, as shown in Figure 151(b). This allows the system to display the current notification target on the first to fourth notification display devices 201 to 204 for the scheduled period of time, even if the timing of when the total number of game balls reaches the shift reference number is arbitrary.

Subsequently, at timing t13, the display continuation period from timing t11 has elapsed, and as shown in Figure 151(b), the notification of the base value stored in the first history area 312 ends, and as shown in Figure 151(f), the pre-shift display begins on the first to fourth notification display devices 201 to 204. Even if the total number of game balls reaches the shift reference number while another base value notification is being performed, the pre-shift display will begin on the first to fourth notification display devices 201 to 204 once the display continuation period for that base value notification has elapsed. Furthermore, even if the total number of game balls reaches the shift reference number while an interval display is being performed, the pre-shift display will begin on the first to fourth notification display devices 201 to 204 once the interval period for that interval display has elapsed.

Subsequently, at timing t14, the execution period for the pre-shift display elapses from timing t13, and as shown in Figure 151(f), the pre-shift display ends. As shown in Figure 151(a), the notification of the base value stored in the current area 311 begins on the first to fourth notification display devices 201 to 204. In other words, even if the notification target when the pre-shift display begins is the base value in the first history area 312, once the pre-shift display ends, notification begins from the base value in the current area 311 corresponding to the first notification order in the base value notification sequence.

Subsequently, at timing t15, the display duration from timing t14 has elapsed, and as shown in Figure 151(a), the notification of the base value stored in the current area 311 ends. As shown in Figure 151(e), the interval-based display mode is then activated on the first to fourth notification display devices 201 to 204. This interval-based display mode ends at timing t16, which is the time when the interval period from timing t15 has elapsed, as shown in Figure 151(e). As shown in Figure 151(b), the display corresponding to the base value in the first history area 312 begins on the first to fourth notification display devices 201 to 204.

The embodiment described in detail above provides the following excellent effects.

The base values stored in the current area 311, first history area 312, second history area 313, and third history area 314 of the calculation result storage area 234 are sequentially displayed on the first to fourth notification display devices 201 to 204. This allows for the individual notification of base values corresponding to different periods while keeping the number of notification display devices 201 to 204 to a minimum. Furthermore, because each base value is displayed in a predetermined order, it becomes easier for the gaming hall manager to understand the types of base values being displayed.

The display order of the base values is determined by corresponding the current area 311, the first history area 312, the second history area 313, and the third history area 314 in the calculation result storage area 234. This simplifies the processing configuration for identifying the type of base value to be displayed when starting the display of base values anew.

Before the display of the next base value changes from the current base value to the current one, the first to fourth notification display devices 201 to 204 switch to an interval-based hidden state. This allows the administrator of the gaming hall to clearly understand that the type of base value being displayed has changed.

In a configuration where the base value is sequentially displayed on the first to fourth notification display devices 201 to 204, if the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the shift reference number (specifically, 60,000 balls) when the calculation period for the base value has just started and neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode is active, the first to fourth notification display devices 201 to 204 will display a pre-shift notification. This makes it possible to notify the system that the total number of game balls has reached the shift reference number using the first to fourth notification display devices 201 to 204.

When the total number of game balls reaches the shift reference number, the base values stored in the current area 311, first history area 312, second history area 313, and third history area 314 are shifted to the later storage area in the calculation result storage area 234. Simultaneously, the various counters 231a to 231e in the normal counter area 231 are cleared to "0," and the calculation of the base value for a new calculation period begins. Therefore, the notification content of the base value in the first to fourth notification display devices 201 to 204 is changed when the total number of game balls reaches the shift reference number. In this case, since the notification of the base value resumes after the pre-shift display is shown when the total number of game balls reaches the shift reference number, it is possible to make the administrator of the gaming hall aware that the notification content of the base value changes when the total number of game balls reaches the shift reference number.

If the total number of game balls reaches the shift threshold while the base value is being displayed, the pre-shift display will begin after the display period for the base value has elapsed. This allows the pre-shift display to begin without interfering with the already ongoing base value display.

In a configuration where multiple base values stored in the calculation result storage area 234 are displayed sequentially according to a predetermined display order, after the pre-shift display is performed, the display starts from the base value in the first position in the predetermined display order. This allows for re-confirmation starting from the base value in the first position in the predetermined display order when the total number of game balls reaches the shift reference number.

In a configuration where a base value is calculated using the result calculation process (Figure 149), the result calculation process is executed multiple times from the start of calculation to the completion of that base value. This reduces the processing load required for executing the result calculation process compared to a configuration where the base value is calculated in a single result calculation.

In a configuration where, when the total number of game balls reaches the shift reference number, a new base value is derived at the moment the shift reference number is reached, followed by the execution of a base value data shift process (step SA216), the first to fourth notification display devices 201 to 204 display the pre-shift status when the total number of game balls reaches the shift reference number. This allows the first to fourth notification display devices 201 to 204 to display the pre-shift status while a new base value is being derived and the base value data shift process is underway, preventing the display of the previous base value from continuing even after the shift reference number has been reached.

Furthermore, from the start of the base value calculation period until the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the initial reference number (specifically, 6000 balls) in situations where neither the opening/closing execution mode based on the jackpot result nor the high-frequency support mode is in effect, the system may be configured, similar to the 35th embodiment described above, to display the initial calculation on the first to fourth notification display devices 201 to 204 when the current base value of area 311 is displayed.

Furthermore, if the total number of game balls reaches the shift reference number (specifically, 60,000 balls) while the first to fourth notification display devices 201 to 204 are in the interval-display state, the pre-shift display may be started immediately. Alternatively, if the base value is displayed on the first to fourth notification display devices 201 to 204, and the total number of game balls reaches the shift reference number (specifically, 60,000 balls), the pre-shift display may be started after the display period for the base value has elapsed. This configuration allows for an early start to the pre-shift display while preventing the already ongoing base value display from being prematurely terminated.

Furthermore, the display content of the pre-shift display is not limited to those described above. While at least some of the display content of the first to fourth notification display devices 201 to 204 may be displayed in other situations, the overall display content of the first to fourth notification display devices 201 to 204 may be configured to be displayed only in situations where it is not displayed. Also, while the configuration states that at least one display segment 321 to 324 of each of the first to fourth notification display devices 201 to 204 is illuminated when the pre-shift display is performed, some of the first to fourth notification display devices 201 to 204 may be configured so that all of the display segments 321 to 324 are turned off. Furthermore, the configuration does not limit the display content of the pre-shift display to being maintained throughout the duration of the pre-shift display; the display content of the pre-shift display may blink throughout the duration of the pre-shift display.

Furthermore, the execution period for the pre-shift display is not limited to a fixed configuration. For example, the execution period for the pre-shift display may vary depending on the time required from when the total number of game balls reaches the shift reference number (specifically, 60,000 balls) until a new base value is calculated and the base value data shift processing is completed.

Furthermore, if the total number of game balls reaches the shift reference number, the system may be configured so that the pre-shift display begins after the display of the last base value in the display cycle of each base value being performed by the first to fourth notification display devices 201 to 204 (i.e., the base value stored in the third history area 314) is completed. This makes it possible to start a new display cycle of each base value via the pre-shift display after the completion of each base value display cycle.

Furthermore, when the total number of game balls reaches the shift reference number, the calculation of the base value is started using the various counters 231a to 231e in the normal counter area 231 at that time. Once the calculation of the base value is complete, data shift processing (step SA216) is performed. In this case, it becomes possible to accurately calculate the base value at the moment the total number of game balls reaches the shift reference number.

Furthermore, during the interval period, instead of the interval display being hidden, a predetermined display may be shown on at least some of the first to fourth notification display devices 201 to 204, and the overall display of the first to fourth notification display devices 201 to 204 may be an interval display with content different from the display content that may occur when the base value is being reported. For example, in each of the first to fourth notification display devices 201 to 204, only the central display segments 321 to 324 may be lit to display "-", or some of the display devices of the first to fourth notification display devices 201 to 204 may display "-", while the remaining display devices remain hidden.

Alternatively, the system may be configured without a set interval period. In this case, once the display period for one base value has elapsed, the display of the next target base value will begin on the first to fourth notification display devices 201 to 204.

<44th Embodiment>
In this embodiment, the start timing of the pre-shift display differs from that of the 43rd embodiment described above. The configurations that differ from the 43rd embodiment will be described below. Configurations that are the same as those in the 43rd embodiment will generally not be described.

The start timing of the pre-shift display in this embodiment will be explained with reference to the time chart in Figure 152. Figure 152(a) shows the period during which the base value stored in the current area 311 is announced by the first to fourth notification display devices 201 to 204, Figure 152(b) shows the period during which the base value stored in the first history area 312 is announced by the first to fourth notification display devices 201 to 204, Figure 152(c) shows the period during which the base value stored in the second history area 313 is announced by the first to fourth notification display devices 201 to 204, and Figure 152(d) shows the period during which the base value stored in the third history area 314 is announced by the first to fourth notification display devices 201 to 204. Figure 152(e) shows the period during which the first to fourth notification display devices 201 to 204 are not displayed for the interval; Figure 152(f) shows the period during which the first to fourth notification display devices 201 to 204 are displayed before the shift; and Figure 152(g) shows the timing when, after the base value calculation period has started, the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the shift reference number (specifically, 60,000 balls) in a situation that is neither the opening/closing execution mode based on the jackpot result nor the high-frequency support mode.

At timings t1 to t11, similar to the time charts in Figures 151(a) to 151(g) in the 43rd embodiment described above, the first to fourth notification display devices 201 to 204 repeatedly display the base value corresponding to the display duration and perform interval-specific hiding during the interval period. The display corresponding to the base value is repeated in the order of current area 311 → first history area 312 → second history area 313 → third history area 314 of the calculation result storage area 234. Then, at timing t11, as shown in Figure 152(b), the display corresponding to the base value stored in the first history area 312 is started on the first to fourth notification display devices 201 to 204.

Subsequently, at timing t12, while the display corresponding to the base value stored in the first history area 312 is in progress, as shown in Figure 152(g), the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) since the start of the new base value calculation period, under conditions neither in the opening/closing execution mode due to a jackpot result nor the high-frequency support mode, reaches the shift reference number (specifically, 60,000 balls). In this case, at timing t12, although the display period corresponding to the base value in the first history area 312 has not yet elapsed since the start of the display at timing t11, the notification of the base value stored in the first history area 312 ends, as shown in Figure 152(b), and the pre-shift display begins on the first to fourth notification display devices 201 to 204, as shown in Figure 152(f).

Furthermore, even if the total number of game balls reaches the shift reference number while other base value notifications are being displayed, the pre-shift display will start on the first to fourth notification display devices 201 to 204 at that time. Also, even if the total number of game balls reaches the shift reference number while interval display is being disabled, the pre-shift display will start on the first to fourth notification display devices 201 to 204 at that time.

Subsequently, at timing t13, the execution period for the pre-shift display elapses from timing t12, and as shown in Figure 152(f), the pre-shift display ends. As shown in Figure 152(a), the notification of the base value stored in the current area 311 begins on the first to fourth notification display devices 201 to 204. In other words, even if the notification target when the pre-shift display begins is the base value in the first history area 312, once the pre-shift display ends, notification begins from the base value in the current area 311 corresponding to the first notification order in the base value notification sequence.

Subsequently, at timing t14, the display duration from timing t13 has elapsed, and as shown in Figure 152(a), the notification of the base value stored in the current area 311 ends. As shown in Figure 152(e), the interval-based display mode is initiated on the first to fourth notification display devices 201 to 204. This interval-based display mode ends at timing t15, which is the timing when the interval period from timing t14 has elapsed, as shown in Figure 152(e). As shown in Figure 152(b), the display corresponding to the base value in the first history area 312 begins on the first to fourth notification display devices 201 to 204.

According to the above configuration, when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the shift reference number (specifically, 60,000 balls) under conditions other than the opening/closing execution mode based on a jackpot result or the high-frequency support mode, the first to fourth notification display devices 201 to 204 will start displaying the pre-shift information at that time. This makes it possible to start the pre-shift information display earlier, enabling early notification that the total number of game balls has reached the shift reference number.

<45th Embodiment>
In this embodiment, the processing configuration of the main process executed by the primary CPU 63 differs from that of the 35th embodiment described above. The configurations that differ from those of the 35th embodiment will be described below. Configurations that are the same as those of the 35th embodiment will generally not be described.

Figure 153 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps SA401 to SA425 in the main processing are executed using a specific control program and specific control data on the main CPU 63.

First, the power-on initial setup process is executed (step SA401). During this process, for example, after the main process starts, the system waits for a predetermined waiting period (specifically, 1 second) before proceeding to the next process. During this predetermined waiting period, the operation and initial setup of the graphic display device 41 are completed. Access to the main RAM 65 is also permitted.

Subsequently, the internal function register setting process is executed (step SA402). In the internal function register setting process, similar to the 35th embodiment described above, the interrupt period of the first timer interrupt process (Figure 133), which is a process that periodically interrupts and is initiated from the main process, is set to the first interrupt period (specifically, 4 milliseconds). The interrupt period of the second timer interrupt process (Figure 134), which is also a process that periodically interrupts and is initiated from the main process, is set to the second interrupt period (specifically, 2 milliseconds), which is shorter than the first interrupt period.

In other words, in this embodiment, similar to the 35th embodiment described above, there are two timer interrupt processes, a first timer interrupt process (Figure 133) and a second timer interrupt process (Figure 134), with relatively long and short interrupt periods. Both the first timer interrupt process (Figure 133) and the second timer interrupt process (Figure 134) are started by interrupting the main process. The second timer interrupt process (Figure 134) is started by interrupting the first timer interrupt process (Figure 133). On the other hand, the first timer interrupt process (Figure 133) is not started by interrupting the second timer interrupt process (Figure 134). Furthermore, if both the first timer interrupt process (Figure 133) and the second timer interrupt process (Figure 134) have elapsed while neither has been executed, the second timer interrupt process (Figure 134) is started first, regardless of the order in which those periods have elapsed. In this respect, the second timer interrupt handler (Figure 134) can be said to be a process that is activated with higher priority than the first timer interrupt handler (Figure 133). However, this is not the only option; a configuration in which the first timer interrupt handler (Figure 133) is activated with higher priority than the second timer interrupt handler (Figure 134) is also possible.

In the internal function register setting process, the first interrupt period of the first timer interrupt process (Figure 133) is set to a predetermined register in the main CPU 63, and the second interrupt period of the second timer interrupt process (Figure 134) is set to a specific register in the main CPU 63. In addition to setting the first and second interrupt periods, the internal function register setting process also performs other operations, such as setting the numerical ranges of various counters, including the numerical range of the random number counter C1.

Subsequently, the startup processing flag located in the work area 221 for specific control is set to "1" (step SA403). Similar to the 35th embodiment described above, the startup processing flag is used by the main CPU 63 to identify a situation where, even if the first timer interrupt processing (Figure 133) is activated, the processes for power outage monitoring, updating various counters, and fraud monitoring among the various processes set in the first timer interrupt processing (Figure 133) should be executed, but the processes for advancing the game should not be executed, and the first timer interrupt processing (Figure 133) should be terminated.

The startup processing flag is set to "1" in the main processing (Figure 153) before the processing for starting the supply of operating power (steps SA401 to SA418) begins and before interrupt permission (step SA404) is enabled, similar to the 35th embodiment described above. It is then cleared to "0" before the processing for starting the supply of operating power ends and the residual processing (steps SA422 to SA425) begins. In this case, similar to the 35th embodiment described above, the first timer interrupt processing (Figure 133) does not execute steps S8907 to S8920 if the startup processing flag is set to "1", thereby preventing the processing necessary to advance the game from being executed while the processing for starting the supply of operating power (steps SA401 to SA418) is being executed. On the other hand, as described above, in the first timer interrupt processing (Figure 133), even if the startup processing flag is set to "1", the processing in steps S8901 to S8905 is executed. This ensures that power outage monitoring is performed even while the power supply start processing (steps SA401 to SA418) is being executed. Furthermore, the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the random number initial value counter CINI are updated, and fraud detection is performed.

In particular, even when the startup process flag is set to "1", the power outage information storage process (step S8901) is executed. This allows the system to execute power outage processing even if a power outage occurs while the power supply start process (steps SA401 to SA418) is being executed. In the power outage processing, similar to the 35th embodiment described above, the power outage flag in the specific control work area 221 is set to "1," and a checksum is calculated and stored in the specific control work area 221. Therefore, when the power supply restarts, it is not identified as an abnormality in the main RAM 65. This allows the system to identify that a power outage occurred during the setting confirmation process (step SA415) or the setting value update process (step SA418) when the power supply restarts.

Incidentally, when the setting confirmation process (step SA415) or the setting value update process (step SA418) is being executed, interrupts are not prohibited for either the first timer interrupt process (Figure 133) or the second timer interrupt process (Figure 134), and interrupts can occur at any time. In this case, if the first timer interrupt process (Figure 133) or the second timer interrupt process (Figure 134) is interrupted and activated in the main process (Figure 153), including the setting confirmation process (step SA415) and the setting value update process (step SA418), information about the return address of the main process (Figure 153) for returning after the timer interrupt process that was activated has finished is saved in the specific control stack area 222, and information about the various registers of the main CPU 63 immediately before the timer interrupt process is activated is also saved in the specific control stack area 222. When the timer interrupt process that was triggered completes, the process returns to the main process (Figure 153) corresponding to the return address information saved in the specific control stack area 222, and the information saved in the specific control stack area 222 is returned to the various registers of the main CPU 63.

After setting the startup process flag to "1" in step SA403, the interrupt permission setting is configured (step SA404). This causes the first timer interrupt process (Figure 133) to interrupt and start at the first interrupt cycle, and the second timer interrupt process (Figure 134) to interrupt and start at the second interrupt cycle. However, because the startup process flag is set to "1" in step SA403, even if the first timer interrupt process (Figure 133) is started, the processes for power outage monitoring, updating various counters, and fraud monitoring are executed, but the processes for advancing the game are not executed, and the first timer interrupt process (Figure 133) terminates.

Subsequently, it is determined whether the reset button 68c is pressed (step SA405). That is, it is determined whether the power-on operation of the pachinko machine 10 was performed and the supply of operating power to the MPU 62 began while the reset button 68c was pressed. Here, in this embodiment, similar to the 35th embodiment described above, the main control device 60 is provided with a setting key insertion section 68a and a reset button 68c, but the update button 68b is not provided. Furthermore, the main control device 60 is provided with first to fourth notification display devices 201 to 204, similar to the 11th embodiment, instead of first to third notification display devices 69a to 69c.

If the reset button 68c is not pressed (step SA405: NO), it is determined whether the power outage flag in the work area 221 for specific control is set to "1" (step SA406). The power outage flag is set to "1" if the power outage processing is executed during the power outage information storage processing (step S8901) of the first timer interrupt processing (Figure 133). The power outage flag is used by the main CPU 63 to determine whether the power outage processing was performed appropriately during the previous power outage.

If the power outage flag is set to "1" (step SA406: YES), checksums are calculated for the work area 221 and the stack area 222 for specific control (step SA407). The method for calculating the checksums is the same as in the 33rd embodiment described above. Then, the checksums for the work area 221 and the stack area 222 for specific control, which were calculated during the power outage processing performed immediately before the supply of operating power to the MPU 62 was stopped and stored in the work area 221, are read, and these read checksums are compared with the checksums calculated in step SA407 (step SA408). Finally, it is determined whether the checksums match (step SA409).

If a negative determination is made in step SA406 or step SA409, that is, if the power outage flag is not set to "1" or the checksum does not match, the game stop flag provided in the specific control work area 221 is set to "1" (step SA410). Setting the game stop flag to "1" allows the first timer interrupt processing (Figure 133) to execute steps S8901 to S8905, while the positive determination in step S8906 prevents the execution of steps S8907 to S8920. Therefore, if the power outage flag is not set to "1" because the power outage processing was not performed properly during the previous power outage, or if the checksum does not match due to a change in the information storage state in at least one of the specific control work area 221 and the specific control stack area 222 since the previous power outage, the processes for power outage monitoring, updating various counters, and fraud monitoring will be executed, but the processes for continuing the game will not be executed.

Subsequently, an abnormality command indicating that an abnormality occurred regarding the power outage flag or checksum at the start of power supply is transmitted to the voice and light emission control device 81 (step SA411). Upon receiving this abnormality command, the voice and light emission control device 81 illuminates the display light emission unit 53 in a manner corresponding to the information abnormality at the start of power supply, and outputs the voice message "Please change the settings." from the speaker unit 54. Furthermore, the text image "Please change the settings." is displayed on the pattern display device 41. These notifications are maintained until the power supply to the pachinko machine 10 is stopped, at which point they terminate. However, even if the power supply to the pachinko machine 10 is temporarily stopped, the above notifications may be continued until the setting value update process (step SA418) is executed and the power supply to the pachinko machine 10 is resumed.

If the power outage flag is set to "1" and the checksum is normal (steps SA406 and SA409: YES), it is determined whether the setting update display flag provided in the work area 221 for specific control is set to "1" (step SA412). The setting update display flag is a flag used by the main CPU 63 to identify that the setting value update process (step SA418) is being executed, similar to the 35th embodiment described above. If the setting update display flag is set to "1", the first to fourth notification display devices 201 to 204 will display an indication that the setting value is being updated and an indication of the setting value in progress. The setting update display flag is set to "1" when the setting value update process (step SA418) is started and cleared to "0" when the setting value update process (step SA418) is completed. Therefore, when the setting value update process (step SA418) is not being executed, the setting update display flag will not be set to "1". However, if the power supply to the main CPU 63 is stopped while the setting value update process (step SA418) is being executed, the setting update display flag will be set to "1" when the power supply to the main CPU 63 is subsequently restored. This state of the setting update display flag being set to "1" will be maintained until the RAM clear process (step SA416) is executed, or until the setting update display flag is cleared to "0" during the setting value update process (step SA418).

If a negative determination is made in step SA412 because the setting update display flag is not set to "1", it is determined whether the setting key insertion unit 68a is being operated ON using the setting key (step SA413). If the setting key insertion unit 68a is being operated ON using the setting key (step SA413: YES), the setting confirmation process is executed (step SA415). Even if the setting key insertion unit 68a is not being operated ON using the setting key (step SA413: NO), if the setting confirmation display flag provided in the work area 221 for specific control is set to "1" (step SA414: YES), the setting confirmation process is executed (step SA415). The setting confirmation process will be explained later.

The setting confirmation display flag is a flag used by the main CPU 63 to identify that the setting confirmation process (step SA415) is being executed, similar to the 35th embodiment described above. When the setting confirmation display flag is set to "1", the first to fourth notification display devices 201 to 204 display an indication that the setting value is being checked and an indication of the currently set setting value. The setting confirmation display flag is set to "1" when the setting confirmation process (step SA415) is started and cleared to "0" when the setting confirmation process (step SA415) is finished. Therefore, when the setting confirmation process (step SA415) is not being executed, the setting confirmation display flag is basically not set to "1". However, if the power supply to the main CPU 63 is stopped while the setting confirmation process (step SA415) is being executed, the setting confirmation display flag will be set to "1" when the power supply to the main CPU 63 is subsequently restarted. The state in which this setting confirmation display flag is set to "1" is maintained until the RAM clear process (step SA416) is executed, or until the process to clear the setting confirmation display flag to "0" is executed in the setting confirmation process (step SA415).

If the reset button 68c is pressed (step SA405: YES), a RAM clear process is executed (step SA416). In the RAM clear process, the work area 221 for specific control is cleared to "0" and initial settings are executed, except for the area where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, the setting reference area 341 described later). As a result, the area indicating whether the win/loss lottery mode is in high probability mode is cleared to "0", so the win/loss lottery mode becomes low probability mode regardless of the win/loss lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. In addition, the game rounds are not executed, the opening/closing execution mode is not executed, the general display unit 38a is not showing a change, and the general electric mechanism 34a is in a closed state. Furthermore, the hold storage area 65a and the general-purpose hold area 65c, both located in the work area 221 for specific control, are cleared to "0". This clears the hold information for both the special display unit 37a and the general-purpose display unit 38a. Additionally, the setting update display flag and setting confirmation display flag, both located in the work area 221 for specific control, are cleared to "0". The setting update area 342, described later, located in the work area 221 for specific control, is also cleared to "0". The RAM clear process also clears the stack area 222 for specific control to "0" and performs initial settings. Furthermore, the RAM clear process clears various registers of the main CPU 63 to "0" before performing initial settings. This initial setting performs the same processing as the internal function register setting process in step SA402.

Subsequently, it is determined whether the setting key insertion unit 68a is ON using the setting key (step SA417). If it is ON (step SA417: YES), the setting value update process is executed (step SA418). The setting value update process will be explained later.

If the process in step SA411 is executed, if a negative result is obtained in step SA414, if the process in step SA415 is executed, if a negative result is obtained in step SA417, or if the process in step SA418 is executed, information corresponding to the initial check period (specifically 5 seconds) is set in the check counter provided in the work area 221 for specific control (step SA419). The value set in the check counter is decremented by 1 each time the second timer interrupt process (Figure 134) is activated, similar to the 35th embodiment described above. If a value of 1 or more is set in the check counter, the check display continues on the first to fourth notification display devices 201 to 204, similar to the 35th embodiment described above.

According to the above configuration, when power supply to the main CPU 63 begins, the initial check period starts after the power supply start processing (steps SA401 to SA418) is completed in the main CPU 63, but before the remaining processing (steps SA422 to SA425) begins. This eliminates the need to control the initial check period while the power supply start processing is running, thus reducing the processing load during this time.

Furthermore, while the setting confirmation process (step SA415) and the setting value update process (step SA418) are executed as processes at the start of power supply, the initial check period begins after the power supply start process is completed. This ensures that even if check displays are shown on the first to fourth notification display devices 201 to 204 during the initial check period, it does not affect the display of setting values using the first to fourth notification display devices 201 to 204.

Subsequently, the startup processing flag in the work area 221 for specific control is cleared to "0" (step SA420). Because the startup processing flag is cleared to "0", if the first timer interrupt processing (Figure 133) is activated, a negative check is performed in step S8906. This ensures that not only the processes in steps S8901 to S8905 are executed, but also the processes in steps S8907 to S8920, thus resolving the state where the processes necessary to advance the game are not executed. Note that in step SA420, the power outage flag in the work area 221 for specific control is also cleared to "0".

Subsequently, a recovery command is transmitted to the voice and light emission control device 81 (step SA421). The content of the information included in the recovery command and the processing performed by the voice and light emission control device 81 upon receiving the recovery command are the same as those in step S7920 of the main processing (Figure 114) in the 33rd embodiment described above.

Subsequently, the process proceeds to the residual processing steps SA422 to SA425. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt process (Figure 133) and the second timer interrupt process (Figure 134), but residual time occurs between one timer interrupt process and the next. This residual time varies depending on the processing completion time of each timer interrupt process, and the residual processing steps SA422 to SA425 are repeatedly executed using this irregular time. In this respect, the residual processing steps SA422 to SA425 can be considered an irregular process that is executed irregularly. Steps SA422 to SA425 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

Next, the configuration of the setpoint values in this embodiment will be described. Figure 154 is an explanatory diagram illustrating the contents of the storage area for setpoint values provided in the work area 221 for specific control.

As shown in Figure 154, the work area 221 for specific control is provided with a setting reference area 341 and a setting update area 342. The setting reference area 341 is a storage area where information for identifying the current setting values of the pachinko machine 10 by the main CPU 63 is stored. In step S503 of the special feature variation start processing (Figure 13), the current setting values of the pachinko machine 10 are identified using the information stored in the setting reference area 341, and the win/fail table corresponding to the identified setting values is read. Then, in step S504, the win/fail judgment process is executed using the read win/fail table. Furthermore, when the setting confirmation display flag in the work area 221 for specific control is set to "1", the setting values corresponding to the information stored in the setting reference area 341 are displayed on the fourth notification display device 204.

Numerical information is stored in the setting reference area 341 as information about the setting value. Specifically, if the numerical information "1" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 is "Setting 1". If the numerical information "2" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 is "Setting 2". If the numerical information "3" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 is "Setting 3". If the numerical information "4" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 is "Setting 4". If the numerical information "5" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 is "Setting 5". If the numerical information "6" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 is "Setting 6".

The setting update area 342 stores information about the setting value being updated during the setting value update process (step SA418). In other words, during the setting value update process (step SA418), the information about the selected setting value is updated each time the reset button 68c is pressed. However, during this update, the setting value information stored in the setting reference area 341 remains unchanged, while the setting value information stored in the setting update area 342 is changed. This makes it possible to update the setting value while retaining the setting value information that was set before the setting value update process (step SA418) began. When the setting value update process (step SA418) is completed, the setting value information stored in the setting update area 342 at that time is overwritten in the setting reference area 341. As a result, the setting value resulting from the update in the setting value update process (step SA418) is set as the current setting value of the pachinko machine 10. Furthermore, when the setting update display flag in the specific control work area 221 is set to "1", the setting value corresponding to the information stored in the setting update area 342 is displayed on the fourth notification display device 204.

Numerical information is stored in the setting update area 342 as information about the setting value. Specifically, if the numerical information "1" is stored in the setting update area 342, the setting value of the update target (selection target or change target) will be "Setting 1". If the numerical information "2" is stored in the setting update area 342, the setting value of the update target will be "Setting 2". If the numerical information "3" is stored in the setting update area 342, the setting value of the update target will be "Setting 3". If the numerical information "4" is stored in the setting update area 342, the setting value of the update target will be "Setting 4". If the numerical information "5" is stored in the setting update area 342, the setting value of the update target will be "Setting 5". If the numerical information "6" is stored in the setting update area 342, the setting value of the update target will be "Setting 6".

Figure 155 is a flowchart showing the configuration verification process executed in step SA415 of the main process (Figure 153). Note that steps SA501 to SA504 in the configuration verification process are executed using the specific control program and specific control data in the main CPU 63.

Assuming that the setting confirmation display flag in the work area 221 for specific control is not set to "1" (step SA501: NO), the setting confirmation display flag is set to "1" (step SA502). When the setting confirmation display flag is set to "1", a positive determination is made in step S9005 of the second timer interrupt processing (Figure 134), and the setting process for the fifth display data buffer 275 during setting confirmation (step S9006) is executed.

Figure 156 is a flowchart showing the setting process for the fifth display data buffer 275 during setting verification. Note that steps SA601 to SA603 in this setting process are executed using a specific control program and specific control data in the main CPU 63.

First, the display data for the setting value corresponding to the setting value information stored in the setting reference area 341 of the work area 221 for specific control is read (step SA601). Then, the read display data for the setting value is set in the fifth display data buffer 275 in the work area 221 for specific control as display data to be applied to the fourth notification display device 204 (step SA602). Furthermore, display data to indicate that the setting value of the pachinko machine 10 is being checked is set in the fifth display data buffer 275 (step SA603).

As described above, the setting process for the fifth display data buffer 275 is executed during the setting confirmation process. In step SA603, the display data set in the fifth display data buffer 275 is displayed on the first to third notification display devices 201 to 203, and in step SA602, the display data set in the fifth display data buffer 275 is displayed on the fourth notification display device 204. As a result, for example, as shown in the explanatory diagram in Figure 124(b), displays indicating that the setting values of the pachinko machine 10 are being confirmed and displays indicating the current setting values of the pachinko machine 10 are shown on the first to fourth notification display devices 201 to 204.

Returning to the explanation of the setting confirmation process (Figure 155), if a positive determination is made in step SA501 or if the process in step SA502 is executed, it is determined whether the setting key insertion unit 68a has switched from the ON state to the OFF state using the setting key (step SA503). Specifically, it is determined whether the reception state of the signal received from the detection sensor that detects the state of the setting key insertion unit 68a has changed from a reception state corresponding to the ON state to a reception state corresponding to the OFF state. Therefore, a negative determination is made in step SA503 not only when the setting key insertion unit 68a is maintained in the ON state, but also when the setting confirmation process is started while the setting key insertion unit 68a is in the OFF state and that OFF state is maintained. If it is not determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SA503: NO), the process in step SA503 is repeated.

When it is determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SA503: YES), the setting confirmation display flag in the work area 221 for specific control is cleared to "0" (step SA504). As a result, a negative determination is made in step S9005 of the second timer interrupt processing (Figure 134), preventing the setting process to the fifth display data buffer 275 during setting confirmation (step S9006). Therefore, the display indicating that the current setting value of the pachinko machine 10 is being checked and the display showing the current setting value of the pachinko machine 10 are cancelled on the first to fourth notification display devices 201 to 204.

As described above, when the power of the pachinko machine 10 is turned ON with the setting key insertion section 68a activated by the setting key without pressing the reset button 68c, power is supplied to the main CPU 63 and the main processing (Figure 153) begins. In this state, the reset button 68c is not pressed and the setting key insertion section 68a is ON. Therefore, the setting confirmation process (Figure 155) is executed while the power supply start process is running, before the process enabling gameplay is executed in the main processing (Figure 153). This makes it possible to check the setting value even when gameplay is not taking place.

Figure 157 is a flowchart showing the setting value update process executed in step SA418 of the main process (Figure 153). Note that the processing in steps SA701 to SA710 of the setting value update process is executed using the specific control program and specific control data in the main CPU 63.

First, it is determined whether the setting update display flag in the work area 221 for specific control is set to "1" (step SA701). If the setting update display flag is not set to "1" (step SA701: NO), the setting update display flag is set to "1" (step SA702). Then, the setting value information stored in the setting reference area 341 in the work area 221 for specific control is overwritten in the setting update area 342 in the work area 221 for specific control (step SA703). As a result, the setting value information that was set when the power supply was last stopped is set in the setting update area 342.

On the other hand, if the power supply is interrupted while the setting value update process is being executed, and then resumed, and the setting value update process starts without executing the RAM clear process (step SA416) of the main process (Figure 153), and the setting value update display flag is already set to "1" (step SA701: YES), then the process in step SA703 is not executed. In this case, the setting value information that was set in the setting value update area 342 during the setting value update process before the power supply was interrupted is maintained, and the processes from step SA704 onwards are executed.

If the setting update display flag is set to "1", a positive determination is made in step S9003 of the second timer interrupt processing (Figure 134), and the setting process for the fifth display data buffer 275 during the setting update (step S9004) is executed.

Figure 158 is a flowchart showing the setting process for the fifth display data buffer 275 during a setting update. Note that steps SA801 to SA803 in this setting process are executed using a specific control program and specific control data in the main CPU 63.

First, the display data for the setting value corresponding to the setting value information stored in the setting update area 342 of the work area 221 for specific control is read (step SA801). Then, the read display data for the setting value is set in the fifth display data buffer 275 in the work area 221 for specific control as display data to be applied to the fourth notification display device 204 (step SA802). Furthermore, display data to indicate that the setting value of the pachinko machine 10 is being updated is set in the fifth display data buffer 275 (step SA803).

As described above, the setting process for the fifth display data buffer 275 is executed during the setting update. Therefore, in step SA803, the display corresponding to the display data set in the fifth display data buffer 275 is displayed on the first to third notification display devices 201 to 203, and in step SA802, the display corresponding to the display data set in the fifth display data buffer 275 is displayed on the fourth notification display device 204. As a result, for example, as shown in the explanatory diagram in Figure 124(a), the first to fourth notification display devices 201 to 204 display an indication that the setting values of the pachinko machine 10 are being updated, and the setting values selected as the update target for the pachinko machine 10 are displayed.

Returning to the explanation of the setting value update process (Figure 157), if a positive determination is made in step SA701 or if the process in step SA703 is executed, it is determined whether the setting value information stored in the setting update area 342 is one of "1" to "6" (step SA704). If it is not one of "1" to "6" (step SA704: NO), "1" is set in the setting update area 342 (step SA705). As a result, the setting value to be updated becomes "Setting 1".

If a positive determination is made in step SA704 or the process in step SA705 is executed, it is determined whether the setting key insertion unit 68a has switched from the ON state to the OFF state using the setting key (step SA706). Specifically, it is determined whether the reception state of the signal received from the detection sensor that detects the state of the setting key insertion unit 68a has changed from a reception state corresponding to the ON state to a reception state corresponding to the OFF state. Therefore, a negative determination is made in step SA706 not only when the setting key insertion unit 68a is maintained in the ON state, but also when the setting value update process is started while the setting key insertion unit 68a is in the OFF state and that OFF state is maintained.

If a negative result is obtained in step SA706, and assuming the reset button 68c is pressed (step SA707: YES), the value in the setting update area 342 is incremented by 1 (step SA708). This means that each time the reset button 68c is pressed, the setting is updated to one level higher. If the reset button 68c is not pressed (step SA707: NO) or if the value in the setting update area 342 is incremented by 1, the process returns to step SA704. However, if step SA704 determines that the value in the setting update area 342 is 7 or greater, then in step SA705, "1" is set in the setting update area 342. This means that if the reset button 68c is pressed once while in the "setting 6" state, the setting will return to "setting 1".

When it is determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SA706: YES), the setting value information stored in the setting update area 342 is overwritten in the setting reference area 341 (step SA709). As a result, the setting value information resulting from the current setting value update process is set in the setting reference area 341, and the setting value corresponding to that set information becomes the current setting value of the pachinko machine 10.

Subsequently, the setting update display flag in the work area 221 for specific control is cleared to "0" (step SA710). This results in a negative judgment being made in step S9003 of the second timer interrupt processing (Figure 134), preventing the setting process to the fifth display data buffer 275 during the setting update (step S9004). Therefore, the display indicating that the current settings of the pachinko machine 10 are being updated, and the display of the selected setting for updating the pachinko machine 10, are cancelled on the first to fourth notification display devices 201 to 204.

As described above, in addition to pressing the reset button 68c while turning on the power of the pachinko machine 10, the setting key insertion unit 68a is also turned on using the setting key while turning on the power of the pachinko machine 10. Based on this, not only is the RAM clear process (step SA416) executed, but the setting value update process (Figure 157) is also executed. Furthermore, as already explained, the setting confirmation process (Figure 155) is executed based on the setting key insertion unit 68a being turned on using the setting key without pressing the reset button 68c. This makes it possible to standardize the ON operation on the setting key insertion unit 68a as the operation required to execute setting-related processing. Therefore, the operation required to trigger setting-related processing can be made easily understandable to the administrator of the gaming hall.

Furthermore, when the setting key insertion unit 68a is turned ON using the setting key while the power of the pachinko machine 10 is turned ON, if the reset button 68c is not pressed, a setting confirmation process is executed. If the reset button 68c is pressed, a setting value update process is executed. This makes it possible to differentiate between the setting confirmation process and the setting value update process depending on whether the reset button 68c is pressed. Therefore, it becomes possible to make the operation content for executing the desired process among the setting confirmation process and the setting value update process easy for the administrator of the gaming hall to understand. Also, by making the operation content for executing the setting value update process more extensive than that for the setting confirmation process, it becomes particularly difficult to perform acts that fraudulently execute the setting value update process.

Next, we will explain the process executed in the main process (Figure 153) when power is restored after a power outage occurs while the setting value update process (Figure 157) or the setting confirmation process (Figure 155) is being executed, referring to the explanatory diagram in Figure 159.

First, we will explain the process executed in the main process (Figure 153) when power is restored after a power outage occurs while neither the setting value update process (Figure 157) nor the setting confirmation process (Figure 155) has been executed.

If the setting key insertion unit 68a is not turned ON and the reset button 68c is not pressed, and the power supply is resumed (i.e., "no operation"), the main process (Figure 153) does not execute any of the following: RAM clearing process (step SA416), setting value update process (step SA418), or setting confirmation process (step SA415). If the setting key insertion unit 68a is not turned ON, but the reset button 68c is pressed and the power supply is resumed (i.e., "RAM clearing operation"), the main process (Figure 153) executes the RAM clearing process (step SA416), while the setting value update process (step SA418) and the setting confirmation process (step SA415) are not executed. When the setting key insertion section 68a is turned ON and the reset button 68c is pressed while the power supply is restored (i.e., a "setting change operation" is performed), the main process (Figure 153) executes the RAM clear process (step SA416) and the setting value update process (step SA418), while the setting confirmation process (step SA415) is not executed. When the setting key insertion section 68a is turned ON but the reset button 68c is not pressed while the power supply is restored (i.e., a "setting confirmation operation" is performed), the setting confirmation process (step SA415) is executed, while the RAM clear process (step SA416) and the setting value update process (step SA418) are not executed.

Next, we will explain the process executed in the main process (Figure 153) when power is restored after a power outage occurs while the setting value update process (step SA418) is being executed (i.e., when the setting update display flag is set to "1").

If the power supply is restored while a "RAM clear operation" has been performed, the main process (Figure 153) will execute the RAM clear process (step SA416), while the setting value update process (step SA418) and the setting confirmation process (step SA415) will not be executed. In other words, even if the power outage process is executed while the setting value update process (step SA418) is being executed, if a "RAM clear operation" is performed when the power supply is restored, the RAM clear process (step SA416) will be executed without restarting or re-executing the setting value update process (step SA418). This makes it possible to prioritize the execution of only the RAM clear process (step SA416) in response to a "RAM clear operation". In this case, if the power outage processing was executed before the processing in step SA709 was executed during the setting value update processing (step SA418), the information of the setting value updated in the setting value update processing (step SA418) (i.e., the changed setting value) is not set in the setting reference area 341. Therefore, the setting value that was set before the setting value update processing (step SA418) started will remain in use even after the power supply is restored. Note that the setting update display flag is cleared to "0" when the RAM clear processing (step SA416) is executed.

If power is restored while a "setting change operation" has been performed, the main process (Figure 153) executes both the RAM clear process (step SA416) and the setting value update process (step SA418), while the setting confirmation process (step SA415) is not executed. In other words, even if the power outage process is executed while the setting value update process (step SA418) is running, if a "setting change operation" is performed upon the subsequent restoration of power, the RAM clear process (step SA416) will be executed, followed by a new start of the setting value update process (step SA418).

As previously explained, when the RAM clear process (step SA416) is executed, the setting update display flag in the work area 221 for specific control is cleared to "0". Therefore, in the setting value update process (Figure 157), a negative determination is made in step SA701, overwriting the setting value information stored in the setting reference area 341 with the setting update area 342. Consequently, if the power outage processing was executed before the processing in step SA709 during the setting value update process (step SA418) before the power supply was stopped, the setting value information updated in that setting value update process (step SA418) is invalid because it is not set in the setting reference area 341. In this case, the setting value update process (step SA418) after the power supply is resumed will update the setting value from the setting value that was set before the setting value update process (step SA418) before the power supply was stopped began.

If the power supply is restored in a "no operation" state, or if the power supply is restored after a "setting confirmation operation" has been performed, the main process (Figure 153) makes a positive determination in step SA412, provided that no abnormalities have occurred with respect to the power outage flag and checksum. As a result, the setting value update process (step SA418) is executed without the RAM clear process (step SA416). If the RAM clear process (step SA416) is not executed, the setting update display flag in the work area 221 for specific control remains set to "1". Therefore, in the setting value update process (Figure 157), a positive determination is made in step SA701, and the setting value information in the setting update area 342 is maintained as is. Consequently, the setting value update will resume from the setting value that was being updated in the setting value update process (step SA418) before the power supply was stopped. This means that if a power outage process is executed during the setting value update process (step SA418), and a "RAM clear operation" is not performed when the power supply is restored, the setting value update process (step SA418) can be resumed even if a "setting change operation" is not performed.

In particular, it is conceivable that the power to the pachinko machine 10 might be accidentally turned OFF during the setting value update process (step SA418). In this case, the power to the pachinko machine 10 would likely be turned ON immediately. In this scenario, it is assumed that the power to the pachinko machine 10 would be turned ON without pressing the reset button 68c while the setting key insertion unit 68a remains ON. This would result in the power supply resuming while the "setting confirmation operation" is still in progress. In this situation, the setting value update process (step SA418) is executed as described above, and the update of the setting value resumes from the setting value that was being updated before the power supply was stopped during the setting value update process (step SA418). Therefore, even if the above-mentioned event occurs, the setting value update can be resumed without any problems.

Next, we will explain the process executed in the main process (Figure 153) when power is restored after a power outage occurs while the setting confirmation process (step SA415) is running (i.e., the setting confirmation display flag is set to "1").

If power is restored after a "RAM clear operation" has been performed, the main process (Figure 153) will execute the RAM clear process (step SA416), while the setting value update process (step SA418) and the setting confirmation process (step SA415) will not be executed. In other words, even if the power outage process is executed while the setting confirmation process (step SA415) is running, if a "RAM clear operation" is performed upon the subsequent restoration of power, the RAM clear process (step SA416) will be executed without re-executing the setting confirmation process (step SA415). This allows for prioritizing the execution of only the RAM clear process (step SA416) in response to a "RAM clear operation." Note that the setting confirmation display flag is cleared to "0" upon execution of the RAM clear process (step SA416).

If the power supply is restored while a "setting change operation" has been performed, the main process (Figure 153) will execute the RAM clear process (step SA416) and the setting value update process (step SA418), while the setting confirmation process (step SA415) will not be executed. In other words, even if the power outage process is executed while the setting confirmation process (step SA415) is being executed, if a "setting change operation" is performed when the power supply is restored afterward, the setting confirmation process (step SA415) will not be executed again, and the setting value update process (step SA418) will be executed after the RAM clear process (step SA416). This makes it possible to prioritize the execution of the RAM clear process (step SA416) and the setting value update process (step SA418) in response to a "setting change operation". Furthermore, even if the setting confirmation process (step SA415) is not executed, the setting value update process (step SA418) is executed, displaying the setting value to be updated on the fourth notification display device 204. Additionally, upon completion of the setting value update process (step SA418), the information of the setting value to be updated at that time is set in the setting reference area 341. Therefore, the administrator of the amusement hall can confirm the current setting value of the pachinko machine 10. Note that the setting confirmation display flag is cleared to "0" when the RAM clear process (step SA416) is executed.

If the power supply is restored while the "settings confirmation operation" has been performed, the main process (Figure 153) executes the settings confirmation process (step SA415) on the condition that no abnormalities have occurred regarding the power outage flag and checksum. This ensures that even if the power outage processing is executed during the settings confirmation process (step SA415), the settings can be resumed by performing the "settings confirmation operation" when the power supply is restored.

If the power supply is restored in a "no operation" state, the main process (Figure 153) performs a positive determination in step SA414, provided that no abnormalities have occurred regarding the power outage flag and checksum. This allows the setting confirmation process (step SA415) to be executed even if the setting key insertion unit 68a has not been turned ON. This makes it possible to resume checking the setting value even if the power outage processing is executed during the setting confirmation process (step SA415) and the power supply is restored in a "no operation" state afterward.

Next, the termination timing of the setting value update process (Figure 157) and the setting confirmation process (Figure 155) in relation to the operating state of the setting key insertion unit 68a will be explained with reference to the time chart in Figure 160. Figure 160(a) shows the period when the power of the pachinko machine 10 is ON, Figure 160(b) shows the period when the setting key insertion unit 68a is ON, Figure 160(c) shows the period when the setting value update process (Figure 157) is being executed, Figure 160(d) shows the period when the setting confirmation process (Figure 155) is being executed, and Figure 160(e) shows the period when the power outage process is being executed.

First, we will explain the normal procedure in which the setting value update process (Figure 157) and the setting confirmation process (Figure 155) are executed.

At timing t1, the setting key insertion unit 68a is turned ON using the setting key, as shown in Figure 160(b). Then, at timing t2, the power to the pachinko machine 10 is turned ON, as shown in Figure 160(a). In this case, the reset button 68c is also pressed. Therefore, at timing t3, the setting value update process (Figure 157) begins, as shown in Figure 160(c). Subsequently, at timing t4, the setting key insertion unit 68a changes from the ON state to the OFF state, as shown in Figure 160(b). This completes the setting value update process (Figure 157), as shown in Figure 160(c).

Furthermore, at timing t5, the setting key insertion unit 68a is turned ON using the setting key, as shown in Figure 160(b). Then, at timing t6, the power to the pachinko machine 10 is turned ON, as shown in Figure 160(a). In this case, the reset button 68c is not pressed. Therefore, at timing t7, the setting confirmation process (Figure 155) is started, as shown in Figure 160(d). Subsequently, at timing t8, the setting key insertion unit 68a changes from the ON state to the OFF state, as shown in Figure 160(b). This completes the setting confirmation process (Figure 155), as shown in Figure 160(d).

Next, we will explain the case where the power outage processing is executed during the setting value update process (Figure 157), and the situation is "no operation" when the power supply is restored.

At timing t9, the setting key insertion unit 68a is turned ON using the setting key, as shown in Figure 160(b). Then, at timing t10, the power to the pachinko machine 10 is turned ON, as shown in Figure 160(a). In this case, the reset button 68c is also pressed. Therefore, at timing t11, the setting value update process (Figure 157) begins, as shown in Figure 160(c). Then, at timing t12, while the setting value update process (Figure 157) is in progress, the power to the pachinko machine 10 is turned OFF, either due to a power OFF operation or a sudden power outage, as shown in Figure 160(a). As a result, the power outage processing begins, as shown in Figure 160(e). In this case, the setting value update process (Figure 157) ends at timing t12, as shown in Figure 160(c), and the power outage processing ends at timing t13, as shown in Figure 160(e).

Subsequently, at timing t14, the setting key insertion unit 68a is turned OFF as shown in Figure 160(b), and in this state, at timing t15, the power of the pachinko machine 10 is turned ON as shown in Figure 160(a). In this case, the reset button 68c is not pressed. In other words, the power of the pachinko machine 10 is turned ON in a "no operation" state. However, when the power of the pachinko machine 10 was turned OFF last time, the power outage processing was executed in the middle of the setting value update processing (Figure 157). Therefore, at timing t16, the setting value update processing (Figure 157) is started as shown in Figure 160(c). In this case, the setting value update process (Figure 157) terminates when it is determined that the setting key insertion unit 68a has switched from an ON state to an OFF state. Therefore, even if the setting key insertion unit 68a remains in the OFF state from the start of the setting value update process (Figure 157), the termination condition for the setting value update process (Figure 157) will not be met.

Subsequently, at time t17, while the setting value update process (Figure 157) is being executed, the setting key insertion unit 68a is turned ON using the setting key, as shown in Figure 160(b). Then, at time t18, the setting key insertion unit 68a changes from the ON state to the OFF state, as shown in Figure 160(b). This completes the setting value update process (Figure 157), as shown in Figure 160(c).

Next, we will explain the case where the power outage processing is executed during the configuration confirmation process (Figure 155), and the situation is "no operation" when the power supply is restored.

At timing t19, the setting key insertion unit 68a is turned ON using the setting key, as shown in Figure 160(b). Then, at timing t20, the power to the pachinko machine 10 is turned ON, as shown in Figure 160(a). In this case, the reset button 68c is not pressed. Therefore, at timing t21, the setting confirmation process (Figure 155) is started, as shown in Figure 160(d). Then, at timing t22, while the setting confirmation process (Figure 155) is in progress, the power to the pachinko machine 10 is turned OFF, either due to a power OFF operation or a sudden power outage, as shown in Figure 160(a). As a result, the power outage processing is started, as shown in Figure 160(e). In this case, at timing t22, the setting confirmation process (Figure 155) ends, as shown in Figure 160(d), and at timing t23, the power outage processing ends, as shown in Figure 160(e).

Subsequently, at timing t24, the setting key insertion unit 68a is turned OFF as shown in Figure 160(b), and in this state, at timing t25, the power of the pachinko machine 10 is turned ON as shown in Figure 160(a). In this case, the reset button 68c is not pressed. In other words, the power of the pachinko machine 10 is turned ON in a "no operation" state. However, when the power of the pachinko machine 10 was turned OFF last time, the power outage processing was executed in the middle of the setting confirmation processing (Figure 155). Therefore, at timing t26, the setting confirmation processing (Figure 155) is started as shown in Figure 160(d). In this case, the setting confirmation process (Figure 155) terminates when it is determined that the setting key insertion unit 68a has switched from the ON state to the OFF state. Therefore, even if the setting key insertion unit 68a remains in the OFF state from the start of the setting confirmation process (Figure 155), the termination condition of the setting confirmation process (Figure 155) will not be met.

Subsequently, at time t27, while the setting confirmation process (Figure 155) is being executed, the setting key insertion unit 68a is turned ON using the setting key, as shown in Figure 160(b). Then, at time t28, the setting key insertion unit 68a changes from the ON state to the OFF state, as shown in Figure 160(b). This completes the setting confirmation process (Figure 155), as shown in Figure 160(d).

The embodiment described in detail above provides the following excellent effects.

In order for the setting value update process (Figure 157) to be executed, it is necessary to perform a "setting change operation" by turning on the setting key insertion unit 68a and pressing the reset button 68c when the power supply is started. This makes it difficult to attempt to illegally change the setting value. In this case, if the power supply is stopped while the setting value update process (Figure 157) is being executed, the setting value update process (Figure 157) may be executed when the power supply is resumed, even if the "setting change operation" has not been performed. This makes it possible to prioritize the execution of the setting value update process (Figure 157).

If the power supply is interrupted while the setting value update process (Figure 157) is being executed, and then the power supply is restored, a "setting confirmation operation" to verify the setting value will be performed. Instead of the setting confirmation process (Figure 155), the setting value update process (Figure 157) will be executed. This allows for prioritizing setting value changes over setting value verification, preventing gameplay from starting before the target setting value has actually been changed.

When the setting value update process (Figure 157) is being executed, the setting value selected for update is displayed on the first to fourth notification display devices 201 to 204. This makes it possible to change the setting value while being aware of the setting value selected for update. Furthermore, because the setting value selected for update is displayed in this way, even in configurations where the setting value update process (Figure 157) takes priority when the power supply is restored, it is still possible to effectively verify the setting value.

When the setting value update process (Figure 157) is being executed, the first to fourth notification display devices 201 to 204 will display not only the setting value selected for update, but also a display indicating that the setting value update process (Figure 157) is being executed. This makes it easier for the gaming hall manager to understand that the setting value update process (Figure 157) has started, even if the "setting confirmation operation" has been performed when the power supply is restored.

If the power supply is interrupted while the setting value update process (Figure 157) is being executed, and then the power supply is resumed, and either "no operation" or "setting confirmation operation" is performed, the setting value will be changed from the value selected before the power supply was interrupted. This allows the setting value to continue changing from the value selected before the power supply was interrupted.

If the power supply is interrupted while the setting value update process (Figure 157) is being executed, and then a "setting change operation" is performed when the power supply is subsequently restored, the setting value will be changed from the currently used setting value. This makes it possible to differentiate the initial setting value when initiating a setting value change depending on the operation performed when the power supply is restored.

Even if the power supply is interrupted while the setting value update process (Figure 157) is being executed, if a "RAM clear operation" is performed when the power supply is restored, the setting value update process (Figure 157) will not be executed. Therefore, even if the power supply is interrupted while the setting value update process (Figure 157) is being executed, if there is no need to perform the setting value update process (Figure 157) afterward, performing a "RAM clear operation" when the power supply is restored will prevent the setting value update process (Figure 157) from being executed.

In order for the setting confirmation process (Figure 155) to be executed, it is necessary to perform a "setting confirmation operation" by turning on the setting key insertion unit 68a when the power supply is started. This makes it difficult to attempt to illegally check the setting value. In this case, if the power supply is stopped while the setting confirmation process (Figure 155) is being executed, the setting confirmation process (Figure 155) may be executed when the power supply is resumed, even if the "setting confirmation operation" has not been performed. This makes it possible to prioritize the execution of the setting confirmation process (Figure 155).

Even if the power supply is interrupted while the setting confirmation process (Figure 155) is being executed, if a "setting change operation" is performed when the power supply is restored, the setting value update process (Figure 157) will be executed without executing the setting confirmation process (Figure 155). This makes it possible to prioritize the setting value change operation over the setting value confirmation operation.

The work area 221 for specific control is provided with a setting reference area 341 and a setting update area 342. Information corresponding to the setting value to be used is stored in the setting reference area 341, while information corresponding to the setting value being changed during the setting value update process (Figure 157) is stored in the setting update area 342. This allows the setting value to be changed during the setting value update process (Figure 157) while the setting reference area 341 retains the setting value information set before the setting value update process (Figure 157) began.

If the power supply is interrupted while the setting value update process (Figure 157) is being executed, and when the power supply is subsequently restored, if there is "no operation" or a "setting confirmation operation" is performed, the setting value should be changed starting from the setting value corresponding to the information stored in the setting update area 342. If a "setting change operation" is performed when the power supply is subsequently restored, the setting value should be changed starting from the setting value corresponding to the information stored in the setting reference area 341. This makes it possible to appropriately generate each of these situations.

In order to start the setting value update process (Figure 157), it is necessary to use the setting key to turn on the setting key insertion unit 68a. Therefore, it is possible to make it difficult to attempt to start the setting value update process (Figure 157) illegally. In this case, the setting value update process (Figure 157) will not end simply by turning off the setting key insertion unit 68a, but will end when the setting key insertion unit 68a is turned off from the ON position. As a result, even if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and the setting key insertion unit 68a is in the OFF state due to "no operation" when the power supply is subsequently restored, the setting value update process (Figure 157) will not terminate immediately. Instead, the setting value update process (Figure 157) will terminate by first turning the setting key insertion unit 68a ON and then OFF. This allows the administrator of the gaming hall to terminate the setting value update process (Figure 157) at a timing that is favorable to them.

In order to start the setting confirmation process (Figure 155), it is necessary to use the setting key to turn on the setting key insertion unit 68a. Therefore, it is possible to make it difficult to attempt to start the setting confirmation process (Figure 155) illegally. In this case, the setting confirmation process (Figure 155) does not end simply by turning off the setting key insertion unit 68a, but only ends when the setting key insertion unit 68a is turned off from the ON position. As a result, even if the power supply is interrupted while the setting confirmation process (Figure 155) is being executed, and the setting key insertion unit 68a is in the OFF state due to "no operation" when the power supply is subsequently restored, the setting confirmation process (Figure 155) will not terminate immediately. Instead, the setting confirmation process (Figure 155) will terminate by first turning the setting key insertion unit 68a ON and then OFF. This allows the administrator of the gaming hall to terminate the setting confirmation process (Figure 155) at a timing that is favorable to them.

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and "no operation" is detected upon resumption of the power supply, the setting value update process (Figure 157) is not limited to starting from the partially changed setting value before the power supply was interrupted. It may also be configured to start from the currently used setting value stored in the setting reference area 341. Additionally, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and "no operation" is detected upon resumption of the power supply, the configuration may be such that the RAM clear process (step SA416) is executed before the setting value update process (Figure 157), or vice versa.

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and the power supply is resumed, the setting value update process (Figure 157) may not be executed if there is "no operation". In this case, the setting value information stored in the setting reference area 341 may be overwritten in the setting update area 342 when the next setting value update process (Figure 157) begins.

Furthermore, if the power supply is interrupted while the configuration confirmation process (Figure 155) is being executed, and the power supply is resumed, the configuration may be configured so that the configuration confirmation process (Figure 155) is not executed if there is "no operation".

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and a "RAM clear operation" is performed when the power supply is restored, the configuration may be such that the setting value update process (Figure 157) is executed after the RAM clear process (step SA416). In this case, the setting value update process (Figure 157) may start from the setting value that was being changed before the power supply was interrupted, or it may start from the currently used setting value stored in the setting reference area 341.

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and a "RAM clear operation" is performed when the power supply is restored, the system may be configured to execute the setting value update process (Figure 157) without executing the RAM clear process (step SA416), or it may be configured to execute the RAM clear process (step SA416) after the setting value update process (Figure 157) has been executed. In this case, the setting value update process (Figure 157) may start from the setting value that was being changed before the power supply was interrupted, or it may start from the currently used setting value stored in the setting reference area 341.

Furthermore, if the power supply is interrupted while the configuration confirmation process (Figure 155) is being executed, and then a "RAM clear operation" is performed upon resuming the power supply, the configuration may be such that the configuration confirmation process (Figure 155) is executed after the RAM clear process (step SA416), or that the configuration confirmation process (Figure 155) is executed without the RAM clear process (step SA416), or that the configuration may be such that the RAM clear process (step SA416) is executed after the configuration confirmation process (Figure 155).

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and a "setting change operation" is performed when the power supply is restored, the setting value update process (Figure 157) is configured to start from the currently used setting value stored in the setting reference area 341. However, the setting value update process (Figure 157) may also be configured to start from the setting value that was being changed before the power supply was interrupted.

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and a "setting change operation" is performed when the power supply is resumed, the system may be configured to execute the setting value update process (Figure 157) without executing the RAM clear process (step SA416), or it may be configured to execute the RAM clear process (step SA416) after the setting value update process (Figure 157) has been executed. In this case, the setting value update process (Figure 157) may start from the setting value that was being changed before the power supply was interrupted, or it may start from the currently used setting value stored in the setting reference area 341.

Furthermore, if the power supply is interrupted while the setting confirmation process (Figure 155) is being executed, and a "setting change operation" is performed when the power supply is restored, the setting value update process (Figure 157) is configured to start from the currently used setting value stored in the setting reference area 341. However, the setting value update process (Figure 157) may also be configured to start from the setting value that was being changed before the power supply was interrupted.

Furthermore, if the power supply is interrupted while the setting confirmation process (Figure 155) is being executed, and then a "setting change operation" is performed upon resumption of power supply, the configuration may be such that the setting value update process (Figure 157) is executed without executing the RAM clear process (step SA416), or the configuration may be such that the RAM clear process (step SA416) is executed after the setting value update process (Figure 157).

Furthermore, if the power supply is interrupted while the setting confirmation process (Figure 155) is being executed, and a "setting change operation" is performed when the power supply is resumed, the system may be configured such that the setting confirmation process (Figure 155) is executed but the setting value update process (Figure 157) is not executed; or the setting confirmation process (Figure 155) is executed before the setting value update process (Figure 157); or the setting value update process (Figure 157) is executed before the setting confirmation process (Figure 155). Additionally, if the power supply is interrupted while the setting confirmation process (Figure 155) is being executed, and a "setting change operation" is performed when the power supply is resumed, the system may be configured such that neither the setting confirmation process (Figure 155) nor the setting value update process (Figure 157) is executed.

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and the power supply is restored, and a "setting confirmation operation" is performed, the setting value update process (Figure 157) is not limited to starting from the setting value that was partially changed before the power supply was interrupted. It may also be configured to start from the currently used setting value stored in the setting reference area 341.

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and the power supply is resumed, and a "setting confirmation operation" is performed, the configuration may be such that the RAM clear process (step SA416) is executed before the setting value update process (Figure 157), or that the setting value update process (Figure 157) is executed before the RAM clear process (step SA416).

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and the power supply is resumed, a "setting confirmation operation" may be performed without executing the setting value update process (Figure 157) if the setting confirmation process (Figure 155) is executed. In this case, the setting value information stored in the setting reference area 341 may be overwritten in the setting update area 342 when the next setting value update process (Figure 157) begins.

Furthermore, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and the power supply is resumed, and a "setting confirmation operation" is performed, the configuration may be such that the setting confirmation process (Figure 155) is executed before the setting value update process (Figure 157), or the setting confirmation process (Figure 155) is executed after the setting value update process (Figure 157). Also, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and the power supply is resumed, and a "setting confirmation operation" is performed, the configuration may be such that neither the setting confirmation process (Figure 155) nor the setting value update process (Figure 157) is executed.

Furthermore, when the setting update display flag in the work area 221 for specific control is set to "1" and power supply is started, the system is not limited to a configuration where, after a predetermined wait time has elapsed in the power-on initial setup process (step SA401), the interrupt for the second timer interrupt process (Figure 134) is permitted, and a display indicating that the setting value is being updated and a display showing the setting value corresponding to the information stored in the setting update area 342 are started on the first to fourth notification display devices 201 to 204. These displays may also be started without waiting for the predetermined wait time to elapse. Alternatively, even if the setting update display flag is set to "1", the system may be configured so that the display indicating that the setting value is being updated and a display showing the setting value corresponding to the information stored in the setting update area 342 are performed only if the setting value update process (Figure 157) is being executed. In this case, it becomes possible to prevent these displays from being shown when the setting value update process (Figure 157) is not being executed.

Furthermore, if the setting confirmation display flag in the work area 221 for specific control is set to "1" and power supply is started, the system is not limited to a configuration where, after a predetermined wait time has elapsed in the power-on initial setup process (step SA401), the interrupt for the second timer interrupt process (Figure 134) is permitted, and a display indicating that the setting value is being checked and a display showing the setting value corresponding to the information stored in the setting reference area 341 are started on the first to fourth notification display devices 201 to 204. These displays may also be started without waiting for the predetermined wait time to elapse. Alternatively, even if the setting confirmation display flag is set to "1", the system may be configured so that, provided that the setting confirmation process (Figure 155) is being executed, a display indicating that the setting value is being checked and a display showing the setting value corresponding to the information stored in the setting update area 342 are shown on the first to fourth notification display devices 201 to 204. In this case, it becomes possible to prevent these displays from being shown when the setting confirmation process (Figure 155) is not being executed.

Furthermore, when the setting value update process (Figure 157) is being executed, the system may be configured to display an image on the symbol display device 41 indicating that the setting value is being updated, or, in addition to or instead of this display, an image showing the operating procedure for updating the setting value may be displayed, or the display light-emitting unit 53 or speaker unit 54 may provide notification indicating that the setting value is being updated. In this case, it becomes possible to clearly inform the administrator of the gaming hall that the setting value update process (Figure 157) is being executed.

Furthermore, when the setting confirmation process (Figure 155) is being executed, the system may be configured to display an image on the symbol display device 41 indicating that the setting value is being confirmed. Alternatively, an image showing the operating procedure for confirming the setting value may be displayed in addition to or instead of this image. The system may also be configured to provide notification via the display light-emitting unit 53 or speaker unit 54 indicating that the setting value is being confirmed. In this case, it becomes possible to clearly inform the administrator of the gaming hall that the setting confirmation process (Figure 155) is being executed.

Furthermore, the operating unit used to update the setting value in the setting value update process (Figure 157) is not limited to the reset button 68c; it may be a dedicated operating unit such as an update button 68b, or an operating unit provided on the main control device 60 to clear abnormal conditions. Also, when a setting key is inserted into the setting key insertion unit 68a and rotated, positions corresponding to "Setting 1" to "Setting 6" may be set, and the setting value corresponding to the rotation position of the setting key insertion unit 68a may be set. Furthermore, the setting key insertion unit 68a may be configured to be able to be rotated beyond the ON position, and each time a rotation beyond the ON position is performed, the setting value being updated is updated to the setting value in the next sequence.

Furthermore, when the setting value update process (Figure 157) is executed, the pachinko machine 10 may be configured to output a corresponding signal to the management computer of the gaming hall. In this case, the signal output may be configured to occur over a predetermined period (for example, 100 milliseconds), and the signal output may continue while the setting value update process (Figure 157) is being executed. This makes it possible for the management computer of the gaming hall to be aware that the setting value update process (Figure 157) has been executed in the pachinko machine 10.

Furthermore, when the setting confirmation process (Figure 155) is executed, the pachinko machine 10 may be configured to output a corresponding signal to the management computer of the gaming hall. In this case, the signal output may be performed for a predetermined period (for example, 100 milliseconds), and the signal output may continue while the setting confirmation process (Figure 155) is being executed. This allows the management computer of the gaming hall to recognize that the setting confirmation process (Figure 155) has been executed in the pachinko machine 10.

Furthermore, a configuration that terminates processing when the key insertion unit changes from the ON state to the OFF state may be applied to processes other than the setting confirmation process (Figure 155) and the setting value update process (Figure 157). For example, a configuration may be set where a predetermined key insertion unit needs to be operated to the ON position in order to display the base value on the first to fourth notification display devices 201 to 204, and where the display terminates when it is determined that the predetermined key insertion unit has changed from the ON state to the OFF state.

Furthermore, the configuration may include a condition for initiating the setting value update process (Figure 157) that at least one of the target objects, either the game machine body 12 or the front door frame 14, must be opened. In this configuration, if the power supply is interrupted while the setting value update process (Figure 157) is being executed, and the power supply is restored with "no operation" or a "setting confirmation operation," the setting value update process (Figure 157) may be initiated even if the target object has not been opened.

Furthermore, the configuration may include a condition for initiating the setting confirmation process (Figure 155) that at least one of the target objects, either the game machine body 12 or the front door frame 14, must be opened. In this configuration, if the power supply is interrupted while the setting confirmation process (Figure 155) is running, and there is "no operation" upon resuming the power supply, the setting confirmation process (Figure 155) may be initiated even if the target object has not been opened.

Furthermore, the RAM clear process executed before the setting value update process (Figure 157) and the RAM clear process executed without the setting value update process may be configured to initialize different areas in the main RAM 65.

Furthermore, if the setting update display flag is not set to "1" when the setting value update process (Figure 157) is started, the configuration is not limited to changing the setting value from the setting value corresponding to the information stored in the setting reference area 341. It may also be configured to change the setting value from a predetermined initial setting value. This initial value could be, for example, "Setting 1," "Setting 6," or any other setting value.

Furthermore, in addition to or instead of the configuration in which the setting value update process (Figure 157) is executed as a process at the start of power supply, the setting value update process (Figure 157) may be executed based on the status after the power supply start process has been completed, based on the fact that a "setting change operation" has been performed. Even in this configuration, if the setting value update process (Figure 157) is completed before the normal termination trigger occurs, the setting value update process (Figure 157) will be executed even if no "setting change operation" has been performed, thereby prioritizing the setting value change operation.

Furthermore, in addition to or instead of the configuration in which the setting confirmation process (Figure 155) is executed as a process when the power supply to the operating system starts, the setting confirmation process (Figure 155) may be executed based on the fact that a "setting confirmation operation" has been performed after the process for starting the power supply to the operating system has finished. Even in this configuration, if the setting confirmation process (Figure 155) is completed before the normal termination trigger occurs, the setting confirmation process (Figure 155) will be executed even if a "setting confirmation operation" has not been performed, thereby prioritizing the verification of the setting value.

<46th Embodiment>
In this embodiment, the processing configuration of the main process executed by the primary CPU 63 differs from that of the 45th embodiment described above. The configurations that differ from those of the 45th embodiment will be described below. Configurations that are the same as those of the 45th embodiment will generally not be described.

Figure 161 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps SA901 to SA925 in the main processing are executed using a specific control program and specific control data on the main CPU 63.

Steps SA901 to SA904 execute the same processes as steps SA401 to SA404 of the main process (Figure 153) in the 45th embodiment described above. Then, it is determined whether the setting update display flag provided in the specific control work area 221 is set to "1" (step SA905). If the power supply is stopped and then resumed while the setting value update process (step SA918) is being executed, the main process will start with the setting update display flag set to "1".

If a negative result is obtained in step SA905, it is determined whether or not the reset button 68c is pressed (step SA906). In other words, it is determined whether or not the power of the pachinko machine 10 is turned ON and the supply of operating power to the MPU 62 begins while the reset button 68c is pressed.

If the reset button 68c is not pressed (step SA906: NO), it is determined whether the power outage flag in the work area 221 for specific control is set to "1" (step SA907). The power outage flag is set to "1" if the power outage processing is executed during the power outage information storage processing (step S8901) of the first timer interrupt processing (Figure 133). The power outage flag is used by the main CPU 63 to determine whether the power outage processing was performed appropriately during the previous power outage.

If the power outage flag is set to "1" (step SA907: YES), checksums are calculated for the work area 221 and the stack area 222 for specific control (step SA908). The method for calculating the checksums is the same as in the 33rd embodiment described above. Then, the checksums for the work area 221 and the stack area 222 for specific control, which were calculated and stored in the work area 221 during the power outage processing performed immediately before the supply of operating power to the MPU 62 was stopped, are read, and these read checksums are compared with the checksums calculated in step SA908 (step SA909). Finally, it is determined whether the checksums match (step SA910).

If a negative determination is made in step SA907 or step SA910, that is, if the power outage flag is not set to "1" or the checksum does not match, the game stop flag provided in the work area 221 for specific control is set to "1" (step SA911). Furthermore, an abnormality command indicating that an abnormality has occurred regarding the power outage flag or checksum at the start of power supply is sent to the voice and light emission control device 81 (step SA912). The processing content of steps SA911 and SA912 is the same as steps SA410 and SA411 of the main processing (Figure 153) in the 45th embodiment described above.

If the power outage flag is set to "1" and the checksum is normal (steps SA907 and SA910: YES), it is determined whether the setting key insertion unit 68a is being turned ON using the setting key (step SA913). If the setting key insertion unit 68a is being turned ON using the setting key (step SA913: YES), the setting confirmation process is executed (step SA914). The processing content of the setting confirmation process is the same as in the 45th embodiment described above. In other words, in this embodiment, even if the setting confirmation display flag provided in the work area 221 for specific control is set to "1", the setting confirmation process will not be executed unless the setting key insertion unit 68a is turned ON. Therefore, even if the power supply is stopped while the setting confirmation process is being executed, the setting confirmation process will not be executed unless the power supply is resumed in the state where the "setting confirmation operation" has been performed.

If the setting update display flag is set to "1" (step SA905: YES), or if the reset button 68c is pressed (step SA906: YES), the RAM clear process is executed (step SA915). The processing content of the RAM clear process is the same as the RAM clear process (step SA416) in the main process (Figure 153) of the 45th embodiment described above.

Subsequently, if the setting update display flag is set to "1" (step SA916: YES), the setting value update process is executed regardless of whether the setting key insertion unit 68a is turned ON or not (step SA918). On the other hand, if the setting update display flag is not set to "1" (step SA916: NO), the setting value update process is executed (step SA918), provided that the setting key insertion unit 68a is turned ON (step SA917: YES). In other words, if the power supply is stopped while the setting value update process is being executed, regardless of the operation performed when the power supply is subsequently resumed, the RAM clear process (step SA915) is executed before the setting value update process (step SA918) is started anew.

If the process in step SA912 is executed, if a negative result is obtained in step SA913, if the process in step SA914 is executed, if a negative result is obtained in step SA917, or if the process in step SA918 is executed, then the processes in steps SA919 to SA925 are executed. The content of the processes in steps SA919 to SA925 is the same as steps SA419 to SA425 of the main process (Figure 153) in the 45th embodiment described above.

Figure 162 is an explanatory diagram illustrating the process executed in the main process (Figure 161) when power is restored after a power outage occurs while the setting value update process (step SA918) or the setting confirmation process (step SA914) is being executed.

When the power outage processing is executed while neither the setting value update process (step SA918) nor the setting confirmation process (step SA914) has been executed, the content of the processing executed in the main process (Figure 161) when the power supply is subsequently restored is the same as in the 45th embodiment described above. In other words, when the power supply is restored in a "no operation" state, the main process (Figure 161) does not execute the RAM clear process (step SA915), the setting value update process (step SA918), or the setting confirmation process (step SA914). Also, when the power supply is restored while a "RAM clear operation" has been performed, the main process (Figure 161) executes the RAM clear process (step SA915), while the setting value update process (step SA918) and the setting confirmation process (step SA914) are not executed. If power supply is restored after a "setting change operation" has been performed, the main process (Figure 161) executes the RAM clear process (step SA915) and the setting value update process (step SA918), while the setting confirmation process (step SA914) is not executed. If power supply is restored after a "setting confirmation operation" has been performed, the main process (Figure 161) executes the setting confirmation process (step SA914), while the RAM clear process (step SA915) and the setting value update process (step SA918) are not executed.

Next, we will explain the process executed in the main process (Figure 161) when power outage processing is performed while the setting value update process (step SA918) is running (i.e., when the setting update display flag is set to "1"), and then power is restored.

Regardless of whether power supply is restored in a "no operation" state, a "RAM clear operation" state, a "setting change operation" state, or a "setting confirmation operation" state, the main process (Figure 161) executes the RAM clear operation (step SA915) and the setting value update operation (step SA918), while the setting confirmation operation (step SA914) is not executed. In other words, if the power outage processing is executed while the setting value update operation (step SA918) is running, regardless of the operation performed when power supply is restored, the RAM clear operation (step SA915) will be executed first, followed by a new start of the setting value update operation (step SA918).

With the above configuration, if the power supply is interrupted during the setting value update process (step SA918), when the power supply is resumed, regardless of the operation performed on the setting key insertion unit 68a and the reset button 68c when the pachinko machine 10 is powered on, the RAM clear process (step SA915) is executed before the setting value update process (step SA918) is started anew. This ensures that if the power supply is interrupted during the setting value update, the system will have a reliable opportunity to complete the setting value update when the power supply is subsequently resumed. Therefore, even if the power supply is interrupted during the setting value update, the game will not start with the setting value from before the previous setting value update process (step SA918) was started when the power supply is subsequently resumed.

Furthermore, if the power supply is interrupted during the setting value update process (step SA918), the RAM clear process (step SA915) is executed before the setting value update process (step SA918) is executed, regardless of the operation performed when the power supply is resumed. This simplifies the processing configuration compared to a configuration where the processing content is changed according to each operation, while still achieving the aforementioned excellent effects.

Next, we will explain the process executed in the main process (Figure 161) when power outage processing is performed while the setting confirmation process (step SA914) is running (i.e., when the setting confirmation display flag is set to "1"), and then power is restored.

When the power outage processing is executed while the setting confirmation process (step SA914) is running (i.e., the setting confirmation display flag is set to "1"), the processing performed by the main process (Figure 161) upon the subsequent resumption of power supply is the same as the processing performed by the main process (Figure 161) upon the resumption of power supply when the power outage processing is executed while neither the setting value update process (Figure 157) nor the setting confirmation process (Figure 155) is running. In other words, even if the power supply is interrupted while the setting confirmation process (step SA914) is running, the processing corresponding to the operation performed when the power is turned ON on the pachinko machine 10 will be executed once the power supply is resumed.

Unlike changing settings, checking settings does not affect gameplay even if the process is terminated midway and not resumed. Therefore, even if the power supply is interrupted during the setting check, the process corresponding to the operation performed when turning on the power of the pachinko machine 10 can be executed, thus prioritizing the operation performed by the administrator of the gaming hall when turning on the power.

<Embodiment 47>
In this embodiment, the content of the processing executed in the main process (Figure 161) when the power supply is restored after a power outage is executed while the setting value update process (step SA918) or the setting confirmation process (step SA914) is being executed differs from that of the 45th embodiment. The configurations that differ from the 45th embodiment will be described below. Configurations that are the same as those in the 45th embodiment will generally not be described.

Figure 163 is an explanatory diagram illustrating the process executed in the main process (Figure 153) when power is restored after a power outage occurs while the setting value update process (Figure 157) or setting confirmation process (Figure 155) is being executed.

If the power outage processing is executed when neither the setting value update processing (Figure 157) nor the setting confirmation processing (Figure 155) has been executed, the content of the processing executed in the main processing (Figure 153) upon the subsequent resumption of power supply is the same as in the 45th embodiment described above. Furthermore, if the power outage processing is executed when the setting confirmation processing (Step Figure 155) has been executed (i.e., when the setting confirmation display flag is set to "1"), the content of the processing executed in the main processing (Figure 153) upon the subsequent resumption of power supply is the same as in the 46th embodiment described above.

When the setting value update process (Figure 157) is being executed (i.e., when the setting update display flag is set to "1"), if the power outage process is executed, the content of the process executed in the main process (Figure 153) when the power supply is subsequently restored is the same as in the 45th embodiment described above: in the case of "no operation" and "setting confirmation operation", the setting value update process (Figure 157) is resumed. In the case of "RAM clear operation" and "setting change operation", the setting value update process (Figure 157) is resumed after the RAM clear process (step SA416) is executed. In this case, in the RAM clear process (step SA416), not only the setting reference area 341 provided in the work area 221 for specific control, but also the setting update display flag and the setting update area 342 provided in the work area 221 for specific control are excluded from the initialization target. Therefore, even if the RAM clear process (step SA416) is executed while the setting update display flag is set to "1", the setting update display flag will be set to "1" when the subsequent setting value update process (Figure 157) begins, and the setting value update will start from the setting value information stored in the setting update area 342 at that time.

With the above configuration, if the power supply is interrupted during the updating of the setting value, not only will the setting value update process (Figure 157) be reliably executed when the power supply is subsequently restored, but it will also be possible to resume the setting value update from the setting value that was being updated just before the power supply was interrupted. This allows the setting value change operation to continue uninterrupted.

<48th Embodiment>
In this embodiment, the content of the processing executed in the main process (Figure 161) when the power supply is restored after a power outage is executed while the setting value update process (step SA918) or the setting confirmation process (step SA914) is being executed differs from that of the 45th embodiment. The configurations that differ from the 45th embodiment will be described below. Configurations that are the same as those in the 45th embodiment will generally not be described.

Figure 164 is an explanatory diagram illustrating the process executed in the main process (Figure 153) when power is restored after a power outage occurs while the setting value update process (Figure 157) or setting confirmation process (Figure 155) is being executed.

If the power outage processing is executed when neither the setting value update processing (Figure 157) nor the setting confirmation processing (Figure 155) has been executed, the content of the processing executed in the main processing (Figure 153) upon the subsequent resumption of power supply is the same as in the 45th embodiment described above. Furthermore, if the power outage processing is executed when the setting confirmation processing (Step Figure 155) has been executed (i.e., when the setting confirmation display flag is set to "1"), the content of the processing executed in the main processing (Figure 153) upon the subsequent resumption of power supply is the same as in the 46th embodiment described above.

When the setting value update process (Figure 157) is being executed (i.e., when the setting update display flag is set to "1"), and the power outage processing is executed, the content of the processing executed in the main process (Figure 153) when the power supply is subsequently restored is the same as the content of the processing executed in the main process (Figure 153) when the power supply is subsequently restored when the power outage processing is executed in a situation where neither the setting value update process (Figure 157) nor the setting confirmation process (Figure 155) is being executed, in the case of "no operation", "RAM clear operation", and "setting confirmation operation". In other words, if there is "no operation," the RAM clear process (step SA416), the setting value update process (Figure 157), and the setting confirmation process (Figure 155) are not executed. If a "RAM clear operation" is performed, the RAM clear process (step SA416) is executed, but the setting value update process (Figure 157) and the setting confirmation process (Figure 155) are not executed. If a "setting confirmation operation" is performed, the setting confirmation process (Figure 155) is executed, but the RAM clear process (step SA416) and the setting value update process (Figure 157) are not executed.

In contrast, in the case of a "setting change operation," the RAM clear process (step SA416) is executed, and then the setting value update process (Figure 157) resumes. In this case, the RAM clear process (step SA416) excludes not only the setting reference area 341 located in the specific control work area 221, but also the setting update display flag and the setting update area 342, both located in the specific control work area 221, from initialization. Therefore, even if the RAM clear process (step SA416) is executed while the setting update display flag is set to "1," the setting update display flag will be set to "1" when the subsequent setting value update process (Figure 157) begins, and the setting value update will start from the setting value information stored in the setting update area 342 at that time.

With the above configuration, even if the power supply is interrupted while the setting values are being updated, it is possible to prioritize the execution of processing corresponding to the actions taken by the gaming hall administrator when the power supply is subsequently restored.

Furthermore, if the power supply is interrupted while a setting value update is in progress, and the power supply is restored while a "setting change operation" is still in progress, it will be possible to resume the setting value update from the point where the power supply was interrupted. This allows the setting value change operation to continue uninterrupted.

<Other Embodiments>
It should be noted that the present invention is not limited to the embodiments described above, and various modifications and improvements are possible without departing from the spirit of the present invention. For example, the following modifications may be made. Incidentally, the following alternative configurations may be applied individually or in combination to the configurations of the above embodiments.

(1) In the first to fourteenth embodiments described above, the parameter indicating the frequency of the opening/closing execution mode was configured to calculate the number of times the opening/closing execution mode occurs per unit game round. However, in addition to or instead of this, the result of dividing the number of times the opening/closing execution mode occurs by the total number of game balls discharged from the game area PA may be used to calculate the parameter. Alternatively, in addition to or instead of this, the result of dividing the number of times the opening/closing execution mode occurs by the sum of the number of balls entering the first operation port 33 and the number of balls entering the second operation port 34 may be used to calculate the parameter. Furthermore, this configuration may also be applied to the fifteenth to forty-eighth embodiments described above.

(2) In the first to fourteenth embodiments described above, the parameter indicating the frequency of occurrence of the high-frequency support mode was calculated by determining the ratio of the number of occurrences of the high-frequency support mode to the number of occurrences of the high-frequency support mode and the number of occurrences of the opening/closing execution mode per unit game round. However, in addition to or instead of this, the result of dividing the number of occurrences of the high-frequency support mode by the total number of game balls discharged from the game area PA may be calculated. Alternatively, in addition to or instead of this, the result of dividing the number of occurrences of the high-frequency support mode by the sum of the number of balls entering the first operation port 33 and the number of balls entering the second operation port 34 may be calculated. Furthermore, this configuration may also be applied to the fifteenth to forty-eighth embodiments described above.

(3) The configuration may include not only jackpot results but also minor win results as game results that trigger the opening/closing execution mode. When a minor win occurs, the opening/closing execution mode is triggered, but the win/loss lottery mode and support mode are not changed before or after the opening/closing execution mode. Furthermore, the configuration may be such that the opening/closing execution mode resulting from a minor win becomes a low-frequency winning mode. In this case, when a jackpot occurs, history information corresponding to the jackpot is stored in the history memory 117, and when a minor win occurs, history information corresponding to the minor win is stored in the history memory 117. In this configuration, parameters indicating the frequency of jackpot occurrences and parameters indicating the frequency of minor win occurrences may be calculated using the history information stored in the history memory 117. This configuration may also be applied to the 15th to 48th embodiments described above.

Furthermore, the probability of winning a minor prize may change depending on the settings of the pachinko machine 10, or it may remain unchanged. In the case where the probability of winning a minor prize changes depending on the settings of the pachinko machine 10, the higher the setting value, the higher the probability of winning a minor prize, or it may be the case that a higher setting value results in a lower probability of winning a minor prize.

Furthermore, in a configuration where minor wins exist, the distribution ratio of the type of jackpot result differs depending on whether the reserved information acquired when a game ball enters the first operation port 33 or the reserved information acquired when a game ball enters the second operation port 34. Additionally, when aiming for entry into the first operation port 33, the launch operation is performed so that the game ball flows down the area to the left of the variable display unit 36 in the game area PA. When aiming for entry into the second operation port 34, the launch operation is performed so that the game ball flows down the area to the right of the variable display unit 36 in the game area PA. Moreover, a minor win result may be generated based on the reserved information acquired when a game ball enters the first operation port 33.

In this configuration, the following 51st parameter may exist as a result of managing the game history. The normal period is defined as the sum of the execution period of the opening/closing execution mode triggered by a minor win result based on ball entry into the first operating port 33 and the execution period of the low-frequency support mode instead of the opening/closing execution mode. Furthermore, the number of balls that enter the out port 24a during the normal period is defined as the number of balls entered K51, the number of balls that enter the general prize entry port 31 during the normal period is defined as the number of balls entered K52, the number of balls that enter the special electric prize entry device 32 during the normal period is defined as the number of balls entered K53, the number of balls that enter the first operating port 33 during the normal period is defined as the number of balls entered K54, and the number of balls that enter the second operating port 34 during the normal period is defined as the number of balls entered K55.
- Parameter 51: The ratio of the total number of game balls dispensed during the normal period (K52 × "number of prize balls for winning into the general prize slot 31" + K53 × "number of prize balls for winning into the special electric prize slot 32" + K54 × "number of prize balls for winning into the first operating slot 33" + K55 × "number of prize balls for winning into the second operating slot 34") / the total number of game balls discharged from the skill area PA during the normal period (K51 + K52 + K53 + K54 + K55). In a configuration in which the above Parameter 51 is calculated, if the probability of winning a small win varies according to the settings of the pachinko machine 10, the normal value of Parameter 51 will vary according to the settings of the pachinko machine 10. Therefore, it is preferable that the history information used to calculate Parameter 51 is erased when the settings of the pachinko machine 10 are changed. On the other hand, if the probability of winning a minor prize does not change according to the settings of the pachinko machine 10, then the normal value of the 51st parameter does not change according to the settings of the pachinko machine 10. Therefore, it is preferable that the history information used to calculate the 51st parameter is not erased even if the settings of the pachinko machine 10 are changed.

(4) In the first to fourteenth embodiments described above, instead of storing history information corresponding to the occurrence of the opening/closing execution mode in the history memory 117 regardless of the type of jackpot result, the history information corresponding to the type of jackpot result may be stored in the history memory 117. In this case, a parameter indicating the frequency of occurrence may be calculated for each type of jackpot result. This configuration may also be applied to the fifteenth to forty-eighth embodiments described above.

(5) In the first to fourteenth embodiments described above, the system is configured to periodically calculate various parameters (parameters 1 to 8, 11 to 18, 21 to 26, 31, and 41 to 42). However, the system is not limited to this configuration. For example, the system may calculate the parameters when the total number of game balls dispensed from the game area PA reaches the calculation trigger number (e.g., 10,000 balls), or when the power supply to the pachinko machine 10 is stopped, or when the number of game rounds reaches the calculation trigger number (e.g., 1,000 rounds). In this case, the history memory 117 may be cleared to "0" at the time the parameters are calculated. This configuration may also be applied to the fifteenth to forty-eighth embodiments described above.

(6) In the first to fourteenth embodiments described above, the configuration was such that all parameters (1st to 8th, 11th to 18th, 21st to 26th, 31st, and 41st to 42nd) were calculated each time the calculation timing for various parameters occurred. However, the configuration is not limited to this, and only a portion of the above parameters may be calculated at a single calculation timing, with the parameter group being calculated changing sequentially each time the calculation timing occurs. For example, parameters 1 to 8 may be calculated at one calculation timing, parameters 11 to 18 at the next calculation timing, parameters 21 to 26 at the next calculation timing, parameters 31 and 41 to 42 at the next calculation timing, and thereafter the change of the calculation targets in the above order may be repeated each time the calculation timing occurs. This makes it possible to reduce the processing load required to calculate the parameters at a single calculation timing. This configuration may also be applied to the fifteenth to forty-eighth embodiments described above.

(7) In the first to fourteenth embodiments described above, the system may be configured to perform calculations of various parameters using the history information in the history memory 117, provided that a game is being played. For example, the system may be configured to perform calculations of various parameters, provided that game balls are supplied to the game area PA. This prevents the calculation of various parameters from being unnecessarily repeated when no game is being played. This configuration may also be applied to the fifteenth to forty-eighth embodiments described above.

(8) In the first to fourteenth embodiments described above, the configuration is not limited to one in which a management IC 66 is provided separately from the main CPU 63. The functions of the management IC 66 may be performed by the main CPU 63. In this case, the correspondence information will be stored in the main ROM 64 in advance. Furthermore, the configuration may also include a history memory 117, a calculation result memory 131, and a separate storage memory 171 provided separately from the main RAM 65, and the functions of the history memory 117, calculation result memory 131, and separate storage memory 171 may be performed by the main RAM 65. In a configuration where the main RAM 65 performs the functions of history memory 117, calculation result memory 131, and separate storage memory 171, when the clear process of the main RAM 65 (steps S105 and S117) is executed, some or all of the areas corresponding to the history memory 117, calculation result memory 131, and separate storage memory 171 may be cleared to "0". Alternatively, the areas corresponding to the history memory 117, calculation result memory 131, and separate storage memory 171 may be excluded from the "0" clearing and only cleared to "0" when the corresponding clear conditions in each of the above embodiments are met. Furthermore, the manual operation content for executing the clear process may differ between the areas corresponding to the history memory 117, calculation result memory 131, and separate storage memory 171 and the other areas in the main RAM 65. Additionally, the function of the management IC 66 may be performed by the voice and light emission control device 81.

(9) In the first to fourteenth embodiments described above, if a new setting is made in the pachinko machine 10, the history information in the history memory 117 is retained without being erased, while the various parameters stored in the calculation result memory 131 are erased. This configuration prevents the notification of various parameters calculated before the new setting was made from being displayed after the new setting has been made. This configuration may also be applied to the fifteenth to forty-eighth embodiments described above.

(10) In the third to fifth embodiments described above, even if a new setting is made for the pachinko machine 10 (i.e., even if the main CPU 63 performs a setting value update process), the clearing process for the history memory 117 may not be performed if the setting value has not changed before or after the setting. This prevents the history information in the history memory 117 from being erased even if the setting value has not changed.

In this configuration, the area for storing setting values in the main RAM 65 is excluded from the "0" clear process even if a complete clear process (step S117) is performed. This configuration allows the main CPU 63 to determine whether the setting value has been changed before or after the setting value update process (step S118). In this case, if the main CPU 63 determines that the setting value has not been changed, it may output a signal to the management CPU 112 to prevent the setting update recognition process from being executed. Conversely, if the main CPU 63 determines that the setting value has been changed, it may output a signal to the management CPU 112 to enable the setting update recognition process to be executed.

Furthermore, when the main CPU 63 receives a signal indicating that a new setting has been made to the pachinko machine 10, the management CPU 112 may determine whether the setting value has been changed by referring to the history information stored in the history memory 117. In this case, if the management CPU 112 determines that the setting value has not been changed, it will not perform the clearing process of the history memory 117. If the management CPU 112 determines that the setting value has been changed, it will perform the clearing process of the history memory 117.

(11) In the third to fifth embodiments described above, even if a new setting is made for the setting state of the pachinko machine 10 (i.e., even if the setting value update process is executed by the main CPU 63), if the setting value has not changed before or after the setting, the calculation process for various parameters triggered by the new setting state may not be executed. This makes it possible to prevent various parameters from being calculated triggered by a new setting state even though the setting value has not changed.

In this configuration, the area for storing setting values in the main RAM 65 is excluded from the "0" clear process even if a complete clear process (step S117) is performed. This configuration allows the main CPU 63 to determine whether the setting value has been changed before or after the setting value update process (step S118). In this case, if the main CPU 63 determines that the setting value has not been changed, it may output a signal to the management CPU 112 to prevent the setting update recognition process from being executed. Conversely, if the main CPU 63 determines that the setting value has been changed, it may output a signal to the management CPU 112 to enable the setting update recognition process to be executed.

Furthermore, when the main CPU 63 receives a signal indicating that a new setting has been made to the pachinko machine 10, the management CPU 112 may determine whether or not the setting value has been changed by referring to the history information stored in the history memory 117. In this case, if the management CPU 112 determines that the setting value has not been changed, it will not perform calculations of various parameters triggered by the new setting. If the management CPU 112 determines that the setting value has been changed, it will perform calculations of various parameters triggered by the new setting.

(12) In the third to fifth embodiments, when a new setting is made for the pachinko machine 10, instead of calculating various parameters at that time using various calculation processes (step S1807), the various parameters stored in the calculation result memory 131 at that time may be stored in the area to be stored among the first to fifth separate storage areas 172 to 176 of the separate storage memory 171, and the information stored in the calculation result memory 131 may be cleared to "0". In this case, since there is no need to calculate various parameters when a new setting is made for the pachinko machine 10, it becomes possible to complete the storage of various parameters in the separate storage memory 171 at an earlier stage.

(13) In the third to fifth embodiments, the contents of various parameters stored in the first to fifth separate storage areas 172 to 176 of the separate storage memory 171 may be displayed on the first to third notification display devices 69a to 69c or other display devices when a predetermined display start operation is performed. The predetermined display start operation may be performed by operating a dedicated operation unit, or by performing a predetermined dedicated operation on an operation unit used for other operations. This makes it possible to easily check the various parameters stored in the separate storage memory 171.

(14) Although the configuration is such that the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 are all subject to the storage of history information (or ball entry history), the configuration is not limited to this, and it is also possible to configure the system so that only some of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 are subject to the storage of history information. For example, it is also possible to configure the system so that only the general prize-winning port 31, special electric prize-winning device 32, and second operation port 34 are subject to the storage of history information, or so that only the general prize-winning port 31 is subject to the storage of history information. Even in this case, it is possible to understand the ball entry patterns of the game balls over a predetermined period for the ball entry sections that are subject to the storage of history information.

(15) The configuration includes signal paths 118a to 118c for transmitting information corresponding to the ball entry result, corresponding to the first prize entry sensor 42a, the second prize entry sensor 43a, and the third prize entry sensor 44a, respectively. However, the configuration is not limited to this. Information corresponding to the ball entry result for the same type of ball entry section may be transmitted as a single type of information, even if there are multiple ball entry sections of the same type and correspondingly multiple ball entry detection sensors. This makes it possible to reduce the number of types of information transmitted from the main CPU 63 to the management IC 66.

(16) In the first to fourteenth embodiments described above, correspondence relationship information indicating the correspondence between the type of information transmitted from the main CPU 63 to the management IC 66 and each buffer 122a to 122o is transmitted from the main CPU 63 to the management IC 66. However, the system is not limited to this configuration, and the correspondence relationship information may be pre-stored in the management IC 66. In this case, since it is not necessary to perform processing to make the management IC 66 recognize the correspondence relationship information, the processing load on the main CPU 63 can be reduced.

(17) In the first to fourteenth embodiments described above, the transmission of correspondence relationship information, which indicates the correspondence between the type of information transmitted from the main CPU 63 to the management IC 66 and each buffer 122a to 122o, from the main CPU 63 to the management IC 66 is performed when the supply of operating power to the main CPU 63 begins. However, the system is not limited to this configuration. For example, the main CPU 63 and the management IC 66 may be configured to communicate bidirectionally, and the correspondence relationship information may be transmitted from the main CPU 63 to the management IC 66 when a signal requesting the transmission of correspondence relationship information is received from the management IC 66. In this case, the correspondence relationship memory 116 is provided as a non-volatile memory and is configured for both reading and writing. The correspondence relationship information provided from the main CPU 63 to the management IC 66 after the pachinko machine 10 is shipped is stored in the correspondence relationship memory 116 even if the supply of operating power to the main CPU 63 is stopped. This makes it possible to reduce the frequency of transmission of correspondence relationship information.

(18) In the first to fourteenth embodiments described above, the transmission of correspondence relationship information, which indicates the correspondence between the type of information transmitted from the main CPU 63 to the management IC 66 and each buffer 122a to 122o, from the main CPU 63 to the management IC 66 is performed using the signal paths 118a to 118g for transmitting detection result information from each ball entry detection sensor 42a to 48a. However, the system is not limited to this configuration, and a dedicated signal path for transmitting correspondence relationship information from the main CPU 63 to the management IC 66 may also be provided. This allows the management IC 66 to determine what type of information it is receiving from the main CPU 63 based on the type of buffer 122a to 122o receiving that information.

(19) In the first to fourteenth embodiments described above, information is transmitted from the main CPU 63 to the management IC 66, while no information is transmitted from the management IC 66 to the main CPU 63. However, the system is not limited to this configuration, and information may be transmitted from the management IC 66 to the main CPU 63. For example, various parameters calculated by the management CPU 112 based on history information may be transmitted to the main CPU 63. In this case, the main CPU 63 may be configured to directly execute notification control of the notification means so that notification corresponding to the content of the received various parameters is made. Alternatively, the main CPU 63 may transmit a command corresponding to the content of the received various parameters to the voice light emission control device 81, thereby enabling notification corresponding to the content of the various parameters to be made using the graphic display device 41, display light emission unit 53, and speaker unit 54.

(20) In the first to 14th embodiments described above, when the supply of operating power to the main CPU 63 is started, various parameters may be calculated by the main CPU 63 or the management CPU 112 based on the history information stored in the history memory 117, and the contents of the calculated parameters may be notified using the pattern display device 41, display light-emitting unit 53, and speaker unit 54, etc. In this case, it becomes possible to confirm whether the ball entry pattern of the game area PA on the immediately preceding business day was normal when the gaming hall begins operations. This configuration may also be applied to the 15th to 48th embodiments described above.

(21) In the first to fourteenth embodiments described above, if the various parameters calculated based on the history information stored in the history memory 117 are abnormal, the pachinko machine 10 may be configured so that game cannot be started until a ban release operation is performed. Configurations to prevent game start include, for example, a configuration in which the launch of game balls is prohibited, a configuration in which each ball entry detection sensor 42a to 49a is disabled, and a configuration in which the win/loss determination process is not executed even if a prize is awarded in the first operation opening 33 or the second operation opening 34. The ban release operation may be an operation in which the power to the pachinko machine 10 is turned on again while the reset button 68c is pressed, or an operation of an operating means that becomes operable when the game machine body 12 is opened relative to the outer frame 11. This makes it possible to prevent game play from continuing even when the ball entry pattern into the game area PA is abnormal. It also makes it possible to prevent game play from continuing even when the frequency of the opening/closing execution mode is abnormal. Furthermore, this configuration may be applied to the embodiments described in the 15th to 48th examples above.

(22) In the first to fourteenth embodiments described above, although history information corresponding to the detection results of the ball entry detection sensors 42a to 48a is stored in the history memory 117, the calculation of various parameters using this history information may not be performed by either the main CPU 63 or the management CPU 112. In this case, the history information may be read by an external device electrically connected to the reading terminal 68d, and the calculation of various parameters using the read history information may be performed by the operator performing the reading operation, or the calculation of various parameters using the read history information may be performed by the external device. In this case, the processing load on the main CPU 63 and the management CPU 112 can be reduced. Furthermore, this configuration may also be applied to the fifteenth to forty-eighth embodiments described above.

(23) In the first to fourteenth embodiments described above, the management IC 66 is provided with a separate power supply from the main CPU 63. Even if the supply of operating power to the main CPU 63 is stopped, the management IC 66 may be configured to perform calculations of various parameters using history information and output history information or various parameters. This makes it possible to read history information and various parameters using an external device, even when the supply of operating power to the main CPU 63 is stopped.

(24) In the first to fourteenth embodiments described above, the read terminal 68d used to read a program from the main ROM 64 is also used as a terminal for reading history information or various parameters with an external device. However, the embodiment is not limited to this configuration, and the terminal used to read history information or various parameters with an external device may be provided separately from the read terminal 68d used to read a program from the main ROM 64. In this case, the terminal used to read history information or various parameters may be provided on the MPU 62, or it may be provided in a location on the main control board 61 separate from the MPU 62.

(25) The configurations described in the first to fourteenth embodiments are not limited to those in which the correspondence memory 116, history memory 117, and calculation result memory 131 are provided as non-volatile storage means such as flash memory. For example, any of these memories 116, 117, or 131 may be provided as volatile storage means that require power supply to store and retain information, and backup power may be supplied to that memory so that information is retained even if the power supply to the main CPU 63 is stopped. In this case, a dedicated backup power device may be provided for that memory, or backup power may be supplied to that memory from the power supply/launch control device 78 that supplies backup power to the main RAM 65.

(26) In the first to fourteenth embodiments described above, the management IC 66 is not limited to a configuration in which the management side CPU 112 is provided as a general-purpose CPU and performs history information storage processing and various parameter calculation processing based on the program and data stored in the management side ROM 113. The management IC 66 may also be configured in which a hardware circuit designed to have these functions is formed. Specifically regarding this configuration, for example in the first embodiment described above, when the hardware circuit receives a signal from the main side CPU 63 indicating that a game ball has been detected by any of the detection sensors 42a to 48a, the corresponding relationship information for the buffer that received the signal is stored in the history memory 117 from the relationship memory 116, and the RTC 115 information at that time is also stored in the history memory 117. Also, for example in the sixth embodiment described above, when the hardware circuit receives a signal from the main side CPU 63 indicating that a game ball has been detected by any of the detection sensors 42a to 48a, the value of the counter corresponding to the buffer that received the signal is incremented by 1. Furthermore, when a calculation trigger occurs as described in the first embodiment above, the hardware circuit calculates various parameters using the history information at that time. Also, when an external output trigger occurs at the read terminal 68d, the hardware circuit outputs the calculation results (various parameters) and the history information to the external terminal.

(27) In the first to fourteenth embodiments described above, the main CPU 63 and the management IC 66 may be provided as separate chips, on separate circuit boards, or as separate control devices.

(28) Regarding the entry of game balls into the out-out port 24a, the number of balls entered is measured. However, regarding entry into the bonus trigger ball entry sections, such as the general prize entry port 31, the special electric prize entry device 32, the first operation port 33, and the second operation port 34, which trigger the payout of prize balls and the determination of wins or losses, the system may be configured to store historical information including RTC information. This makes it possible to extract the entry history of game balls into the bonus trigger ball entry sections and calculate the frequency of game ball entry into each bonus trigger ball entry section relative to the total number of game balls dispensed.

(29) The system may include events other than those in the above embodiments as triggers for storing historical information. For example, the system may store as historical information at least one of the following: when the lower tray 56a becomes full, the timing at which the full state begins, and the timing at which the full state is released. Similarly, the system may store as historical information when the tank 75 becomes empty of balls, the timing at which the empty state begins, and the timing at which the empty state is released. Furthermore, the system may store as historical information when the dispensing device 76 enters an abnormal state, the timing at which the abnormal state of the dispensing device 76 begins, and the timing at which the abnormal state of the dispensing device 76 is released. In this case, it becomes possible to grasp the frequency of these events.

(30) In the first embodiment described above, the 16th buffer 122p of the input port 121 of the management I/F 111 is configured to correspond to an output instruction signal, as this is pre-set in the design stage of the management IC 66. However, the configuration is not limited to this, and the fact that the 16th buffer 122p corresponds to an output instruction signal may also be recognized by the management IC 66 when a type identification command is sent from the main CPU 63. Also, in the first embodiment described above, the 15th buffer 122o of the input port 121 of the management I/F 111 is configured to correspond to a setting value update signal, as this is pre-set in the design stage of the management IC 66. However, the configuration is not limited to this, and the fact that the 15th buffer 122o corresponds to a setting value update signal may also be recognized by the management IC 66 when a type identification command is sent from the main CPU 63. In this case, it becomes unnecessary to pre-set the correspondence between each buffer 122a to 122p and the type of signal input to those buffers 122a to 122p in the management IC 66.

(31) In the first to fourteenth embodiments described above, the management IC 66 may be configured to transmit a normal operation signal to the main CPU 63 when it is operating normally. In this case, the main CPU 63 can monitor whether the management IC 66 is operating normally.

(32) The display device that shows the setting value in progress during the setting value update process is not limited to the first to fourth notification display devices 201 to 204, but may also be the graphic display device 41, or a dedicated display device. Furthermore, the display device that shows the setting value during the setting confirmation process is not limited to the first to fourth notification display devices 201 to 204, but may also be the graphic display device 41, or a dedicated display device.

(33) The operation unit used to update the setting value in the setting value update process is not limited to the update button 68b, but may also be the reset button 68c. Furthermore, when a setting key is inserted into the setting key insertion unit 68a and rotated, positions corresponding to "Setting 1" to "Setting 6" may be set, and the setting value corresponding to the rotation position of the setting key insertion unit 68a may be set. Alternatively, the setting key insertion unit 68a may be configured to allow rotation beyond the ON position, and each time rotation beyond the ON position is performed, the setting value being updated is updated to the next setting value in the sequence.

(34) In the embodiments of the 1st to 10th and 15th to 21st described above, the 1st to 3rd notification display devices 69a to 69c are arranged side by side. However, they may also be arranged vertically, diagonally, or in two vertical rows. Furthermore, in the embodiments of the 11th to 14th and 22nd to 44th described above, the 1st to 4th notification display devices 201 to 204 are arranged side by side. However, they may also be arranged vertically, diagonally, or in two vertical rows. Also, in the embodiments of the 15th to 21st described above, the 1st to 4th notification display devices 201 to 204 may be used as a display device for displaying the management results of the game history.

(35) In the first to fourteenth embodiments described above, the history information used to calculate parameters whose normal values fluctuate according to the settings of the pachinko machine 10 (hereinafter referred to as "variable history information") and the history information used to calculate parameters whose normal values do not fluctuate according to the settings of the pachinko machine 10 (hereinafter referred to as "non-variable history information") may be stored in different areas of the history memory 117. In this case, when the settings of the pachinko machine 10 are newly set or changed, the area in the history memory 117 where the variable history information is stored is cleared to "0", while the area in the history memory 117 where the non-variable history information is stored is not cleared to "0". This allows for accurate calculation of parameters whose normal values fluctuate according to the settings of the pachinko machine 10 even after the settings have been changed, and improves the accuracy of calculations for parameters whose normal values do not fluctuate according to the settings of the pachinko machine 10. This configuration may also be applied to the fifteenth to forty-eighth embodiments described above.

(36) In the 15th to 21st embodiments described above, the stack area 222 for specific control and the stack area 224 for non-specific control may not be pre-specified in the main RAM 65. Even in this case, the areas corresponding to these stack areas 222 and 224 will be specified in the main RAM 65 during the design phase of the pachinko machine 10. However, if the storage processing of information specifying these areas exceeds the storage capacity of those areas, information not originally intended will be written to areas not originally intended. Therefore, the main RAM 65 may be configured to be cleared to "0".

(37) In the above 15th to 21st embodiments, when the clearing process of the main RAM 65 (steps S105 and S117) is performed, the work area 221 for specific control and the stack area 222 for specific control are cleared to "0", but the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". Alternatively, the clearing process of the main RAM 65 (steps S105 and S117) may be configured to clear not only the work area 221 and the stack area 222 for specific control but also the work area 223 and the stack area 224 for non-specific control to "0". Furthermore, in the clearing process of the main RAM 65 (steps S105 and S117), not only the work area 221 and stack area 222 for specific control, but also the normal counter area 231, the counter area 232 for opening/closing execution mode, and the counter area 233 for high-frequency support mode may be cleared to "0," but the calculation result storage area 234 may not be cleared to "0." In this case, it becomes possible to protect the information stored in the calculation result storage area 234.

(38) In the 15th to 25th embodiments described above, the operation for clearing the work area 221 for specific control and the stack area 222 for specific control to "0" may be configured to be different from the operation for clearing the work area 223 for non-specific control and the stack area 224 for non-specific control to "0". For example, when the reset button 68c is operated and the supply of operating power to the pachinko machine 10 is started, the work area 221 for specific control and the stack area 222 for specific control are cleared to "0", and when the update button 68b is operated and the supply of operating power to the pachinko machine 10 is started, the work area 223 for non-specific control and the stack area 224 for non-specific control are cleared to "0". This makes it possible to selectively erase each piece of information. Furthermore, in this configuration, if power is supplied to the pachinko machine 10 while both the update button 68b and the reset button 68c are operated, the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may all be cleared to "0". This improves the efficiency of clearing information from each of the areas 221 to 224 collectively in the configuration that allows selective erasure as described above.

(39) In embodiments 15 to 18 and 20 described above, similar to embodiment 19, the information of the stack pointer of the main CPU 63 may be saved to the work area 223 for non-specific control when processing corresponding to non-specific control begins, and the saved information may be restored to the stack pointer of the main CPU 63 when returning to processing corresponding to specific control. This allows the stack pointer information of the main CPU 63 to change when processing corresponding to non-specific control begins, but when processing corresponding to non-specific control ends, the state of the stack pointer of the main CPU 63 can be restored to the state before processing corresponding to the non-specific control began.

(40) In the 15th to 25th embodiments described above, the system was configured to execute processes corresponding to non-specific control, such as processes for collecting game history information, processes for calculating various parameters using the collected history information, and processes for reporting the calculation results. However, it is also possible to configure the system so that only a portion of these processes are executed as processes corresponding to non-specific control, and the rest are executed as processes corresponding to specific control. Furthermore, in addition to or instead of the processes for collecting game history information, processes for calculating various parameters using the collected history information, and processes for reporting the calculation results, other processes may be executed as processes corresponding to non-specific control. For example, at least one of the processes of fraud monitoring and reporting the monitoring results may be executed as a process corresponding to non-specific control.

(41) In the embodiments described above (15th to 25th), when the main CPU 63 returns to processing corresponding to specific control from a situation where processing corresponding to non-specific control is being executed, the flag register, stack pointer, and various registers of the main CPU 63 are not saved to the main RAM 65. Alternatively, when the main CPU 63 returns to processing corresponding to specific control from a situation where processing corresponding to non-specific control is being executed, at least some of the information from the flag register, stack pointer, and various registers of the main CPU 63 may be saved to the main RAM 65, and this saved information may be restored to the corresponding memory area of the main CPU 63 when processing corresponding to non-specific control is restarted. This makes it possible to carry over and use the information of the main CPU 63 used in processing corresponding to non-specific control.

(42) In the 15th to 25th embodiments described above, various parameters are calculated when the total number of game balls dispensed from the game area reaches 6,000. However, the total number of game balls that triggers this calculation may be greater than or less than 6,000. For example, the parameters may be calculated when the total number of game balls dispensed from the game area reaches 60,000. In this case, the storage capacity required to store game history information will increase. However, by storing game history information in a management RAM 241 externally attached to the MPU 62, as in the 21st embodiment described above, it is possible to flexibly accommodate this increase in storage capacity.

(43) In the 15th to 25th embodiments described above, the 61st to 68th parameters were calculated as a result of managing the game history. However, in addition to or instead of this, the 31st, 41st, and 42nd parameters of the first embodiment may also be calculated.

(44) In the embodiments described in the 15th to 25th above, when a process for setting the configuration state of the pachinko machine 10 is executed or when the configuration state of the pachinko machine 10 is changed, not only the work area 221 for specific control and the stack area 222 for specific control, but also the work area 223 for non-specific control and the stack area 224 for non-specific control may be cleared to "0". In this case, when a process for setting the configuration state of the pachinko machine 10 is executed or when the configuration state of the pachinko machine 10 is changed, the normal counter area 231, the counter area 232 for opening/closing execution mode, the counter area 233 for high-frequency support mode, and the calculation result storage area 234 will be cleared to "0".

Furthermore, when a process is executed to set a new state for the pachinko machine 10, or when the state of the pachinko machine 10 is changed, the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233 are cleared to "0," not only the work area 221 and the stack area 222 for specific control, but the calculation result storage area 234 is not cleared to "0." In this case, it becomes possible to protect the information stored in the calculation result storage area 234.

Furthermore, when a process to set a new state for the pachinko machine 10 is executed, or when the state of the pachinko machine 10 is changed, the specific control work area 221 and the specific control stack area 222 are cleared to "0," but the non-specific control work area 223 and the non-specific control stack area 224 are not cleared to "0." In this case, it becomes possible to protect the information stored in the non-specific control work area 223 and the non-specific control stack area 224.

Furthermore, in the case of the configuration described in (43) above, when a process for setting a new setting state of the pachinko machine 10 is executed or when the setting state of the pachinko machine 10 is changed, the history information for calculating the 31st parameter, 41st parameter, and 42nd parameter in the first embodiment is erased, but the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, and the calculation result storage area 234 may not be cleared to "0".

(45) In the first to forty-eight embodiments described above, instead of using the total number of game balls discharged from the game area PA to calculate various parameters, the total number of game balls supplied to the game area PA may be used. In this case, for example, a detection sensor may be provided to detect game balls that have been launched from the game ball launching mechanism 27 and reached the game area PA, and the number of game balls supplied to the game area PA may be measured based on the detection result of the detection sensor. In this configuration, since it is not necessary to measure the number of game balls discharged from the out-out port 24a, the out-out port detection sensor 48a may not be provided.

(46) In the embodiments described in the 15th to 48th embodiments above, at least a portion of the information of the various registers and stack pointer of the main CPU 63 may be saved to a specific control stack area 222 or a non-specific control stack area 224 by a load instruction. In this case, it is necessary to update the stack pointer information of the main CPU 63 when saving the information to the stack areas 222 and 224. Alternatively, the information saved to the stack areas 222 and 224 may be restored to the corresponding memory area of the main CPU 63 by a load instruction. In this case as well, it is necessary to update the stack pointer information of the main CPU 63 when restoring the information from the stack areas 222 and 224.

(47) In each of the above embodiments, if a setting value update process is being performed, a corresponding notification may be provided by one of the pattern display device 41, the display light-emitting unit 53, or the speaker unit 54. This allows the administrator of the gaming hall to clearly understand that a setting value update process is being performed.

(48) In each of the above embodiments, the history of newly set values may be stored in the main RAM 65. Alternatively, the history of newly set values may be stored in the RAM provided in the sound and light emission control device 81. In this case, each time a setting value update process is completed, a command containing information about the setting value set in the setting value update process is sent from the main CPU 63 to the sound and light emission control device 81. Each time the sound and light emission control device 81 receives this command, it cumulatively stores information indicating that a new setting value has been set and information indicating the setting value at that time in its RAM. In this configuration, when a predetermined operation is performed, the setting history of the setting values cumulatively stored in the RAM of the sound and light emission control device 81 may be displayed on the graphic display device 41.

(49) In each of the above embodiments, when a new setting value is set during the setting value update process, the information indicating the number of game balls to be dispensed, stored in the payout control device 77, is not erased. Alternatively, the information indicating the number of game balls to be dispensed may be erased. Furthermore, if the setting value update process is executed but the setting value is not changed, the information indicating the number of game balls to be dispensed is not erased. However, if the setting value is changed, the information indicating the number of game balls to be dispensed is erased.

(50) In each of the above embodiments, if the setting value update process is performed but the setting value is not changed, the areas 221 to 224 of the main RAM 65 will not be cleared to "0". However, if the setting value is changed, at least a portion of the areas 221 to 224 of the main RAM 65 may be cleared to "0". For example, if the setting value is changed, the areas other than the setting value counter in the work area 221 for specific control may be cleared to "0".

(51) In the 22nd to 48th embodiments described above, even when the main CPU 63 is executing a setting confirmation process (Figure 87) to confirm the set value, the operation of movable parts that contribute to the game's profit may be maintained. For example, in a configuration where the ball entry means that allows balls to enter in the opening/closing execution mode is provided with a V-zone and a non-V-zone, and a distribution member is provided to distribute game balls that enter the ball entry means to either the V-zone or the non-V-zone, the operation of the distribution member may be maintained even when the setting confirmation process is executing to confirm the set value. In this case, even if someone tries to stop the operation of the distribution member by fraudulently creating a situation in which the setting confirmation process is executed, it will be impossible to do so. Furthermore, even when the setting confirmation process is executed to verify the setting values, other movable parts that continue to operate include, in addition to the distribution member described above, distribution members that distribute game balls to either a favorable opening where game balls entering the ball entry means will trigger a round game, or an outlet that ejects game balls that have entered the ball entry means without allowing them to enter the favorable opening.

(52) In the embodiments described in the 22nd to 48th embodiments above, at least one of the work area 223 for non-specific control and the stack area 224 for non-specific control may be configured not to be subject to monitoring for information anomalies. In this case, even if an information anomaly is identified in the work area 221 for specific control and the stack area 222 for specific control, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". This configuration prevents the situation in which the work area 223 for non-specific control and the stack area 224 for non-specific control are cleared to "0" based on the occurrence of an information anomaly.

(53) In the embodiments described in the 22nd to 48th embodiments above, the monitoring of whether or not an information anomaly has occurred in the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may all be performed by processes corresponding to non-specific control. Furthermore, the processing to clear each area 221 to 224 to "0" when an information anomaly occurs may all be performed by processes corresponding to non-specific control.

(54) In each of the above embodiments, the main RAM 65 requires power supply to store and retain information, and backup power is supplied to the main RAM 65 even when the power supply of the pachinko machine 10 is OFF. However, the main RAM 65 may be configured as a non-volatile memory that does not require power supply to store and retain information.

(55) In each of the above embodiments, instead of a configuration in which the target area of the main RAM 65 is initialized by executing a process to clear it to "0" and an initial setting process, the target area may be initialized by executing an initial setting process without executing a process to clear it to "0".

(56) In each of the above embodiments, if the setting key insertion unit 68a is turned ON when the supply of operating power to the main CPU 63 is started, the setting value update process may be executed without requiring any other operation. Alternatively, instead of the setting key insertion unit 68a, which is turned ON/OFF by a setting key, a setting switch that can be directly turned ON/OFF by hand may be provided. Furthermore, if the setting key insertion unit 68a is not provided, and the reset button 68c is pressed when the supply of operating power to the main CPU 63 is started, the setting value update process may be executed without requiring any other operation. In this case, a cover member may be provided that can be switched between a closed state that covers the reset button 68c and an open state that does not cover it, and a locking device may be provided to lock this cover member in the closed position.

(57) In the setting value update process, if the setting key insertion unit 68a is operated to the OFF position and the state is maintained for a predetermined period, the selected setting value may be confirmed and the setting value update process may be terminated. Alternatively, if a termination period (e.g., 5 minutes) has elapsed since the start of the setting value update process, the selected setting value may be automatically confirmed and the setting value update process may be terminated. Furthermore, in the setting value update process, if the update button 68b or reset button 68c is pressed and held for a termination period (e.g., 10 seconds) or longer, the selected setting value may be confirmed and the setting value update process may be terminated.

(58) The setting key insertion unit 68a may be configured to be able to be rotated beyond the ON position, and each time the rotation operation beyond the ON position is performed, the setting value in the process of being updated is updated to the setting value in the next order. In this configuration, a setting confirmation process that enables confirmation of the setting value is started when the supply of operating power to the main CPU 63 is started while the setting key insertion unit 68a is operated to the ON position, and the setting confirmation process is terminated when the setting key insertion unit 68a is operated to the OFF position. Alternatively, a setting confirmation process that enables confirmation of the setting value is started when the supply of operating power to the main CPU 63 is started while the update button 68b or reset button 68c is pressed, and the setting confirmation process is terminated when the button is released. Furthermore, in a configuration where a setting switch that can be directly operated ON/OFF by hand is provided instead of a setting key insertion section 68a that is operated ON/OFF by a setting key, a setting confirmation process that enables verification of the setting value may be initiated when the setting switch is operated ON and power supply to the main CPU 63 is started, and the setting confirmation process may be terminated when the setting switch is operated OFF or when it is operated ON after being operated OFF. Alternatively, in a configuration where a setting switch that can be directly operated ON/OFF by hand is provided instead of a setting key insertion section 68a that is operated ON/OFF by a setting key, a setting confirmation process that enables verification of the setting value may be initiated when the setting switch is operated ON and power supply to the main CPU 63 is started, and the setting confirmation process may be terminated when the reset button 68c is pressed.

(59) In each of the above embodiments, when a setting confirmation process or a setting value update process is performed, the image corresponding to the procedure may be displayed on the graphic display device 41, and the sound corresponding to the procedure may be output from the speaker unit 54 to assist this. For example, in the setting value update process in the 33rd embodiment, the system may be configured to notify the user that pressing the reset button 68c changes the setting value by one level, and that turning off the setting key insertion unit 68a terminates the setting value update process. This makes it easier to perform the setting value update work. Since the display control of the graphic display device 41 and the sound output control of the speaker unit 54 are performed by the sound light output control device 81, it is necessary that a command corresponding to the setting confirmation process or setting value update process is sent from the main CPU 63 when the process is started, and a command corresponding to the setting confirmation process or setting value update process is sent from the main CPU 63 when the process is terminated.

(60) Instead of the configuration in which the display control device 82 is controlled by the sound and light emission control device 81 based on commands transmitted from the main control device 60, the display control device 82 may control the sound and light emission control device 81 based on commands transmitted from the main control device 60. Furthermore, instead of the configuration in which the sound and light emission control device 81 and the display control device 82 are provided separately, both control devices may be provided as a single control device. The functions of one of these two control devices may be integrated into the main control device 60, or both functions of these two control devices may be integrated into the main control device 60. The configuration of the commands transmitted from the main control device 60 to the sound and light emission control device 81, and the configuration of the commands transmitted from the sound and light emission control device 81 to the display control device 82, are also arbitrary.

(61) The present invention can also be applied to other types of pachinko machines different from the embodiments described above, such as pachinko machines in which an electric mechanism opens a predetermined number of times when a game ball enters a specific area of a special device, pachinko machines in which a right is generated and a jackpot is won when a game ball enters a specific area of a special device, pachinko machines equipped with other mechanisms, arrangement ball machines, mahjong ball machines, and other gaming machines.

Furthermore, the present invention can also be applied to non-paper-scissors gaming machines, such as slot machines equipped with multiple reels each bearing multiple symbols arranged circumferentially. The reels begin rotating upon insertion of a medal and operation of a start lever. After the reels stop due to operation of a stop switch or elapsed time, if a specific symbol or combination of symbols is found on an active line visible through the display window, the player is awarded a bonus, such as a medal payout.

Furthermore, the present invention can also be applied to a gaming machine that combines elements of a pachinko machine and a slot machine, in which the gaming machine body, supported by an outer frame in an openable and closable manner, is equipped with a storage unit and a retrieval device, and the reels start rotating when a start lever is operated after a predetermined number of gaming balls stored in the storage unit have been retrieved by the retrieval device.

When applying the present invention to slot machines or gaming machines that combine pachinko and slot machines, for example, the system may store the results of the prize draw process performed when a game is started based on the operation of the start lever as history information, and use this history information to calculate the actual winning probability of each prize. It may also store the transition to a special game state, such as a bonus game, as history information, and use this history information to calculate the actual transition probability to the special game state. Furthermore, it may calculate the ratio of the number of games played in the special game state to the total number of games played. The system may also be configured to allow external devices to read this history information and various parameters, or to provide notifications corresponding to the calculation results of the various parameters within the gaming machine itself. Additionally, the system may have multiple setting states, such as "Setting 1" to "Setting 6," and the winning probability in the prize draw process may vary according to the setting state. In this case, the configurations described in the above embodiments may be applied to the handling of history information, the calculation of various parameters, and the handling of repeated changes when a setting state is newly set or the setting value is changed.

(62) The characteristic configurations of the first to forty-eight embodiments described above may be applied to each other in any combination. For example, the characteristic configuration of the first embodiment may be combined with the characteristic configuration of the sixth embodiment, the characteristic configuration of the tenth embodiment, the characteristic configuration of the thirtyth embodiment, and the characteristic configuration of the forty-fifth embodiment. Alternatively, the characteristic configuration of the second embodiment may be combined with the characteristic configuration of the fourth embodiment, the characteristic configuration of the eighth embodiment, the characteristic configuration of the eleventh embodiment, the characteristic configuration of the thirty-third embodiment, and the characteristic configuration of the forty-third embodiment. Alternatively, the characteristic configuration of the first embodiment may be combined with the characteristic configuration of the fifteenth embodiment, the characteristic configuration of the twenty-first embodiment, the characteristic configuration of the twenty-ninth embodiment, and the characteristic configuration of the thirty-fourth embodiment. Alternatively, the characteristic configuration of the second embodiment may be combined with the characteristic configuration of the sixteenth embodiment, the characteristic configuration of the twenty-second embodiment, the characteristic configuration of the thirty-fifth embodiment, and the characteristic configuration of the thirty-nineth embodiment. Furthermore, the configurations of the alternative embodiments described above may be applied in any combination to a configuration in which the characteristic configurations of the first to forty-eight embodiments described above are applied in a predetermined combination.

<Regarding the group of inventions extracted from each of the above embodiments>
The following describes the features of the group of inventions extracted from each of the embodiments described above, showing their effects and other aspects as necessary. For ease of understanding, corresponding configurations in each of the embodiments described above will be indicated in parentheses as appropriate, but the invention is not limited to these specific configurations indicated in parentheses.

<Characteristics Group A>
Feature A1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A history storage execution means (a function that executes history setting processing in the management CPU 112) stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (history memory 117),
Information erasure means (a function that executes the process in step S1809 in the management CPU 112 in the third embodiment, a function that executes the process in step S2109 in the management CPU 112 in the fifth embodiment, a function that executes the processes in steps S2306 to S2308 in the management CPU 112 in the sixth embodiment, and a function that executes the process in step S2608 in the management CPU 112 in the eighth embodiment),
A gaming machine characterized by having the following features.

According to Feature A1, the system is configured to select a setting value from multiple levels corresponding to the player's advantage, so the player expects the most advantageous setting value to be used. Furthermore, when a predetermined event occurs, the corresponding history information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, it becomes possible to effectively manage the frequency of occurrences of the predetermined event. Additionally, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented.

In this case, at least a portion of the history information stored in the history storage means is erased, with the setting of the target value being newly configured being at least one of the conditions. This makes it possible to adjust the contents of the history storage means to suitably manage the frequency of occurrence of predetermined events in the situation after the new setting of the target value has been configured.

Feature A2. Ball entry means (first operating port 33, second operating port 34) into which game balls flowing down the game area can enter,
Information acquisition means (a function that executes the processing in step S401 in the main CPU 63) that acquires special information based on the fact that a game ball has entered the ball entry means,
The grant determination means (a function that executes the processing in steps S503 and S504 in the main CPU 63) performs a grant determination to determine whether the special information corresponds to the grant information,
Based on the granting determination result indicating that the special information corresponds to the granting information, the system includes a granting means (a function that executes the processing in steps S409 to S412 in the main CPU 63) that grants a benefit (open/close execution mode) to the player,
The gaming machine according to feature A1, characterized in that the probability of obtaining the aforementioned granting result in the granting determination changes according to the aforementioned setting value.

According to Feature A2, it becomes possible to vary the probability of receiving a corresponding result in a so-called pachinko machine according to the set value. In this case, by having the configuration of Feature A1, it becomes possible to adjust the contents of the history storage means so that the frequency of occurrence of a predetermined event in the situation after the probability of receiving a corresponding result has been changed can be appropriately managed.

Feature A3. The gaming machine according to Feature A1 or A2, characterized in that the information erasure means erases all of the history information stored in the history storage means, provided that at least one condition is that the setting value to be used has been set by the setting means.

According to Feature A3, when a new setting value is made, all history information stored in the history storage means is erased. This makes it possible to identify the frequency of a predetermined event based on the timing when the new setting value was made.

Feature A4. The gaming machine according to Feature A1 or A2, characterized in that the information erasure means erases a portion of the history information stored in the history storage means, while retaining a portion of the history information stored in the history storage means, provided that at least one condition is that the setting value to be used has been set by the setting means.

According to Feature A4, when a new setting value is configured, it becomes possible to delete unnecessary historical information for managing the frequency of subsequent predetermined events, while retaining the historical information necessary for managing the frequency of subsequent predetermined events. This allows for efficient management of the frequency of predetermined events after a new setting value has been configured.

Feature A5. The history information stored in the history storage means includes first history information (history information indicating that an opening/closing execution mode occurred) in which the probability of occurrence of the predetermined event corresponding to the history information changes according to the set value, and second history information (history information indicating that a game ball was ejected from the game area PA) which does not change according to the set value.
The gaming machine according to feature A4, wherein the information erasure means erases the first history information stored in the history storage means and retains the second history information stored in the history storage means, provided that at least one condition is that the setting value to be used has been set by the setting means.

According to Feature A5, when a new setting value is configured, the first history information corresponding to a predetermined event whose occurrence probability fluctuates according to the setting value is deleted, while the second history information corresponding to a predetermined event whose occurrence probability does not fluctuate according to the setting value is not deleted. This allows for the deletion of first history information that is undesirable for identifying the occurrence frequency of the predetermined event corresponding to the first history information if it is carried over after the new setting value is configured. On the other hand, by not deleting the second history information even when a new setting value is configured, it is possible to secure a larger number of second history information entries that can be referenced when identifying the occurrence frequency of the predetermined event corresponding to the second history information, thereby enabling more accurate identification of the occurrence frequency of the predetermined event corresponding to the second history information.

Feature A6. Ball entry means (first operating port 33, second operating port 34) into which game balls flowing down the game area can enter,
Information acquisition means (a function that executes the processing in step S401 in the main CPU 63) that acquires special information based on the fact that a game ball has entered the ball entry means,
The grant determination means (a function that executes the processing in steps S503 and S504 in the main CPU 63) performs a grant determination to determine whether the special information corresponds to the grant information,
The system includes a bonus granting means (a function that executes the processing in steps S409 to S412 in the main CPU 63) that grants a bonus (open/close execution mode) to the player based on the granting result in the granting determination that the special information corresponds to the granting information,
The configuration is such that the probability of obtaining the aforementioned assignment result changes in the assignment determination according to the aforementioned setting value.
The first history information includes information corresponding to the granting of the aforementioned benefit,
The gaming machine according to feature A5, characterized in that the second history information includes information corresponding to the ejection of a game ball from the game area in a predetermined manner.

According to Feature A6, the probability of receiving a bonus varies depending on the setting value. Therefore, by deleting the first history information when a new setting value is set, it becomes possible to identify the frequency of bonus distribution under the newly set setting value. On the other hand, since the frequency of game balls being dispensed from the game area does not vary depending on the setting value, by not deleting the second history information even when a new setting value is set, it becomes possible to accurately identify the frequency of game balls being dispensed from the game area in a predetermined manner.

Feature A7. The gaming machine according to any one of Features A1 to A6, characterized in that the information erasure means erases at least a portion of the history information when the setting means has set the target setting value, and the history storage means has stored a predetermined amount or more of the history information.

According to Feature A7, if the history storage means does not contain a predetermined amount of history information, the history information will not be erased even if a new setting value is made for the target setting. This prevents the history storage means from repeatedly erasing the history information even if new setting values are repeatedly made while the game is not being played.

Feature A8. A gaming machine according to any one of Features A1 to A7, characterized in that, at least one condition is that the setting value to be used has been set by the setting means, the machine includes an information derivation means (in the third embodiment, a function to execute the processing in step S1807 of the management CPU 112; in the fifth embodiment, a function to execute the processing in step S2107 of the management CPU 112) that derives behavioral information corresponding to the results of the game over a predetermined period using the history information stored in the history storage means.

According to Feature A8, in a configuration having the same configuration as Feature A1, where at least a portion of the history information stored in the history storage means is erased under at least one condition that a new setting value to be used is made, the configuration derives behavioral information corresponding to the results of the game over a predetermined period using the history information stored in the history storage means, triggered by the setting value being changed. This makes it possible to understand the management results of the game history, such as the frequency of occurrence of predetermined events, in the situation before the setting value was changed, even if at least a portion of the history information is erased when the setting value is changed.

Feature A9. The gaming machine according to Feature A8, characterized by comprising a mode information storage means (separate storage memory 171) for storing the mode information derived by the information derivation means.

According to Feature A9, when a new setting value is made, and the history information stored in the history storage means is used to derive behavioral information corresponding to the game results over a predetermined period, that behavioral information is stored in the behavioral information storage means. This makes it possible to understand the game history management results under the conditions before the setting value change, even if the setting value is changed, at any subsequent time.

Feature A10. The gaming machine according to Feature A9, characterized in that the mode information storage means is capable of storing multiple mode information items.

According to Feature A10, since the behavior information storage means can store multiple behavior information sets, it becomes possible to grasp the management results of game history over multiple periods based on the timing of new setting values. Furthermore, even if new setting values are repeatedly set while no game is being played, it becomes possible to increase the likelihood that behavior information derived using history information from situations where gameplay is actually taking place remains in the behavior information storage means.

Feature A11. The aspect information storage means is capable of storing a predetermined number of aspect information,
The gaming machine is characterized by having means for executing special processing when the setting of the target setting value by the setting means occurs more than a predetermined number of times under predetermined conditions (in the third embodiment, a function for executing repeated change monitoring processing in the management CPU 112, and in the fourth embodiment, a function for executing repeated change monitoring processing in the main CPU 63), as described in feature A9 or A10.

According to Feature A11, in order to prevent the behavioral information derived using the history information of the actual gameplay situation from remaining in the behavioral information storage means, if the setting value is repeatedly changed while the game is not being played, a special process is executed in response. This makes it possible to deal with such actions.

Feature A12. The gaming machine according to any one of Features A8 to A11, characterized in that the information extraction means extracts the pattern information when the history storage means stores a predetermined amount or more of the predetermined history information.

According to feature A12, since the pattern information is derived only when a predetermined amount of predetermined history information is stored in the history storage means, it is possible to prevent the unnecessary deriving of pattern information.

Feature A13. The gaming machine according to any one of Features A1 to A12, characterized in that the information erasure means does not erase the history information until a specific amount or more of the predetermined history information is stored in the history storage means after the setting of the setting value to be used by the setting means, and erases the history information that was stored in the history storage means before the setting of the setting value when a specific amount or more of the predetermined history information is stored in the history storage means after the setting of the setting value to be used by the setting means.

According to Feature A13, until a specific amount of predetermined historical information is newly stored in the history storage means, the historical information stored before the setting value to be used is not erased, even if a new setting value is made. This makes it possible to identify the results of game history management for a predetermined period, even if a new setting value is made.

Feature A14. The history storage means comprises a first history storage means (first history memory 191) and a second history storage means (second history memory 192),
The history storage execution means is
If the predetermined event occurs during a predetermined period from the time the setting value to be used is set by the setting means until the release condition is met, means for storing the corresponding history information in both the first history storage means and the second history storage means (a function that executes the processing in step S2604 in the management CPU 112),
If the predetermined event occurs during a period other than the predetermined period, the first history storage means and the second history storage means, which are set as storage targets, are provided with means for storing the corresponding history information (a function that executes the processing in step S2603 in the management CPU 112),
Equipped with,
The gaming machine according to any one of features A1 to A13, characterized in that, when the release condition is met, the information erasure means erases the history information stored in the first history storage means and the second history storage means that was previously set as the storage target.

According to Feature A14, until a specific amount of history information is newly stored in the history storage means, even if a new setting is made for the setting value to be used, the history information stored before that setting is not erased. This makes it possible to identify the results of game history management for a predetermined period, even if a new setting value is made. Furthermore, this effect can be achieved simply by appropriately changing the history storage means that stores the history information between the first and second history storage means.

Feature A15. The gaming machine according to Feature A14, characterized by comprising information derivation means (a function that executes the processing in step S2703 in the management CPU 112) that derives behavioral information corresponding to the results of the game over a predetermined period using the history information stored in the first history storage means and the second history storage means, which is set as the storage target.

According to Feature A15, even if history information is stored in both the first and second history storage means due to the setting of new settings, it becomes possible to appropriately derive the mode information using the history information.

Furthermore, for the configuration of features A1 to A15, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Characteristics Group B>
Feature B1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A history storage execution means (a function that executes history setting processing in the management CPU 112) stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (history memory 117),
Equipped with,
A gaming machine characterized in that predetermined history information stored in the history storage means before the setting of the target setting value by the setting means is retained in the history storage means even after the setting of the target setting value by the setting means is performed.

According to Feature B1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, the player expects the target setting value to be more advantageous. Furthermore, when a predetermined event occurs, the corresponding history information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, it becomes possible to effectively manage the frequency of occurrences of the predetermined event. Additionally, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented.

In this case, even if new settings are made to the target values, the history information stored in the history storage means is not erased but retained. This allows the history information to continue to be stored in the history storage means even after new settings are made to the target values, making it possible to identify the results of game history management using the history information accumulated in the history storage means over a long period of time.

Feature B2. The gaming machine according to Feature B1, characterized in that the history storage execution means includes a setting-time storage execution means (in the first embodiment, a function to execute the processing in step S1307 of the management CPU 112; in the seventh embodiment, a function to execute the processing in step S2408 of the management CPU 112) which stores the corresponding history information in the history storage means when the setting means sets the setting value to be used.

According to Feature B2, in a configuration where history information is retained without being erased even when a new setting value is made, history information corresponding to the new setting value is stored in the history storage means. This makes it possible to distinguish between history information before and after a new setting value is made.

Feature B3. The gaming machine according to Feature B2, characterized in that, when the setting means sets the setting value to be used, it stores information corresponding to the set setting value as history information in the history storage means.

According to Feature B3, it is possible to identify the content of previously set settings by referring to the history information.

Feature B4. The gaming machine according to any one of Feature B1 to B3, characterized in that the history storage means comprises a plurality of corresponding history storage means (history memories 181 to 186 for settings 1 to 6) corresponding to each of the plurality of setting values that can be set by the setting means.

According to Feature B4, since a corresponding history storage means is provided for each setting value, it is possible to store history information separately for each setting value.

Feature B5. The gaming machine according to Feature B4, characterized in that, when the setting value to be used is set by the setting means, the corresponding history storage means is provided with means to store the history information corresponding to the set value (a function that executes the processing in step S2406 in the management CPU 112).

According to Feature B5, when a new setting value is added, the corresponding history storage means becomes the target for storing subsequent history information. Therefore, it becomes possible to store history information separately for each setting value.

Feature B6. The gaming machine according to Feature B5, characterized by having information derivation means (a function that executes display output processing in the management CPU 112) that derives behavioral information corresponding to the results of games during a predetermined period using the history information stored in the corresponding history storage means that is the target of the storage.

According to Feature B6, in a configuration where history information is stored separately for each setting value, it becomes possible to derive behavioral information corresponding to the currently set setting value.

Feature B7. Ball entry means (first operating port 33, second operating port 34) into which game balls flowing down the game area can enter,
Information acquisition means (a function that executes the processing in step S401 in the main CPU 63) that acquires special information based on the fact that a game ball has entered the ball entry means,
The grant determination means (a function that executes the processing in steps S503 and S504 in the main CPU 63) performs a grant determination to determine whether the special information corresponds to the grant information,
The system includes a bonus granting means (a function that executes the processing in steps S409 to S412 in the main CPU 63) that grants a bonus (open/close execution mode) to the player based on the granting result in the granting determination that the special information corresponds to the granting information,
The gaming machine according to any one of the features B1 to B6, characterized in that the probability of obtaining the corresponding grant result in the grant determination changes according to the setting value.

According to Feature B7, it becomes possible to vary the probability of receiving a corresponding result in a so-called pachinko machine according to the set value.

Furthermore, for the configuration of features B1 to B7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Characteristics Group C>
Feature C1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A history storage execution means (a function that executes history setting processing in the management CPU 112) stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (history memory 117),
A post-setting response means (a function that executes the processing in steps S2506 and S2605 to S2609 in the management CPU 112) that does not erase the history information until at least a certain amount of predetermined history information has been stored in the history storage means after the setting of the setting value to be used by the setting means,
A gaming machine characterized by having the following features.

According to Feature C1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, the player expects the target setting value to be more advantageous. Furthermore, when a predetermined event occurs, the corresponding history information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Additionally, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented.

In this case, until a specific amount of predetermined historical information is newly stored in the history storage means, the historical information stored before the setting value to be used is not erased, even if the setting value is changed. This makes it possible to identify the results of game history management for a predetermined period, even if the setting value is changed.

Feature C2. The post-setting response means, when the setting means has set the target setting value, erases the history information stored in the history storage means that was stored before the setting value was set, if the history information has been stored in the history storage means for a predetermined amount or more after the setting means has set the target setting value. This is the gaming machine according to Feature C1.

According to feature C2, when a specific amount of history information is stored in the history storage means, enabling the identification of the game history management results for a predetermined period after a new setting value has been made, the history information stored in the history storage means before the new setting value was made is erased. This prevents unnecessary history information from remaining stored in the history storage means.

Feature C3. The history storage means comprises a first history storage means (first history memory 191) and a second history storage means (second history memory 192),
The history storage execution means is
When the predetermined event occurs, the first history storage means and the second history storage means, which are set as the storage target, are provided with means for storing the corresponding history information (a function that executes the processing in step S2603 in the management CPU 112),
From the time the setting means sets the setting value to be used until the predetermined history information is stored in the first history storage means and the second history storage means that is not set as the target of storage, until the predetermined event occurs, means for storing the corresponding history information in both the first history storage means and the second history storage means (a function that executes the processing in step S2604 in the management CPU 112),
Equipped with,
The post-setting response means is:
After the setting means has set the setting value to be used, if a predetermined amount or more of the history information is stored in the first history storage means and the second history storage means that is not set as the storage target, means for changing the storage target between the first history storage means and the second history storage means (a function that executes the processing of step S2607 in the management CPU 112),
After the setting means has set the setting value to be used, if a predetermined amount or more of the history information is stored in the first history storage means and the second history storage means that is not set as the storage target, means for erasing the history information in the first history storage means and the second history storage means that was previously set as the storage target (a function that executes the process in step S2608 in the management CPU 112),
A gaming machine according to feature C1 or C2, characterized by having the following features.

According to feature C3, until a specific amount of history information is newly stored in the history storage means, even if a new setting is made for the setting value to be used, the history information stored before that setting is not erased. This makes it possible to identify the results of game history management for a predetermined period, even if a new setting value is made. Furthermore, this effect can be achieved simply by appropriately changing the history storage means that stores the history information between the first and second history storage means.

Feature C4. The gaming machine according to Feature C3, characterized by comprising information derivation means (a function that executes the processing in step S2703 in the management CPU 112) that derives behavioral information corresponding to the results of the game over a predetermined period using the history information stored in the first history storage means and the second history storage means, which is set as the storage target.

According to feature C4, even when history information is stored in both the first and second history storage means due to the setting of new settings, it becomes possible to appropriately derive the mode information using the history information.

Feature C5. Ball entry means (first operating port 33, second operating port 34) into which game balls flowing down the game area can enter,
Information acquisition means (a function that executes the processing in step S401 in the main CPU 63) that acquires special information based on the fact that a game ball has entered the ball entry means,
The grant determination means (a function that executes the processing in steps S503 and S504 in the main CPU 63) performs a grant determination to determine whether the special information corresponds to the grant information,
Based on the granting determination result indicating that the special information corresponds to the granting information, the system includes a granting means (a function that executes the processing in steps S409 to S412 in the main CPU 63) that grants a benefit (open/close execution mode) to the player,
The gaming machine according to any one of features C1 to C4, characterized in that the probability of obtaining the corresponding grant result in the grant determination changes according to the setting value.

According to feature C5, it becomes possible to vary the probability of receiving a corresponding result in a so-called pachinko machine according to the set value.

Furthermore, for the configuration of features C1 to C5, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features Group D>
Feature D1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A special execution means that performs special processing on the condition that the setting of the setting value to be used by the setting means was performed in special circumstances (in the third embodiment, a function to perform repeated change monitoring processing on the management CPU 112; in the fourth embodiment, a function to perform repeated change monitoring processing on the main CPU 63; in the fifth embodiment, a function to make a negative determination in step S2106 on the management CPU 112),
A gaming machine characterized by having the following features.

According to Feature D1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, the player expects the target setting value to be more advantageous. In this case, special processing is executed based on at least one condition: that a new setting value was made under special circumstances. This makes it possible to address situations where a new setting value is made under unfavorable circumstances.

Feature D2. The gaming machine according to Feature D1, characterized in that the special execution means executes the special processing on the condition that the setting of the target setting value by the setting means has been performed a specific number of times or more in the special situation.

According to Feature D2, even if a new setting value is configured in a special situation, if the number of such configurations is below a specified number, the special processing will not be executed. This prevents special processing from being executed when a regular user configures a new setting value in a special situation less than a specified number of times.

Feature D3. The gaming machine according to Feature D1 or D2, characterized in that the special execution means executes the special processing under the condition that the setting of the target setting value by the setting means has been performed, in a situation where no game has been played since the setting of the target setting value by the setting means, or where no game has been played for a predetermined standard or more since the setting of the target setting value by the setting means.

According to Feature D3, if a new setting value is made while the game is not being played or is not being played in a substantial manner, a special process is executed. Therefore, it is possible to address such an action if it occurs.

Feature D4. The gaming machine according to any one of Feature D1 to D3, characterized in that the special execution means performs a notification process as the special processing.

According to feature D4, notification processing is executed on the condition that a new setting of the target value is performed under special circumstances. This makes it possible to prompt action if a new setting is performed under undesirable circumstances.

Feature D5. A history storage execution means (a function that executes history setting processing in the management CPU 112) that stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (history memory 117),
The setting means has set the setting value to be used, and at least one condition is that the setting means has set the setting value to be used, and the information derivation means (a function that executes the processing in step S1807 in the management CPU 112 in the third embodiment, and a function that executes the processing in step S2107 in the management CPU 112 in the fifth embodiment) derives behavioral information corresponding to the results of the game over a predetermined period using the history information stored in the history storage means,
A gaming machine according to any one of the features D1 to D4, characterized by having the following features.

According to feature D5, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be effectively managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented.

In this case, when a new setting value is made, the history information stored in the history storage means is used to derive behavioral information corresponding to the game results over a predetermined period. This makes it possible to understand the management results of the game history, such as the frequency of occurrence of predetermined events, under the conditions before the setting value was changed.

Feature D6. The gaming machine according to Feature D5, characterized in that the special execution means, under at least one condition that the setting of the target setting value by the setting means has been performed in the special situation, does not allow the information derivation means to perform the derivation of the mode information as a special process.

According to feature D6, even if a new setting value is made to the target setting, if the setting is made under undesirable circumstances, the behavioral information will not be derived. This prevents the unnecessary derivation of behavioral information.

Feature D7. The gaming machine according to Feature D5 or D6, characterized by comprising a mode information storage means (separate storage memory 171) for storing the mode information derived by the information derivation means.

According to Feature D7, when a new setting value is made, and the history information stored in the history storage means is used to derive behavioral information corresponding to the game results over a predetermined period, that behavioral information is stored in the behavioral information storage means. This makes it possible to understand the game history management results under the conditions before the setting value change, even if the setting value is changed, at any subsequent time.

Feature D8. The gaming machine according to Feature D7, characterized in that the mode information storage means is capable of storing multiple mode information items.

According to Feature D8, since the behavior information storage means can store multiple behavior information sets, it becomes possible to grasp the management results of game history over multiple periods based on the timing of new setting values. Furthermore, even if new setting values are repeatedly set while no game is being played, it becomes possible to increase the likelihood that behavior information derived using history information from situations where gameplay is actually taking place remains in the behavior information storage means.

Feature D9. The aspect information storage means is capable of storing a predetermined number of aspect information.
The gaming machine according to feature D7 or D8, characterized in that the special execution means executes the special processing when the setting of the target setting value by the setting means occurs more than a predetermined number of times in the special situation.

According to Feature D9, in order to prevent the behavioral information derived using the history information of the actual gameplay situation from remaining in the behavioral information storage means, if the setting value is repeatedly changed while the game is not being played, a special process is executed in response. This makes it possible to deal with such actions.

Feature D10. Ball entry means (first operating port 33, second operating port 34) into which game balls flowing down the game area can enter,
Information acquisition means (a function that executes the processing in step S401 in the main CPU 63) that acquires special information based on the fact that a game ball has entered the ball entry means,
The grant determination means (a function that executes the processing in steps S503 and S504 in the main CPU 63) performs a grant determination to determine whether the special information corresponds to the grant information,
Based on the granting determination result indicating that the special information corresponds to the granting information, the system includes a granting means (a function that executes the processing in steps S409 to S412 in the main CPU 63) that grants a benefit (open/close execution mode) to the player,
The gaming machine according to any one of the features D1 to D9, characterized in that the probability of obtaining the aforementioned grant result in the grant determination changes according to the aforementioned setting value.

According to feature D10, it becomes possible to vary the probability of receiving a corresponding result in a so-called pachinko machine according to the set value.

Furthermore, for the configuration of features D1 to D10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Features Group E>
Feature E1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A history storage execution means (a function that executes history setting processing in the management CPU 112) stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (history memory 117),
The setting means has set the setting value to be used, and at least one condition is that the setting means has set the setting value to be used, and the information derivation means (a function that executes the processing in step S1807 in the management CPU 112 in the third embodiment, and a function that executes the processing in step S2107 in the management CPU 112 in the fifth embodiment) derives behavioral information corresponding to the results of the game over a predetermined period using the history information stored in the history storage means,
A gaming machine characterized by having the following features.

According to Feature E1, the system is configured to select a setting value from multiple levels corresponding to the player's advantage, so the player expects a more advantageous setting value to be used. Furthermore, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, it becomes possible to effectively manage the frequency of occurrences of the predetermined event. Additionally, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented.

In this case, when a new setting value is made, the history information stored in the history storage means is used to derive behavioral information corresponding to the game results over a predetermined period. This makes it possible to understand the management results of the game history, such as the frequency of occurrence of predetermined events, under the conditions before the setting value was changed.

Feature E2. The gaming machine according to Feature E1, further characterized by comprising a mode information storage means (separate storage memory 171) for storing the mode information derived by the information derivation means.

According to Feature E2, when a new setting value is made, and the history information stored in the history storage means is used to derive behavioral information corresponding to the game results over a predetermined period, that behavioral information is stored in the behavioral information storage means. This makes it possible to understand the game history management results under the conditions before the setting value change, even if the setting value is changed, at any subsequent time.

Feature E3. The gaming machine according to Feature E2, characterized in that the mode information storage means is capable of storing multiple mode information items.

According to Feature E3, since the behavior information storage means can store multiple behavior information sets, it becomes possible to grasp the management results of game history over multiple periods based on the timing of new setting values. Furthermore, even if new setting values are repeatedly set while no game is being played, it becomes possible to increase the likelihood that behavior information derived using history information from situations where gameplay is actually taking place remains in the behavior information storage means.

Feature E4. The manner information storage means is capable of storing a predetermined number of manner information,
The gaming machine is characterized by having means for executing special processing when the setting of the target setting value by the setting means occurs more than a predetermined number of times under predetermined conditions (in the third embodiment, a function for executing repeated change monitoring processing in the management CPU 112, and in the fourth embodiment, a function for executing repeated change monitoring processing in the main CPU 63), as described in feature E2 or E3.

According to Feature E4, in order to prevent the behavioral information derived using the history information of the actual gameplay situation from remaining in the behavioral information storage means, if the setting value is repeatedly changed while the game is not being played, a special process is executed in response. This makes it possible to deal with such actions.

Feature E5. The gaming machine according to any one of Features E1 to E4, characterized in that the information extraction means extracts the pattern information when the history storage means has a predetermined amount or more of the predetermined history information stored in it.

According to feature E5, since the pattern information is derived only when a predetermined amount or more of predetermined history information is stored in the history storage means, it becomes possible to prevent the unnecessary deriving of pattern information.

Feature E6. Ball entry means (first operating port 33, second operating port 34) into which game balls flowing down the game area can enter,
Information acquisition means (a function that executes the processing in step S401 in the main CPU 63) that acquires special information based on the fact that a game ball has entered the ball entry means,
The grant determination means (a function that executes the processing in steps S503 and S504 in the main CPU 63) performs a grant determination to determine whether the special information corresponds to the grant information,
Based on the granting determination result indicating that the special information corresponds to the granting information, the system includes a granting means (a function that executes the processing in steps S409 to S412 in the main CPU 63) that grants a benefit (open/close execution mode) to the player,
The gaming machine according to any one of features E1 to E5, characterized in that the probability of obtaining the corresponding grant result in the grant determination changes according to the setting value.

According to feature E6, it becomes possible to vary the probability of receiving a corresponding result in a so-called pachinko machine according to the set value.

Furthermore, for the configuration of features E1 to E6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the inventions relating to the above-mentioned features A, B, C, D, and E, the following problems can be solved.

Pachinko machines and slot machines are well-known examples of gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, the game ball is dispensed back into the tray storage section from a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In the case of gaming machines like those exemplified above, proper management of the gaming machines is necessary, and there is still room for improvement in this regard.

<Features Group F>
Feature F1. Ball entry means (first operating port 33, second operating port 34) into which game balls flowing down the game area can enter,
Information acquisition means (a function that executes the processing in step S401 in the main CPU 63) that acquires special information based on the fact that a game ball has entered the ball entry means,
The grant determination means (a function that executes the processing in steps S503 and S504 in the main CPU 63) performs a grant determination to determine whether the special information corresponds to the grant information,
Based on the granting determination result indicating that the special information corresponds to the granting information, a granting means (a function that executes the processing in steps S409 to S412 in the main CPU 63) grants a grant (open/close execution mode) to the player,
A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
Equipped with,
The assignment determination means has a high-probability mode and a low-probability mode as modes for the assignment determination, such that the probability of obtaining the assignment result is relatively high or low.
A gaming machine characterized in that the probability of obtaining the corresponding result changes, at least in the low probability mode, according to the setting value.

According to Feature F1, in so-called pachinko machines, it becomes possible to vary the probability of obtaining the corresponding result, at least in the low probability mode, depending on the setting value. This makes it possible to create situations where the probability of obtaining the corresponding result is advantageous or disadvantageous, even within a single gaming machine. Therefore, it becomes possible to enhance the enjoyment of the game.

Feature F2. The gaming machine according to Feature F1, characterized in that the probability of obtaining the corresponding result in the high-probability mode does not change according to the setting value.

According to Feature F2, the probability of receiving a corresponding result in low-probability mode is varied according to the set value, while the probability of receiving a corresponding result in high-probability mode is not varied according to the set value. This allows the influence of the set value to be limited to the situation in low-probability mode.

Feature F3. There are multiple types of the aforementioned benefits.
The gaming machine according to feature F1 or F2, characterized in that the selection method of the aforementioned benefits does not change according to the setting value.

According to Feature F3, the probability of receiving a reward in low-probability mode is varied according to the set value, while the method of selecting the reward is not varied according to the set value. This allows the influence of the set value to be limited to the situation in low-probability mode.

Furthermore, for the configuration of features F1 to F3, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned feature group F, the following problems can be solved.

Pachinko machines and slot machines are well-known examples of gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, the game ball is dispensed back into the tray storage section from a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In the case of gaming machines like those exemplified above, there is a need to enhance the enjoyment of the game, and there is still room for improvement in this regard.

<Features Group G>
Feature G1. A history storage execution means (a function that executes history setting processing in the management CPU 112) that stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (history memory 117),
Information deriving means for deriving behavioral information corresponding to the results of games over a predetermined period using the history information stored in the history storage means (in the first embodiment, a function to execute the processing in steps S1402 to S1412 in the management CPU 112; in the third embodiment, a function to execute the processing in step S1807 in the management CPU 112; in the fifth embodiment, a function to execute the processing in step S2107 in the management CPU 112),
A first information display control means (a function that executes display processing in the management CPU 112) controls the display of an information display means (first to third notification display devices 69a to 69c in the first to tenth embodiments, and first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) so that a display corresponding to the aspect information derived by the information derivation means is shown,
A second information display control means for controlling the display of the information display means so that a display corresponding to information different from the aforementioned aspect information is shown (in the first to tenth embodiments, a function to execute the processing of steps S202 and S208 in the main CPU 63; in the eleventh embodiment, a function to execute the processing of steps S3101, S3103 and S3109 in the main CPU 63; in the twelfth embodiment, a function to execute the processing of steps S3201, S3202, S3204 and S3210 in the main CPU 63; in the thirteenth embodiment, a function to execute error display processing in the main CPU 63),
A gaming machine characterized by having the following features.

According to Feature G1, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be effectively managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, behavioral information corresponding to the game results over a predetermined period is derived using the history information stored in the history storage means. Then, the information display means displays the behavioral information. This makes it possible to grasp the management results of the game history, such as the frequency of occurrence of the predetermined event. Moreover, the information display means displays not only the behavioral information but also other information. This allows for effective utilization of the information display means.

Feature G2. The gaming machine according to Feature G1, characterized in that the period during which the information display means displays information corresponding to the aspect information is distinguished from the period during which the information display means displays information corresponding to the other information.

According to Feature G2, by understanding the status of the display in the information display means, it becomes possible to identify whether the display corresponds to the aspect information or to a display corresponding to other information.

Feature G3. The gaming machine according to Feature G1 or G2, characterized in that the second information display control means controls the display of the information display means so that the display mode is different from the display mode when the display corresponding to the mode information is performed, thereby causing the display corresponding to the other information to be performed.

According to Feature G3, by understanding the display mode of the information display means, it becomes possible to identify whether the information display means is displaying information corresponding to the mode information or information corresponding to other information.

Feature G4. A gaming machine according to any one of Feature G1 to G3, characterized in that it is provided with a plurality of individual information display means (in the first to tenth embodiments, the first to third notification display devices 69a to 69c; in the eleventh to fourteenth embodiments, the first to fourth notification display devices 201 to 204) each capable of displaying multiple types of information.

According to Feature G4, by using multiple individual information display means to display information corresponding to the aspect information, it becomes possible to display a wide variety of aspect information. Furthermore, the presence of multiple individual information display means makes it possible to significantly differentiate the display manner between cases where information corresponding to aspect information is displayed and cases where information corresponding to other information is displayed.

Feature G5. The gaming machine according to Feature G4, characterized in that, when the second information display control means is to display the information corresponding to the other information, it causes a predetermined individual information display means (in the first to tenth embodiments, the first notification display device 69a and the second notification display device 69b; in the eleventh and twelfth embodiments, the first notification display device 201, the second notification display device 202, and the third notification display device 203; in the thirteenth embodiment, the first notification display device 201 and the second notification display device 202) that does not become invisible when the display corresponding to the aspect information is displayed among the plurality of individual information display means to become invisible.

According to Feature G5, a predetermined individual information display means that remains visible when displaying aspect information is performed becomes invisible when displaying other information is performed. This makes it possible to clearly identify whether displaying aspect information or other information is being performed simply by identifying the type of individual information display means that is currently invisible.

Feature G6. When the second information display control means causes the display corresponding to the other information to be displayed, it causes a specific individual information display means (in the first to tenth embodiments, the third notification display device 69c; in the eleventh and twelfth embodiments, the fourth notification display device 204; in the thirteenth embodiment, the third notification display device 203 and the fourth notification display device 204) to be in a display state among the plurality of individual information display means that are in a display state when the manner information is displayed.
The gaming machine according to feature G5, characterized in that the content of the display means of the specific individual information display means when a display corresponding to the aforementioned separate information is made can be displayed on the specific individual information display means when a display corresponding to the aforementioned aspect information is made.

According to Feature G6, in a specific individual information display means, the display content that can be displayed when a display corresponding to aspect information is performed can also be displayed when a display corresponding to other information is performed. This makes it possible to avoid restricting the display content when a display corresponding to aspect information is performed. Furthermore, even if a specific individual information display means has a configuration that allows for the same display content, a predetermined individual information display means that does not become invisible when a display corresponding to aspect information is performed, as stipulated in Feature G5, becomes invisible when a display corresponding to other information is performed. Therefore, it is possible to identify which display is being performed by multiple individual information display means.

Feature G7. The gaming machine according to Feature G5 or G6, characterized in that, when the first information display control means causes the display corresponding to the mode information, each of the plurality of individual information display means is set to a display state.

According to Feature G7, when a display corresponding to aspect information is performed, each of the multiple individual information display means becomes visible. Therefore, it is possible to clearly distinguish this from cases where a display corresponding to other information is performed, where a predetermined individual information display means remains hidden.

Feature G8. The gaming machine according to any one of Feature G5 to G7, characterized in that the first information display control means sequentially changes the display of the aspect information in the information display means, and even when changing the display of the aspect information, the predetermined individual information display means is not kept in a hidden state.

According to Feature G8, when a display corresponding to the aspect information is shown, the predetermined individual information display means is not kept hidden. This makes it possible to identify whether a display corresponding to the aspect information or a display corresponding to other information is being shown in the multiple individual information display means, regardless of when the multiple individual information display means were checked.

Feature G9. The gaming machine according to any one of Features G5 to G8, characterized in that the second information display control means causes one specific individual information display means (the third notification display device 69c in the first to tenth embodiments, and the fourth notification display device 204 in the eleventh and twelfth embodiments) to display the information corresponding to the other information, while the remaining individual information display means are kept hidden.

According to feature G9, when a display corresponding to different information is being shown, only one individual information display means will be in the display state, making it easier to determine whether or not a display corresponding to different information is being shown.

Feature G10. The multiple individual information display means are arranged in a predetermined direction.
The gaming machine according to feature G9, characterized in that the specific individual information display means is located at the end of a plurality of individual information display means arranged in the predetermined direction.

According to feature G10, since the single individual information display means that displays information corresponding to other information is located at the end in a predetermined direction, it becomes easier to determine whether or not information corresponding to other information is being displayed.

Feature G11. The first information display control means is configured such that a display corresponding to the type of the manner information to be displayed is performed in a portion of the plurality of individual information display means, which are individual information display means for type display targets (first notification display device 69a in the first to tenth embodiments, and first notification display device 201 and second notification display device 202 in the eleventh to fourteenth embodiments), and a display corresponding to the content of the manner information to be displayed is performed in a portion of the plurality of individual information display means, which are individual information display means for result display targets (second notification display device 69b and third notification display device 69c in the first to tenth embodiments, and third notification display device 203 and fourth notification display device 204 in the eleventh to fourteenth embodiments).
The gaming machine according to any one of features G5 to G10, characterized in that the predetermined individual information display means corresponds to the individual information display means for the type of display target.

According to Feature G11, when a display corresponding to the type information is shown, the individual information display means for the type display target displays a display corresponding to the type of type information to be displayed, and the individual information display means for the result display displays a display corresponding to the content of the type information to be displayed. This makes it easier to understand the type information being displayed. In this case, when a display corresponding to different information is shown, the individual information display means for the type display target becomes invisible. Therefore, the invisible state of the type display corresponds to different information, making it easier to understand that different information is being displayed.

Feature G12. The information display means has a plurality of unit light-emitting units (display segments 201a to 201g, 202a to 202g), and is configured to display a predetermined information by combining the unit light-emitting units that are in a light-emitting state among the plurality of unit light-emitting units.
The second information display control means enables the display of the other information by enabling the display of the other information by enabling the display of the other information by enabling the unit light-emitting unit among the plurality of unit light-emitting units which can be enabled when the display corresponding to the manner information is enabled, and the combination of the unit light-emitting units which is enabled when the display corresponding to the other information is enabled is such that it is a combination that does not exist when the display corresponding to the manner information is enabled. This is a gaming machine according to any one of the features G1 to G11.

According to Feature G12, by activating the unit light-emitting units that can be activated when a display corresponding to the aspect information is performed, a display corresponding to other information is performed. This allows for diversification of displays corresponding to aspect information while minimizing restrictions on the content of the display corresponding to the aspect information. On the other hand, the combination of unit light-emitting units that activates when a display corresponding to other information is performed is a combination that does not exist when a display corresponding to aspect information is performed. Therefore, by understanding the combination of unit light-emitting units that activate, it becomes possible to determine whether a display corresponding to aspect information or a display corresponding to other information is being performed.

Feature G13. There are multiple display modes for the display corresponding to the aspect information in the information display means.
The gaming machine according to feature G12, characterized in that, among the plurality of unit light-emitting units, there are no unit light-emitting units that do not light up even when all of the displays corresponding to the aspect information of the plurality of aspects are performed.

According to feature G13, since any combination of unit light-emitting units is set to a light-emitting state when a display corresponding to the aspect information is performed, it becomes possible to minimize restrictions on the content of the display corresponding to the aspect information in order to diversify the displays corresponding to the aspect information.

Feature G14. The system includes multiple individual information display means, including specific individual information display means (third notification display device 69c in the first to tenth embodiments, fourth notification display device 204 in the eleventh and twelfth embodiments, and third notification display device 203 and fourth notification display device 204 in the thirteenth embodiment),
The gaming machine according to feature G12 or G13, characterized in that when the second information display control means causes the display corresponding to the other information to be displayed, it causes a predetermined individual information display means (first notification display device 69a and second notification display device 69b in the first to tenth embodiments, first notification display device 201, second notification display device 202 and third notification display device 203 in the eleventh and twelfth embodiments, and first notification display device 201 and second notification display device 202 in the thirteenth embodiment) to be turned off.

According to Feature G14, a predetermined individual information display means that remains hidden when a display corresponding to aspect information is displayed becomes hidden when a display corresponding to other information is displayed. This makes it possible to clearly identify whether a display corresponding to aspect information or another type of information is being displayed simply by identifying the type of individual information display means that is currently hidden.

Feature G15. Equipped with setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage.
The gaming machine according to any one of features G1 to G14, characterized in that the second information display control means causes the display of the other information when the set value can be changed.

According to feature G15, the information display means that displays information corresponding to the configuration can also be used as a display means for notifying that it is possible to change the set value.

Feature G16. The gaming machine according to Feature G15, characterized in that the second information display control means causes the display of information corresponding to the currently selected setting value as the display corresponding to the other information.

According to feature G16, the information display means that displays information corresponding to the configuration information can also be used as a display means for displaying setting values that are being changed.

Feature G17. The gaming machine according to any one of Feature G1 to G16, characterized in that the second information display control means causes a display corresponding to an abnormal state of the gaming machine as a display corresponding to the other information.

According to feature G17, the information display means that displays information corresponding to the mode information can also be used as a display means for displaying information corresponding to the abnormal state of the gaming machine.

Feature G18. The gaming machine according to Feature G17, characterized in that, when the second information display control means is to display a message corresponding to the abnormal state when the abnormal state is not occurring, it displays a message corresponding to the absence of the abnormal state.

According to feature G18, it becomes possible to clearly identify whether or not an abnormal condition has occurred by checking the information display means.

Furthermore, for the configuration of features G1 to G18, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Characteristics Group H>
Feature H1. A history storage execution means (a function that executes history setting processing in the management CPU 112) that stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (history memory 117),
Information deriving means for deriving behavioral information corresponding to the results of games over a predetermined period using the history information stored in the history storage means (in the first embodiment, a function to execute the processing in steps S1402 to S1412 in the management CPU 112; in the third embodiment, a function to execute the processing in step S1807 in the management CPU 112; in the fifth embodiment, a function to execute the processing in step S2107 in the management CPU 112),
A first information display control means (a function that executes display processing in the management CPU 112) controls the display of an information display means (first to third notification display devices 69a to 69c in the first to tenth embodiments, and first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) so that a display corresponding to the aspect information derived by the information derivation means is shown,
A second information display control means for controlling the display of the information display means so that a display corresponding to information different from the aforementioned aspect information is shown (in the first to tenth embodiments, a function to execute the processing of steps S202 and S208 in the main CPU 63; in the eleventh embodiment, a function to execute the processing of steps S3101, S3103 and S3109 in the main CPU 63; in the twelfth embodiment, a function to execute the processing of steps S3201, S3202, S3204 and S3210 in the main CPU 63; in the thirteenth embodiment, a function to execute error display processing in the main CPU 63),
Equipped with,
The information display means has a plurality of unit light-emitting units (display segments 201a to 201g, 202a to 202g), and is configured to display a predetermined information by combining the unit light-emitting units that are in a light-emitting state among the plurality of unit light-emitting units.
The second information display control means enables the display of the other information by enabling the display of the other information by enabling the display of the other information by enabling the display of the unit light-emitting unit among the plurality of unit light-emitting units which can be enabled when the display corresponding to the manner information is enabled, and the combination of the unit light-emitting units which is enabled when the display corresponding to the other information is enabled is such that it is a combination that does not exist when the display corresponding to the manner information is enabled.

According to Feature H1, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be effectively managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, using the history information stored in the history storage means, behavioral information corresponding to the results of gameplay over a predetermined period is derived. Then, the information display means displays the behavioral information. This makes it possible to grasp the management results of game history, such as the frequency of occurrence of the predetermined event. Moreover, the information display means displays not only the behavioral information but also other information. This allows for effective utilization of the information display means.

Furthermore, by activating the unit light-emitting units that can be activated when a display corresponding to the aspect information is performed, a display corresponding to other information is performed. This allows for greater diversification of displays corresponding to aspect information while minimizing restrictions on the content of the display corresponding to the aspect information. On the other hand, the combination of unit light-emitting units that activates when a display corresponding to other information is performed does not exist when a display corresponding to aspect information is performed. Therefore, by understanding the combination of unit light-emitting units that activate, it becomes possible to determine whether a display corresponding to aspect information or a display corresponding to other information is being performed.

Feature H2. There are multiple display modes for the display corresponding to the aspect information in the information display means.
The gaming machine according to feature H1, characterized in that, among the plurality of unit light-emitting units, there are no unit light-emitting units that do not light up even when all of the display corresponding to the aspect information of the plurality of aspects is performed.

According to Feature H2, since any combination of unit light-emitting units is set to illuminate when a display corresponding to the aspect information is performed, it becomes possible to minimize restrictions on the content of the display corresponding to the aspect information in order to diversify the displays corresponding to the aspect information.

Feature H3. The system includes multiple individual information display means, including specific individual information display means (third notification display device 69c in the first to tenth embodiments, fourth notification display device 204 in the eleventh and twelfth embodiments, and third notification display device 203 and fourth notification display device 204 in the thirteenth embodiment),
The gaming machine according to feature H1 or H2, characterized in that when the second information display control means causes the display corresponding to the other information to be displayed, it causes a predetermined individual information display means (first notification display device 69a and second notification display device 69b in the first to tenth embodiments, first notification display device 201, second notification display device 202 and third notification display device 203 in the eleventh and twelfth embodiments, and first notification display device 201 and second notification display device 202 in the thirteenth embodiment) to be hidden.

According to Feature H3, a predetermined individual information display means that remains hidden when displaying information corresponding to the aspect information is displayed becomes hidden when displaying information corresponding to other information is displayed. This makes it possible to clearly identify whether the display corresponding to the aspect information or the display corresponding to other information is being displayed simply by identifying the type of individual information display means that is currently hidden.

Feature H4. The gaming machine according to Feature H3, characterized in that, when the first information display control means causes the display corresponding to the pattern information to be performed, each of the plurality of individual information display means is set to a display state.

According to Feature H4, when a display corresponding to the aspect information is performed, each of the multiple individual information display means becomes visible. Therefore, it is possible to clearly distinguish this from cases where a display corresponding to other information is performed, where a predetermined individual information display means remains hidden.

Feature H5. The gaming machine according to Feature H3 or H4, characterized in that the first information display control means sequentially changes the display of the aspect information in the information display means, and even when changing the display of the aspect information, the predetermined individual information display means is not kept in a hidden state.

According to Feature H5, when a display corresponding to the aspect information is shown, the predetermined individual information display means is not kept hidden. This makes it possible to identify whether a display corresponding to the aspect information or a display corresponding to other information is being shown in the multiple individual information display means, regardless of when the multiple individual information display means were checked.

Feature H6. Equipped with a setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
The gaming machine according to any one of features H1 to H5, characterized in that the second information display control means causes the display of the other information when the set value can be changed.

According to feature H6, the information display means that displays information corresponding to the configuration can also be used as a display means for notifying that it is possible to change the set value.

Feature H7. The gaming machine according to Feature H6, characterized in that the second information display control means causes the display of information corresponding to the currently selected setting value as the display corresponding to the other information.

According to Feature H7, the information display means that displays information corresponding to the configuration information can also be used as a display means for displaying setting values that are being changed.

Furthermore, for the configuration of features H1 to H7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features Group I>
Feature I1. A history storage execution means (a function that executes history setting processing in the management CPU 112) that stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (history memory 117),
Information deriving means for deriving behavioral information corresponding to the results of games over a predetermined period using the history information stored in the history storage means (in the first embodiment, a function to execute the processing of steps S1402 to S1412 in the management CPU 112; in the third embodiment, a function to execute the processing of step S1807 in the management CPU 112; in the fifth embodiment, a function to execute the processing of step S2107 in the management CPU 112),
A first information display control means (a function that executes display processing in the management CPU 112) controls the display of the information display means (first to fourth notification display devices 201 to 204) so that a display corresponding to the manner information derived by the information derivation means is shown,
A second information display control means (a function that executes abnormality display processing in the main CPU 63) controls the display of the information display means so that a display corresponding to the abnormal state of the gaming machine is shown,
A gaming machine characterized by having the following features.

According to Feature I1, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be effectively managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, behavioral information corresponding to the game results over a predetermined period is derived using the history information stored in the history storage means. Then, the information display means displays information corresponding to the behavioral information. This makes it possible to grasp the management results of the game history, such as the frequency of occurrence of the predetermined event. Moreover, the information display means displays not only the behavioral information but also information corresponding to abnormal states of the gaming machine. This allows for effective utilization of the information display means.

Feature I2. The gaming machine according to Feature I1, characterized in that, when the second information display control means is to display a message corresponding to the abnormal state when the abnormal state is not occurring, it displays a message corresponding to the absence of the abnormal state.

According to Feature I2, it becomes possible to clearly identify whether or not an abnormal condition has occurred by checking the information display means.

Feature I3. The gaming machine according to Feature I1 or I2, characterized in that the period during which the information display means displays information corresponding to the mode is distinguished from the period during which the information display means displays information corresponding to the abnormal state.

According to Feature I3, by understanding the status of the display in the information display means, it becomes possible to identify whether the display in the information display means corresponds to the type information or to the display corresponding to the abnormal state.

Feature I4. The gaming machine according to Feature G1 or G2, characterized in that the second information display control means controls the display of the information display means so that a display corresponding to the abnormal state is performed, thereby resulting in a display different from the display mode when a display corresponding to the mode information is performed.

According to Feature I4, by understanding the display mode of the information display means, it becomes possible to identify whether the information display means is displaying information corresponding to the mode or information corresponding to the abnormal state.

Feature I5. A gaming machine according to any one of Feature I1 to I4, characterized in that it is equipped with multiple individual information display means (first to fourth notification display devices 201 to 204) each capable of displaying multiple types of information.

According to Feature I5, by using multiple individual information display means to display information corresponding to the behavioral information, it becomes possible to display a wide variety of behavioral information. Furthermore, the presence of multiple individual information display means makes it possible to significantly differentiate the display style between cases where information corresponding to behavioral information is displayed and cases where information corresponding to abnormal conditions is displayed.

Feature I6. The gaming machine according to Feature I5, characterized in that, when the second information display control means causes a display corresponding to the abnormal state to be displayed, it causes predetermined individual information display means (first notification display device 201 and second notification display device 202) that do not become invisible when a display corresponding to the mode information is displayed among the plurality of individual information display means to become invisible.

According to Feature I6, a predetermined individual information display means that remains hidden when a display corresponding to the behavioral information is displayed becomes hidden when a display corresponding to the abnormal state is displayed. This makes it possible to clearly identify whether a display corresponding to the behavioral information or a display corresponding to the abnormal state is being displayed simply by identifying the type of individual information display means that is currently hidden.

Feature I7. When the second information display control means is to display the abnormal state, it sets to display a specific individual information display means (third notification display device 203 and fourth notification display device 204) which is in a display state when displaying the manner information among the plurality of individual information display means,
The gaming machine according to feature I6, characterized in that the content of the display means of the specific individual information display means when a display corresponding to the abnormal state is made can be displayed on the specific individual information display means when a display corresponding to the manner information is made.

According to Feature I7, in a specific individual information display means, the display content that can be displayed when a display corresponding to the manner information is performed can also be displayed when a display corresponding to an abnormal state is performed. This makes it possible to avoid restricting the display content when a display corresponding to the manner information is performed. Furthermore, even if a specific individual information display means has a configuration that allows for the same display content, a predetermined individual information display means that does not become invisible when a display corresponding to the manner information is performed, while possessing the configuration of Feature I7, becomes invisible when a display corresponding to an abnormal state is performed. Therefore, it is possible to identify which display is being performed by multiple individual information display means.

Feature I8. The gaming machine according to Feature I6 or I7, characterized in that, when the first information display control means causes the display corresponding to the mode information to be performed, each of the plurality of individual information display means is set to a display state.

According to Feature I8, when a display corresponding to the aspect information is performed, each of the multiple individual information display means becomes visible. Therefore, it is possible to clearly distinguish this from a case where a display corresponding to an abnormal state where a predetermined individual information display means is hidden is performed.

Feature I9. The gaming machine according to any one of Features I6 to I8, characterized in that the first information display control means sequentially changes the display of the aspect information in the information display means, and even when changing the display of the aspect information, the predetermined individual information display means is not kept in a hidden state.

According to Feature I9, when a display corresponding to the behavioral information is shown, the predetermined individual information display means is not kept hidden. This makes it possible to identify whether a display corresponding to the behavioral information or a display corresponding to an abnormal state is being shown in the multiple individual information display means, regardless of when the multiple individual information display means were checked.

Furthermore, for the configuration of features I1 to I9, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features Group J>
Feature J1. A history storage execution means (a function that executes history setting processing in the management CPU 112) that stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (history memory 117),
Information deriving means for deriving behavioral information corresponding to the results of games over a predetermined period using the history information stored in the history storage means (in the first embodiment, a function to execute the processing in steps S1402 to S1412 in the management CPU 112; in the third embodiment, a function to execute the processing in step S1807 in the management CPU 112; in the fifth embodiment, a function to execute the processing in step S2107 in the management CPU 112),
A first information display control means (a function that executes display processing in the management CPU 112) controls the display of an information display means (first to third notification display devices 69a to 69c in the first to tenth embodiments, and first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) so that a display corresponding to the aspect information derived by the information derivation means is shown,
Equipped with,
The first information display control means sequentially changes the display corresponding to the manner information in the information display means, and is characterized in that the information display means is not kept in a non-display state even when the display corresponding to the manner information is changed.

According to Feature J1, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, using the history information stored in the history storage means, behavioral information corresponding to the results of gameplay over a predetermined period is derived. Then, a display corresponding to the behavioral information is shown by the information display means. This makes it possible to grasp the management results of game history, such as the frequency of occurrence of the predetermined event. Furthermore, when a display corresponding to the behavioral information is shown, the information display means is not kept hidden. This makes it possible to identify the display corresponding to the behavioral information regardless of when the information display means is checked.

Feature J2. The gaming machine according to Feature J1, characterized in that it is equipped with multiple individual information display means (first to third notification display devices 69a to 69c in the first to tenth embodiments, and first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments), each capable of displaying multiple types of information.

According to feature J2, by using multiple individual information display means to display information corresponding to the aspect information, it becomes possible to display a wide variety of aspect information.

Feature J3. The gaming machine according to Feature J2, characterized in that, when the first information display control means causes the display corresponding to the pattern information, each of the plurality of individual information display means is set to a display state.

According to feature J3, when a display corresponding to the aspect information is provided, each of the multiple individual information display means enters a display state, and even when the display corresponding to the aspect information is changed, it remains in the display state. This makes it easier to understand the aspect information.

Feature J4. The gaming machine according to Feature J2 or J3, characterized in that the first information display control means is configured to display a type of information to be displayed in some of the individual information display means (first notification display device 69a in the first to tenth embodiments, and first notification display device 201 and second notification display device 202 in the eleventh to fourteenth embodiments), and to display a content of the manner information to be displayed in some of the individual information display means (second notification display device 69b and third notification display device 69c in the first to tenth embodiments, and third notification display device 203 and fourth notification display device 204 in the eleventh to fourteenth embodiments).

According to Feature J4, when a display corresponding to the type information is provided, the individual information display means for the type display target displays a display corresponding to the type of type information to be displayed, and the individual information display means for the result display displays a display corresponding to the content of the type information to be displayed. This makes it easier to understand the type information being displayed.

Furthermore, for the configuration of features J1 to J4, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Characteristics Group K>
Feature K1. When a predetermined event occurs as a result of the game being played, it is equipped with a history storage execution means (a function that executes history setting processing in the management CPU 112) that stores the corresponding game history information in the history storage means (history memory 117).
The gaming machine is characterized in that, when the history storage execution means is in a restricted state, it includes means to prevent the history information from being stored in the history storage means even if the predetermined event occurs (a function to make a negative determination in step S3501 of the main CPU 63).

According to feature K1, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, in restricted situations, even if a predetermined event occurs, the history information is not stored, thus preventing the storage of history information in situations where it is undesirable.

Feature K2. The gaming machine according to Feature K1, characterized in that the aforementioned restriction situation may occur as a situation from the start of supplying operating power to the history storage execution means until the restriction release event occurs.

According to feature K2, it becomes possible to prevent the occurrence of predetermined events during the operational check immediately after the start of power supply from being stored as historical information.

Feature K3. A means for setting the restriction status when the supply of operating power to the history storage execution means is started and the restriction condition is met (a function for executing the processing of step S3610 in the main CPU 63),
When the supply of operating power to the history storage execution means is started and the limiting condition is not met, means for not setting the limiting condition (a function that executes the processing of step S3621 in the main CPU 63),
A gaming machine characterized by having the features described in feature K2.

According to feature K3, whether or not the restriction condition is met determines whether or not the restriction status is set. This allows for preventing the restriction status from being set as needed.

Feature K4. The gaming machine according to any one of Feature K1 to K3, characterized in that the aforementioned restriction situation may occur from the time the supply of operating power to the history storage execution means begins until the number of game balls dispensed from the game area exceeds a predetermined standard number.

According to feature K4, it is possible to prevent the storage of history information from occurring until the number of game balls dispensed from the game area exceeds a predetermined standard number, after the power supply for operation has started.

Feature K5. A history storage execution means (a function that executes normal ball entry management processing, ball entry management processing in open/close execution mode and ball entry management processing in high-frequency support mode in the main CPU 63) that stores the history information of the game corresponding to the predetermined event that occurs when the game is executed, in the history storage means (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233),
Information derivation means (a function that executes the processing in step S4208 in the main CPU 63) that derives behavioral information corresponding to the results of the game during a predetermined period using the history information stored in the history storage means,
Equipped with,
The gaming machine is characterized in that the information extraction means does not extract the aforementioned mode information when a restriction is in place.

According to feature K5, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, behavioral information corresponding to the game results over a predetermined period is derived using the history information stored in the history storage means. This makes it possible to grasp the management results of the game history, such as the frequency of occurrence of the predetermined event. Moreover, in restricted situations, even if a predetermined event occurs, behavioral information is not derived, thus preventing the deriving of behavioral information in situations where it is undesirable.

Feature K6. The gaming machine according to Feature K5, characterized in that the aforementioned restriction situation may occur as a situation from the start of supplying operating power to the history storage execution means until the restriction release event occurs.

According to feature K6, it becomes possible to prevent the deriving of behavioral information using historical information based on the occurrence of predetermined events during an operational check immediately after the start of power supply.

Feature K7. The gaming machine according to Feature K5 or K6, characterized in that the aforementioned restriction situation may occur from the time the supply of operating power to the history storage execution means begins until the number of game balls dispensed from the game area exceeds a predetermined standard number.

According to feature K7, it is possible to prevent the deriving of behavioral information from occurring until the number of game balls dispensed from the game area exceeds a predetermined standard number, after the power supply for operation has started.

Furthermore, for the configuration of features K1 to K7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the inventions relating to the above-mentioned features G, H, I, J, and K, the following problems can be solved.

Pachinko machines and slot machines are well-known examples of gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, the game ball is dispensed back into the tray storage section from a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In the case of gaming machines like those exemplified above, proper management of the gaming machines is necessary, and there is still room for improvement in this regard.

<Characteristics Group L>
Feature L1. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes,
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 21st embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 21st embodiments),
When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, a saving execution means (in the 15th embodiment, a function to execute steps S3802 and S3902 to S3907 in the main CPU 63; in the 16th embodiment, a function to execute step S4402 in the main CPU 63; in the 17th embodiment, a function to execute steps S4502 to S4507 in the main CPU 63; in the 18th embodiment, a function to execute step S4602 in the main CPU 63; in the 19th embodiment, a function to execute steps S4701 and S4703 in the main CPU 63) is provided,
When the second predetermined process is completed or after it is completed, a recovery execution means (in the 15th embodiment, a function to execute steps S3804 and S3910 to S3915 in the main CPU 63; in the 16th embodiment, a function to execute step S4404 in the main CPU 63; in the 17th embodiment, a function to execute steps S4510 to S4515 in the main CPU 63; in the 18th embodiment, a function to execute step S4605 in the main CPU 63; in the 19th embodiment, a function to execute steps S4705 and S4706 in the main CPU 63) is provided,
A gaming machine characterized by having the following features.

According to feature L1, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is already executing the second predetermined process, at least a portion of the information stored in the internal storage means is saved to the predetermined storage means. This prevents the information stored in the internal storage means during the execution of the first predetermined process from being overwritten when the second predetermined process is executed. Furthermore, when the second predetermined process is completed or after its completion, the information saved to the predetermined storage means is restored to the internal storage means. This allows the system to execute a different process from the second predetermined process based on the state of the internal storage means before the execution of the second predetermined process. Therefore, various types of control can be suitably performed.

Feature L2. The gaming machine according to Feature L1, characterized in that the predetermined information is a portion of the information stored in the internal storage means.

According to feature L2, only a portion of the information stored in the internal storage means is saved to the predetermined storage means. Therefore, the storage capacity required in the predetermined storage means to save the information from the internal storage means can be reduced.

Feature L3. The internal storage means comprises at least a first storage area (WA register, BC register, DE register, HL register, IX register and IY register) and a second storage area (registers other than WA register, BC register, DE register, HL register, IX register and IY register),
The second predetermined processing execution means is configured to store information in the first storage area during the second predetermined processing, while not storing information in the second storage area.
The gaming machine according to feature L2, characterized in that the saving execution means saves the information stored in the first storage area to the predetermined storage means.

According to feature L3, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is already in the process of executing the second predetermined process, the information in the first storage area, which is the target of information storage in the second predetermined process, is saved to the predetermined storage means within the internal storage means. This allows the system to execute a different process from the second predetermined process when the second predetermined process is completed, based on the state of the internal storage means before the execution of the second predetermined process, while simultaneously reducing the storage capacity required to save the information in the predetermined storage means.

Feature L4. The predetermined storage means is
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
Equipped with,
The gaming machine according to any one of features L1 to L3, characterized in that the saving execution means saves the predetermined information to the second predetermined storage area.

According to feature L4, by providing a first predetermined storage area and a second predetermined storage area in the predetermined storage means, it becomes possible to clearly differentiate the storage locations of information in the predetermined storage means between the first predetermined process and the second predetermined process. This prevents information used in the other process from being erased when one of the first or second predetermined processes is executed. In this case, when transitioning from executing the first predetermined process to executing the second predetermined process, or when the system enters the state of executing the second predetermined process, at least a portion of the information stored in the internal storage means is saved to the second predetermined storage area. This makes it possible to save the information in the internal storage means immediately before the second predetermined process begins, and to save this information without using the first predetermined storage area.

Feature L5. The aforementioned evacuation execution means is
When the situation changes from executing the first predetermined process to executing the second predetermined process, means for saving the first predetermined information, which is a portion of the information stored in the internal storage means, to the first predetermined storage area in the first predetermined process (in the 15th embodiment, a function to execute the process in step S3802 in the main CPU 63; in the 16th embodiment, a function to execute the process in step S4402 in the main CPU 63),
When the situation changes from executing the first predetermined process to executing the second predetermined process, means for saving a portion of the information stored in the internal storage means, which is the second predetermined information, to the second predetermined storage area during the second predetermined process (in the 15th embodiment, a function to execute the processes of steps S3902 to S3907 in the main CPU 63; in the 17th embodiment, a function to execute the processes of steps S4502 to S4507 in the main CPU 63; in the 18th embodiment, a function to execute the process of step S4602 in the main CPU 63; in the 19th embodiment, a function to execute the processes of steps S4702 and S4703 in the main CPU 63),
A gaming machine characterized by having the features described in feature L4.

According to feature L5, the first predetermined information, which is a portion of the information stored in the internal storage means, is saved to the first predetermined storage area during the first predetermined process, and the second predetermined information, which is a portion of the information stored in the internal storage means, is saved to the second predetermined storage area during the second predetermined process. This makes it possible to save the information at a timing that is favorable for each piece of information stored in the internal storage means, and also makes it possible to distribute the process for saving the information between the first predetermined process and the second predetermined process.

Feature L6. The gaming machine according to Feature L5, characterized in that the first predetermined information is information in a flag register provided in the internal storage means.

According to feature L6, it becomes possible to appropriately save the information in the flag register while the first predetermined process is being executed.

Feature L7. The second predetermined storage area is,
A stack area (stack area 224 for non-specific control) where information can be written by a push command and read by a pop command,
A work area (work area 223 for non-specific control) where information can be written to and read by load commands,
Equipped with,
The gaming machine according to any one of features L4 to L6, characterized in that the saving execution means saves the predetermined information to one of the stack area and the work area.

According to feature L7, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation becomes one where the second predetermined process is being executed, at least a portion of the information stored in the internal storage means is saved to one of the stack area and work area in the second predetermined storage area. This makes it possible to consolidate the destinations for saving information, and simplifies the processing configurations for saving and restoring the information.

Feature L8. The gaming machine according to Feature L7, characterized in that the saving execution means saves the predetermined information to the work area.

According to feature L8, since the backup destination for at least some of the information stored in the internal memory is the work area, it becomes possible to back up the information without cumulatively modifying the stack pointer.

Feature L9. The first predetermined storage area allows for the storage and retrieval of information when the first predetermined process is executed, and when the second predetermined process is executed, it allows for the retrieval of information but does not allow for the storage of information.
The gaming machine according to any one of features L4 to L8, characterized in that the second predetermined storage area allows for the storage and retrieval of information when the second predetermined processing is performed, and allows for the retrieval of information but does not allow for the storage of information when the first predetermined processing is performed.

According to feature L9, the first predetermined memory area can be treated as a dedicated memory area for the first predetermined process, and the second predetermined memory area can be treated as a dedicated memory area for the second predetermined process.

Feature L10. The predetermined storage means is
A stack area (stack area 224 for non-specific control) where information can be written by a push command and read by a pop command,
A work area (work area 223 for non-specific control) where information can be written to and read by load commands,
Equipped with,
The gaming machine according to any one of features L1 to L9, characterized in that the saving execution means saves the predetermined information to one of the stack area and the work area.

According to feature L10, it becomes possible to consolidate the backup locations of predetermined information, and to simplify the processing configuration for backing up predetermined information and the processing configuration for restoring predetermined information.

Feature L11. The gaming machine according to Feature L10, characterized in that the saving execution means saves the predetermined information to the work area.

According to feature L11, since the destination for saving the predetermined information is the work area, it becomes possible to save the information without cumulatively changing the stack pointer.

Feature L12. The predetermined information is a portion of the information stored in the internal storage means.
The gaming machine according to feature L11, characterized in that the saving execution means includes means for saving specific information, which is a part of the information stored in the internal storage means, to the stack area when the situation changes from the situation in which the first predetermined process is being executed to the situation in which the second predetermined process is being executed, or when the situation changes to the situation in which the second predetermined process is being executed (a function to execute the process of step S3802 in the main CPU 63).

According to feature L12, in a configuration where predetermined information is saved to the work area, specific information is saved to the stack area. This makes it possible to distribute the information stored in the internal storage means between the work area and the stack area during saving.

Feature L13. The gaming machine according to Feature L12, characterized in that the predetermined information contains more information than the specific information.

According to feature L13, by saving predetermined information with a larger amount of information than specific information to the work area, it becomes possible to prevent a large amount of information from being cumulatively stored in the stack area when saving information stored in the internal storage means.

Feature L14. When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation becomes one where the second predetermined process is being executed, the information in the stack pointer provided in the internal storage means becomes fixed information.
The gaming machine according to any one of the features L1 to L13, characterized in that the information of the stack pointer provided in the internal storage means is not subject to saving by the saving execution means.

According to feature L14, since there is no need to allocate capacity in the predetermined storage means to save the stack pointer information, the capacity of the predetermined storage means can be reduced. Furthermore, even in a configuration where the stack pointer information is not saved, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, the stack pointer information becomes fixed information. Therefore, even without saving the stack pointer information as described above, it is possible to restore the stack pointer information to what it was before the second predetermined process started.

Feature L15. The gaming machine according to Feature L14, characterized by having means for setting the fixed information in the stack pointer when the second predetermined process is completed or after it is completed (in the 15th embodiment, a function to execute the process in step S3909 in the main CPU 63; in the 17th embodiment, a function to execute the process in step S4509 in the main CPU 63; and in the 18th embodiment, a function to execute the process in step S4604 in the main CPU 63).

According to feature L15, when the second predetermined process is completed or after it has been completed, it is possible to restore the stack pointer information to what it was before the second predetermined process was started.

Feature L16. The gaming machine according to Feature L14 or L15, characterized by providing means for setting second corresponding start information corresponding to the second predetermined process in the stack pointer when transitioning from the state of executing the first predetermined process to the state of executing the second predetermined process, or when the state of executing the second predetermined process has been established. (In the 15th embodiment, a function to execute the process of step S3901 in the main CPU 63; in the 17th embodiment, a function to execute the process of step S4501 in the main CPU 63; in the 18th embodiment, a function to execute the process of step S4601 in the main CPU 63).

According to feature L16, when the second predetermined process is initiated, the second corresponding start information corresponding to the second predetermined process is set to the stack pointer, making it possible to store information in the stack area at the appropriate address during the second predetermined process.

Feature L17. The first predetermined process includes a process for controlling the progress of the game,
The gaming machine according to any one of features L1 to L16, characterized in that the second predetermined process includes a process for managing the gaming history.

According to feature L17, a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process. This makes it possible to prevent the information used in the game history management process from being overwritten when the process for controlling the progress of the game is executed.

Feature L18. The predetermined storage means is
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
Equipped with,
The gaming machine according to feature L17, characterized in that the second predetermined storage area includes a history storage area (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which history information of the game corresponding to a predetermined event occurs when the game is executed.

According to feature L18, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, since a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten during the execution of the process for controlling the progress of the game.

Feature L19. The gaming machine according to Feature L18, characterized in that the second predetermined processing execution means includes information derivation means (a function that executes the processing in step S4208 in the main CPU 63) that derives mode information corresponding to the results of the game during a predetermined period using the history information stored in the history storage area.

According to feature L19, by using the history information stored in the history storage area to derive behavioral information corresponding to the results of gameplay over a predetermined period, it becomes possible to grasp the management results of game history, such as the frequency of occurrence of predetermined events.

Feature L20. The gaming machine according to Feature L19, characterized in that the second predetermined storage area includes a mode information storage area (calculation result storage area 234) for storing the mode information derived by the information derivation means.

According to feature L20, when behavioral information corresponding to the results of gameplay over a predetermined period is derived using historical information, that behavioral information is stored in the behavioral information storage area. This makes it possible to grasp the management results of the game history at any time. Furthermore, since a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, it is possible to prevent the information stored in the behavioral information storage area from being overwritten during the execution of the process for controlling the progress of the game.

Furthermore, for the configuration of features L1 to L20, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Characteristics of Group M>
Feature M1. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes.
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 21st embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 21st embodiments),
When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, a saving execution means (in the 15th embodiment, a function to execute steps S3902 to S3907 in the main CPU 63; in the 17th embodiment, a function to execute steps S4502 to S4507 in the main CPU 63; in the 18th embodiment, a function to execute step S4602 in the main CPU 63; in the 19th embodiment, a function to execute steps S4701 and S4703 in the main CPU 63) saves predetermined information, which is at least a portion of the information stored in the internal storage means, to a predetermined storage means (main RAM 65).
When the second predetermined process is completed or after it is completed, a recovery execution means (in the 15th embodiment, a function to execute the processes of steps S3910 to S3915 in the main CPU 63; in the 17th embodiment, a function to execute the processes of steps S4510 to S4515 in the main CPU 63; in the 18th embodiment, a function to execute the process of step S4605 in the main CPU 63; in the 19th embodiment, a function to execute the processes of steps S4705 and S4706 in the main CPU 63) is provided,
Equipped with,
The aforementioned saving execution means is characterized by saving the predetermined information to the predetermined storage means by a load command.

According to Feature M1, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is already in the state to execute the second predetermined process, the predetermined information, which is at least a portion of the information stored in the internal storage means, is saved to the predetermined storage means. This prevents the information stored in the internal storage means during the execution of the first predetermined process from being overwritten when the second predetermined process is executed. Furthermore, when the second predetermined process is completed or after completion, the predetermined information saved to the predetermined storage means is restored to the internal storage means. This allows the system to execute a process different from the second predetermined process based on the state of the internal storage means before the execution of the second predetermined process. When the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is already in the state to execute the second predetermined process, the predetermined information is saved to the predetermined storage means by a load instruction. This makes it possible to save the predetermined information without requiring a change to the stack pointer.

Feature M2. The predetermined storage means is
A stack area (stack area 224 for non-specific control) where information can be written by a push command and read by a pop command,
A work area (work area 223 for non-specific control) where information can be written to and read by load commands,
Equipped with,
The gaming machine according to feature M1, characterized in that the saving execution means saves the predetermined information to the work area.

According to feature M2, since the backup destination for predetermined information, which is at least a portion of the information stored in the internal storage means, is the work area, it becomes possible to back up the information without cumulatively changing the stack pointer.

Feature M3. The predetermined information is a portion of the information stored in the internal storage means.
The gaming machine according to feature M2, characterized in that the saving execution means includes means for saving specific information, which is a part of the information stored in the internal storage means, to the stack area when the situation changes from the situation in which the first predetermined process is being executed to the situation in which the second predetermined process is being executed, or when the situation has become such that the second predetermined process is being executed (a function to execute the process of step S3802 in the main CPU 63).

According to feature M3, in a configuration where predetermined information is saved to the work area, specific information is saved to the stack area. This makes it possible to distribute the information stored in the internal storage means between the work area and the stack area during saving.

Feature M4. The gaming machine described in Feature M3, characterized in that the predetermined information contains more information than the specific information.

According to feature M4, by saving predetermined information with a larger amount of data than specific information to the work area, it becomes possible to prevent a large amount of information from being cumulatively stored in the stack area when saving information stored in the internal storage means.

Feature M5. The work area is,
A first work area (work area 221 for specific control) where information is stored when the first predetermined process is executed,
A second work area (work area 223 for non-specific control) where information is stored when the second predetermined process is executed,
Equipped with,
The gaming machine according to any one of features M2 to M4, characterized in that the saving execution means saves the predetermined information to the second work area.

According to feature M5, by providing a first work area and a second work area within the work area, it becomes possible to clearly differentiate the storage locations of information in the work area between the first predetermined process and the second predetermined process. This prevents information used in the other process from being erased when one of the processes is executed. In this case, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, at least a portion of the information stored in the internal storage means is saved to the second work area. This makes it possible to save the information in the internal storage means immediately before the second predetermined process starts, and to save this information without using the first work area.

Feature M6. The first work area allows for the storage and retrieval of information when the first predetermined process is executed, and when the second predetermined process is executed, it is possible to read information but not to store information.
The gaming machine according to feature M5, characterized in that the second work area allows for the storage and retrieval of information when the second predetermined process is executed, and while the first predetermined process allows for the retrieval of information, it does not allow for the storage of information.

According to feature M6, the first work area can be treated as a dedicated storage area for the first predetermined process, and the second work area can be treated as a dedicated storage area for the second predetermined process.

Feature M7. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes.
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 21st embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 21st embodiments),
When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, a saving execution means (in the 15th embodiment, a function to execute steps S3902 to S3907 in the main CPU 63; in the 17th embodiment, a function to execute steps S4502 to S4507 in the main CPU 63; in the 18th embodiment, a function to execute step S4602 in the main CPU 63; in the 19th embodiment, a function to execute steps S4701 and S4703 in the main CPU 63) saves predetermined information, which is at least a portion of the information stored in the internal storage means, to a predetermined storage means (main RAM 65).
When the second predetermined process is completed or after it is completed, a recovery execution means (in the 15th embodiment, a function to execute the processes of steps S3910 to S3915 in the main CPU 63; in the 17th embodiment, a function to execute the processes of steps S4510 to S4515 in the main CPU 63; in the 18th embodiment, a function to execute the process of step S4605 in the main CPU 63; in the 19th embodiment, a function to execute the processes of steps S4705 and S4706 in the main CPU 63) is provided,
Equipped with,
The predetermined storage means is
A stack area (stack area 224 for non-specific control) where information can be written by a push command and read by a pop command,
A work area (work area 223 for non-specific control) where information can be written to and read by load commands,
Equipped with,
The aforementioned saving execution means is characterized by saving the predetermined information to one of the stack area and the work area.

According to feature M7, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, predetermined information, which is at least a portion of the information stored in the internal storage means, is saved to the predetermined storage means. This makes it possible to prevent the information stored in the internal storage means during the execution of the first predetermined process from being overwritten when the second predetermined process is executed. Furthermore, when the second predetermined process is completed or after its completion, the predetermined information saved to the predetermined storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process based on the state of the internal storage means before the execution of the second predetermined process when the second predetermined process is completed.

Furthermore, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is already executing the second predetermined process, the predetermined information is saved to either the stack area or the work area of the predetermined storage means. This makes it possible to consolidate the information saving locations and simplify the processing configurations for saving and restoring the information.

Furthermore, for the configuration of features M1 to M7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features Group N>
Feature N1. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes,
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 21st embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 21st embodiments),
Equipped with,
A gaming machine characterized in that, when the situation changes from executing the first predetermined process to executing the second predetermined process, the information in the stack pointer provided in the internal storage means becomes fixed information.

According to feature N1, when the system transitions from executing the first predetermined process to executing the second predetermined process, the information of the stack pointer stored in the internal storage means becomes fixed information. Therefore, there is no need to save the stack pointer information when starting the second predetermined process. This eliminates the need to allocate storage space for saving the stack pointer information. Furthermore, since the information of the stack pointer becomes fixed information when the system transitions from executing the first predetermined process to executing the second predetermined process, it is possible to restore the stack pointer information to its state before the start of the second predetermined process without saving the stack pointer information as described above.

Feature N2. The gaming machine according to Feature N1, characterized in that, upon completion of the second predetermined processing or after completion, it includes means for setting the fixed information in the stack pointer (in the 15th embodiment, a function to execute the processing in step S3909 in the main CPU 63; in the 17th embodiment, a function to execute the processing in step S4509 in the main CPU 63; and in the 18th embodiment, a function to execute the processing in step S4604 in the main CPU 63).

According to feature N2, when the second predetermined process is completed or after it has been completed, it is possible to restore the stack pointer information to what it was before the second predetermined process was started.

Feature N3. The gaming machine according to Feature N1 or N2, characterized by providing means for setting second corresponding start information corresponding to the second predetermined process in the stack pointer when transitioning from the state of executing the first predetermined process to the state of executing the second predetermined process (in the 15th embodiment, a function to execute the process of step S3901 in the main CPU 63; in the 17th embodiment, a function to execute the process of step S4501 in the main CPU 63; and in the 18th embodiment, a function to execute the process of step S4601 in the main CPU 63).

According to feature N3, when the second predetermined process is initiated, the second corresponding start information corresponding to the second predetermined process is set to the stack pointer, making it possible to store information in the stack area at the appropriate address during the second predetermined process.

Feature N4. When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, a saving execution means (in the 15th embodiment, a function to execute steps S3802 and S3902 to S3907 in the main CPU 63; in the 16th embodiment, a function to execute step S4402 in the main CPU 63; in the 17th embodiment, a function to execute steps S4502 to S4507 in the main CPU 63; in the 18th embodiment, a function to execute step S4602 in the main CPU 63; in the 19th embodiment, a function to execute steps S4701 and S4703 in the main CPU 63) is provided,
When the second predetermined process is completed or after it is completed, a recovery execution means (in the 15th embodiment, a function to execute steps S3804 and S3910 to S3915 in the main CPU 63; in the 16th embodiment, a function to execute step S4404 in the main CPU 63; in the 17th embodiment, a function to execute steps S4510 to S4515 in the main CPU 63; in the 18th embodiment, a function to execute step S4605 in the main CPU 63; in the 19th embodiment, a function to execute steps S4705 and S4706 in the main CPU 63) is provided,
Equipped with,
The gaming machine according to any one of the features N1 to N3, characterized in that the information of the stack pointer provided in the internal storage means is not subject to saving by the saving execution means.

According to feature N4, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, at least a portion of the information stored in the internal storage means is saved to the predetermined storage means. This makes it possible to prevent the information stored in the internal storage means during the execution of the first predetermined process from being overwritten when the second predetermined process is executed. Furthermore, when the second predetermined process is completed or after it has been completed, the information saved to the predetermined storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process from the state of the internal storage means before the execution of the second predetermined process when the second predetermined process is completed. In addition, since the information of the stack pointer is not subject to saving, there is no need to reserve capacity in the predetermined storage means for saving the information of the stack pointer. Therefore, it is possible to reduce the capacity of the predetermined storage means. Furthermore, even in a configuration where the stack pointer information is not saved, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system enters the state of executing the second predetermined process, the stack pointer information becomes fixed. Therefore, even without saving the stack pointer information as described above, it is possible to restore the stack pointer information to what it was before the second predetermined process began.

Feature N5. The predetermined storage means is
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
Equipped with,
The gaming machine according to feature N4, characterized in that the saving execution means saves the predetermined information to the second predetermined storage area.

According to feature N5, by providing a first predetermined storage area and a second predetermined storage area in the predetermined storage means, it becomes possible to clearly differentiate the storage locations of information in the predetermined storage means between the first predetermined process and the second predetermined process. This prevents information used in the other process from being erased when one of the first or second predetermined processes is executed. In this case, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation becomes one where the second predetermined process is being executed, at least a portion of the information stored in the internal storage means is saved to the second predetermined storage area. This makes it possible to save the information in the internal storage means immediately before the second predetermined process starts, and to save this information without using the first predetermined storage area.

Feature N6. The first predetermined storage area is capable of storing and reading information when the first predetermined process is executed, and when the second predetermined process is executed, it is possible to read information but not store information.
The gaming machine according to feature N5, characterized in that the second predetermined storage area allows for the storage and retrieval of information when the second predetermined processing is performed, and allows for the retrieval of information but does not allow for the storage of information when the first predetermined processing is performed.

According to feature N6, the first predetermined memory area can be treated as a dedicated memory area for the first predetermined process, and the second predetermined memory area can be treated as a dedicated memory area for the second predetermined process.

Furthermore, for the configuration of features N1 to N6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Characteristics Group O>
Feature O1. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes.
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 21st embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 21st embodiments),
When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, the first state setting means (a function that executes the processing in steps S4803 to S4808 in the main CPU 63) sets the state of a predetermined storage area (WA register, BC register, DE register, HL register, IX register, and IY register), which is at least a part of the storage area in the internal storage means, to a predetermined state,
A second state setting means (a function that executes the processing in steps S4903 to S4908 in the main CPU 63) that sets the state of the predetermined storage area to the predetermined state when the second predetermined processing is completed or after it is completed,
A gaming machine characterized by having the following features.

According to Feature O1, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is in the process of executing the second predetermined process, the state of the predetermined storage area in the internal storage means is set to a predetermined state. When the second predetermined process is completed, or after completion, the state of the predetermined storage area is set to the predetermined state again. This makes it possible to maintain the predetermined state of the predetermined storage area before and after the second predetermined process. Therefore, it is possible to prevent the state of the predetermined storage area resulting from one of the first or second predetermined processes from affecting the other process. As a result, various types of control can be performed effectively.

Feature O2. The gaming machine according to Feature O1, characterized in that the predetermined state is the state when the supply of operating power to the control means is started.

According to feature O2, the predetermined memory area is set to the state when the supply of operating power to the control means is started, thus simplifying the processing configuration for setting to the predetermined state.

Feature O3. The gaming machine according to Feature O1 or O2, characterized in that the predetermined state is a state in which the predetermined memory area is cleared to "0".

According to Feature O3, since the predetermined memory area is set to a predetermined state of "0" (cleared), the processing configuration for setting it to the predetermined state can be simplified.

Feature O4. The gaming machine according to any one of Feature O1 to O3, characterized in that the predetermined storage area is a part of the storage area in the internal storage means.

According to feature O4, since only a portion of the internal storage means's storage area is set to a predetermined state, the processing load required to set it to that predetermined state can be reduced.

Feature O5. The internal storage means comprises at least the predetermined storage area and a separate storage area (registers other than the WA register, BC register, DE register, HL register, IX register, and IY register),
The second predetermined processing execution means is configured to store information in the predetermined storage area during the second predetermined processing, while not storing information in the other storage area.
The gaming machine according to feature O4, characterized in that the first state setting means and the second state setting means are configured not to change the state of the separate storage area.

According to Feature O5, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system enters the state where the second predetermined process is being executed, the predetermined storage area in the internal storage means, which is the target of information storage in the second predetermined process, is set to a predetermined state. This prevents the state of the predetermined storage area due to the first predetermined process from affecting the second predetermined process. Furthermore, since the state of other storage areas is not changed, setting them to a predetermined state when the second predetermined process begins does not affect processing after the second predetermined process is completed.

Feature O6. The gaming machine according to any one of Features O1 to O5, characterized in that the information in the predetermined storage area before the setting of the predetermined state by the first state setting means is information that is not used after the completion of the second predetermined process.

According to feature O6, even if the predetermined storage area is set to a predetermined state when the conditions for executing the second predetermined process are met, or when the conditions for executing the second predetermined process are met, it is possible to ensure that this does not affect the processing after the completion of the second predetermined process.

Feature O7. When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, a saving execution means (a function that executes the process of step S4802 in the main CPU 63) saves some of the predetermined information (flag register information), which is stored in the internal storage means, to a predetermined storage means (main RAM 65),
When the second predetermined process is completed or after it is completed, a recovery execution means (a function that executes the process of step S4810 in the main CPU 63) is provided to restore the predetermined information saved in the predetermined storage means back to the internal storage means,
A gaming machine according to any one of features O1 to O6, characterized by having the following features.

According to Feature O7, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is already executing the second predetermined process, a portion of the information stored in the internal storage means, known as predetermined information, is saved to the predetermined storage means. This prevents the information stored in the internal storage means during the execution of the first predetermined process, which is necessary for the subsequent execution of the first predetermined process, from being overwritten when the second predetermined process is executed. Furthermore, when the second predetermined process is completed, or after its completion, the predetermined information saved to the predetermined storage means is restored to the internal storage means. This allows the system to execute a process different from the second predetermined process, based on the state of the internal storage means before the execution of the second predetermined process, once the second predetermined process is completed.

Feature O8. The first predetermined process includes a process for controlling the progress of the game,
The gaming machine according to any one of features O1 to O7, characterized in that the second predetermined process includes a process for managing the gaming history.

According to feature O8, the first predetermined process is to execute a process for controlling the progress of the game, and the second predetermined process is to execute a process for managing the game history. This makes it possible to prevent the information used in the game history management process from being overwritten when the process for controlling the progress of the game is executed.

Feature O9. The predetermined storage means is
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
Equipped with,
The gaming machine according to feature O8, wherein the second predetermined storage area includes a history storage area (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which history information of the game corresponding to a predetermined event occurs when the game is executed.

According to Feature O9, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, since a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten during the execution of the process for controlling the progress of the game.

Feature O10. The gaming machine according to Feature O9, characterized in that the second predetermined processing execution means includes information derivation means (a function that executes the processing in step S4208 in the main CPU 63) that derives mode information corresponding to the results of the game during a predetermined period using the history information stored in the history storage area.

According to feature O10, by using the history information stored in the history storage area to derive behavioral information corresponding to the results of gameplay over a predetermined period, it becomes possible to grasp the management results of game history, such as the frequency of occurrence of predetermined events.

Feature O11. The gaming machine according to Feature O10, characterized in that the second predetermined storage area includes a mode information storage area (calculation result storage area 234) for storing the mode information derived by the information derivation means.

According to feature O11, when behavioral information corresponding to the results of gameplay over a predetermined period is derived using historical information, that behavioral information is stored in the behavioral information storage area. This makes it possible to grasp the management results of the game history at any time. Furthermore, by executing a process to control the progress of the game as the first predetermined process, and a process to manage the game history as the second predetermined process, it becomes possible to prevent the information stored in the behavioral information storage area from being overwritten during the execution of the process to control the progress of the game.

Furthermore, for the configuration of features O1 to O11, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Characteristics P group>
Feature P1. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes.
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 21st embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 21st embodiments),
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
A gaming machine characterized by having the following features.

According to feature P1, a first predetermined storage area and a second predetermined storage area are provided. The first predetermined storage area is treated as a dedicated storage area for the first predetermined process, and the second predetermined storage area is treated as a dedicated storage area for the second predetermined process. This makes it possible to clearly differentiate the storage locations of information in the predetermined storage means for the first predetermined process and the second predetermined process. Therefore, it is possible to prevent information used in the other process from being erased when one of the first or second predetermined processes is executed.

Feature P2. The first predetermined process includes a process for controlling the progress of the game,
The gaming machine according to feature P1, characterized in that the second predetermined process includes a process for managing the gaming history.

According to feature P2, a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process. This makes it possible to prevent the information used in the game history management process from being overwritten when the process for controlling the progress of the game is executed.

Feature P3. The gaming machine according to Feature P2, characterized in that the second predetermined storage area includes a history storage area (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which history information of the game is stored when a predetermined event occurs as a result of the game being played.

According to Feature P3, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, since a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten during the execution of the process for controlling the progress of the game.

Feature P4. The gaming machine according to Feature P3, characterized in that the second predetermined processing execution means includes information derivation means (a function that executes the processing in step S4208 in the main CPU 63) that derives mode information corresponding to the results of the game during a predetermined period using the history information stored in the history storage area.

According to Feature P4, by using the history information stored in the history memory area to derive behavioral information corresponding to the results of gameplay over a predetermined period, it becomes possible to grasp the management results of game history, such as the frequency of occurrence of predetermined events.

Feature P5. The gaming machine according to Feature P4, characterized in that the second predetermined storage area includes a mode information storage area (calculation result storage area 234) for storing the mode information derived by the information derivation means.

According to feature P5, when behavioral information corresponding to the results of gameplay over a predetermined period is derived using historical information, that behavioral information is stored in the behavioral information storage area. This makes it possible to grasp the management results of the game history at any time. Furthermore, since a process to control the progress of the game is executed as the first predetermined process, and a process to manage the game history is executed as the second predetermined process, it is possible to prevent the information stored in the behavioral information storage area from being overwritten during the execution of the process to control the progress of the game.

Feature P6. A first saving means (in the 15th embodiment, a function that executes the process in step S3802 in the main CPU 63, and in the 16th embodiment, a function that executes the process in step S4402 in the main CPU 63) that saves a portion of the information stored in the internal storage means, when the situation changes from executing the first predetermined process to executing the second predetermined process,
When the situation changes from executing the first predetermined process to executing the second predetermined process, a second saving means (in the 15th embodiment, a function to execute steps S3902 to S3907 in the main CPU 63; in the 17th embodiment, a function to execute steps S4502 to S4507 in the main CPU 63; in the 18th embodiment, a function to execute step S4602 in the main CPU 63; in the 19th embodiment, a function to execute steps S4701 and S4703 in the main CPU 63) saves a portion of the second predetermined information stored in the internal storage means to the second predetermined storage area during the second predetermined process.
A gaming machine according to any one of features P1 to P5, characterized by having the following features.

According to feature P6, the first predetermined information, which is a portion of the information stored in the internal storage means, is saved to the first predetermined storage area during the first predetermined process, and the second predetermined information, which is a portion of the information stored in the internal storage means, is saved to the second predetermined storage area during the second predetermined process. This makes it possible to save the information at a timing that is favorable for each piece of information stored in the internal storage means, and also makes it possible to distribute the process for saving the information between the first predetermined process and the second predetermined process.

Feature P7. When the second predetermined process is completed or after it is completed, a first restoration execution means (in the 15th embodiment, a function that executes the process of step S3804 in the main CPU 63, in the 16th embodiment, a function that executes the process of step S4404 in the main CPU 63) restores the first predetermined information saved in the first predetermined storage area to the internal storage means,
When the second predetermined processing is completed or after it is completed, a second recovery execution means (in the 15th embodiment, a function to execute the processing of steps S3910 to S3915 in the main CPU 63; in the 17th embodiment, a function to execute the processing of steps S4510 to S4515 in the main CPU 63; in the 18th embodiment, a function to execute the processing of step S4605 in the main CPU 63; in the 19th embodiment, a function to execute the processing of steps S4705 and S4706 in the main CPU 63) is provided to restore the second predetermined information saved in the second predetermined storage area to the internal storage means.
A gaming machine characterized by having the features described in P6.

According to feature P7, when the second predetermined process is completed or after it is completed, the first predetermined information saved in the first predetermined storage area is returned to the internal storage means, and the second predetermined information saved in the second predetermined storage area is returned to the internal storage means. Therefore, it is possible to restore the state of the internal storage means to the state it was in before the second predetermined process was started.

Feature P8. The gaming machine according to feature P6 or P7, characterized in that the first predetermined information includes information from a flag register provided in the internal storage means.

According to feature P8, it becomes possible to appropriately save the information in the flag register while the first predetermined process is being executed.

Feature P9. The gaming machine according to any one of Feature P6 to P8, characterized in that the second predetermined information includes the information of all registers in the internal storage means.

According to feature P9, since the information of all registers in the internal storage means is saved together, there is no need to selectively save the information of each register.

Feature P10. The second predetermined storage area is,
A stack area (stack area 224 for non-specific control) where information is written by a push command and read by a pop command,
A work area (work area 223 for non-specific control) where information is written and read by load commands,
Equipped with,
The gaming machine according to feature P9, characterized in that the second saving execution means saves the second predetermined information to one of the stack area and the work area.

According to feature P10, the information of all registers in the internal storage means is saved to either the stack area or the work area in the second predetermined storage area. This makes it possible to consolidate the destination for saving all register information, simplifying the processing configuration for saving and restoring the information.

Feature P11. The gaming machine according to Feature P10, characterized in that the second saving execution means saves the second predetermined information to the stack area.

According to feature P11, it becomes possible to save all register information without using the work area.

Feature P12. The gaming machine according to any one of features P6 to P11, characterized in that the second predetermined information includes information about the stack pointer of the internal storage means.

According to feature P12, it becomes possible to appropriately save the stack pointer information while the first predetermined process is being executed.

Furthermore, for the configuration of features P1 to P12, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

According to the inventions relating to the above-mentioned features L, M, N, O, and P, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front where game balls are stored. These stored balls are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters a ball entry section in the game area, for example, it is dispensed back into the tray storage section from a payout device. Furthermore, some pachinko machines are known to have an upper and lower tray storage section. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like those exemplified above, various controls need to be implemented effectively, and there is still room for improvement in this regard.

<Features Q group>
Feature Q1. A control means (MPU 62) that executes various processes and temporarily stores information in an internal storage means (registers of the main CPU 63) when executing a process,
A history storage means (management RAM 241) is provided as a separate chip from the control means and is capable of temporarily storing information,
Equipped with,
The game machine is characterized in that the control means includes a history storage execution means (a function that executes normal ball entry management processing in the main CPU 63, ball entry management processing in the opening/closing execution mode, and ball entry management processing in the high-frequency support mode) which stores the history information of the game corresponding to a predetermined event when the game is executed.

According to Feature Q1, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be effectively managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, since the history storage means is provided as a separate chip from the control means, it is possible to increase the storage capacity for storing history information while utilizing a general-purpose control means.

Feature Q2. The gaming machine according to Feature Q1, characterized in that the control means includes a predetermined storage means (main RAM 65) for temporarily storing information when various processes are executed.

According to Feature Q2, in a configuration that includes not only a predetermined storage means provided in the control means but also a history storage means provided as a separate chip from the control means, it becomes possible to store and retain a large amount of history information by storing history information in the history storage means.

Feature Q3. The gaming machine according to Feature Q2, characterized in that the control means temporarily stores the information in the predetermined storage means when performing processing related to the history information.

According to Feature Q3, in a configuration where the history storage means for storing history information is provided as a separate chip from the control means, when processing related to history information is executed, the information is temporarily stored in a predetermined storage means provided in the control means. Therefore, it is possible to prevent a drastic decrease in processing speed when executing processing related to history information.

Feature Q4. The gaming machine according to any one of Feature Q1 to Q3, characterized in that the control means includes an information derivation means (a function that executes the processing in step S4208 in the main CPU 63) that derives behavioral information corresponding to the results of the game during a predetermined period using the history information stored in the history storage means.

According to Feature Q4, by using the history information stored in the history storage means to derive behavioral information corresponding to the results of gameplay over a predetermined period, it becomes possible to grasp the management results of game history, such as the frequency of occurrence of predetermined events.

Feature Q5. The gaming machine according to Feature Q4, characterized in that the second predetermined storage area includes a mode information storage area (calculation result storage area 234) for storing the mode information derived by the information derivation means.

According to Feature Q5, when behavioral information corresponding to the results of gameplay over a predetermined period is derived using historical information, that behavioral information is stored in the behavioral information storage area. This makes it possible to grasp the management results of gameplay history at any time.

Furthermore, for the configuration of features Q1 to Q5, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned group of features Q, the following problems can be solved.

Pachinko machines and slot machines are well-known examples of gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, the game ball is dispensed back into the tray storage section from a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In the case of gaming machines like those exemplified above, proper management of the gaming machines is necessary, and there is still room for improvement in this regard.

<Features R group>
Feature R1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
When the supply of operating power to the control means having the setting means is started, a situation generating means (a function that executes the processing of steps S5003 to S5006 in the main CPU 63, in another embodiment a function that executes the processing of steps S5503 to S5507 in the main CPU 63, and in the 23rd embodiment a function that executes the processing of steps S5703 to S5705 and S5715 in the main CPU 63) is provided to create a situation in which the setting value to be used can be changed based on the occurrence of multiple events including the first and second events.
A gaming machine characterized by having the following features.

According to Feature R1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, the player expects the target setting value to be the most advantageous. In this case, for the target setting value to be set, multiple events, including the first and second events, must occur when the power supply to the control means begins. This makes it difficult to fraudulently manipulate the setting value to be used.

Feature R2. It is equipped with an opening detection means for detecting that the opening/closing body (front door frame 14) is in an open state (in the 22nd embodiment, it is a function that executes the processing of step S5005 in the main CPU 63; in another embodiment, it is a function that executes the processing of step S5505 in the main CPU 63; in the 23rd embodiment, it is a function that executes the processing of step S5703 in the main CPU 63),
The gaming machine according to feature R1, characterized in that the situation generation means identifies that the first event has occurred based on the fact that the opening/closing body is in an open state as determined by the opening/closing detection means.

According to feature R2, the opening/closing mechanism must be in an open state for the target setting value to be set. This makes it possible to highlight any fraudulent attempts to set the target setting value, thereby making it easier to detect such fraudulent activity.

Feature R3. It is equipped with a separate open detection means for detecting that the separate open/closed body (game machine body 12) is in an open state (in the 22nd embodiment, it is a function that executes the processing of step S5006 in the main CPU 63; in another embodiment, it is a function that executes the processing of step S5506 in the main CPU 63; in the 23rd embodiment, it is a function that executes the processing of step S5704 in the main CPU 63),
The gaming machine according to feature R2, characterized in that the situation generation means identifies that the second event has occurred based on the fact that the separate opening detection means has determined that the separate opening body is in an open state.

According to feature R3, in order for the target setting value to be set, it is necessary not only to open one of the opening/closing mechanisms but also to open another opening/closing mechanism. This makes it more difficult to fraudulently set the target setting value and also makes such fraudulent activity more conspicuous.

Feature R4. The setting means is configured to perform at least one of the following based on the operation of a predetermined operating means (update button 68b, reset button 68c):
The gaming machine according to feature R2 or R3, characterized in that the predetermined operating means is configured to be operable by opening a separate opening/closing body.

According to feature R4, the setting of the target value cannot be performed unless a different opening/closing element, which is opened to enable operation of a predetermined operating means, is opened. This makes it more difficult to fraudulently set the target value and also makes such fraudulent activity more conspicuous.

Feature R5. The opening and closing body defines the front side of the game machine in the game area through which the game balls flow down.
The gaming machine according to any one of the features R2 to R4, characterized in that the gaming area is opened to the front of the gaming machine by opening the opening/closing body.

According to feature R5, in order for the target setting value to be set, the opening mechanism must be in the open position, opening the game area to the front of the game machine. This makes it more difficult to fraudulently set the target setting value, and also makes such fraudulent activity more conspicuous.

Feature R6. The gaming machine according to any one of Features R1 to R5, characterized in that the situation generation means identifies that one of the multiple events has occurred based on the fact that a predetermined operation has been performed on the setting key insertion part (setting key insertion part 68a) using a setting key.

According to feature R6, in order for the target setting value to be set, it is necessary not only to perform a predetermined operation using the setting key on the setting key insertion part, but also to generate a separate event. This makes it difficult to fraudulently set the target setting value.

Feature R7. The game machine according to any one of Features R1 to R6, characterized in that the situation generation means identifies that one of the multiple events has occurred based on the occurrence of a predetermined game event (operation of the launching device 28, ball entry into the through gate 35) that occurs when a game is played.

According to Feature R7, in order for the target setting value to be set, it is necessary not only to generate a predetermined game event that occurs when a game is played, but also to generate a separate event. This makes it difficult to fraudulently manipulate the setting value to be used.

Feature R8. The game machine according to any one of Features R1 to R7, characterized in that the situation generation means identifies that one of the multiple events has occurred based on the detection of a game ball by a ball entry detection means (gate detection sensor 49a) that detects when a game ball enters a predetermined ball entry section provided in the game area.

According to feature R8, in order for the target setting value to be set, it is necessary to insert a game ball into the designated ball entry area, and also to cause another event to occur. This makes it difficult to fraudulently set the target setting value.

Feature R9. The system includes a setting value notification means (a function that executes setting confirmation processing in the main CPU 63) which notifies the setting value to be used set by the setting means via a notification means.
The gaming machine according to any one of the features R1 to R8, characterized in that the setting value notification means causes the notification means to notify the setting value to be used, which was set by the setting means, based on the occurrence of a plurality of events including the first event and the second event.

According to feature R9, it becomes more difficult to fraudulently verify the settings. Furthermore, since the administrator of the gaming hall only needs to trigger the first and second events when setting or verifying the target settings, the work becomes standardized, making it easier to understand each step.

Feature R10. Setting means for setting a target setting value from among multiple setting values corresponding to the player's advantage (a function that executes setting value update processing in the main CPU 63),
A situation generating means (in the 22nd embodiment, a function that executes the processing of steps S5003 to S5006 in the main CPU 63; in another embodiment, a function that executes the processing of steps S5503 to S5507 in the main CPU 63; in the 23rd embodiment, a function that executes the processing of steps S5703 to S5705 and S5715 in the main CPU 63) is provided to create a situation in which a setting is possible, based on the occurrence of multiple events including the fact that a predetermined operation is performed by a setting key on the setting key insertion part (setting key insertion part 68a) and a separate event different from the predetermined operation performed by the setting key on the setting key insertion part.
A gaming machine characterized by having the following features.

According to feature R10, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, the player expects the target setting value to be the most advantageous. In this case, in order for the target setting value to be set, it is necessary not only to perform a predetermined operation with the setting key on the setting key insertion part, but also to generate a separate event. This makes it difficult to fraudulently set the target setting value.

Feature R11. It is equipped with an opening detection means for detecting that the opening/closing body (front door frame 14) is in an open state (in the 22nd embodiment, it is a function that executes the processing of step S5005 in the main CPU 63; in another embodiment, it is a function that executes the processing of step S5505 in the main CPU 63; in the 23rd embodiment, it is a function that executes the processing of step S5703 in the main CPU 63),
The gaming machine according to feature R10, characterized in that the situation generation means identifies that the separate event is occurring based on the fact that the opening/closing body is in an open state, as determined by the opening detection means.

According to feature R11, the opening/closing mechanism must be in an open state in order for the target setting value to be set. This makes it possible to highlight any fraudulent activity, such as the unauthorized setting of the target setting value, and consequently, to make such fraudulent activity easier to detect.

Feature R12. It is equipped with a separate open detection means for detecting that the separate open/closed body (game machine body 12) is in an open state (in the 22nd embodiment, it is a function that executes the processing of step S5006 in the main CPU 63; in another embodiment, it is a function that executes the processing of step S5506 in the main CPU 63; in the 23rd embodiment, it is a function that executes the processing of step S5704 in the main CPU 63),
The gaming machine according to feature R11, characterized in that the situation generation means identifies that one of the multiple events has occurred based on the fact that the separate opening detection means has determined that the separate opening body is in an open state.

According to feature R12, in order for the target setting value to be set, it is necessary not only to open one of the opening/closing mechanisms but also to open another opening/closing mechanism. This makes it more difficult to fraudulently set the target setting value and also makes such fraudulent activity more conspicuous.

Feature R13. The setting means is configured to perform at least one of the following based on the operation of a predetermined operating means (update button 68b, reset button 68c):
The gaming machine according to feature R11 or R12, characterized in that the predetermined operating means is configured to be operable by opening a separate opening/closing body.

According to feature R13, the setting of the target value cannot be performed unless a different opening/closing body, which is opened to enable operation of a predetermined operating means, is opened. This makes it more difficult to fraudulently set the target value and also makes such fraudulent activity more conspicuous.

Feature R14. The opening and closing body defines the front side of the game machine in the game area through which the game balls flow down.
The gaming machine according to any one of the features R11 to R13, characterized in that the gaming area is opened to the front of the gaming machine by opening the opening/closing body.

According to feature R14, in order for the target setting value to be set, the opening mechanism must be in the open position, opening the game area to the front of the game machine. This makes it more difficult to fraudulently set the target setting value, and also makes such fraudulent activity more conspicuous.

Feature R15. The gaming machine according to any one of Feature R10 to R14, characterized in that the situation generation means identifies that one of the multiple events has occurred based on the occurrence of a predetermined game event (operation of the launching device 28, ball entry into the through gate 35) that occurs when a game is played.

According to feature R15, in order for the target setting value to be set, it is necessary not only to perform a predetermined operation with the setting key on the setting key insertion part, but also to generate a predetermined game event that occurs when the game is played. This makes it difficult to fraudulently set the target setting value.

Feature R16. The game machine according to any one of Features R10 to R15, characterized in that the situation generation means identifies that one of the multiple events has occurred based on the detection of a game ball by a ball entry detection means (gate detection sensor 49a) that detects when a game ball enters a predetermined ball entry section provided in the game area.

According to feature R16, in order to set the target setting value, it is necessary not only to perform a predetermined operation with the setting key on the setting key insertion part, but also to insert a game ball into the designated ball entry part. This makes it difficult to fraudulently set the target setting value.

Feature R17. The system is equipped with a setting value notification means (a function that executes setting confirmation processing in the main CPU 63) which notifies the setting value to be used set by the setting means via a notification means.
The gaming machine according to any one of the features R10 to R16, characterized in that the setting value notification means notifies the setting value to be used, set by the setting means, based on the fact that a predetermined operation has been performed by the setting key on the setting key insertion part and that a plurality of events have occurred, including both of the separate events.

According to feature R17, it becomes more difficult to fraudulently verify the settings. Furthermore, when setting or verifying the settings, the administrator of the gaming hall only needs to perform the prescribed operation using the setting key on the setting key insertion point and trigger a separate event. This standardizes the work and makes it easier to understand each step.

Furthermore, for the configuration of features R1 to R17, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned feature group R, the following problems can be solved.

Pachinko machines and slot machines are well-known examples of gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, the game ball is dispensed back into the tray storage section from a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In the case of gaming machines like those exemplified above, it is necessary to address fraudulent activities against the machines, and there is still room for improvement in this regard.

<Characteristic S Group>
Feature S1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A means for generating a state in which the setting value to be used can be changed (in the 22nd embodiment, a function to execute the processing of steps S5003 to S5006 and steps S5401 to S5408 in the main CPU 63; in another embodiment, a function to execute the processing of steps S5503 to S5507 in the main CPU 63; in the 23rd embodiment, a function to execute the processing of steps S5703 to S5705 and S5715 in the main CPU 63; in the 24th embodiment, a function to execute the processing of steps S5801 to S5804 in the main CPU 63; in the 25th embodiment, a function to execute the processing of steps S5901 to S5904 in the main CPU 63),
A setting value determination means (in the 22nd embodiment, a function that executes the processing in steps S5017 and S5111 to S5112 in the main CPU 63; in another embodiment, a function that executes the processing in steps S5611 to S5612 in the main CPU 63), which determines whether the setting value before the setting-possible state is reached is the same as the setting value set by the setting means.
A gaming machine characterized by having the following features.

According to Feature S1, since the system is configured to select a setting value from multiple levels corresponding to the player's advantage, the player expects a more advantageous setting value to be selected. In this case, it is determined whether the setting value before the setting availability state is the same as the setting value set in that setting availability state. This makes it possible to perform processing corresponding to whether the setting values are the same across the setting availability state. Therefore, when a setting value is selected, it becomes possible to create a favorable situation for that setting result, and the setting value setting process can be performed more efficiently.

Feature S2. The gaming machine according to Feature S1, characterized in that it includes a same-time means (in the 22nd embodiment, a function to execute the process in step S5113 of the main CPU 63; in another embodiment, a function to execute the process in step S5613 of the main CPU 63) that causes the setting value before the setting-possible state is reached to be the same as the setting value set by the setting means, based on the setting value recognition means's recognition that the setting value is the same as the setting value set by the setting means.

According to feature S2, when the setting value is the same across the configurable state, the same-time processing is executed, making it possible to create a favorable situation for having the same setting value.

Feature S3. The gaming machine according to Feature S2, characterized in that the same-time means performs a process as the same-time processing to ensure that notification is given when the set value has not been changed.

According to feature S3, it becomes possible to notify the administrator of the gaming hall, etc., that the setting value was the same across the period when the setting was possible.

Feature S4. A gaming machine according to any one of Features S1 to S3, characterized by the provision of a non-same-time means (in the 22nd embodiment, a function to execute the process in step S5114 of the main CPU 63; in another embodiment, a function to execute the process in step S5614 of the main CPU 63) that, based on the determination by the setting value determination means that the setting value before the setting-possible state is reached and the setting value set by the setting means are different, executes a corresponding non-same-time process.

According to feature S4, if the setting value is not the same across the configurable state, a non-identical processing is executed, making it possible to create a favorable situation in response to the change in the setting value.

Feature S5. The gaming machine according to Feature S4, characterized in that the non-same-time means performs a process as the non-same-time processing to ensure that notification is given when the set value has been changed.

According to feature S5, it becomes possible to notify the administrator of the gaming hall, etc., that the setting value has been changed after a period of configurability.

Feature S6. The gaming machine according to any one of Features S1 to S5, characterized in that the status generation means causes the setting to become available based on the need to erase the information in the storage means that stores the setting value after the supply of operating power to the control means having the setting means has started.

According to feature S6, if it becomes necessary to erase the information in the storage means that stores the setting value, the system enters a setting-enabled state. This prevents the game from continuing even after the setting value information has been erased. In this case, the system, with the configuration of feature S1 described above, determines whether the setting value before entering the setting-enabled state is the same as the setting value set in that state. This makes it possible to execute processing corresponding to whether the setting value is the same across the setting-enabled state.

Feature S7. The gaming machine according to Feature S6, characterized by providing a means (in the 22nd embodiment, a function to execute the process in step S5113 in the main CPU 63; in another embodiment, a function to execute the process in step S5613 in the main CPU 63) for providing notification that the setting value was not changed, based on the setting value recognition means determining that the setting value before the setting-possible state was reached and the setting value set by the setting means are the same.

According to feature S7, even if the setting becomes available due to the erasure of information in the memory means, if the setting value remains the same during that period, a notification is issued indicating that the setting value has not been changed. This makes it possible to inform the player that the setting value has not been changed even if the setting becomes available mid-game, allowing the player to continue playing with peace of mind.

Feature S8. The means for generating the situation is,
Based on the commencement of the supply of operating power to the control means having the setting means, a first status generating means (in the 22nd embodiment, a function that executes the processing of steps S5003 to S5006 in the main CPU 63; in another embodiment, a function that executes the processing of steps S5503 to S5507 in the main CPU 63; in the 23rd embodiment, a function that executes the processing of steps S5703 to S5705 and S5715 in the main CPU 63) is provided to cause the setting state to be established.
After the supply of operating power to the control means has started, a second status generating means (in the 22nd embodiment, a function to execute the processing of steps S5401 to S5408 in the main CPU 63; in the 24th embodiment, a function to execute the processing of steps S5801 to S5804 in the main CPU 63; in the 25th embodiment, a function to execute the processing of steps S5901 to S5904 in the main CPU 63) is provided to cause the setting to become possible, based on the need to erase the information in the storage means that stores the setting value after the supply of operating power to the control means has started,
Equipped with,
The gaming machine according to any one of features S1 to S7, characterized in that the setting value determination means determines whether the setting value before the setting condition is created and the setting value set by the setting means are the same, regardless of whether the setting condition is created by the first condition generating means or the setting condition is created by the second condition generating means.

According to feature S8, when it becomes necessary to erase the information in the storage means that stores the setting value, the system enters a state where setting is possible. This prevents the game from continuing even after the setting value information has been erased. In this case, using the same process as when the system enters a state where setting is possible based on the start of power supply to the control means, it is possible to execute a process corresponding to whether the setting value is the same or not, when the system enters a state where setting is possible due to the erasure of the information in the storage means.

Furthermore, for the configuration of features S1 to S8, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned feature group S, the following problems can be solved.

Pachinko machines and slot machines are well-known examples of gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, the game ball is dispensed back into the tray storage section from a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like those exemplified above, it is necessary to create favorable conditions when the setting values that determine the advantage of the gaming machine are set, and there is still room for improvement in this regard.

<Features T group>
Feature T1. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes.
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 25th embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 25th embodiments),
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
A first monitoring execution means for monitoring whether the first predetermined storage area is normal (in the 22nd embodiment, a function to execute the processing of steps S5401 to S5404 in the main CPU 63; in the 24th embodiment, a function to execute the processing of steps S5801 to S5804 in the main CPU 63; in the 25th embodiment, a function to execute the processing of steps S5901 to S5904 in the main CPU 63; in the 32nd embodiment, a function to execute the processing of steps S7701 to S7703 in the main CPU 63),
A second monitoring execution means for monitoring whether the second predetermined storage area is normal (in the 22nd embodiment, a function to execute the processing of steps S5405 to S5408 in the main CPU 63; in the 24th embodiment, a function to execute the processing of steps S5809, S5810, S5812 and S5813 in the main CPU 63; in the 25th embodiment, a function to execute the processing of steps S6101, S6102, S6105 and S6106 in the main CPU 63; in the 32nd embodiment, a function to execute the processing of steps S7706 to S7708 in the main CPU 63),
A gaming machine characterized by having the following features.

According to feature T1, a first predetermined storage area and a second predetermined storage area are provided. The first predetermined storage area is treated as a dedicated storage area for the first predetermined process, and the second predetermined storage area is treated as a dedicated storage area for the second predetermined process. This makes it possible to clearly differentiate the storage locations of information in the predetermined storage means for the first predetermined process and the second predetermined process. Therefore, it is possible to prevent information used in the other process from being erased when one of the first or second predetermined processes is executed. Furthermore, by monitoring whether the first predetermined storage area is functioning correctly and monitoring whether the second predetermined storage area is functioning correctly, it is possible to determine whether the conditions are such that the first and second predetermined processes can be performed correctly.

Feature T2. The gaming machine according to Feature T1, characterized in that monitoring by the first monitoring execution means and monitoring by the second monitoring execution means are performed in either the first predetermined process or the second predetermined process.

According to feature T2, monitoring whether the first predetermined storage area is functioning correctly and monitoring whether the second predetermined storage area is functioning correctly are performed centrally in either the first predetermined process or the second predetermined process. This simplifies the processing configuration compared to a configuration where monitoring of each storage area is distributed between the first and second predetermined processes.

Feature T3. The gaming machine according to Feature T1 or T2, characterized in that monitoring by the first monitoring execution means and monitoring by the second monitoring execution means are performed in the first predetermined process.

According to feature T3, it becomes possible to consolidate and execute the monitoring of whether the first predetermined storage area is functioning normally and the monitoring of whether the second predetermined storage area is functioning normally in the first predetermined process.

Feature T4. A gaming machine according to any one of Feature T1 to T3, characterized by comprising a predetermined erasure means (in the 22nd embodiment, a function to execute the process in step S5410 in the main CPU 63; in the 24th embodiment, a function to execute the processes in steps S5806, S5811, and S5814 in the main CPU 63; and in the 25th embodiment, a function to execute the processes in steps S5906, S6103, and S6107 in the main CPU 63) for erasing the information in the first predetermined storage area based on the first monitoring execution means identifying that the first predetermined storage area is abnormal.

According to feature T4, if the first predetermined storage area is abnormal, the information in the first predetermined storage area is erased, thereby preventing the first predetermined process from being executed while the first predetermined storage area is in an abnormal state.

Feature T5. The gaming machine according to Feature T4, characterized in that the predetermined erasure means erases the information in the first predetermined storage area and erases the information in the second predetermined storage area based on the first monitoring execution means identifying that the first predetermined storage area is abnormal.

According to feature T5, if the first predetermined storage area is abnormal, not only the first predetermined storage area but also the second predetermined storage area is erased. This makes it possible to erase the information in the second predetermined storage area regardless of the monitoring results by the second monitoring execution means, if there is a possibility of an abnormality occurring in the second predetermined storage area.

Feature T6. The gaming machine according to Feature T4 or T5, characterized in that the predetermined erasure means erases the information in the second predetermined storage area based on the second monitoring execution means identifying that the second predetermined storage area is abnormal.

According to feature T6, if the first predetermined storage area is abnormal, the information in the first predetermined storage area is erased, thereby preventing the first predetermined process from being executed while the first predetermined storage area is in an abnormal state.

Feature T7. The gaming machine according to Feature T6, characterized in that the predetermined erasure means erases the information in the second predetermined storage area and erases the information in the first predetermined storage area based on the second monitoring execution means identifying that the second predetermined storage area is abnormal.

According to feature T7, if the second predetermined storage area is abnormal, not only the second predetermined storage area but also the first predetermined storage area is erased. This makes it possible to erase the information in the first predetermined storage area regardless of the monitoring results by the first monitoring execution means, if there is a possibility of an abnormality in the first predetermined storage area.

Feature T8. The gaming machine according to any one of Feature T4 to T7, characterized in that the process for erasing information using the predetermined erasure means is performed in either the first predetermined process or the second predetermined process.

According to feature T8, the process of erasing information in each predetermined storage area based on the identification of an anomaly is consolidated and executed in either the first predetermined process or the second predetermined process. This simplifies the processing configuration compared to a configuration where the erasure of information in each storage area is distributed between the first and second predetermined processes.

Feature T9. The gaming machine according to any one of Feature T4 to T7, characterized in that the process for erasing information using the predetermined erasure means is performed in the first predetermined process.

According to feature T9, it becomes possible to consolidate and execute the process of erasing information in each predetermined storage area based on the identification of an abnormality in the first predetermined process.

Feature T10. The first predetermined process includes a process for controlling the progress of the game,
The gaming machine according to any one of features T1 to T9, characterized in that the second predetermined process includes a process for managing the gaming history.

According to feature T10, a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process. This makes it possible to prevent the information used in the process for managing the game history from being overwritten when the process for controlling the progress of the game is executed.

Feature T11. The gaming machine according to Feature T10, characterized in that the second predetermined storage area includes a history storage area (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which history information of the game corresponding to a predetermined event occurring when the game is executed.

According to feature T11, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, since a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten during the execution of the process for controlling the progress of the game.

Feature T12. The gaming machine according to Feature T11, characterized in that the second predetermined processing execution means includes information derivation means (a function that executes the processing in step S4208 in the main CPU 63) that derives mode information corresponding to the results of the game during a predetermined period using the history information stored in the history storage area.

According to feature T12, by using the history information stored in the history storage area to derive behavioral information corresponding to the results of gameplay over a predetermined period, it becomes possible to grasp the management results of game history, such as the frequency of occurrence of predetermined events.

Feature T13. The gaming machine according to Feature T12, characterized in that the second predetermined storage area includes a mode information storage area (calculation result storage area 234) for storing the mode information derived by the information derivation means.

According to feature T13, when behavioral information corresponding to the results of gameplay over a predetermined period is derived using historical information, that behavioral information is stored in the behavioral information storage area. This makes it possible to grasp the management results of the game history at any time. Furthermore, by executing a process to control the progress of the game as the first predetermined process, and a process to manage the game history as the second predetermined process, it becomes possible to prevent the information stored in the behavioral information storage area from being overwritten during the execution of the process to control the progress of the game.

Furthermore, for the configuration of features T1 to T13, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Features Group U>
Feature U1. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes.
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 34th embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 34th embodiments),
When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, a state setting means (in the 26th embodiment, a function to execute the processes of steps S6202 to S6204 and step S6211 in the main CPU 63; in the 27th embodiment, a function to execute the processes of steps S6302 to S6307 and step S6312 in the main CPU 63) is provided,
A gaming machine characterized by having the following features.

According to feature U1, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation becomes one where the second predetermined process is being executed, the state of the flag register in the internal storage means is set to a specific state. This makes it possible to start the second predetermined process when the state of the flag register is a predetermined specific state. Therefore, various controls can be performed effectively.

Feature U2. The gaming machine according to Feature U1, characterized in that the specific state is the state when the supply of operating power to the control means is started.

According to feature U2, the flag register is set to the state when power is supplied to the control means as a specific state, thus simplifying the processing configuration for setting to that specific state.

Feature U3. The gaming machine according to feature U1 or U2, characterized in that the specific state is a state in which the flag register is cleared to "0".

According to feature U3, the flag register is set to a "0" state as a specific condition, thus simplifying the processing configuration required to set it to that specific state.

Feature U4. A gaming machine according to any one of Feature U1 to U3, characterized by having means for causing the state of the flag register to become the specific state when the second predetermined process is completed or after it is completed (in the 26th embodiment, a function to execute the processes of steps S6213 to S6218 in the main CPU 63; in the 27th embodiment, a function to execute the processes of steps S6314 to S6322 in the main CPU 63).

According to feature U4, the state of the flag register is set to a specific state not only when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is in the process of executing the second predetermined process, but also when the second predetermined process is completed or has been completed. This makes it possible to resume the first predetermined process when the state of the flag register is in a predetermined specific state. Furthermore, it is possible to set the state of the flag register to a specific state before and after the second predetermined process. Therefore, it is possible to prevent the state of the flag register resulting from one of the first or second predetermined processes from affecting the other process.

Feature U5. The control means is equipped with a predetermined storage means (main RAM 65) in which information is temporarily stored when processing is performed,
The state setting means is,
Means for causing the state of a predetermined storage area in the predetermined storage means to become the specific state (in the 26th embodiment, a function to execute the processing of steps S6202 to S6204 in the main CPU 63; in the 27th embodiment, a function to execute the processing of steps S6302 to S6307 in the main CPU 63),
Means for causing the state of the flag register to become the specified state by storing the information stored in the predetermined storage area in the flag register (in the 26th embodiment, a function to execute the process of step S6211 in the main CPU 63; in the 27th embodiment, a function to execute the process of step S6312 in the main CPU 63),
A gaming machine according to any one of the features U1 to U4, characterized by having the following features.

According to feature U5, even if the control means does not allow the state of the flag register to be directly set to a specific state as an instruction, it becomes possible to set the state of the flag register to a specific state by writing information to and reading that information from a predetermined storage means.

Feature U6. The predetermined storage means is
A stack area (specific control stack area 222) on which the control means can write information by push command and on which the control means can read information by pop command,
The control means has a work area (work area 221 for specific control) where it is possible to write and read information by load command,
Equipped with,
The gaming machine according to feature U5, characterized in that the predetermined memory area is provided in the stack area.

According to feature U6, even in configurations where information stored in the work area cannot be directly written to the flag register, it is possible to set the state of the flag register to a specific state by writing information to and reading that information from the stack area.

Feature U7. When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, the internal storage means is provided with means to cause the state of a predetermined register to be in a predetermined state (in the 26th embodiment, a function to execute the processes of steps S6205 to S6210 in the main CPU 63; in the 27th embodiment, a function to execute the processes of steps S6308 to S6311 in the main CPU 63).
The gaming machine according to any one of features U1 to U6, characterized in that the state setting means causes the state of the flag register to become the specific state after the state of the predetermined register has been set to the predetermined state.

The state of the flag register may change each time various processes are executed in the control means. In this case, according to feature U7, since the state of the flag register is set to a specific state after the state of a predetermined register is set to a predetermined state, it becomes possible to ensure that the flag register is in a specific state immediately before the start of the second predetermined process.

Feature U8. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes.
The game machine is characterized in that the control means includes means for causing the state of the flag register to be in a specific state (in the 26th embodiment, a function to execute the processing of steps S6202 to S6204 and step S6211 in the main CPU 63, and in the 27th embodiment, a function to execute the processing of steps S6302 to S6307 and step S6312 in the main CPU 63).

According to feature U8, it is possible to set the state of the flag register to a specific state as needed.

Furthermore, for the configuration of features U1 to U8, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features Group V>
Feature V1. It is equipped with control means (main CPU 63) that executes various processes and temporarily stores information in internal storage means (registers of the main CPU 63) when executing processes,
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 34th embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 34th embodiments),
When the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, a save execution means (in the 15th embodiment, a function to execute the process in step S3802 in the main CPU 63; in the 16th embodiment, a function to execute the process in step S4402 in the main CPU 63; in the 20th embodiment, a function to execute the process in step S4802 in the main CPU 63; in the 28th embodiment, a function to execute the processes in steps S6402 to S6405 in the main CPU 63; in the 29th embodiment, a function to execute the processes in steps S6502 to S6509 in the main CPU 63) is provided,
When the second predetermined process is completed or after it is completed, a recovery execution means (a function that executes the process of step S3804 in the main CPU 63 in the 15th embodiment, a function that executes the process of step S4404 in the main CPU 63 in the 16th embodiment, a function that executes the process of step S4810 in the main CPU 63 in the 20th embodiment, a function that executes the process of steps S6407 to S6415 in the main CPU 63 in the 28th embodiment, and a function that executes the process of steps S6511 to S6518 in the main CPU 63) is provided,
A gaming machine characterized by having the following features.

According to Feature V1, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is already executing the second predetermined process, the information in the flag register is saved to a predetermined storage means. This prevents the information stored in the flag register during the execution of the first predetermined process from being overwritten when the second predetermined process is executed. Furthermore, when the second predetermined process is completed, or after its completion, the information saved in the predetermined storage means is restored to the flag register. This allows the system to execute a different process from the second predetermined process based on the state of the flag register before the execution of the second predetermined process. Therefore, various types of control can be suitably performed.

Feature V2. The predetermined storage means is
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
Equipped with,
The gaming machine according to feature V1, characterized in that the saving execution means saves the information of the flag register to the first predetermined storage area.

According to Feature V2, by providing a first predetermined storage area and a second predetermined storage area in the predetermined storage means, it becomes possible to clearly differentiate the storage locations of information in the predetermined storage means between the first predetermined process and the second predetermined process. This prevents information used in the other process from being erased when one of the first or second predetermined processes is executed. In this case, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation becomes one where the second predetermined process is to be executed, the information in the flag register is saved to the first predetermined storage area. This makes it possible to save the information in the flag register immediately before the second predetermined process starts, and to save this information without using the second predetermined storage area.

Feature V3. The first predetermined storage area allows for the storage and retrieval of information when the first predetermined process is executed, and when the second predetermined process is executed, it allows for the retrieval of information but does not allow for the storage of information.
The gaming machine according to feature V2, characterized in that the second predetermined storage area allows for the storage and retrieval of information when the second predetermined processing is performed, and allows for the retrieval of information but does not allow for the storage of information when the first predetermined processing is performed.

According to feature V3, the first predetermined memory area can be treated as a dedicated memory area for the first predetermined process, and the second predetermined memory area can be treated as a dedicated memory area for the second predetermined process.

Feature V4. The predetermined storage means is
A stack area (specific control stack area 222) where information can be written by a push command and read by a pop command,
A work area (work area 221 for specific control) where information can be written to and read by load commands,
Equipped with,
The gaming machine according to any one of features V1 to V3, characterized in that the saving execution means saves the information of the flag register to one of the stack area and the work area.

According to Feature V4, when the system transitions from executing the first predetermined process to executing the second predetermined process, or when the system is already executing the second predetermined process, the flag register information is saved to either the stack area or the work area of the second predetermined storage area. This allows for the consolidation of information saving locations, simplifying the processing configurations for saving and restoring the information.

Feature V5. The gaming machine according to Feature V4, characterized in that the saving execution means saves the information of the flag register to the work area.

According to Feature V5, because the flag register information is saved to the work area, it becomes possible to save this information without cumulatively modifying the stack pointer.

Feature V6. The aforementioned retraction execution means is
Means for storing the information of the flag register in a predetermined register provided in the internal storage means (in the 28th embodiment, a function to execute the processing of steps S6402 and S6403 in the main CPU 63; in the 29th embodiment, a function to execute the processing of steps S6502 to S6505 in the main CPU 63),
Means for storing the information of the flag register stored in the predetermined register in the predetermined storage means (in the 28th embodiment, a function to execute the processing of step S6404 in the main CPU 63; in the 29th embodiment, a function to execute the processing of step S6506 in the main CPU 63),
A gaming machine according to any one of features V1 to V5, characterized by having the following features.

According to Feature V6, even in a configuration where the information in the flag register cannot be directly saved to the predetermined storage means as an instruction of the control means, it is possible to save the information in the flag register to the predetermined storage means by utilizing the writing of information to the predetermined register and the writing of the information stored in the predetermined register to the predetermined storage means.

Furthermore, for the configuration of features V1 to V6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features of Group W>
Feature W1. Equipped with control means (main CPU 63) for executing various processes,
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 34th embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 34th embodiments),
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
An abnormal event monitoring means (program monitoring unit 252) that monitors whether or not an abnormal event has occurred,
A means for generating an erasure status (reset signal output unit 251) that enables a situation in which an information erasure process is performed on at least the first predetermined storage area based on the fact that the abnormal event has been identified by the abnormal event monitoring means,
A gaming machine characterized by having the following features.

According to feature W1, a first predetermined storage area and a second predetermined storage area are provided. The first predetermined storage area is treated as a dedicated storage area for the first predetermined process, and the second predetermined storage area is treated as a dedicated storage area for the second predetermined process. This makes it possible to clearly differentiate the storage locations of information in the predetermined storage means for the first predetermined process and the second predetermined process. Therefore, it is possible to prevent information used in the other process from being erased when one of the first predetermined process or the second predetermined process is executed. Furthermore, based on the identification of an abnormal event, an information erasure process is performed on at least the first predetermined storage area. This makes it possible to prevent the first predetermined process from being executed with the information in the first predetermined storage area still retained despite the occurrence of an abnormal event.

Feature W2. The control means is,
Means for performing a process to store power outage response information when the supply of operating power to the control means is stopped (in the 30th embodiment, a function to perform the processes in steps S6709 and S6710 in the main CPU 63; in the 32nd embodiment, a function to perform the processes in steps S7609 to S7611 in the main CPU 63),
In a situation where the aforementioned power outage response information is not stored, if the supply of operating power to the control means is started and the processing at the start of supply is executed, means to ensure that the information erasure process is executed for at least the first predetermined storage area (in the 30th embodiment, a function to execute the process in step S6607 in the main CPU 63; in the 31st embodiment, a function to execute the clear process in case of an abnormality in the main CPU 63; in the 32nd embodiment, a function to execute the processes in steps S7704, S7705, S7808 and S7810 in the main CPU 63),
Equipped with,
The gaming machine according to feature W1, characterized in that the erasure status generation means causes the control means to execute the power outage response information when the power outage response information is not stored, based on the abnormal event monitoring means identifying that the abnormal event has occurred.

According to feature W2, if power supply to the control means is initiated and the power supply initiation process is executed while power outage response information is not stored, information erasure processing is performed at least on the first predetermined storage area. This prevents the first predetermined processing from being executed with the information in the first predetermined storage area still retained when power supply to the control means is initiated while power outage processing is not properly performed. In this case, based on the identification of an abnormal event, the power supply initiation process is executed by the control means while power outage response information is not stored. This configuration, which executes information erasure processing when power supply initiation processing is executed by the control means while power outage response information is not stored, makes it possible to ensure that information erasure processing is performed in response to abnormal events.

Feature W3. The control means executes various processes when a reset signal is received, and starts the power supply start process based on the change from a situation where the reset signal is not received to a situation where the reset signal is received while operating power is being supplied.
The game machine according to feature W2, characterized in that the erase status generation means, based on the abnormal event monitoring means identifying that the abnormal event has occurred, sets the control means to a state in which it does not receive the reset signal, and then sets the control means to a state in which it receives the reset signal.

According to feature W3, the above-mentioned excellent effects can be achieved by switching the reception state of the reset signal.

Feature W4. The control means is configured to temporarily store information in an internal storage means (registers and program counter of the main CPU 63) when executing a process, and is configured to temporarily save the information stored in the internal storage means to the first predetermined storage area.
The abnormal event monitoring means monitors whether or not an abnormality has occurred in the information stored in the internal storage means as the abnormal event,
The gaming machine according to any one of features W1 to W3, characterized in that the erasure status generating means causes a situation in which the erasure process of the information is performed on at least the first predetermined storage area and the internal storage means.

According to feature W4, since the information stored in the internal storage means can be temporarily saved to the first predetermined storage area, if an abnormality occurs in the information stored in the internal storage means, there is a possibility that an abnormality has also occurred in the information stored in the first predetermined storage area. In this case, if an abnormality occurs in the information stored in the internal storage means, the information erasure process is performed not only on the internal storage means but also on the first predetermined storage area. This makes it possible to prevent the first predetermined process from being executed in its current state even if an abnormality has occurred in the information stored in the first predetermined storage area.

Feature W5. The gaming machine according to any one of Feature W1 to W4, characterized in that the erasure status generation means prevents the erasure process of the information from being executed on the second predetermined storage area even if the abnormal event monitoring means identifies that an abnormal event has occurred.

According to feature W5, even if an abnormal event occurs, it becomes possible to retain the information in the second predetermined memory area.

Feature W6. The gaming machine according to any one of Features W1 to W4, characterized in that the erasure status generating means causes a situation in which the erasure process of the information is executed for both the first predetermined storage area and the second predetermined storage area, based on the abnormal event monitoring means identifying that the abnormal event has occurred.

According to feature W6, based on the identification of an abnormal event, information erasure processing is performed on both the first and second predetermined storage areas. This prevents the first predetermined processing from being executed while the information in the first predetermined storage area remains intact despite the occurrence of an abnormal event, and also prevents the second predetermined processing from being executed while the information in the second predetermined storage area remains intact despite the occurrence of an abnormal event.

Feature W7. The gaming machine according to Feature W6, characterized in that the erasure process of the information in the first predetermined storage area is performed in the first predetermined process, and the erasure process of the information in the second predetermined storage area is performed in the second predetermined process.

According to feature W7, with regard to the information erasure process, it becomes possible to treat the first predetermined storage area as a dedicated storage area for the first predetermined process, and the second predetermined storage area as a dedicated storage area for the second predetermined process.

Feature W8. The first predetermined process includes a process for controlling the progress of the game,
The gaming machine according to any one of features W1 to W7, characterized in that the second predetermined process includes a process for managing the gaming history.

According to feature W8, a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process. This makes it possible to prevent the information used in the process for managing the game history from being overwritten when the process for controlling the progress of the game is executed.

Feature W9. The gaming machine according to Feature W8, characterized in that the second predetermined storage area includes a history storage area (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which history information of the game corresponding to a predetermined event occurring when the game is executed.

According to feature W9, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, since a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten during the execution of the process for controlling the progress of the game.

Feature W10. The gaming machine according to Feature W9, characterized in that the second predetermined processing execution means includes information derivation means (a function that executes the processing in step S4208 in the main CPU 63) that derives pattern information corresponding to the results of the game during a predetermined period using the history information stored in the history storage area.

According to feature W10, by using the history information stored in the history storage area to derive behavioral information corresponding to the results of gameplay over a predetermined period, it becomes possible to grasp the management results of game history, such as the frequency of occurrence of predetermined events.

Feature W11. The gaming machine according to Feature W10, characterized in that the second predetermined storage area includes a mode information storage area (calculation result storage area 234) for storing the mode information derived by the information derivation means.

According to feature W11, when behavioral information corresponding to the results of gameplay over a predetermined period is derived using historical information, that behavioral information is stored in the behavioral information storage area. This makes it possible to grasp the management results of the game history at any time. Furthermore, since a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, it is possible to prevent the information stored in the behavioral information storage area from being overwritten during the execution of the process for controlling the progress of the game.

Furthermore, for the configuration of features W1 to W11, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Features Group X>
Feature X1. Equipped with control means (main CPU 63) for executing various processes,
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 34th embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 34th embodiments),
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
Equipped with,
The gaming machine is characterized in that the second predetermined processing execution means includes an erasure execution means (in the 25th embodiment, a function to execute steps S6103 and S6107 in the main CPU 63; in the 30th embodiment, a function to execute step S7204 in the main CPU 63; in the 31st embodiment, a function to execute step S7508 in the main CPU 63; and in the 32nd embodiment, a function to execute steps S7808 and S7810 in the main CPU 63) which causes the erasure execution means to execute an erasure process for the second predetermined storage area as the second predetermined processing based on the occurrence of an erasure trigger (in the 25th embodiment, a function to execute steps S6103 and S6107 in the main CPU 63; in the 30th embodiment, a function to execute step S7204 in the main CPU 63; in the 31st embodiment, a function to execute step S7508 in the main CPU 63; and in the 32nd embodiment, a function to execute steps S7808 and S7810 in the main CPU 63).

According to feature X1, a first predetermined storage area and a second predetermined storage area are provided. The first predetermined storage area is treated as a dedicated storage area for the first predetermined process, and the second predetermined storage area is treated as a dedicated storage area for the second predetermined process. This makes it possible to clearly differentiate the storage locations of information in the predetermined storage means for the first predetermined process and the second predetermined process. Therefore, it is possible to prevent information used in the other process from being erased when one of the first or second predetermined processes is executed.

Furthermore, when an erasure trigger occurs, the erasure process is executed on the second predetermined memory area. This prevents the second predetermined process from being executed while the information in the second predetermined memory area remains unchanged, even if some abnormality has occurred in the second predetermined memory area. Additionally, since the erasure process is executed by the second predetermined process, the first predetermined process is prevented from intervening in the updating of information in the second predetermined memory area.

Feature X2. The gaming machine according to Feature X1, characterized in that the erasure execution means performs the erasure process on the second predetermined storage area while ensuring that non-erasure target information (management monitoring flag, return address information, various register information) is not erased.

According to feature X2, the information erasure process for the second predetermined storage area is performed in a manner that prevents the erasure of non-erasure target information in that second predetermined storage area. This makes it possible to perform the information erasure process for the second predetermined storage area while preventing the erasure of necessary information.

Feature X3. The second predetermined processing execution means includes a storage execution means (in the 30th embodiment, a function to execute steps S7102 to S7107 in the main CPU 63; in the 31st embodiment, a function to execute steps S7502 to S7507 in the main CPU 63; in the 32nd embodiment, a function to execute steps S7802 to S7807 in the main CPU 63) that is necessary to return to the state of executing the first predetermined processing when the state changes from the state of executing the first predetermined processing to the state of executing the second predetermined processing.
The gaming machine according to feature X2, characterized in that the erasure execution means performs an erasure process on the second predetermined storage area of the information while ensuring that the recovery response information is not erased as non-erasure target information.

According to feature X3, it becomes possible to perform the information erasure process on the second predetermined storage area while ensuring that the recovery response information necessary when returning from the state in which the second predetermined process is being executed to the state in which the first predetermined process is being executed is not erased.

Feature X4. The gaming machine according to Feature X3, characterized in that the memory execution means stores information of the program's return address in the second predetermined memory area as the return-response information when the second predetermined process is completed and the program returns to the first predetermined process.

According to feature X4, the information erasure process is performed on the second predetermined storage area while ensuring that the program's return address information is not erased when returning to the first predetermined processing. Therefore, even if the information erasure process is performed on the second predetermined storage area, it is possible to return to the predetermined program in the first predetermined processing once the second predetermined processing is completed.

Feature X5. The control means is configured to temporarily store information in an internal storage means (registers of the main CPU 63) when executing a process.
The gaming machine according to feature X3 or X4, characterized in that the memory execution means stores the information stored in the internal memory means in the second predetermined memory area as the recovery response information.

According to feature X5, since the information erasure process is performed on the second predetermined storage area while ensuring that the information in the internal storage means used in the first predetermined process is not erased, even if the information erasure process is performed on the second predetermined storage area, it is possible to restore the information used in the first predetermined process to the internal storage means once the second predetermined process is completed.

Feature X6. The game machine according to any one of Feature X1 to X5, characterized in that the erasure execution means performs the erasure process on the second predetermined storage area as an occurrence of the erasure trigger, based on the occurrence of an abnormality in the second predetermined storage area.

According to feature X6, since the information erasure process is performed on the second predetermined storage area based on the occurrence of an abnormality in that area, it is possible to prevent the second predetermined process from being executed while the second predetermined storage area is still in an abnormal state.

Feature X7. The gaming machine according to Feature X6, characterized in that the second predetermined processing execution means includes means for monitoring whether the second predetermined storage area is normal (in the 30th embodiment, a function for executing the processing in steps S7201 to S7203 in the main CPU 63) as the second predetermined processing.

According to feature X7, not only is the information erasure process for the second predetermined storage area performed within the second predetermined processing, but monitoring whether the second predetermined storage area is functioning correctly is also performed within the second predetermined processing without the intervention of the first predetermined processing. Therefore, it becomes possible to perform both the monitoring of whether the second predetermined storage area is functioning correctly and the information erasure process for the second predetermined storage area as a single series of operations within the second predetermined processing.

Feature X8. The first predetermined process includes a process for controlling the progress of the game,
The gaming machine according to any one of features X1 to X7, characterized in that the second predetermined process includes a process for managing the gaming history.

According to feature X8, a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process. This makes it possible to prevent the information used in the process for managing the game history from being overwritten when the process for controlling the progress of the game is executed.

Feature X9. The gaming machine according to Feature X8, characterized in that the second predetermined storage area includes a history storage area (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which history information of the game corresponding to a predetermined event occurring when the game is executed.

According to feature X9, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, since a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten during the execution of the process for controlling the progress of the game.

Feature X10. The gaming machine according to Feature X9, characterized in that the second predetermined processing execution means includes information derivation means (a function that executes the processing in step S4208 in the main CPU 63) that derives pattern information corresponding to the results of the game during a predetermined period using the history information stored in the history storage area.

According to feature X10, by using the history information stored in the history storage area to derive behavioral information corresponding to the results of gameplay over a predetermined period, it becomes possible to grasp the management results of game history, such as the frequency of occurrence of predetermined events.

Feature X11. The gaming machine according to Feature X10, characterized in that the second predetermined storage area includes a mode information storage area (calculation result storage area 234) for storing the mode information derived by the information derivation means.

According to feature X11, when behavioral information corresponding to the results of gameplay over a predetermined period is derived using historical information, that behavioral information is stored in the behavioral information storage area. This makes it possible to grasp the management results of the game history at any time. Furthermore, by executing a process to control the progress of the game as the first predetermined process, and a process to manage the game history as the second predetermined process, it becomes possible to prevent the information stored in the behavioral information storage area from being overwritten during the execution of the process to control the progress of the game.

Furthermore, for the configuration of features X1 to X11, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Characteristics of Group Y>
Feature Y1. Equipped with control means (main CPU 63) for executing various processes,
The control means is,
A first predetermined processing execution means that executes a first predetermined processing among the various processing described above (a function that executes processing other than management execution processing on the main CPU 63 in the 15th to 34th embodiments),
A second predetermined processing execution means for executing a second predetermined processing among the various processing described above (a function for executing management execution processing on the main CPU 63 in the 15th to 34th embodiments),
When the first predetermined process is executed, a first predetermined storage area (work area 221 for specific control, stack area 222 for specific control) where information is stored,
When the second predetermined process is executed, a second predetermined storage area (work area 223 for non-specific control, stack area 224 for non-specific control) where information is stored,
A first calculation means for calculating first reference numerical information corresponding to a plurality of pieces of information stored in the first predetermined storage area (in the 30th embodiment, a function to execute the processing of steps S6604 and S6710 in the main CPU 63; in the 31st embodiment, a function to execute the processing of step S7304 in the main CPU 63; in the 32nd embodiment, a function to execute the processing of steps S7610 and S7701 in the main CPU 63),
A gaming machine characterized by having the following features.

According to feature Y1, a first predetermined storage area and a second predetermined storage area are provided. The first predetermined storage area is treated as a dedicated storage area for the first predetermined process, and the second predetermined storage area is treated as a dedicated storage area for the second predetermined process. This makes it possible to clearly differentiate the storage locations of information in the predetermined storage means for the first predetermined process and the second predetermined process. Therefore, it is possible to prevent information used in the other process from being erased when one of the first predetermined process or the other is executed. In this case, a first reference numerical information corresponding to multiple pieces of information stored in the first predetermined storage area is calculated. By using this first reference numerical information, it is possible to determine whether or not an information anomaly has occurred only in the first predetermined storage area.

Feature Y2. The gaming machine according to Feature Y1, characterized by comprising information erasure means (in the 30th embodiment, a function to execute the process in step S6607 in the main CPU 63; in the 31st embodiment, a function to execute the processes in steps S7401 and S7402 in the main CPU 63; and in the 32nd embodiment, a function to execute the processes in steps S7704 and S7705 in the main CPU 63) that causes the information erasure process to be executed on the first predetermined storage area based on the identification of an anomaly with respect to the first reference numerical information calculated by the first calculation means.

According to feature Y2, if an anomaly is detected regarding the first reference numerical information, an information erasure process is performed on the first predetermined storage area. This prevents the first predetermined process from being executed while the information in the first predetermined storage area remains intact, even though an information anomaly has occurred.

Feature Y3. The first calculation means is,
A first power outage calculation means (in the 30th embodiment, a function that executes the process of step S6710 in the main CPU 63, and in the 32nd embodiment, a function that executes the process of step S7610 in the main CPU 63) that calculates the first reference numerical information when the supply of operating power to the control means is stopped,
A first power-on calculation means (in the 30th embodiment, a function that executes the process in step S6604 in the main CPU 63; in the 31st embodiment, a function that executes the process in step S7304 in the main CPU 63; in the 32nd embodiment, a function that executes the process in step S7701 in the main CPU 63) that calculates the first reference numerical information when the supply of operating power to the control means is started,
Equipped with,
The gaming machine according to feature Y2, wherein the information erasure means is configured such that the information erasure process is performed on at least the first predetermined storage area based on the fact that the first reference numerical information calculated by the first power outage calculation means does not match the first reference numerical information calculated by the first power on calculation means.

According to feature Y3, it is possible to determine whether or not information in the first predetermined storage area is retained after a power supply interruption has occurred by calculating the first reference numerical information. Furthermore, if the information in the first predetermined storage area is not retained after the power supply interruption has occurred, an information erasure process is performed on the first predetermined storage area. This prevents the first predetermined process from being executed while the information in the first predetermined storage area remains intact, even if an information anomaly has occurred.

Feature Y4. The gaming machine according to Feature Y2 or Y3, characterized in that, even if the information erasure means identifies an abnormality with respect to the first reference numerical information calculated by the first calculation means, it does not perform an information erasure process on the second predetermined storage area.

According to feature Y4, when an anomaly is detected in the first reference numerical information, an information erasure process is performed on the first predetermined storage area, while no information erasure process is performed on the second predetermined storage area. This prevents the information in the second predetermined storage area from being erased when an information anomaly occurs in the first predetermined storage area.

Feature Y5. The gaming machine according to any one of Feature Y1 to Y4, characterized in that the first reference numerical information is information that does not change in accordance with the information stored in the second predetermined storage area.

According to feature Y5, in a configuration where a first predetermined storage area and a second predetermined storage area exist, it becomes possible to individually identify information anomalies in the first predetermined storage area using the first reference numerical information.

Feature Y6. A gaming machine according to any one of Feature Y1 to Y5, characterized by comprising a second calculation means (a function that executes the processing in steps S7611 and S7706 in the main CPU 63) for calculating second reference numerical information corresponding to a plurality of pieces of information stored in the second predetermined storage area.

According to feature Y6, a second reference numerical value is calculated that corresponds to multiple pieces of information stored in the second predetermined memory area. By using this second reference numerical value, it becomes possible to determine whether or not an information anomaly has occurred only in the second predetermined memory area.

Feature Y7. The gaming machine according to Feature Y6, characterized in that it includes means (a function that executes the processing in steps S7808 and S7810 in the main CPU 63) for performing an information erasure process on at least the second predetermined storage area based on the identification of an anomaly with respect to the second reference numerical information calculated by the second calculation means.

According to feature Y7, if an anomaly is detected regarding the second reference numerical information, an information erasure process is performed on the second predetermined storage area. This prevents the second predetermined process from being executed while the information in the second predetermined storage area remains intact, even though an information anomaly has occurred.

Feature Y8. The first predetermined process includes a process for controlling the progress of the game,
The gaming machine according to any one of features Y1 to Y7, characterized in that the second predetermined process includes a process for managing the gaming history.

According to feature Y8, a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process. This makes it possible to prevent the information used in the process for managing the game history from being overwritten when the process for controlling the progress of the game is executed.

Feature Y9. The gaming machine according to Feature Y8, characterized in that the second predetermined storage area includes a history storage area (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which history information of the game corresponding to a predetermined event occurring when the game is executed.

According to feature Y9, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store information for managing the number or frequency of occurrences of the predetermined event, and by utilizing this managed information, the frequency of occurrence of the predetermined event can be appropriately managed. Furthermore, because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Additionally, since a process for controlling the progress of the game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten during the execution of the process for controlling the progress of the game.

Feature Y10. The gaming machine according to Feature Y9, characterized in that the second predetermined processing execution means includes information derivation means (a function that executes the processing in step S4208 in the main CPU 63) that derives pattern information corresponding to the results of the game during a predetermined period using the history information stored in the history storage area.

According to feature Y10, by using the history information stored in the history storage area to derive behavioral information corresponding to the results of gameplay over a predetermined period, it becomes possible to grasp the management results of game history, such as the frequency of occurrence of predetermined events.

Feature Y11. The gaming machine according to Feature Y10, characterized in that the second predetermined storage area includes a mode information storage area (calculation result storage area 234) for storing the mode information derived by the information derivation means.

According to feature Y11, when behavioral information corresponding to the results of gameplay over a predetermined period is derived using historical information, that behavioral information is stored in the behavioral information storage area. This makes it possible to grasp the management results of the game history at any time. Furthermore, by executing a process to control the progress of the game as the first predetermined process, and a process to manage the game history as the second predetermined process, it becomes possible to prevent the information stored in the behavioral information storage area from being overwritten during the execution of the process to control the progress of the game.

Furthermore, for the configuration of features Y1 to Y11, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned features T, U, V, W, X, and Y, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front where game balls are stored. These stored balls are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters a ball entry section in the game area, for example, it is dispensed back into the tray storage section from a payout device. Furthermore, some pachinko machines are known to have an upper and lower tray storage section. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like the examples above, various controls need to be implemented effectively, and there is still room for improvement in this regard.

<Features Group Z>
Feature Z1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A means for generating a situation in which the setting value to be used can be changed (a function that executes the processing in steps S7905, S7916, and S7917 in the main CPU 63),
In a situation where the supply of operating power to the control means (main CPU 63) having the setting means has started and the processing at the start of supply has been executed, a setting notification means (a function that executes setting confirmation processing in the main CPU 63) is provided to notify the setting value of the target to be used in a situation where the setting is not possible,
A gaming machine characterized by having the following features.

According to Feature Z1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, the player expects the target setting value to be the most advantageous. In this case, to confirm the target setting value, it is necessary to temporarily stop the power supply to the control means and then restart the power supply to the control means. This makes it difficult to fraudulently check the setting value. Furthermore, since the setting value is notified while the power supply restart process is being executed, there is no need to notify the setting value while the game is interrupted. Therefore, the notification of the setting value can be performed effectively.

Feature Z2. The gaming machine according to Feature Z1, characterized in that the situation generation means causes the configurable situation to occur when the supply start process is being executed.

According to feature Z2, it becomes possible to consolidate the situations in which the setting value to be used can be configured and the situations in which the setting value to be used is notified when it is not possible to configure it, into the situation when the processing at the start of supply is being executed.

Feature Z3. It is equipped with a first identification means for identifying the occurrence of a first trigger event (a function that executes the processing in steps S7912 and S7916 in the main CPU 63),
The gaming machine according to feature Z1 or Z2, characterized in that the setting notification means provides notification of the setting value of the target to be used in a situation where the setting is not possible, based on the situation in which the supply start processing is being executed and the occurrence of the first trigger event has been identified by the first identification means.

According to feature Z3, in order to notify the set value of the target being used, it is necessary not only to start supplying operating power to the control means but also to generate a first trigger event. This makes it difficult to attempt to illegally verify the set value.

Feature Z4. The gaming machine according to Feature Z3, characterized in that the first triggering event is that a predetermined operation is performed on the setting key insertion unit (setting key insertion unit 68a) using a setting key.

According to feature Z4, in order to notify the user of the settings for use, a predetermined operation using the setting key on the setting key insertion part is required. This makes it difficult to attempt to illegally check the setting values.

Feature Z5. The setting notification means is configured to notify the setting value of the target being used in a situation where the setting is not possible, when the notification condition is met based on the situation in which the supply start processing is being executed and the occurrence of the first trigger event has been identified by the first identification means.
The aforementioned situation generation means is configured to enter the configurable state when the setting conditions are met based on the situation in which the supply start processing is being executed and the occurrence of the first trigger event has been identified by the first identification means,
The gaming machine according to feature Z3 or Z4, characterized in that the notification conditions and the setting conditions are different.

According to feature Z5, whether generating a configurable state or notifying the target setting value, it is necessary not only to start supplying operating power to the control means but also to generate a first trigger event. This makes it difficult to fraudulently set the target setting value or to fraudulently verify the target setting value. On the other hand, because the setting conditions for generating a configurable state and the notification conditions for notifying the target setting value are different, it is possible to generate either the configurable state or the notification state independently.

Feature Z6. It is equipped with a second identification means for identifying the occurrence of a second trigger event (a function that executes the processing in step S7905 in the main CPU 63),
The setting conditions are established based on the situation in which the supply start process is being executed, the occurrence of the first trigger event is identified by the first identifying means, and the occurrence of the second trigger event is identified by the second identifying means.
The gaming machine according to feature Z5, characterized in that the notification condition is established based on the situation in which the supply start processing is being executed, the occurrence of the first trigger event has been identified by the first identifying means, and the occurrence of the second trigger event has not been identified by the second identifying means.

According to feature Z6, in order to generate a configurable state, it is necessary not only to start supplying operating power to the control means and generate a first trigger event, but also to generate a second trigger event. This makes it possible to make the operation to generate a configurable state more complex in a configuration where, whether setting the target setting value or notifying the target setting value, it is necessary to start supplying operating power to the control means and generate a first trigger event. Therefore, it becomes possible to more effectively prevent acts that attempt to fraudulently set the target setting value.

Feature Z7. The gaming machine according to Feature Z6, characterized in that the second triggering event is the operation of a predetermined operating means (reset button 68c).

According to feature Z7, generating a configurable state requires not only initiating the supply of operating power to the control means and generating the first trigger event, but also operating a predetermined operating means. This makes it difficult to attempt to fraudulently set the target setting value, while preventing the operation required to legitimately generate a configurable state from becoming excessively complicated.

Feature Z8. The gaming machine according to Feature Z6 or Z7, characterized in that it is equipped with information erasure means (a function that executes the processing in step S7915 in the main CPU 63) that performs information erasure processing based on the situation in which the second trigger event has been identified by the second identification means while the supply start processing is being executed.

According to feature Z8, by utilizing the second trigger event necessary to execute the information erasure process, it becomes possible to differentiate the conditions for generating a configurable state from the conditions for notifying the target setting value when the configurable state is not in effect.

Feature Z9. The gaming machine according to Feature Z8, characterized in that the information erasure means performs the information erasure process even when the configurable situation occurs.

According to feature Z9, it becomes possible to perform an information erasure process when a configurable state is reached.

Feature Z10. The gaming machine according to Feature Z8 or Z9, characterized in that, while the supply start processing is being executed, the occurrence of the second trigger event is identified by the second identification means, but the occurrence of the first trigger event is not identified by the first identification means, the information erasure process is executed by the information erasure means, even though the setting-possible state is not achieved.

According to feature Z10, depending on whether or not a first trigger event occurs when the supply of operating power to the control means is started, it is possible to select between two cases: one where the information erasure process is executed and the system becomes configurable, and another where the information erasure process is executed but the system does not become configurable.

Furthermore, for the configuration of features Z1 to Z10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Features group a>
Feature a1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A means for generating a situation in which the setting value to be used can be changed (a function that executes the processing in steps S7905, S7916, and S7917 in the main CPU 63),
Information erasure means for performing information erasure processing (a function that performs the processing in step S7915 in the main CPU 63),
A setting notification means (a function that executes setting confirmation processing in the main CPU 63) that notifies the setting value of the target to be used when the setting is not possible,
A first identification means for identifying the occurrence of a first trigger event (a function that executes the processing in steps S7912 and S7916 in the main CPU 63),
A second identification means for identifying the occurrence of a second trigger event (a function that executes the processing in step S7905 in the main CPU 63),
Equipped with,
The situation generating means causes the setting-enabled state to occur based on the situation in which the supply of operating power to the control means having the setting means has started and the processing at the start of supply has been executed, the occurrence of the first trigger event has been identified by the first identifying means, and the occurrence of the second trigger event has been identified by the second identifying means.
The information erasure means executes the information erasure process based on the fact that the occurrence of the second trigger event has been identified by the second identification means while the supply start process is being executed.
In a situation where the supply start process is being executed, and the occurrence of the second trigger event is identified by the second identification means, but the occurrence of the first trigger event is not identified by the first identification means, the information erasure process is executed by the information erasure means, even though the configurable situation is not achieved.
The setting notification means is characterized in that, based on the situation in which the supply start processing is being executed, the occurrence of the first trigger event has been identified by the first identification means, but the occurrence of the second trigger event has not been identified by the second identification means, the setting value of the target to be used in a situation in which the setting is not possible is notified.

According to feature a1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, players expect the target setting value to be the most advantageous. Furthermore, the system allows for information erasure, preventing gameplay from continuing even when an information anomaly occurs. Additionally, the system can notify the player of the target setting value, allowing them to verify the setting value.

In this case, in order to confirm the setting value that is set as the target of use, it is necessary to start supplying operating power to the control means and generate the first trigger event. This makes it difficult to attempt to illegally check the setting value.

Furthermore, in order to generate a configurable state, it is necessary not only to start supplying operating power to the control means and generate a first trigger event, but also to generate a second trigger event. This makes it possible to make the operation to generate a configurable state more complex in a configuration where, whether the setting of the target setting value is performed or the target setting value is notified, it is necessary to start supplying operating power to the control means and generate a first trigger event. Therefore, it becomes possible to more effectively prevent acts that attempt to fraudulently set the target setting value.

Furthermore, by utilizing the second trigger event necessary to execute the information erasure process, it becomes possible to differentiate the conditions for generating a configurable state from the conditions for notifying the target setting value when the configurable state is not available.

Furthermore, depending on whether or not the first trigger event occurs when power is supplied to the control means, it is possible to select between two scenarios: one where the information erasure process is executed and the system becomes configurable, and another where the information erasure process is executed but the system does not become configurable.

Feature a2. The gaming machine according to Feature a1, characterized in that the first trigger event is that a predetermined operation is performed on the setting key insertion unit (setting key insertion unit 68a) using a setting key.

According to feature a2, in order to notify the user of the settings for use, a predetermined operation using the setting key on the setting key insertion part is required. This makes it difficult to attempt to illegally check the setting values.

Feature a3. The gaming machine according to feature a1 or a2, characterized in that the second triggering event is the operation of a predetermined operating means (reset button 68c).

According to feature a3, generating a configurable state requires not only initiating the supply of operating power to the control means and generating the first trigger event, but also operating a predetermined operating means. This makes it difficult to attempt to fraudulently set the target setting value, while preventing the operation required to legitimately generate a configurable state from becoming excessively complicated.

Furthermore, for the configuration of features a1 to a3, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned features Z and features a, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front where game balls are stored. These stored balls are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters a ball entry section in the game area, for example, it is dispensed back into the tray storage section from a payout device. Furthermore, some pachinko machines are known to have an upper and lower tray storage section. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like the examples above, a configuration is required that allows for the appropriate verification of the setting values that determine the advantage of the gaming machine, and there is still room for improvement in this regard.

<Features group b>
Feature b1. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A means for generating a situation in which the setting value to be used can be changed (a function that executes the processing in steps S7905, S7916, and S7917 in the main CPU 63),
A setting monitoring means (a function that executes the process in step S8220 in the main CPU 63) that performs a setting monitoring process to monitor whether the setting value of the target being used is abnormal,
Equipped with,
A gaming machine characterized in that the setting monitoring process is not included in the processing performed when the supply of operating power to the control means having the setting means is started.

According to feature b1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, players expect the target setting value to be the most advantageous. Furthermore, a setting monitoring process is executed to check whether the target setting value is abnormal, allowing for corrective action if an abnormal setting value is detected. Additionally, since the setting monitoring process is not included in the initial supply processing, the above-mentioned excellent effects can be achieved without increasing the processing load during the initial supply processing.

Feature b2. The gaming machine according to feature b1, characterized in that the situation generation means generates the configurable situation while the supply start process is being executed.

According to feature b2, since the configurable state occurs while the supply start processing is being executed, it becomes possible to set the target setting value before the game starts. In this case, since the target setting value is set during the supply start processing, the processing load of the supply start processing increases accordingly. In contrast, with the configuration of feature b1 described above, since the supply start processing does not include setting monitoring processing, it becomes possible to monitor whether the target setting value is abnormal without further increasing the processing load of the supply start processing.

Feature b3. The gaming machine according to feature b1 or b2, characterized in that the setting monitoring means executes the setting monitoring process after the processing at the start of supply is completed.

According to feature b3, since the setting monitoring process is executed after the initial supply startup process is completed, it becomes possible to monitor whether the setting values of the target system are abnormal without increasing the processing load of the initial supply startup process.

Feature b4. The gaming machine according to feature b3, characterized in that the setting monitoring means executes the setting monitoring process each time a monitoring trigger occurs after the processing at the start of supply is completed.

According to feature b4, since the setting monitoring process is executed every time a monitoring trigger occurs after the initial supply start-up process is completed, it becomes easier to identify when the setting value of the target system is abnormal.

Feature b5. It is equipped with means for executing interrupt processing that is activated periodically (a function for executing the first timer interrupt processing in the main CPU 63),
The gaming machine according to any one of features b1 to b4, characterized in that the interrupt processing includes the setting monitoring processing.

According to feature b5, since the configuration monitoring process is executed each time the system is started periodically, it becomes possible to increase the frequency of monitoring whether the configuration values being used are abnormal.

Feature b6. The gaming machine according to any one of features b1 to b5, characterized in that the setting monitoring means includes means for restricting the progress of the game based on the setting monitoring process identifying that the setting value of the target being used is abnormal (a function that executes the processing in steps S8207 and S8302 in the main CPU 63).

According to feature b6, if the system detects that the setting value of the target is abnormal, the game's progress will be restricted. Therefore, it is possible to prevent the game from continuing even when the setting value of the target is abnormal.

Feature b7. The gaming machine according to any one of features b1 to b6, characterized in that the setting monitoring means includes means (a function that executes the processing in step S8303 in the main CPU 63) for executing a notification that allows the player to recognize that the setting-enabled state should be created, based on the identification of an abnormal setting value of the target being used in the setting monitoring process.

According to feature b7, if an abnormal setting value for the target system is identified, a notification is issued to the player informing them that the system should be made configurable. Therefore, if the setting value for the target system becomes abnormal, it is possible to prompt the administrator of the gaming hall to correct it.

Furthermore, for the configuration of features b1 to b7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned feature group b, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front where game balls are stored. These stored balls are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters a ball entry section in the game area, for example, it is dispensed back into the tray storage section from a payout device. Furthermore, some pachinko machines are known to have an upper and lower tray storage section. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like those exemplified above, it is necessary to appropriately manage the setting values that determine the advantage of the gaming machine, and there is still room for improvement in this regard.

<Features group c>
Feature c1. A predetermined display means (first to fourth notification display devices 201 to 204),
A predetermined display control means for controlling the display of the predetermined display means (a function that executes a second timer interrupt process in the main CPU 63),
Equipped with,
The game machine is characterized in that the predetermined display control means includes a check control means (in the 35th embodiment, a function to execute the process in step S9102 in the main CPU 63, and in the 38th embodiment, a function to execute the process in step S9602 in the main CPU 63) which causes the predetermined display control means to perform a check display that allows confirmation of whether the predetermined display means is normal or not based on the occurrence of a check trigger.

According to feature c1, a check indicator is displayed by a predetermined display means based on the occurrence of a check trigger. This makes it possible to confirm whether the predetermined display means is functioning correctly or not.

Feature c2. The predetermined display means has a plurality of light-emitting parts (display segments 321 to 324),
The gaming machine according to feature c1, characterized in that the check display is a display that allows confirmation that each of the multiple light-emitting parts can be illuminated.

According to feature c2, each of the multiple light-emitting parts of the predetermined display means illuminates as a check indicator. This makes it possible to verify whether each of the multiple light-emitting parts of the predetermined display means illuminates or not.

Feature c3. The gaming machine according to feature c1 or c2, characterized in that the check trigger occurs when the supply of operating power is started.

According to feature c3, a check indicator is displayed when the power supply for operation begins, making it possible to quickly confirm whether the designated display means is functioning correctly.

Feature c4. The gaming machine according to any one of features c1 to c3, characterized in that the check trigger occurs each time the supply of operating power is started.

According to feature c4, it becomes possible to check whether the predetermined display means is functioning correctly each time the power supply for operation is initiated.

Feature c5. The gaming machine according to any one of features c1 to c4, characterized in that the check trigger occurs without requiring any operation to generate the check trigger when the supply of operating power is started.

According to feature c5, when the power supply for operation is started, a check indicator is displayed without requiring any special operation, making it easy to confirm whether the designated indicator means is functioning correctly.

Feature c6. The gaming machine according to any one of features c1 to c5, characterized in that the check control means causes the predetermined display means to display the check when the supply of operating power is started and the check trigger has occurred, and does not cause the predetermined display means to display the check when the supply of operating power is started and the check trigger has not occurred.

According to feature c6, a check display is shown when the power supply for operation begins and a check trigger occurs, making it possible to confirm whether the predetermined display means is functioning correctly before gameplay begins on the gaming machine. On the other hand, even if the power supply for operation begins, if no check trigger occurs, the check display is not shown, thus preventing the check display from being shown in situations where it is unnecessary.

Feature c7. The system includes means for storing information in a usage-corresponding storage means (management start flag) based on whether the gaming machine has been used in a predetermined manner (a function that executes the processing in step S8606 in the main CPU 63),
The game machine according to feature c6, characterized in that the check control means causes the predetermined display means to display the check when the supply of operating power is started and the information stored in the usage-compatible storage means does not correspond to the usage-compatible information, and does not cause the predetermined display means to display the check when the supply of operating power is started and the information stored in the usage-compatible storage means corresponds to the usage-compatible information, and does not cause the predetermined display means to display the check when the supply of operating power is started and the information stored in the usage-compatible storage means does not correspond to the check

According to feature c7, until the gaming machine is used in a predetermined manner, a check indicator is displayed on the predetermined display means when the supply of operating power begins. However, even if the supply of operating power begins based on the gaming machine being used in a predetermined manner, the check indicator is not displayed on the predetermined display means. This allows, for example, at the stage of the gaming machine's shipment, a check indicator is displayed on the predetermined display means when the supply of operating power begins, enabling verification of whether the predetermined display means is functioning correctly. After the gaming machine is installed in a gaming hall, the check indicator is not displayed on the predetermined display means even if the supply of operating power begins.

Feature c8. The check control means is
A display termination means that terminates the check display in the predetermined display means based on the occurrence of a termination trigger (a function that executes the processing in step S9002 in the main CPU 63 and a function that makes a negative determination in step S9101),
Even if the aforementioned termination trigger has not occurred, a cancellation means (a function in the main CPU 63 to execute the process in step S9203 and a function to make a negative determination in step S9101, a function in the main CPU 63 to execute the process in step S9308 and a function to make a negative determination in step S9101) terminates the check display in the predetermined display means based on the occurrence of a cancellation trigger,
A gaming machine according to any one of features c1 to c7, characterized by having the following features.

According to feature c8, the check display is terminated based on the occurrence of a cancellation trigger, even if the termination trigger for the check display has not occurred. Therefore, even when the check display is being performed by the predetermined display means, it is possible to terminate the check display midway and perform another display.

Feature c9. The gaming machine according to feature c8, characterized in that the cancellation trigger occurs based on the operation of a predetermined operating means (reset button 68c).

According to feature c9, since a cancellation trigger is generated based on the operation of a predetermined operating means, it becomes possible to terminate the check display at any desired timing.

Feature c10. The predetermined display control means includes a separate display control means (a function that executes the processing of steps S9004 and S9006 in the main CPU 63) that causes a different display from the check display to be displayed when a different display execution status occurs.
The gaming machine according to feature c8 or c9, characterized in that the cancellation trigger occurs based on the execution status of the separate display described above.

According to feature c10, the check display terminates when a cancellation trigger occurs based on the status of the alternative display execution, making it possible to prioritize the alternative display over the check display.

Feature c11. The gaming machine according to any one of features c1 to c10, characterized by having means for waiting for the processing to proceed when the check display is being executed on the predetermined display means (a function for executing the processing in step S9406 in the main CPU 63).

According to feature c11, since a check display is shown by a predetermined display means while processing is in a waiting state, it is possible to perform the check display while suppressing an increase in processing load.

Feature c12. The game machine according to any one of features c1 to c11, characterized in that the check control means starts the check display on the predetermined display means before the process for controlling the progress of the game is executed when the supply of operating power is started.

According to feature c12, once the power supply for operation is initiated, it becomes possible to verify whether the predetermined display means is functioning correctly before gameplay begins on the gaming machine.

Feature c13. Setting means for setting a target setting value from among multiple setting values corresponding to the player's advantage (a function that executes setting value update processing in the main CPU 63),
Means for executing processing at the start of power supply based on the commencement of power supply (in the 35th embodiment, a function that executes the processing in steps S8801 to S8819 in the main CPU 63; in the 36th embodiment, a function that executes the processing in steps S9401 to S9420 in the main CPU 63),
Equipped with,
The configuration allows predetermined setting-related processing (setting confirmation processing, setting value update processing) to be executed when the processing for starting the supply of the operating power is being performed,
The gaming machine according to feature c12, characterized in that the check control means starts the check display on the predetermined display means while the process for starting the supply of operating power is being executed.

According to feature c13, the system is configured so that the target setting value is selected from multiple levels of setting values corresponding to the player's advantage. Therefore, the player expects the target setting value to be more advantageous. Furthermore, predetermined setting-related processing can be executed while the power supply start process is running. This makes it possible to execute setting-related processing before the game starts. In this case, a check display is initiated by a predetermined display means while the power supply start process is running. This makes it possible to consolidate the processing for initiating the check display by the predetermined display means, as well as the predetermined setting-related processing, into the power supply start process.

Feature c14. The gaming machine according to feature c13, characterized in that the check control means includes means for initiating the check display on the predetermined display means before the timing when the predetermined setting-related processing can be executed (in the 35th embodiment, a function to execute the processing in steps S8804 and S8805 in the main CPU 63; in the 36th embodiment, a function to execute the processing in steps S9404 and S9405 in the main CPU 63).

According to feature c14, it becomes possible to verify whether the predetermined display means is functioning correctly before the predetermined setting-related processing is executed.

Feature c15. The gaming machine according to feature c13 or c14, characterized in that the predetermined display control means includes means for causing the current setting value to be displayed on the predetermined display means when the predetermined setting-related processing is executed (a function for executing the processing in steps S9004 and S9006 in the main CPU 63).

According to feature c15, when a predetermined setting-related process is executed, the current setting value is displayed on the predetermined display means. Therefore, the administrator of the gaming hall can understand the current setting value by checking the predetermined display means. In this case, with the configuration of feature c13 described above, the process at the start of power supply includes not only the predetermined setting-related process but also the process for starting the check display on the predetermined display means. Therefore, the tasks of checking the predetermined display means to determine whether it is functioning correctly and checking the predetermined display means to understand the current setting value can be performed together while the power supply start process is running.

Furthermore, when the configuration of feature c14 described above is implemented, the check display is initiated by the predetermined display means before the current setting value is displayed by the predetermined display means. Therefore, after confirming whether the predetermined display means is functioning correctly, it becomes possible to use the predetermined display means to confirm the current setting value. This enables accurate confirmation of the setting value.

Feature c16. The check control means is
A means for starting the check display in the predetermined display means before the timing when the predetermined setting-related processing can be executed (a function that executes the processing in steps S8804 and S8805 in the main CPU 63),
Means for terminating the check display based on the occurrence of a cancellation trigger in the predetermined setting-related processing while the check display is being performed (a function in the main CPU 63 to execute the process in step S9203 and a function to make a negative determination in step S9101, a function in the main CPU 63 to execute the process in step S9308 and a function to make a negative determination in step S9101),
The gaming machine described in feature c15, characterized by having the following features.

According to feature c16, the check display is initiated by the predetermined display means before the current setting value is displayed by the predetermined display means. Therefore, after confirming whether the predetermined display means is functioning correctly, it becomes possible to use the predetermined display means to confirm the current setting value. This enables accurate confirmation of the setting value. Furthermore, the check display is terminated when a predetermined setting-related process is executed and a cancellation trigger occurs while the check display is running. This means that when a predetermined setting-related process is executed, the check display can be terminated without waiting for it to end, and the current setting value can be displayed by the predetermined display means. Therefore, confirmation of the current setting value can be performed earlier.

Feature c17. The gaming machine according to feature c16, characterized in that the cancellation trigger occurs based on the operation of a predetermined operating means (reset button 68c).

According to feature c17, since a cancellation trigger is generated based on the operation of a predetermined operating means, it becomes possible to terminate the check display at any desired timing.

Feature c18. A gaming machine according to any one of features c13 to c17, characterized by having means for executing a process to create a configurable state in which the setting value to be used can be changed, as the predetermined setting-related processing (in the 35th embodiment, a function to make a positive determination in steps S8806, S8817, and S8818 of the main CPU 63; in the 36th embodiment, a function to make a positive determination in steps S9407, S9418, and S9419 of the main CPU 63).

According to feature c18, the process for initiating the supply of operating power can consolidate not only the process for setting the target setting value but also the process for initiating a check display using a predetermined display means.

Feature c19. The setting means updates the setting value to be used based on the operation of a predetermined operating means (reset button 68c) in the setting-enabled state.
The aforementioned check control means is
A means for starting the check display in the predetermined display means before the setting becomes possible (a function that executes the processing of steps S8804 and S8805 in the main CPU 63),
Means for terminating the check display when the check display is being displayed and the predetermined operating means is operated in the configurable state (a function in the main CPU 63 to execute the process in step S9203 and a function to make a negative determination in step S9101, a function in the main CPU 63 to execute the process in step S9308 and a function to make a negative determination in step S9101),
Equipped with,
The gaming machine according to feature c18, wherein the predetermined display control means includes means for causing the current setting value to be displayed on the predetermined display means after the check display has been completed in the setting-possible state (a function for executing the processing of steps S9004 and S9006 in the main CPU 63).

According to feature c19, the check display is initiated by the predetermined display means before the current setting value is displayed by the predetermined display means. Therefore, after confirming whether the predetermined display means is functioning correctly, it becomes possible to use the predetermined display means to confirm the current setting value. This enables accurate confirmation of the setting value. Furthermore, when the setting becomes ready and the predetermined operation means is operated while the check display is running, the check display ends and the current setting value is displayed. This means that when the setting becomes ready, the check display can be terminated and the current setting value displayed by the predetermined display means without waiting for the check display to end. Therefore, confirmation of the current setting value can be performed earlier.

Furthermore, in a configuration where the setting value to be used is updated based on the operation of a predetermined operating means while the setting is configurable, the check display ends and the current setting value is displayed based on the operation of the predetermined operating means while the setting is configurable. Therefore, a dedicated operation to end the check display and display the current setting value is not required. Thus, the work efficiency of updating the setting value to be used can be improved.

Feature c20. The gaming machine according to any one of features c13 to c19, characterized in that it includes means for performing a process to display the current setting value on the predetermined display means (a function for performing setting confirmation processing in the main CPU 63).

According to feature c20, the process for initiating the supply of operating power can be consolidated to include not only the process for confirming the current setting value, but also the process for initiating a check display using a predetermined display means.

Feature c21. The gaming machine according to any one of features c1 to c20, characterized in that the predetermined display control means includes means for causing the predetermined display means to display information corresponding to the management results of the game history (a function for executing the processing in steps S8708, S8709, and S9107 in the main CPU 63).

According to feature c21, it becomes possible to notify the administrator of the gaming hall of the results of the gaming history management. In this case, by providing the configuration of feature c1 above and having a check display on a predetermined display means, it becomes possible to confirm whether the information corresponding to the gaming history management results on the predetermined display means is being displayed accurately.

Furthermore, for the configuration of features c1 to c21, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Feature group d>
Feature d1. A predetermined display means (first to fourth notification display devices 201 to 204),
A predetermined display control means for controlling the display of the predetermined display means (a function that executes a second timer interrupt process in the main CPU 63),
Equipped with,
The game machine is characterized in that the predetermined display control means includes a check control means (in the 35th embodiment, a function to execute the process in step S9102 in the main CPU 63, and in the 38th embodiment, a function to execute the process in step S9602 in the main CPU 63) that causes the predetermined display control means to perform a check display so as to be able to confirm whether the predetermined display means is normal or not when the supply of operating power is started and before the process for controlling the progress of the game is executed.

According to feature d1, the check display is performed by the predetermined display means, making it possible to confirm whether the predetermined display means is functioning correctly. Furthermore, since the check display is initiated before the processing to control the game's progress is executed when the power supply is started, it is possible to confirm whether the predetermined display means is functioning correctly before the game is played on the gaming machine when the power supply is started.

Feature d2. A setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
Means for executing processing at the start of power supply based on the commencement of power supply (in the 35th embodiment, a function that executes the processing in steps S8801 to S8819 in the main CPU 63; in the 36th embodiment, a function that executes the processing in steps S9401 to S9420 in the main CPU 63),
Equipped with,
The configuration allows predetermined setting-related processing (setting confirmation processing, setting value update processing) to be executed when the processing for starting the supply of the operating power is being performed,
The gaming machine according to feature d1, characterized in that the check control means starts the check display on the predetermined display means while the process for starting the supply of operating power is being executed.

According to feature d2, the system is configured so that the target setting value is selected from multiple levels of settings corresponding to the player's advantage. Therefore, the player expects the target setting value to be more advantageous. Furthermore, predetermined setting-related processing can be executed while the power supply start process is running. This makes it possible to execute setting-related processing before the game starts. In this case, a check display is initiated on a predetermined display means while the power supply start process is running. This makes it possible to consolidate the processing for initiating the check display on the predetermined display means, as well as the predetermined setting-related processing, into the power supply start process.

Feature d3. The gaming machine according to feature d2, characterized in that the check control means includes means for starting the check display on the predetermined display means before the timing when the predetermined setting-related processing can be executed (in the 35th embodiment, a function to execute the processing in steps S8804 and S8805 in the main CPU 63; in the 36th embodiment, a function to execute the processing in steps S9404 and S9405 in the main CPU 63).

According to feature d3, it becomes possible to verify whether the predetermined display means is functioning correctly before the predetermined setting-related processing is executed.

Feature d4. The gaming machine according to feature d2 or d3, characterized in that the predetermined display control means includes means for causing the current setting value to be displayed on the predetermined display means when the predetermined setting-related processing is executed (a function for executing the processing in steps S9004 and S9006 in the main CPU 63).

According to feature d4, when a predetermined setting-related process is executed, the current setting value is displayed on the predetermined display means. Therefore, the administrator of the gaming hall can understand the current setting value by checking the predetermined display means. In this case, with the configuration of feature d2 described above, the process at the start of power supply includes not only the predetermined setting-related process but also the process for starting the check display on the predetermined display means. Therefore, the tasks of checking the predetermined display means to determine whether it is functioning correctly and checking the predetermined display means to understand the current setting value can be performed together while the power supply start process is running.

Furthermore, when the configuration of feature d3 described above is implemented, the check display is initiated by the predetermined display means before the current setting value is displayed by the predetermined display means. Therefore, after confirming whether the predetermined display means is functioning correctly, it becomes possible to use the predetermined display means to confirm the current setting value. This enables accurate confirmation of the setting value.

Feature d5. The check control means is
A means for starting the check display in the predetermined display means before the timing when the predetermined setting-related processing can be executed (a function that executes the processing in steps S8804 and S8805 in the main CPU 63),
Means for terminating the check display based on the occurrence of a cancellation trigger in the predetermined setting-related processing while the check display is being performed (a function in the main CPU 63 to execute the process in step S9203 and a function to make a negative determination in step S9101, a function in the main CPU 63 to execute the process in step S9308 and a function to make a negative determination in step S9101),
The gaming machine described in feature d4, which is characterized by having the following features.

According to feature d5, the check display is initiated on the predetermined display means before the current setting value is displayed on the predetermined display means. Therefore, after confirming whether the predetermined display means is functioning correctly, it becomes possible to use the predetermined display means to confirm the current setting value. This enables accurate confirmation of the setting value. Furthermore, the check display is terminated when a predetermined setting-related process is executed and a cancellation trigger occurs while the check display is running. This means that when the predetermined setting-related process is executed, the check display can be terminated without waiting for it to end, and the current setting value can be displayed on the predetermined display means. Therefore, confirmation of the current setting value can be performed earlier.

Feature d6. The gaming machine according to feature d5, characterized in that the cancellation trigger occurs based on the operation of a predetermined operating means (reset button 68c).

According to feature d6, since a cancellation trigger is generated based on the operation of a predetermined operating means, it becomes possible to terminate the check display at any desired timing.

Feature d7. A gaming machine according to any one of features d2 to d6, characterized in that it includes means for executing a process to create a configurable state in which the setting value to be used can be changed, as the predetermined setting-related processing (in the 35th embodiment, a function to make a positive determination in steps S8806, S8817, and S8818 of the main CPU 63; in the 36th embodiment, a function to make a positive determination in steps S9407, S9418, and S9419 of the main CPU 63).

According to feature d7, the process for initiating the supply of operating power can be consolidated to include not only the process for setting the target setting value but also the process for initiating a check display using a predetermined display means.

Feature d8. The setting means updates the setting value to be used based on the operation of a predetermined operating means (reset button 68c) in the setting-enabled state.
The aforementioned check control means is
A means for starting the check display in the predetermined display means before the setting becomes possible (a function that executes the processing of steps S8804 and S8805 in the main CPU 63),
Means for terminating the check display when the check display is being displayed and the predetermined operating means is operated in the configurable state (a function in the main CPU 63 to execute the process in step S9203 and a function to make a negative determination in step S9101, a function in the main CPU 63 to execute the process in step S9308 and a function to make a negative determination in step S9101),
Equipped with,
The gaming machine according to feature d7, wherein the predetermined display control means includes means for causing the current setting value to be displayed on the predetermined display means after the check display has been terminated in the setting-possible state (a function that executes the processing of steps S9004 and S9006 in the main CPU 63).

According to feature d8, the check display is initiated by the predetermined display means before the current setting value is displayed by the predetermined display means. Therefore, after confirming whether the predetermined display means is functioning correctly, it becomes possible to use the predetermined display means to confirm the current setting value. This enables accurate confirmation of the setting value. Furthermore, when the setting becomes ready and the predetermined operation means is operated while the check display is running, the check display ends and the current setting value is displayed. This means that when the setting becomes ready, the check display can be terminated and the current setting value displayed by the predetermined display means without waiting for the check display to end. Therefore, confirmation of the current setting value can be performed earlier.

Furthermore, in a configuration where the setting value to be used is updated based on the operation of a predetermined operating means while the setting is configurable, the check display ends and the current setting value is displayed based on the operation of the predetermined operating means while the setting is configurable. Therefore, a dedicated operation to end the check display and display the current setting value is not required. Thus, the work efficiency of updating the setting value to be used can be improved.

Feature d9. The gaming machine according to any one of features d2 to d8, characterized in that it includes means for performing a process to display the current setting value on the predetermined display means as a predetermined setting-related process (a function for performing setting confirmation processing in the main CPU 63).

According to feature d9, the process for initiating the supply of operating power can be consolidated to include not only the process for confirming the current setting value, but also the process for initiating a check display using a predetermined display means.

Feature d10. The gaming machine according to any one of features d1 to d9, characterized in that the predetermined display control means includes means for causing the predetermined display means to display information corresponding to the management results of the game history (a function for executing the processing in steps S8708, S8709, and S9107 in the main CPU 63).

According to feature d10, it becomes possible to notify the gaming hall manager of the results of the gaming history management. In this case, by providing the configuration of feature d1 and having a check display on a predetermined display means, it becomes possible to confirm whether the information corresponding to the gaming history management results on the predetermined display means is being displayed accurately.

Furthermore, for the configuration of features d1 to d10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

According to the inventions relating to the above-mentioned features c and d, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front where game balls are stored. These stored balls are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters a ball entry section in the game area, for example, it is dispensed back into the tray storage section from a payout device. Furthermore, some pachinko machines are known to have an upper and lower tray storage section. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like those exemplified above, a configuration is required that allows for verification of whether the display on the designated display means is being performed accurately, and there is still room for improvement in this regard.

<Features e>
Feature e1. A history storage execution means (a function that executes normal ball entry management processing in the main CPU 63) that stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (normal counter area 231),
Information derivation means (a function that executes the processing in step S8601 in the main CPU 63) that derives mode information (base value) corresponding to the result of the game using the history information stored in the history storage means,
A configuration information storage means (calculation result storage area 234) that stores the configuration information derived by the said information derivation means,
Equipped with,
The amusement machine is characterized in that the mode information storage means is capable of storing a plurality of mode information derived at different timings by the information derivation means.

According to feature e1, when a predetermined event occurs, corresponding history information is stored in the history storage means. Because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Furthermore, using the history information stored in the history storage means, behavioral information corresponding to the game result is derived, and this derived behavioral information is stored in the behavioral information storage means. This allows the gaming machine to store information for managing the number or frequency of occurrences of predetermined events, and by utilizing this managed information, the frequency of occurrence of predetermined events can be appropriately managed. Additionally, the behavioral information storage means can store multiple pieces of behavioral information derived at different timings. This makes it possible to grasp the frequency of occurrence of predetermined events over multiple periods, thus enabling accurate determination of the frequency of occurrence of predetermined events.

Feature e2. The aspect information storage means is
The most recent memory area (current area 311) stores the most recent aspect information derived by the information derivation means,
The gaming machine according to feature e1, further comprising: a past memory area (first to third history areas 312 to 314) that stores the manner information derived by the information derivation means prior to the manner information stored in the most recent memory area.

According to feature e2, since both the most recent behavioral information and the previously derived past behavioral information are stored, it becomes possible to grasp not only the frequency of occurrence of a given event but also its past occurrences.

Feature e3. A period elapsed determination means that determines when a predetermined period has elapsed from the occurrence of a period start trigger until the occurrence of a period end trigger (a function that executes the processing in steps S8605 and S8613 in the main CPU 63),
In a situation where the expiration of the period has not been determined by the period elapsed identification means, the most recent storage execution means (a function that executes the processing of step S8602 in the main CPU 63) stores the manner information derived by the information derivation means in the most recent storage area,
Based on the determination that the predetermined period has elapsed by the period elapsed determination means, the past storage execution means (a function that executes the processing of steps S8607 and S8614 in the main CPU 63) stores in the past storage area period corresponding to the form information corresponding to the result of the game during the predetermined period, which is derived by the information derivation means using the history information stored in the history storage means.
The gaming machine described in feature e2, characterized by having the following features.

According to feature e3, the behavioral information derived before a predetermined period has elapsed is stored in the most recent memory area, while the behavioral information derived after a predetermined period has elapsed is stored in the past memory area. This makes it possible to grasp the most recent frequency of a predetermined event, as well as the past frequency of a predetermined event over a predetermined period. Furthermore, since the past memory area stores behavioral information over a predetermined period, it is possible to reduce the amount of behavioral information stored in the past memory area.

Feature e4. The gaming machine according to feature e3, characterized in that it includes means for erasing the history information stored in the history storage means (a function that executes the processing in steps S8608 and S8615 in the main CPU 63) based on the determination that the predetermined period has elapsed by the period elapsed determination means.

According to feature e4, since the history information in the history information storage means is erased after a predetermined period has elapsed, the required storage capacity in the history information storage means can be reduced. Furthermore, even though the history information is erased after a predetermined period, the behavioral information derived using the history information during that period is stored in the past memory area, making it possible to later determine the frequency of occurrence of a predetermined event during that period.

Feature e5. The gaming machine according to any one of features e2 to e4, characterized in that the past memory area can store multiple sets of the aforementioned configuration information with different derived timings.

According to feature e5, since multiple types of information are stored in the past memory area, it becomes possible to compare the occurrence frequency of predetermined events corresponding to multiple time periods.

Feature e6. A period elapsed determination means that determines when a predetermined period has elapsed from the occurrence of a predetermined period start trigger until the occurrence of a predetermined period end trigger (a function that executes the processing in steps S8605 and S8613 in the main CPU 63),
Based on the determination that the predetermined period has elapsed by the period elapsed determination means, a past storage execution means (a function that executes the processing of steps S8607 and S8614 in the main CPU 63) causes the period-corresponding pattern information corresponding to the results of the game during the predetermined period, derived by the information derivation means using the history information stored in the history storage means, to store the pattern information storage means,
Equipped with,
The gaming machine according to any one of features e1 to e5, characterized in that the manner information storage means is capable of storing a plurality of manner information corresponding to different predetermined periods.

According to feature e6, since multiple past pattern information derived in units of a predetermined period is stored, it becomes possible to compare the occurrence frequency of predetermined events corresponding to multiple periods while keeping the number of pattern information stored in the pattern information storage means low.

Feature e7. The gaming machine according to feature e6, characterized in that it includes means for erasing the history information stored in the history storage means (a function that executes the processing in steps S8608 and S8615 in the main CPU 63) based on the determination that the predetermined period has elapsed by the period elapsed determination means.

According to feature e7, since the history information in the history information storage means is erased after a predetermined period has elapsed, the required storage capacity in the history information storage means can be reduced. Furthermore, even though the history information is erased after a predetermined period, the behavioral information derived using the history information during that period is stored in the past memory area, making it possible to later determine the frequency of occurrence of a predetermined event during that period.

Feature e8. The gaming machine according to any one of features e1 to e7, characterized in that it includes means for controlling the notification means (first to fourth notification display devices 201 to 204) so that notifications corresponding to each of the multiple pieces of information stored in the manner information storage means are executed sequentially (a function that executes the processing of steps S8702 to S8709 in the main CPU 63).

According to feature e8, notification corresponding to the behavioral information is provided by the notification means. This makes it possible to grasp the frequency of occurrence of a predetermined event. Furthermore, since notifications corresponding to each of the multiple behavioral information items are executed sequentially, it is possible to individually grasp the frequency of occurrence of a predetermined event over multiple periods while keeping the number of notification means to a minimum.

Feature e9. The manner information storage means comprises a first storage area (first history area 312) capable of storing the manner information, and a second storage area (second history area 313) capable of storing the manner information.
The gaming machine is characterized in that, when an information shift trigger occurs, it is provided with means for shifting the mode information stored in the first storage area to the second storage area by an instruction including at least an LDIR instruction (a function that executes the processing of steps S8607 and S8614 in the main CPU 63), as described in any one of features e1 to e8.

According to feature e9, a simple processing configuration makes it possible to shift information between memory areas.

Furthermore, for the configuration of features e1 to e9, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned feature group e, the following problems can be solved.

Pachinko machines and slot machines are well-known examples of gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, the game ball is dispensed back into the tray storage section from a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In the case of gaming machines like those exemplified above, proper management of the gaming machines is necessary, and there is still room for improvement in this regard.

<Features f group>
Feature f1. Means for executing processing at the start of power supply based on the commencement of power supply (in the 35th embodiment, a function that executes the processing in steps S8801 to S8819 in the main CPU 63; in the 36th embodiment, a function that executes the processing in steps S9401 to S9420 in the main CPU 63),
A power outage monitoring means (a function that executes the process in step S8901 in the main CPU 63) is provided to enable the execution of a power outage monitoring process for monitoring the occurrence of a power outage while the process for starting the supply of the operating power is being executed,
A gaming machine characterized by having the following features.

According to feature f1, power outage monitoring is performed even when the power supply startup process is running. Therefore, if a power outage occurs while the power supply startup process is running, it becomes possible to deal with it appropriately.

Feature f2. It is equipped with means for executing interrupt processing that is activated periodically (a function for executing the first timer interrupt processing in the main CPU 63),
The interrupt processing includes the power outage monitoring process,
The gaming machine according to feature f1, characterized in that the interrupt process can be interrupted and started while the process for starting the supply of operating power is being executed.

According to feature f2, even while the power supply startup process is running, the interrupt handler is periodically interrupted and activated. Therefore, even while the power supply startup process is running, it becomes possible to periodically monitor for power outages.

Feature f3. The gaming machine according to feature f2, characterized in that the interrupt processing can be initiated by interrupting even when the post-processing (steps S8822 to S8825 in the main CPU 63) is being executed after the processing for starting the supply of operating power has been completed.

According to feature f3, by utilizing an interrupt process that can be activated while post-completion processing is being executed, it becomes possible to periodically monitor for power outages while the power supply start-up process is being executed.

Feature f4. The interrupt processing includes progress-responding processing (steps S8907 to S8920 in the main CPU 63) that is performed to control the progress of the game.
If the interrupt process is triggered while the process for starting the supply of operating power is being executed, the power outage monitoring process will be executed, but the progress response process will not be executed.
The gaming machine according to feature f3, characterized in that if the interrupt process is interrupted and started while the aforementioned termination process is being executed, both the power outage monitoring process and the progress response process may be executed.

According to feature f4, in a configuration where an interrupt process that can be activated while post-completion processing is being executed is used to periodically monitor for power outages while the power supply start process is being executed, it becomes possible to prevent the game progress control processing from being executed even if the interrupt process is activated while the power supply start process is being executed.

Feature f5. Equipped with a setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage.
The gaming machine according to any one of features f1 to f4, characterized in that, while the process for starting the supply of the operating power is being executed, a configurable state may be reached in which the setting value to be used can be changed.

According to feature f5, the power outage monitoring process is executed even when the target settings are being configured. Therefore, even if a power outage occurs while the target settings are being configured, it is possible to deal with it appropriately.

Feature f6. The gaming machine according to feature f5, characterized in that, if the power supply is stopped after a power outage is identified by the power outage monitoring process, it is possible to continue playing the game using the settings that were set for use before the power supply was stopped, once the power supply is restored.

According to feature f6, even if a power outage occurs while the target settings are configured, the power outage monitoring process will detect the outage. Therefore, once the power supply is restored, gameplay will be possible using the settings that were selected at the time of the power outage. This means that even if a power outage occurs while the target settings are configured, there is no need to reconfigure the settings once the power supply is restored.

Furthermore, for the configuration of features f1 to f6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned feature group f, the following problems can be solved.

Pachinko machines and slot machines are well-known examples of gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, the game ball is dispensed back into the tray storage section from a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like those exemplified above, it is necessary to appropriately deal with power outages, and there is still room for improvement in this regard.

<Characteristics group g>
Feature g1. A setting-dependent storage means (setting-dependent storage area 325 in the 39th embodiment, setting-dependent storage area 326 in the 40th embodiment) having a plurality of first predetermined numbers of setting-dependent storage areas (first to sixth setting information storage areas 325a to 325f in the 39th embodiment, and first to third setting information storage areas 326a to 326c in the 40th embodiment) for storing setting-dependent information corresponding to the player's advantage (win/loss table for low probability mode, win/loss table for high probability mode),
A setting means for setting the setting values to be used (a function that executes setting value update processing in the main CPU 63),
A profit-related means (a function that executes the special symbol variation start process in the main CPU 63) that uses the setting-corresponding information stored in the setting-corresponding storage area corresponding to the setting value set by the setting means to execute profit-related processing (step S504) related to the player's benefit,
Equipped with,
A gaming machine characterized in that the number of types of setting values that can be set by the setting means is less than the first predetermined number.

According to feature g1, since the configuration allows for the selection of a setting value from multiple levels corresponding to the player's advantage, the player expects the most advantageous setting value to be selected. In this case, in a configuration where a first predetermined number of setting-corresponding memory areas are provided for storing setting-corresponding information corresponding to the setting values, the number of types of setting values to be used is less than the first predetermined number. This makes it possible to standardize the configuration of the setting-corresponding memory means with a gaming machine where the number of types of setting values to be used is the first predetermined number, and simplifies the design work of the gaming machine when changing the number of types of setting values. Therefore, it becomes possible to optimize the configuration related to the setting values.

Feature g2. It is equipped with a correspondence information storage means (a set value counter in the work area 221 for specific control) that is capable of storing correspondence information corresponding to each of the first predetermined number of setting-corresponding storage areas,
The setting means sets the setting value to be used by changing the corresponding information stored in the corresponding information storage means based on the change operation.
The gaming machine according to feature g1, wherein the setting information for the setting value that can be set by the setting means is stored in at least one setting-corresponding storage area, and the same setting information is stored in a plurality of setting-corresponding storage areas which are a part of the first predetermined number, so that the setting information is stored in all of the first predetermined number of setting-corresponding storage areas.

According to feature g2, the corresponding information stored in the corresponding information storage means is changed based on the change operation, thereby changing the setting value to be used. The setting corresponding information in the setting corresponding storage area corresponding to the changed corresponding information is then used in the profit-related processing, resulting in the profit-related processing being executed in a manner corresponding to the setting value to be used. In this case, the setting corresponding information for the setting values that can be set by the setting means is stored in at least one setting corresponding storage area. Furthermore, since the same setting corresponding information is stored in multiple setting corresponding storage areas, which are only a portion of the first predetermined number, setting corresponding information is stored in all of the first predetermined number of setting corresponding storage areas. This makes it possible to use the first predetermined number of setting corresponding storage areas as they are, and to use the same configuration that determines the setting value to be used using the corresponding information storage means, while reducing the number of types of setting values to be used to less than the first predetermined number.

Feature g3. The aforementioned profit-related means are
Means for reading the setting correspondence information from the setting correspondence storage area corresponding to the corresponding correspondence information stored in the corresponding information storage means (a function for executing the read operation of the validity table in the main CPU 63),
A means for executing the profit-related processing using the read-out setting correspondence information (a function for executing the processing in step S504 in the main CPU 63),
A gaming machine as described in feature g2, characterized by having the following features.

According to feature g3, even if the number of types of setting values to be used is less than the first predetermined number, profit-related processing can be performed using setting-corresponding information read from the setting-corresponding storage area corresponding to the corresponding information stored in the corresponding information storage means. Therefore, the configuration for reading setting-corresponding information when executing profit-related processing can be used as is.

Feature g4. In a situation where it is possible to change the corresponding information stored in the corresponding information storage means, the system is equipped with a predetermined display control means (a function that executes the processing of steps S9801 to S9804 in the main CPU 63) that causes a predetermined display means (fourth notification display device 204) to display a value corresponding to the current setting value.
The predetermined display control means is
Means for reading display information of setting values corresponding to the setting corresponding information stored in the setting corresponding storage area of the corresponding information storage means (a function that executes the processing of steps S9801 to S9803 in the main CPU 63),
Means for causing the predetermined display means to display the display information corresponding to the read setting value (a function that executes the processing in step S9804 in the main CPU 63),
A gaming machine characterized by having the features described in g2 or g3.

According to feature g4, when changing the setting value to be used, it is possible to change the setting value while confirming the display corresponding to the current setting value displayed on a predetermined display means. In this case, even if the number of types of setting values to be used is less than the first predetermined number, the configuration reads the display information of the setting value corresponding to the setting corresponding information in the setting corresponding storage area of the corresponding information storage means, and causes the predetermined display means to display the display corresponding to the read setting value display information. This makes it possible to use the same configuration for reading the display information of the setting value when executing the display corresponding to the setting value.

Feature g5. The number of types of setting values that can be set by the setting means is a divisor of the first predetermined number and is different from the first predetermined number.
The gaming machine according to feature g4, characterized in that the number of setting-corresponding memory areas, in which the setting-corresponding information corresponding to each setting value is stored, is the same for each setting value.

According to feature g5, even if the number of types of setting values to be used is less than the first predetermined number, it is possible to make the frequency of displaying the setting value using the predetermined display means the same for each setting value.

Feature g6. The gaming machine according to feature g4 or g5, characterized in that, in the order of modification of the corresponding information stored in the corresponding information storage means, the setting corresponding information corresponding to a consecutive sequence of corresponding information is not stored in the setting corresponding storage area corresponding to the same setting value.

According to feature g6, each time a change operation is performed, the setting value to be displayed can be changed using a predetermined display means. This improves the operability of the change operation, even in configurations where the number of types of setting values to be used is less than the first predetermined number.

Furthermore, for the configuration of features g1 to g6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned group of features g, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front where game balls are stored. These stored balls are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters a ball entry section in the game area, for example, it is dispensed back into the tray storage section from a payout device. Furthermore, some pachinko machines are known to have an upper and lower tray storage section. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like those exemplified above, it is necessary to optimize the configuration of the setting values that determine the advantage of the gaming machine, and there is still room for improvement in this regard.

<Characteristics h group>
Features h1. Display means (special drawing display unit 37a, special drawing hold display unit 37b, general drawing display unit 38a, general drawing hold display unit 38b, first to fourth notification display devices 201 to 204, first to fifth display circuits 261 to 265),
A display control means (main CPU 63) transmits display data (display data signal, display clock signal) corresponding to the display content to be displayed on the display means,
When the display data is transmitted by the display control means, a display execution means (display IC 266) sets the display on the display means so that the display content corresponds to the display data,
In a gaming machine equipped with the following features,
The system comprises multiple of the aforementioned display means,
The display control means includes a sequential transmission means (a function that executes a second timer interrupt process in the main CPU 63) that sequentially transmits the display data corresponding to each of the plurality of display means to the display execution means.
When the display execution means receives the display data from the display control means, it performs the display setting on the display means among the plurality of display means that is the target of setting the display data, so that the display content corresponds to the display data.
The gaming machine is characterized in that the transmission interval of the display data from the sequential transmission means to the display execution means is such that the display setting is performed by the display execution means for each display means before each display means becomes unable to maintain the display corresponding to the display data.

According to feature h1, the display execution means performs display settings for the display means according to the display data transmitted from the display control means, thereby controlling the display means to display content corresponding to the display data. This makes it possible to reduce the processing load of the display control means. In this case, in a configuration with multiple display means, the display execution means is not provided in a one-to-one correspondence with the multiple display means, but rather one display execution means is used for multiple display means. This makes it possible to increase the number of display means while suppressing the increase in the number of display execution means. Furthermore, the transmission interval of display data from the display control means to the display execution means is set so that the display settings are performed by the display execution means for each display means before each display means can no longer maintain the display corresponding to the display data. This makes it possible to appropriately display the display corresponding to the display data in each display means, even in a configuration where one display execution means is used for multiple display means. From the above, it becomes possible to make the configuration for display control of the display means suitable.

Feature h2. The gaming machine according to Feature h1, characterized in that when the sequential transmission means transmits the display data to the display execution means, it transmits identifiable information (type data signal, type clock signal) to the display execution means that allows for the identification of the type of display means to which the display data is set.

According to feature h2, when display data is transmitted from the display control means, the display execution means only needs to set that display data for the display means corresponding to the identifiable information transmitted from the display control means. This makes it possible to simplify the configuration of the display execution means, even in a configuration where one display execution means is used for multiple display means.

Feature h3. The gaming machine according to feature h1 or h2, characterized in that the sequential transmission means transmits the display data so that the update cycle is repeated when the multiple display means are each targeted for setting the display data once in a predetermined order.

According to feature h3, the display control means only needs to change the display means to which the display data is to be transmitted according to a predetermined order, thus simplifying the processing configuration of the display control means.

Feature h4. The gaming machine according to any one of features h1 to h3, characterized in that the sequential transmission means transmits the display data for one of the display means even if the content of the display data for that display means is the same as the content of the display data transmitted when that display means was previously the target of transmission.

According to feature h4, since the display data to be transmitted is sent even if its content has not changed, it is possible to continue the same display using a predetermined display means, even in a configuration where one display execution means is used for multiple display means.

Feature h5. The gaming machine according to any one of features h1 to h4, characterized in that the sequential transmission means executes a process for transmitting the display data in a predetermined interrupt process (second timer interrupt process) that is activated by interrupting the process while the display control means is executing a predetermined process.

According to feature h5, since the process for transmitting display data is executed in a predetermined interrupt process, it becomes possible to set the period for setting display data to each display means to a predetermined period. Therefore, even in a configuration where one display execution means is used for multiple display means, it becomes possible to set the display data by the display execution means for each display means before it becomes impossible for each display means to maintain the display corresponding to the display data.

Feature h6. The gaming machine according to feature h5, characterized in that the process for transmitting the display data to the multiple display means targeted by the display setting by the display execution means is consolidated into the predetermined interrupt processing.

According to feature h6, it becomes possible to set the period for setting display data on each display means targeted by the display execution means to the same period.

Feature h7. The display control means includes means for interrupting and activating a specific interrupt process (first timer interrupt process) while the predetermined process is being executed (a function for executing the first timer interrupt process in the main CPU 63),
The gaming machine according to feature h5 or h6, characterized in that the interrupt period of the predetermined interrupt processing is shorter than the interrupt period of the specific interrupt processing.

According to feature h7, the process of transmitting display data to the display execution means is executed at a predetermined interrupt process with a shorter interval than the interrupt period of the specific interrupt process. This makes it possible to transmit display data at a shorter interval compared to a configuration where the process of transmitting display data to the display execution means is executed at a specific interrupt process.

Feature h8. The gaming machine according to feature h7, characterized in that a process for advancing the game is executed in the specific interrupt processing.

According to feature h8, it becomes possible to achieve the excellent effects already described by ensuring that specific interrupt processing is activated at appropriate intervals during the execution of processes necessary to advance the game.

Feature h9. The gaming machine according to feature h7 or h8, characterized in that the predetermined interrupt process is activated by interrupting even when the specific interrupt process is being executed.

According to feature h9, the predetermined interrupt process is activated even when a specific interrupt process is being executed. Therefore, even in a configuration where a specific interrupt process is activated via an interrupt, it is possible to set the transmission cycle of the display data to a predetermined cycle.

Feature h10. A gaming machine according to any one of features h7 to h9, characterized in that the interrupt of the specific interrupt process is prohibited when the predetermined interrupt process is initiated, and the interrupt of the specific interrupt process is permitted when the predetermined interrupt process is terminated.

According to feature h10, it becomes possible to prevent a specific interrupt process from interrupting and executing while a predetermined interrupt process is already running. This allows prioritizing the process for transmitting display data.

Feature h11. The display control means includes means for executing processing at the start of power supply when power supply is started (in the 33rd embodiment, a function to execute the processing in steps S7901 to S7918 in the main CPU 63; in the 35th embodiment, a function to execute the processing in steps S8801 to S8819 in the main CPU 63; in the 36th embodiment, a function to execute the processing in steps S9401 to S9420 in the main CPU 63; in the 37th embodiment, a function to execute the processing in steps S9501 to S9518 in the main CPU 63; in the 42nd embodiment, a function to execute the processing in steps S9901 to S9917 in the main CPU 63),
The gaming machine according to any one of features h5 to h10, characterized in that the predetermined interrupt process is initiated by interrupting even when the process for starting the supply of operating power is being executed.

According to feature h11, it is possible to control the display of multiple display means even while the power supply start-up process is being executed. Furthermore, because a predetermined interrupt process is activated by interrupting the power supply start-up process, it is possible to control the display of multiple display means while the power supply start-up process is being executed, without complicating the processing configuration of the power supply start-up process.

Feature h12. It is equipped with a setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage.
In a situation where the process for starting the supply of the operating power is being executed, the configuration may be such that it is possible to change the setting value to be used.
The gaming machine according to feature h11, characterized in that the sequential transmission means transmits the display data to the display execution means so that a display corresponding to the current setting value is displayed on a predetermined display means in the settingable state.

According to feature h12, when the setting value to be used is being configured, the current setting value is displayed on a predetermined display means, making it easier to configure the setting value to be used.

Feature h13. The display control means includes means for executing progress-response processing to control the progress of the game after the processing at the start of supplying the operating power has been completed (a function for executing the first timer interrupt processing in the main CPU 63),
The sequential transmission means transmits the display data to the display execution means so that a corresponding display corresponding to the execution result of the progress response process is performed on at least some of the display means among the plurality of display means.
The gaming machine according to feature h11 or h12, characterized in that the predetermined interrupt processing is initiated by interrupting even after the processing for starting the supply of operating power has been completed.

According to feature h13, by utilizing a predetermined interrupt process, it becomes possible to control the display of multiple display means both during the process of initiating the supply of operating power and after the process of initiating the supply of operating power has been completed.

Furthermore, for the configuration of features h1 to h13, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Features group i>
Feature i1. A first interrupt execution means (a function that executes the first timer interrupt process in the main CPU 63) that interrupts the other process and executes the first interrupt process based on the elapsed first interrupt cycle while other processes are being executed,
A second interrupt execution means (a function that executes the second timer interrupt process in the main CPU 63) interrupts other processes and executes the second interrupt process based on the elapsed second interrupt cycle while other processes are being executed,
Equipped with,
The second interrupt period is shorter than the first interrupt period.
A gaming machine characterized in that the process for controlling the display of predetermined display means (special figure display unit 37a, special figure hold display unit 37b, general figure display unit 38a, general figure hold display unit 38b, first to fourth notification display devices 201 to 204) is performed in the second interrupt process.

According to feature i1, the process for controlling the display of a predetermined display means is executed in a predetermined interrupt process with a shorter interrupt period than that of a specific interrupt process. This makes it possible to control the display of a predetermined display means at a shorter interval compared to a configuration where the process for controlling the display of a predetermined display means is executed in a specific interrupt process.

Feature i2. The gaming machine according to Feature i1, characterized in that a process for advancing the game is executed in the first interrupt processing.

According to feature i2, it becomes possible to achieve the excellent effects already described by ensuring that the first interrupt process is activated at an appropriate interval for executing the processes necessary to advance the game.

Feature i3. The gaming machine according to feature i1 or i2, characterized in that the second interrupt process is initiated even when the first interrupt process is being executed.

According to feature i3, the second interrupt process is initiated even when the first interrupt process is running. Therefore, even in a configuration where the first interrupt process is initiated via an interrupt, it becomes possible to control the display of a predetermined display means at a predetermined cycle.

Feature i4. A gaming machine according to any one of features i1 to i3, characterized in that the interrupt for the first interrupt process is prohibited when the second interrupt process is initiated, and the interrupt for the first interrupt process is permitted when the second interrupt process is terminated.

According to feature i4, it becomes possible to prevent the first interrupt process from interrupting and executing while the second interrupt process is being executed. This makes it possible to prioritize the display control of a predetermined display means.

Feature i5. When the supply of operating power is started, it is equipped with means for executing the processing that occurs when the supply of operating power is started (a function that executes the main processing in the main CPU 63),
The gaming machine according to any one of features i1 to i4, characterized in that the second interrupt process is initiated by interrupting even when the process for starting the supply of operating power is being executed.

According to feature i5, it is possible to control the display of a predetermined display means even while the process for starting the supply of operating power is being executed. Furthermore, because the second interrupt process is activated by interrupting the process for starting the supply of operating power, it is possible to control the display of a predetermined display means while the process for starting the supply of operating power is being executed, without complicating the processing configuration of the power supply startup process.

Feature i6. It is equipped with a setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
In a situation where the process for starting the supply of the operating power is being executed, the configuration may be such that it is possible to change the setting value to be used.
The gaming machine according to feature i5, characterized in that the second interrupt execution means executes a process in the second interrupt process to cause the predetermined display means to display a value corresponding to the current setting value when the setting is possible.

According to feature i6, when the target setting value is being configured, the current setting value is displayed on a predetermined display means, making it easier to configure the target setting value.

Feature i7. The gaming machine according to feature i5 or i6, characterized in that the second interrupt execution means executes the second interrupt process based on the elapsed second interrupt cycle, even after the processing at the start of supplying the operating power has been completed.

According to feature i7, by utilizing a predetermined interrupt process, it becomes possible to control the display of a predetermined display means both during the process of initiating the supply of operating power and after the process of initiating the supply of operating power has been completed.

Furthermore, for the configuration of features i1 to i7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the inventions relating to the above-mentioned features h and i, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front where game balls are stored. These stored balls are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters a ball entry section in the game area, for example, it is dispensed back into the tray storage section from a payout device. Furthermore, some pachinko machines are known to have an upper and lower tray storage section. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like the examples above, it is necessary to have a suitable configuration for displaying information using the display means, and there is still room for improvement in this regard.

<Features group j>
Feature j1. Means for executing processing at the start of power supply based on the commencement of power supply (in the 33rd embodiment, a function to execute the processing in steps S7901 to S7918 in the main CPU 63; in the 35th embodiment, a function to execute the processing in steps S8801 to S8819 in the main CPU 63; in the 36th embodiment, a function to execute the processing in steps S9401 to S9420 in the main CPU 63; in the 37th embodiment, a function to execute the processing in steps S9501 to S9518 in the main CPU 63; in the 42nd embodiment, a function to execute the processing in steps S9901 to S9917 in the main CPU 63),
A predetermined interrupt execution means (a function to execute a first timer interrupt in the main CPU 63, a function to execute a second timer interrupt in the main CPU 63) interrupts the process at the start of supplying the operating power and executes a predetermined interrupt process,
A gaming machine characterized by having the following features.

According to feature j1, even when the process for starting the supply of operating power is being executed, a predetermined interrupt process is interrupted and activated. Therefore, it is possible to prioritize the execution of the process set as the predetermined interrupt process, even immediately after the start of the supply of operating power. Furthermore, since it is not necessary to set the predetermined interrupt process for the process for starting the supply of operating power, it is possible to prioritize the execution of the process set as the predetermined interrupt process, even immediately after the start of the supply of operating power, without complicating the processing configuration of the process for starting the supply of operating power. Thus, it is possible to suitably perform the processing when the supply of operating power is started.

Feature j2. The gaming machine according to Feature j1, characterized in that the predetermined interrupt execution means executes a process for displaying and controlling predetermined display means (special figure display unit 37a, special figure hold display unit 37b, general figure display unit 38a, general figure hold display unit 38b, first to fourth notification display devices 201 to 204) using the predetermined interrupt process.

According to feature j2, it is possible to display a predetermined information using a predetermined display means even immediately after the start of power supply.

Feature j3. It is equipped with a setting means (a function that executes setting value update processing in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
In a situation where the process for starting the supply of the operating power is being executed, the configuration may be such that it is possible to change the setting value to be used.
The gaming machine according to feature j1 or j2, characterized in that the predetermined interrupt execution means executes a process in the predetermined interrupt process to cause a predetermined display means (fourth notification display device 204) to display a value corresponding to the current setting value when the setting is possible.

According to feature j3, when the target setting value is being configured, the current setting value is displayed on a predetermined display means, making it easier to configure the target setting value.

Feature j4. The gaming machine according to any one of features j1 to j3, characterized in that the predetermined interrupt execution means executes the predetermined interrupt process based on the elapsed predetermined interrupt cycle even after the processing at the start of supplying the operating power has been completed.

According to feature j4, by utilizing a predetermined interrupt process, it becomes possible to execute the process set as the predetermined interrupt process both when the process for starting the supply of operating power is being executed and when the process for starting the supply of operating power has finished.

Feature j5. The gaming machine according to any one of features j1 to j4, characterized in that the predetermined interrupt execution means executes a power outage monitoring process (step S8901) for monitoring the occurrence of a power outage in the predetermined interrupt process.

According to feature j5, the power outage monitoring process is executed even when the power supply startup process is running. Therefore, if a power outage occurs while the power supply startup process is running, it becomes possible to deal with it appropriately.

Feature j6. The predetermined interrupt processing includes progress-responding processing (steps S8907 to S8920 in the main CPU 63) that is performed to control the progress of the game.
If the predetermined interrupt process is activated while the process for starting the supply of operating power is being executed, the power outage monitoring process will be executed, but the progress response process will not be executed.
The gaming machine according to feature j5, characterized in that if the predetermined interrupt process is interrupted and started while the post-completion process (steps S8822 to S8825 in the main CPU 63) is being executed after the process for starting the supply of operating power has been completed, both the power outage monitoring process and the progress response process can be executed.

According to feature j6, in a configuration where a predetermined interrupt process that can be activated by interrupting while post-completion processing is being executed is used to periodically monitor for power outages while the power supply start-up process is being executed, it becomes possible to prevent the execution of the progress-controlling process for controlling the game's progress even if the predetermined interrupt process is activated by interrupting while the power supply start-up process is being executed.

Furthermore, for the configuration of features j1 to j6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned group of features, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front where game balls are stored. These stored balls are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters a ball entry section in the game area, for example, it is dispensed back into the tray storage section from a payout device. Furthermore, some pachinko machines are known to have an upper and lower tray storage section. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like those exemplified above, it is necessary that the processing when the power supply for operation begins is carried out appropriately, and there is still room for improvement in this regard.

<Features k group>
Feature k1. A history storage execution means (a function that executes normal ball entry management processing in the main CPU 63) that stores the history information of the game corresponding to a predetermined event that occurs when the game is played, in the history storage means (normal counter area 231),
Information derivation means (a function that executes the processing of step SA201 in the main CPU 63) that derives mode information (base value) corresponding to the result of the game using the history information stored in the history storage means,
A mode information display control means (function for executing display processing and second timer interrupt processing in the main CPU 63) controls the display of the information display means (first to fourth notification display devices 201 to 204) so that a display corresponding to the mode information derived by the information derivation means is shown,
A predetermined corresponding display control means (a function that executes the processing of step SA320 and the second timer interrupt processing in the main CPU 63) is provided to ensure that a predetermined corresponding display (pre-shift display) is performed by the information display means before a new display corresponding to the manner information is started based on the occurrence of a predetermined display trigger,
A gaming machine characterized by having the following features.

According to feature k1, when a predetermined event occurs, the corresponding history information is stored in the history storage means. Because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Furthermore, using the history information stored in the history storage means, behavioral information corresponding to the game result is derived, and a display corresponding to that derived behavioral information is shown by the information display means. This makes it possible to grasp the results of game history management, such as the frequency of predetermined events. Also, based on the occurrence of a predetermined display trigger, a predetermined corresponding display is shown by the information display means before a new display corresponding to the behavioral information is initiated. This makes it possible to prioritize the predetermined corresponding display over the display corresponding to the behavioral information when a predetermined display trigger occurs, and to notify the user that a predetermined display trigger has occurred using the information display means.

Feature k2. It is equipped with a period elapsed determination means (a function that executes the processing of step SA210 in the main CPU 63) that determines when a predetermined period has elapsed from the occurrence of a predetermined period start trigger until the occurrence of a predetermined period end trigger.
The gaming machine according to feature k1, characterized in that the predetermined corresponding display control means is configured such that when the predetermined period has elapsed, the predetermined display trigger is considered to have occurred, and the predetermined corresponding display is performed by the information display means.

According to feature k2, after a predetermined period has elapsed, a predetermined corresponding display is shown on the information display means, and thereafter, a new display corresponding to the behavioral information is initiated on the information display means. This makes it possible for the administrator of the gaming hall to recognize that the behavioral information displayed on the information display means is from after the predetermined period has elapsed.

Feature k3. The information derivation means derives the pattern information using the history information corresponding to the predetermined event that occurred after the predetermined period, based on the determination that the predetermined period has elapsed by the period elapsed determination means.
The gaming machine according to feature k2, wherein the predetermined corresponding display control means, based on the determination by the period elapsed determination means that the predetermined period has elapsed, causes the predetermined corresponding display to be displayed by the information display means before the display corresponding to the pattern information derived by the information derivation means is displayed by the information display means using the history information corresponding to the predetermined event that occurred after the predetermined period.

According to feature k3, in a configuration where new behavioral information is derived based on the elapsed of a predetermined period, after the predetermined period has elapsed, a predetermined corresponding display is shown on the information display means, followed by a display corresponding to the newly derived behavioral information after the predetermined period has elapsed. This allows the manager of the gaming hall to determine whether the display on the information display means corresponds to the newly derived behavioral information after the predetermined period has elapsed.

Feature k4. The gaming machine according to feature k3, characterized in that it includes means for erasing the history information stored in the history storage means (a function that executes the processing of step SA217 in the main CPU 63) based on the determination that the predetermined period has elapsed by the period elapsed determination means.

According to feature k4, since the history information in the history information storage means is erased after a predetermined period has elapsed, it is possible to reduce the required storage capacity in the history information storage means.

Feature k5. Based on the determination that the predetermined period has elapsed by the period elapsed determination means, the system includes a storage execution means (a function that executes the processing of steps SA203 and SA216 in the main CPU 63) which stores the pattern information corresponding to the results of the game during the predetermined period, derived by the information derivation means using the history information stored in the history storage means, as period-corresponding pattern information in the pattern information storage means (calculation result storage area 234),
The aforementioned mode information display control means controls the information display means to display information such that a display corresponding to the period-corresponding mode information stored in the mode information storage means is performed.
The gaming machine according to any one of features k2 to k4, characterized in that the predetermined corresponding display control means causes the predetermined corresponding display to be displayed by the information display means before the display corresponding to the period-corresponding pattern information newly stored in the pattern information storage means by the storage execution means is displayed by the information display means, based on the period elapsed identification means determining that the predetermined period has elapsed.

According to feature k5, past pattern information derived in predetermined period units is stored as period-corresponding pattern information, and a display corresponding to this period-corresponding pattern information is shown by the information display means. This allows the amusement hall manager to grasp past period-corresponding pattern information derived in predetermined period units by checking the information display means. Furthermore, after the predetermined period has elapsed, the information display means displays a predetermined corresponding display, followed by a display corresponding to the newly derived period-corresponding pattern information resulting from the elapsed period. This allows the amusement hall manager to determine whether the display on the information display means corresponding to the period-corresponding pattern information is a display corresponding to the newly derived period-corresponding pattern information based on the elapsed period.

Feature k6. The mode information storage means is capable of storing a plurality of mode information corresponding to different predetermined periods,
The gaming machine according to feature k5, characterized in that the aspect information display control means controls the information display means to display information such that a display corresponding to each of the plurality of period-corresponding aspect information stored in the aspect information storage means is performed.

According to feature k6, multiple pieces of past period-corresponding pattern information derived in predetermined period units are stored, and the information display means displays the corresponding information for these multiple period-corresponding pattern pieces. Therefore, it becomes possible to compare the occurrence frequencies of predetermined events corresponding to multiple predetermined periods.

Feature k7. A gaming machine according to any one of features k1 to k6, characterized in that it includes means (a function that executes the processing of step SA316 and the second timer interrupt processing in the main CPU 63) to return the information display means to the pre-switching state (interval non-display state) before displaying a different type of type information from the state in which the display corresponding to the type information is being displayed.

According to feature k7, when the display information to be displayed changes, the information display means reverts to the pre-switching state, allowing the gaming hall manager to clearly understand that the display information has changed. In this case, the system has the configuration of feature k1, and a predetermined corresponding display is made by the information display means based on the occurrence of a predetermined display trigger. This makes it possible to notify the system that a predetermined display trigger has occurred by using an information display means that displays information corresponding to different display information with a pre-switching state in between.

Feature k8. The gaming machine according to any one of features k1 to k7, characterized in that, when the predetermined corresponding display control means occurs, the predetermined corresponding display is started by the information display means even if the display duration for the display corresponding to the pattern information has not elapsed.

According to feature k8, when a predetermined display trigger occurs, the predetermined corresponding display is initiated even if the display corresponding to the aspect information is still in progress. This makes it possible to notify the system early of the occurrence of a predetermined display trigger.

Feature k9. The gaming machine according to any one of features k1 to k7, characterized in that, if the predetermined corresponding display control means occurs during the display duration period of the display corresponding to the aspect information, the predetermined corresponding display is started by the information display means after the display duration period has elapsed.

According to feature k9, even if a predetermined display trigger occurs, the predetermined corresponding display will only begin after the display corresponding to the currently displayed aspect information has been completed. This makes it possible to notify the system that a predetermined display trigger has occurred without interfering with the display corresponding to the aspect information that is already being displayed.

Feature k10. The system includes a mode information storage means (calculation result storage area 234) for storing the mode information derived by the information derivation means,
The aspect information storage means includes a plurality of specific storage areas (current area 311, first history area 312, second history area 313, third history area 314) to enable storage of each of the plurality of aspect information derived at different timings by the information derivation means.
The gaming machine according to any one of features k1 to k9, characterized in that the aspect information display control means controls the information display means so that the display of each of the multiple aspect information stored in the multiple specific storage areas is executed sequentially according to a predetermined display order.

According to feature k10, since notifications corresponding to each of the multiple types of information are executed sequentially, it becomes possible to individually grasp the frequency of occurrence of predetermined events over multiple periods while keeping the number of information display means to a minimum. Furthermore, since displays corresponding to each of the multiple types of information stored in multiple specific memory areas are executed sequentially according to a predetermined display order, it becomes easier for the manager of the gaming hall to understand the types of type of information being displayed.

Feature k11. The gaming machine according to feature k10, characterized in that a predetermined display order is defined in association with the multiple specific memory areas.

According to feature k11, since a predetermined display order for the display corresponding to the aspect information is defined in association with multiple specific memory areas, it becomes possible to simplify the processing configuration for identifying the type of aspect information to be displayed when starting a new display corresponding to one aspect information.

Feature k12. The gaming machine according to feature k10 or k11, characterized in that, when the information display means is instructed to display a representation corresponding to the representation information after the predetermined corresponding display has been performed by the information display means, it starts with the display corresponding to the representation information corresponding to the first order in the predetermined display sequence.

According to feature k12, after a predetermined display trigger occurs and a predetermined corresponding display is made, the display begins with the display corresponding to the first aspect in the predetermined display sequence. This allows the display corresponding to the aspect information to be reconfirmed starting from the first aspect of the predetermined display sequence when a predetermined display trigger occurs.

Feature k13. A period elapsed determination means (a function that executes the processing of step SA210 in the main CPU 63) that determines when a predetermined period has elapsed from the occurrence of a predetermined period start trigger until the occurrence of a predetermined period end trigger,
Based on the determination that the predetermined period has elapsed by the period elapsed determination means, a storage execution means (a function that executes the processing of steps SA203 and SA216 in the main CPU 63) stores the mode information corresponding to the results of the game during the predetermined period, which is derived by the information derivation means using the history information stored in the history storage means, as period-corresponding mode information in the plurality of specified storage areas,
Equipped with,
The gaming machine according to any one of features k10 to k12, characterized in that the memory execution means causes the period-corresponding pattern information to be stored in the plurality of specific memory areas in the order derived by the information derivation means.

According to feature k13, it becomes possible to verify the period-corresponding aspect information in the derived order.

Feature k14. The gaming machine according to any one of features k1 to k13, characterized in that the information extraction means performs an information extraction process to extract the manner information based on the occurrence of a processing execution trigger, and the information extraction process is executed multiple times from the start of the extraction of the manner information until the extraction of the manner information is completed.

According to feature k14, since the information derivation process is executed multiple times from the start of the derivation of the aspect information until its completion, the processing load for executing the information derivation process can be reduced compared to a configuration in which the derivation of aspect information is completed in a single process.

Feature k15. A period elapsed determination means (a function that executes the processing of step SA210 in the main CPU 63) that determines when a predetermined period has elapsed from the occurrence of a predetermined period start trigger until the occurrence of a predetermined period end trigger,
Based on the determination that the predetermined period has elapsed by the period elapsed determination means, the storage execution means (a function that executes the processing of steps SA203 and SA216 in the main CPU 63) stores the pattern information corresponding to the results of the game during the predetermined period, which is derived by the information derivation means using the history information stored in the history storage means, as period-corresponding pattern information in the pattern information storage means (calculation result storage area 234),
Equipped with,
The aforementioned mode information display control means controls the information display means to display information such that a display corresponding to the period-corresponding mode information stored in the mode information storage means is performed.
The gaming machine according to feature k14, characterized in that the predetermined corresponding display control means is configured such that when the predetermined period has elapsed, the predetermined display trigger is considered to have occurred, and the predetermined corresponding display is performed by the information display means.

According to feature k15, past pattern information derived in predetermined period units is stored as period-corresponding pattern information, and a display corresponding to this period-corresponding pattern information is performed by the information display means. This allows the manager of the amusement hall to grasp past period-corresponding pattern information derived in predetermined period units by checking the information display means. Furthermore, after the predetermined period has elapsed, the information display means performs a predetermined corresponding display, followed by a display corresponding to the newly derived period-corresponding pattern information resulting from the elapsed period. This allows the manager of the amusement hall to determine whether the display on the information display means corresponding to the period-corresponding pattern information is a display corresponding to newly derived period-corresponding pattern information based on the elapsed period. Additionally, it is possible to perform a predetermined corresponding display during the period in which the period-corresponding pattern information is being derived, thus preventing a display corresponding to the period-corresponding pattern information from being performed unrelated to the fact that the predetermined period has elapsed and the period-corresponding pattern information is still being derived.

Feature k16. The gaming machine according to feature k15, characterized in that the predetermined corresponding display control means causes the predetermined corresponding display to be performed by the information display means for a period longer than the longest period required to derive one of the aforementioned aspect information by the information derivation means.

According to feature k16, if a predetermined period has elapsed and the period-corresponding pattern information is being derived, the information display means will display the predetermined corresponding information.

Furthermore, for the configuration of features k1 to k16, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Features group I>
Feature l1. When a predetermined event occurs as a result of the game being played, a history storage execution means (a function that executes normal ball entry management processing in the main CPU 63) stores the corresponding game history information in the history storage means (normal counter area 231),
Information derivation means (a function that executes the processing of step SA201 in the main CPU 63) that derives mode information (base value) corresponding to the result of the game using the history information stored in the history storage means,
A configuration information storage means (calculation result storage area 234) that stores the configuration information derived by the information derivation means,
A mode information display control means (function for executing display processing and second timer interrupt processing in the main CPU 63) controls the display of the information display means (first to fourth notification display devices 201 to 204) so that a display corresponding to the mode information stored in the mode information storage means is shown,
Equipped with,
The aforementioned aspect information storage means includes a plurality of specific storage areas (current area 311, first history area 312, second history area 313, third history area 314) to enable storage of each of the plurality of aspect information derived at different timings by the information derivation means,
The amusement machine is characterized in that the aspect information display control means controls the information display means so that the display of each of the multiple aspect information stored in the multiple specific storage areas is executed sequentially according to a predetermined display order.

According to feature l1, when a predetermined event occurs, corresponding history information is stored in the history storage means. Because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Furthermore, using the history information stored in the history storage means, behavioral information corresponding to the game result is derived, and this derived behavioral information is displayed by the information display means. This makes it possible to understand the management results of the game history, such as the frequency of predetermined events.

Furthermore, the behavior information storage means stores multiple behavior information items with different timings, and sequentially executes notifications corresponding to each of these behavior information items. This allows for the individual tracking of the frequency of predetermined events over multiple periods while minimizing the number of information display means. Additionally, since the displays corresponding to each of the multiple behavior information items stored in multiple specific storage areas are executed sequentially according to a predetermined display order, it becomes easier for the amusement hall manager to understand the types of behavior information being displayed.

Feature 2. The gaming machine according to Feature 1, characterized in that a predetermined display order is defined in association with the multiple specific memory areas.

According to feature l2, since a predetermined display order for the display corresponding to the aspect information is defined in association with multiple specific memory areas, it becomes possible to simplify the processing configuration for identifying the type of aspect information to be displayed when starting a new display corresponding to one aspect information.

Feature 3. Based on the occurrence of a predetermined display trigger, the system includes a predetermined corresponding display control means (a function that executes the processing of step SA320 and the second timer interrupt processing in the main CPU 63) which ensures that a predetermined corresponding display (pre-shift display) is performed in the information display means before a new display corresponding to the manner information is started.
The amusement machine according to feature l1 or l2, characterized in that, when the information display means causes the information display means to display a representation corresponding to the representation information after the predetermined corresponding display has been performed by the information display means, it starts with the display corresponding to the representation information corresponding to the first order in the predetermined display sequence.

According to feature l3, after a predetermined display trigger occurs and a predetermined corresponding display is performed, the display begins with the display corresponding to the first element in the predetermined display sequence. This allows for re-confirmation of the display information corresponding to the element starting from the first element in the predetermined display sequence when a predetermined display trigger occurs.

Feature 4. A period elapsed determination means (a function that executes the processing of step SA210 in the main CPU 63) that determines when a predetermined period has elapsed from the occurrence of a predetermined period start trigger until the occurrence of a predetermined period end trigger,
Based on the determination that the predetermined period has elapsed by the period elapsed determination means, a storage execution means (a function that executes the processing of steps SA203 and SA216 in the main CPU 63) stores the mode information corresponding to the results of the game during the predetermined period, which is derived by the information derivation means using the history information stored in the history storage means, as period-corresponding mode information in the plurality of specified storage areas,
Equipped with,
The gaming machine according to any one of features l1 to l3, characterized in that the memory execution means causes the period-corresponding pattern information to be stored in the plurality of specific memory areas in the order derived by the information derivation means.

According to feature l4, it becomes possible to verify the period-corresponding pattern information in the derived order.

Feature l5. A gaming machine according to any one of features l1 to l4, characterized in that it includes means (a function that executes the processing of step SA316 and the second timer interrupt processing in the main CPU 63) to return the information display means to the pre-switching state (interval non-display state) before displaying a different type of type information from the state in which the display corresponding to the type information is being displayed.

According to feature l5, when the information to be displayed changes, the information display means reverts to its pre-switching state, allowing the administrator of the gaming hall to clearly understand that the information to be displayed has changed.

Furthermore, for the configuration of features l1 to l5, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features group m>
Feature m1. When a predetermined event occurs as a result of the game being played, a history storage execution means (a function that executes normal ball entry management processing in the main CPU 63) stores the corresponding game history information in the history storage means (normal counter area 231),
Information derivation means (a function that executes the processing of step SA201 in the main CPU 63) that derives mode information (base value) corresponding to the result of the game using the history information stored in the history storage means,
Equipped with,
The information derivation means performs an information derivation process to derive the manner information based on the occurrence of a processing execution trigger, and is characterized in that the information derivation process is performed multiple times from the start of the derivation of the manner information until the completion of the derivation of the manner information.

According to feature m1, when a predetermined event occurs, corresponding history information is stored in the history storage means. Because the history information is stored within the gaming machine itself, unauthorized access to or modification of the history information can be prevented. Furthermore, by using the history information stored in the history storage means to derive behavioral information corresponding to the game's results over a predetermined period, it becomes possible to understand the management results of the game history, such as the frequency of predetermined events. Also, since the information deriving process is executed multiple times from the start to the completion of the behavioral information deriving, the processing load for executing the information deriving process can be reduced compared to a configuration where the behavioral information deriving is completed in a single information deriving process.

Feature m2. A period elapsed determination means (a function that executes the processing of step SA210 in the main CPU 63) that determines when a predetermined period has elapsed from the occurrence of a predetermined period start trigger until the occurrence of a predetermined period end trigger,
Based on the determination that the predetermined period has elapsed by the period elapsed determination means, the storage execution means (a function that executes the processing of steps SA203 and SA216 in the main CPU 63) stores the pattern information corresponding to the results of the game during the predetermined period, which is derived by the information derivation means using the history information stored in the history storage means, as period-corresponding pattern information in the pattern information storage means (calculation result storage area 234),
A mode information display control means (function for executing display processing and second timer interrupt processing in the main CPU 63) controls the display of the information display means (first to fourth notification display devices 201 to 204) so that a display corresponding to the period-corresponding mode information stored in the mode information storage means is shown,
Based on the determination that the predetermined period has elapsed by the period elapsed determination means, a predetermined corresponding display control means (a function that executes the processing of step SA320 and the second timer interrupt processing in the main CPU 63) is provided to cause a predetermined corresponding display to be performed in the information display means,
The gaming machine described in feature m1, characterized by having the following features.

According to feature m2, past pattern information derived in predetermined period units is stored as period-corresponding pattern information, and a display corresponding to this period-corresponding pattern information is shown by the information display means. This allows the amusement hall manager to grasp past period-corresponding pattern information derived in predetermined period units by checking the information display means. Furthermore, after the predetermined period has elapsed, the information display means displays the predetermined corresponding information, followed by a display corresponding to the newly derived period-corresponding pattern information resulting from the elapsed period. This allows the amusement hall manager to determine whether the display on the information display means corresponding to the period-corresponding pattern information is a display corresponding to newly derived period-corresponding pattern information based on the elapsed period. Additionally, it is possible to ensure that the predetermined corresponding display is shown during the period in which the period-corresponding pattern information is being derived, preventing the display of period-corresponding pattern information from being shown unrelated to the elapsed period.

Feature m3. The gaming machine according to feature m2, characterized in that the predetermined corresponding display control means causes the predetermined corresponding display to be performed by the information display means for a period longer than the longest period required to derive one of the aforementioned aspect information by the information derivation means.

According to feature m3, if a predetermined period has elapsed and the period-corresponding pattern information is being derived, the information display means will display the predetermined corresponding information.

Furthermore, for the configuration of features m1 to m3, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned features k, l, and m, the following problems can be solved.

Pachinko machines and slot machines are well-known examples of gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to the player. The game balls stored in this tray storage section are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, the game ball is dispensed back into the tray storage section from a payout device. Furthermore, in pachinko machines, a configuration with an upper and lower tray storage section is also known. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In the case of gaming machines like those exemplified above, proper management of the gaming machines is necessary, and there is still room for improvement in this regard.

<Features group n>
Feature n1. Setting means for setting a target setting value from among multiple setting values corresponding to the player's advantage (a function that executes the processing of step SA709 in the main CPU 63),
When the supply of operating power is started, a condition generating means (a condition in which a setting value update process is executed) is provided to create a configurable state (a condition in which a setting value update process is executed) in which the setting value to be used can be changed, based on the fact that a first setting-related operation (ON operation of the setting key insertion part 68a and pressing operation of the reset button 68c) has been performed.
When the supply of operating power is started, a notification generating means (a function that executes a setting confirmation process in the main CPU 63) is provided to notify the setting value to be used that has been set by the setting means based on the fact that a second setting-related operation (ON operation of the setting key insertion unit 68a) has been performed,
Equipped with,
The aforementioned situation generation means is characterized by including a post-start generation means (in the 45th embodiment, a function to make a positive determination in step SA412 of the main CPU 63, and in the 46th embodiment, a function to make a positive determination in steps SA905 and SA916 of the main CPU 63) that ensures that if the supply of operating power is stopped in the middle of the configurable situation, the configurable situation is returned even if the second setting-related operation is performed when the supply of operating power is started thereafter.

According to feature n1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, players expect the target setting value to be the most advantageous. Furthermore, since changing the target setting value requires performing a first setting-related operation when the power supply is initiated, it becomes difficult to attempt to fraudulently change the target setting value. Additionally, since the target setting value is announced by performing a second setting-related operation when the power supply is initiated, the administrator of the gaming hall can check the target setting value as needed.

Furthermore, if the power supply is interrupted while the system is in a configurable state, the system will revert to a configurable state even if a second setting-related operation is performed when the power supply is subsequently restored. This allows the system to prioritize the change of the target setting value over notification of the setting value when the power supply is restored, preventing the game from starting prematurely before the setting change is actually complete.

Feature n2. The gaming machine according to Feature n1, characterized in that it is equipped with a status notification means (a function to execute the processing in steps SA801 to SA803 in the main CPU 63 and a function to execute the second timer interrupt processing) that notifies the setting value in the process of changing it when the setting is possible.

According to feature n2, when the system is configurable, the setting value being changed is notified, making it possible to change the setting value while understanding the current setting value. Furthermore, because the setting value being changed is notified when the system is configurable, even if a second setting-related operation is performed when the power supply is initiated, and the system becomes configurable, it is still possible to effectively confirm the setting value, even in a configuration where the setting value change operation takes priority.

Feature n3. The gaming machine according to feature n2, characterized in that both the status notification means and the notification generation means display the target setting value using predetermined display means (first to fourth notification display devices 201 to 204).

According to feature n3, whether a setting value is changed or confirmed, the target setting value is displayed on the predetermined display means, making it possible to use the predetermined display means for both situations. Furthermore, even if the configuration is such that a setting becomes possible when the second setting-related operation is performed upon commencement of power supply, the setting value is displayed on the predetermined display means upon entering a setting-possible state. Therefore, the administrator of the gaming hall who performed the second setting-related operation can confirm the setting value by visually inspecting the predetermined display means.

Feature n4. The gaming machine according to feature n3, characterized in that the status notification means displays a corresponding value to the setting value being changed and a corresponding status indicating that the setting is possible, both using the predetermined display means.

According to feature n4, when the system is in a configurable state, a display is shown not only corresponding to the setting value being changed, but also indicating that the system is configurable. This makes it easier for the administrator of the gaming hall to recognize that the system is configurable if the power supply is interrupted while the system is configurable, and then resumed after the power supply is restarted, even if a second setting-related operation is performed.

Feature n5. The post-start generation means, when in the state of being settable, allows for a change in the settable value from the selected value if the supply of operating power is stopped during the state of being settable, as described in any one of features n1 to n4.

According to feature n5, even if the power supply is interrupted during the setting process, once the power supply is restored, it becomes possible to continue the setting change operation from the state immediately before the power supply was interrupted.

Feature n6. A setting-corresponding storage means (setting reference area 341) that stores setting-corresponding information corresponding to the setting value set by the setting means,
A selection-corresponding storage means (setting update area 342) that stores selection-corresponding information corresponding to the setting value selected in the above-mentioned configurable state,
Equipped with,
The aforementioned situation generation means includes means for changing the selection corresponding information stored in the selection corresponding storage means (a function that executes the processing of step SA708 in the main CPU 63) so that when a change trigger occurs in the configurable situation, the setting value to be selected is changed.
The setting means sets the setting value that was selected in the setting-enabled state as the target for use by storing information corresponding to the selection-response information stored in the selection-response storage means as the setting-response information when an termination trigger occurs in the setting-enabled state.
The gaming machine according to any one of features n1 to n5, characterized in that, when the setting-enabled state is established, if the supply of operating power is stopped during the setting-enabled state, the setting value can be changed from the setting value corresponding to the selection-enabled information stored in the selection-enabled storage means.

According to feature n6, the system is provided with a setting-corresponding storage means that stores setting-corresponding information corresponding to the setting value of the target being used, and a selection-corresponding storage means that stores selection-corresponding information corresponding to the setting value being changed in the setting-enabled state. This allows the system to change the setting value while retaining the setting value information that was set before the setting-enabled state began. In this case, if the power supply is interrupted during the setting-enabled state and then resumed, the setting value will be changed from the setting value corresponding to the selection-corresponding information stored in the selection-corresponding storage means at the time the power supply was interrupted. Therefore, even if the power supply is interrupted during the setting-enabled state, once the power supply is resumed, the setting value change operation can be continued from the state immediately before the power supply was interrupted.

Feature n7. The gaming machine according to Feature n6, characterized in that, when the supply of operating power is stopped during the settingable status and the supply of operating power is subsequently started, the first setting-related operation is performed, and the setting value corresponding to the setting-corresponding information stored in the setting-corresponding storage means is modified (in the 45th embodiment, a function to make an affirmative determination in step SA417 of the main CPU 63; in the 46th embodiment, a function to make an affirmative determination in step SA917 of the main CPU 63).

According to feature n7, if the power supply is interrupted during the configurable state and then resumed, and a second setting-related operation is performed, it is possible to resume changing the setting value from the setting value that was being changed before the power supply was interrupted. On the other hand, if the power supply is interrupted during the configurable state and then resumed, and a second setting-related operation is performed, the setting value is changed from the setting value corresponding to the setting-corresponding information stored in the setting-corresponding storage means. This makes it possible to make the initial setting value when initiating a setting value change different depending on the operation performed when the power supply is resumed.

Feature n8. The post-start generation means is capable of ensuring that the setting-enabled state is achieved even if neither the first setting-related operation nor the second setting-related operation is performed when the supply of operating power is stopped during the setting-enabled state and the supply of operating power is subsequently restarted, as described in any one of features n1 to n7.

According to feature n8, if the power supply is interrupted while the system is in a configurable state, the system can become configurable again even if neither the first nor the second configuration-related operation is performed when the power supply is restarted. Therefore, if the power supply is interrupted while a setting value is being changed, it becomes possible to actively create a situation where the setting value can be changed when the power supply is restarted.

Feature n9. The first setting-related operation includes the setting key insertion unit (setting key insertion unit 68a) being set to a predetermined corresponding state (ON operation state) by the setting key,
The gaming machine according to any one of features n1 to n8, characterized in that the status generation means includes means for terminating the configurable status based on the setting key insertion unit determining that the setting key has changed from a predetermined corresponding state to a specific corresponding state (an OFF operation state).

According to feature n9, in order to enter a configurable state, it is necessary to use a setting key to set the setting key insertion unit to a predetermined corresponding state. Therefore, it becomes difficult to attempt to illegally change the target setting value. In this case, the configurable state does not end simply because the setting key insertion unit is in a specific corresponding state; it ends when the setting key insertion unit changes from a predetermined corresponding state to a specific corresponding state. This means that if the power supply to the operating unit is interrupted during the configurable state, and then the power supply is restarted while the setting key insertion unit is in a specific corresponding state, the configurable state will not end immediately. Instead, the configurable state will end when the setting key insertion unit is changed from a specific corresponding state to a predetermined corresponding state, and then again from a predetermined corresponding state to a specific corresponding state. This allows the administrator of the gaming hall to terminate the configurable state at a favorable timing.

Feature n10. The gaming machine according to any one of features n1 to n9, characterized in that the status generation means causes the setting-enabled state to be reached when the supply of operating power is stopped while the setting value of the target being used is being notified by the notification generation means, and the supply of operating power is subsequently restarted, and the first setting-related operation is performed at that time.

According to feature n10, even if the power supply is interrupted while the notification of the target setting value is being made, the system will become configurable if the first setting-related operation is performed when the power supply is subsequently restarted. This makes it possible to prioritize the operation of changing the setting value over the operation of confirming the setting value.

Furthermore, for the configuration of features n1 to n10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W 11. One or more of the following configurations may be applied: Feature X1-X11, Feature Y1-Y11, Feature Z1-Z10, Feature a1-a3, Feature b1-b7, Feature c1-c21, Feature d1-d10, Feature e1-e9, Feature f1-f6, Feature g1-g6, Feature h1-h13, Feature i1-i7, Feature j1-j6, Feature k1-k16, Feature l1-l5, Feature m1-m3, Feature n1-n10, Feature o1-o7, Feature p1-p7, Feature q1-q8, Feature r1-r7, and Feature s1-s4. This makes it possible to achieve synergistic effects from the combined configurations.

<Characteristics group O>
Feature o1. Means for executing a profit-granting process in a manner corresponding to the setting value set as the target of use from among multiple setting values corresponding to the player's advantage (a function that executes the processing in steps S503 and S504 in the main CPU 63),
A setting-related execution means for executing predetermined setting-related processing related to the aforementioned setting value (a function for executing setting value update processing in the main CPU 63, and a function for executing setting confirmation processing in the main CPU 63),
Based on the fact that the supply of operating power was stopped before the completion of the predetermined setting-related processing, the predetermined setting-related processing is restarted from where it left off after the supply of operating power is restarted (in the 45th embodiment, a function to make a positive determination in step SA412 and a function to make a positive determination in step SA414 of the main CPU 63; in the 46th embodiment, a function to make a positive determination in steps SA905 and SA916 of the main CPU 63),
A gaming machine characterized by having the following features.

According to feature o1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, the player expects the target setting value to be the most advantageous. In this case, even if the power supply is interrupted before the predetermined setting-related processing is completed, the predetermined setting-related processing will resume from where it left off once the power supply is restored. This ensures that even if the power supply is interrupted during the predetermined setting-related processing, the processing can continue once the power supply is restored.

Feature o2. The setting-related execution means executes the predetermined setting-related process based on the fact that a predetermined setting-related operation (if the predetermined setting-related process is a setting value update process, the setting key insertion unit 68a is turned ON and the reset button 68c is pressed; if the predetermined setting-related process is a setting confirmation process, the setting key insertion unit 68a is turned ON) has been performed.
The gaming machine according to feature o1, characterized in that the intermediate restart means restarts the predetermined setting-related processing from where it left off, even if the predetermined setting-related operation was not performed.

According to feature o2, if the power supply is interrupted before the predetermined setting-related processing is completed, the predetermined setting-related processing will resume from where it left off, even if the predetermined setting-related operation was not performed. Therefore, it is possible to prioritize the resumption of the predetermined setting-related processing from where it left off.

Feature o3. The setting-related execution means executes the predetermined setting-related processing based on the fact that the predetermined setting-related operation has been performed when the supply of operating power is started.
The aforementioned restart means restarts the predetermined setting-related processing from where it left off even if the predetermined setting-related operations were not performed when the supply of operating power was started.
The gaming machine according to feature o2, characterized in that, if the supply of operating power is stopped before the predetermined setting-related processing is completed, and the supply of operating power is then started, the predetermined setting-related operation is performed, and the predetermined setting-related processing is not restarted from where it left off by the intermediate restart means, but rather the predetermined setting-related processing is newly started by the setting-related execution means.

According to feature o3, since the predetermined setting-related processing is executed based on the fact that a predetermined setting-related operation has been performed when the supply of operating power is started, it becomes difficult to perform acts that illegally execute the predetermined setting-related processing. In this case, even if the predetermined setting-related operation is not performed when the supply of operating power is stopped and then resumed during the predetermined setting-related processing, the predetermined setting-related processing will resume from where it left off, thus prioritizing the resumption of the predetermined setting-related processing from where it left off. On the other hand, if the predetermined setting-related operation is performed when the supply of operating power is stopped and then resumed during the predetermined setting-related processing, the predetermined setting-related processing will not resume from where it left off, but will start anew. This makes it possible to choose between starting the predetermined setting-related processing anew or resuming the predetermined setting-related processing from where it left off, depending on whether or not the predetermined setting-related operation was performed when the supply of operating power is resumed after the supply of operating power is stopped and then resumed during the predetermined setting-related processing.

Feature o4. The predetermined setting-related operation includes the setting key insertion unit (setting key insertion unit 68a) being set to a predetermined corresponding state (ON operation state) by the setting key.
The gaming machine according to feature o2 or o3, characterized in that the setting-related execution means includes means for terminating the predetermined setting-related processing based on the setting key insertion unit determining that the setting key has changed from a predetermined corresponding state to a specific corresponding state (an OFF operation state) by the setting key (a function to execute the processing of step SA504 in the main CPU 63, and a function to execute the processing of steps SA709 and SA710 in the main CPU 63).

According to feature o4, in order to initiate the predetermined setting-related processing, it is necessary to use a setting key to set the setting key insertion unit to a predetermined corresponding state. Therefore, it becomes difficult to perform acts that illegally execute the predetermined setting-related processing. In this case, the predetermined setting-related processing does not terminate simply because the setting key insertion unit is in a specific corresponding state; it terminates only when the setting key insertion unit changes from the predetermined corresponding state to a specific corresponding state. As a result, even if the power supply is stopped before the predetermined setting-related processing is completed, and then the power supply is restarted while the setting key insertion unit is in a specific corresponding state, the predetermined setting-related processing will not terminate immediately. Instead, the predetermined setting-related processing will terminate only after the setting key insertion unit is changed from the specific corresponding state to the predetermined corresponding state, and then again from the predetermined corresponding state to the specific corresponding state. This allows the administrator of the gaming hall to terminate the predetermined setting-related processing at a favorable timing.

Feature o5. The gaming machine according to any one of features o1 to o4, characterized in that the predetermined setting-related processing is a process for changing the setting value to be used.

According to feature o5, even if the power supply is interrupted while a setting value is being changed, the change can be resumed from the point where the setting value was being changed once the power supply is restored. This means that even if the power supply is interrupted while a setting value is being changed, the setting value change process can be continued once the power supply is restored.

Feature o6. The aforementioned predetermined setting-related processing is a process for changing the setting value to be used.
A setting-corresponding storage means (setting reference area 341) that stores setting-corresponding information corresponding to the setting value to be used,
A selection-corresponding storage means (setting update area 342) that stores selection-corresponding information corresponding to the setting value selected in the predetermined setting-related processing,
Equipped with,
The aforementioned setting-related execution means is:
As the predetermined setting-related processing, means for changing the selection-corresponding information stored in the selection-corresponding storage means so that the setting value to be selected is changed when a change trigger occurs (a function that executes the processing of step SA708 in the main CPU 63),
As the predetermined setting-related processing, when a termination trigger occurs, the information corresponding to the selection-corresponding information stored in the selection-corresponding storage means is stored in the setting-corresponding storage means as setting-corresponding information, thereby setting the setting value that was the target of selection as the target of use (a function that executes the processing of step SA709 in the main CPU 63),
Equipped with,
The gaming machine according to any one of features o1 to o5, characterized in that the intermediate restart means allows a change in the setting value from the setting value corresponding to the selection-corresponding information stored in the selection-corresponding storage means when the supply of operating power is stopped before the predetermined setting-related processing is completed.

According to feature o6, the system is provided with a setting-corresponding storage means that stores setting-corresponding information corresponding to the setting value of the target being used, and a selection-corresponding storage means that stores selection-corresponding information corresponding to the setting value being changed in the setting-enabled state. This allows the system to change the setting value while retaining the setting value information that was set before the setting-enabled state began. In this case, if the power supply is interrupted while the setting value is being changed and then resumed, the setting value change will be performed using the setting value corresponding to the selection-corresponding information stored in the selection-corresponding storage means at the time the power supply was interrupted. Therefore, even if the power supply is interrupted while the setting value is being changed, once the power supply is resumed, the setting value change operation can be continued from the state immediately before the power supply was interrupted.

Feature o7. The setting-related execution means executes the predetermined setting-related processing based on the fact that a predetermined setting-related operation has been performed when the supply of operating power is started.
The aforementioned restart means restarts the predetermined setting-related processing from a predetermined point in time based on the fact that the predetermined setting-related operation was not performed when the supply of operating power was started.
The gaming machine according to feature o6, wherein the setting-related execution means is provided with means that allows the setting value to be changed from the setting value corresponding to the setting-related information stored in the setting-related storage means if the supply of operating power is stopped before the predetermined setting-related processing is completed and the supply of operating power is started thereafter, and the predetermined setting-related operation is performed (in the 45th embodiment, a function to make an affirmative determination in step SA417 of the main CPU 63, and in the 46th embodiment, a function to make an affirmative determination in step SA917 of the main CPU 63).

According to feature o7, if the power supply is interrupted while a setting value is being changed and then resumed, it is possible to resume changing the setting value from the setting value that was being changed before the power supply was interrupted, based on the assumption that no predetermined setting-related operation was performed. On the other hand, if the power supply is interrupted while a setting value is being changed and then resumed, and a predetermined setting-related operation is performed, the setting value will be changed from the setting value corresponding to the setting-related information stored in the setting-related storage means. This makes it possible to make the initial setting value when starting a setting value change different depending on the operation performed when the power supply is resumed.

Furthermore, for the configuration of features o1 to o7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features p group>
Feature p1. Means for executing a profit-granting process in a manner corresponding to the setting value set as the target of use from among multiple setting values corresponding to the player's advantage (a function that executes the processing in steps S503 and S504 in the main CPU 63),
The system includes setting-related execution means (a function to execute a setting value update process in the main CPU 63, and a function to execute a setting confirmation process in the main CPU 63) that executes a predetermined setting-related process related to the setting value based on the execution of a predetermined setting-related operation (if the predetermined setting-related process is a setting value update process, the setting key insertion unit 68a is turned ON and the reset button 68c is pressed; if the predetermined setting-related process is a setting confirmation process, the setting key insertion unit 68a is turned ON),
The setting-related execution means is characterized by having a post-supply execution means that, if the supply of operating power is stopped before the predetermined setting-related processing is completed, will execute the predetermined setting-related processing even if the predetermined setting-related operation is not performed after the supply of operating power is started (in the 45th embodiment, a function to make an affirmative determination in step SA412 and a function to make an affirmative determination in step SA414 of the main CPU 63; in the 46th embodiment, a function to make an affirmative determination in steps SA905 and SA916 of the main CPU 63).

According to feature p1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, the player expects the target setting value to be more advantageous. Furthermore, it is possible to ensure that a predetermined setting-related process is executed by performing a predetermined setting-related operation. In this case, even if the power supply is interrupted before the predetermined setting-related process is completed, the predetermined setting-related process will be executed when the power supply is restored, even if the predetermined setting-related operation has not been performed. This makes it possible to prioritize the execution of the predetermined setting-related process.

Feature p2. The setting-related execution means executes the predetermined setting-related processing based on the fact that the predetermined setting-related operation has been performed when the supply of operating power is started.
The gaming machine according to feature p1, characterized in that the post-supply execution means executes the predetermined setting-related processing even if the predetermined setting-related operation is not performed when the supply of operating power is started.

According to feature p2, since the predetermined setting-related processing is executed based on the fact that predetermined setting-related operations have been performed when the supply of operating power is started, it becomes difficult to perform acts that illegally execute the predetermined setting-related processing. In this case, even if the predetermined setting-related operations are not performed when the supply of operating power is stopped and then resumed during the predetermined setting-related processing, the predetermined setting-related processing will still be executed, thus prioritizing the execution of the predetermined setting-related processing.

Feature p3. The predetermined setting-related operation includes the setting key insertion unit (setting key insertion unit 68a) being set to a predetermined corresponding state (ON operation state) by the setting key.
The gaming machine according to feature p1 or p2, characterized in that the setting-related execution means includes means for terminating the predetermined setting-related processing based on the setting key insertion unit determining that the setting key has changed from a predetermined corresponding state to a specific corresponding state (an OFF operation state) by the setting key (a function to execute the processing of step SA504 in the main CPU 63, and a function to execute the processing of steps SA709 and SA710 in the main CPU 63).

According to feature p3, in order to initiate the predetermined setting-related processing, it is necessary to use a setting key to set the setting key insertion unit to a predetermined corresponding state. Therefore, it becomes difficult to fraudulently execute the predetermined setting-related processing. In this case, the predetermined setting-related processing does not terminate simply because the setting key insertion unit is in a specific corresponding state; it terminates only when the setting key insertion unit changes from the predetermined corresponding state to a specific corresponding state. As a result, even if the power supply is stopped before the predetermined setting-related processing is completed, and then the power supply is restarted while the setting key insertion unit is in a specific corresponding state, the predetermined setting-related processing will not terminate immediately. Instead, the predetermined setting-related processing will terminate only after the setting key insertion unit is changed from the specific corresponding state to the predetermined corresponding state, and then again from the predetermined corresponding state to the specific corresponding state. This allows the administrator of the gaming hall to terminate the predetermined setting-related processing at a favorable timing.

Feature p4. The gaming machine according to any one of features p1 to p3, characterized in that, even if the supply of operating power is stopped before the completion of the predetermined setting-related processing, the post-supply execution means does not execute the predetermined setting-related processing if a specific related operation is performed when the supply of operating power is subsequently started.

According to feature p4, even if the power supply is stopped before the predetermined setting-related processing is completed, if a specific related operation is performed when the power supply is subsequently restarted, the predetermined setting-related processing will not be executed. This means that even if the power supply is stopped before the predetermined setting-related processing is completed, if there is no need to perform the predetermined setting-related processing afterward, it is possible to prevent the predetermined setting-related processing from being executed by performing a specific related operation when the power supply is restarted.

Feature p5. The gaming machine according to any one of features p1 to p4, characterized in that the predetermined setting-related processing is a process for notifying the setting value to be used.

According to feature p5, if the power supply is interrupted while the set value notification is in progress, the notification of the set value will restart when the power supply is restored, even if the predetermined setting-related operations are not performed. This makes it possible to prioritize the notification of the set value.

Feature p6. Setting means for setting a target setting value from among multiple setting values corresponding to the player's advantage (a function that executes the processing of step SA709 in the main CPU 63),
When the supply of operating power is started, a condition generating means (a condition in which a setting value update process is executed) is provided to create a configurable state (a condition in which a setting value update process is executed) in which the setting value to be used can be changed, based on the fact that specific related operations (ON operation of the setting key insertion part 68a and pressing operation of the reset button 68c) have been performed.
Equipped with,
The post-supply execution means will not execute the predetermined setting-related processing if the supply of operating power is stopped before the predetermined setting-related processing is completed, but the specific related operation is performed when the supply of operating power is started afterward.
The gaming machine according to feature p5, characterized in that the condition generating means ensures that even if the supply of operating power is stopped before the predetermined setting-related processing is completed, the setting-enabled state is achieved when the specific related operation is performed after the supply of operating power is started.

According to feature p6, even if the power supply is interrupted while the set value notification is in progress, if a specific related operation is performed when the power supply is subsequently restarted, the set value notification will not be executed. Instead, the system will enter a state where the set value can be changed. This allows the system to prioritize the creation of a configurable state over the notification of the set value when a specific related operation is performed to create a configurable state where the set value can be changed.

Feature p7. The gaming machine according to any one of features p1 to p6, characterized in that the predetermined setting-related processing is a process for changing the setting value to be used.

According to feature p7, even if the power supply is interrupted while changing a setting value, the setting value can be changed once the power supply is restored. This means that even if the power supply is interrupted while changing a setting value, the setting value change can be continued once the power supply is restored.

Furthermore, for the configuration of features p1 to p7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features q group>
Feature q1. Means for executing a profit-granting process in a manner corresponding to the setting value set as the target of use from among multiple setting values corresponding to the player's advantage (a function that executes the processing in steps S503 and S504 in the main CPU 63),
A setting-related execution means for executing predetermined setting-related processing related to the aforementioned setting value (a function for executing setting value update processing in the main CPU 63, and a function for executing setting confirmation processing in the main CPU 63),
Equipped with,
The setting-related execution means is characterized in that, even if the supply of operating power is stopped before the predetermined setting-related processing is completed, if a specific related operation (RAM clear operation or setting change operation if the predetermined setting-related processing is a setting confirmation processing, or RAM clear operation if the predetermined setting-related processing is a setting value update processing) is performed when the supply of operating power is started afterward, the predetermined setting-related processing will not be executed.

According to feature q1, the system is configured so that the target setting value is selected from multiple levels corresponding to the player's advantage. Therefore, the player expects the target setting value to be the most advantageous. In this case, even if the power supply is stopped before the predetermined setting-related processing is completed, if a specific related operation is performed when the power supply is restarted, the predetermined setting-related processing will not be executed. This means that even if the power supply is stopped before the predetermined setting-related processing is completed, if there is no need to perform the predetermined setting-related processing afterward, it is possible to prevent the predetermined setting-related processing from being executed by performing a specific related operation when the power supply is restarted.

Feature q2. The gaming machine according to feature q1, characterized in that the predetermined setting-related processing is a process for notifying the setting value to be used.

According to feature q2, even if the power supply is interrupted while the set value notification is in progress, if a specific related operation is performed when the power supply is restarted, the set value notification will not resume. Therefore, if there is no need to continue the set value notification after the power supply is interrupted, it is possible to prevent the notification from being restarted by performing a specific related operation when the power supply is restarted.

Feature q3. The setting-related execution means executes the predetermined setting-related process based on the performance of a predetermined setting-related operation (if the predetermined setting-related process is a setting value update process, the setting key insertion unit 68a is turned ON and the reset button 68c is pressed; if the predetermined setting-related process is a setting confirmation process, the setting key insertion unit 68a is turned ON), and even if the power supply is stopped before the predetermined setting-related process is completed, if the power supply is restarted afterward, the predetermined setting-related process will not be executed if the specific related operation is performed instead of the predetermined setting-related operation. This is the gaming machine according to feature q1 or q2.

According to feature q3, since a predetermined setting-related operation is required to perform a predetermined setting-related process, it becomes more difficult to perform actions that illegally execute the predetermined setting-related process.

Feature q4. The gaming machine according to feature q3, characterized in that the setting-related execution means includes means for executing the predetermined setting-related processing even if the predetermined setting-related processing is not performed, if the supply of operating power is stopped before the predetermined setting-related processing is completed and the supply of operating power is subsequently started. (In the 45th embodiment, this means includes a function to make an affirmative judgment in step SA412 of the main CPU 63 and a function to make an affirmative judgment in step SA414 of the main CPU 63.)

According to feature q4, if the power supply is stopped before the predetermined setting-related processing is completed, it becomes possible to choose whether or not to execute the predetermined setting-related processing without performing the predetermined setting-related operation, depending on whether or not a specific related operation is performed when the power supply is restarted.

Feature q5. The predetermined setting-related operation includes the setting key insertion unit (setting key insertion unit 68a) being set to a predetermined corresponding state (ON operation state) by the setting key.
The gaming machine according to feature q4, characterized in that the setting-related execution means includes means for terminating the predetermined setting-related processing based on the setting key insertion unit determining that the setting key has changed from a predetermined corresponding state to a specific corresponding state (an OFF operation state) by the setting key (a function to execute the processing of step SA504 in the main CPU 63, and a function to execute the processing of steps SA709 and SA710 in the main CPU 63).

According to feature q5, in order to initiate the predetermined setting-related processing, it is necessary to use a setting key to set the setting key insertion unit to a predetermined corresponding state. Therefore, it becomes difficult to perform acts that illegally execute the predetermined setting-related processing. In this case, the predetermined setting-related processing does not terminate simply because the setting key insertion unit is in a specific corresponding state; it terminates only when the setting key insertion unit changes from the predetermined corresponding state to a specific corresponding state. As a result, even if the power supply is stopped before the predetermined setting-related processing is completed, and then the power supply is restarted while the setting key insertion unit is in a specific corresponding state, the predetermined setting-related processing will not terminate immediately. Instead, the predetermined setting-related processing will terminate only after the setting key insertion unit is changed from the specific corresponding state to the predetermined corresponding state, and then again from the predetermined corresponding state to the specific corresponding state. This allows the administrator of the gaming hall to terminate the predetermined setting-related processing at a favorable timing.

Feature q6. A gaming machine according to any one of features q1 to q5, characterized by having a separate execution means that performs a different process from the predetermined setting-related process based on the fact that the specific related operation is performed when the supply of operating power is started (a function that performs only the RAM clear process in the main CPU 63 and does not perform the setting value update process if the predetermined setting-related process is a setting confirmation process, or a function that performs both the RAM clear process and the setting value update process in the main CPU 63, or a function that performs only the RAM clear process in the main CPU 63 and does not perform the setting value update process if the predetermined setting-related process is a setting value update process).

According to feature q6, by utilizing specific related operations performed to execute a separate process, it becomes possible to prevent the predetermined setting-related process from being executed if the power supply is stopped before the predetermined setting-related process is completed and then restarted afterward.

Feature q7. The gaming machine according to feature q6, characterized in that the separate execution means executes the separate process based on the fact that the specific related operation was performed when the supply of operating power is restarted after the predetermined setting-related process is completed.

According to feature q7, even if the power supply is stopped before the predetermined setting-related processing is completed, if the power supply is restarted afterward and a specific related operation is performed, it becomes possible to prioritize the execution of a different process over the predetermined setting-related processing.

Feature q8. The gaming machine according to feature q6 or q7, characterized in that the predetermined setting-related processing is a processing for notifying the setting value to be used, and the separate processing is a processing for changing the setting value to be used.

According to feature q8, even if the power supply is interrupted while the set value notification is in progress, if a specific related operation is performed when the power supply is restarted, the set value notification will not resume. Therefore, if there is no need to continue the set value notification after the power supply is interrupted, it is possible to prevent the notification from being restarted by performing a specific related operation when the power supply is restarted. Furthermore, a specific related operation to execute a process to change the set value can be used as an operation to prevent the set value notification from being restarted.

Furthermore, for the configuration of features q1 to q8, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

<Features r group>
Feature r1. A setting means (a function that executes the processing of step SA709 in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage,
A means for generating a situation in which the setting value to be used can be changed (a situation in which the setting value update process is executed) (in the 45th embodiment, a function to make a positive determination in step SA412 and a function to make a positive determination in step SA417 of the main CPU 63; in the 46th embodiment, a function to make a positive determination in step SA905 and step SA916 of the main CPU 63 and a function to make a positive determination in step SA917),
A setting-corresponding storage means (setting reference area 341) that stores setting-corresponding information corresponding to the setting value set by the setting means,
A selection-corresponding storage means (setting update area 342) that stores selection-corresponding information corresponding to the setting value selected in the above-mentioned configurable state,
Equipped with,
The aforementioned situation generation means includes means for changing the selection corresponding information stored in the selection corresponding storage means (a function that executes the processing of step SA708 in the main CPU 63) so that when a change trigger occurs in the configurable situation, the setting value to be selected is changed.
The setting means is characterized in that, when an termination trigger occurs in the setting-possible state, it stores in the setting-possible storage means information corresponding to the selection-possible information stored in the selection-possible storage means as setting-possible information, thereby setting the setting value that was the target of selection in the setting-possible state as the target of use.

According to feature r1, since the system is configured to select a setting value from multiple levels corresponding to the player's advantage, the player expects the most advantageous setting value to be selected. In this case, by providing a setting-corresponding storage means that stores setting-corresponding information corresponding to the selected setting value, and a selection-corresponding storage means that stores selection-corresponding information corresponding to the setting value being changed during the setting-enabled state, it becomes possible to change the setting value during the setting-enabled state while retaining the setting value information that was set before the setting-enabled state began.

Feature r2. The gaming machine according to Feature r1, characterized in that the situation generation means includes a first change execution means (a function that makes an affirmative judgment in step SA701 of the main CPU 63) that enables a change in the setting value from the setting value corresponding to the selection-corresponding information stored in the selection-corresponding storage means in the previous setting-corresponding situation when the setting-corresponding situation ends before the termination trigger occurs.

Feature r2. If the configurable state ends before a termination trigger occurs, and then the configurable state is restarted, the setting value will be changed from the setting value corresponding to the selection information stored in the selection-corresponding storage means. This means that even if the configurable state ends before a termination trigger occurs, when the configurable state is restarted, the operation to change the setting value will continue from the setting value that was last selected in the previous configurable state.

Feature r3. The gaming machine according to feature r2, characterized in that the situation generation means includes a second change execution means (a function that makes a negative determination in step SA701 of the main CPU 63) that enables a change to the setting value from the setting corresponding information stored in the setting corresponding storage means in the setting corresponding situation that occurs after the setting corresponding situation has ended before the termination trigger occurs.

According to feature r3, if a configurable state ends before a termination trigger occurs and then starts again, it becomes possible to resume changing the setting value from the last selected setting value in the previous configurable state. Furthermore, if a configurable state ends before a termination trigger occurs and then starts again, it becomes possible to change the setting value from the setting corresponding to the setting corresponding information stored in the setting corresponding storage means. This makes it possible to vary the initial setting value when initiating a setting value change depending on the situation when the configurable state is resumed.

Feature r4. The gaming machine according to feature r3, characterized in that the second change execution means enables a change to the setting value from the setting corresponding information stored in the setting corresponding storage means in the setting-enabled state that occurs after the setting-enabled state has ended due to the occurrence of the termination trigger.

According to feature r4, under normal configurable conditions, the setting value will be changed from the current setting value of the target object.

Feature r5. The gaming machine according to feature r3 or r4, characterized in that the situation generating means is provided with means (a function to execute the processing of steps SA405, SA412, and SA417 in the main CPU 63) to cause one of the following situations to occur: a situation in which a setting value corresponding to the selection-corresponding information stored in the selection-corresponding storage means is changed from the setting value corresponding to the setting-corresponding information stored in the setting-corresponding storage means, based on a specific related operation being performed when the setting-corresponding situation starts after the setting-corresponding situation has ended, before the termination trigger occurs in the setting-corresponding situation.

According to feature r5, if a configurable state ends before a termination trigger occurs, and then a configurable state begins again, the administrator of the gaming hall can choose whether to resume changing the setting value from the last selected setting value in the previous configurable state, or to start changing the setting value from the currently used setting value.

Feature r6. The gaming machine according to any one of features r1 to r5, characterized in that it includes means (a function that executes the processing of steps SA801 to SA803 in the main CPU 63) for displaying the setting value corresponding to the selection-corresponding information stored in the selection-corresponding storage means in the setting-possible state, using predetermined display means (first to fourth notification display devices 201 to 204).

According to feature r6, it becomes possible to change the setting value while checking the setting value in progress when the setting is configurable.

Feature r7. A gaming machine according to any one of features r1 to r6, characterized in that, in situations where the setting is not possible, the setting value corresponding to the setting information stored in the setting-compatible storage means is displayed by a predetermined display means (first to fourth notification display devices 201 to 204) (a function that executes the processing of steps SA601 to SA603 in the main CPU 63).

According to feature r7, it becomes possible to check the current settings of the target system as needed.

Furthermore, for the configuration of features r1 to r7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, and features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned group n, group o, group p, group q, and group r features, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on its front where game balls are stored. These stored balls are guided to a game ball launching device and launched towards the game area according to the player's launching operation. When a game ball enters a ball entry section in the game area, for example, it is dispensed back into the tray storage section from a payout device. Furthermore, some pachinko machines are known to have an upper and lower tray storage section. In this case, game balls stored in the upper tray storage section are guided to the game ball launching device, and any excess game balls in the upper tray storage section are discharged into the lower tray storage section.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like those exemplified above, it is necessary to optimize the configuration of the setting values that determine the advantage of the gaming machine, and there is still room for improvement in this regard.

<Features group s>
Feature s1. A predetermined response initiation means (in the 45th embodiment, a function to make an affirmative determination in step SA413 and a function to make an affirmative determination in step SA417 of the main CPU 63; in the 46th embodiment, a function to make an affirmative determination in step SA913 and a function to make an affirmative determination in step SA917 of the main CPU 63) that initiates a predetermined response process (setting confirmation process, setting value update process) based on the predetermined key insertion part (setting key insertion part 68a) being set to a predetermined response state (ON operation state) by a predetermined key,
A predetermined response termination means (a function that executes the processing of steps SA709 and SA710 in the main CPU 63) terminates the predetermined response processing based on the determination that the predetermined key insertion unit has been changed from the predetermined response state to a specific response state (OFF operation state) by the predetermined key,
A gaming machine characterized by having the following features.

According to feature s1, in order to start the predetermined response process, it is necessary to use a predetermined key to put the predetermined key insertion unit into a predetermined response state. Therefore, it becomes difficult to attempt to start the predetermined response process fraudulently. In this case, the predetermined response process does not terminate simply because the predetermined key insertion unit is in a specific response state; it terminates only when the predetermined key insertion unit changes from the predetermined response state to a specific response state. As a result, even if the predetermined response process is started while the predetermined key insertion unit is in a specific response state for some reason, the predetermined response process will not terminate immediately. Instead, the predetermined response process will terminate only after the predetermined key insertion unit is changed from the specific response state to the predetermined response state, and then again from the predetermined response state to the specific response state. This allows the administrator of the gaming hall to terminate the predetermined response process at a favorable timing.

Feature s2. The gaming machine according to Feature s1, characterized by comprising a separate starting means (in the 45th embodiment, a function to make an affirmative determination in step SA412 and a function to make an affirmative determination in step SA414 of the main CPU 63; in the 46th embodiment, a function to make an affirmative determination in steps SA905 and SA916 of the main CPU 63) that initiates the predetermined corresponding processing when the predetermined key insertion section is in the predetermined corresponding state based on the fulfillment of a specific starting condition.

According to feature s2, since the predetermined response process is initiated even when the predetermined key insertion unit is in a specific response state based on the fulfillment of a specific start condition, it is possible to diversify the triggers for initiating the predetermined response process. However, in this configuration, the predetermined response process is initiated when the predetermined key insertion unit is in a specific response state. In contrast, with the configuration of feature s1, the predetermined response process does not terminate simply because the predetermined key insertion unit is in a specific response state; it terminates when the predetermined key insertion unit changes from a predetermined response state to a specific response state. Therefore, even if the predetermined response process is initiated when the predetermined key insertion unit is in a specific response state, it does not terminate immediately. The predetermined response process terminates only after the predetermined key insertion unit is changed from a specific response state to a predetermined response state, and then again from a predetermined response state to a specific response state. This allows the predetermined response process to terminate at a timing favorable to the administrator of the gaming hall.

Feature s3. The predetermined response initiation means initiates the predetermined response process based on the fact that the predetermined key insertion unit is in the predetermined response state when the supply of operating power is started.
The gaming machine according to feature s2, characterized in that the aforementioned specific start condition is met when the supply of operating power is stopped while the predetermined corresponding process is being executed and the supply of operating power is resumed.

According to feature s3, the predetermined response process is initiated based on the predetermined key insertion unit being in a predetermined corresponding state when the power supply is started. This makes it difficult to attempt to start the predetermined response process illegally. Furthermore, even if the power supply is stopped while the predetermined response process is being executed, if the specific start condition is met when the power supply is resumed, the predetermined response process will start even if the predetermined key insertion unit is not in the predetermined corresponding state. This allows for prioritizing the start of the predetermined response process if it is terminated prematurely.

Feature s4. It is equipped with means for executing a profit-granting process in a manner corresponding to the setting value set as the target of use from among multiple setting values corresponding to the player's advantage (a function that executes the processing in steps S503 and S504 in the main CPU 63),
The gaming machine according to any one of features s1 to s3, characterized in that the predetermined corresponding process is a process related to the set value.

According to feature s4, it becomes possible to achieve the above-mentioned excellent effects on processing related to the set values.

Furthermore, for the configuration of features s1 to s4, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W1 1. One or more of the following configurations may be applied: features X1-X11, features Y1-Y11, features Z1-Z10, features a1-a3, features b1-b7, features c1-c21, features d1-d10, features e1-e9, features f1-f6, features g1-g6, features h1-h13, features i1-i7, features j1-j6, features k1-k16, features l1-l5, features m1-m3, features n1-n10, features o1-o7, features p1-p7, features q1-q8, features r1-r7, and features s1-s4. This allows for synergistic effects from the combined configurations.

According to the invention relating to the above-mentioned group of features, the following problems can be solved.

Examples of gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage unit on its front for storing game balls given to the player. The game balls stored in this tray storage unit are guided to a game ball launching device and launched towards the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section in the game area, a lottery process is executed, for example, by a control means, to determine whether or not to generate a game state favorable to the player.

Furthermore, in slot machines, when a new game is started by operating the start lever while tokens are bet, the control system executes a lottery process. If the lottery process is executed, the control system starts the reels spinning. If the stop button is operated while the reels are spinning, the control system stops the reels spinning. If the stopping result after the reels stop corresponds to the winning combination in the lottery, the player is awarded the corresponding prize.

In gaming machines like the examples above, the processing in the control system needs to proceed smoothly, and there is still room for improvement in this regard.

The following shows the basic configuration of a gaming machine to which each of the above features can be applied or to which each of the above features can be applied.

Pachinko game machine: A game machine comprising an operating means operated by a player, a game ball launching means that launches game balls based on the operation of the operating means, a ball passage that guides the launched game balls to a predetermined game area, and various game components arranged within the game area, wherein the game machine grants a reward to the player when a game ball passes through a predetermined passage among these game components.

Slot machines and other revolving-type gaming machines: These machines are equipped with a symbol display device that displays multiple symbols in a variable manner. The variable display of the multiple symbols is initiated by the operation of a start operation means, and the variable display of the multiple symbols is stopped by the operation of a stop operation means or after a predetermined time has elapsed. The machine then grants the player a reward based on the symbols displayed after the display stops.

10...Pachinko machine, 12...Game machine body, 14...Front door frame, 28...Launch operation device, 33...First operation port, 34...Second operation port, 35...Through gate, 49a...Gate detection sensor, 63...Main CPU, 65...Main RAM, 68a...Setting key insertion part, 68b...Update button, 68c...Reset button, 69a...First notification display device, 69b...Second notification display device, 69c...Third notification display device, 112...Management Side CPU, 117...History memory, 171...Separate storage memory, 181-186...History memory for settings 1-6, 191...First history memory, 192...Second history memory, 201...First notification display device, 201a-201g...Display segments, 202...Second notification display device, 202a-202g...Display segments, 203...Third notification display device, 204...Fourth notification display device, 221...Specific Control work area, 222... Stack area for specific control, 223... Work area for non-specific control, 224... Stack area for non-specific control, 231... Normal counter area, 232... Counter area for opening/closing execution mode, 233... Counter area for high-frequency support mode, 234... Calculation result storage area, 241... Management RAM, 251... Reset signal output unit, 252... Program monitoring unit, 266... Display IC, 311... Current area, 312... First history area, 313... Second history area, 314... Third history area, 321-324... Display segments, 325... Setting-compatible storage area, 325a-325f... First to sixth setting information storage area, 326... Setting-compatible storage area, 326a-326c... First to third setting information storage area, 341... Setting reference area, 342... Setting update area.

Claims (1)

A history storage execution means that stores the history information of a game corresponding to a predetermined event that occurs when a game is played,
Information deriving means for deriving behavioral information corresponding to the result of the game using the history information stored in the history storage means,
A configuration information storage means for storing the configuration information derived by the information derivation means,
A manner information display control means that controls the display of manner information corresponding to the manner information stored in the manner information storage means to be displayed by the information display means,
A predetermined corresponding display control means that controls the information display means to ensure that a predetermined corresponding display is performed before a new display corresponding to the aspect information is initiated, based on the occurrence of a predetermined display trigger.
A setting means for setting a value corresponding to the player's advantage,
A condition generating means that creates a condition in which the setting value can be set by the setting means,
Equipped with,
The aforementioned aspect information storage means includes a plurality of specific storage areas that enable the storage of each of the plurality of aspect information,
The aspect information display control means controls the information display means to sequentially execute displays corresponding to each of the multiple aspect information stored in the multiple specific storage areas according to a predetermined display order, and when the information display means is to be made to perform a display corresponding to the aspect information after the predetermined corresponding display has been performed, it starts with the display corresponding to the aspect information corresponding to the first order in the predetermined display order.
The information derivation means derives the aspect information using the historical information during a predetermined advantageous period.
This gaming machine is equipped with control means for performing various processes,
The control means is
An in-area processing execution means that executes in-area processing, which is processing that uses a program stored in a predetermined address range storage area of a program storage means,
An out-of-bounds processing execution means that performs out-of-bounds processing, which is processing that utilizes a program stored in a storage area of an address range outside the predetermined address range of the program storage means,
Equipped with,
This gaming machine is
When processing within the aforementioned region is performed, information can be written to and read from the corresponding storage area within the region, while when processing outside the aforementioned region is performed, information can be read but information cannot be written to the corresponding storage area within the region.
When the aforementioned out-of-area processing is performed, information can be written to and read from the out-of-area corresponding storage area, while when the aforementioned in-area processing is performed, information can be read but information cannot be written to the out-of-area corresponding storage area,
Equipped with,
The gaming machine is characterized in that the domain-based processing execution means includes means capable of executing a process as a domain-based process that can determine whether or not the setting value set as the target for use is normal .