JP7843787B2 - Peak current load control circuit - Google Patents

Description

This application claims priority to the Chinese patent applications filed with the China National Patent Office on March 31, 2022, application number 202210331067.8, invention title "Peak Current Load Control Circuit," and application number 202220729267.4, invention title "Peak Current Load Control Circuit," also filed with the China National Patent Office on March 31, 2022. All contents of these applications are incorporated into this application by reference.

This invention relates to the field of power electronics, particularly to peak current load control circuits.

In smart speaker applications, when playing bass frequencies, the instantaneous output of the smart speaker can be several times higher than its normal playback output. For example, with the Tmall Genie X5 speaker, the rated output displayed on the charger is 12V 2A (24W). During bass playback, the peak output current reaches 3.8A, and the instantaneous output reaches 45.6W. Such instantaneous high output causes a significant drop in the charger's output voltage, resulting in the smart speaker shutting down and restarting.

Therefore, the current challenge is to avoid the significant drop in the charger's output voltage during momentary high-power operation, which can cause smart speakers to shut down and restart, and to improve the stability of the charger's output voltage.

The objective of this invention is to provide a peak current load control circuit that avoids load interruption and restart caused by a significant drop in the charger's output voltage during instantaneous high power consumption, thereby improving the stability of the charger's output voltage.

To solve the above technical problems, the peak current load control circuit provided in the present invention is:
A reference voltage adjustment circuit for generating a reference voltage control signal based on the constant current mode signal and/or constant voltage mode signal of the primary side control chip,
A peak load detection module for adjusting a reference voltage for peak load detection based on the reference voltage control signal, performing peak load detection on the primary side control chip based on the reference voltage, and adjusting the control mode of the primary side control chip, wherein the control mode includes a constant current loop control mode and a constant voltage loop control mode, and the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage, and the peak load reference voltage is k times the overcurrent protection reference voltage (where k is greater than 1).

Optionally, the reference voltage adjustment circuit is used to generate a first control signal corresponding to the peak load reference voltage when the primary control chip is in the constant current loop control mode, based on the constant current mode signal and/or the constant voltage mode signal; and to generate a second control signal corresponding to the overcurrent protection reference voltage when the primary control chip is in the constant voltage loop control mode and the reference voltage is the peak load reference voltage. The reference voltage control signal includes the first and second control signals.

The reference voltage adjustment circuit may be optionally configured as follows:
The constant current adjustment circuit includes a constant current adjustment circuit that, based on a constant current mode start signal and a constant current mode end signal corresponding to the constant current mode signal, generates a first control signal after the primary side control chip enters the constant current loop control mode, and generates a second control signal after the reference voltage is the peak load reference voltage and the primary side control chip has ended the constant current loop control mode, where the reference voltage is the peak load reference voltage and the primary side control chip has ended the constant current loop control mode.

Optionally, the constant current adjustment circuit includes a first AND gate element, a first RS flip-flop, a D flip-flop, and a paraphase amplifier.
Of these, the first input terminal of the first AND gate element is connected to the output terminal of the constant current mode termination signal, the second input terminal of the first AND gate element is connected to the Q output terminal of the D flip-flop, the output terminal of the first AND gate element is connected to the R input terminal of the first RS flip-flop, the S input terminal of the first RS flip-flop is connected to the output terminal of the constant current mode start signal, the Q output terminal of the first RS flip-flop is connected to the D input terminal of the D flip-flop, the clock input terminal of the D flip-flop is connected to the output terminal of the turn-on pulse signal that drives the turn-on of the primary side control chip cycle, the Q output terminal of the D flip-flop is connected to the input terminal of the paraphase amplifier, and the output terminal of the paraphase amplifier is connected to the input terminal of the reference voltage control signal of the peak load detection module.

Optionally, the first RS flip-flop includes a first Norgate element and a second Norgate element.
Of these, the first input terminal of the first Noah gate element is connected to the output terminal of the constant current mode start signal, the second input terminal of the first Noah gate element is connected to the output terminal of the second Noah gate element, the output terminal of the first Noah gate element is connected to the first input terminal of the second Noah gate element, the second input terminal of the second Noah gate element is connected to the output terminal of the first AND gate element, and the common terminal connecting the output terminal of the second Noah gate element and the second input terminal of the first Noah gate element is connected to the D input terminal of the D flip-flop as the Q output terminal of the first RS flip-flop.

Optionally, the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the medium-high reference voltage, and a fourth control signal corresponding to the medium-low reference voltage, wherein the peak load reference voltage is greater than the medium-high reference voltage, greater than the medium-low reference voltage, and greater than the overcurrent protection reference voltage.
In response to this, the reference voltage adjustment circuit is used to generate the following based on the constant current mode signal and/or the constant voltage mode signal: the fourth control signal when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode; the second control signal when the reference voltage is the medium-low reference voltage and the primary side control chip is in the constant voltage loop control mode; the third control signal when the reference voltage is the medium-low reference voltage and the primary side control chip is in the constant current loop control mode; the fourth control signal when the reference voltage is the medium-high reference voltage and the primary side control chip is in the constant voltage loop control mode; the first control signal when the reference voltage is the medium-high reference voltage and the primary side control chip is in the constant current loop control mode; and the third control signal when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant voltage loop control mode.

Optionally, the peak current load control circuit further:
The system includes a timing circuit that counts the peak load duration and/or overcurrent protection duration, outputs a peak load protection restart control signal when the peak load duration reaches a first threshold, and/or outputs an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold.

Optionally, the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage. The timing circuit is specifically used to count the peak load duration and the overcurrent protection duration based on the constant current mode signal of the primary control chip, and to output the peak load protection restart control signal when the peak load duration reaches the first threshold, and to output the overcurrent protection restart control signal when the overcurrent protection duration reaches the second threshold. The peak load duration is the duration when the reference voltage is the peak load reference voltage and the primary control chip is in the constant current loop control mode, and the overcurrent protection duration is the duration when the reference voltage is the overcurrent protection reference voltage and the primary control chip is in the constant current loop control mode, or when the reference voltage is the peak load reference voltage.

Optionally, the timing circuit includes a peak load timing circuit and an overcurrent protection timing circuit, of which,
The overcurrent protection timing circuit includes a second AND gate element, a second RS flip-flop, and a first timer, wherein the first input terminal of the second AND gate element is connected to the output terminal of the reference voltage control signal of the reference voltage adjustment circuit, the second input terminal of the second AND gate element is connected to the output terminal of the constant current mode termination delay signal corresponding to the constant current mode signal, the output terminal of the second AND gate element is connected to the R input terminal of the second RS flip-flop, the S input terminal of the second RS flip-flop is connected to the output terminal of the constant current mode start signal corresponding to the constant current mode signal, the Q output terminal of the second RS flip-flop is connected to the enable terminal of the first timer, the output terminal of the first timer is used as the output terminal of the overcurrent protection timing circuit to output the overcurrent protection restart control signal when the duration of the received enable signal reaches the second threshold, and the turn-on delay signal is a pulse signal that follows a predetermined number of turn-on pulse signals after the termination of the constant current mode control mode.
The peak load timing circuit includes a third AND gate element and a second timer, wherein the first input terminal of the third AND gate element is connected to the output terminal of the constant current mode signal, the second input terminal of the third AND gate element is connected to the output terminal of the paraphase signal corresponding to the reference voltage control signal, and the output terminal of the third AND gate element is connected to the enable terminal of the second timer, and the output terminal of the second timer is used as the output terminal of the peak load timing circuit to output the peak load protection restart control signal when the duration of the received enable signal reaches the first threshold.

Optionally, the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the medium-high reference voltage, and a fourth control signal corresponding to the medium-low reference voltage, wherein the peak load reference voltage is greater than the medium-high reference voltage, greater than the medium-low reference voltage, and greater than the overcurrent protection reference voltage.
In response, the timing circuit is used to count the peak load duration and the overcurrent protection duration based on the constant current mode signal of the primary side control chip, to output the peak load protection restart control signal when the peak load duration reaches the first threshold, and to output the overcurrent protection restart control signal when the overcurrent protection duration reaches the second threshold. The peak load duration is the duration when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant current loop control mode, and the overcurrent protection duration is the duration when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode, or when the reference voltage is the medium-low reference voltage, the medium-high reference voltage, or the peak load reference voltage.

The peak current load control circuit provided in this invention includes a reference voltage adjustment circuit for generating a reference voltage control signal based on a constant current mode signal and/or a constant voltage mode signal of a primary side control chip, and a peak load detection module for adjusting the reference voltage for peak load detection based on the reference voltage control signal, performing peak load detection on the primary side control chip based on the reference voltage, and adjusting the control mode of the primary side control chip, wherein the control mode includes a constant current loop control mode and a constant voltage loop control mode, the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage, and the peak load reference voltage is k times the overcurrent protection reference voltage (where k is greater than 1).

From this, it can be seen that the present invention, by installing a reference voltage adjustment circuit and controlling and adjusting the reference voltage for peak load detection of the primary side control chip based on the constant current mode signal and/or constant voltage mode signal of the primary side control chip, controls the switching between the constant current loop control mode and the constant voltage loop control mode of the primary side control chip. This prevents load-shatter restarts that occur when the output voltage of the primary side regulation charger drops sharply due to a momentary increase in output voltage, thereby improving the stability of the output voltage when the primary side regulation charger detects a peak current load.

To more clearly illustrate the embodiments of the present invention or the techniques in the prior art, the following briefly introduces the drawings necessary for use in the embodiments or the prior art. However, the drawings in the following description are merely embodiments of the present invention, and it will be obvious to those skilled in the art that, without any creative work, other drawings can be obtained based on the provided drawings.

Figure 1 is a block diagram of the configuration of the peak current load control circuit provided in an embodiment of the present invention. Figure 2 is a schematic diagram illustrating the principle of control mode switching of the primary side control chip. Figure 3 is a schematic diagram of peak load detection with two-position reference voltage switching provided in an embodiment of the present invention. Figure 4 is a schematic diagram of peak load detection for four-position reference voltage switching provided in an embodiment of the present invention. Figure 5 is a schematic diagram of a reference voltage adjustment circuit within a peak current load control circuit provided in an embodiment of the present invention. Figure 6 is a schematic diagram of the overcurrent protection timing circuit in the peak current load control circuit provided in an embodiment of the present invention. Figure 7 is a schematic diagram of the peak load timing circuit within the peak current load control circuit provided in an embodiment of the present invention. Figure 8 is a schematic sequence diagram of the related signals of the constant current mode signal in the peak current load control circuit provided in an embodiment of the present invention.

To further clarify the object, technical method, and advantages of the embodiments of the present invention, the technical method of the embodiments is described clearly and completely below, in conjunction with the drawings of the embodiments. However, it is clear that the embodiments described are only some, not all, embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention, without any creative work on their part, fall within the scope of the present invention.

Referring to Figure 1, Figure 1 is a block diagram of the configuration of a peak current load control circuit provided in an embodiment of the present invention. The peak current load control circuit is
A reference voltage adjustment circuit 10 for generating a reference voltage control signal based on the constant current mode signal and/or constant voltage mode signal of the primary side control chip,
A peak load detection module 20 for adjusting the reference voltage for peak load detection based on a reference voltage control signal, performing peak load detection on a primary side control chip based on the reference voltage, and adjusting the control mode of the primary side control chip, wherein the control mode includes a constant current loop control mode and a constant voltage loop control mode, and the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage, and the peak load reference voltage is k times the overcurrent protection reference voltage (where k is greater than 1).

The principle behind whether the load of a primary side regulation (PSR) system is controlled by a CV (constant voltage) loop or a CC (constant current) loop is that the load weight is detected in real time by the load capacity determined by the reference voltage (VrefCC) corresponding to the constant current point. Therefore, if the load can be moved, the entire PSR system is controlled using the CV loop; if the load cannot be moved, the entire PSR system is controlled using the CC loop. As shown in Figure 2, section A to B belongs to the constant voltage CV section, and the output of the primary side regulation system is controlled by the CV loop. Section B to C belongs to the constant current CC section, and since the CV loop cannot move the load in this section, the system output is controlled by the CC loop.

Specifically, the following formula can be used for peak load detection performed by the peak load detection module 20 on the primary side control chip.

In the above equation, Iout is the average output current of the CC loop control of the primary side control chip, Np is the number of turns of the primary side coil of the transformer, Ns is the number of turns of the secondary side coil of the transformer, Rcs is the resistance value of the peak current sampling resistor, and VrefCC is the reference voltage, i.e., the reference voltage of the CC loop control.

In other words, the peak load detection module 20, based on the reference voltage (VrefCC) controlled and adjusted based on the reference voltage adjustment circuit 10, employs the same or a similar method as the peak load detection method in the prior art to perform peak load detection on the primary side control chip, and can adjust and switch between the constant current loop control mode or constant voltage loop control mode adopted by the primary side control chip.

Accordingly, the peak load detection module 20 of this embodiment adjusts the reference voltage for peak load detection based on the reference voltage control signal transmitted by the connected reference voltage adjustment circuit 10, thereby adjusting and switching the load capacitance of the primary side control chip. Furthermore, based on the load conditions at that time, it adjusts the switching of the control mode of the primary side control chip, namely between constant current loop control mode and constant voltage loop control mode, thereby improving the stability of the output voltage of the primary side regulation charger.

It should be explained that the specific number and values of the reference voltage for peak load detection in this embodiment can be set by the designer based on the practical scenario and user needs. For example, the reference voltage can include a reference voltage corresponding to the output current point of overcurrent protection (OCP) (i.e., OCP point, points A and D in Figure 3) (i.e., overcurrent protection reference voltage) and a reference voltage corresponding to the output current point of the peak load (i.e., Pk Load point, points B and C in Figure 3) (i.e., peak load reference voltage). Accordingly, the reference voltage control signal transmitted by the reference voltage adjustment circuit 10 to the peak load detection module 20 can include a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage, where Pk Load/OCP = k, i.e., the peak load reference voltage is k times the overcurrent protection reference voltage, and k is greater than 1. In other words, when k is large, if the output current for the load is between the OCP point and the Pk Load point, peak load detection can be controlled in two positions: an overcurrent protection reference voltage (VrefCCL) and a peak load reference voltage (VrefCCH). The reference voltage (VrefCC) that determines the constant current point can be switched between VrefCCL and VrefCCH. Correspondingly, the peak load detection module 20 can also be controlled by switching the control mode of the primary side control chip between a constant current loop control mode (CC Mode) and a constant voltage loop control mode (CV Mode). Compared to conventional peak load detection with a fixed reference voltage, this avoids situations where the output voltage drops excessively.

Furthermore, in this embodiment, the reference voltage (VrefCC) that determines the constant current point may include a preset reference voltage between the overcurrent protection reference voltage and the peak load reference voltage. Increasing the number of VrefCC positions further improves the ripple during the control mode switching process of the primary side control chip. Therefore, the more positions VrefCC has, the better the ripple performance. For example, if the number of preset reference voltages between the overcurrent protection reference voltage and the peak load reference voltage is two, the reference voltage (VrefCC) can include four positions: peak load reference voltage (VrefCCH), overcurrent protection reference voltage (VrefCCL), medium-high reference voltage (VrefCCMHigh), and medium-low reference voltage (VrefCCMLow). Of these, VrefCCH > VrefCCMHigh > VrefCCMLow > VrefCCL. As shown in Figure 4, when the ΔVrefCC between two adjacent positions is the same, by installing VrefCC at four positions, the ΔVrefCC that changes between two adjacent positions each time can be reduced to only 1/3 of the VrefCC between the original two positions, thereby improving ripple.

In this embodiment, the constant current mode signal of the primary control chip may be the signal of the constant current loop control mode adopted by the primary control chip, for example, the CCMode signal in Figure 8. That is, when the control mode of the primary control chip is constant current loop control mode, the CCMode signal is at a high level, and when the control mode of the primary control chip is constant voltage loop control mode, the CCMode signal is at a low level. The constant voltage mode signal of the primary control chip may be the signal of the constant voltage loop control mode adopted by the primary control chip. For example, when the control mode of the primary control chip is constant current loop control mode, the constant voltage mode signal may be at a low level, and when the control mode of the primary control chip is constant voltage loop control mode, the constant voltage mode signal may be at a high level.

Accordingly, the reference voltage adjustment circuit 10 in this embodiment can control the reference voltage for peak load detection adjusted by the peak load detection module 20 by generating a reference voltage control signal based on a constant current mode signal and/or a constant voltage mode signal.

For example, if the reference voltage for peak load detection includes both a peak load reference voltage and an overcurrent protection reference voltage, the reference voltage adjustment circuit 10 can be used to generate a first control signal corresponding to the peak load reference voltage when the primary control chip is in constant current loop control mode, and a second control signal corresponding to the overcurrent protection reference voltage when the primary control chip is in constant voltage loop control mode and the reference voltage is the peak load reference voltage, and the reference voltage control signal includes both the first and second control signals. As shown in Figure 3, the constant current point corresponding to the overcurrent protection reference voltage (VrefCCL) is the OCP point, and the constant current point for the peak load reference voltage (VrefCCH) is the Pk Load point. 1) When the load is lower than the OCP point, i.e., below point A, the output current of the PSR device is below the OCP point determined by VrefCCL, and it operates in the CV section. That is, the PSR device control mode is CV Mode (constant voltage loop control mode).

2) When the load is higher than the OCP point and lower than the Pk Load point, that is, when the load is between point A and point B, the load capacitance determined by VrefCCL cannot move this load, and the peak load detection module 20 switches the control mode of the primary side control chip from CV Mode to CC Mode (i.e., constant current loop control mode). At this time, the reference voltage adjustment circuit 10 controls the peak load detection module 20 to switch the reference voltage from VrefCCL to VrefCCH. In other words, the load capacitance of the PSR device is raised from the OCP point to the Pk Load point. After switching to VrefCCH, the PSR device can move the load between A and B. The peak load detection module 20 switches the control mode of the primary side control chip from CC Mode to CV Mode. At this time, the reference voltage adjustment circuit 10 controls the peak load detection module 20 to switch the reference voltage from VrefCCH to VrefCCL, that is, it can reduce the load capacity of the PSR system from the Pk Load point to the OCP point. After this, the above process is repeated, and the reference voltage (VrefCC) that determines the constant current point is switched between VrefCCH and VrefCCL.

3) If the load is higher than the Pk Load point, i.e., if the load is between points B and C, the load capacitance of the PSR device switches to the Pk Load point determined by VrefCCH. At this time, the PSR device cannot move the load, VrefCC stabilizes at VrefCCH, and the control mode of the primary control chip remains CC Mode.

4) If the load continues to change and falls below the Pk Load point, i.e., if the load is between point C and point D, repeat the process in 2) above.

5) If the load continues to change and falls below the OCP point, i.e., if the load is lower than point D, VrefCC will stabilize at VrefCCL, and the control mode of the primary control chip will remain CV Mode.

Accordingly, the specific circuit structure of the reference voltage adjustment circuit 10 in this embodiment can be set by the designer based on the practical scenario and user needs. When the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage, the reference voltage adjustment circuit 10 can include a constant current adjustment circuit. The constant current adjustment circuit can be used to generate a first control signal after the primary side control chip enters constant current loop control mode based on a constant current mode start signal and a constant current mode end signal corresponding to the constant current mode signal, and to generate a second control signal after the reference voltage is the peak load reference voltage and the primary side control chip has ended constant current loop control mode. Of these, the constant current mode start signal corresponding to the constant current mode signal may be a pulse signal at the start of constant current loop control mode (CC Mode), as shown by the CCMode_beginpulse signal in Figure 8, and the constant current mode end signal corresponding to the constant current mode signal may be a pulse signal at the end of constant current loop control mode, as shown by the CCMode_endpulse signal in Figure 8. In response to this, the reference voltage adjustment circuit 10 may further include a signal conversion circuit that converts the constant current mode signal of the primary control chip into a constant current mode start signal and a constant current mode end signal, and generates a reference voltage control signal based on the constant current mode start signal and constant current mode end signal output by the signal conversion circuit.

Specifically, as shown in Figure 5, when the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage, the constant current adjustment circuit described above may include a first AND gate element 11 (and2, i.e., two input terminal AND gate elements), a first RS flip-flop 12 (an RS flip-flop composed of two Nor2, i.e., two input terminal Nor gate elements), a D flip-flop 13 (DFF), and a paraphase amplifier 14. Of these, the first input terminal of the first AND gate element 11 is connected to the output terminal of the constant current mode termination signal, the second input terminal of the first AND gate element 11 is connected to the Q output terminal of the D flip-flop 13, the output terminal of the first AND gate element 11 is connected to the R input terminal of the first RS flip-flop 12, the S input terminal of the first RS flip-flop 12 is connected to the output terminal of the constant current mode start signal, the Q output terminal of the first RS flip-flop 12 is connected to the D input terminal of the D flip-flop 13, and the clock input terminal (CLK) of the D flip-flop 13 is connected to the turn of the cycle of the primary side control chip. The Q output terminal of the D flip-flop 13 is connected to the output terminal of the turn-on pulse signal (PFM) that drives the ON state, the Q output terminal of the D flip-flop 13 is connected to the input terminal of the paraphase amplifier 14, and the output terminal of the paraphase amplifier 14 is connected to the input terminal of the reference voltage control signal of the peak load detection module 20. The turn-on pulse signal that drives the turn-on of the primary control chip cycle may be the turn-on signal that drives each cycle of the primary control chip, and the reset input terminal (reset) of the D flip-flop 13 can be connected to the output terminal of the corresponding reset signal (Reset).

In response to this, by connecting the second input terminal of the first AND gate element 11 to the Q output terminal of the D flip-flop 13, the constant current adjustment circuit can be used to generate a reference voltage control signal based on the input constant current mode start signal and constant current mode end signal. Furthermore, by connecting the second input terminal of the first AND gate element 11 to the input terminal of the peak load reference voltage usage status signal, the constant current adjustment circuit can also be used to generate a reference voltage control signal based on the input constant current mode start signal, constant current mode end signal, and peak load reference voltage usage status signal. No limitations are imposed in this embodiment.

Accordingly, this embodiment does not limit the specific circuit configuration of the first RS flip-flop 12. As shown in Figure 5, the first RS flip-flop 12 may include a first Noah gate element and a second Noah gate element. The first input terminal of the first Noah gate element is connected to the output terminal of the constant current mode start signal; the second input terminal of the first Noah gate element is connected to the output terminal of the second Noah gate element; the output terminal of the first Noah gate element is connected to the first input terminal of the second Noah gate element; the second input terminal of the second Noah gate element is connected to the output terminal of the first AND gate element 11; and the common terminal connecting the output terminal of the second Noah gate element and the second input terminal of the first Noah gate element is connected to the D input terminal of the D flip-flop 13 as the Q output terminal of the first RS flip-flop 12.

For example, if the reference voltage for peak load detection includes a peak load reference voltage, an overcurrent protection reference voltage, and a medium-low reference voltage and a medium-high reference voltage between the overcurrent protection reference voltage and the peak load reference voltage, the reference voltage control signal may include a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the medium-high reference voltage, and a fourth control signal corresponding to the medium-low reference voltage. Specifically, the reference voltage adjustment circuit 10 generates the fourth control signal based on a constant current mode signal and/or a constant voltage mode signal when the reference voltage is an overcurrent protection reference voltage and the primary side control chip is in constant current loop control mode. It can be used to generate a second control signal when the reference voltage is a medium-low reference voltage and the primary control chip is in constant voltage loop control mode; a third control signal when the reference voltage is a medium-low reference voltage and the primary control chip is in constant current loop control mode; a fourth control signal when the reference voltage is a medium-high reference voltage and the primary control chip is in constant voltage loop control mode; a first control signal when the reference voltage is a medium-high reference voltage and the primary control chip is in constant current loop control mode; and a third control signal when the reference voltage is a peak load reference voltage and the primary control chip is in constant voltage loop control mode.

As shown in Figure 4, the constant current point for the overcurrent protection reference voltage (VrefCCL) is point OCP, the constant current point corresponding to the peak load reference voltage (VrefCCH) is point Pk Load, the constant current point corresponding to the medium-low reference voltage (VrefCCMLow) is point B, and the constant current point corresponding to the medium-high reference voltage (VrefCCMHigh) is point C. The reference voltage for peak load detection (VrefCC) can be switched between four positions: VrefCCL, VrefCCMLow, VrefCCMHigh, and VrefCCH. 1) VrefCCL → VrefCCMLow: When a CC Mode trigger is detected while in the VrefCCL state, VrefCC can be switched from VrefCCL to VrefCCMLow. 2) VrefCCMLow → VrefCCL: When the end of CC Mode (i.e., the trigger for CV Mode) is detected while in the VrefCCMLow state, it means that the PSR device can move the load at that time while in the VrefCCMLow state, so VrefCC switches from VrefCCMLow to VrefCCL. 3) VrefCCMLow → VrefCCMHigh: When the trigger for CC Mode is detected while in the VrefCCMLow state, it means that VrefCCMLow is insufficient to move the load at that time, so VrefCC switches from VrefCCMLow to VrefCCMHigh. 4) VrefCCMHigh → VrefCCMLow: When the end of CC Mode is detected while in the VrefCCMHigh state, it means that VrefCCMHigh can move the load at that time, so VrefCC can be switched from VrefCCMHigh to VrefCCMLow. 5) VrefCCMHigh → VrefCCH: When the trigger for CC Mode is detected while in the VrefCCMHigh state, it means that VrefCCMHigh is insufficient to move the load at that time, so VrefCC can be switched from VrefCCMHigh to VrefCCH. 6) VrefCCH → VrefCCMHigh: When the end of CC Mode is detected while in the VrefCCH state, VrefCCH can move the load at that time, so VrefCC can be switched from VrefCCH to VrefCCMHigh. 7) When the end of CV Mode is detected while in the VrefCCL state, VrefCCL can move the load at that time, so VrefCC can maintain its VrefCCL state.

In response to this, when the reference voltage includes an overcurrent protection reference voltage, a peak load reference voltage, a medium-low reference voltage, and a medium-high reference voltage, the specific circuit structure of the reference voltage adjustment circuit 10 can be set using a method similar to that of the reference voltage adjustment circuit 10 in which the reference voltage includes the two positions of overcurrent protection reference voltage and peak load reference voltage. This embodiment does not impose any limitations on this.

Furthermore, the peak current load control circuit provided in this embodiment includes a timing circuit for restarting the charger system by counting the peak load duration and/or overcurrent protection duration, outputting a peak load protection restart control signal when the peak load duration reaches a first threshold, and/or outputting an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold. The peak load duration may be greater than or equal to the duration of the constant current point (such as the Pk Load point) where the current required by the load corresponds to the peak load reference voltage, and the overcurrent protection duration may be greater than or equal to the duration of the constant current point (such as the OCP point) where the current required by the load corresponds to the overcurrent protection reference voltage.

In response to this, the timing circuit can be used to trigger a peak load protection restart in the PSR device by counting the peak load duration and overcurrent protection duration, and by outputting a peak load protection restart control signal when the peak load duration reaches a first threshold, and by outputting an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold, thereby triggering an OCP protection restart in the PSR device.

For example, the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage. The timing circuit can be used to count the peak load duration and the overcurrent protection duration based on the constant current mode signal of the primary side control chip, and to output a peak load protection restart control signal when the peak load duration reaches a first threshold, and to output an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold. Of these, the peak load duration is the duration when the reference voltage is the peak load reference voltage and the primary side control chip is in constant current loop control mode, and overcurrent The protection duration is the duration when the reference voltage is the overcurrent protection reference voltage and the primary control chip is in constant current loop control mode, or when the reference voltage is the peak load reference voltage. As shown in Figure 3, the timing circuit starts counting the overcurrent protection duration at point A (i.e., OCP count) and ends counting the overcurrent protection duration at point D. If the overcurrent protection duration is greater than or equal to a second threshold (e.g., 1.5 s), it triggers an OCP protection restart of the PSR device. If the overcurrent protection duration falls below the second threshold, the PSR device can continue to operate. The timing circuit also starts counting the peak load duration at point B (i.e., PK Load count) and ends counting the peak load duration at point C. If the peak load duration is greater than or equal to a first threshold (e.g., 150 ms), it triggers a peak load protection restart of the PSR device. If the peak load duration falls below the first threshold, the PSR device can continue to operate. In other words, as shown by the output current (Output Current) on the left side of Figure 3, when the output current of the PSR device exceeds the OCP point, the OCP count starts. If the PK Load point is reached during this time, another PK Load count starts. However, if the duration of the PK Load count has not reached 150 ms, the peak load protection restart cannot be triggered. At this point, the OCP count is still ongoing, and after reaching 1.5 seconds, the OPC protection is triggered. As shown by the output current on the right side of Figure 3, when the output current of the PSR device exceeds the OCP point, the OCP count starts. If the PK Load point is reached during this time, another PK Load count starts. If the duration of the PK Load count reaches 150 ms, the peak load protection restart is triggered. At this point, the OCP count simultaneously ends, and the duration is less than 1.5 seconds.

For example, if the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the medium-high reference voltage, and a fourth control signal corresponding to the medium-low reference voltage, the timing circuit can specifically be used to count the peak load duration and the overcurrent protection duration based on the constant current mode signal of the primary side control chip, and to output a peak load protection restart control signal when the peak load duration reaches a first threshold, and to output an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold, and the peak load duration is the duration when the reference voltage is the peak load reference voltage and the primary side control chip is in constant current loop control mode. The duration of overcurrent protection is the duration when the reference voltage is the overcurrent protection reference voltage and the primary control chip is in constant current loop control mode, or when the reference voltage is a medium-low reference voltage, medium-high reference voltage, or peak load reference voltage. As shown in Figure 4, the timing circuit starts counting the overcurrent protection duration at point A (i.e., OCP count) and ends counting the overcurrent protection duration at point F. If the overcurrent protection duration is greater than or equal to a second threshold (e.g., 1.5 s), it triggers an OCP protection restart of the PSR device. If the overcurrent protection duration falls below the second threshold, the PSR device can continue to operate. The timing circuit also starts counting the peak load duration at point D (i.e., PK Load count) and ends counting the peak load duration at point E. If the peak load duration is greater than or equal to a first threshold (e.g., 150 ms), it triggers a peak load protection restart of the PSR device. If the peak load duration falls below the first threshold, the PSR device can continue to operate.

In other words, as shown in Figure 4, at point A, the load exceeds the OCP point, VrefCCL becomes VrefCCMLow, and the Tocp (i.e., overcurrent protection period) count begins. In the A-B section, VrefCC switches between VrefCCL and VrefCCMLow to detect the load. In the B-C section, VrefCC switches between VrefCCMLow and VrefCCMHigh to detect the load. In the C-D section, VrefCC first switches between VrefCCMHigh and VrefCCH, then between VrefCCMLow and VrefCCMHigh, and finally between VrefCCMHigh and VrefCCH. The system switches to detect the load. In the D-E section, Tpeakload (i.e., peak load duration) is counted within this section. In the E-F section, VrefCC first switches between VrefCCH and VrefCCMHigh. After the load falls below the constant current point corresponding to VrefCCMHigh, it switches between VrefCCMHigh and VrefCCMLow. After the load falls below the constant current point corresponding to VrefCCMLow, it switches between VrefCCMLow and VrefCCL. After the load falls below the OCP point, VrefCC stabilizes at VrefCCL and exits the TCP count.

In response to this, the specific circuit structure of the timing circuit described above can be set by the designer based on the practical scenario and user requirements. For example, the timing circuit may include a peak load timing circuit and an overcurrent protection timing circuit. The peak load timing circuit can be used to count the peak load duration and output a peak load protection restart control signal when the peak load duration reaches a first threshold. The overcurrent protection timing circuit can be used to count the overcurrent protection duration and output an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold.

Specifically, when the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage, as shown in Figure 6, the overcurrent protection timing circuit includes a second AND gate element 21 (AND2), a second RS flip-flop 22 (two NOR2), and a first timer 23 (Time It may include Counter 1), the first input terminal of the second AND gate element 21 is connected to the output terminal of the reference voltage control signal of the reference voltage adjustment circuit 10 (such as the output terminal of the paraphase amplifier 14 in Figure 5), the second input terminal of the second AND gate element 21 is connected to the output terminal of the constant current mode termination delay signal (CV_EN_12Pulse) corresponding to the constant current mode signal, the output terminal of the second AND gate element 21 is connected to the R input of the second RS flip-flop 22, the S input terminal of the second RS flip-flop 22 is connected to the output terminal of the constant current mode start signal corresponding to the constant current mode signal, and the Q output terminal of the second RS flip-flop 22 is connected to the first timer 23 The enable terminal is connected, and the output terminal of the first timer 23 is used as the output terminal of the overcurrent protection timing circuit to output a peak load protection restart control signal (Tocp_pro) when the duration of the received enable signal reaches a second threshold. The turn-on delay signal is a pulse signal that follows a predetermined number of turn-on pulse signals after the end of the constant current mode control mode, for example, CV_EN_12Pulse in Figure 8, that is, a pulse signal that follows a continuous count of 12 turn-on pulse signals (i.e., CV mode switching pulse signals, for example, the PFM signal in Figure 5) after the end of CCMode.

Specifically, when the reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage, the peak load timing circuit may include a third AND gate element 31 (and2) and a second timer 32 (Time Counter2), as shown in Figure 7. The first input terminal of the third AND gate element 31 is connected to the output terminal of the constant current mode signal, the second input terminal of the third AND gate element 31 is connected to the output terminal of the paraphase signal corresponding to the reference voltage control signal (such as the input terminal of the paraphase amplifier 14 in Figure 5), and the output terminal of the third AND gate element 31 is connected to the enable terminal of the second timer 32. The output terminal of the second timer 32 is used as the output terminal of the peak load timing circuit to output a peak load protection restart control signal (Tpeakload_pro) when the duration of the received enable signal reaches a first threshold.

In this embodiment, the present invention controls the switching between the constant current loop control mode and the constant voltage loop control mode of the primary side control chip by controlling the reference voltage for peak load detection of the primary side control chip based on the constant current mode signal and/or constant voltage mode signal of the primary side control chip through the installation of the reference voltage adjustment circuit 10. This prevents load-shatter restarts that occur when the output voltage of the primary side regulation charger drops sharply due to a sudden increase in output voltage, thereby improving the stability of the output voltage when the primary side regulation charger detects a peak current load.

Each embodiment in this specification is described in a gradual manner, but each embodiment focuses on explaining the differences from other embodiments, and parts that are identical or similar between embodiments can be referenced to one another.

As described above, the peak current load control circuit provided by the present invention has been introduced in detail. In this text, the principles and embodiments of the present invention are described by applying specific examples, but the above description of embodiments is merely to help in understanding the method and central concept of the present invention. Therefore, it should be noted that those skilled in the art may make some improvements and modifications to the present invention, provided that they do not depart from the principles of the present invention, but such improvements and modifications are also included within the scope of protection of the claims of the present invention.

Claims (9)

A reference voltage adjustment circuit for generating a reference voltage control signal based on the constant current mode signal and/or constant voltage mode signal of the primary side control chip,
A peak load detection module for adjusting a reference voltage for peak load detection based on the reference voltage control signal, performing peak load detection on the primary side control chip based on the reference voltage, and adjusting the control mode of the primary side control chip, wherein the control mode includes a constant current loop control mode and a constant voltage loop control mode, and the reference voltage includes an overcurrent protection reference voltage and a peak load reference voltage, and the peak load reference voltage is k times the overcurrent protection reference voltage (where k is greater than 1) ,
Specifically, the reference voltage adjustment circuit is used to generate a first control signal corresponding to the peak load reference voltage when the primary side control chip is in the constant current loop control mode, based on the constant current mode signal and/or the constant voltage mode signal, and to generate a second control signal corresponding to the overcurrent protection reference voltage when the primary side control chip is in the constant voltage loop control mode and the reference voltage is the peak load reference voltage, wherein the reference voltage control signal includes the first control signal and the second control signal.
Peak current load control circuit. The aforementioned reference voltage adjustment circuit
The constant current adjustment circuit is characterized by including a constant current adjustment circuit that generates the first control signal after the primary side control chip enters the constant current loop control mode based on the constant current mode start signal and constant current mode end signal corresponding to the constant current mode signal, and generates the second control signal after the reference voltage is the peak load reference voltage and the primary side control chip has ended the constant current loop control mode, wherein the reference voltage is the peak load reference voltage and the primary side control chip has ended the constant current loop control mode.
The peak current load control circuit according to claim 1 . The constant current adjustment circuit includes a first AND gate element, a first RS flip-flop, a D flip-flop, and a paraphase amplifier.
The first input terminal of the first AND gate element is connected to the output terminal of the constant current mode termination signal; the second input terminal of the first AND gate element is connected to the Q output terminal of the D flip-flop; the output terminal of the first AND gate element is connected to the R input terminal of the first RS flip-flop; the S input terminal of the first RS flip-flop is connected to the output terminal of the constant current mode start signal; the Q output terminal of the first RS flip-flop is connected to the D input terminal of the D flip-flop; the clock input terminal of the D flip-flop is connected to the output terminal of the turn-on pulse signal that drives the cycle turn-on of the primary side control chip; the Q output terminal of the D flip-flop is connected to the input terminal of the paraphase amplifier; and the output terminal of the paraphase amplifier is connected to the input terminal of the reference voltage control signal of the peak load detection module.
The peak current load control circuit according to claim 2 . The first RS flip-flop includes a first Noa gate element and a second Noa gate element.
The first input terminal of the first Noah gate element is connected to the output terminal of the constant current mode start signal, the second input terminal of the first Noah gate element is connected to the output terminal of the second Noah gate element, the output terminal of the first Noah gate element is connected to the first input terminal of the second Noah gate element, the second input terminal of the second Noah gate element is connected to the output terminal of the first AND gate element, and the common terminal connecting the output terminal of the second Noah gate element and the second input terminal of the first Noah gate element is connected to the D input terminal of the D flip-flop as the Q output terminal of the first RS flip-flop.
The peak current load control circuit according to claim 3 . The reference voltage control signal includes a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the medium-high reference voltage, and a fourth control signal corresponding to the medium-low reference voltage, of which the peak load reference voltage is greater than the medium-high reference voltage, greater than the medium-low reference voltage, and greater than the overcurrent protection reference voltage.
In response to this, the reference voltage adjustment circuit is specifically used to generate the fourth control signal when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode, based on the constant current mode signal and/or the constant voltage mode signal; generate the second control signal when the reference voltage is the medium-low reference voltage and the primary side control chip is in the constant voltage loop control mode; generate the third control signal when the reference voltage is the medium-low reference voltage and the primary side control chip is in the constant current loop control mode; generate the fourth control signal when the reference voltage is the medium-high reference voltage and the primary side control chip is in the constant voltage loop control mode; generate the first control signal when the reference voltage is the medium-high reference voltage and the primary side control chip is in the constant current loop control mode; and generate the third control signal when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant voltage loop control mode.
The peak current load control circuit according to claim 1. The system further includes a timing circuit that counts the peak load duration and/or the overcurrent protection duration, outputs a peak load protection restart control signal when the peak load duration reaches a first threshold, and/or outputs an overcurrent protection restart control signal when the overcurrent protection duration reaches a second threshold,
The timing circuit is characterized by outputting the peak load protection restart control signal and/or the overcurrent protection restart control signal in order to restart the charger system.
A peak current load control circuit according to any one of claims 1 to 5 . The reference voltage control signal includes a first control signal corresponding to the peak load reference voltage and a second control signal corresponding to the overcurrent protection reference voltage, and the timing circuit is used to count the peak load duration and the overcurrent protection duration based on the constant current mode signal of the primary side control chip, to output the peak load protection restart control signal when the peak load duration reaches the first threshold, and to output the overcurrent protection restart control signal when the overcurrent protection duration reaches the second threshold, wherein the peak load duration is the duration when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant current loop control mode, and the overcurrent protection duration is the duration when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode, or when the reference voltage is the peak load reference voltage, as described in claim 6 . The timing circuit includes a peak load timing circuit and an overcurrent protection timing circuit, of which,
The overcurrent protection timing circuit includes a second AND gate element, a second RS flip-flop, and a first timer, wherein the first input terminal of the second AND gate element is connected to the output terminal of the reference voltage control signal of the reference voltage adjustment circuit, the second input terminal of the second AND gate element is connected to the output terminal of the constant current mode termination delay signal corresponding to the constant current mode signal, the output terminal of the second AND gate element is connected to the R input terminal of the second RS flip-flop, the S input terminal of the second RS flip-flop is connected to the output terminal of the constant current mode start signal corresponding to the constant current mode signal, the Q output terminal of the second RS flip-flop is connected to the enable terminal of the first timer, and the output terminal of the first timer is used as the output terminal of the overcurrent protection timing circuit to output the overcurrent protection restart control signal when the duration of the received enable signal reaches the second threshold, and the turn-on delay signal is a pulse signal that follows a predetermined number of turn-on pulse signals after the termination of the constant current mode control mode.
The peak load timing circuit includes a third AND gate element and a second timer, wherein the first input terminal of the third AND gate element is connected to the output terminal of the constant current mode signal, the second input terminal of the third AND gate element is connected to the output terminal of the paraphase signal corresponding to the reference voltage control signal, the output terminal of the third AND gate element is connected to the enable terminal of the second timer, and the output terminal of the second timer is used as the output terminal of the peak load timing circuit to output the peak load protection restart control signal when the duration of the received enable signal reaches the first threshold, characterized in that
The peak current load control circuit according to claim 7 . The reference voltage control signal includes a first control signal corresponding to the peak load reference voltage, a second control signal corresponding to the overcurrent protection reference voltage, a third control signal corresponding to the medium-high reference voltage, and a fourth control signal corresponding to the medium-low reference voltage, of which the peak load reference voltage is greater than the medium-high reference voltage, greater than the medium-low reference voltage, and greater than the overcurrent protection reference voltage.
In response, the timing circuit is used to count the peak load duration and the overcurrent protection duration based on the constant current mode signal of the primary side control chip, and to output the peak load protection restart control signal when the peak load duration reaches the first threshold, and to output the overcurrent protection restart control signal when the overcurrent protection duration reaches the second threshold, wherein the peak load duration is the duration when the reference voltage is the peak load reference voltage and the primary side control chip is in the constant current loop control mode, and the overcurrent protection duration is the duration when the reference voltage is the overcurrent protection reference voltage and the primary side control chip is in the constant current loop control mode, or when the reference voltage is the medium-low reference voltage, the medium-high reference voltage, or the peak load reference voltage.
The peak current load control circuit according to claim 6 .