JP7779396B2 - Information processing device and packet processing method - Google Patents

Description

The present invention relates to an information processing device and a packet processing method.

There is a method (NFV: Network Function Virtualization) in which the functions of network equipment are implemented as software (VM: Virtual machine) on a general-purpose server virtualization platform.

NFV technology is already being used in a variety of services because it allows for the consolidation of physical equipment, thereby reducing capital costs.

For example, NFV allows a general-purpose server to function as a virtual gateway, which is a virtualized gateway that connects different networks.

In NFV, network packets are processed by the CPU, but because the CPU's processing performance is low, when traffic volume increases, a single server cannot accommodate it all, and multiple servers must be prepared. This increases equipment costs and power consumption.

Therefore, a technology has been proposed to improve transfer performance by offloading processing that the CPU is not good at to a hardware (H/W) accelerator.

Examples of offloading methods using existing technology include:
A method in which all processing is offloaded to a hardware accelerator (hereinafter referred to as "method 1")
(2) A method in which software and hardware accelerators are integrated inline on a general-purpose server (hereinafter referred to as "Method 2").
etc.

KORONA, Mateusz, et al., "FPGA implementation of IPsec protocol suite for multigigabit networks", In: 2017 International Conference on Systems, Signals and Image Processing (IWSSIP). IEEE, 2017. p. 1-5 LI, Xiaoyao, et al., "DHL: Enabling flexible software network functions with FPGA acceleration", In: 2018 IEEE 38th International Conference on Distributed Computing Systems (ICDCS). IEEE, 2018. p. 1-11 "Advanced Networking and Security for the Most Demanding Cloud and Data Center Workloads", [online], [Retrieved June 22, 2022], Internet <URL: https://nvdam.widen.net/s/qpszhmhpzt/networking-overal-dpu-datasheet-connectx-6-dx-smartnic-1991450>

Method 1 is high-performance (efficient) because all processing is performed by hardware, but it has the disadvantage that it cannot be equipped with many functions due to strict resource limitations on hardware (for example, it cannot have multiple functions such as ARP or redundancy).

Method 2 appears to be efficient because only high-load processing is handled by the hardware accelerator, but it has the disadvantage that processing speed depends on the software because all packets pass through the software once.

The present invention has been made in consideration of the above points and aims to improve the balance between efficiency and flexibility in packet processing.

Therefore, in order to solve the above problem, an information processing device has an integrated circuit that receives packets, and the integrated circuit includes a distribution unit that is configured to determine whether or not to have software execute processing on the packet based on the source and destination of the packet, and to forward the packet to the software if the software is to execute the processing, a processing unit that is configured to execute processing on the packet if the distribution unit determines not to have the software execute the processing, and a forwarding unit that is configured to forward the packet processed by the processing unit, and the IP addresses and MAC addresses of the integrated circuit and the software are different, and the distribution unit is configured to rewrite the destination MAC address of the packet to the MAC address of the software when the software is to execute the processing .

It improves the balance between efficiency and flexibility in packet processing.

FIG. 1 is a diagram illustrating an example of a network configuration according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a hardware configuration of a general-purpose server 10 according to an embodiment of the present invention. FIG. 1 is a diagram for explaining an outline of the configuration of a general-purpose server 10 as a network device. FIG. 10 is a diagram for explaining a modified example of the general configuration of a general-purpose server 10 as a network device. FIG. 1 is a diagram for explaining a first embodiment (connection method 1). FIG. 10 is a diagram showing an example of a header of a packet transferred by an opposing device 20-1 in the first embodiment. FIG. 4 is a diagram illustrating an example of a configuration of a matching table according to the first embodiment. FIG. 10 is a diagram illustrating an example of a received packet after the destination MAC address has been rewritten. FIG. 10 is a diagram for explaining a second embodiment (connection method 2). FIG. 11 is a diagram showing an example of a header of a packet transferred by an opposing device 20-1 in the second embodiment. FIG. 11 is a diagram illustrating an example of a configuration of a matching table according to the second embodiment. FIG. 13 is a sequence diagram illustrating an example of a processing procedure executed for ARP (ARP-2) when the H/W accelerator 12 is determined as a destination of a received packet in the fourth embodiment. FIG. 13 is a sequence diagram illustrating an example of a processing procedure executed for ARP (ARP-2) when the virtual GW 11 is determined as a destination of a received packet in the fourth embodiment. FIG. 13 is a diagram illustrating an example of a functional configuration of a virtual GW 11 according to a fifth embodiment. FIG. 13 is a sequence diagram illustrating an example of a processing procedure executed for ARP (ARP-3) when the H/W accelerator 12 is determined as a destination of a received packet in the fifth embodiment. FIG. 20 is a sequence diagram illustrating an example of a processing procedure executed for ARP (ARP-3) when the virtual GW 11 is determined as a destination of a received packet in the fifth embodiment.

The following describes an embodiment of the present invention based on the drawings. Figure 1 shows an example of a network configuration in an embodiment of the present invention. In Figure 1, the general-purpose server 10 is one or more general-purpose computers that function as a network device (a virtual gateway) that connects the different networks N1 and N2.

Terminals 30-1 and 30-2 are devices that serve as the end points (starting point or ending point) of the communication, and from the perspective of the general-purpose server 10, one of them is the source of the packet and the other is the destination of the packet. However, the source and destination switch roles as the communication progresses. In this embodiment, we will explain the case where terminal 30-1 is the source and terminal 30-2 is the destination.

The opposing devices 20-1 and 20-2 are nodes adjacent to the general-purpose server 10 in network N1 or network N2. For example, the opposing devices 20-1 and 20-2 are L3 routers.

Figure 2 is a diagram showing an example of the hardware configuration of a general-purpose server 10 in an embodiment of the present invention. The general-purpose server 10 in Figure 2 has a drive device 100, an auxiliary storage device 102, a memory device 103, a CPU 104, an interface device 105, and a H/W accelerator 12, all of which are interconnected by a bus B.

The program that realizes processing on the general-purpose server 10 is provided by a recording medium 101 such as a CD-ROM. When the recording medium 101 storing the program is inserted into the drive device 100, the program is installed from the recording medium 101 to the auxiliary storage device 102 via the drive device 100. However, the program does not necessarily have to be installed from the recording medium 101; it may be downloaded from another computer via a network. The auxiliary storage device 102 stores the installed program as well as necessary files, data, etc.

When an instruction to start a program is received, the memory device 103 reads and stores the program from the auxiliary storage device 102. The CPU 104 executes functions related to the general-purpose server 10 in accordance with the program stored in the memory device 103. The interface device 105 is used as an interface for connecting to a network.

The H/W accelerator 12 is a hardware accelerator (integrated circuit) to which some of the processing executed by the CPU 104 is offloaded. For example, an FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit) may be used as the H/W accelerator 12.

Figure 3 is a diagram illustrating the general configuration of a general-purpose server 10 as a network device. As shown in Figure 3, a H/W accelerator 12 and one or more virtual GWs 11 enable the general-purpose device to function as a network device.

The H/W accelerator 12 is as described in Figure 2.

The virtual GW11 is a virtual gateway implemented by software (programs) using NFV (Network Functions Virtualization) technology, and is implemented by the CPU 104 executing one or more programs installed on the general-purpose server 10. Figure 3 shows two virtual GW11s, virtual GW11-1 and virtual GW11-2 (hereinafter referred to as "virtual GW11" when not distinguishing between them), but there may be one virtual GW11, or three or more virtual GW11s.

In Figure 3, the H/W accelerator 12 and each virtual GW 11 are connected by a virtual L2 bridge and are capable of communication.

As shown in FIG. 3, the H/W accelerator 12 has a distribution unit 121, a B processing unit 122, a routing unit 123, an ARP processing unit 124, an ARP table 125, and ports 126-1 and 126-2. Each of these units is realized by a circuit that constitutes the H/W accelerator 12. Port 126-1 is a port connected to the opposing device 20-1. Port 126-2 is a port connected to the opposing device 20-2.

The distribution unit 121 performs processing to distribute packets (hereinafter referred to as "received packets") from the opposing device 20-1 received by port 126-1 to the H/W accelerator 12 or the virtual GW 11.

The B processing unit 122 performs processing offloaded to the H/W accelerator 12 (hereinafter referred to as "B processing") on received packets assigned to the H/W accelerator 12.

The routing unit 123 routes received packets assigned to the H/W accelerator 12.

The ARP processing unit 124 performs ARP-based processing (processing to obtain a MAC address from an IP address) on received packets assigned to the H/W accelerator 12. The ARP table 125 stores IP addresses and MAC addresses in association with each other.

On the other hand, the virtual GW 11 has an A processing unit 111, a routing unit 112, an ARP processing unit 113, an ARP table 114, etc. Since each of these units is included in the virtual GW 11, they are realized by processing in which one or more programs installed on the general-purpose server 10 are executed by the CPU 104.

The A processing unit 111 performs a certain processing (hereinafter referred to as "A processing") different from the B processing on the received packets allocated to the virtual GW 11.

The routing unit 112 performs the same processing (routing) as the routing unit 123 on received packets allocated to the virtual GW 11. The ARP processing unit 113 performs the same processing AR (processing to obtain a MAC address from an IP address) as the ARP processing unit 124 on received packets allocated to the virtual GW 11. The ARP table 114 stores IP addresses and MAC addresses in association with each other.

In this embodiment, it is assumed that either process A or process B is performed on each received packet. Of these, process A is performed by the virtual GW 11, which is software, and process B is offloaded to the H/W accelerator 12, which is hardware. Because hardware can perform processes with higher performance than software, process B may, for example, be a process with a higher priority than process A, or a complex (high-load) process. For example, an example of process A is the process (IKE (Internet Key Exchange)) performed when an IPsec session is established. An example of process B is the encryption and decryption of main signal packets communicated after an IPsec session is established, or the encap and decap of encapsulation headers.

In addition, both the virtual GW 11 and the H/W accelerator 12 have the function of performing the processing required as a gateway (routing, processing based on ARP) for both received packets on which processing A is performed and received packets on which processing B is performed.

As shown in FIG. 3, the H/W accelerator 12 is directly connected to the network. That is, a packet from the opposing device 20 is first received by the H/W accelerator 12. If the packet can be processed by the H/W accelerator 12 (i.e., if processing B should be performed on the packet), the H/W accelerator 12 performs the processing without forwarding the packet to the virtual GW 11. Therefore, packets may be forwarded without passing through the virtual GW 11. As a result, the average processing speed (efficiency) can be improved compared to when packets are processed solely by software. Furthermore, some packets are processed by the virtual GW 11. Because the virtual GW 11 is software, its functionality can be expanded more flexibly than by hardware. As described above, the configuration of this embodiment can improve the balance between efficiency and flexibility in packet processing.

Note that while Figure 3 shows an example in which the virtual GW 11 and H/W accelerator 12 are placed on the same general-purpose server 10, the virtual GW 11 and H/W accelerator 12 may also be placed on different general-purpose servers 10.

Figure 4 is a diagram for explaining a modified example of the general configuration of the general-purpose server 10 as a network device. In Figure 4, parts that are the same as those in Figure 3 are given the same reference numerals and their explanations are omitted.

In Figure 4, the general-purpose server 10 is distributed between general-purpose server 10-1 and general-purpose server 10-2. General-purpose server 10-1 has a H/W accelerator 12. General-purpose server 10-2 has a virtual GW 11. In this case, general-purpose server 10-1 and general-purpose server 10-2 are connected, for example, via a physical L2 bridge rather than a virtual L2 bridge.

The following specific methods will be explained below.
(1) Two connection methods (Connection Method 1 and Connection Method 2) when both the virtual GW 11 and the H/W accelerator 12 have IP addresses
(2) Three ARP table update methods (ARP-1, ARP-2, ARP-3) when both the virtual GW 11 and the H/W accelerator 12 have their own ARP tables
The two connection methods (connection method 1 and connection method 2) in (1) will be described as the first and second embodiments, and the three update methods (ARP-1, ARP-2, ARP-3) in (2) will be described as the third to fifth embodiments.

The configurations shown in Figures 3 and 4 can be applied to any of the embodiments.

Figure 5 is a diagram for explaining the first embodiment (connection method 1). Note that in Figure 5, some of the components described in Figure 3 are omitted for convenience.

In Figure 5, each virtual GW 11 and H/W accelerator 12 has a different IP address and MAC address. In Figure 5, the IP address of virtual GW 11-1 is "IP1" and the MAC address is "MAC1". The IP address of virtual GW 11-2 is "IP2" and the MAC address is "MAC2". The IP address of H/W accelerator 12 is "IP0" and the MAC address is "MAC0".

The default gateway of the opposite device 20-1, which forwards packets from the terminal 30-1 that is the packet forwarding source, is set to "IP0", which is the IP address of the H/W accelerator 12. Therefore, the opposite device 20-1 forwards all packets to the node (H/W accelerator 12) corresponding to IP0. Even if there are multiple virtual GWs 11, the NEXTHOP is always "IP0/MAC0". The header of the packet forwarded by the opposite device 20-1 is as shown in Figure 6.

Figure 6 is a diagram showing an example of the header of a packet forwarded by the opposing device 20-1 in the first embodiment. In Figure 6, the value of DstIP (destination IP address), <forwarding destination>, indicates the IP address of terminal 30-2. The value of SrcIP (source IP address), <forwarding source>, indicates the IP address of terminal 30-1. The value of SrcMAC (source MAC address), <opposing device 1>, indicates the MAC address of the opposing device 20-1. The value of DstMAC (destination MAC address), MAC0, is the MAC address of the H/W accelerator 12.

In this way, in the first embodiment, even if the general-purpose server 10 has multiple virtual GWs 11, the opposing device 20-1 does not need to distinguish between them and simply sends all packets to the IP/MAC on the H/W accelerator 12 side.

In Figure 5, the allocation unit 121 of the H/W accelerator 12 includes a judgment unit 121-1 and a rewrite unit 121-2.

The judgment unit 121-1 compares the received packet with the matching table held by the distribution unit 121 to determine whether the received packet should be distributed to the virtual GW 11 or the H/W accelerator 12 (whether the received packet should be processed by the virtual GW 11).

Figure 7 shows an example of the configuration of a matching table in the first embodiment. As shown in Figure 7, the matching table pre-registers "forwarding destinations" according to the packet's 5-tuple (protocol, SrcMAC (source MAC address), DstMAC (destination MAC address), SrcIP (source IP address), DstIP (destination IP address)).

If the 5-tuple of the received packet matches any record in the matching table, the judgment unit 121-1 determines that the virtual GW 11 corresponding to the MAC address set in the "forwarding destination" of that record is the destination of the received packet (the virtual GW 11 will be made to process the received packet). On the other hand, if the 5-tuple of the received packet does not match any record in the matching table, the judgment unit 121-1 determines that the destination of the received packet is the H/W accelerator 12 (the virtual GW 11 will not be made to process the received packet). However, the comparison with the records in the matching table does not have to be of the entire 5-tuple. For example, it may be determined whether there is a match only for the IP (SrcIP (source IP address) and DstIP (destination IP address)).

The determination unit 121-1 transfers received packets that it determines are destined for the H/W accelerator 12 to the H/W accelerator 12. The received packets are processed by the B processing unit 122 and then routed (transferred) by the routing unit 123.

The determination unit 121-1 inputs received packets that it determines are to be assigned to one of the virtual GWs 11 to the rewrite unit 121-2. The rewrite unit 121-2 rewrites the DstMAC (destination MAC address) of the received packets input from the determination unit 121-1 to the MAC address of the virtual GW 11 that the determination unit 121-1 determined is to be the assignment destination (the "forwarding destination" of the record that the received packet matches in the matching table).

Figure 8 shows an example of a received packet after the destination MAC address has been rewritten. In Figure 8, the DstMAC value in Figure 6 has been rewritten to "MAC1".

The rewrite unit 121-2 forwards the received packet to the virtual GW 11-1 corresponding to the rewritten DstMAC. The received packet undergoes processing A in the virtual GW 11-1 and is routed (forwarded) by the routing unit of the virtual GW 11-1.

Next, we will explain the second embodiment. In the second embodiment, we will explain the differences from the first embodiment. Points that are not specifically mentioned in the second embodiment may be the same as those in the first embodiment.

Figure 9 is a diagram for explaining the second embodiment (connection method 2). In Figure 9, parts that are the same as or correspond to those in Figure 5 are given the same reference numerals.

In Figure 9, the H/W accelerator 12 has the same IP address and MAC address as each virtual GW11. As shown in Figure 9, if there are multiple virtual GW11, the H/W accelerator 12 also has multiple IP addresses and MAC addresses corresponding to each virtual GW11. Specifically, in the example of Figure 9, the IP address and MAC address of virtual GW11-1 are IP1 and MAC1, respectively. The P address and MAC address of virtual GW11-2 are IP2 and MAC2, respectively. The H/W accelerator 12 has IP address and MAC address pairs of IP1 and MAC1, and IP2 and MAC2.

The opposing device 20-1 forwards packets without distinguishing between the virtual GW 11 and the H/W accelerator 12. However, if there are multiple virtual GWs 11, the opposing device 20-1 distinguishes which IP address/MAC address to set as NEXTHOP.

Figure 10 shows an example of the header of a packet forwarded by the opposing device 20-1 in the second embodiment. The packet in Figure 10 is a packet forwarded by the opposing device 20-1 when virtual GW11-1 is set as NEXTHOP.

The determination unit 121-1 compares the received packet with the matching table held by the distribution unit 121 to determine whether the received packet should be distributed to the virtual GW 11 or the H/W accelerator 12.

Figure 11 is a diagram showing an example of the configuration of a matching table in the second embodiment. Compared to the matching table in Figure 7, the matching table shown in Figure 11 does not have an item for "forwarding destination." This is because in the second embodiment, virtual GW11s are distinguished in the header of received packets, so there is no need to register a "forwarding destination."

If the 5-tuple of the received packet matches any record in the matching table, the judgment unit 121-1 judges that the virtual GW 11 corresponding to the DstMAC and DstIP of the received packet is the destination of the received packet. On the other hand, if the 5-tuple of the received packet does not match any record in the matching table, the judgment unit 121-1 judges that the destination of the received packet is the H/W accelerator 12. However, the comparison with the records in the matching table does not have to be for the entire 5-tuple. For example, it may be determined whether there is a match for only the IP (SrcIP (source IP address) and DstIP (destination IP address)).

The determination unit 121-1 transfers received packets that it determines are destined for the H/W accelerator 12 to the H/W accelerator 12. The received packets are processed by the B processing unit 122 and then routed (transferred) by the routing unit 123.

The determination unit 121-1 also forwards a received packet that it determines is assigned to one of the virtual GWs 11 to the virtual GW 11 corresponding to the DstMAC and DstIP of the received packet. That is, in the second embodiment, the header of the received packet is not rewritten. Therefore, in the second embodiment, the distribution unit 121 does not have a rewriting unit 121-2. The received packet shown in Figure 10 is forwarded to the virtual GW 11-1. The received packet undergoes processing A in the virtual GW 11-1, and is routed (forwarded) by the routing unit of the virtual GW 11-1.

Next, we will explain the third embodiment (ARP-1). The third embodiment is suitable when the IP address and MAC address are different between the virtual GW 11 and the H/W accelerator 12 (i.e., when the first embodiment is adopted).

In the third embodiment, the ARP processing unit 113 of the virtual GW 11 and the ARP processing unit 124 of the H/W accelerator 12 each execute ARP independently (separately). For example, the ARP processing unit 113 executes ARP when the MAC address corresponding to the DstIP of a received packet forwarded to the virtual GW 11 is not registered in the ARP table 114, and registers the execution result in the ARP table 114. Furthermore, the ARP processing unit 124 executes ARP when the MAC address corresponding to the DstIP of a received packet to be sorted by the H/W accelerator 12 is not registered in the ARP table 125, and registers the execution result in the ARP table 125.

Next, we will explain the fourth embodiment. The fourth embodiment is suitable when the H/W accelerator 12 has the same IP address and MAC address as the virtual GW 11 (i.e., when the second embodiment is adopted).

In the fourth embodiment, the virtual GW 11 executes ARP independently, and the H/W accelerator 12 performs a snoop on the result of the ARP execution by the virtual GW 11 to update the ARP table 125 of the H/W accelerator 12. Below, the processing procedure executed in the fourth embodiment will be explained separately for the case where the H/W accelerator 12 is determined as the destination of the received packet and the case where the virtual GW 11 is determined as the destination of the received packet.

Figure 12 is a sequence diagram illustrating an example of the processing procedure performed for ARP (ARP-2) when the H/W accelerator 12 is determined to be the destination for a received packet in the fourth embodiment.

When the routing unit 123 of the H/W accelerator 12 determines that a received packet allocated to the H/W accelerator 12 should be forwarded to the opposing device 20-2, the ARP processing unit 124 obtains the MAC address corresponding to the IP address of the opposing device 20-2 from the ARP table 125 (S101).

If an entry corresponding to the IP address is registered in the ARP table 125, the routing unit 123 forwards the received packet to the acquired MAC address (addressed to the opposing device 20-2) (S121).

On the other hand, if an entry corresponding to the IP address is not registered in the ARP table 125 (if the MAC address corresponding to the IP address cannot be identified based on the ARP table 125), steps S102 and S103 are executed.

In step S102, the ARP processing unit 124 of the H/W accelerator 12 sends an ARP execution request, including the received packet, to the virtual GW 11. Next, when the routing unit 112 of the virtual GW 11 determines that the received packet should be forwarded to the opposing device 20-2, the ARP processing unit 113 obtains the MAC address corresponding to the IP address of the opposing device 20-2 from the ARP table 114 (S103).

If an entry corresponding to the IP address is not registered in the ARP table 114, steps S111 to S115 are executed.

In step S111, the ARP processing unit 113 sends an ARP request including the IP address. Subsequently, when the opposing device 20-2 corresponding to the IP address sends an ARP reply including the MAC address of the opposing device 20-2 to the general-purpose server 10, the H/W accelerator 12 receives the ARP reply (S112). The ARP processing unit 124 of the H/W accelerator 12 snoops the ARP reply (obtains the IP address and MAC address correspondence information from the ARP reply) and registers an entry associating the IP address with the MAC address in the ARP table 125 (S113). As a result, the ARP processing unit 124 can identify the MAC address corresponding to the IP address and synchronize the contents of the ARP table 125 with the ARP table 114.

The ARP processing unit 124 also forwards the ARP reply to the virtual GW 11 (S114). The routing unit 123 of the H/W accelerator 12 forwards the received packet to the MAC address (addressed to the opposing device 20-2) (S121). Based on the ARP reply, the ARP processing unit 113 of the virtual GW 11 registers an entry in the ARP table 114 that associates the IP address with the MAC address (S115).

Figure 13 is a sequence diagram illustrating an example of the processing procedure executed for ARP (ARP-2) when the virtual GW11 is determined to be the destination for a received packet in the fourth embodiment. In Figure 13, steps that are the same as or correspond to those in Figure 12 are assigned the same step numbers, and their explanations will be omitted as appropriate.

When the routing unit 112 of the virtual GW11 determines that the received packet allocated to the virtual GW11 should be forwarded to the opposing device 20-2, the ARP processing unit 113 obtains the MAC address corresponding to the IP address of the opposing device 20-2 from the ARP table 114 (S103).

If an entry corresponding to the IP address is registered in the ARP table 114, the routing unit 112 forwards the received packet to the acquired MAC address (addressed to the opposing device 20-2) (S122).

On the other hand, if an entry corresponding to the IP address is not registered in the ARP table 114, steps S111 to S115 are executed, and then step S122 is executed.

Next, we will explain the fifth embodiment. The fifth embodiment is suitable when the H/W accelerator 12 has the same IP address and MAC address as the virtual GW 11 (i.e., when the second embodiment is adopted).

In the fifth embodiment, the virtual GW 11 independently executes ARP to update the ARP table 114 and also updates the ARP table 125 of the H/W accelerator 12.

Figure 14 is a diagram showing an example of the functional configuration of a virtual GW11 in the fifth embodiment. In Figure 14, parts that are the same as those in Figure 3 or Figure 4 are given the same reference numerals, and their explanations are omitted.

In Figure 14, the virtual GW11 further has a setting unit 115. The setting unit 115 registers the ARP result of the virtual GW11 in the ARP table 125 of the H/W accelerator 12.

Below, the processing procedures executed in the fifth embodiment are explained separately for when the H/W accelerator 12 is determined as the destination for the received packet and when the virtual GW 11 is determined as the destination for the received packet.

Figure 15 is a sequence diagram illustrating an example of the processing procedure executed for ARP (ARP-3) when the H/W accelerator 12 is determined to be the destination of a received packet in the fifth embodiment. In Figure 15, the same steps as in Figure 12 are assigned the same step numbers, and their explanations are omitted.

In Figure 15, step S113 (SNOP of ARP reply) is not executed, and step S116 is executed.

In step S116, the setting unit 115 registers the entry registered in the ARP table 114 in step S115 in the ARP table 125 of the H/W accelerator 12. As a result, the contents of the ARP table 125 can be synchronized with the ARP table 114.

Figure 16 is a sequence diagram illustrating an example of the processing procedure executed for ARP (ARP-3) when the virtual GW11 is determined to be the destination for a received packet in the fifth embodiment. In Figure 16, the same steps as those in Figure 13 or Figure 15 are assigned the same step numbers, and their explanations will be omitted as appropriate.

In Figure 16, step S113 (SNooping the ARP reply) is not executed, and step S116 is executed. The processing content of step S116 is as described in Figure 15. As a result, the contents of ARP table 125 can be synchronized with ARP table 114.

In the fourth and fifth embodiments, the cache clear time of the ARP table 125 of the H/W accelerator 12 and the ARP table 114 of the virtual GW 11 is the same. This allows the consistency of the state of each ARP table to be maintained.

In each of the above embodiments, the general-purpose server 10 is an example of an information processing device. The B processing unit 122 is an example of a processing unit. The routing unit 123 is an example of a forwarding unit.

The above describes in detail the embodiments of the present invention, but the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as described in the claims.

10 General-purpose server 11 Virtual GW
12 H/W accelerator 20 Counterpart device 30 Terminal 100 Drive device 101 Recording medium 102 Auxiliary storage device 103 Memory device 104 CPU
105 Interface device 111 A processing unit 112 Routing unit 113 ARP processing unit 114 ARP table 115 Setting unit 121 Distribution unit 121-1 Determination unit 121-2 Rewriting unit 122 B processing unit 123 Routing unit 124 ARP processing unit 125 ARP table 126-1 Port 126-2 Port B Bus

Claims (4)

an integrated circuit for receiving a packet;
The integrated circuit comprises:
a distribution unit configured to determine whether or not to cause software to execute processing on the packet based on the source and destination of the packet, and to transfer the packet to the software if the software is to execute the processing;
a processing unit configured to execute a process on the packet when the allocating unit determines not to cause the software to execute the process;
a forwarding unit configured to forward the packets processed by the processing unit;
Including ,
The integrated circuit and the software have different IP addresses and MAC addresses;
the distribution unit is configured to rewrite the destination MAC address of the packet to the MAC address of the software when causing the software to execute the process.
1. An information processing device comprising: the integrated circuit and the software each have an ARP table;
The integrated circuit comprises:
When the MAC address of the destination of the packet cannot be identified using an ARP table included in the integrated circuit, the integrated circuit is configured to cause the software to execute processing based on ARP to identify the MAC address.
2. The information processing apparatus according to claim 1 , wherein: an integrated circuit receiving the packet,
a distribution procedure of determining whether or not to cause software to execute processing on the packet based on the source and destination of the packet, and transferring the packet to the software if the processing is to be executed by the software;
a processing procedure for executing a process on the packet when the sorting procedure determines that the software should not execute the process;
a forwarding procedure for forwarding the packets processed by the processing procedure;
Run
The integrated circuit and the software have different IP addresses and MAC addresses;
the sorting step rewrites a destination MAC address of the packet to a MAC address of the software when the software is to execute the process;
A packet processing method comprising: the integrated circuit and the software each have an ARP table;
The integrated circuit comprises:
If the MAC address of the destination of the packet cannot be identified using the ARP table of the integrated circuit, the software is caused to execute processing based on ARP to identify the MAC address.
4. The packet processing method according to claim 3 .