JP7608884B2 - Signal processing device, image reading device, information processing device, and program - Google Patents

Description

The present invention relates to a signal processing device, an image reading device, an information processing device, and a program.

Patent document 1 describes a signal processing device, an image reading device, an information processing device, and a program that can cause the downstream circuit to recognize colors corresponding to image information in a predetermined color order, compared to when the input/output means does not output an alternative synchronization signal to the downstream circuit. The AFE outputs image information indicating an image generated for each of a predetermined number of colors together with a first synchronization signal in a color order in which the multiple colors circulate. The input/output circuit acquires image information corresponding to the input first synchronization signal in synchronization with the input of the first synchronization signal output by the AFE, and outputs the acquired image information to the downstream circuit in the acquisition order together with a second synchronization signal generated in response to the input of the first synchronization signal. Then, when the first synchronization signal is not input, an alternative synchronization signal that replaces the second synchronization signal is output to the downstream circuit.

JP 2015-192174 A

However, when synchronizing the color state between a scanner that transfers images line-sequentially and a scanning circuit, if an abnormality occurs in the scanning circuit, the color state becomes out of synchronization, and it may not be possible to return to a normal state.

The present invention aims to provide a technology that can restore a normal state even if an abnormality occurs in the scanning circuit and the color state becomes unsynchronized.

The invention described in claim 1 is a signal processing device that includes a processor that inputs and processes signals generated for each of a plurality of colors and outputting the plurality of colors in a predetermined order and in a circular manner, and the processor executes a program to detect the timing of the start of each color among the plurality of colors and output a synchronization signal, inputs the signal, sequentially updates the color to be captured among the plurality of colors in accordance with the synchronization signal, and interrupts the output of the synchronization signal to interrupt the update if the updated color does not match the color output at the timing when the synchronization signal was output.

The invention described in claim 2 is the signal processing device described in claim 1, in which the processor captures the updated color signal and stores it in the memory unit, and when the output of the synchronization signal is resumed, controls the address at which the captured signal is stored in the memory unit to the address at the timing when the output of the synchronization signal was interrupted.

The invention described in claim 3 is a signal processing device according to either claim 1 or claim 2, in which the multiple colors are composed of a first color, a second color, and a third color, and are output alternately and cyclically in the order of the first color, the second color, and the third color, and when the processor detects the timing of the beginning of the first color, it interrupts the output of the synchronization signal if the updated color is the second color or the third color.

The invention described in claim 4 is the signal processing device described in claim 3, in which the processor interrupts output of the synchronization signal when the timing at which the beginning of the first color is detected is not the beginning of a page.

The invention described in claim 5 is an image reading device that includes a generating means that receives reflected light when a light of each of a plurality of colors is irradiated to an image area including an image on a recording medium in a cyclical color order, and outputs a signal obtained by receiving the light, and a signal processing device described in any one of claims 1 to 4 that processes the signal generated by the generating means.

The invention described in claim 6 is an information processing device including the image reading device described in claim 5 and an image forming device that forms an image based on a signal processed by the signal processing device included in the image reading device.

The invention described in claim 7 is a program that causes a computer to function as detection means that inputs a signal generated for each of a plurality of colors, in which the plurality of colors are output in a predetermined order and in a circular manner, detects the timing of the start of each of the plurality of colors, and outputs a synchronization signal, and update means that inputs the signal and sequentially updates the color to be captured among the plurality of colors in accordance with the synchronization signal from the detection means, and interrupts the output of the synchronization signal if the color updated by the update means does not match the color output at the timing when the synchronization signal is output.

According to the invention described in claims 1, 3-7, even if an abnormality occurs in the scanning circuit and the color state becomes out of sync, the device can be restored to a normal state.

According to the invention described in claim 2, image information in which an abnormality has occurred can be overwritten with correct image information and stored in the memory unit.

1 is an overall configuration diagram of an information processing apparatus according to an embodiment; FIG. 1 is a functional block diagram of an information processing apparatus according to an embodiment. FIG. 1 is a basic configuration diagram (part 1) that is the premise of an image reading unit according to an embodiment. FIG. 2 is a second diagram showing the basic configuration of the image reading unit according to the embodiment; 4 is a timing chart in the basic configuration of the embodiment. FIG. 2 is a configuration diagram (part 1) of an image reading unit according to an embodiment. FIG. 2 is a configuration diagram (part 2) of the image reading unit according to the embodiment. 4 is a timing chart in the configuration of the embodiment. 1 is a process flowchart (part 1) of an embodiment. 13 is a second processing flowchart of the embodiment. 11 is a processing flowchart (part 3) of the embodiment.

The following describes an embodiment of the present invention with reference to the drawings.

First, we will explain the overall configuration of the information processing device according to this embodiment.

Figure 1 shows an external perspective view of an information processing device 100. Similar to the information processing device described in JP 2015-192174 A, the information processing device 100 includes an image reading unit 102, an image forming unit 104, a paper storage unit 106, and a UI (user interface) unit 108.

The image reading unit 102 includes a document table 110 and a discharge table 112. A pair of guide members 114A and 114B are provided on the upper surface of the document table 110. One of the pair of guide members 114A and 114B is manually moved in the width direction of the document placed on the document table 110, and guides the document in the transport direction when the document placed on the document table 110 is transported. The image reading unit 102 takes in the documents placed on the document table 110 one by one, reads the image of the taken document in a line-sequential manner, and acquires image information. The acquired image information is output to a CPU, and then the document is discharged to the discharge table 112. Here, the line-sequential manner refers to a method of color separation by switching between red (R), green (G), and blue (B) light sources every time one line is read in one reading operation by a line sensor.
The paper storage unit 106 stores paper, which is an example of a recording medium, by size, and the image forming unit 104 takes out paper from the paper storage unit 106 and forms an image on the taken-out paper. The image forming unit 104 discharges the paper on which the image has been formed to a discharge tray 116. The image forming method is an electrophotographic method, an inkjet method, or the like.

The UI unit 108 includes a touch panel display 108A for displaying images and a switch 108B. The touch panel display 108A and the switch 108B accept various instructions from a user of the information processing device 100. Examples of various instructions include an instruction to the image reading unit 102 to start reading an image (scan start instruction), and an instruction to the image forming unit 104 to start forming an image. The touch panel display 108A displays various information such as the results of processing executed in response to the accepted instructions and warnings.

The image reading unit 102 includes a housing and a document transport device, and the document transport device has a document tray and a discharge tray. The housing houses the image reading unit main body, and a rectangular opening is formed on the top surface of the housing. The opening is covered by a platen glass on which the document is placed.

The image reading unit main body includes a CIS (contact image sensor), an image processing circuit, and a motor. The CIS and image processing circuit are mounted on a carriage, and the carriage receives the driving force of the motor and moves in the sub-scanning direction, which is the longitudinal direction of the opening.

The CIS includes a first LED (Light Emitting Diode), a second LED, and a third LED. The first LED is an LED having an emission wavelength of red (R), the second LED is an LED having an emission wavelength of green (G), and the third LED is an LED having an emission wavelength of blue (B). The first LED, second LED, and third LED are driven sequentially so that the light of each color of RGB is emitted in a predetermined order.

Here, the predetermined order refers to a predetermined color order in which RGB is circulated (hereinafter, for ease of explanation, this will be referred to as the "circulating color order").

The CIS includes a light guide, a light collecting section, and a photoelectric conversion element.

The light guide is formed in an elongated shape along the main scanning direction. The first to third LEDs are attached to one end of the light guide, and the light emitted by the first to third LEDs is guided to the document via the platen glass.

The focusing section is a lens unit in which multiple erect life-size imaging lens elements are arranged along the main scanning direction, and focuses the light reflected by the document when the first to third LEDs irradiate the document with light.

The photoelectric conversion elements are arranged in a number of pieces along the main scanning direction, and receive the light focused by the focusing section and perform photoelectric conversion to generate and output image information. The image information includes image information showing an R image, image information showing a G image, and image information showing a B image.

Image information from the CIS is supplied to an AFE (Analog Front End). The AFE adjusts the image information input from the photoelectric conversion element using an amplifier, A/D converter, filter, etc. (not shown), and outputs the adjusted image information.

FIG. 2 shows a functional block diagram of the information processing device 100. The information processing device 100 includes a controller 160. The controller 160 includes a CPU (Central Processing Unit) 162, a primary storage unit 164, and a secondary storage unit 166. The primary storage unit 164 is a volatile memory (e.g., RAM (Random Access Memory)) used as a work area during execution of various programs. The secondary storage unit 166 is a non-volatile memory (e.g., flash memory or HDD (Hard Disk Drive)) that stores in advance control programs that control the operation of the information processing device 100, various parameters, and the like. The CPU 162, the primary storage unit 164, and the secondary storage unit 166 are connected to each other via a bus 168.

The information processing device 100 includes an input/output interface (I/O) 170 that electrically connects the CPU 162 to various input/output devices and transmits/receives various information between the CPU 162 and the various input/output devices. The information processing device 100 includes an image reading unit 102, an image forming unit 104, and a UI unit 108 as input/output devices that are electrically connected to the CPU 162 via a bus 168 by being connected to the I/O 170. The information processing device 100 also includes an external interface (I/F) 172 and a communication I/F 174 as input/output devices.

The external I/F 172 is connected to an external device (e.g., a USB memory) and transmits and receives various information between the external device and the CPU 162. The communication I/F 174 is connected to a communication means such as a LAN (Local Area Network) or the Internet and transmits and receives various information to and from an external device 176 connected to the communication means.

The CPU 162 transmits and receives various information to and from the above-mentioned input/output devices via the bus 168 and the I/O 170, thereby grasping the operating status of the input/output devices and controlling the input/output devices.

Now, let's return to the explanation of the image reading unit itself.

The CIS includes an LED drive circuit. The LED drive circuit is connected to each of the first to third LEDs. The AFE is connected to the LED drive circuit and is connected to the I/O 170 via a signal line.

The AFE controls the driving of the LED drive circuit according to a lighting start signal input from the CPU 162 via the I/O 170 and a signal line in response to a scan start instruction received by the UI unit 108. The LED drive circuit, under the control of the AFE, repeatedly causes the first to third LEDs to emit light in the order of the first LED, the second LED, and the third LED. In other words, when a lighting start signal is input, the AFE controls the LED drive circuit to cause the first LED to emit light first, and thereafter to emit light in a cyclic color order.

The image processing circuit has a function of processing the image information input from the AFE in a cyclic color order starting from a specific color (here, R), and performs image processing such as shading correction and pixel layout conversion processing on the image information input from the AFE.

Figure 3 shows the configuration of the CIS, AFE, and part of the image processing circuit. This is a basic configuration diagram that is the premise of this embodiment. The image reading unit main body includes a CIS 121, an AFE 122, and an image processing circuit, but the CIS 121 and AFE 122 can be functionally separated as a scanner, and the image processing circuit can be functionally separated as a scan circuit.

The image processing circuit shown in FIG. 3 includes an input/output circuit 123, an ANF (Anti Noise Function) circuit 124, an R, G, B line head detection circuit 125, a pixel capture FIFO memory 126, and a DMA (Direct Memory Access) 127 as main components for storing image information in the DDR 128. At least a part of the image processing circuit may be configured with a processor such as a CPU. For example, the input/output circuit 123, the ANF circuit 124, and the R, G, B line head detection circuit 125 may be configured with one or more CPUs. The ANF circuit 124 and the R, G, B line head detection circuit 125 may be manufactured by different manufacturers, in which case the ANF circuit 124 and the R, G, B line head detection circuit 125 may be configured with separate processors. The one or more CPUs realize the processing of each part by reading and executing the control program stored in the program memory. Of course, each part of the scan circuit may be realized by hardware.

The scanner including the CIS 121 and the AFE 122 outputs image information in line sequence in the order of R, G, B as described above.
R image information → G image information → B image information → R image information → G image information → B image information → ...
The image information is output in the order of R, G, and B. R, G, and B are appropriately referred to as the first color, the second color, and the third color, respectively.

The input/output circuit 123 has a serial-to-parallel conversion function and converts serial image information into parallel image information and outputs it.

The ANF circuit 124 detects the beginning of each line of the R image information, G image information, and B image information, generates a line beginning signal indicating the detection, and outputs it to the R, G, and B line beginning detection circuits.

The R, G, B line head detection circuit 125 is a circuit that manages the color state of the image information to be captured into the pixel capture FIFO memory 126, and each time it detects a line head signal, it updates the R, G, B color states in sequence and outputs a capture start control signal to the pixel capture FIFO memory 126. The R, G, B line head detection circuit 125 does not determine whether the image information currently being transferred is R image information, G image information, or B image information from the image information input from the scanner, but simply detects the line head each time
R→G→B→R→G→B→・・・
In other words, the color state is changed in the following order:
First color → Second color → Third color → First color → Second color → Third color → ...
The color state is converted in the following order.

More specifically, when the R, G, B line head detection circuit 125 receives a line head signal of R image information from the ANF circuit 124, it controls the pixel capture FIFO memory 126 to capture R image information in response to this line head signal. At this time, the current color state managed by the R, G, B line head detection circuit 125 is "R color" or "end of B color", which indicates that processing of the previous color, B color, has already ended. Here, "R color" means the color state resulting from updating the previous color, B color. Then, when the R, G, B line head detection circuit 125 captures a specified number of pixels from the line head into the pixel capture FIFO memory 126, it ends the capture of R image information. At this time, the color state becomes "end of R color".

Next, when the R, G, B line head detection circuit 125 receives a line head signal of G image information from the ANF circuit 124, it controls the pixel capture FIFO memory 126 to capture G image information in response to this line head signal. At this time, the color state is either "G color" as a result of the update, or "End of R color" indicating that processing of the previous color, R color, has already ended. Then, when the R, G, B line head detection circuit 125 captures a specified number of pixels from the line head into the pixel capture FIFO memory 126, it ends the capture of G image information.

Next, when the R, G, B line head detection circuit 125 receives a line head signal of the B image information from the ANF circuit 124, it controls the pixel capture FIFO memory 126 to capture the B image information in response to this line head signal. At this time, the color state is either "B color" as a result of the update, or "end of G color" indicating that processing of the previous color, G color, has already ended. Then, when the R, G, B line head detection circuit 125 captures a specified number of pixels from the line head into the pixel capture FIFO memory 126, it ends the capture of the B image information.

Next, when the R, G, B line head detection circuit 125 receives the line head signal of the R image information again from the ANF circuit 124, it controls the pixel capture FIFO memory 126 in response to this line head signal to capture the R image information. At this time, the color state is either "R color" as a result of the update, or "End of B color" indicating that processing of the previous color, B color, has already ended. Then, when the R, G, B line head detection circuit 125 captures a specified number of pixels from the line head into the pixel capture FIFO memory 126, it ends the capture of the R image information.

The pixel capture FIFO memory 126 sequentially captures R image information, G image information, and B image information in response to a control signal from the R, G, and B line head detection circuit 125.

The DMA 127 reads the image information captured in the pixel capture FIFO memory 126 and transfers it directly to the DDR (Double-Data-Rate Synchronous Dynamic Random Access Memory) 128.

In this way, the ANF circuit 124 generates a line head signal in synchronization with the image information from the scanner, outputs it to the R, G, and B line head detection circuit 125, and controls the capture of image information for each color, so that even if noise is mixed in and disrupts the image information transferred from the scanner, the color state can be synchronized.

However, as shown in Fig. 4, if some abnormality, for example some problem occurs in the R, G, B line head detection circuit 125, causing a difference in color state between the ANF circuit 124 and the R, G, B line head detection circuit 125 (in Fig. 4, the mismatch in color state between the two is indicated by an X), the color state of the scanned image transferred from the scanner and the color state of the ANF circuit 124 remain synchronized, but the color state of the ANF circuit 124 and the color state of the R, G, B line head detection circuit 125 are not synchronized, so that a situation may arise in which the image information of the scanned image transferred from the scanner cannot be captured in the pixel capture FIFO memory 126 and further the DDR 128 in the correct R, G, B color order. The reason for this is that, as described above, the R, G, B line head detection circuit 125 does not determine whether the image information currently being transferred is R image information, G image information, or B image information from the image information input from the scanner, but simply detects the head of a line every time it detects the head of a line.
R→G→B→R→G→B→・・・
This is because the color state is changed sequentially in the order of

Figure 5 shows a timing chart of the scanner, ANF circuit 124, and R, G, B line head detection circuit 125.

Figure 5 (a) is a timing chart of image information transferred from the scanner. R image information, G image information, and B image information are transferred in that order.

Figure 5 (b) is a timing chart of the line head detection of R image information, G image information, and B image information in the ANF circuit 124. When the ANF circuit 124 detects the line head of R image information, G image information, and B image information from the image information from the input/output circuit 123, it generates a line head signal as a pulse signal and outputs it to the R, G, B line head detection circuit 125.

5C is a timing chart of the R, G, B line head detection circuit 125. When the R, G, B line head detection circuit 125 receives a line head signal from the ANF circuit 124, it instructs the pixel capture FIFO memory 126 to start capturing, and sequentially changes the state of the colors to be captured.
R→G→B→R→G→B→・・・
and update it.

Therefore, if the circuit is operating normally, when the R, G, B line head detection circuit 125 receives a line head signal from the ANF circuit 124 that detects the line head of R image information, it updates the color state from the previous color state of B to R and controls the pixel capture FIFO memory 126 to capture R image information. Then, when the specified number of pixels of image information have been captured from the line head, the capture of R image information ends. In the figure, the rising edge of the rectangular pulse signal indicates the start timing of the capture of R image information, and the falling edge of the rectangular pulse signal indicates the end timing of the capture of R image information.

Next, when the R, G, B line head detection circuit 125 receives a line head signal from the ANF circuit 124 to detect the line head of the G image information, it updates the color state from the previous color state of R to G and controls the pixel capture FIFO memory 126 to capture the G image information. Then, when the specified number of pixels of image information have been captured from the line head, the capture of the G image information ends. In the figure, the rising edge of the rectangular pulse signal indicates the start timing of the capture of the G image information, and the falling edge of the rectangular pulse signal indicates the end timing of the capture of the G image information.

Next, when the R, G, B line head detection circuit 125 receives a line head signal from the ANF circuit 124 to detect the line head of the B image information, it updates the color state from the previous color state of G to B and controls the pixel capture FIFO memory 126 to capture the B image information. Then, when the specified number of pixels of image information have been captured from the line head, the capture of the B image information ends. In the figure, the rising edge of the rectangular pulse signal indicates the start timing of the capture of the B image information, and the falling edge of the rectangular pulse signal indicates the end timing of the capture of the B image information.

If the system is operating normally, the above process is repeated, and the process proceeds while the color state detected by the ANF circuit 124 matches the color state controlled by the R, G, and B line head detection circuit of the scan circuit.

On the other hand, for example, a malfunction may occur in the R, G, B line head detection circuit 125, causing the color state detected by the ANF circuit 124 to no longer match the color state controlled by the R, G, B line head detection circuit 125 for capturing. For example, suppose that a line head signal that detects the line head of R image information is received from the ANF circuit 124, the color state is updated to R color, and control is performed to capture the R image information in the pixel capture FIFO memory 126, but some abnormality occurs and the capture state of the R image information continues.

In this case, even if the R, G, B line head detection circuit 125 receives a line head signal from the ANF circuit 124 to detect the line head of the G image information, it maintains control so that the R image information is directly captured in the pixel capture FIFO memory 126 without updating the color state from R to G.

And even if for some reason the R, G, B line head detection circuit 125 operates again and resumes updating the color state in response to a line head signal from the ANF circuit 124, when it receives a line head signal from the ANF circuit 124 that detects the line head of the B image information, it updates the color state from the current color state of R to G and controls the pixel capture FIFO memory 126 to capture G image information (in reality it should be controlled to capture B image information).

Furthermore, this mismatched color state continues, making it impossible to return to a normal state. Here, "returning to a normal state" means that the color state detected by the ANF circuit 124 and the color state detected by the R, G, B line head detection circuit 125 move from a mismatched state to a matched state.

This problem can be eliminated by configuring the R, G, B line head detection circuit 125 to determine whether the image information currently being transferred is R image information, G image information, or B image information. However, if the R, G, B line head detection circuit 125 is supplied by another manufacturer, it is not easy to change the configuration.

Therefore, in this embodiment, when the ANF circuit 124 detects the line head of the R image information signal, G image information signal, or B image information signal received from the input/output circuit 123, it does not always generate a line head signal indicating the line head and output it to the R, G, B line head detection circuit 125, but instead acquires and monitors the color state in the R, G, B line head detection circuit 125, and does not output a line head signal if the color associated with the line head of the R image information signal, G image information signal, or B image information signal received from the input/output circuit 123 does not match the color state in the R, G, B line head detection circuit 125, and outputs a line head signal only when both colors match.

The ANF circuit 124 in this embodiment is
- A function to monitor the color status of the R, G, and B line head detection circuits and compare it with the color status of the transferred image information. - A function to interrupt (mask) the output of the line head signal if the color status does not match.

Figure 6 shows the configuration of the ANF circuit 124 and the R, G, B line head detection circuit 125 in this embodiment. It is almost the same as the configuration in Figure 3, but the function of the ANF circuit 124 is different. In Figure 6, the ANF circuit 124 can be realized by a processor that executes a control program. The ANF circuit 124 also functions as a detection means. The R, G, B line head detection circuit 125 can be realized by another processor that executes a control program. The R, G, B line head detection circuit 125 also functions as an update means that updates the color state.

The ANF circuit 124 inputs image information from the input/output circuit 123, detects the line beginnings of the R image information, G image information, and B image information, and outputs a line beginning signal as a synchronization signal.

The ANF circuit 124 also acquires the color state of the R, G, B line head detection circuit 125. The R, G, B line head detection circuit 125 may always output its color state, i.e., the color state of the image information captured in the pixel capture FIFO memory 126, to the ANF circuit 124, or may output its color state to the ANF circuit 124 in response to a transmission request from the ANF circuit 124. In the latter case, the ANF circuit 124 may generate a line head signal at the timing when it detects the line heads of the R image information, G image information, and B image information, and request the R, G, B line head detection circuit 125 to transmit the color state before outputting the signal to the R, G, B line head detection circuit 125.

Then, the ANF circuit 124 compares the color state of the line head of the R image information, G image information, and B image information detected from the image information of the input/output circuit 123 with the color state of the R, G, B line head detection circuit 125, and determines whether the two match.

More specifically, at the timing when the ANF circuit 124 detects the line head of the R image information, if everything is normal, the R, G, B line head detection circuit 125 controls the pixel capture FIFO memory 126 to capture image information of B color, which is the previous color state, so the ANF circuit 124 determines whether the color state of the R, G, B line head detection circuit 125 is the end of B color at the timing when the ANF circuit 124 detects the line head of the R image information, and if it is the end of B color, determines that they match. The following are cases when the two match.
Color of the line head detected by the ANF circuit: Color state of the R, G, B line head detection circuit R: End of B G: End of R B: End of G Of course, if the color state in the R, G, B line head detection circuit 125 means the color state after updating, that is, the color state to be processed next, then it would be determined that the color states of both match just because they are the same color.

If the comparison result shows that the two are the same, the ANF circuit 124 generates a line head signal as a synchronization signal and outputs it to the R, G, B line head detection circuit 125. The R, G, B line head detection circuit 125 receives the line head signal from the ANF circuit 124, and in response updates the color state to the next color and captures image information (pixels) into the pixel capture FIFO memory 126. In other words, if B color has already been captured, the color state is updated to the next R color and control is performed to capture the pixels of the R image information. Also, if R color has already been captured, the color state is updated to the next G color and control is performed to capture the pixels of the G image information.

On the other hand, if the comparison result shows that the two do not match, the ANF circuit 124 determines that some abnormality has occurred and does not generate a line head signal or output it to the R, G, B line head detection circuit 125. Since the R, G, B line head detection circuit 125 does not receive a line head signal from the ANF circuit 124, it does not update the color state to the next color in response, and maintains the current color state as is.

If the two continue to be inconsistent and then match again, the ANF circuit 124 generates a line head signal when it detects the line head again and outputs it to the R, G, B line head detection circuit 125. The R, G, B line head detection circuit 125 receives the line head signal from the ANF circuit 124, and in response updates the color state to the next color and captures image information (pixels) again into the pixel capture FIFO memory 126. This allows the color state detected by the ANF circuit 124 to match the color state in the R, G, B line head detection circuit 125, and the capture of image information is resumed, allowing a quick recovery from the abnormal state.

The ANF circuit 124 is synchronized with the image information transferred from the scanner, and by synchronizing the color state of the ANF circuit 124 with the R, G, B line head detection circuit 125, the color state of the scanner and the scan circuit can ultimately be synchronized.

The image information captured in the pixel capture FIFO memory 126 is addressed by the DMA 127 and directly transferred to the DDR 128, which serves as a storage unit, for storage. However, if an abnormality occurs, erroneous image information from the abnormality will be stored in the DDR 128 via the DMA 127. Therefore, it is preferable for the ANF circuit 124 to adjust the address of the DMA 127 so that the image information of the line in which the abnormality occurred is overwritten with the image information of the line after normality has been restored.

For this reason, as shown in FIG. 7, when an abnormality occurs, the ANF circuit 124 stops outputting the line head signal and subtracts one from the line counter value for specifying the address of the DMA 127 in order to move the address of the DMA 127 back by one line. In other words, under normal conditions, the ANF circuit 124 generates a line head signal and outputs it to the R, G, and B line head detection circuit 125, adds one to the line counter value, outputs it to the DMA 127, and advances the address of the DMA 127 by one line, but when an abnormality is detected, the line counter value is subtracted by one and outputs it to the DMA 127 so as to move the address of the DMA 127 back by one line. The DMA 127 writes the image information captured in the pixel capture FIFO memory 126 to an address of the DDR 128 according to the line counter value from the ANF circuit 124.

Figure 8 shows a timing chart of the scanner, ANF circuit 124, and R, G, B line head detection circuit 125 in this embodiment. This is a timing chart corresponding to Figure 5.

Figure 8 (a) is a timing chart of image information transferred from the scanner. R image information, G image information, and B image information are transferred in that order.

Figure 8 (b) is a timing chart of the line head detection of R image information, G image information, and B image information in the ANF circuit 124. As a basic operation, when the ANF circuit 124 detects the line head of R image information, G image information, and B image information from the image information from the input/output circuit, it generates a line head signal as a pulse signal and outputs it to the R, G, B line head detection circuit 125.

8C is a timing chart of the R, G, B line head detection circuit 125. When the R, G, B line head detection circuit 125 receives a line head signal from the ANF circuit 124, it instructs the pixel capture FIFO memory 126 to start capturing, and sequentially changes the state of the colors to be captured.
R→G→B→R→G→B→・・・
and update it.

Therefore, if the circuit is operating normally, when the R, G, B line head detection circuit 125 receives a line head signal from the ANF circuit 124 that detects the line head of R image information, it updates the color state from the previous color state of B to R and controls the pixel capture FIFO memory 126 to capture R image information. Then, when the specified number of pixels of image information have been captured from the line head, the capture of R image information ends. In the figure, the rising edge of the rectangular pulse signal indicates the start timing of the capture of R image information, and the falling edge of the rectangular pulse signal indicates the end timing of the capture of R image information.

Next, when the R, G, B line head detection circuit 125 receives a line head signal from the ANF circuit 124 to detect the line head of the G image information, it updates the color state from the previous color state of R to G and controls the pixel capture FIFO memory 126 to capture the G image information. Then, when a predetermined number of pixels of image information have been captured from the line head, the capture of the G image information ends. In the figure, the rising edge of the rectangular pulse signal indicates the start timing of the capture of the G image information, and the falling edge of the rectangular pulse signal indicates the end timing of the capture of the G image information.

Next, when the R, G, B line head detection circuit 125 receives a line head signal from the ANF circuit 124 to detect the line head of the B image information, it updates the color state from the previous color state of G to B and controls the pixel capture FIFO memory 126 to capture the B image information. Then, when a predetermined number of pixels of image information have been captured from the line head, the capture of the B image information ends. In the figure, the rising edge of the rectangular pulse signal indicates the start timing of the capture of the B image information, and the falling edge of the rectangular pulse signal indicates the end timing of the capture of the B image information.

If the system is operating normally, the above process is repeated, and the process proceeds while synchronizing the color state detected by the ANF circuit 124 with the color state controlled by the R, G, B line head detection circuit 125 of the scan circuit.

On the other hand, suppose an abnormality occurs in the R, G, B line head detection circuit 125. Specifically, suppose some abnormality occurs during the import process of R image information. After this, the color state detected by the ANF circuit 124 and the color state in the R, G, B line head detection circuit 125 do not match. In other words, when the ANF circuit 124 detects the line head of the G image information, under normal conditions the color state of the R, G, B line head detection circuit 125 should be that the import of R color has ended, but an abnormality has occurred and the import of R color has not ended, so the color states of the two do not match.

In this case, even if the ANF circuit 124 detects the line head of the G image information, it does not output a line head signal because it does not match the color state of the R, G, B line head detection circuit 125. In FIG. 8(b), the dashed pulse signal indicates that the line head signal is not output even if the line head of the G image information is detected. Because the line head signal is not output, the R, G, B line head detection circuit 125 does not receive a line head signal from the ANF circuit 124 and maintains the current color state as is without updating it. In other words, the state in which the capture of R color is not completed is maintained as is.

Next, even if the ANF circuit 124 detects the line head of the B image information, the color state of the R, G, B line head detection circuit 125 should be that the G color capture is complete under normal conditions. However, because an abnormality has occurred and the R color capture is not complete, the two color states do not match, so the ANF circuit 124 does not output a line head signal even if it detects the line head of the B image information. In FIG. 8B, the dashed pulse signal indicates that the line head signal is not output even if the line head of the B image information is detected. Since the line head signal is not output, the R, G, B line head detection circuit 125 does not receive a line head signal from the ANF circuit 124 and maintains the current color state as it is without updating it. In other words, the state in which the R color capture is not complete is maintained as it is.

Next, when the ANF circuit 124 detects the line head of the R image information, the current color state of the R, G, B line head detection circuit 125 is a state in which the capture of R image information is continuing, i.e., the previous capture of B color has ended, so the two color states match again, and the ANF circuit 124 generates and outputs a line head signal at the timing of detecting the line head of the R image information again. In FIG. 8(b), the re-output of the line head signal is shown as a solid pulse signal. When the R, G, B line head detection circuit 125 receives the line head signal, it resumes the capture of R image information into the pixel capture FIFO memory 126, and ends the capture of R image information when it has captured the specified number of pixels of R image information from the line head.

After that, the color state detected by the ANF circuit 124 and the color state in the R, G, B line head detection circuit 125 again match, so the ANF circuit 124 generates a line head signal each time it detects the head of a line of R image information, G image information, or B image information, and outputs it to the R, G, B line head detection circuit 125.

Next, the processing of this embodiment will be explained in more detail using a flowchart.

Figures 9, 10, and 11 show processing flowcharts for the embodiment.

First, in FIG. 9, the ANF circuit 124 reserves the DMA address at the beginning of the page (S101). Next, the abnormality flag is initialized to 0 (D102). This abnormality flag is identification information indicating that an abnormality has occurred, and is set to 0 if no abnormality has occurred and to 1 if an abnormality has occurred.

Next, the ANF circuit 124 detects the line head of the R image information from the image information sent from the input/output circuit 123 (S103). If the line head of the R image information is not detected, the process is repeated until it is detected.

When the start of a line of R image information is detected (YES in s103), the ANF circuit 124 determines whether this detection timing is the start of a page or whether the color state of the R, G, B line start detection circuit 125 at this detection timing is B color, i.e., after the end of the B image information (S104).

As described above, the R, G, B line head detection circuit 125 does not determine whether the image information currently being transferred is R image information, G image information, or B image information, but simply performs the following every time it detects the head of a line:
R→G→B→R→G→B→・・・
The ANF circuit 124 obtains the current color state of the R, G, B line head detection circuit 125, and determines whether the color state of the R, G, B line head detection circuit 125 is B, that is, whether the B image information has ended.

Here, after the B color is finished, it is updated to the next R color, so it may be compared with the updated R color. However, it should be noted that the update actually occurs after the R, G, B line head detection circuit 125 receives the head line signal from the ANF circuit 124, so the updated color state has not yet been achieved before the line head signal is received.

If the timing at which the line head of the R image information is detected is the top of a page, or the color state of the R, G, B line head detection circuit 125 is after the end of the B image information (YES in S104), since the image information is transferred in the order of R, G, B, the detection at this timing is the correct line head of the R image information, and the ANF circuit 124 maintains the abnormality flag at 0 (S105), issues a line head signal indicating that the line head of the R image information has been detected, and outputs it to the R, G, B line head detection circuit 125 (S106). Then, the line counter is incremented by adding 1. When the R, G, B line head detection circuit 125 receives the line head signal from the ANF circuit 124, it changes the color state to the color next to B, specifically R, and outputs an acquisition start signal to the pixel acquisition FIFO memory 126.

On the other hand, if the timing of detecting the line head of the R image information is not after the page head or the end of the B image information (NO in S104), the color state detected by the ANF circuit 124 and the color state in the R, G, B line head detection circuit 125 do not match, so the value of the abnormality flag is checked (S108), and if the abnormality flag is 0, an abnormality is detected and the abnormality flag is set from 0 to 1 (S109). In this case, the ANF circuit 124 does not issue a line head signal despite detecting the line head of the R image information (not executing the process of S106), and decrements the line counter by 1 (S110). Since the R, G, B line head detection circuit 125 does not input the line head signal from the ANF circuit 124, it does not update the color state to the color next to R, specifically G, and maintains the current color state as it is and captures the image information into the pixel capture FIFO memory 126.

Also, if the abnormality flag is already set to 1 (NO in S108), the process proceeds to the process in FIG. 10 without changing the line counter value.

After incrementing the line counter by 1 (S107) or decrementing the line counter by 1 (S108), the ANF circuit 124 reserves the first DMA address of the next line according to the line counter and outputs it to the DMA 127 (S111). Then, the process proceeds to the process shown in FIG. 10.

In FIG. 10, the ANF circuit 124 detects the line head of the G image information from the image information sent from the input/output circuit 123 (S112). If the line head of the G image information is not detected, the process is repeated until it is detected.

When the line head of the G image information is detected (YES in S112), the ANF circuit 124 judges whether the color state of the R, G, B line head detection circuit 125 is R, that is, whether the R image information has ended (S113). In other words, the ANF circuit 124 obtains the current color state of the R, G, B line head detection circuit 125 and judges whether the color state of the R, G, B line head detection circuit 125 is R, that is, whether the R image information has ended.

If the R, G, B line head detection circuit 125 detects the line head of the G image information after the end of the R image information (YES in S113), it determines that the detection at this timing is the correct line head of the G image information, sets the abnormality flag to 0 (S114), and issues a line head signal indicating that the line head of the G image information has been detected and outputs it to the R, G, B line head detection circuit 125 (S115). Then, it increments the line counter by 1 (S116). When the R, G, B line head detection circuit 125 receives the line head signal from the ANF circuit 124, it changes the color state to the color next to R, specifically G, and outputs an acquisition start signal to the pixel acquisition FIFO memory 126.

On the other hand, if the timing of detecting the line head of the G image information is not after the end of the R image information (NO in S113), the color state detected by the ANF circuit 124 and the color state in the R, G, B line head detection circuit 125 do not match, so the value of the abnormality flag is checked (S117), and if the abnormality flag is 0, an abnormality is detected and the abnormality flag is set from 0 to 1 (S118). In this case, the ANF circuit 124 does not issue a line head signal despite detecting the line head of the G image information (processing of S115 is not executed), and decrements the line counter by 1 (S119). Since the R, G, B line head detection circuit 125 does not input the line head signal from the ANF circuit 124, the color state is not updated and the current color state is maintained as it is.

Also, if the abnormality flag is already set to 1 (NO in S117), the process proceeds to FIG. 11.

After incrementing or decrementing the line counter by 1, the ANF circuit 124 reserves the first DMA address of the next line according to the line counter (S120). Then, the process proceeds to the process shown in FIG. 11.

In FIG. 11, the ANF circuit 124 detects the line head of the B image information from the image information sent from the input/output circuit 123 (S121). If the line head of the B image information is not detected, the process is repeated until it is detected.

When the line head of the B image information is detected (YES in S121), the ANF circuit 124 judges whether the color state of the R, G, B line head detection circuit 125 is G color, that is, whether the end of the G image information has occurred (S122). In other words, the ANF circuit 124 obtains the current color state of the R, G, B line head detection circuit 125, and judges whether the color state of the R, G, B line head detection circuit 125 is G color, that is, whether the end of the G image information has occurred.

If the R, G, B line head detection circuit 125 detects the line head of the B image information after the end of the G image information (YES in S122), it determines that the detection at this timing is the correct line head of the B image information, sets the abnormality flag to 0 (S123), and issues a line head signal indicating that the line head of the B image information has been detected and outputs it to the R, G, B line head detection circuit (S124). Then, it increments the line counter by 1 (S125). When the R, G, B line head detection circuit 125 receives the line head signal from the ANF circuit 124, it changes the color state to the color next to G, specifically B, and outputs an acquisition start signal to the pixel acquisition FIFO memory 126.

On the other hand, if the timing at which the line head of the B image information is detected is not after the end of the G image information (NO in S122), the detection at this timing is not the correct line head of the B image information, that is, the color state detected by the ANF circuit 124 does not match the color state in the R, G, B line head detection circuit 125, so the value of the abnormality flag is checked (S126), and if the abnormality flag is 0, an abnormality is determined to have occurred and the abnormality flag is set from 0 to 1 (S127). In this case, the ANF circuit 124 does not issue a line head signal despite having detected the line head of the B image information (the process of S124 is not executed), and the line counter is decremented by 1 (S128). Since the R, G, B line head detection circuit 125 does not input the line head signal from the ANF circuit 124, the color state is not updated and the current color state is maintained as it is.

Also, if the abnormality flag has already been set to 1 (NO in S126), the process returns to the process of detecting the beginning of the line for the R image information in FIG. 9 (S103) and repeats the processes in FIGS. 9 to 11.

After incrementing or decrementing the line counter by 1, the ANF circuit 124 reserves the first DMA address of the next line according to the line counter (S129). Then, it determines whether the value of the line counter has reached the set number of lines (S130).

If the line counter value has reached the set number of lines, the process ends (YES in S130), and if the line counter value has not reached the set number of lines (NO in S130), the process returns to the R image information line start detection process (S103) in FIG. 9 and repeats the processes in FIGS. 9 to 11.

According to the above process, when the abnormality flag is set to 1, the output of the line head signal from the ANF circuit 124 to the R, G, B line head detection circuit 125 is interrupted, and the update of the color state in the R, G, B line head detection circuit 125 is interrupted. Then, when the ANF circuit 124 detects the head of any of the R image information, G image information, or B image information, and the color state detected by the ANF circuit 124 and the color state in the R, G, B line head detection circuit 125 match again at the timing of the detection of the line head, the abnormality flag is set from 1 to 0 again, the output of the line head signal from the ANF circuit 124 to the R, G, B line head detection circuit 125 is resumed, and the update of the color state in the R, G, B line head detection circuit 125 is resumed.

As described above, in this embodiment, the R, G, B line head detection circuit 125 of the scan circuit controls the capture of pixels into the pixel capture FIFO memory 126 by inputting a line head signal from the ANF circuit 124, and changes the color state in the order of R→G→B→R→G→B→...
and so on. The ANF circuit 124 acquires the color state of the R, G, B line head detection circuit 125, and when it detects that the color state detected by the ANF circuit 124 and the color state of the R, G, B line head detection circuit 125 do not match and are out of synchronization, the output of the line head signal from the ANF circuit 124 to the R, G, B line head detection circuit is interrupted to interrupt the updating of the color information in the R, G, B line head detection circuit 125. When the color state detected by the ANF circuit 124 and the color state in the R, G, B line head detection circuit 125 match and are synchronized again, the output of the line head signal from the ANF circuit 124 to the R, G, B line head detection circuit 125 is resumed to resume the updating of the color state in the R, G, B line head detection circuit 125, thereby resynchronizing the color state.

In addition, in this embodiment, when an abnormality occurs, the value of the line counter of the ANF circuit 124 is decremented by 1 and the address of the DMA 127 is moved back by one line. Normally, the address advances by one line and is stored in the DDR 128, so that even after a recovery from the abnormality, data is stored starting from the line following the abnormal line. However, after a recovery from the abnormality to normal, the abnormal line can be overwritten with the normal line, so various processes can be performed using the correct image information stored in the DDR 128.

In the above embodiment, the processor refers to a processor in a broad sense, and may be a general-purpose processor (e.g., a CPU Central Processing Unit, etc.) or a dedicated processor (e.g., a GPU
Graphics Processing Unit, ASIC Application Specific Integrated Circuit, FPGA
Field Programmable Gate Arrays, programmable logic devices, etc.

In addition, the processor operations in the above embodiments may not only be performed by a single processor, but may also be performed by multiple processors located at physically separate locations working together. Furthermore, the order of the processor operations is not limited to the order described in the above embodiments, and may be changed as appropriate.

REFERENCE SIGNS LIST 100 information processing device, 102 image reading unit, 121 CIS, 122 AFE, 123 input/output circuit, 124 ANF circuit, 125 R, G, B line head detection circuit, 126 pixel capture FIFO memory, 127 DMA, 128 DDR.

Claims (7)

The present invention includes a processor that receives and processes signals generated for each of a plurality of colors and output in a predetermined order and in a cyclic manner for the plurality of colors, the processor executing a program to:
Detecting the timing of the start of each color among the plurality of colors and outputting a synchronization signal;
inputting the signal, and sequentially updating the color to be captured among the plurality of colors in response to the synchronization signal;
if the updated color does not match the color output at the timing of outputting the synchronization signal, the output of the synchronization signal is interrupted to interrupt the update.
Signal processing device. The processor,
The updated color signal is captured and stored in the memory.
When the output of the synchronization signal is resumed, an address at which the captured signal is stored in the storage unit is controlled to an address at the timing when the output of the synchronization signal was interrupted.
The signal processing device according to claim 1 . the plurality of colors are composed of a first color, a second color, and a third color, and the first color, the second color, and the third color are output alternately and cyclically in this order;
when the processor detects the timing of the beginning of the first color, and the updated color is the second color or the third color, the processor interrupts output of the synchronization signal;
3. A signal processing device according to claim 1 or 2. The processor,
interrupting the output of the synchronization signal when the timing of the start of the first color is not the start of a page.
The signal processing device according to claim 3 . a generating means for receiving reflected light when a light of each of a plurality of colors is irradiated onto an image area including an image on a recording medium in a cyclical color order of the plurality of colors, and outputting a signal obtained by receiving the reflected light;
A signal processing device according to any one of claims 1 to 4, which processes the signal generated by the generating means;
An image reading device comprising: The image reading device according to claim 5 ;
an image forming apparatus that forms an image based on the signal processed by the signal processing apparatus included in the image reading apparatus;
An information processing device comprising: Computer,
a detection means for receiving a signal generated for each of a plurality of colors and outputting the plurality of colors in a predetermined order and in a cyclical manner, detecting the timing of the start of each of the plurality of colors and outputting a synchronization signal;
an update means for receiving the signal and sequentially updating the color to be captured among the plurality of colors in response to the synchronization signal from the detection means;
and interrupting the output of the synchronization signal when the color updated by the update means does not match the color output at the timing of outputting the synchronization signal.
program.