JP7524407B2 - Photodetector and electronic device - Google Patents

Description

This disclosure relates to a photodetector element and electronic device, and in particular to a photodetector element and electronic device that can improve the characteristics of SPAD pixels.

In recent years, distance image sensors that measure distance using the ToF (Time-of-Flight) method have been attracting attention. For example, distance image sensors can use pixel arrays formed by arranging multiple SPAD (Single Photon Avalanche Diode) pixels in a plane using CMOS (Complementary Metal Oxide Semiconductor) semiconductor integrated circuit technology. In a SPAD pixel, when a single photon enters a high-electric field PN junction region under the application of a voltage much larger than the breakdown voltage, avalanche amplification occurs. By detecting the time when the current flows at that time, it is possible to measure distance with high accuracy.

For example, Patent Document 1 discloses a technology that reduces crosstalk to adjacent pixels caused by light emission in high electric field regions by using a structure that creates separation between pixels in a photodiode array in which avalanche photodiodes are arranged.

Patent Document 2 also discloses a technology for improving the sensitivity of SPAD pixels in single photon avalanche diodes by embedding a layer that forms a high electric field region and depleting it with a bias.

JP 2013-48278 A JP 2015-41746 A

However, the structure disclosed in Patent Document 1 only reduces optical crosstalk by physically isolating pixels using an insulating film, and does not improve sensitivity.

In addition, in the structure disclosed in Patent Document 2, light is emitted in the high electric field region within a pixel, causing photons to be incident on adjacent pixels, resulting in crosstalk in which photons are unintentionally detected in adjacent pixels. Furthermore, there are concerns that sensitivity may decrease because incident light is transmitted to the surface (front surface) on which the gates and wiring are formed, which is opposite the light incident surface (back surface).

Therefore, there is a demand for SPAD pixels with better characteristics that prevent the occurrence of such crosstalk and improve sensitivity.

This disclosure has been made in light of these circumstances, and aims to improve the characteristics of SPAD pixels.

A photodetector element according to one aspect of the present disclosure includes a pixel array section in which a plurality of pixels are arranged in an array, an avalanche photodiode element provided on a semiconductor substrate, the avalanche photodiode element multiplying carriers by a high electric field region provided for each of the pixels, and an inter-pixel isolation section is provided to isolate the avalanche photodiode element from adjacent pixels on the semiconductor substrate on which the avalanche photodiode element is formed.
The semiconductor substrate includes a first metal wiring provided in a first wiring layer laminated on a surface opposite to the light receiving surface of the semiconductor substrate so as to cover at least the high electric field region in a plan view, and connected to the cathode of the avalanche photodiode element via a first electrode, and a second metal wiring provided in the first wiring layer and connected to the anode of the avalanche photodiode element via a second electrode, and in a cross-sectional view, the first metal wiring is provided between the second metal wirings within one pixel region, and a polysilicon film which is a reflective film that reflects light is formed on the surface of the semiconductor substrate, the polysilicon film being formed over a range wider than the high electric field region so as to cover at least all but a portion including a contact electrode for supplying a negative voltage to the high electric field region and the periphery of the contact electrode .

An electronic device according to one aspect of the present disclosure includes a pixel array section in which a plurality of pixels are arranged in an array, an avalanche photodiode element provided on a semiconductor substrate and multiplying carriers by a high electric field region provided for each of the pixels, an inter-pixel isolation section that isolates adjacent pixels on the semiconductor substrate on which the avalanche photodiode element is formed, and a first wiring layer that is laminated on a surface opposite to a light receiving surface of the semiconductor substrate so as to cover at least the high electric field region in a plan view and that is connected to a cathode of the avalanche photodiode element via a first electrode. the avalanche photodiode element has a first metal wiring connected to the anode of the avalanche photodiode element, and a second metal wiring provided in the first wiring layer and connected to the anode of the avalanche photodiode element via a second electrode, and in a cross-sectional view, the first metal wiring is provided between the second metal wiring within one pixel region , and the photodetector element is formed over a range wider than the high electric field region so as to cover at least all but a portion including a contact electrode for supplying a negative voltage to the high electric field region and a periphery of the contact electrode, and a polysilicon film which is a reflective film that reflects light is formed on the surface of the semiconductor substrate .

In one aspect of the present disclosure, a pixel array section includes a plurality of pixels arranged in an array, an avalanche photodiode element that multiplies carriers by a high electric field region provided for each pixel is provided on a semiconductor substrate, and an inter-pixel separation section separates the avalanche photodiode element from other adjacent pixels on the semiconductor substrate on which the avalanche photodiode element is formed. The first metal wiring is provided in a first wiring layer laminated on a surface opposite to the light receiving surface of the semiconductor substrate so as to cover at least the high electric field region in a plan view, and is connected to the cathode of the avalanche photodiode element via a first electrode. The second metal wiring is provided in the first wiring layer and connected to the anode of the avalanche photodiode element via a second electrode. In a cross-sectional view, the first metal wiring is provided between the second metal wirings in one pixel region, and a polysilicon film that is a reflective film that reflects light is formed on the surface of the semiconductor substrate, the polysilicon film being formed in a range wider than the high electric field region so as to cover at least the entire surface of the semiconductor substrate except for a contact electrode for supplying a negative voltage to the high electric field region and a portion including the periphery of the contact electrode .

According to one aspect of the present disclosure, it is possible to improve the characteristics of SPAD pixels.

1 is a block diagram showing a configuration example of an embodiment of a sensor chip to which the present technology is applied; FIG. 2 is a diagram showing a first example of a cross-sectional configuration of a SPAD pixel. FIG. 2 is a diagram showing a first example of a planar configuration in a wiring layer of a SPAD pixel. FIG. 13 is a diagram showing a second example of a cross-sectional configuration of a SPAD pixel. FIG. 13 is a diagram showing a second example of a planar configuration in a wiring layer of a SPAD pixel. FIG. 13 is a diagram showing a third example of a cross-sectional configuration of a SPAD pixel. FIG. 13 is a diagram showing a third example of a planar configuration in a wiring layer of a SPAD pixel. FIG. 13 is a diagram showing a fourth example of a cross-sectional configuration of a SPAD pixel. FIG. 13 is a diagram showing a fifth example of a cross-sectional configuration of a SPAD pixel. FIG. 13 is a diagram showing a fifth example of a planar configuration in a wiring layer of a SPAD pixel. FIG. 13 is a diagram showing a sixth example cross-sectional configuration of a SPAD pixel. FIG. 13 is a diagram showing a seventh example of a cross-sectional configuration of a SPAD pixel. FIG. 13 is a diagram showing an eighth example of a cross-sectional configuration of a SPAD pixel. FIG. 2 is a block diagram showing an example of the configuration of a range image sensor. FIG. 1 is a diagram showing an example of use of an image sensor.

Below, specific embodiments of the present technology will be described in detail with reference to the drawings.

<Sensor chip configuration example>

Figure 1 is a block diagram showing an example of the configuration of one embodiment of a sensor chip to which this technology is applied.

In FIG. 1, the sensor chip 11 is configured with a pixel array section 12 and a bias voltage application section 13.

The pixel array section 12 is a light receiving surface that receives light collected by an optical system (not shown), and has a plurality of SPAD pixels 21 arranged in a matrix. As shown on the right side of FIG. 1, the SPAD pixel 21 is configured with a SPAD element 31, a p-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 32, and a CMOS inverter 33.

The SPAD element 31 forms an avalanche multiplication region by applying a large negative voltage VBD to the cathode, and can avalanche multiply electrons generated by the incidence of one photon. When the voltage caused by the electrons avalanche multiplied by the SPAD element 31 reaches the negative voltage VBD, the p-type MOSFET 32 releases the electrons multiplied by the SPAD element 31 and performs quenching to return the voltage to the initial voltage. The CMOS inverter 33 shapes the voltage generated by the electrons multiplied by the SPAD element 31, and outputs a light receiving signal (APD OUT) in which a pulse waveform is generated starting from the arrival time of one photon.

The bias voltage application unit 13 applies a bias voltage to each of the multiple SPAD pixels 21 arranged in the pixel array unit 12.

The sensor chip 11 configured in this manner outputs a light reception signal for each SPAD pixel 21 and supplies it to a downstream calculation processing unit (not shown). For example, the calculation processing unit performs calculation processing to find the distance to the subject based on the timing at which a pulse indicating the arrival time of one photon is generated in each light reception signal, and finds the distance for each SPAD pixel 21. Then, based on these distances, a distance image is generated in which the distances to the subject detected by the multiple SPAD pixels 21 are arranged in a plane.

<First example of SPAD pixel configuration>

A first configuration example of a SPAD pixel 21 formed on the sensor chip 11 will be described with reference to Figures 2 and 3. Figure 2 shows a cross-sectional configuration example of a SPAD pixel 21, and Figure 3 shows a planar configuration example of the wiring layer of the SPAD pixel 21.

2, the sensor chip 11 has a laminated structure in which a sensor substrate 41, a sensor side wiring layer 42, and a logic side wiring layer 43 are laminated, and a logic circuit substrate (not shown) is laminated on the logic side wiring layer 43. The logic circuit substrate is formed with, for example, the bias voltage application unit 13 in FIG. 1, a p-type MOSFET 32, a CMOS inverter 33, and the like. For example, the sensor chip 11 can be manufactured by a manufacturing method in which the sensor side wiring layer 42 is formed on the sensor substrate 41, and the logic side wiring layer 43 is formed on the logic circuit substrate, and then the sensor side wiring layer 42 and the logic side wiring layer 43 are bonded at their bonding surfaces (surfaces indicated by dashed lines in FIG. 2).

The sensor substrate 41 is, for example, a semiconductor substrate formed by thinly slicing single crystal silicon, and the p-type or n-type impurity concentration is controlled, with a SPAD element 31 formed for each SPAD pixel 21. In addition, the surface facing downward of the sensor substrate 41 in FIG. 2 is the light receiving surface that receives light, and a sensor side wiring layer 42 is laminated on the surface opposite the light receiving surface.

The sensor side wiring layer 42 and the logic side wiring layer 43 are provided with wiring for supplying voltage to be applied to the SPAD element 31, wiring for extracting electrons generated by the SPAD element 31 from the sensor substrate 41, and the like.

The SPAD element 31 is composed of an N-well 51, a P-type diffusion layer 52, an N-type diffusion layer 53, a hole accumulation layer 54, a pinning layer 55, and a high-concentration P-type diffusion layer 56 formed on the sensor substrate 41. In the SPAD element 31, an avalanche multiplication region 57 is formed by a depletion layer formed in the region where the P-type diffusion layer 52 and the N-type diffusion layer 53 are connected.

The N-well 51 is formed by controlling the impurity concentration of the sensor substrate 41 to be of n-type, and forms an electric field that transfers electrons generated by photoelectric conversion in the SPAD element 31 to the avalanche multiplication region 57. Note that instead of the N-well 51, a P-well may be formed by controlling the impurity concentration of the sensor substrate 41 to be of p-type.

The P-type diffusion layer 52 is a dense P-type diffusion layer (P+) formed near the surface of the sensor substrate 41 on the back side (the lower side in FIG. 2) of the N-type diffusion layer 53, and is formed so as to cover almost the entire surface of the SPAD element 31.

The N-type diffusion layer 53 is a dense N-type diffusion layer (N+) formed near the surface of the sensor substrate 41 on the surface side (upper side in FIG. 2) of the P-type diffusion layer 52, and is formed so as to cover almost the entire surface of the SPAD element 31. In addition, the N-type diffusion layer 53 has a convex shape with a part of it extending to the surface of the sensor substrate 41 in order to connect to the contact electrode 71 for supplying a negative voltage to form the avalanche multiplication region 57.

The hole accumulation layer 54 is a P-type diffusion layer (P) formed to surround the side and bottom surfaces of the N-well 51, and accumulates holes. The hole accumulation layer 54 is also electrically connected to the anode of the SPAD element 31, allowing bias adjustment. This strengthens the hole concentration in the hole accumulation layer 54 and strengthens the pinning including the pinning layer 55, making it possible to suppress, for example, the generation of dark current.

The pinning layer 55 is a dense P-type diffusion layer (P+) formed on the surface outside the hole accumulation layer 54 (the back surface of the sensor substrate 41 or the side surface in contact with the insulating film 62), and like the hole accumulation layer 54, it suppresses, for example, the generation of dark current.

The high-concentration P-type diffusion layer 56 is a high-concentration P-type diffusion layer (P++) formed in the vicinity of the surface of the sensor substrate 41 so as to surround the outer periphery of the N-well 51, and is used to connect to the contact electrode 72 for electrically connecting the hole accumulation layer 54 to the anode of the SPAD element 31.

The avalanche multiplication region 57 is a high electric field region formed at the interface between the P-type diffusion layer 52 and the N-type diffusion layer 53 by a large negative voltage applied to the N-type diffusion layer 53, and multiplies the electrons (e-) generated by one photon incident on the SPAD element 31.

In addition, in the sensor chip 11, each SPAD element 31 is insulated and separated by a pixel separation section 63 having a double structure of a metal film 61 and an insulating film 62 formed between adjacent SPAD elements 31. For example, the pixel separation section 63 is formed so as to penetrate from the back surface to the front surface of the sensor substrate 41.

The metal film 61 is a film formed of a metal (e.g., tungsten) that reflects light, and the insulating film 62 is a film with insulating properties such as SiO2. For example, the inter-pixel separation section 63 is formed by embedding the metal film 61 in the sensor substrate 41 so that the surface of the metal film 61 is covered with the insulating film 62, and the inter-pixel separation section 63 electrically and optically separates the adjacent SPAD elements 31.

Contact electrodes 71 to 73, metal wiring 74 to 76, contact electrodes 77 to 79, and metal pads 80 to 82 are formed on the sensor side wiring layer 42.

The contact electrode 71 connects the N-type diffusion layer 53 to the metal wiring 74, the contact electrode 72 connects the high-concentration P-type diffusion layer 56 to the metal wiring 75, and the contact electrode 73 connects the metal film 61 to the metal wiring 76.

For example, as shown in FIG. 3, the metal wiring 74 is formed wider than the avalanche multiplication region 57 so as to cover at least the avalanche multiplication region 57. The metal wiring 74 reflects the light that has passed through the SPAD element 31 back to the SPAD element 31, as shown by the hollow arrow in FIG. 2.

Metal wiring 75 is formed so as to overlap with high concentration P-type diffusion layer 56 so as to surround the outer periphery of metal wiring 74, for example, as shown in FIG. 3. Metal wiring 76 is formed so as to connect to metal film 61 at the four corners of SPAD pixel 21, for example, as shown in FIG. 3.

Contact electrode 77 connects metal wiring 74 to metal pad 80, contact electrode 78 connects metal wiring 75 to metal pad 81, and contact electrode 79 connects metal wiring 76 to metal pad 82.

Metal pads 80 to 82 are used to electrically and mechanically connect to metal pads 101 to 103 formed on the logic side wiring layer 43 by the metal (Cu) that forms each of them.

Electrode pads 91 to 93, an insulating layer 94, contact electrodes 95 to 100, and metal pads 101 to 103 are formed on the logic side wiring layer 43.

The electrode pads 91 to 93 are each used to connect to a logic circuit board (not shown), and the insulating layer 94 insulates the electrode pads 91 to 93 from each other.

Contact electrodes 95 and 96 connect electrode pad 91 to metal pad 101, contact electrodes 97 and 98 connect electrode pad 92 to metal pad 102, and contact electrodes 99 and 100 connect electrode pad 93 to metal pad 103.

Metal pad 101 is bonded to metal pad 80, metal pad 102 is bonded to metal pad 81, and metal pad 103 is bonded to metal pad 82.

With this wiring structure, for example, the electrode pad 91 is connected to the N-type diffusion layer 53 via the contact electrodes 95 and 96, the metal pad 101, the metal pad 80, the contact electrode 77, the metal wiring 74, and the contact electrode 71. Therefore, in the SPAD pixel 21, the large negative voltage applied to the N-type diffusion layer 53 can be supplied from the logic circuit board to the electrode pad 91.

The electrode pad 92 is connected to the high-concentration P-type diffusion layer 56 via the contact electrodes 97 and 98, the metal pad 102, the metal pad 81, the contact electrode 78, the metal wiring 75, and the contact electrode 72. Therefore, in the SPAD pixel 21, the anode of the SPAD element 31 electrically connected to the hole accumulation layer 54 is connected to the electrode pad 92, making it possible to adjust the bias for the hole accumulation layer 54 via the electrode pad 92.

Furthermore, the electrode pad 93 is connected to the metal film 61 via the contact electrodes 99 and 100, the metal pad 103, the metal pad 82, the contact electrode 79, the metal wiring 76, and the contact electrode 73. Therefore, in the SPAD pixel 21, the bias voltage supplied to the electrode pad 93 from the logic circuit board can be applied to the metal film 61.

As described above, the SPAD pixel 21 has metal wiring 74 formed wider than the avalanche multiplication region 57 so as to cover at least the avalanche multiplication region 57, and the metal film 61 formed to penetrate the sensor substrate 41. That is, the SPAD pixel 21 is formed to have a reflective structure in which the metal wiring 74 and metal film 61 surround all of the SPAD element 31 except for the light incidence surface. As a result, the SPAD pixel 21 can prevent the occurrence of optical crosstalk and improve the sensitivity of the SPAD element 31 by the effect of reflecting light by the metal wiring 74 and metal film 61.

The SPAD pixel 21 also has a hole accumulation layer 54 surrounding the sides and bottom of the N-well 51, and the hole accumulation layer 54 is electrically connected to the anode of the SPAD element 31, allowing bias adjustment. Furthermore, the SPAD pixel 21 can form an electric field that assists carriers into the avalanche multiplication region 57 by applying a bias voltage to the metal film 61 of the inter-pixel separator 63.

The SPAD pixel 21 configured as described above prevents crosstalk from occurring and improves the sensitivity of the SPAD element 31, thereby improving its characteristics.

<Second example of SPAD pixel configuration>

A sensor chip 11A in which a SPAD pixel 21A of a second configuration example is formed will be described with reference to Figures 4 and 5. Figure 4 shows a cross-sectional configuration example of the SPAD pixel 21A, and Figure 5 shows a planar configuration example of the wiring layer of the SPAD pixel 21A. Note that in the sensor chip 11A and SPAD pixel 21A shown in Figures 4 and 5, components common to the sensor chip 11 and SPAD pixel 21 of Figures 2 and 3 are given the same reference numerals, and detailed descriptions thereof will be omitted.

As shown in FIG. 4, the SPAD pixel 21A of the sensor chip 11A has a different configuration from the SPAD pixel 21 of the sensor chip 11 in FIG. 2 in that an inner lens 111 is arranged in the sensor side wiring layer 42A.

The inner lens 111 is disposed between the sensor substrate 41A and the metal wiring 74, and is a convex-shaped focusing lens that is convex toward the sensor substrate 41A. For example, the inner lens 111 is formed so as to focus the reflected light reflected by the metal wiring 74 toward the center of the SPAD element 31A.

In addition, in the SPAD pixel 21A, in order to connect the N-type diffusion layer 53A and the metal wiring 74 while avoiding the inner lens 111, four contact electrodes 71A are arranged at the four corners outside the inner lens 111, as shown in FIG. 5. In addition, the N-type diffusion layer 53A formed in the SPAD element 31A of the sensor substrate 41A has a convex shape such that a part of it is formed on the surface of the sensor substrate 41 so as to correspond to the position of the contact electrodes 71A.

The SPAD pixel 21A is configured in this manner, and for example, light that is incident on the SPAD element 31A from a certain degree of oblique direction and passes through is focused by the inner lens 111 toward the center of the SPAD element 31A when reflected by the metal wiring 74. Therefore, the SPAD pixel 21A can improve the light-focusing efficiency by the inner lens 111, preventing the occurrence of crosstalk and improving the sensitivity of the SPAD element 31A, thereby improving the characteristics.

<Third example of SPAD pixel configuration>

With reference to Figures 6 and 7, a sensor chip 11B in which a SPAD pixel 21B of a third configuration example is formed will be described. Figure 6 shows a cross-sectional configuration example of the SPAD pixel 21B, and Figure 7 shows a planar configuration example of the wiring layer of the SPAD pixel 21B. Note that in the sensor chip 11B and SPAD pixel 21B shown in Figures 6 and 7, components common to the sensor chip 11 and SPAD pixel 21 in Figures 2 and 3 are given the same reference numerals, and detailed descriptions thereof will be omitted.

As shown in FIG. 6, the SPAD pixel 21B of the sensor chip 11B has a different configuration from the SPAD pixel 21 of the sensor chip 11 in FIG. 2 in that a light-shielding film 121 is disposed on the sensor side wiring layer 42B.

The light-shielding film 121 is disposed between the metal wiring 74 and 75 and the metal pads 80 to 82, and blocks light that passes through the gaps between the metal wiring 74 and 75. As shown in FIG. 7, the light-shielding film 121 has openings at the locations where the contact electrodes 77 and 78 penetrate, and is formed over almost the entire surface except for the openings.

The light-shielding film 121 can be formed of a light-reflecting metal (e.g., tungsten) like the metal film 61, and reflects light that has passed through the SPAD element 31 and the gap between the metal wirings 74 and 75, as shown by the white arrow in Figure 6.

The inter-pixel separation portion 63B of the SPAD pixel 21B is formed so that the metal film 61B and the insulating film 62B protrude through the sensor substrate 41 toward the sensor-side wiring layer 42B and reach the light-shielding film 121. The metal film 61B is electrically connected to the light-shielding film 121. The contact electrode 79B is formed to connect between the metal pad 82 and the light-shielding film 121, and a bias voltage is applied to the metal film 61B via the light-shielding film 121.

SPAD pixel 21B is configured in this manner, and metal film 61B and light-shielding film 121 are formed to cover the layer in which metal wiring 74 and 75 are formed, thereby ensuring that light transmitted through SPAD element 31 is reflected. Therefore, SPAD pixel 21B can prevent light from entering other adjacent SPAD elements 31 by metal film 61B and light-shielding film 121, preventing crosstalk from occurring and improving the sensitivity of SPAD element 31, thereby improving characteristics.

<Fourth example of SPAD pixel configuration>

With reference to FIG. 8, a sensor chip 11C in which a SPAD pixel 21C of a fourth configuration example is formed will be described. FIG. 8 shows a cross-sectional configuration example of a SPAD pixel 21C. Note that in the sensor chip 11C and SPAD pixel 21C shown in FIG. 8, components common to the sensor chip 11 and SPAD pixel 21 in FIG. 2 are given the same reference numerals, and detailed descriptions thereof will be omitted.

As shown in FIG. 8, the SPAD pixel 21C of the sensor chip 11C has a different configuration from the SPAD pixel 21 of the sensor chip 11 in FIG. 2 in that an N-type region 131 is formed in the SPAD element 31C of the sensor substrate 41C.

The N-type region 131 is formed so as to contact the P-type diffusion layer 52 at the center of the SPAD element 31C, and forms a potential gradient that makes it easier for carriers (electrons) generated in the SPAD element 31C to drift from the periphery toward the center. In other words, in the SPAD element 31C, by forming the N-type region 131 by injecting N-type impurities into the N-well 51, an electric field that collects carriers is formed because the element is originally N-type.

Furthermore, in the SPAD element 31C, by applying a bias voltage to the metal film 61 of the pixel separation portion 63, the hole accumulation layer 54 and the N-well 51 are pulled to the potential of the bias voltage, so that a stronger potential well can be formed. This allows the SPAD element 31C to strengthen the electric field that drifts carriers toward the N-type region 131 more than when such a potential is not applied. Therefore, the SPAD element 31C makes it easier for carriers to gather in the N-type region 131, and as a result, it is possible for electrons to reach the avalanche multiplication region 57 efficiently.

The pixel separation section 63 can have a double reflection structure by being formed from a metal film 61 and an insulating film 62. By adjusting the bias voltage applied to the metal film 61, a hole accumulation layer 54 that accumulates holes may be induced on the outer periphery of the SPAD element 31C.

SPAD pixel 21C is configured in this way, and for example, minute carriers generated by light reflected by metal film 61 are captured as a signal by strengthening the potential gradient in N-type region 131 by applying a bias voltage to metal film 61. Therefore, SPAD pixel 21C can improve its sensitivity by capturing such minute carriers, thereby improving its characteristics.

<Fifth example of SPAD pixel configuration>

A sensor chip 11D in which a SPAD pixel 21D of a fifth configuration example is formed will be described with reference to Figures 9 and 10. Figure 9 shows a cross-sectional configuration example of the SPAD pixel 21D, and Figure 10 shows a planar configuration example of the wiring layer of the SPAD pixel 21D. Note that in the sensor chip 11D and SPAD pixel 21D shown in Figures 9 and 10, components common to the sensor chip 11 and SPAD pixel 21 of Figures 2 and 3 are given the same reference numerals, and detailed descriptions thereof will be omitted.

As shown in Figures 9 and 10, the SPAD pixel 21D of the sensor chip 11D has a different configuration from the SPAD pixel 21 of the sensor chip 11 in Figures 2 and 3 in that reflective films 141 and 142 are arranged on the sensor side wiring layer 42D.

The reflective films 141 and 142 are, for example, polysilicon films formed on the surface of the sensor substrate 41 and used as gate electrodes of transistors, and have the property of reflecting light. As shown in FIG. 10, it is preferable that the reflective film 141 is formed over an area wider than the avalanche multiplication region 57 so that at least the avalanche multiplication region 57 is covered by the reflective film 141 in a plan view. In other words, the reflective film 141 is formed so as to overlap the metal wiring 74 in a plan view.

The SPAD pixel 21D is configured in this manner, and light that passes through the SPAD element 31 is reflected by the reflective films 141 and 142, which are positioned closer to the sensor substrate 41 than the metal wiring 74, reducing the amount of light that passes through to the sensor side wiring layer 42D. Therefore, the SPAD pixel 21D can effectively contain light by the reflective films 141 and 142, preventing the occurrence of crosstalk and improving the sensitivity of the SPAD element 31, thereby improving the characteristics.

<Sixth example of SPAD pixel configuration>

With reference to FIG. 11, a sensor chip 11E in which a SPAD pixel 21E of a sixth configuration example is formed will be described. FIG. 11 shows a cross-sectional configuration example of a SPAD pixel 21E. Note that in the sensor chip 11E and SPAD pixel 21E shown in FIG. 11, components common to the sensor chip 11 and SPAD pixel 21 in FIG. 2 are given the same reference numerals, and detailed descriptions thereof will be omitted.

As shown in FIG. 11, the SPAD pixel 21E of the sensor chip 11E has a different configuration from the SPAD pixel 21 of the sensor chip 11 in FIG. 2 in that a hole accumulation layer 151 is formed on the surface of the sensor substrate 41E.

In addition, in the SPAD pixel 21E, reflective films 141 and 142 are arranged in the same manner as in the SPAD pixel 21D shown in FIG. 10, and wiring for applying a bias voltage to the reflective film 141 and the like are formed in the sensor side wiring layer 42E and the logic side wiring layer 43E.

That is, in the sensor side wiring layer 42E, the contact electrode 152, the metal wiring 153, the contact electrode 154, and the metal pad 155 are connected to each other, and the contact electrode 152 is connected to the reflective film 141. In addition, in the logic side wiring layer 43E, the electrode pad 156, the contact electrodes 157 and 158, and the metal pad 159 are connected to each other, and the metal pad 159 and the metal pad 155 are joined.

Therefore, in the SPAD pixel 21E, a bias voltage supplied to the electrode pad 156 is applied to the reflective film 141, and a hole accumulation layer 151 that accumulates holes is formed between the reflective film 141 and the N-type diffusion layer 53 on the surface of the sensor substrate 41E.

SPAD pixel 21E is configured in this manner, and light transmitted through SPAD element 31E is reflected by reflective films 141 and 142, while hole accumulation layer 151 suppresses dark current by avoiding exposure to the surface of avalanche multiplication region 57. Therefore, SPAD pixel 21E prevents crosstalk from occurring, improves the sensitivity of SPAD element 31, and suppresses dark current, thereby improving characteristics.

<Seventh example of SPAD pixel configuration>

With reference to FIG. 12, a sensor chip 11F in which a SPAD pixel 21F of a seventh configuration example is formed will be described. FIG. 12 shows a cross-sectional configuration example of a SPAD pixel 21F. Note that in the sensor chip 11F and SPAD pixel 21F shown in FIG. 12, components common to the sensor chip 11 and SPAD pixel 21 in FIG. 2 are given the same reference numerals, and detailed descriptions thereof will be omitted.

As shown in FIG. 12, the SPAD pixel 21F of the sensor chip 11F has a different configuration from the SPAD pixel 21 of the sensor chip 11 in FIG. 2 in that the sensor side wiring layer 42F has a two-layer wiring structure.

That is, while the sensor side wiring layer 42 of the sensor chip 11 in FIG. 2 has a single-layer wiring structure in which the metal wires 74 to 76 are arranged, the sensor side wiring layer 42F of the sensor chip 11F has a two-layer wiring structure in which the metal wires 74 to 76 and the metal wires 163 to 165 are arranged in a stacked manner. Note that a multi-layer wiring structure of two or more layers may also be adopted.

The metal wirings 74 to 76 and the metal wirings 163 to 165 are formed so that the gaps between the metal wirings 74 to 76 do not overlap the gaps between the metal wirings 163 to 165 in a plan view. That is, the metal wirings 74 to 76 and the metal wirings 163 to 165 are formed so as to be alternately multiplexed.

Furthermore, in SPAD pixel 21F, similar to SPAD pixel 21D in FIG. 9, reflective films 141 and 142 are laminated on the surface of the sensor substrate 41.

In addition, the sensor side wiring layer 42F of the sensor chip 11F is formed with contact electrodes 161 and 162 that connect the metal wiring 74 and the metal wiring 163, a contact electrode 166 that connects the metal pad 81 and the metal wiring 164, and a contact electrode 167 that connects the metal pad 82 and the metal wiring 165.

SPAD pixel 21F is configured in this manner, and light that passes through SPAD element 31 is reflected by reflective materials (i.e., metal wiring 74 to 76, metal wiring 163 to 165, and reflective films 141 and 142) that are formed in multiple layers in sensor-side wiring layer 42F so as to cover avalanche multiplication region 57. Therefore, SPAD pixel 21F can suppress diffraction and scattered reflection of light that passes through SPAD element 31, preventing the occurrence of crosstalk and improving the sensitivity of SPAD element 31, thereby improving characteristics.

<8th example of SPAD pixel configuration>

With reference to FIG. 13, a sensor chip 11G in which a SPAD pixel 21G of an eighth configuration example is formed will be described. FIG. 13 shows a cross-sectional configuration example of a SPAD pixel 21G. Note that in the sensor chip 11G and SPAD pixel 21G shown in FIG. 13, components common to the sensor chip 11 and SPAD pixel 21 in FIG. 2 are given the same reference numerals, and detailed descriptions thereof will be omitted.

As shown in FIG. 13, the SPAD pixel 21G of the sensor chip 11G has a different configuration from the SPAD pixel 21 of the sensor chip 11 in FIG. 2 in that the height of the inter-pixel separation portion 63G is formed to coincide with the surface (bulk surface) of the sensor substrate 41.

For example, in the SPAD pixel 21 of FIG. 2, the inter-pixel separation portion 63 is formed so as to protrude slightly from the surface of the sensor substrate 41 into the sensor-side wiring layer 42. In contrast, in the SPAD pixel 21G, the metal film 61G and insulating film 62G constituting the inter-pixel separation portion 63G are formed so as to coincide with the surface of the sensor substrate 41.

In this way, if the occurrence of crosstalk can be sufficiently suppressed even if the height of the inter-pixel separation portion 63G is formed low, it may be formed low enough to be flush with the surface of the sensor substrate 41. In other words, the inter-pixel separation portion 63 does not need to be formed so as to protrude from the surface of the sensor substrate 41 into the sensor side wiring layer 42.

Even in the SPAD pixel 21G formed in this manner, the light passing through the SPAD element 31 is reflected by the metal wiring 74, which prevents crosstalk from occurring and improves the sensitivity of the SPAD element 31, thereby improving the characteristics.

As with SPAD pixel 21G, a configuration in which the height of inter-pixel separation portion 63G is formed to coincide with the surface of sensor substrate 41 may be used in combination with the configurations of SPAD pixels 21A to 31F described above.

<Example of imaging device configuration>

Figure 14 is a block diagram showing an example of the configuration of a range image sensor, which is an electronic device that uses a sensor chip 11.

As shown in FIG. 14, the distance image sensor 201 is configured to include an optical system 202, a sensor chip 203, an image processing circuit 204, a monitor 205, and a memory 206. The distance image sensor 201 can obtain a distance image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected from a light source device 211 toward the subject and reflected by the surface of the subject.

The optical system 202 is composed of one or more lenses, and guides image light (incident light) from a subject to the sensor chip 203, forming an image on the light receiving surface (sensor portion) of the sensor chip 203.

The sensor chip 11 of each of the above-mentioned embodiments is applied as the sensor chip 203, and a distance signal indicating the distance calculated from the light receiving signal (APD OUT) output from the sensor chip 203 is supplied to the image processing circuit 204.

The image processing circuit 204 performs image processing to construct a distance image based on the distance signal supplied from the sensor chip 203, and the distance image (image data) obtained by this image processing is supplied to the monitor 205 for display, or supplied to the memory 206 for storage (recording).

In the distance image sensor 201 configured in this manner, by applying the sensor chip 11 described above, it is possible to obtain, for example, a more accurate distance image as the characteristics of the SPAD pixel 21 improve.

<Examples of using image sensors>

Figure 15 shows an example of using the image sensor (distance image sensor) described above.

The image sensor described above can be used in a variety of cases, for example, to sense light such as visible light, infrared light, ultraviolet light, and X-rays, as follows:

- Devices that take images for viewing, such as digital cameras and mobile devices with camera functions; - Devices for traffic purposes, such as in-vehicle sensors that take images of the front and rear of a car, the surroundings, and the interior of the car for safe driving such as automatic stopping and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure the distance between vehicles, etc.; - Devices for home appliances such as TVs, refrigerators, and air conditioners that take images of users' gestures and operate devices in accordance with those gestures; - Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light; - Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication; - Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp; - Devices for sports purposes, such as action cameras and wearable cameras for sports purposes, etc.; - Devices for agricultural purposes, such as cameras for monitoring the condition of fields and crops.

The present technology can also be configured as follows.
(1)
a pixel array section in which a plurality of pixels are arranged in an array;
an avalanche photodiode element that multiplies carriers by a high electric field region provided for each pixel;
an inter-pixel isolation portion that insulates and isolates adjacent pixels on a semiconductor substrate on which the avalanche photodiode element is formed;
a metal wiring provided in a wiring layer laminated on a surface opposite to the light receiving surface of the semiconductor substrate so as to cover at least the high electric field region.
(2)
The sensor chip described in (1) above further comprises an inner lens provided between the metal wiring and the semiconductor substrate, which focuses light that passes through the avalanche photodiode element and is reflected by the metal wiring onto the center of the avalanche photodiode element.
(3)
The sensor chip according to (1) or (2) above, wherein the inter-pixel isolation portion is formed so as to penetrate from a rear surface of the semiconductor substrate to the front surface.
(4)
The inter-pixel isolation portion has a double structure made of a light-reflecting metal film and an insulating film having insulating properties, and is embedded in the semiconductor substrate so that the surface of the metal film is covered with the insulating film. The sensor chip described in any of (1) to (3) above.
(5)
The sensor chip described in any one of (1) to (4) above, wherein a hole accumulation layer that accumulates holes is induced on the outer periphery of the avalanche photodiode element by applying a voltage to a metal film embedded in the semiconductor substrate as the inter-pixel isolation portion.
(6)
The sensor chip according to any one of (1) to (5) above, wherein an electric field that causes carriers to drift is strengthened by applying a voltage to a metal film that is embedded in the semiconductor substrate as the pixel isolation portion.
(7)
The sensor chip according to any one of (1) to (6) above, further comprising a reflective film that reflects light and is formed on the surface of the semiconductor substrate so as to cover at least the high electric field region.
(8)
The sensor chip according to (7) above, wherein a hole accumulation layer that accumulates holes is formed in the vicinity of the surface of the semiconductor substrate by applying a voltage to the reflective film.
(9)
The sensor chip according to (7) or (8) above, wherein the reflective film is formed so as to overlap the first to third metal wirings when viewed in a plan view.
(10)
The sensor chip according to any one of (1) to (9) above, wherein the height of the inter-pixel separation portion is formed so as to be substantially equal to the surface of the semiconductor substrate.
(11)
a pixel array section in which a plurality of pixels are arranged in an array;
an avalanche photodiode element that multiplies carriers by a high electric field region provided for each pixel;
an inter-pixel isolation portion that insulates and isolates adjacent pixels on a semiconductor substrate on which the avalanche photodiode element is formed;
and metal wiring provided in a wiring layer laminated on a surface opposite to the light receiving surface of the semiconductor substrate so as to cover at least the high electric field region.

Note that this embodiment is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of this disclosure.

11 sensor chip, 12 pixel array section, 13 bias voltage application section, 21 SPAD pixel, 31 SPAD element, 32 p-type MOSFET 32, 33 CMOS inverter, 41 sensor substrate, 42 sensor side wiring layer, 43 logic side wiring layer, 51 N well, 52 P-type diffusion layer, 53 N-type diffusion layer, 54 hole accumulation layer, 55 pinning layer, 56 high concentration P-type diffusion layer, 57 avalanche multiplication region, 61 metal film, 62 insulating film, 63 pixel separation section, 71 to 73 contact electrodes, 74 to 76 metal wiring, 77 to 79 contact electrodes, 80 to 82 metal pads, 91 to 93 electrode pads, 94 insulating layer, 95 to 100 contact electrodes, 101 to 103 metal pads

Claims (14)

a pixel array section in which a plurality of pixels are arranged in an array;
an avalanche photodiode element provided on a semiconductor substrate, the avalanche photodiode element multiplying carriers by a high electric field region provided for each pixel;
an inter-pixel isolation portion that isolates adjacent pixels from each other on the semiconductor substrate on which the avalanche photodiode element is formed;
a first metal wiring provided in a first wiring layer laminated on a surface of the semiconductor substrate opposite to the light receiving surface so as to cover at least the high electric field region in a plan view, the first metal wiring being connected to a cathode of the avalanche photodiode element via a first electrode;
a second metal wiring provided in the first wiring layer and connected to the anode of the avalanche photodiode element via a second electrode;
When viewed in cross section, the first metal wiring is provided between the second metal wirings within one pixel region ,
A polysilicon film is formed on the surface of the semiconductor substrate, the polysilicon film being a reflective film that reflects light and is formed in a range wider than the high electric field region so as to cover at least the area except for a contact electrode for supplying a negative voltage to the high electric field region and a portion including the periphery of the contact electrode.
Light detection element. The photodetector element according to claim 1, further comprising a third metal wiring provided in a second wiring layer so as to be staggered and multiplexed to fill a gap between the first metal wiring and the second metal wiring in a plan view. The photodetector element according to claim 2 , wherein the second wiring layer includes a plurality of the third metal wirings. 4. The photodetector element according to claim 3, wherein the first metal wiring, the second metal wiring and the plurality of third metal wirings are arranged such that, in a planar view, gaps provided between the first metal wiring and the second metal wiring and gaps provided between the plurality of third metal wirings do not overlap. The photodetector element according to claim 2 , wherein the first wiring layer is disposed between the semiconductor substrate and the second wiring layer. A hole accumulation layer that accumulates holes is formed in the vicinity of the surface of the semiconductor substrate by applying a voltage to the polysilicon film.
The photodetector element according to claim 1 . The reflective film is formed so as to overlap the first to third metal wirings when viewed in a plan view.
The photodetector element according to claim 6 . 2. The photodetector element according to claim 1, further comprising: an inner lens provided between the first metal wiring and the semiconductor substrate, the inner lens focusing light that passes through the avalanche photodiode element and is reflected by the first metal wiring at a center of the avalanche photodiode element. The photodetector element according to claim 1 , wherein the inter-pixel isolation portion is formed so as to penetrate the semiconductor substrate from a rear surface to the front surface. 2. The photodetector element according to claim 1, wherein the inter-pixel isolation portion has a double structure made of a light-reflecting metal film and an insulating film having insulating properties, and is formed by being embedded in the semiconductor substrate so that a surface of the metal film is covered with the insulating film. 2. The photodetector element according to claim 1, wherein a hole accumulation layer for accumulating holes is induced on an outer periphery of the avalanche photodiode element by applying a voltage to a metal film embedded in the semiconductor substrate as the inter-pixel isolation portion. The photodetector element according to claim 1 , wherein an electric field that causes carriers to drift is strengthened by applying a voltage to a metal film that is embedded in the semiconductor substrate as the inter-pixel isolation portion. The photodetector element according to claim 1 , wherein the inter-pixel isolation portion is formed so as to have a height substantially equal to a surface of the semiconductor substrate. a pixel array section in which a plurality of pixels are arranged in an array;
an avalanche photodiode element provided on a semiconductor substrate, the avalanche photodiode element multiplying carriers by a high electric field region provided for each pixel;
an inter-pixel isolation portion that isolates adjacent pixels from each other on the semiconductor substrate on which the avalanche photodiode element is formed;
a first metal wiring provided in a first wiring layer laminated on a surface of the semiconductor substrate opposite to the light receiving surface so as to cover at least the high electric field region in a plan view, the first metal wiring being connected to a cathode of the avalanche photodiode element via a first electrode;
a second metal wiring provided in the first wiring layer and connected to the anode of the avalanche photodiode element via a second electrode;
When viewed in cross section, the first metal wiring is provided between the second metal wirings within one pixel region ,
A polysilicon film is formed on the surface of the semiconductor substrate, the polysilicon film being a reflective film that reflects light and is formed in a range wider than the high electric field region so as to cover at least the area except for a contact electrode for supplying a negative voltage to the high electric field region and a portion including the periphery of the contact electrode.
An electronic device equipped with a light detection element.

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