JP7512116B2 - Magnetic memory - Google Patents

Description

The present invention relates to a magnetic memory.

Attention is being focused on next-generation non-volatile memory to replace flash memory and other memory devices, which are reaching the limits of miniaturization. For example, MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistance Random Access Memory), and PCRAM (Phase Change Random Access Memory) are known as next-generation non-volatile memories.

MRAM is a memory device that uses a magnetoresistive element. The resistance value of the magnetoresistive element changes depending on the difference in the relative angle between the magnetization directions of the two magnetic films. MRAM stores the resistance value of the magnetoresistive element as data.

Some memory devices have a reference element to improve data reliability (for example, see Patent Document 1). By comparing the resistance of the reference element and the memory element, it is possible to prevent erroneous writing, erroneous reading, and the like.

Patent No. 6510758

The reference element is used to refer to the data. If the resistance of the reference element changes, the data standard changes and the reliability of the data decreases.

The present invention was made in consideration of the above problems, and aims to provide a magnetic memory with high data reliability.

(1) A magnetic memory according to a first aspect includes an array region including a memory element, a reference region including a reference element, and a read circuit connected to the array region and the reference region and comparing a signal from the array region with a signal from the reference region, the memory element and the reference element each include a memory layer including a ferromagnetic material, a reference layer including a ferromagnetic material, and a spacer layer between the memory layer and the reference layer, the reference layer has, in order from the side closest to the memory layer, a first layer, a nonmagnetic layer, and a second layer, and the reference element and the memory element have different ratios of the sum of the thicknesses of the magnetic layers in the second layer to the sum of the thicknesses of the magnetic layers in the first layer.

(2) In the magnetic memory according to the above aspect, the value obtained by dividing the thickness of the second magnetic layer by the thickness of the first magnetic layer may be greater for the reference element than for the memory element.

(3) In the magnetic memory according to the above aspect, the memory element and the reference element each have a wiring layer on the opposite side of the memory layer to the spacer layer, and the width of the wiring layer in the reference element may be wider than the width of the wiring layer in the memory element.

(4) In the magnetic memory according to the above aspect, the leakage magnetic field from the reference layer of the reference element may be greater than the coercivity of the memory layer of the reference element.

(5) In a plan view of the magnetic memory according to the above aspect seen from the stacking direction, the maximum width of the memory layer of the reference element may be wider than the maximum width of the memory element.

(6) In a plan view of the magnetic memory according to the above aspect from the stacking direction, the maximum width of the memory layer of the reference element may be greater than 20 nm.

(7) In a plan view of the magnetic memory according to the above aspect from the stacking direction, the maximum width of the memory element may be 20 nm or less.

(8) In the magnetic memory according to the above aspect, the reference region may have a plurality of reference elements, the reference region may have a plurality of first element groups in which a plurality of reference elements are arranged in series, and the plurality of first element groups may each be arranged in parallel.

(9) In the magnetic memory according to the above aspect, the reference region may have a plurality of reference elements, the reference region may have a plurality of second element groups in which the plurality of reference elements are arranged in parallel, and the plurality of second element groups may each be arranged in series.

(10) In the magnetic memory according to the above aspect, the array region and the reference region may each be connected to a power supply, and the read voltage applied to the reference region may be higher than the read voltage applied to the array region.

(11) In the magnetic memory according to the above aspect, the easy magnetization axes of the memory layer and the reference layer are in the stacking direction, the value obtained by dividing the thickness of the second magnetic layer by the thickness of the first magnetic layer is larger in the reference element than in the memory element, and when reading data, the reference element may cause a read current to flow from the reference layer to the memory layer.

(12) In the magnetic memory according to the above aspect, the easy magnetization axes of the memory layer and the reference layer are in the stacking direction, the value obtained by dividing the thickness of the second magnetic layer by the thickness of the first magnetic layer is larger in the memory element than in the reference element, and when reading data, the reference element may cause a read current to flow from the memory layer to the reference layer.

(13) In the magnetic memory according to the above aspect, the easy magnetization axes of the memory layer and the reference layer are in an in-plane direction intersecting the stacking direction, the value obtained by dividing the thickness of the magnetic layer of the second layer by the thickness of the magnetic layer of the first layer is larger for the reference element than for the memory element, and when reading data, the reference element may cause a read current to flow from the memory layer to the reference layer.

(14) In the magnetic memory according to the above aspect, the magnetization easy axes of the memory layer and the reference layer are in an in-plane direction intersecting the stacking direction, the value obtained by dividing the thickness of the magnetic layer of the second layer by the thickness of the magnetic layer of the first layer is larger in the memory element than in the reference element, and when reading data, the reference element may cause a read current to flow from the reference layer to the memory layer.

The magnetic memory described above has high data reliability.

1 is a block diagram of a magnetic memory according to a first embodiment. FIG. 4 is a circuit diagram of an array region and a reference region according to the first embodiment. 4 is a cross-sectional view of an array region and a reference region according to the first embodiment. FIG. 2 is a cross-sectional view of a memory element in an array region according to the first embodiment. FIG. 4 is a cross-sectional view of a reference layer of the memory element according to the first embodiment. 2 is a plan view of a memory element in an array region according to the first embodiment. FIG. 4 is a cross-sectional view of a reference element in a reference region according to the first embodiment. FIG. FIG. 2 is a plan view of a reference element in a reference region according to the first embodiment. FIG. 11 is a circuit diagram of another example of the array region and the reference region according to the first embodiment. FIG. 2 is a cross-sectional view of a first example of a series connection of reference elements. FIG. 11 is a cross-sectional view of a second example of a series connection of reference elements. FIG. 11 is a cross-sectional view of a third example of a series connection of reference elements. FIG. 11 is a cross-sectional view of a fourth example of a series connection of reference elements. FIG. 11 is a cross-sectional view of a first example of a parallel connection of reference elements. FIG. 11 is a cross-sectional view of a second example of a parallel connection of reference elements. FIG. 11 is a cross-sectional view of a third example of a parallel connection of reference elements. FIG. 11 is a cross-sectional view of a fourth example of a parallel connection of reference elements. FIG. 13 is a cross-sectional view of a fifth example of a parallel connection of reference elements. 13 is a cross-sectional view of a reference element in a reference region according to a first modified example. FIG. FIG. 13 is a cross-sectional view of a reference element in a reference region according to a second modified example. FIG. 13 is a cross-sectional view of a reference element in a reference region according to a third modified example.

The present embodiment will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic parts in an enlarged scale for the sake of convenience in order to make the features easier to understand, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited to them. Appropriate changes can be made within the scope of the effects of the present invention.

First, let us define the directions. One direction on one surface of a substrate Sub (see FIG. 3) described later is the x-direction, and the direction perpendicular to the x-direction is the y-direction. The x-direction is, for example, the row direction in which magnetoresistance effect elements are arranged in a magnetic memory described later, and is the direction in which the wiring layers of the magnetoresistance effect elements extend. The y-direction is, for example, the column direction in which magnetoresistance effect elements are arranged in a magnetic memory described later. The z-direction is a direction perpendicular to the x-direction and the y-direction. The z-direction is an example of a stacking direction. Hereinafter, the +z direction may be expressed as "up" and the -z direction as "down". Up and down do not necessarily coincide with the direction in which gravity is applied.

In this specification, "extending in a first direction" means that the length in the first direction is longer than the length in any other direction. In this specification, "connection" is not limited to direct connection, but also includes connection via a layer.

"First embodiment"
1 is a block diagram of a magnetic memory 200 according to a first embodiment. The magnetic memory 200 has an array area MA, a reference area RA, and a peripheral circuit area PC. Magnetoresistance effect elements are integrated in the array area MA and the reference area RA.

The peripheral circuit area PC has a control circuit that controls the operation of the array area MA and the reference area RA. The peripheral circuit area PC is, for example, on the side of the array area MA and the reference area RA in the x-direction or y-direction. The peripheral circuit area PC has, for example, a write circuit WC and a read circuit RC.

The write circuit WC controls the operation of writing information to the magnetoresistive elements in the array area MA. The write circuit WC includes, for example, a power supply, a CPU (Central Processing Unit), a controller, and a data latch. The data latch calculates signals and temporarily holds them for each page.

The read circuit RC controls the operation of reading information from the magnetoresistance effect elements in the array area MA or reference area RA. The read circuit WC includes, for example, a power supply P, a CPU (Central Processing Unit), a controller, a data latch, and a sense amplifier SA. The sense amplifier SA compares a signal from the array area MA with a signal from the reference area RA. The signal is, for example, the combined resistance of the magnetoresistance effect elements belonging to the reference area RA, the potential of the reference area RA, etc. The sense amplifier SA is connected to the array area MA and the reference area RA.

FIG. 2 is a circuit diagram of the array area MA and reference area RA according to the first embodiment. The array area MA and reference area RA have magnetoresistive effect elements arranged in a matrix, for example. Hereinafter, the magnetoresistive effect element belonging to the array area MA will be referred to as the memory element 100, and the magnetoresistive effect element belonging to the reference area RA will be referred to as the reference element 101.

The array region MA shown in FIG. 2 has, for example, a plurality of memory elements 100, a plurality of read transistors RTr, and a plurality of common transistors CTr. The plurality of memory elements 100 are arranged, for example, in a matrix. The read transistors RTr and the common transistors CTr are each connected to, for example, each of the memory elements 100.

The reference region RA shown in FIG. 2 has, for example, a plurality of reference elements 101, a plurality of read transistors RTr, and a plurality of common transistors CTr. The reference region RA has, for example, a plurality of first element groups EG1 in which a plurality of reference elements 101 are connected in series, and the plurality of first element groups EG1 are each arranged in parallel. The plurality of reference elements 101 are, for example, arranged in a matrix. The read transistors RTr and the common transistors CTr are each connected to, for example, each of the reference elements 101.

The memory element 100 and the reference element 101 are each connected to a write transistor WTr, a read transistor RTr, and a common transistor CTr.

The write transistor WTr is connected to a write wiring WL. The write wiring WL is a wiring through which a current flows when data is written to the memory element 100. For example, the write wiring WL is connected across each of the memory elements 100 belonging to the same column or row. The write wiring WL may be connected to each of the reference elements 101 belonging to the same column or row. The write transistor WTr, together with the common transistor CTr, controls the write current flowing along the wiring layers 20, 40. The write transistor WTr shown in FIG. 2 belongs to the peripheral circuit area PC. The write transistor WTr is disposed between the write wiring WL and the wiring layer 20, and may belong to the array area MA or the reference area RA.

The read transistor RTr is connected to the read wiring RL. The read wiring RL is electrically connected to the stack 10 of the memory element 100 or the stack 30 of the reference element 101. The read wiring RL is connected across each of the memory elements 100 or the reference elements 101 belonging to the same column or row. The read transistor RTr, together with the common transistor CTr, controls the current flowing in the stacking direction of the stacks 10, 30. The read transistor RTr is disposed between the read wiring RL and the stacks 10, 30, respectively. The read transistor RTr is disposed at one end of the read wiring RL and may belong to the peripheral circuit region PC.

The common transistor CTr is connected to a common wiring CL. The common transistor CTr controls the write current that flows along the wiring layers 20, 40 when writing data, and controls the current that flows in the stacking direction of the stacks 10, 30 when reading data. The common wiring CL is connected across each of the memory elements 100 or reference elements 101 that belong to the same column or row. The common transistor CTr is disposed between the common wiring CL and the wiring layers 20, 40, respectively. The common transistor CTr is disposed at one end of the common wiring CL, and may belong to the peripheral circuit region PC.

The write transistor WTr, the read transistor RTr, and the common transistor CTr are, for example, field effect transistors. The gate electrodes of the write transistor WTr, the read transistor RTr, and the common transistor CTr are, for example, connected to the write circuit WC or the read circuit RC. The write transistor WTr, the read transistor RTr, and the common transistor CTr may be replaced with other switching elements. The switching elements are, for example, an element that uses a phase change of a crystal layer such as an Ovonic Threshold Switch (OTS), an element that uses a change in band structure such as a metal-insulator transition (MIT) switch, an element that uses a breakdown voltage such as a Zener diode and an avalanche diode, and an element whose conductivity changes with a change in atomic position.

Figure 3 is a cross-sectional view of the array region MA and reference region RA according to the first embodiment. Figure 3 is an xz cross-section passing through the center of the memory element 100 and the reference element 101 in the y direction. For the sake of explanation, the write wiring WL and the common wiring CL at different positions in the y direction are shown by dotted lines in Figure 3. The write transistor WTr and the read transistor RTr are at different positions in the y direction.

The write transistor WTr, read transistor RTr, and common transistor CTr are on a substrate Sub. The memory element 100 and reference element 101 are on a different layer from these transistors on the substrate Sub. The memory element 100 and reference element 101 and these transistors are at different positions in the z direction. The memory element 100 and reference element 101 and these transistors are connected by via wiring V. Conductive layers 51 and 52 may be provided between the memory element 100 and reference element 101 and the via wiring V. The conductive layers 51 and 52 include, for example, any one selected from the group consisting of Ag, Cu, Co, Al, and Au.

The memory element 100, the reference element 101, the transistors thereof, and the via wiring V are covered with an insulating layer In. The insulating layer In is an insulating layer that insulates between the wirings of the multilayer wiring and between the elements. The insulating layer In is, for example, silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon carbide (SiC), chromium nitride, silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO _x ), or the like.

These transistors are, for example, field effect transistors. The transistors have, for example, a gate electrode G, a gate insulating film GI, a source region S, and a drain region D. The source region S and the drain region D are names defined by the direction of current flow, and their positions change depending on the direction of current flow. The source region S and the drain region D are formed in a substrate Sub. The substrate Sub is, for example, a semiconductor substrate. The gate electrode G is sandwiched between the source region S and the drain region D when viewed from the z direction. The gate electrode G controls the flow of charges between the source region S and the drain region D. The gate electrode G is connected, for example, to a write circuit WC or a read circuit RC.

Figure 4 is a cross-sectional view of the memory element 100 according to the first embodiment. Figure 4 is a cross-section of the memory element 100 cut in the xz plane passing through the center of the width of the wiring layer 20 in the y direction.

The memory element 100 has, for example, a stack 10 and an interconnect layer 20. The resistance value in the z direction of the stack 10 changes when spins are injected from the interconnect layer 20 into the stack 10. The memory element 100 is a spin element that utilizes spin orbit torque (SOT), and may be called a spin orbit torque type magnetoresistance effect element, a spin injection type magnetoresistance effect element, or a spin current magnetoresistance effect element. The interconnect layer 20 may be called a spin orbit torque interconnect.

The laminate 10 is laminated on the wiring layer 20. There may be other layers between the laminate 10 and the wiring layer 20.

The laminate 10 has a memory layer 11, a reference layer 12, and a spacer layer 13. The spacer layer 13 is sandwiched between the memory layer 11 and the reference layer 12. The memory layer 11 is closer to the wiring layer 20 than the reference layer 12.

The memory layer 11 includes a ferromagnetic material. The memory layer 11 is a layer that triggers data storage by changing the direction of magnetization _M11 . The memory layer 11 may be called a magnetization free layer. Spins are injected into the memory layer 11 from the wiring layer 20. The magnetization _M11 of the memory layer 11 receives spin orbit torque (SOT) due to the spins injected from the wiring layer 20. When the magnetization M11 of the memory layer ₁₁ receives a sufficient spin orbit torque, the orientation direction changes.

The easy axis of magnetization of the memory layer 11 may be the z direction or any direction in the xy plane. When the easy axis of magnetization of the memory layer 11 is in the z direction, the memory layer 11 is called a perpendicular magnetization film. When the easy axis of magnetization of the memory layer 11 is in any direction in the xy direction, the memory layer 11 is called an in-plane magnetization film. Figure 4 shows an example in which the memory layer 11 is a perpendicular magnetization film.

The memory layer 11 contains, for example, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni. The memory layer 11 is, for example, an alloy containing one or more of these metals, or an alloy containing these metals and at least one of the elements B, C, and N. The ferromagnetic material is, for example, Co-Fe, Co-Fe-B, Ni-Fe, Co-Ho, Sm-Fe, Fe-Pt, Co-Pt, or Co-Cr-Pt. Co-Fe is, for example, an alloy with a superlattice structure of Co and Fe. The Co-Fe alloy with a superlattice structure has Co layers and Fe layers stacked alternately.

The storage layer 11 may include a Heusler alloy. The Heusler alloy includes an intermetallic compound having a chemical composition of XYZ or X ₂ YZ. X is a transition metal element or a noble metal element of the Co, Fe, Ni, or Cu group on the periodic table, Y is a transition metal element or an element type of X of the Mn, V, Cr, or Ti group, and Z is a typical element of groups III to V. The Heusler alloy is, for example, Co ₂ FeSi, Co ₂ FeGe, Co ₂ FeGa, Co ₂ MnSi, Co ₂ Mn _1-a Fe _a Al _b Si _1-b , Co ₂ FeGe _1-c Ga _c , etc. The Heusler alloy has a high spin polarizability.

The reference layer 12 includes a ferromagnetic material. The reference layer 12 is a layer having magnetization _M121 that serves as a reference for the direction of magnetization _M11 of the memory layer 11. The magnetizations _M121 , _M122 of the reference layer 12 are less likely to change their orientation direction than the magnetization _M11 of the memory layer 11 when a predetermined external force is applied. The reference layer 12 is sometimes referred to as a magnetization fixed layer. The resistance value of the stack 10 changes depending on the difference in the relative angle of magnetization between the memory layer 11 and the reference layer 12.

The reference layer 12 has a first layer 121, a second layer 122, and a nonmagnetic layer 123. The nonmagnetic layer 123 is sandwiched between the first layer 121 and the second layer 122. The reference layer 12 has, in order from the side closest to the memory layer 11, the first layer 121, the nonmagnetic layer 123, and the second layer 122.

The first layer 121 and the second layer 122 include a ferromagnetic material. The magnetization M ₁₂₁ of the first layer 121 and the magnetization M ₁₂₂ of the second layer 122 are antiferromagnetically coupled by RKKY interaction. The magnetization M ₁₂₁ of the first layer 121 and the magnetization M ₁₂₂ of the second layer 122 are antiferromagnetically coupled to increase the coercive force of the reference layer 12. The reference layer 12 has a synthetic antiferromagnetic structure in which the first layer 121 and the second layer 122 are antiferromagnetically coupled. For example, the first layer 121 and the second layer 122 can be made of the same material as the storage layer 11. The magnetization easy axes of the first layer 121 and the second layer 122 may be in the z direction or any direction in the xy plane. FIG. 4 shows an example in which the first layer 121 and the second layer 122 are perpendicular magnetization films.

The thickness t1 of the first layer 121 and the thickness t2 of the second layer 122 may be the same or different. For example, when the first layer 121 and the second layer 122 are made of the same material, it is preferable that the thickness t1 of the first layer 121 and the thickness t2 of the second layer 122 are approximately the same. On the other hand, when the first layer 121 and the second layer 122 are made of different materials, it is preferable that the thickness t1 of the first layer 121 and the thickness t2 of the second layer 122 are different. Approximately the same means that the difference between the thickness t1 of the first layer 121 and the thickness t2 of the second layer 122 is within 10% of the thickness t1 of the first layer 121. Furthermore, the thickness t1 of the first layer 121 and the thickness t2 of the second layer 122 mean the sum of the thicknesses of the magnetic layers included in each layer.

Furthermore, it is preferable that the product of the thickness t1 and the saturation magnetization of the first layer 121 is approximately the same as the product of the thickness t2 and the saturation magnetization of the second layer 122. The magnetic field generated from the first layer 121 and the magnetic field generated from the second layer 122 cancel each other out, and the leakage magnetic field generated from the entire reference layer 12 is reduced.

FIG. 5 is an example of a cross-sectional view of the reference layer 12 of the memory element 100 according to the first embodiment. The first layer 121 and the second layer 122 shown in FIG. 5 are formed by alternately stacking magnetic layers FM and non-magnetic layers NM. For example, when the first layer 121 and the second layer 122 are Co-Pt, the first layer 121 and the second layer 122 are laminated films in which Co layers and Pt layers are alternately stacked, which corresponds to the example of FIG. 5. Adjacent magnetic layers FM are ferromagnetically coupled to each other. The magnetic layer FM is not limited to Co, but may be Fe, Ni, etc. The non-magnetic layer NM is not limited to Pt, but may be B, etc. In this case, the thickness t1 of the first layer 121 is the total thickness of the magnetic layers FM included in the first layer 121, and the thickness t2 of the second layer 122 is the total thickness of the magnetic layers FM included in the second layer 122.

In contrast, when the first layer 121 and the second layer 122 are made of only ferromagnetic material, the thickness t1 of the first layer 121 matches the total thickness of the magnetic layers included in the first layer 121, and the thickness t2 of the second layer 122 matches the total thickness of the magnetic layers FM included in the second layer 122. For example, this is the case when the first layer 121 and the second layer 122 are made of Co-Fe or Ni-Fe.

The nonmagnetic layer 123 includes at least one selected from the group consisting of Ru, Ir, and Rh. The thickness of the nonmagnetic layer 123 is a thickness at which the magnetization M ₁₂₁ and the magnetization M ₁₂₂ are antiferromagnetically coupled. The magnetization M ₁₂₁ and the magnetization M ₁₂₂ may be ferromagnetically coupled or antiferromagnetically coupled depending on the thickness of the nonmagnetic layer 123. For example, when the nonmagnetic layer 123 is made of Ru, the two ferromagnetic layers sandwiching the nonmagnetic layer 123 are antiferromagnetically coupled when the thickness of the nonmagnetic layer 123 is 7 Å or more and 10 Å or less, or 4 Å or more and 5 Å or less. For example, when the nonmagnetic layer 123 is made of Ir, the two ferromagnetic layers sandwiching the nonmagnetic layer 123 are antiferromagnetically coupled when the thickness of the nonmagnetic layer 123 is 3.5 Å or more and 5.5 Å or less.

The laminate 10 may have layers other than the memory layer 11, the reference layer 12, and the spacer layer 13. For example, a base layer may be provided between the wiring layer 20 and the laminate 10. Also, for example, a cap layer may be provided between the laminate 10 and the electrode E1. The base layer and the cap layer enhance the crystallinity of each layer constituting the laminate 10.

6 is a plan view of the memory element 100 in the array region MA according to the first embodiment. The stack 10 is a columnar body. The stack 10 has, for example, shape anisotropy when viewed from the z direction. Having shape anisotropy means that a circumscribing ellipse that contains the stack 10 has a major axis and a minor axis. The stack 10 is, for example, an ellipse as shown in FIG. 6 when viewed from the z direction. The major axis of the ellipse may face any direction in the xy plane. The shape of the stack 10 when viewed from the z direction is not limited to this case, and may be a circle, a rectangle, or an indefinite shape. The maximum width L10a of the stack 10 when viewed from the z direction is, for example, 20 nm or less. When the memory layer 11 and the reference layer 12 of the stack 10 are made into a single magnetic domain, the MR ratio of the memory element 100 is improved.

The spacer layer 13 is made of a non-magnetic insulator, semiconductor, or metal. The non-magnetic insulator is, for example, Al ₂ O ₃ , SiO ₂ , MgO, MgAl ₂ O ₄ , and materials in which a part of Al, Si, and Mg is replaced with Zn, Be, or the like. When the spacer layer 13 is made of a non-magnetic insulator, the spacer layer 13 is a tunnel barrier layer. MgO and MgAl ₂ O ₄ are easy to realize a coherent tunnel between the memory layer 11 and the reference layer 12. The non-magnetic metal is, for example, Cu, Au, Ag, Al, Cr, or the like. Furthermore, the non-magnetic semiconductor is, for example, Si, Ge, CuInSe ₂ , CuGaSe ₂ , Cu(In,Ga)Se ₂ , or the like.

The thickness of the spacer layer 13 is 8 Å to 40 Å if the spacer layer 13 is an insulator, and 10 Å to 100 Å if the spacer layer 13 is a conductor. The spacer layer 13 inhibits magnetic coupling between the memory layer 11 and the reference layer 12.

The wiring layer 20 contacts, for example, one surface of the stack 10. The wiring layer 20 is on the opposite side of the memory layer 11 to the spacer layer 13. The wiring layer 20 is a write wiring for writing data to the memory element 100. The wiring layer 20 extends in the x direction. At least a portion of the wiring layer 20 sandwiches the memory layer 11 together with the spacer layer 13 in the z direction.

The wiring layer 20 generates a spin current by the spin Hall effect when the current I flows, and injects spin into the memory layer 11. The wiring layer 20 applies, for example, a spin orbit torque (SOT) to the magnetization _M11 of the memory layer 11 that is sufficient to reverse the magnetization of the memory layer 11. The spin Hall effect is a phenomenon in which a spin current is induced in a direction perpendicular to the direction of the current flow based on the spin orbit interaction when a current flows. The spin Hall effect is common to the normal Hall effect in that the direction of movement (movement) of moving charges (electrons) is bent. In the normal Hall effect, the direction of movement of a charged particle moving in a magnetic field is bent by the Lorentz force. In contrast, in the spin Hall effect, the direction of movement of the spin is bent by the movement of electrons (current flow) even in the absence of a magnetic field.

For example, when a current flows through the wiring layer 20, the first spins oriented in one direction and the second spins oriented in the opposite direction to the first spins are bent by the spin Hall effect in a direction perpendicular to the direction of the current I. For example, the first spins oriented in the -y direction are bent in the +z direction, and the second spins oriented in the +y direction are bent in the -z direction.

In nonmagnetic materials (materials that are not ferromagnetic), the number of electrons in the first spin and the number of electrons in the second spin caused by the spin Hall effect are equal. In other words, the number of electrons in the first spin facing the +z direction is equal to the number of electrons in the second spin facing the -z direction. The first spins and second spins flow in a direction that eliminates the uneven distribution of spins. When the first spins and second spins move in the z direction, the flow of charges cancels each other out, so the amount of current is zero. Spin currents that do not involve current are specifically called pure spin currents.

If the flow of electrons of the first spin is represented as J _↑ , the flow of electrons of the second spin is represented as J _↓ , and the spin current is represented as _JS , then _JS = J _↑ - J _↓ . The spin current _JS is generated in the z direction. The first spin is injected from the wiring layer 20 into the memory layer 11.

The wiring layer 20 includes any one of a metal, alloy, intermetallic compound, metal boride, metal carbide, metal silicide, and metal phosphide that has the function of generating a spin current by the spin Hall effect when a current I flows.

The wiring layer 20 includes, for example, a non-magnetic heavy metal as a main element. The main element is the element that constitutes the wiring layer 20 at the highest ratio. The wiring layer 20 includes, for example, a heavy metal having a specific gravity equal to or greater than yttrium (Y). The non-magnetic heavy metal has a large atomic number of 39 or more and has d electrons or f electrons in the outermost shell, so that a strong spin-orbit interaction occurs. The spin Hall effect occurs due to the spin-orbit interaction, and spins tend to be unevenly distributed in the wiring layer 20, making it easier for a spin current J _S to occur. The wiring layer 20 includes, for example, any one selected from the group consisting of Au, Hf, Mo, Pt, W, and Ta.

The wiring layer 20 may contain a magnetic metal. The magnetic metal is a ferromagnetic metal or an antiferromagnetic metal. A small amount of magnetic metal contained in a nonmagnetic material becomes a scattering factor for spins. A small amount is, for example, 3% or less of the total molar ratio of the elements constituting the wiring layer 20. When spins are scattered by the magnetic metal, the spin-orbit interaction is enhanced, and the efficiency of generating a spin current relative to an electric current increases.

The wiring layer 20 may include a topological insulator. A topological insulator is a material in which the interior is an insulator or a high resistance material, but a spin-polarized metallic state occurs on the surface. In a topological insulator, an internal magnetic field is generated due to spin-orbit interaction. In a topological insulator, a new topological phase appears due to the effect of spin-orbit interaction even in the absence of an external magnetic field. A topological insulator can generate a pure spin current with high efficiency due to a strong spin-orbit interaction and the breaking of inversion symmetry at the edges.

Examples of topological insulators include SnTe, _{Bi1.5Sb0.5Te1.7Se1.3} , _TlBiSe2 , _Bi2Te3 , Bi1 _{- xSbx} , (Bi1 _{- xSbx} ) _2Te3 , _etc. Topological insulators are capable of generating spin _{currents with high efficiency} .

Figure 7 is a cross-sectional view of the reference element 101 according to the first embodiment. Figure 7 is a cross-section of the reference element 101 cut in the xz plane passing through the center of the width of the wiring layer 40 in the y direction.

The reference element 101 basically maintains a specific state, except for a refresh process or the like that returns data to an initial state. The specific state refers to the relationship between the relative angle of the magnetization _M31 of the memory layer 31 and the magnetization of the reference layer 32, which will be described later. The reference element 101 does not newly rewrite data, and maintains predetermined data as a reference for the memory element 100.

The reference element 101 has, for example, a stacked body 30 and a wiring layer 40. Other layers may be present between the stacked body 30 and the wiring layer 40. The configuration of the reference element 101 is similar to that of the memory element 100. Differences between the reference element 101 and the memory element 100 will be described below, and explanations of similarities may be omitted.

The laminate 30 has a memory layer 31, a reference layer 32, and a spacer layer 33. The spacer layer 33 is sandwiched between the memory layer 31 and the reference layer 32. The memory layer 31 is closer to the wiring layer 40 than the reference layer 32. The configuration and material of the memory layer 31 are the same as those of the memory layer 11.

The magnetization _M31 of the memory layer 31 maintains a predetermined state in principle. That is, the orientation direction of the magnetization _M31 does not change in principle. The easy axis of magnetization of the memory layer 31 may be the z direction or any direction in the xy plane. It is preferable that the easy axis of magnetization of the memory layer 31 approximately coincides with the easy axis of magnetization of the memory layer 11. The memory layer 31 shown in FIG. 7 is a perpendicular magnetization film and has the easy axis of magnetization in the z direction.

In principle, the reference layer 32 also maintains a predetermined state. The orientation direction of the magnetization M ₃₂ also does not change in principle. The resistance value in the stacking direction of the stack 30 maintains a constant value.

The reference layer 32 has a first layer 321, a second layer 322, and a nonmagnetic layer 323. The nonmagnetic layer 323 is sandwiched between the first layer 321 and the second layer 322. The reference layer 32 has, in order from the side closest to the memory layer 31, the first layer 321, the nonmagnetic layer 323, and the second layer 322.

The first layer 321 and the second layer 322 include a ferromagnetic material. The magnetization M ₃₂₁ of the first layer 321 and the magnetization M ₃₂₂ of the second layer 322 are antiferromagnetically coupled by RKKY interaction. For example, the first layer 321 and the second layer 322 are made of the same material as the first layer 121 and the second layer 122. The magnetization easy axes of the first layer 321 and the second layer 322 may be in the z direction or any direction in the xy plane. It is preferable that the magnetization easy axes of the first layer 321 and the second layer 322 are approximately the same as the magnetization easy axes of the first layer 121 and the second layer 122. The first layer 321 and the second layer 322 shown in FIG. 7 are perpendicular magnetization films and have magnetization easy axes in the z direction.

The thickness t3 of the first layer 321 and the thickness t4 of the second layer 322 may be the same or different. For example, when the first layer 321 and the second layer 322 are made of the same material, it is preferable that the thickness t3 of the first layer 321 and the thickness t4 of the second layer 322 are different. On the other hand, for example, when the first layer 321 and the second layer 322 are made of different materials, the thickness t3 of the first layer 321 and the thickness t4 of the second layer 322 may be the same. The thickness t3 of the first layer 321 and the thickness t4 of the second layer 322 mean the total thickness of the magnetic layers included in each layer. In the reference element 101 shown in FIG. 7, the thickness t4 of the second layer 322 is thicker than the thickness t3 of the first layer 321.

The product of the thickness t3 and the saturation magnetization of the first layer 321 is different from the product of the thickness t4 and the saturation magnetization of the second layer 322. The magnetic field generated from the first layer 121 and the magnetic field generated from the second layer 122 that are not canceled out are generated as a leakage magnetic field from the entire reference layer 12.

For example, the reference layer 32 generates a leakage magnetic field H _L1 according to the film thickness difference between the first layer 321 and the second layer 322. The direction of the leakage magnetic field H _L1 applied to the memory layer 31 and the direction of the magnetization M ₃₁ of the memory layer 31 are approximately the same. The magnetization M ₃₁ becomes difficult to reverse by applying the leakage magnetic field H _L1 to the memory layer 31. The leakage magnetic field H _L1 may be, for example, larger than the coercive force of the memory layer 31. If the leakage magnetic field H _L1 is larger than the coercive force of the memory layer 31, even if the magnetization M ₃₁ of the memory layer 31 is unexpectedly reversed, it spontaneously returns to the original state.

The ratio of the thickness t4 of the second layer 322 to the thickness t3 of the first layer 321 in the reference element 101 is different from, for example, the ratio of the thickness t2 of the second layer 122 to the thickness t1 of the first layer 121 in the memory element 100. For example, the value obtained by dividing the thickness t4 of the second layer 322 by the thickness t3 of the first layer 321 in the reference element 101 is greater than, for example, the value obtained by dividing the thickness t2 of the second layer 122 by the thickness t1 of the first layer 121 in the memory element 100. The reference element 101 utilizes the leakage magnetic field H _L1 to maintain the magnetization state of the stack 30. In contrast, when a leakage magnetic field occurs in the memory element 100, the magnetization M ₃₁ of the memory layer 31, which can take two states, is less likely to take one state. Therefore, it is preferable that the leakage magnetic field does not occur in the memory element 100.

When the above relationship is satisfied, the magnetization state of the reference element 101 is maintained in a predetermined state, and fluctuations in the reference value can be suppressed. In addition, it is possible to prevent unnecessary external forces from being applied to the memory layer 11 of the memory element 100, making it easier to rewrite data in the memory element 100.

The nonmagnetic layer 323 is similar to the nonmagnetic layer 123. The stack 30 may have layers other than the memory layer 31, the reference layer 32, and the spacer layer 33. The spacer layer 33 is similar to the spacer layer 13.

8 is a plan view of the reference element 101 in the array region MA according to the first embodiment. The stack 30 has, for example, shape anisotropy when viewed from the z direction. The shape of the stack 30 is not particularly limited. The maximum width L30a of the stack 30 when viewed from the z direction is larger than the maximum width L10a of the stack 10 when viewed from the z direction. When the volume of the memory layer 31 is large, the coercive force of the memory layer 31 is small, and it becomes easier to fix the direction of the magnetization _M31 by the leakage magnetic field H _L1 . The maximum width L30a of the stack 30 when viewed from the z direction is, for example, 20 nm or more.

The wiring layer 40 contacts, for example, one surface of the stack 30. The wiring layer 40 is on the opposite side of the memory layer 31 to the spacer layer 33. The wiring layer 40 has a similar configuration to the wiring layer 20. The reference element 101 does not need to have a wiring layer 40 because data is not rewritten.

The width W40 of the wiring layer 40 is, for example, wider than the width W20 of the wiring layer 20. It is preferable that the width W20 of the wiring layer 20 is narrow in order to increase the write current density, but since the wiring layer 40 is not intended for writing data, there is no limit to the width W40.

Next, a method for manufacturing the array area MA and reference area RA of the magnetic memory 200 will be described. The array area MA and reference area RA are formed by a process of stacking each layer and a process of processing a part of each layer into a predetermined shape. The stacking of each layer can be performed using a sputtering method, a chemical vapor deposition (CVD) method, an electron beam evaporation method (EB evaporation method), an atomic laser deposition method, etc. The processing of each layer can be performed using photolithography, etc.

First, impurities are doped into predetermined positions of the substrate Sub to form a source region S and a drain region D. Next, a gate insulating film GI and a gate electrode G are laminated in this order at a position between the source region S and the drain region D on the substrate Sub. Next, an insulating layer is formed to cover these.

Next, an opening is formed in the insulating layer, for example, by anisotropic etching. The opening is formed at a position between the source region S and the drain region D in a plan view from the z direction. The opening reaches the surface of the substrate Sub. The opening is filled with a conductor to become a via wiring V.

Next, an insulating layer is laminated to cover the via wiring V, and then conductive layers 51 and 52 are formed at positions overlapping the via wiring V. The conductive layers 51 and 52 are made of, for example, a material harder than the via wiring V. The surfaces of the insulating layer and conductive layers 51 and 52 are chemically mechanically polished (CMP). Using a hard material for the conductive layers 51 and 52 increases the flatness of the surfaces. Next, a conductive layer is laminated on the insulating layer and conductive layers 51 and 52.

The conductive layer is then processed into a predetermined shape to form the wiring layers 20, 40. The wiring layers 20, 40 are then surrounded by an insulating layer. A laminated film is then formed on the insulating layer and the wiring layers 20, 40, by stacking a magnetic layer, a non-magnetic layer, a magnetic layer, a non-magnetic layer, and a magnetic layer in that order. The laminated film is then processed into a predetermined shape to obtain the laminated bodies 10, 30. Finally, the laminated bodies 10, 30 are covered with an insulator, and the electrode E1 is connected to obtain the magnetic memory 200.

Next, the operation of the magnetic memory 200 according to the first embodiment will be described. First, the write operation to the magnetic memory 200 will be described. The write operation to the magnetic memory 200 is performed on the memory element 100 in the array region MA.

First, write data is input to the write circuit WC. The write data is sent to the array area MA, for example, page by page. In the array area MA, the data is written to the memory element 100 corresponding to the write data.

The write circuit WC turns on the write transistor WTr and the common transistor CTr connected to the memory element 100 corresponding to the data. When the write transistor WTr and the common transistor CTr are turned on, a write current flows along the wiring layer 20.

The write current generates the spin Hall effect, and spins are injected into the storage layer 11. The spins injected into the storage layer 11 apply a spin-orbit torque (SOT) to the magnetization _M11 of the storage layer 11, changing the orientation of the magnetization _M11 of the storage layer 11. The orientation of the magnetization _M11 can be freely controlled by the flow direction of the write current.

The resistance value in the stacking direction of the stack 10 is small when the magnetization _M11 of the memory layer 11 and the magnetization M12 of the reference layer ₁₂ are parallel, and is large when the magnetization _M11 of the memory layer 11 and the magnetization _M12 of the reference layer 12 are antiparallel. The memory element 100 stores data as the resistance value in the stacking direction of the stack 10.

Next, the operation of reading data from the magnetic memory 200 will be described. The operation of reading data from the magnetic memory 200 is performed by the read circuit RC by comparing the signal from the array area MA with the signal from the reference area RA.

First, a read voltage is applied to each of the array area MA and the reference area RA from the power supply P in the read circuit RC. The read voltage applied to the reference area RA is, for example, higher than the read voltage applied to the array area MA. By reducing the read voltage applied to the array area MA, erroneous writing during reading can be suppressed.

The read voltage is applied to the memory element 100 that reads data in the array area MA, and the reference element 101 that defines the reference value of the reference area RA. The read circuit RC turns on the read transistor RTr and common transistor CTr that are connected to these memory elements 100 and reference elements 101.

A read current flows in the stacking direction of the stack 10 of the memory element 100. A read current I _R1 also flows in the stacking direction of the stack 30 of the reference element 101 (see FIG. 7 ). In the case of FIG. 7 , a read current I _R1 flows in the reference element 101 from the reference layer 32 toward the memory layer 31. When the read current I _R1 is applied in this direction, the direction of the spins injected into the memory layer 31 coincides with the orientation direction of the magnetization M ₃₁ of the memory layer 31, and magnetization reversal of the magnetization M ₃₁ of the memory layer 31 can be suppressed.

The amount of current or voltage output from the memory element 100 varies depending on the resistance value in the stacking direction of the stack 10. For example, if the read current is a constant current, the potential difference in the stacking direction of the stack 10 changes depending on the resistance value in the stacking direction of the stack 10, and for example, the potential of the read wiring RL changes. For example, this potential is sent to the sense amplifier SA of the read circuit RC. Similarly, when a read current is applied to the reference element 101, a potential is also sent from the reference region RA to the sense amplifier SA. The potential of the reference region RA is, for example, a composite value of the potentials of multiple reference elements 101.

The sense amplifier SA compares this potential with the potential of the reference area RA and reads out the data. The potential of the reference area RA is set to a value between a value (minimum value) when the magnetization _M11 of the memory layer 11 and the magnetization _M12 of the reference layer 12 are parallel to each other and a value (maximum value) when the magnetization _M11 of the memory layer 11 and the magnetization _M12 of the reference layer 12 are antiparallel to each other.

The potential of the reference region RA can be freely designed, for example, by connecting the reference elements 101 in series and in parallel. For example, the reference region RA may have a plurality of first element groups EG1 in which a plurality of reference elements 101 are arranged in series, as shown in FIG. 2, and the first element groups EG1 may each be arranged in parallel. Also, for example, as shown in FIG. 9, the reference region RA may have a plurality of second element groups EG2 in which a plurality of reference elements 101 are arranged in parallel, and the second element groups EG2 may each be arranged in series.

For example, the read circuit RC sets the potential of the memory element 100 to "1" when it is higher than the potential of the reference area RA, and sets the potential of the memory element 100 to "0" when it is lower than the potential of the reference area RA. The magnetic memory 200 can read data at high speed by reading data by comparing it with the reference, without the need to read the specific values of each of the memory elements 100.

The magnetic memory 200 according to the first embodiment utilizes the leakage magnetic field H _L1 to stabilize the magnetization _M31 of the memory layer 31 of the reference element 101. Therefore, it is possible to suppress unexpected magnetization reversal of the magnetization _M31 of the reference element 101, and to suppress fluctuation of the reference. That is, the magnetic memory 200 according to the first embodiment has a stable reference and high reliability of data.

Although an example of the first embodiment has been given so far, the present invention is not limited to this example.

For example, Figs. 10 to 13 are specific configuration examples of serial connection of reference elements. Fig. 10 is a first example of serial connection, in which the stack 30 of the first reference element and the wiring layer 40 of the second reference element are connected by wiring. Fig. 11 is a second example of serial connection, which differs from the first example in that one end face of the wiring layer 40 and the side of the stack 30 are continuous. The second example has better integration than the first example. Fig. 12 is a third example of serial connection, in which the first reference element and the second reference element share the wiring layer 40. Fig. 13 is a fourth example of serial connection, which differs from the third example in that the end face of the wiring layer 40 and the side of the stack 30 are continuous. The fourth example has better integration than the third example.

For example, Figs. 14 to 18 are specific configuration examples of parallel connection of reference elements. Fig. 14 is a first example of parallel connection, in which the stacks 30 of the first reference element and the second reference element and the wiring layers 40 are connected to each other by wiring. Fig. 15 is a second example of parallel connection, which differs from the first example in that one end face of the wiring layer 40 and the side of the stack 30 are continuous. Fig. 16 is a third example of parallel connection, which differs from the first example in that the first reference element and the second reference element share the wiring layer 40. Fig. 17 is a fourth example of parallel connection, in which two stacks 30 are lined up in the width direction of one wiring layer 40. In the fourth example, the distances from the ends of the wiring layer 40 to the two stacks 30 are equal and the parasitic resistances are equal, so there is less noise. Fig. 18 is a fifth example of parallel connection, in which the stacks 30 are arranged in a matrix in the width direction and length direction of one wiring layer 40.

FIG. 19 is a cross-sectional view of a reference element 101A according to the first modified example. The reference element 101A differs from the reference element 101 in the configuration of the reference layer 34. The other configurations are the same as those of the reference element 101, and therefore will not be described.

The laminate 30A has a memory layer 31, a reference layer 34, and a spacer layer 33. The reference layer 34 has a first layer 341, a second layer 342, and a non-magnetic layer 343. In the reference element 101A shown in FIG. 19, the thickness t3 of the first layer 341 is greater than the thickness t4 of the second layer 342. The value obtained by dividing the thickness of the magnetic layer of the second layer 342 of the reference element 101A by the thickness of the magnetic layer of the first layer 341 is smaller than the value obtained by dividing the thickness of the magnetic layer of the second layer 122 of the memory element 100 (see FIG. 4) by the thickness of the magnetic layer of the first layer 121.

The direction of the leakage magnetic field H _L2 is opposite to that of the leakage magnetic field H _L1 shown in Fig. 7. The direction of the leakage magnetic field H _L2 applied to the memory layer 31 and the direction of the magnetization _M31 of the memory layer 31 are approximately the same, so the direction of the magnetization _M31 of the memory layer 31 is also reversed from that in Fig. 7. In the reference element 101A, the orientation direction of the magnetization _M31 is stabilized by the leakage magnetic field H _L2 , so the reference is less likely to fluctuate.

In the reference element 101A according to the first modification, it is preferable that the read current I _R2 flows from the memory layer 31 toward the reference layer 34. When the read current I _R2 is applied in this direction, the direction of the spins injected into the memory layer 31 coincides with the orientation direction of the magnetization _M31 of the memory layer 31, and magnetization reversal of the magnetization _M31 of the memory layer 31 can be suppressed.

FIG. 20 is a cross-sectional view of a reference element 101B according to a second modified example. The reference element 101B differs from the reference element 101 in that the magnetic layer is an in-plane magnetized film. The rest of the configuration is the same as that of the reference element 101, and a description thereof will be omitted.

The laminate 30B has a memory layer 35, a reference layer 36, and a spacer layer 33. The memory layer 35 and the reference layer 36 are made of materials that are easily magnetized in-plane. The reference layer 36 has a first layer 361, a second layer 362, and a nonmagnetic layer 363. In the reference element 101B shown in FIG. 20, the film thickness t4 of the second layer 362 is thicker than the film thickness t3 of the first layer 361. The value obtained by dividing the thickness of the magnetic layer of the second layer 362 of the reference element 101B by the thickness of the magnetic layer of the first layer 361 is greater than the value obtained by dividing the thickness of the magnetic layer of the second layer 122 of the memory element 100 (see FIG. 4) by the thickness of the magnetic layer of the first layer 121.

The leakage magnetic field H _L3 is generated so as to loop between the first layer 361 and the second layer 362. The direction of the leakage magnetic field H _L3 applied to the memory layer 35 and the direction of the magnetization M ₃₅ of the memory layer 35 are approximately the same. The magnetization M ₃₅ of the memory layer 35 is oriented in, for example, the -x direction. In the reference element 101B, the orientation direction of the magnetization M ₃₅ is stabilized by the leakage magnetic field H _L3 , so the reference is less likely to fluctuate.

In the reference element 101B according to the second modification, it is preferable to flow the read current I _R3 from the memory layer 35 toward the reference layer 36. When the read current I _R3 is applied in this direction, the direction of the spins injected into the memory layer 35 coincides with the orientation direction of the magnetization M35 of the memory layer ₃₅ , and magnetization reversal of the magnetization M35 of the memory layer ₃₅ can be suppressed.

FIG. 21 is a cross-sectional view of a reference element 101C according to a third modified example. The magnetic layer of the reference element 101C is an in-plane magnetized film, and the configuration of the reference layer 37 is different from that of the reference element 101. The other configurations are the same as those of the reference element 101, and therefore will not be described.

The laminate 30C has a memory layer 35, a reference layer 37, and a spacer layer 33. The memory layer 35 and the reference layer 37 are made of a material that is easily magnetized in-plane. The reference layer 37 has a first layer 371, a second layer 372, and a nonmagnetic layer 373. In the reference element 101C shown in FIG. 21, the thickness t3 of the first layer 371 is thicker than the thickness t4 of the second layer 372. The value obtained by dividing the thickness of the magnetic layer of the second layer 372 of the reference element 101C by the thickness of the magnetic layer of the first layer 371 is smaller than the value obtained by dividing the thickness of the magnetic layer of the second layer 122 of the memory element 100 (see FIG. 4) by the thickness of the magnetic layer of the first layer 121.

The leakage magnetic field H _L4 is generated so as to loop between the first layer 371 and the second layer 372. The direction of the leakage magnetic field H _L4 applied to the memory layer 35 and the direction of the magnetization M ₃₅ of the memory layer 35 are approximately the same. The direction of the magnetization M ₃₅ of the memory layer 35 is reversed from that in FIG. 20, and is, for example, the +x direction. In the reference element 101C, the orientation direction of the magnetization M ₃₅ is stabilized by the leakage magnetic field H _L4 , so that the reference is less likely to fluctuate.

In the reference element 101C according to the third modification, it is preferable to flow the read current I _R4 from the reference layer 37 toward the memory layer 35. When the read current I _R4 is applied in this direction, the direction of the spins injected into the memory layer 35 coincides with the orientation direction of the magnetization M35 of the memory layer ₃₅ , and magnetization reversal of the magnetization M35 of the memory layer ₃₅ can be suppressed.

10, 30, 30A, 30B, 30C Stacked body 11, 31, 35 Memory layer 12, 32, 36, 37 Reference layer 13, 33 Spacer layer 20, 40 Wiring layer 51, 52 Conductive layer 100 Memory element 101, 101A, 101B, 101C Reference element 200 Magnetic memory 321, 341, 361, 371 First layer 322, 342, 362, 372 Second layer 323, 343, 363, 373 Non-magnetic layer CL Common wiring CTr Common transistor EG1 First element group EG2 Second element group FM Magnetic layer H _L1 , H _L2 , H _L3 , H _L4 Leakage magnetic field I _R1 , I _R2 , I _R3 , I _R4 Read current L10a, L30a Maximum width MA Array region P Power supply PC Peripheral circuit region RA Reference region RC Read circuit RL Read wiring RTr Read path transistor SA Sense amplifier WC Write circuit WL Write wiring WTr Write transistor

Claims (15)

an array region including memory elements;
a reference region including a reference element;
a read circuit connected to the array region and the reference region for comparing a signal from the array region with a signal from the reference region;
The memory element and the reference element each include a memory layer including a ferromagnetic material, a reference layer including a ferromagnetic material, and a spacer layer between the memory layer and the reference layer;
the reference layer has, in order from the side closest to the storage layer, a first layer, a nonmagnetic layer, and a second layer,
the reference element and the memory element have different ratios of a total thickness of the magnetic layers in the second layer to a total thickness of the magnetic layers in the first layer;
the easy magnetization axes of the memory layer and the reference layer are in an in-plane direction intersecting a stacking direction,
a value obtained by dividing a thickness of the second magnetic layer by a thickness of the first magnetic layer is larger in the reference element than in the memory element;
A magnetic memory in which, when reading data, the reference element causes a read current to flow from the memory layer to the reference layer. an array region including memory elements;
a reference region including a reference element;
a read circuit connected to the array region and the reference region for comparing a signal from the array region with a signal from the reference region;
The memory element and the reference element each include a memory layer including a ferromagnetic material, a reference layer including a ferromagnetic material, and a spacer layer between the memory layer and the reference layer;
the reference layer has, in order from the side closest to the storage layer, a first layer, a nonmagnetic layer, and a second layer,
the reference element and the memory element have different ratios of a total thickness of the magnetic layers in the second layer to a total thickness of the magnetic layers in the first layer;
the easy magnetization axes of the memory layer and the reference layer are in an in-plane direction intersecting a stacking direction,
a value obtained by dividing a thickness of the magnetic layer of the second layer by a thickness of the magnetic layer of the first layer is larger in the memory element than in the reference element;
A magnetic memory in which, when reading data, the reference element causes a read current to flow from the reference layer to the memory layer. an array region including memory elements;
a reference region including a reference element;
a read circuit connected to the array region and the reference region for comparing a signal from the array region with a signal from the reference region;
The memory element and the reference element each include a memory layer including a ferromagnetic material, a reference layer including a ferromagnetic material, and a spacer layer between the memory layer and the reference layer;
the reference layer has, in order from the side closest to the storage layer, a first layer, a nonmagnetic layer, and a second layer,
the reference element and the memory element have different ratios of a total thickness of the magnetic layers in the second layer to a total thickness of the magnetic layers in the first layer;
The array area and the reference area are each connected to a power supply;
A magnetic memory , wherein a read voltage applied to the reference area is higher than a read voltage applied to the array area . an array region including memory elements;
a reference region including a reference element;
a read circuit connected to the array region and the reference region for comparing a signal from the array region with a signal from the reference region;
Each of the memory element and the reference element includes a wiring layer and a stacked body;
the laminate is laminated on the wiring layer,
the stack includes a memory layer including a ferromagnetic material, a reference layer including a ferromagnetic material, and a spacer layer between the memory layer and the reference layer,
the memory layer is closer to the wiring layer than the reference layer;
a resistance value in a stacking direction of the stacked body is changed by injecting spins from the wiring layer into the stacked body;
A plurality of the laminates are laminated in the wiring layer of the reference element,
the reference layer has, in order from the side closest to the storage layer, a first layer, a nonmagnetic layer, and a second layer,
A magnetic memory, wherein the reference element and the memory element have different ratios of the total thickness of the magnetic layers in the second layer to the total thickness of the magnetic layers in the first layer. 5. The magnetic memory according to claim 3, wherein a value obtained by dividing a thickness of the second magnetic layer by a thickness of the first magnetic layer is larger in the reference element than in the memory element. The array area and the reference area are each connected to a power supply;
The magnetic memory according to claim 1 , wherein a read voltage applied to the reference region is higher than a read voltage applied to the array region. the easy magnetization axes of the memory layer and the reference layer are in a stacking direction,
a value obtained by dividing a thickness of the second magnetic layer by a thickness of the first magnetic layer is larger in the reference element than in the memory element;
5. The magnetic memory according to claim 3, wherein , when reading data, a read current flows from the reference layer to the storage layer in the reference element. the easy magnetization axes of the memory layer and the reference layer are in a stacking direction,
a value obtained by dividing a thickness of the magnetic layer of the second layer by a thickness of the magnetic layer of the first layer is larger in the memory element than in the reference element;
5. The magnetic memory according to claim 3, wherein, when reading data, a read current flows from the storage layer to the reference layer in the reference element. each of the memory element and the reference element has a wiring layer on an opposite side of the memory layer to the spacer layer;
9. The magnetic memory according to claim 1, wherein a width of said wiring layer in said reference element is wider than a width of said wiring layer in said memory element. 10. The magnetic memory according to claim 1 , wherein a leakage magnetic field from the reference layer of the reference element is greater than a coercive force of the storage layer of the reference element. 11. The magnetic memory according to claim 1 , wherein, in a plan view seen from a stacking direction, a maximum width of the memory layer of the reference element is wider than a maximum width of the memory layer of the memory element. The magnetic memory according to claim 1 , wherein the maximum width of the storage layer of the reference element is greater than 20 nm in a plan view seen from the stacking direction. 13. The magnetic memory according to claim 1, wherein the maximum width of the memory layer of the memory element is 20 nm or less in a plan view seen from the stacking direction. The reference region has a plurality of reference elements,
the reference region includes a plurality of first element groups in which a plurality of reference elements are arranged in series;
The magnetic memory according to claim 1 , wherein the plurality of first element groups are arranged in parallel. The reference region has a plurality of reference elements,
the reference region has a plurality of second element groups in which a plurality of reference elements are arranged in parallel;
The magnetic memory according to claim 1 , wherein the plurality of second element groups are arranged in series.