JP7506576B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device.

In case a malfunction occurs during startup of a SoC (System on Chip), it is becoming increasingly important to have technology that can analyze which process is causing the malfunction.

JP 2009-211625 A

Patent document 1 discloses a technique for saving the process number where a timeout occurs in a non-volatile memory while a program that performs initialization processing is being executed. However, the technique described in patent document 1 has difficulty in dealing with cases where multiple processors perform parallel processing.

One aspect of the present invention provides a semiconductor device that can improve the accuracy of analyzing operational failures.

A semiconductor device according to one embodiment of the present invention includes a first processor, a second processor operable in parallel with the first processor, and a failure analysis circuit. The failure analysis circuit includes a first memory, a timer that starts operating when the semiconductor device is powered on, a control circuit that receives start information for a first process and a second process that are executed in response to the semiconductor device being powered on from the first processor and the second processor, respectively, and writes the start information and information based on the count value of the timer when the start information is received in association with each other in the first memory, and an interface circuit that enables access to the first memory from outside the semiconductor device.

1 is a block diagram of a semiconductor device according to a first embodiment. 4 is a flowchart showing the operation of the semiconductor device according to the first embodiment. 5 is a flowchart showing a process flow at the time of starting up the semiconductor device according to the first embodiment. 4 is a diagram showing an example of information recorded at the start-up of the semiconductor device according to the first embodiment. 10 is a flowchart showing a process flow at the time of starting up the semiconductor device according to the second embodiment. 13 is a diagram showing an example of information recorded at the start-up of the semiconductor device according to the second embodiment. FIG. 13 is a block diagram of a television system control circuit according to a third embodiment. 4 is a flowchart showing an example of an operation at the start-up of the semiconductor device according to the first to third embodiments. 13 is a diagram showing an example of information recorded at the start-up of the semiconductor device according to the first modification of the first to third embodiments. FIG. 13 is a block diagram of a failure analysis circuit included in a semiconductor device according to a second modification of the first to third embodiments.

Embodiments of the present invention will be described below with reference to the drawings. Note that in the drawings, identical or equivalent elements are given the same reference numerals, and duplicate descriptions will be omitted.

First Embodiment
A semiconductor device according to a first embodiment of the present invention will be described. This embodiment relates to the configuration of a SoC (System on Chip) having a plurality of processors, and also to the operation of the SoC when power is applied.

<About the composition>
1 is a block diagram of an SoC according to this embodiment. As shown in the figure, the SoC 1 includes a plurality of processors 100 (in this example, four CPUs 100-1 to 100-4), a ROM 200, a RAM 300, a power supply detection circuit 400, and a failure analysis circuit 500.

CPUs 100-1 to 100-4 execute the necessary information processing within SoC1 and are capable of parallel operation. In this example, an example is shown in which SoC1 has four CPUs 100-1 to 100-4, but the number is not limited to four, as long as there are two or more, and at least some of the CPUs may be other processors such as GPUs (Graphics Processing Units) rather than CPUs. In the following description, when there is no need to distinguish between CPUs 100-1 to 100-4, they will simply be referred to as CPUs 100.

ROM 200 stores the programs executed by CPU 100 and necessary data. Specifically, it stores a startup program 201 for performing the processes required to start up SoC1 when power is applied to SoC1, and an operating system 202 for running SoC1. RAM 300 also functions as a working area for CPU 100. Access to RAM 300 from outside SoC1 becomes possible, for example, after the operating system has started up.

The power supply detection circuit 400 detects when power is applied to the SoC1 and transmits a signal to that effect, for example, to the CPU 100 and the failure analysis circuit 500.

The failure analysis circuit 500 is part of the circuitry that constitutes SoC1, and is used to analyze any startup failures that occur when SoC1 is started up. The failure analysis circuit 500 broadly comprises a reset circuit 510, a timer circuit 520, a memory unit 530, and an interface circuit 540.

When the reset circuit 510 receives a signal indicating power detection from the power detection circuit 400, it generates a reset signal. Then, it supplies the generated reset signal to the timer circuit 520 and the memory unit 530.

The timer circuit 520 counts up, for example, based on a clock signal provided from a clock generation circuit (not shown). More specifically, when the timer circuit 520 receives a reset signal from the reset circuit 510, it resets the count value (for example, to zero) and starts counting up, triggered by the reset signal. In this example, a case is described in which the count value of the timer circuit 520 corresponds to the elapsed time since the start of counting. Note that the timer circuit 520 may count down instead of counting up, and is not limited as long as the count value corresponds to the elapsed time.

The memory unit 530 holds a read/write control circuit 531, a RAM 532, and an address counter 533. The memory unit 530 stores a log of the process executed by the CPU 100 when the SoC1 is powered on, and can output the log to the outside of the SoC1 via the interface circuit 540.

The read/write control circuit 531 roughly comprises a write circuit 600 and a read circuit 610.

The write circuit 600 includes a write control unit 601, a cache memory 602, and an adder unit 603 (603-1 to 603-4). Each of the adders 603-1 to 603-4 is associated with a CPU 100-1 to 100-4. The adders 603-1 to 603-4 receive information (start information) on the process number called for the CPU 100-1 to 100-4 and the process number of the process (sub-process) within the process from the CPU 100-1 to 100-4, respectively, and also receive a count value (i.e., elapsed time information) from the timer circuit 520. These data are then written to the cache memory 602 under the control of the write control unit 601. The cache memory 602 temporarily holds the data received from the adder unit 603 in order to write the received data to the RAM 532 without missing any data, even when start information is received simultaneously from multiple adders 603. The write control unit 601 controls the cache memory 602 and the adder unit 603. The write control unit 601 also counts up (or counts down) the counter value of the address counter 533. The counter value of the address counter 533 specifies an address in the RAM 532. The write control unit 601 then controls to write data held in the cache memory 602 to the address in the RAM 532 specified by the address counter 533. The read circuit 610 also reads data from the RAM 532 in response to a request from the interface circuit 540 and transfers it to the interface circuit 540. At this time, the read circuit 610 can access the desired address by counting up (or counting down) the counter value of the address counter 533.

RAM 532 is, for example, an SRAM, and holds data transferred from cache memory 602 according to commands from write circuit 600. It also reads out the held data according to commands from read circuit 610 and transfers it to read circuit 610. RAM 532 may be configured to erase all held data when it receives a reset signal from reset circuit 510. At this time, it may be the case that only log data (details of which will be described later) from when CPU 100 executes the startup program is erased.

The address counter 533 generates an address for specifying a specific area in the RAM 532. As described above, the address counter 533 can increment (or decrement) the address it generates to generate a new address in accordance with instructions from the write circuit 600 and read circuit 610. It then transfers the generated address to the RAM 532. The count value (address) of the address counter 533 is reset (for example, to "0x00") when it receives a reset signal from the reset circuit 510. Note that in this specification, numbers preceded by "0x" indicate that they are in hexadecimal notation.

Next, the interface circuit 540 will be described. The interface circuit 540 is responsible for transmitting and receiving signals between the outside of SoC1 and the failure analysis circuit 500. More specifically, when the interface circuit 540 receives a command to read log data during execution of the above-mentioned startup program from, for example, a tester outside SoC1, it transfers this command to the read circuit 610. Then, it transmits the log data read by the read circuit 610 to the tester. The interface circuit 540 allows the failure analysis circuit 500 to be accessed from the outside of SoC1 independently of other circuits such as the CPU 100. One example of the interface circuit 540 is the JTAG (Joint Test Action Group) interface.

<About operation>
Next, the operation of the SoC1 configured as described above when power is applied will be described with reference to the failure analysis circuit 500. Figure 2 is a flow chart showing the operation of the SoC1 when power is applied.

As shown in the figure, the power supply detection circuit 400 first detects that power has been applied to the SoC1 (step S10), and then transmits a detection signal to the CPU 100 and the failure analysis circuit 500 to inform them of this.

In the failure analysis circuit 500 that has received the detection signal, the reset circuit 510 issues a reset signal and sends it to the timer circuit 520, the RAM 532, and the address counter 533. As a result, the timer circuit 520, the RAM 532, and the address counter 533 are reset (step S11). More specifically, the count value in the timer circuit 520 is set to zero (in other words, the time is 00 hours, 00 minutes, 00 seconds, 000 milliseconds), data in the RAM 532 (e.g., log data) is erased, and the address in the address counter 533 is set to zero (e.g., "0x00"). Of course, these values are merely examples, and the reset value may be other values.

Then, the timer circuit 520 starts counting with the reset signal as a trigger (step S12). In other words, it essentially measures the elapsed time from immediately after power-on. The CPU 100 also reads the startup program 201 from the ROM 200 and executes it (step S13). Note that, although the example in FIG. 1 shows a case where the startup program 201 and the operating system 202 are stored in the same ROM 200, the startup program 201 may be stored in a separate ROM dedicated to startup. Also, when stored in the same ROM 200 as other application programs such as the operating system, the startup program 201 may be stored in a dedicated area that is first read and accessed when power is turned on.

The startup program 201 includes multiple processes, and the multiple CPUs 100 each execute the processes they are to execute in a specified order. Each process includes multiple operations. Each CPU 100 then notifies the addition unit 603 of the failure analysis circuit 500 of the start of the process it has called and the operation with the number scheduled to be executed in that process (step S14).

In response to an instruction from the write control unit 601, the addition unit 603 associates the process and processing number received from the corresponding CPU 100 with the count number received from the timer circuit 520, i.e., the elapsed time, and writes these data to the cache memory 602. Furthermore, the write control unit 601 writes the data written to the cache memory 602 to the RAM 532. At this time, the data is written to an area corresponding to the address generated by the address counter 533 (step S15).

The write circuit 600 repeats the above steps S14 and S15 while incrementing the address generated by the address counter 533 (step S17) until the startup program processing is completed (step S16, NO) or the processing times out. Details of steps S14 and S15 will be described later using a specific example.

After the startup program is finished (step S16, YES), when a request to read log data is received from, for example, a tester outside the SoC1 (step S18, YES), the read circuit 610 reads the log data from the RAM 532 and outputs the log data to the tester via the interface circuit 540 (step S19). That is, upon receiving a read request from the interface circuit 540, the read circuit 610 instructs the address counter 533 to specify the top address of the area in which the log data is stored, and then reads the data from the RAM 532 while incrementing the address. Note that if only a portion of the log data is requested from the outside, the read circuit 610 may instruct the address counter 533 to specify only that area.

<<Specific examples>>
3 and 4, a specific example of the operation of the CPU 100 and the data stored in the RAM 532 in steps S14 and S15 will be described. FIG. 3 shows the flow of processing by the CPU 100 that executes the startup program 201 immediately after power-on. In the notation "process Pi-j" in the figure, in this example, i is an integer from 1 to 6, each of which indicates the number (order) of a process included in the startup program 201, and j is an integer from 1 to 4, indicating that the corresponding process is the CPU 100-1 to 100-4. Therefore, for example, process P1-1 indicates that process P1 in the startup program 201 is executed by the CPU 100-1. Also, for the sake of simplicity, the number of processes (sub-processes) in each process P is two, and the respective process numbers are called "S" and "E".

In the example of Figure 3, immediately after power-on, process P1-1 is called first and executed by CPU 100-1. When process P1-1 is completed, process P1-1 then calls processes P2-1 and P2-3, which are then executed by CPUs 100-1 and 100-3, respectively.

Subsequently, when process P2-1 is completed, process P2-1 calls processes P3-1 and P3-2, which are then executed by CPUs 100-1 and 100-2. Furthermore, when process P2-3 is completed, process P2-3 calls processes P3-3 and P3-4, which are then executed by CPUs 100-3 and 100-4.

Furthermore, when process 3-1 is completed, process P4-1 is called by process 3-1, which is then executed by CPU 100-1. When processes P3-2 and P4-1 are completed, processes P3-2 and P4-1 each call process P5-1, which is then executed by CPU 100-1. Note that process P5-1 will not begin execution unless it is called by both processes P3-2 and P4-1. Similarly, when process P5-3 is called by both processes P3-3 and P3-4, process P5-3 is executed by CPU 100-3.

After that, processes P5-1 and P5-3 are completed, and when they call process P6-1, process P6-1 is executed by CPU 100-1. This completes the startup process of SoC1.

In the above example, assume that a problem occurs in process P3-1 and the processing does not complete. Figure 4 shows the log data stored in RAM 532 in this case.

As shown in the figure, when process P1-1 is called at 00:00:00:010 elapsed time after power-on, CPU 100-1 sends a processing start notification (corresponding to the above-mentioned start information) for process P1-1 to write circuit 600. This start notification includes the process name of the process to be started (P1-1 in this example) and the processing number ("S" in this example) of the processing target (sub-process) in that process. Then, write circuit 600 writes the received process name P1-1 and processing number "S" to address "0x00" in RAM 532. Next, when CPU 100-1 completes processing of processing number "S", it sends a processing start notification of process P1-1 processing number "E" to write circuit 600 at 00:00:00:100 elapsed time after power-on, and these data are written to address "0x01" in RAM 532. Note that the processing of process P1-1 with process number "E" is executed after the processing of process P1-1 with process number "S" is completed. Therefore, the issuance of a start notification for process P1-1 with process number "E" indicates that the processing of process P1-1 with process number "S" has ended normally.

Next, at 00:00:00:110, which is the elapsed time from power-on, CPUs 100-1 and 100-3 send start notifications for process number "S" of processes P2-1 and P2-3 to write circuit 600, and these data are written to addresses "0x02" and "0x03" in RAM 532. Since processes P2-1 and P2-3 are both called by process P1-1, the fact that these processes P2-1 and P2-3 have been called indicates that process P1-1 has ended normally.

After that, information about process number "E" of processes P2-1 and P2-2 is written to addresses "0x04" and "0x05", and information about process number "S" of process P3-1 is written to address "0x06". Information about process number "S" of processes P3-2, P3-3, and P3-4 is written sequentially to "0x07" to "0x09", and information about process number "E" of processes P3-2, P3-3, and P3-4 is written sequentially to "0x0A" to "0x0C".

Furthermore, information regarding process number "S" of process P5-1 is written to address "0x0D", and information regarding process numbers "S" and "E" of process P5-3 is written to addresses "0x0E" and "0x0F". And finally, information regarding process number "S" of process P6-1 is written to address "0x10".

According to the log data in FIG. 4, the processing of process P3-1 with processing number "S" is recorded at address "0x06", but the processing of process P3-1 with processing number "E" is not recorded. Also, as shown in FIG. 3, process P4-1 is called after the processing of process P3-1 is completed. In this example, since a malfunction has occurred in process P3-1, process P4-1 is not called, and the processing of process P4-1 is not recorded in the log data in FIG. 4. Furthermore, process P5-1 is executed after the processing of process P3-2 and process P4-1 is completed. In this example, since process P4-1 is not called, process P5-1 is not executed, and therefore only the processing number "S" is recorded for process P5-1, and not the processing number "E". The same is true for process P6-1.

Then, because the execution order of each process can be determined based on the elapsed time since power was turned on, it can be seen that a malfunction occurred in process P3-1 first. It can also be seen that processes P4-1, P5-1, and P6-1 were not executed due to the malfunction in process P3-1.

<Effects of this embodiment>
As described above, according to the SoC1 of this embodiment, the failure analysis circuit 500 records information about each process executed by the CPU 100 when the SoC1 is started, together with the elapsed time from power-on. Therefore, when a failure occurs during processing at the start, it becomes easy to identify which process the failure occurred in, and the accuracy of failure analysis can be improved. In addition, the write circuit 600 holds a cache memory 602, and writes data to the cache memory 602 before writing data to the RAM 532. Therefore, even if process start notifications are received from multiple processors at the same time, the data can be temporarily held in the cache memory 602, and then information about each process can be written sequentially to the RAM 532. Therefore, the log data can be recorded with high accuracy.

Furthermore, in this embodiment, the failure analysis circuit 500 includes an interface circuit 540 that controls communication with the outside of the SoC1. The interface circuit 540 can be operated by the read/write control circuit 531 independently of the CPU 100. Therefore, even if the operating system is not started, it is possible to read the log data from the RAM 532, making failure analysis easier.

Second Embodiment
Next, a semiconductor device according to a second embodiment of the present invention will be described. This embodiment relates to a specific example of a case where a defect occurs different from the case described in Figures 3 and 4 of the first embodiment. Therefore, the configuration and operation of the SoC1 according to this embodiment are similar to those of the first embodiment, and therefore a description thereof will be omitted.

<Specific examples of startup processing>
Fig. 5 shows the flow of processing by the CPU 100 that executes the startup program 201 immediately after power-on, and corresponds to Fig. 3 described in the first embodiment. The example in Fig. 5 differs from Fig. 3 in that process P5-3 references the result 310 of process P3-1. Therefore, if process P5-3 ends before process P3-1 ends normally, there is a very high possibility that process P5-3 will output an incorrect result. Fig. 6 shows an example of log data in such a case, and corresponds to Fig. 4 described in the first embodiment.

As shown in the figure, similar to the first embodiment, the processing number "S" of process P3-1 is recorded at address "0x06" along with the elapsed time from power-on, 00:00:00:310. In this example, the processing number "E" of process P3-1 is recorded at address "0x10" along with the elapsed time, 00:00:00:530. Therefore, it is highly likely that process P3-1 has terminated normally.

However, at times 00:00:00:510 and 00:00:00:520, before process P3-1 was terminated, the process numbers "S" and "E" of process P5-3 were already recorded at addresses "0x0E" and "0x0F." This shows that process P5-3 was executed without referencing the normal processing result 310 of process P3-1.

<Effects of this embodiment>
As described above, according to this embodiment, even when a process refers to the processing results of another process, it is possible to know whether the process is being executed normally by looking at the elapsed time in the log data.

Third Embodiment
Next, a semiconductor device according to a third embodiment of the present invention will be described. In this embodiment, the first or second embodiment is applied to a television system, and an EDID read control circuit is used instead of JTAG for the log data read interface. Only the differences from the first and second embodiments will be described below.

Figure 7 is a block diagram of a television system 2 according to this embodiment. The television system 2 is, for example, a television receiver. As shown in the figure, the television system 2 includes the SoC 1 described in the first embodiment, a flash memory 3, an LCD (Liquid Crystal Display) control unit 4, an audio processor 5, a power supply unit 6, and an HDMI (High-Definition Multimedia Interface) connector 7. The flash memory 3 holds, for example, an application program 8 for execution by the SoC 1. The LCD control unit 4 displays a video signal as an image on the liquid crystal display based on the control of the SoC 1. The audio processor 5 outputs an audio signal as sound from an audio device. The power supply unit 6 generates a voltage required for each unit of the television system 2 by, for example, stepping up or stepping down a voltage provided from the outside. The HDMI connector 7 transmits and receives signals to and from the outside according to the HDMI standard.

The SoC1 according to this embodiment also includes an EDID (Extended Display Identification Data) memory 700, an EDID read control circuit 800, a flash interface circuit 900, and an internal interface circuit 1000, in addition to the CPU 100, ROM 200, RAM 300, power supply detection circuit 400, and failure analysis circuit 500 described in the first embodiment.

The internal interface circuit 1000 is responsible for transmitting and receiving signals between the SoC 1 and the LCD control unit 4, audio processor 5, and power supply unit 6 within the television system 2. For example, it transmits commands from the CPU 100 in the SoC 1 to each unit, or receives signals from each unit and transfers them to the CPU 100.

The flash interface 900 accesses the flash memory 3 without going through the internal interface circuit 1000. It then transfers the application program 8 required within the SoC 1 to, for example, the RAM 300, and also transfers the processing results of the CPU 100 to the flash memory 3.

The EDID memory 700 holds the EDID. The EDID includes information such as the screen size, supported resolution, refresh rate, color characteristics, and manufacturer of the display in the television system 2.

The EDID read control circuit 800 controls the reading of EDID from the EDID memory and the reading of log data from the failure analysis circuit 500. The EDID read control circuit 800 is connected to the HDMI connector 7 via a DDC (Display Data Channel) line.

In the above configuration, the failure analysis circuit 500 is assigned a slave address of, for example, "0xB0", and the EDID memory 700 is assigned a slave address of, for example, "0xA0". An external device connected to the television system 2 via the HDMI connector 7 accesses the failure analysis circuit 500 or the EDID memory 700 by specifying the slave address.

For example, if the external device is a recorder or the like, the external device specifies "0xA0" as the slave address and requests data from the EDID read control circuit 800 via the DDC line. The EDID read control circuit 800 then accesses the EDID memory according to the received slave address, reads the EDID, and outputs it to the external device. On the other hand, if the external device is a startup information reading device 10 such as a tester, the external device specifies "0xB0" as the slave address and requests data from the EDID read control circuit 800 via the DDC line. The EDID read control circuit 800 then accesses the failure analysis circuit 500 according to the received slave address, reads the log data, and outputs it to the external device.

<Effects of this embodiment>
As described above, the SoC 1 described in the first and second embodiments can be applied to a television system. In this case, by using HDMI, it is possible to select either the failure analysis circuit 500 or the EDID memory 700. This allows failure analysis in the television system 2 to be performed easily and with high accuracy.

<Modifications, etc.>
As described above, according to the configurations described in the first to third embodiments, the failure analysis circuit 500 stores the process number of each process being started, together with information on the elapsed time from the start of the start-up, in the memory 532 inside the SoC1. This memory 532 can be directly accessed from outside the SoC1, for example, by using an interface such as JTAG. Therefore, even if the SoC1 cannot be started, the log data can be read out from the memory 532 to the outside, and it is possible to identify at what point in the start-up process the failure occurred.

As described in the third embodiment, the failure analysis circuit 500 can also be applied to the startup failure analysis of an LSI incorporating a CPU such as an 8K processor. As an example, if an LSI cannot be shipped due to a startup failure, the LSI becomes a repair target, and if the defective part cannot be identified, it becomes unrepairable and is discarded. However, by using the failure analysis circuit 500 according to the above embodiment, it becomes easy to identify where the defect is in the SoC, flash memory, DDR memory, and other peripheral devices that are deeply involved in startup. In addition, since the order of processing in each process and the time required for processing can be identified from the elapsed time recorded in the log data, it becomes easy to identify not only hardware defects but also software defects. As a result, the possibility of salvaging the LSI to be repaired by replacing parts can be improved.

Note that the embodiment is not limited to the above-described form, and various modifications are possible. For example, an example of the process at the time of startup may be as shown in FIG. 8. FIG. 8 is a flowchart of the startup process of SoC1. As shown in the figure, when power is applied to SoC1, the BIOS is started first (step S20), and the CPU 100 checks the hardware and starts the boot loader from the MBR (Master Boot Record) (step S21). The boot loader reads the kernel from the boot memory, for example, to the RAM, and the CPU 100 starts the kernel (step S22). The kernel initializes the memory and sets the system clock, and starts the init process (step S23). The init process executes the system initialization script and executes the service according to the runlevel, which results in the operating system starting and the startup process being completed. Each of the above steps S20 to S23 corresponds to the processes P1 to P6 described in FIG. 3 and FIG. 5.

Of course, the startup process is not limited to that shown in FIG. 8, and in the case of the television system described in the third embodiment, for example, it may be any process from when the television receiver is turned on until an image is normally displayed on the display and sound is normally output from the speaker. Furthermore, the failure analysis circuit 500 described in the first and second embodiments above may record the processing results of the processor 100 related to any process after startup as log data, not limited to the startup process.

In the above embodiment, the fault analysis circuit 500 receives a notification of the start of processing (sub-process) in each process from the CPU 100, and records log data in the RAM 532 based on this notification. As described above, a process that requires a call from multiple processes (for example, processes P5-1, P5-3, and P6-1 in FIG. 3) does not start actual processing unless it is called from all the processes that require it. In this regard, for example, the fault analysis circuit 500 may receive a completion notification indicating that processing has ended normally, instead of a start notification. That is, when the CPU 100 ends the processing of each process normally, it notifies the fault analysis circuit 500 of this fact, and when the processing of each process cannot be ended normally, it does not notify the fault analysis circuit 500 or notifies the fault analysis circuit 500 of the fact that the processing cannot be ended normally. An example of log data in this case is shown in FIG. 9. FIG. 9 corresponds to FIG. 4. As shown in the figure, the process P3-1 cannot be completed normally, so it is not recorded in the log data. Furthermore, the processes P5-1 and P6-1 cannot start processing, so they are not recorded in the log data. Even in such a case, it is possible to identify the defective part. Also, even if the failure analysis circuit 500 receives a start notification, the start notification may be output when the execution of the sub-process actually starts. In this case, for example, in the example of the first embodiment, the process of process number "S" of process P3-1 cannot be completed normally due to a malfunction, but the process itself actually starts, so that process P3-1 is recorded at address "0x06" as in the example of FIG. 4, but processes P5-1 and P6-1, which do not actually start processing, are not recorded.

In the above embodiment, the read circuit 610 outputs the log data to the outside. However, the read circuit 610 may identify the defective part and output the information to the outside. An example of the defect analysis circuit 500 in such a case is shown in FIG. 10. As shown in the figure, in the defect analysis circuit 500 according to this example, the read circuit 610 in the configuration of FIG. 1 described in the first embodiment includes a read control unit 611 and a defect analysis unit 612. In response to a request received from the interface circuit 540, the read control unit 611 reads the log data from the RAM 532 and transfers it to the defect analysis unit 612. The defect analysis unit 612 refers to the received log data and identifies in which process the defect occurs based on the elapsed time and the order of the process. Then, the identified defect information is output to the outside via the interface circuit 540.

In the above embodiment, the write circuit 600 has been described with reference to an example in which the count value received from the timer circuit 520 corresponds to the elapsed time since power-on. Specifically, for example, the timer circuit 520 may convert the count value into the elapsed time and output it to the adder 603, or the count value given to the adder 603 from the timer circuit 520 may be converted into the elapsed time by, for example, the write control unit 601. However, the elapsed time recorded as log data is not necessarily limited to the elapsed time since power-on, and may be, for example, the count value itself. Even in this case, the processing order of each process can be specified based on the count value. Alternatively, the timer circuit 520 may have a clock function that operates on, for example, a battery provided inside the SoC. Then, the timer circuit 520 may transmit the current time to the adder 603, and the write control unit 601 may record information on each process in the RAM 532 together with the current time instead of the elapsed time since power-on. Even in this case, the processing order of each process can be specified based on the time information corresponding to each process. Furthermore, the timer circuit 520 may be provided outside the SoC1. In other words, SoC1 needs to be able to receive information about the time from outside in some form.

In addition, the above embodiment has been described with reference to an example in which multiple processors are provided. However, in cases where a single processor can execute multiple processes simultaneously, the present invention is not limited to the case in which multiple processors are provided. Furthermore, the above embodiment is not limited to SoCs, but can be applied to semiconductor devices in general, and can be applied to any application other than the television system described in the third embodiment. Furthermore, the order of the processes in the flowcharts described in the above embodiment can be changed as much as possible.

Although several embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned forms and can be modified as appropriate. Furthermore, the above configurations can be replaced with substantially similar configurations, configurations that provide similar effects, or configurations that can achieve similar purposes.

1...SoC, 2...TV system, 3...Flash memory, 4...LCD control unit, 5...Audio processor, 6...Power supply unit, 7...HDMI connector, 10...Boot information reading device, 100...CPU, 200...ROM, 201...Boot program, 202...Operating system, 300, 532...RAM, 400...Power supply detection circuit, 500...Failure analysis circuit, 510...Reset circuit, 520...Timer circuit, 530...Memory unit, 531...Read/write control circuit, 533...Address counter, 540...Interface circuit, 1000...Internal interface circuit, 600...Write circuit, 601...Write control unit, 602...Cache memory, 603...Adder, 610...Read circuit, 611...Read control unit, 612...Failure analysis unit, 700...EDID memory, 800...EDID read control circuit, 900...Flash interface circuit

Claims (9)

A first processor;
a second processor operable in parallel with the first processor;
A semiconductor device comprising:
A first memory;
a timer that starts operating when power is applied to the semiconductor device;
a control circuit that receives from the first processor and the second processor start information of a first process and a second process that are executed in response to power-on of the semiconductor device, respectively, and writes the start information and information based on a count value of the timer at the time the start information is received in the first memory in association with each other;
and an interface circuit that enables access to the first memory from outside the semiconductor device. the control circuit receives, as the start information, a notification that the first process has been called or a notification that the second process has been called from the first processor and the second processor;
2. The semiconductor device according to claim 1, wherein the information based on the count value of said timer corresponds to an elapsed time from when said semiconductor device is powered on until said notification is received. The start information includes a process name of the called process and a number of a sub-process included in the process;
3. The semiconductor device according to claim 2, wherein said control circuit writes said process name, said sub-process number, and said elapsed time in said first memory in association with each other. The semiconductor device according to any one of claims 1 to 3, wherein the first process and the second process are at least a part of the startup process of the semiconductor device. The semiconductor device according to claim 4, wherein the control circuit does not write information about a process included in the startup process to the first memory if the control circuit does not receive start information about the process from the first processor or the second processor. The semiconductor device according to claim 4 or 5, wherein the startup process is a process required from when the semiconductor device is powered on until the operating system starts up. The semiconductor device according to any one of claims 1 to 6, wherein the interface circuit is accessible to the outside even when the startup of the semiconductor device is incomplete. The semiconductor device controls a television receiver,
6. The semiconductor device according to claim 4, wherein the start-up process includes processes required for the television receiver to display an image on a display and output an audio from a speaker. A second memory for storing an EDID;
a read circuit capable of reading data from the first memory and the second memory,
the interface circuit is assigned a first address and the second memory is assigned a second address;
9. The semiconductor device according to claim 8, wherein the read circuit reads data from either the first memory or the second memory by specifying the first address or the second address via a DDC (Display Data Channel).

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