JP7490543B2 - Photoelectric conversion device and camera - Google Patents

Description

The present invention relates to a photoelectric conversion device.

The provision of grooves in the semiconductor layer of photoelectric conversion devices such as CMOS image sensors used in cameras is being considered. The isolation section formed by the grooves acts as a barrier against light and electric charges, improving sensitivity and suppressing color mixing, thereby improving the performance of the photoelectric conversion device.

Patent Document 1 describes the provision of a trench (105) that extends from the back surface (101b) of a substrate (101) on which a photoelectric conversion element (102) is provided to the STI (111) on the front surface (101a) of the substrate (101).

US Patent Application Publication No. 2013/0069190

Patent Document 1 does not describe the planar layout of the trenches, but depending on the layout of the trenches, the improvement in performance of the photoelectric conversion device may not be sufficient, or the performance of the photoelectric conversion device may actually decrease. This may be due to, for example, limitations on sensitivity improvement and increased noise caused by the location of the trenches.

Therefore, the present invention aims to improve the performance of photoelectric conversion devices.

The present invention relates to a photoelectric conversion device having a pixel region including a plurality of photoelectric conversion elements, the device having a first surface and a second surface opposite to the first surface, and a semiconductor layer in which the plurality of photoelectric conversion elements are arranged between the first surface and the second surface, and a virtual plane along the second surface between the first surface and the second surface is defined as a third surface, the pixel region includes an element isolation portion formed by an insulator arranged closer to the first surface than the third surface, and a first isolation portion and a second isolation portion formed by a groove provided in the semiconductor layer so as to pass through the third surface, the first isolation portion overlapping the element isolation portion in a normal direction to the third surface, and the end of the second isolation portion on the first surface side is located closer to the second surface than the end of the first isolation portion on the first surface side.

The present invention provides a photoelectric conversion device with improved performance.

FIG. 1 is a schematic diagram illustrating a photoelectric conversion device. FIG. 1 is a schematic diagram illustrating a photoelectric conversion device. FIG. 1 is a schematic diagram illustrating a photoelectric conversion device. FIG. 1 is a schematic diagram illustrating a photoelectric conversion device. 1A to 1C are schematic diagrams illustrating a method for manufacturing a photoelectric conversion device.

Below, a description will be given of an embodiment of the present invention with reference to the drawings. Note that in the following description and drawings, common reference symbols are used for configurations that are common across multiple drawings. Therefore, common configurations will be described with mutual reference to multiple drawings, and descriptions of configurations with common reference symbols will be omitted as appropriate.

Figure 1(a) is a cross-sectional view showing an embodiment of a back-illuminated imaging device as an example of a photoelectric conversion device. Figure 1(b) is an enlarged view of the semiconductor layer of the photoelectric conversion device and the structure in the vicinity thereof.

The photoelectric conversion device 1000 has a pixel region PX including a plurality of photoelectric conversion elements PD. As described below, the pixel region PX further includes a separation section that electrically or optically separates various elements. The pixel region PX may also include a color filter array or a microlens array. The photoelectric conversion device 1000 includes a peripheral region (not shown) in addition to the pixel region. The peripheral region includes a drive circuit for driving the circuit (pixel circuit) of the pixel region PX and a signal processing circuit for processing signals from the pixel circuit. The configuration of the pixel region PX of the photoelectric conversion device 1000 will be described in detail below.

The photoelectric conversion device 1000 comprises a semiconductor layer 100 having a surface 1 and a back surface 2 opposite to the surface 1. The photoelectric conversion element PD of the pixel region PX is disposed in the semiconductor layer 100. The photoelectric conversion element PD is disposed between the surface 1 and the back surface 2. The semiconductor layer 100 is, for example, a single crystal silicon layer, but is not limited to a single crystal silicon layer as long as the semiconductor layer is capable of photoelectric conversion. The semiconductor layer 100 has a thickness T of about 1 to 10 μm (see FIG. 1(b)). The thickness T of the semiconductor layer 100 corresponds to the distance between the surface 1 and the back surface 2.

The photoelectric conversion device 1000 is arranged on the surface 1 side and includes an element isolation section 10 that is composed of a groove 11 in the semiconductor layer 100 and an insulator 12 in the groove 11. The element isolation section 10 may have an STI structure or a LOCOS structure. The groove 11 of the element isolation section 10 has a depth D1 of about 100 to 1000 nm from the surface 1 (see FIG. 1(b)). The insulator 12 that constitutes the element isolation section 10 is made of, for example, silicon oxide.

The photoelectric conversion device 1000 also includes a pixel separation section 20 formed by a groove 21 provided in the semiconductor layer 100. The pixel separation section 20 is arranged through the plane 3. The plane 3 is located between the front surface 1 and the back surface 2, closer to the back surface 2 than the element separation section 10, and is a virtual plane along the front surface 1 and/or the back surface 2. The plane 3 can be set between an intermediate plane, which is a virtual plane located equidistant from the front surface 1 and the back surface 2, and the back surface 2, for example, at a position T/4 from the back surface 2. The plane 3 can be parallel to the back surface 2. The direction perpendicular to the plane 3 is referred to as the normal direction N, and the direction parallel to the plane 3 is referred to as the in-plane direction P. In the normal direction N, the pixel separation section 20 extends across both the front surface 1 side and the back surface 2 side with respect to the plane 3. The groove 21 in this example is provided in the semiconductor layer 100 from the back surface 2 toward the front surface 1. Therefore, the groove 21 has a side surface that is continuous with the back surface 2. However, the groove 21 may be provided in the semiconductor layer 100 from the front surface 1 side toward the back surface 2, and the groove 21 may not reach the back surface 2. The groove 21 of the pixel separating section 20 has a depth D2 of about 1 to 10 μm from the front surface 1 (see FIG. 1B). Within the plane 3, the semiconductor layer 100 is discontinuous across the pixel separating section 20. A solid 22 may be present in the groove 21 of the pixel separating section 20, a vacuum space or a gas may be present, or both a gas and a solid 22 may be disposed. The solid 22 present in the groove 21 may be any of an insulator, a conductor, and a semiconductor. The insulator as the solid 22 present in the groove 21 is typically silicon oxide, but silicon nitride, silicon oxynitride, tantalum oxide, hafnium oxide, titanium oxide, and the like may also be used. The conductor as the solid 22 present in the groove 21 is typically metal or polysilicon, but aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, metal silicide, and the like may also be used. The semiconductor as the solid 22 present in the groove 21 is typically single crystal silicon, but may be amorphous silicon. The conductivity type of the semiconductor as the solid 22 present in the groove 21 is preferably the opposite conductivity type to the signal charge stored in the photoelectric conversion element described below.

The photoelectric conversion device 1000 further includes a pixel separation section 30 formed by a groove 31 provided in the semiconductor layer 100. The pixel separation section 30 is also arranged through the plane 3. The groove 31 is provided in the semiconductor layer 100 from the back surface 2 toward the front surface 1. Therefore, the groove 31 has a side surface that is continuous with the back surface 2. The groove 31 of the pixel separation section 30 has a depth D3 of about 1 to 10 μm from the front surface 1 (see FIG. 1(b)). Within the plane 3, the semiconductor layer 100 is discontinuous across the pixel separation section 30. A solid 32 may be present in the groove 31 of the pixel separation section 30, a vacuum space or a gas may be present, or both a gas and a solid 32 may be arranged. The solid 32 present in the groove 31 is the same as the solid 32 present in the groove 31 of the pixel separation section 20, so a description thereof will be omitted.

The pixel isolation section 20 and the pixel isolation section 30 are located at different positions in the in-plane direction P. The pixel isolation section 20 overlaps with the element isolation section 10 in the normal direction N. That is, as shown in FIG. 1(a), the pixel isolation section 20 is disposed below the element isolation section 10. The pixel isolation section 30 is disposed at a different position from the pixel isolation section 20 on the plane 3. The positions of the pixel isolation section 20 and the pixel isolation section 30 in the in-plane direction P will be described in detail later.

The pixel separation section 20 and the pixel separation section 30 have different depths in the normal direction N. The pixel separation section 30 is arranged shallower relative to the back surface 2 than the pixel separation section 20. The pixel separation section 20 and the pixel separation section 30 will be described with reference to FIG. 1B. The depth D2 of the pixel separation section 20 from the back surface 2 is greater than the depth D3 of the pixel separation section 30 from the back surface 2 (D2>D3). In other words, the end 39 on the front surface 1 side of the pixel separation section 30 is located closer to the back surface 2 than the end 29 on the front surface 1 side of the pixel separation section 20. FIG. 1A shows a plane 4. The plane 4 is a virtual plane along the front surface 1 and/or the back surface 2, located closer to the back surface 2 than the element separation section 10 between the front surface 1 and the back surface 2, and located closer to the front surface 1 than the plane 3. The plane 4 can be set between the front surface 1 and the intermediate plane, which is a virtual plane equidistant from the front surface 1 and the back surface 2, for example, at a position T/4 from the front surface 1. Pixel isolation section 20 is disposed through plane 4, whereas pixel isolation section 30 does not pass through plane 4. Edge 29 on the surface 1 side of pixel isolation section 20 is located between element isolation section 10 and plane 4, whereas edge 39 on the surface 1 side of pixel isolation section 30 is located between plane 3 and plane 4.

In this example, the pixel isolation section 20 is connected to the element isolation section 10. Therefore, the sum of the depth D1 of the element isolation section 10 from the front surface 1 and the depth D2 of the pixel isolation section 20 from the back surface 2 is equal to or greater than the thickness T of the semiconductor layer 100 (D1+D2≧T). The depth D3 of the pixel isolation section 30 from the back surface 2 is smaller than the thickness T of the semiconductor layer 100 (D3<T). It is preferable that the depth of the pixel isolation section 30 is about half the thickness T of the semiconductor layer 100, for example, 1/4 to 3/4 (T×1/4≦D3≦T×3/4).

A photoelectric conversion element PD is provided between the front surface 1 and the back surface 2 of the semiconductor layer 100. The photoelectric conversion element PD in this example is a photodiode, but may be a photogate or the like. The photoelectric conversion element PD as a photodiode includes an n-type impurity region 40 that functions as an accumulation region for accumulating signal charges (electrons), and a p-type impurity region 50 that forms a pn junction with the impurity region 40. Electrons generated by photoelectric conversion in the p-type impurity region 50 are accumulated in the impurity region 40. It is preferable that the impurity region 40 is located within the plane 3. The impurity region 50 is located between the plane 3 and the back surface 2. Here, an electron accumulation type photodiode is exemplified, but a hole accumulation type photodiode can also be adopted. In that case, the conductivity type of the impurity region may be reversed to that of the electron accumulation type. A conductivity type in which the signal charge is a majority carrier is called the first conductivity type, and a conductivity type in which the signal charge is a minority carrier is called the second conductivity type. If the signal charge is an electron, the n-type in which the electron is a majority carrier is called the first conductivity type. In addition, the portion of the semiconductor layer 100 regarded as the photoelectric conversion element PD is the portion that generates the charge that is read out as the signal charge through photoelectric conversion. Strictly speaking, the portion regarded as the photoelectric conversion element PD is determined by the impurity concentration distribution in the semiconductor layer 100 and the potential profile based on the applied voltage.

A pixel transistor 90 is provided on the surface 1 side of the semiconductor layer 100. FIG. 1 shows a channel region 70 and a gate electrode 80 of the pixel transistor 90. The pixel transistor 90 includes a transfer transistor, an amplification transistor, a reset transistor, and a selection transistor. The transfer transistor transfers the signal charge of the photoelectric conversion element PD to the charge detection region. The charge detection region is composed of a floating diffusion region. The amplification transistor generates a signal based on the charge by a source follower circuit, and has a gate connected to the charge detection region. The reset transistor has a drain connected to the charge detection region, and resets the charge of the photoelectric conversion element PD. The selection transistor selects whether to connect or disconnect the amplification transistor to the output line.

The semiconductor layer 100 is composed of a p-type impurity region 60 outside the photoelectric conversion element PD. The p-type impurity region 60 has a higher impurity concentration than the p-type impurity region 50. A part of the impurity region 60 can function as a potential barrier that suppresses the mixing of charges between pixels. A part of the impurity region 60 can also function as a potential barrier that suppresses the noise charge generated at the interface between the semiconductor layer 100 and the insulator from being taken into the photoelectric conversion element PD. The impurity region 60 also includes a dense p-type well contact to which a conductive member that supplies a fixed potential such as a ground potential is connected. A potential is supplied from the well contact to the impurity region 50 of the photoelectric conversion element PD via the impurity region 60.

The pixel separation units 20 and 30 are arranged around the photoelectric conversion element PD. The pixel separation units 20 and 30 have a configuration that can suppress color mixing between adjacent pixels.

On the front surface 1 side, an insulating film 300 is provided, which is made up of multiple wiring layers 310, 320, and 330 and multiple interlayer insulating layers surrounding them. The output line made up of the wiring layers is provided so as to output the signal charge generated by the photoelectric conversion element PD to the subsequent stage as an electrical signal via the pixel transistor 90.

In the back-illuminated imaging device shown in FIG. 1(a), a dielectric film 410, a light-shielding member 420, a color filter array 430, and a microlens array 440 are provided on the back surface 2 side. The dielectric film 410 functions as a protective film (passivation film), a planarizing film, and/or an anti-reflection film. A support substrate 400 is provided on the front surface 1 side, on top of the insulating film 300. An integrated circuit such as a signal processing circuit can also be provided on the support substrate 400. The semiconductor layer 100 has a thickness of about 1 to 10 μm. The support substrate has a thickness of about 50 to 800 μm.

The color filter array 430 is arranged to selectively transmit only light of a specific wavelength. For example, color filters that transmit red, green, and blue wavelengths may be arranged. Also, pixels that transmit white light may be mixed in. Each microlens of the microlens array 440 arranged corresponding to each pixel is arranged to focus incident light on the photoelectric conversion element PD.

As shown in FIG. 1B, the semiconductor layer 100 has an element region defined by the element isolation section 10. The element region is divided according to its position relative to the element isolation section 10. The lower end of the element region in the depth direction coincides with the bottom surface of the element isolation section 10 at a depth D1. FIG. 2 shows element regions 111, 112, 113, and 114 as element regions included in the semiconductor layer 100. The element region 111 is provided with an n-type impurity region 41 as an accumulation region for the photoelectric conversion element PD1, and the element region 112 is provided with an n-type impurity region 42 as an accumulation region for the photoelectric conversion element PD2. The element region 113 is disposed between the element region 111 and the element region 112, and semiconductor elements such as transistors, capacitance elements, and resistance elements are provided in the element region 113. The shape of the element region 113 is different from the shapes of the element region 111 and the element region 112. This is because the element region 113 is provided with semiconductor elements such as transistors other than the photoelectric conversion element PD. Typically, the area of element region 113 is smaller than the area of element region 111 and element region 112.

In this example, a pixel transistor is provided as a semiconductor element in the element region 113 described above. A typical pixel transistor can be a MOS transistor. In FIG. 2, a channel region 70 is shown as an impurity region of the pixel transistor, which is a MOS transistor, but a source region and a drain region (not shown) are also provided in the element region 113. A gate electrode 80 of the pixel transistor is provided on the channel region 70. An n-type impurity region 43 is provided in the element region 114 as an accumulation region of the photoelectric conversion element PD3. The range shown as the photoelectric conversion elements PD1, PD2, and PD3 in FIG. 1B corresponds to the n-type impurity region 40, which is the accumulation region of the photoelectric conversion element PD in FIG. 1. Outside the range shown as the impurity regions 41, 42, and 43 in FIG. 2, there is an impurity region corresponding to the p-type impurity region 50 forming the photoelectric conversion element.

The element isolation section 10 includes isolation regions 101, 102, and 103. Isolation region 101 is located between element region 111 and element region 113. Isolation region 102 is located between element region 112 and element region 113. Isolation region 103 is located between element region 111 and element region 114.

The semiconductor layer 100 has a semiconductor region on the back surface 2 side of the element isolation section 10, which corresponds to the distribution of the element regions and isolation regions on the front surface 1 side. The semiconductor region on the back surface 2 side is divided by its position relative to the isolation region or element region of the element isolation section 10. Each semiconductor region is located between any isolation region of the element isolation section 10 or any element region of the semiconductor layer 100 and the back surface 2 in the normal direction N. As such semiconductor regions, the semiconductor layer 100 includes semiconductor regions 121, 122, 123, 124, 125, 126, and 127. The semiconductor region 121 is located between the element region 111 and the back surface 2, the semiconductor region 122 is located between the element region 112 and the back surface 2, and the semiconductor region 123 is located between the element region 113 and the back surface 2. The semiconductor region 127 is located between the element region 114 and the back surface 2. The semiconductor region 124 is located between the isolation region 101 and the back surface 2, the semiconductor region 125 is located between the isolation region 102 and the back surface 2, and the semiconductor region 126 is located between the isolation region 103 and the back surface 2. In the following description, the term "semiconductor region" refers to a position that corresponds to the isolation region and the element region as described above. Meanwhile, the region in the semiconductor layer 100 that is divided by a predetermined conductivity type, impurity species, and impurity concentration for the operation of the semiconductor element is described as an "impurity region."

The pixel separation section 20 overlaps with the separation region 103 in the normal direction N. The pixel separation section 20 is composed of a groove 21. In the in-plane direction P, the pixel separation section 20 is located between the semiconductor region 121 and the semiconductor region 127. The pixel separation section 20 divides the semiconductor region 126 into a plurality of parts. As a result, the semiconductor region 126 includes a part 1261 located between the pixel separation section 20 and the semiconductor region 121 and a part 1262 located between the pixel separation section 20 and the semiconductor region 127. In this example, the pixel separation section 20 is connected to the separation region 103. In addition, in this example, the pixel separation section 20 reaches the rear surface 2. In other words, the groove 21 constituting the pixel separation section 20 is continuous with the rear surface 2. When the pixel separation section 20 and the separation region 103 are separated from each other, a part of the semiconductor region 126 is located between the pixel separation section 20 and the separation region 103. When the pixel isolation section 20 and the rear surface 2 are separated, a part of the semiconductor region 126 is located between the pixel isolation section 20 and the rear surface 2. It is sufficient that the pixel isolation section 20 has at least a part in the in-plane direction P that overlaps with the element isolation section 10 in the normal direction N. The pixel isolation section 20 may have a part in the in-plane direction P that does not overlap with the element isolation section 10 in the normal direction N.

The pixel isolation section 30 overlaps the intermediate region 110 between the element region 111 and the element region 112 in the normal direction N. The intermediate region 110 between the element region 111 and the element region 112 includes the isolation region 101, the isolation region 102, and the element region 113, and in this example, the pixel isolation section 30 overlaps the element region 113. The pixel isolation section 30 may overlap the isolation region 101 and/or the isolation region 102 in the normal direction N. The pixel isolation section 30 may not overlap the element region 113 in the normal direction N. In this way, the pixel isolation section 30 may have a portion that does not overlap the element isolation section 10 in the normal direction N.

The pixel separating section 30 is composed of a groove 31. In the in-plane direction P, the pixel separating section 30 is located between the semiconductor region 121 and the semiconductor region 122. The pixel separating section 30 overlapping with the element region 113 is located between the semiconductor region 124 and the semiconductor region 125 in the in-plane direction P. The pixel separating section 30 divides the semiconductor region 123 into a plurality of parts. As a result, the semiconductor region 123 includes a part 1231 located between the pixel separating section 30 and the semiconductor region 121, and a part 1232 located between the pixel separating section 30 and the semiconductor region 122.

In this way, within plane 3, semiconductor region 121 and semiconductor region 127 are discontinuous due to pixel separation section 20. Also, semiconductor region 121 and semiconductor region 122 are discontinuous due to pixel separation section 30. This reduces the mixing of light between pixels, improving the optical characteristics of the photoelectric conversion device. Also, mixing of charges between pixels is reduced, improving the electrical characteristics of the photoelectric conversion device.

The pixel isolation section 30 is separated from the region between the element region 111 and the element region 112, i.e., from the isolation region 101, the isolation region 102, and the element region 113. This makes it possible to reduce noise caused in the pixel transistor 90 by the pixel isolation section 30. It is also possible to reduce the effect on the operation of the pixel transistor 90 caused by stress concentration or stress concentration occurring in the vicinity of the isolation region 101, the isolation region 102, and the element region 113. In addition, it is possible to suppress the occurrence of defects (such as transfer defects) in the semiconductor layer 100 due to stress concentration, and therefore it is also possible to reduce the dark current taken in by the photoelectric conversion element PD.

In particular, the channel region 70 is located in the gate electrode 80 of the pixel transistor 90. The channel region 70 is more sensitive to noise than the source/drain region of the transistor. Therefore, it is preferable to arrange the pixel separation section 30 shallower than the pixel separation section 20 so as to overlap the channel region 70 and the gate electrode 80. In particular, it is effective that the pixel separation section 30 does not contact at least the gate insulating film of the pixel transistor 90. In addition, the pixel separation section 30 may be provided with a first portion shallower than the pixel separation section 20 and a second portion shallower than the first portion. In other words, the end of the second portion on the surface 1 side is located closer to the back surface 2 than the end of the second portion on the surface 1 side. The second portion may overlap the channel region 70 and the gate electrode 80, and the first portion may overlap another region, for example, the source/drain region.

It is desirable to provide a high density p-type impurity region to separate the pixel isolation section 30 from the photoelectric conversion element PD. If the pixel isolation section 30 is placed under isolation region 101 or isolation region 102, the size of the photoelectric conversion element PD is limited by the high density p-type impurity region. Therefore, by placing the pixel isolation section 30 under element region 113, the photoelectric conversion element PD can be made larger.

Furthermore, it is possible to use the semiconductor regions 124 and 125 adjacent to the semiconductor region 123 as the photoelectric conversion element PD. If the pixel separation section 20 were arranged in the semiconductor region 124, the pixel separation section 20 would prevent the movement of charges between the semiconductor region 123 and the semiconductor region 121. This would make it difficult to effectively use the semiconductor region 123 as the photoelectric conversion element PD. By arranging the pixel separation section 30 under the element region 113 in this way, the photoelectric conversion element PD1 can be extended from the semiconductor region 121 to the semiconductor region 124. Also, the photoelectric conversion element PD2 can be extended from the semiconductor region 122 to the semiconductor region 125. This can improve the sensitivity.

The pixel separation section 20 is not provided between the separation region 101 and the back surface 2. Therefore, the semiconductor region 121 and the semiconductor region 123 are continuous through the semiconductor region 124 in the plane 3. That is, in the plane 3, the semiconductor layer 100 is continuous under the element region 111, the element region 113, and the separation region 101. In this way, since the pixel separation section 20 is not provided under the separation region 101 and the semiconductor layer 100 is continuous, scattering of light by the groove 21 of the pixel separation section 20 is suppressed. Therefore, the amount of light incident on the photoelectric conversion element PD can be increased, and the sensitivity is improved. In addition, by moving the pixel separation section 20, which is a noise source, away from the impurity region 40, which is the accumulation region of the photoelectric conversion element PD, it is possible to suppress the noise generated near the pixel separation section 20 from being taken into the photoelectric conversion element PD. Furthermore, it is possible to use not only the element region 111 and the semiconductor region 121, but also the semiconductor region 124 as the photoelectric conversion element PD. If a pixel separation section 20 is arranged in the semiconductor region 124, the volume of the photoelectric conversion element PD will be reduced by the amount of the pixel separation section 20, resulting in a decrease in sensitivity.

In the example shown in FIG. 1, the photoelectric conversion element PD is arranged up to the region corresponding to the semiconductor regions 123, 124 in FIG. 2. This makes it easy to make the center of the photoelectric conversion element PD coincide with or approach the focusing position of the microlens (typically the optical axis of the microlens). To bring the focusing position of the microlens closer to the center of the photodiode, the distance between the optical axis of the microlens and the separation region 101 can be made smaller than the distance between the optical axis of the microlens and the separation region 103. This allows the microlens to focus light at positions roughly equal distances from the pixel separation sections 20, 30.

Figures 2(a) to (d) show modified examples of the pixel isolation section 20 connected to the element isolation section 10. As shown in Figure 2(a), a high-density p-type impurity region 61 for a p-type channel stop can be provided around the element isolation section 10. It is desirable to provide the bottom of the pixel isolation section 20 so that it is in contact with the impurity region 61. This makes it possible to suppress problems such as dark current even for defects near the bottom of the pixel isolation section 20, just like the element isolation section 10.

Also, as shown in FIG. 2(b), the pixel isolation section 20 may be arranged so that its bottom is embedded in the bottom of the element isolation section 10. In this way, the interface between the element isolation section 10 and the pixel isolation section 20 can be kept away from the semiconductor layer 100, thereby reducing defects that may occur around the bottom of the pixel isolation section 20.

2(a) and (b), the width W1 of the isolation region of the element isolation section 10 to which the pixel isolation section 20 is connected should be greater than the width W2 of the pixel isolation section 20 (W1>W2). This makes it easier to connect the bottom of the pixel isolation section 20 to the bottom of the element isolation section 10 even if misalignment occurs.

Also, as shown in Figs. 2(c) and (d), a part of the pixel isolation section 20 may face the element region. Furthermore, as shown in Figs. 2(c) and (d), the pixel isolation section 20 may be connected to both of a plurality of isolation regions that face each other across the element region. Figs. 2(c) and (d) show a case where the part of the pixel isolation section 20 that faces the element region is located on the front surface 1 side of the bottom surface of the element isolation section 10. Fig. 2(c) shows a case where the part of the pixel isolation section 20 that faces the isolation region is located on the back surface 2 side of the part that faces the element region. Fig. 2(d) shows a case where the part of the element isolation section 10 that does not face the pixel isolation section 20 is located on the back surface 2 side of the part that faces the pixel isolation section 20.

2(e) and (f), a dense p-type impurity region 62 can be provided around the pixel separation section 20 to suppress the intrusion of noise-causing electric charges from the pixel separation section 20 to the semiconductor element. Similarly, a dense p-type impurity region 62 can be provided around the pixel separation section 20 to suppress the intrusion of noise-causing electric charges from the pixel separation section 20 to the semiconductor element. Similarly, a dense p-type impurity region 63 can be provided around the pixel separation section 30 to suppress the intrusion of noise-causing electric charges from the pixel separation section 30 to the semiconductor element. As shown in FIG. 2(e), the positions at which the impurity region 62 and the impurity region 63 are provided may be the same regardless of the difference in depth between the pixel separation sections 20 and 30. In FIG. 2(e), the impurity region 62 and the impurity region 63 are provided to the same depth as the element separation section 10. Also, as shown in FIG. 2(e), the positions at which the impurity region 62 and the impurity region 63 are provided may be different depending on the difference in depth between the pixel separation sections 20 and 30. In FIG. 2(e), an impurity region 62 around the pixel separating section 20, which is deeper than the pixel separating section 30 with respect to the back surface 2, is provided to a position deeper on the back surface 2 than an impurity region 63 around the pixel separating section 30, which is shallower than the pixel separating section 20 with respect to the back surface 2. Note that the high p-type impurity regions 62 and 63 may be continuous with the high p-type impurity region 61 shown in FIG. 2(a) or may be formed integrally therewith.

Figure 2(e) shows a case where pixel isolation section 20 is not connected to element isolation section 10. Figure 2(f) shows a case where pixel isolation section 20 does not reach rear surface 2. Even in the cases of Figures 2(e) and (f), pixel isolation section 20 and pixel isolation section 30 pass through plane 3, pixel isolation section 20 passes through plane 4, and pixel isolation section 30 does not pass through plane 4.

As shown in FIG. 2(g), pixel separation sections 20 and 30 having different depths may have different inclination angles of the side surfaces of grooves 21 and 31. For example, the inclination angle θ1 of the side surface of groove 21 in deep pixel separation section 20 is made smaller than the inclination angle θ2 of the side surface of groove 31 in shallow pixel separation section 30 (θ1<θ2). In addition, the widths of grooves 21 and 31 are narrowed toward surface 1. In this way, in areas around pixel separation section 30 where there is concern that defects or stress concentration may affect the operation of the transistor, the volume of pixel separation section 30 can be reduced to suppress the effect on the operation of the transistor.

Alternatively, as shown in FIG. 2(h), the pixel isolation section 20 and pixel isolation section 30, which have different depths, may have different curvatures at their bottoms. For example, the curvature of the bottom surface of groove 21 in the deep pixel isolation section 20 may be made larger than the curvature of the bottom surface of groove 31 in the shallow pixel isolation section 30. By reducing the curvature of the bottom surface of groove 31 in pixel isolation section 30, it is possible to alleviate local stress. If the curvature of the bottom surface of groove 21 in pixel isolation section 20 is large, the tip of pixel isolation section 20 may be embedded into element isolation section 10 as shown in FIG. 2(h).

The shape of the pixel separator 20 is not limited to that of this embodiment, and any known trench shape can be used as appropriate. For example, the shape may be tapered from the back surface 2 side to the front surface 1 side of the semiconductor layer 100, or may be tapered inversely. Alternatively, the shape may have multiple inclination angles. By adjusting the shape of the pixel separators 20 and 30 in this way, it is possible to suppress color mixing in each pixel, improve sensitivity, and reduce noise.

Below, an example of the layout of the pixel region PX is shown using Figures 3 and 4. Note that in the following example, the above-mentioned in-plane direction P is described as being divided into the X direction and the Y direction, which intersect (are perpendicular to) each other. The normal direction P is described as the Z direction, which intersects (is perpendicular to) the X direction and the Y direction. The layout of the X-Y plane in Figures 3 and 4 is described as being seen through the semiconductor layer 100, the element isolation section 10, and the pixel isolation sections 20 and 30 from the rear surface 2 side.

Therefore, in the areas where the element isolation section 10 and the pixel isolation sections 20 and 30 overlap, the hatching of the element isolation section 10 is shown overlapping the hatching of the pixel isolation sections 20 and 30.

A first example of a pixel layout is shown using Figure 3. The pixel separation sections are arranged in a grid pattern and are formed so that their depths differ in the X and Y directions. That is, deep pixel separation sections 20 extend in the X direction, and shallow pixel separation sections 30 extend in the Y direction.

Figure 3 shows four types of element regions. The first type of element region includes a photodiode PDm, a transfer gate TXm, and a floating diffusion FDm. The second type of element region includes a reset transistor RSn. The third type of element region includes an amplifier transistor SFn and a selection transistor SLn. The fourth type of element region includes a well contact WCn. Here, m is a number determined for m pixels, and in Figure 4, n = 1 to 4, and is shown with PD1, PD3, FD2, and FD4. n is a number determined for each pixel, and in Figure 4, m = 1, 2, and is shown with RS1, RS2, SD1, and SF2. If m is an odd number, n = (m + 1) / 2, and if m is an even number, n = m / 2.

After the potential of the floating diffusion FDm is reset by the reset transistor RSn, the charge from the photodiode PDm is transferred to the floating diffusion FDm via the transfer gate TXm. The potential change at the floating diffusion FDm is transmitted to the gate of the amplifier transistor SFn through a wiring (not shown). The signal amplified by the amplifier transistor SFn constituting the source follower circuit is sequentially read out to the output signal line (not shown) via the selection transistor SLn. In other words, the operations of photoelectric conversion, accumulation, charge detection, amplification, and pixel selection are performed within one pixel. The well contact WCn also controls the potential of the well region of the pixel. Multiple photodiodes PDm share the reset transistor RSn, the amplifier transistor SFn, and the selection transistor SLn. In this case, the sharing relationship satisfies n = (m + 1) / 2 if m is an odd number, and n = m / 2 if m is an even number.

It is also possible to arrange a pixel transistor for each pixel, rather than sharing the pixel transistor among multiple photodiodes. Also, signals may be read out separately from multiple photodiodes PD in one pixel, and these signals may be combined. In this way, light rays split into pupils by multiple photodiodes PD in one pixel are detected separately, making it possible to perform distance measurement or focus detection using a phase difference detection method. Also, the dynamic range can be expanded by combining signals by varying the sensitivity of multiple photodiodes PDp in one pixel.

The photodiode PD1 and the photodiode PD2 are arranged in the X direction. The photodiode PD1 and the photodiode PD3 are arranged in the Y direction. The element region in which the photodiode PD3 is arranged is adjacent to the element region in which the photodiode PD1 is arranged. Here, two element regions adjacent to each other means that there is no element region between the two element regions. The element region in which the photodiode PD1 is arranged corresponds to the element region 111 described in FIG. 1(a), and the element region in which the photodiode PD2 is arranged corresponds to the element region 112 described in FIG. 2. The element region in which the amplifier transistor SFn and the selection transistor SLn are arranged corresponds to the element region 113 described in FIG. 2. The element region in which the photodiode PD3 is arranged corresponds to the element region 114 described in FIG. 2.

The element isolation section 10 has an isolation region 103 between the element region in which the photodiode PD1 is arranged and the element region in which the photodiode PD3 is arranged. The pixel isolation section 20 overlaps the isolation region 103 in the Z direction.

The pixel separating section 30 is provided with a first section 36 that is shallower than the pixel separating section 20, and a second section 37 that is even shallower than the first section 36. In other words, the end of the second section 27 on the front surface 1 side is located closer to the back surface 2 side than the end of the second section 36 on the front surface 1 side. The second section 37 may overlap the channel region 70 or the gate electrode 80, and the first section 36 may overlap another region, for example, a source/drain region.

A second portion 37 of the pixel separator 30 is provided shallower under the channel region where there is concern that the operation of the pixel transistor may be affected. Under the source/drain region, the first portion 36 of the pixel separator 30 is provided deeper than under the channel region, but the source/drain region may also be provided shallower than the other pixel separators 30 (first portion 36). Depending on the structure of the surface 1 side of the semiconductor layer 100, the depth may be continuously varied along the longitudinal direction of the pixel separators 20, 30. In this case, the width of the pixel separators 20, 30 may be continuously varied along the longitudinal direction of the pixel separators 20, 30. In addition, it is desirable to gradually change the line width or depth of the pixel separators 20, 30 at the locations where they change.

A second example of a pixel layout is shown using Figure 4. As shown in Figure 4, an element isolation section 10 made of silicon oxide is provided between an element region in which multiple photodiodes PDn (n = 1 to 4) are arranged and an element region in which the surrounding pixel transistors are provided. No element isolation section 10 is provided between adjacent photodiodes PDn. Although not shown, adjacent photodiodes PDn are isolated by a p-type high impurity region 63 formed by ion implantation.

As shown in the plan view of FIG. 4, the width of the pixel isolation portion is locally wide at the position opposite the element isolation portion 10, and the width is relatively narrow in other areas. The relatively wider pixel isolation portion can be formed deeper.

The width W2 of the deep pixel separation section 20 in contact with the element separation section 10 on the surface 1 side of the semiconductor layer 100 is wider than the width W3 of the shallow pixel separation section 30 having a depth D3 up to the middle of the semiconductor layer 100 (W2>W3). Also, the pixel separation section 30 having a depth up to the middle of the semiconductor layer 100 has a different width according to the different depths. That is, the width W3 of the first portion 36 of the pixel separation section 30 having the depth D3 is larger than the width W4 of the second portion 37 of the pixel separation section 30 having a depth D4 smaller than the depth D3 (W3>W4). In this way, the smaller the depth of the pixel separation section, the smaller the width of the pixel separation section can be. Note that when the widths of the pixel separation sections 20 and 30 change in the Z direction (thickness direction of the semiconductor layer 100), the widths of the pixel separation sections 20 and 30 on the third surface 3 can be used as representative widths. Since both the pixel separation section 20 and the pixel separation section 30 are located on the third surface 3, it is easy to compare the widths.

According to the present embodiment described above, even when the pixel isolation sections 20, 30 surround an area including two adjacent photodiodes, the depth of the pixel isolation sections 20, 30 is made to differ depending on the structure on the surface 1 side of the semiconductor layer 100. This makes it possible to suppress the influence on the photoelectric conversion characteristics or transistor characteristics, and to effectively suppress color mixing between adjacent pixels.

Next, a method for manufacturing a solid-state imaging device according to this embodiment will be described with reference to FIG.

First, in step a shown in FIG. 5(a), a trench 11 for an element isolation section 10 is formed on the front surface F side of the semiconductor substrate SUB. A channel stop layer (not shown) is formed around the trench 11 by ion implantation.

Next, in step b shown in FIG. 5B, the trench 11 is filled with an insulator 12 for the element isolation portion 10. Silicon oxide is suitable for the insulator 12. Excess insulator outside the trench 11 is removed by a CMP method or the like. This forms the element isolation portion 10 having an STI (Shallow Trench Isolation) structure.

Next, in step c shown in FIG. 5(c), a gate insulating film (not shown) and a gate electrode 80 are laminated on the surface F of the semiconductor substrate SUB to form pixel transistors (not shown). Furthermore, the photoelectric conversion element PD and the source and drain regions of the pixel transistors are formed by ion implantation performed from the surface F side of the semiconductor substrate SUB. Furthermore, impurity regions 62 and 63 can be formed in the semiconductor region in which the pixel isolation sections 20 and 30 are formed in this step.

Next, in step d shown in FIG. 5(d), an insulating layer is laminated to cover the gate electrode 80, and then a contact hole is formed in the insulating layer. A multilayer wiring structure is formed by further laminating a wiring layer and an interlayer insulating layer on the insulating layer in which the contact hole is formed. In this example, three wiring layers 310, 320, and 330 are formed. For example, copper wiring or aluminum wiring can be used for the wiring structure.

Next, in step e shown in FIG. 5(e), the support substrate 400 is bonded from above the insulating film 300. The bonding may be performed by bonding with an adhesive, or other known methods may be used as appropriate. However, it is preferable to carry out the process at 400° C. or less so as not to affect the wiring structure, etc.

Next, in step f shown in FIG. 5(f), a thinning process is performed from the back surface B1 side of the semiconductor substrate SUB until the semiconductor substrate SUB has a desired thickness. This thinning of the semiconductor substrate SUB results in a new back surface B2 appearing in place of the back surface B1. The thinning may be performed so that the photoelectric conversion element PD is exposed on the back surface B2. For example, chemical mechanical polishing (CMP), dry etching, wet etching, etc. can be used. These methods can also be combined. For example, the film thickness of the thinned semiconductor substrate SUB is in the range of 1 to 10 μm, and from the viewpoint of improving the light receiving sensitivity of the photodiode or the mechanical strength of the semiconductor substrate, it is preferable that the film thickness is in the range of 2 to 5 μm.

5(g), the groove 21 of the pixel isolation section 20 is formed from the back surface B2 side of the semiconductor substrate SUB at a position facing the element isolation section 10 formed on the front surface F side of the semiconductor substrate SUB. At this time, the depth of the groove 21 of the pixel isolation section 20 from the back surface B2 is preferably set to a depth such that the bottom of the pixel isolation section 20 reaches the element isolation section 10. For example, if the thickness of the thinned semiconductor substrate SUB is about 2 μm and the depth of the element isolation section 10 is about 0.3 μm, the groove 21 arranged opposite to the pixel isolation section 20 is formed to have a depth of about 1.7 μm. Such a pixel isolation section 20 is formed by the following procedure. Note that the width of the bottom of the pixel isolation section 20 is preferably relatively narrower than the width of the bottom of the element isolation section 10. This makes it easier to bring the bottom of the pixel isolation section 20 into contact with the bottom of the element isolation section 10 even if misalignment occurs.

The grooves 21 of the pixel isolation section 20 are not provided under the isolation region 101 of the element isolation section 10 adjacent to the photoelectric conversion element PD. This makes it possible to improve the photoelectric conversion performance described above.

The method of forming the pixel isolation section 20 will be described in more detail. First, in order to form the grooves 21 of the pixel isolation section 20 and the grooves 31 of the pixel isolation section 30 in the semiconductor substrate SUB, the grooves 21 and 31 having the desired width are formed, for example, by using an anisotropic dry etching method. For etching silicon, the Bosch process, in which a protective film formation step and an etching step are repeated every few seconds, can also be used. When processing the grooves 21 of the pixel isolation section 20 by dry etching, the element isolation section 10 may be used to detect the end of the etching of the semiconductor substrate SUB. Alternatively, etching may be performed by specifying the etching time according to the film thickness of the semiconductor substrate SUB. Also, a part of the bottom of the element isolation section 10 may be etched.

The grooves 21 and 31 of different depths can be formed simultaneously using the same etching mask (not shown). By etching the semiconductor substrate SUB under etching conditions utilizing the microloading effect, a deep groove 21 is formed under the wide opening of the mask pattern of the etching mask, and a shallow groove 31 is formed under the narrow opening. The microloading effect is a phenomenon in which the etching speed decreases as the opening width becomes smaller. By setting the mask pattern of the etching mask, grooves of different depths can be formed in a simple process. The semiconductor substrate SUB can also be etched under etching conditions utilizing the reverse microloading effect. In that case, the deep groove 21 can be formed under the narrow opening of the mask pattern of the etching mask, and the shallow groove 31 can be formed under the wide opening. Of course, it is also possible to form the deep groove 21 and the shallow groove 31 in separate processes, but there are many disadvantages, such as an increase in the lithography process and the problem of mask residue entering the deep groove 21.

Next, in step g shown in FIG. 5(g), solids 22 and 32 are formed in the grooves 21 and 31. First, a fixed charge film (not shown) is formed to suppress dark current generated on the rear surface 2 of the semiconductor layer 100. For this purpose, a fixed charge film (not shown) is formed along the shape of the rear surface B2 of the semiconductor substrate SUB. This fixed charge film is formed at least on the rear surface B2 of the semiconductor substrate SUB, and may be formed so as to further cover the side walls and bottom surface of the groove 21 of the pixel separation section 20. By covering the side walls and bottom surface of the pixel separation section 20 with a fixed charge film in this way, it is possible to suppress dark current that may be generated, for example, on the surface of the groove 21. As the fixed charge film, for example, a hafnium oxide film can be used by atomic layer deposition (ALD).

Next, a solid 22 made of a dielectric, a metal material, or other light-shielding material, or a combination of these materials, is formed inside the pixel separation section 20 of the semiconductor substrate SUB. For example, a material having a lower refractive index than silicon constituting the semiconductor substrate SUB, such as a silicon oxide film or a titanium oxide film, is formed on the fixed charge film. Then, a conductive material can be embedded using chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form the pixel separation section 20. Alternatively, a silicon oxide film is formed on the fixed charge film using atomic layer deposition (ALD), and then a silicon oxide film is deposited using HDP (High Density Plasma) CVD. In this way, the pixel separation section 20 may be formed by embedding the insulating film with a two-layer structure. In particular, a material that can be formed at a low temperature of 400° C. or less is preferable, and for example, amorphous silicon doped with P-type impurities, copper, tungsten, etc. are preferably formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The above-mentioned fixed charge film may also be used as the solid 22.

Although the above describes an example in which a solid 22 is embedded inside the pixel separation section 20, the configuration inside the groove 21 is not limited to this, and any structure capable of suppressing color mixing may be used, and known configurations and manufacturing methods may be applied. Also, for example, the pixel separation section 20 may have a groove 21 in which part or all of it is hollow.

In this example, the pixel isolation section 20 is formed from the back surface B2 side of the semiconductor substrate, but the method of forming the pixel isolation section 20 is not limited to the method described here. For example, the groove 21 may be formed from the front surface F side of the semiconductor substrate SUB before forming the element isolation section 10 described in steps a and b.

After this, the structure shown in FIG. 1(a) is formed. A dielectric film 410 is formed on the back surface B2 side of the semiconductor substrate SUB, and a light shielding member 420 is patterned between the pixels on the dielectric film 410. The light shielding member 420 is formed by forming a film by sputtering or chemical vapor deposition (CVD), and then processing the film to remove all areas other than those requiring the light shielding structure, including between the pixels. The material of the light shielding member 420 can be, for example, a laminated film of titanium and tungsten, or a laminated film of titanium nitride and tungsten.

Next, a planarization film (not shown) is formed, and a color filter array 430, for example, red, green, and blue, is formed on the planarization film in correspondence with each pixel, and a microlens array 440 is formed on top of that. Each color filter and microlens is formed in correspondence with each unit pixel of the pixel array. This completes the photoelectric conversion device. The semiconductor substrate SUB is used as the semiconductor layer 100 described above.

According to the above-described embodiment, a deep pixel isolation section 20 and a shallow pixel isolation section 30 are used in combination in the pixel region PX. By extending the deep pixel isolation section 20 in the depth direction toward the element isolation section 10, it is possible to effectively suppress color mixing between adjacent pixels. In addition, even if the shallow pixel isolation section 30 is arranged under an element region in which transistors or the like are provided or an isolation region where defects are likely to occur, the effects of noise and the like can be reduced. This allows the pixel isolation sections 20 and 30 to be arranged in a layout suitable for photoelectric conversion. This makes it possible to improve the performance of the photoelectric conversion device.

The photoelectric conversion device described above can be applied to an imaging device (image sensor) used in a camera or the like. In addition, it can also be applied to a sensor for focus detection (AF: autofocus) and a sensor for photometry (AE: autoexposure). In addition to the photoelectric conversion device as an imaging device, a camera can be equipped with at least one of a signal processing device, a storage device, a display device, and an optical device. The signal processing device is, for example, a CPU or DSP, and processes a signal obtained from the imaging device. The storage device is, for example, a DRAM or flash memory, and stores information based on the signal obtained from the imaging device. The display device is, for example, a liquid crystal display or an organic EL display, and displays information based on the signal obtained by the imaging device. The optical device is, for example, a lens, a mirror, a shutter, or a filter, and guides light to the imaging device. The camera referred to here includes not only dedicated camera devices such as still cameras, video cameras, and surveillance cameras, but also information terminals with imaging functions and moving objects (vehicles and aircraft) with imaging functions.

In addition, matters that are not explicitly described in this specification but can be understood from the attached drawings or common technical knowledge also constitute part of this disclosure. The present invention can be modified as appropriate without departing from the scope of the technical idea of this disclosure.

Reference Signs List 100 Semiconductor layer 1 Front surface 2 Back surface 3 Plane 10 Element isolation section 20 Pixel isolation section 30 Pixel isolation section

Claims (12)

A photoelectric conversion device having a pixel region including a plurality of photoelectric conversion elements,
a semiconductor layer having a first surface and a second surface opposite to the first surface, the plurality of photoelectric conversion elements being disposed between the first surface and the second surface, the semiconductor layer including a MOS transistor having a gate electrode disposed on the first surface side, a first semiconductor region of a first conductivity type which is a source region or a drain region of the MOS transistor, a well region of the pixel region, and a well contact disposed on the first surface for controlling a potential of the well region;
a lattice-shaped groove is disposed in the pixel region of the semiconductor layer, extends from the second surface toward the first surface, and is disposed along a first direction and a second direction intersecting the first direction in a plan view of the first surface;
In a cross-sectional view of the first surface along the first direction, the groove has a first region and a second region , the semiconductor layer extends between the first region and the first surface, and the second region has a length from the second surface longer than that of the first region ;
In a plan view of the first surface, a portion of the first region overlaps with the well contact;
the well region is located between an end of the first region on the first surface side and the well contact in a cross-sectional view with respect to the first surface ,
an element isolation portion including an insulator, the element isolation portion being disposed on the first surface side of the semiconductor layer in the pixel region;
a portion of the insulator is located between the semiconductor layer and a gate electrode of the MOS transistor;
In a plan view of the first surface, the second region overlaps with the element isolation portion.
A photoelectric conversion device comprising: The photoelectric conversion device according to claim 1 , wherein another part of the first region overlaps with the element isolation portion in the plan view. The photoelectric conversion device according to claim 2 , wherein a portion of the first region does not overlap with the element isolation portion in the plan view. 4. The photoelectric conversion device according to claim 1 , wherein the element isolation portion is a shallow trench isolation. 5. The photoelectric conversion device according to claim 1 , wherein a portion of the semiconductor layer is disposed between at least a portion of the insulator and at least a portion of the second region . 5. The photoelectric conversion device according to claim 1 , wherein a part of the second region is connected to the insulator. the plurality of photoelectric conversion elements include a first photoelectric conversion element, a second photoelectric conversion element, and a third photoelectric conversion element;
the first photoelectric conversion element and the second photoelectric conversion element are arranged along the second direction,
the second photoelectric conversion element and the third photoelectric conversion element are arranged along the first direction,
the first region is disposed between the first photoelectric conversion element and the second photoelectric conversion element;
7. The photoelectric conversion device according to claim 1, wherein the second region is disposed between the second photoelectric conversion element and the third photoelectric conversion element. 8. The photoelectric conversion device according to claim 1, wherein the first region overlaps with the MOS transistor in the plan view. 9. The photoelectric conversion device according to claim 1, wherein an insulator is disposed in the groove. A photoelectric conversion device according to any one of claims 1 to 9, characterized in that, when the length of the first region from the second surface is D1 and the distance between the first surface and the second surface is T, T x 1/4 ≦ D1 ≦ T x 3/4 is satisfied. The photoelectric conversion device according to claim 1 , wherein the second region is located at least at a corner of the lattice shape in the plan view. The photoelectric conversion device according to any one of claims 1 to 11 ,
At least one of a signal processing device that processes a signal output from the photoelectric conversion device, a storage device that stores information based on the signal output from the photoelectric conversion device, a display device that displays information based on the signal output from the photoelectric conversion device, and an optical device that guides light to the photoelectric conversion device;
A camera comprising:

Images