JP7488989B2 - On-chip 3D system in which TSV groups each containing multiple TSVs connect layers - Google Patents

Description

Article 30, paragraph 2 of the Patent Act applies (1) Announced on October 1, 2019 at https://mcsoc-forum.org/m2019/wp-content/uploads/2019/10/Khanh_OCTT.pdf (2) Announced on October 1, 2019 at the 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019) Proceedings, pages 223-228. (3) Announced at the 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019) on October 3, 2019. (4) Announced at https://ieeeexplorer.ieee.org/document/8906722 on November 21, 2019. (5) Announced at https://ieeeexplorer.ieee.org/document/8894077 on November 7, 2019. (6) Published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, No. 3, pp. 672-685, March 2020.

The present invention relates to an on-chip three-dimensional system in which a TSV group containing multiple TSVs connects between layers.

Scaling down transistors is a traditional approach to increase integration density. However, reaching the natural barrier of atomic size makes transistor scaling infeasible and even close geometries very expensive. Therefore, the need for higher integration density requires manufacturing processes to find alternative solutions. Also, heterogeneous technologies such as analog/RF, sensor/MEMS, RFID and memory need to be integrated on the same die to increase throughput and power efficiency density. In both cases, such integration methods need to evolve to achieve higher density and diversity (Non-Patent Document 1).

To achieve such heterogeneous integration, and due to the integration density problems of conventional 2D ICs, 3D ICs (three-dimensional integrated circuits) have been proposed as a promising solution (Non-Patent Document 2). 3D ICs not only allow for a single plane of devices, but also allow for an additional integration dimension supporting vertically stacked planes or even fully vertical placement and interconnection.

State-of-the-art 3D ICs using bond wires, solder balls, through-silicon vias or couplings are based on separate fabrication layers and then stacked on top of each other (Non-Patent Document 2). In particular, the fabrication layers are aligned and connected via special interconnection media. The interconnection media allows communication between layers providing signal, power or clock wires. As a result, 3D ICs allow the integration of different technologies. Separate fabrication allows different technology nodes and different device types. Also, instead of shrinking transistors, which are limited by molecular size, stacking more layers allows the area cost to be kept small while placing more transistors in a die. Stacked structures allow shorter wire lengths, which results in lower power consumption and lower latency.

Among the technologies related to 3D ICs, through-silicon-vias (TSVs) are one of the most mature, allowing communication between layers (Non-Patent Document 3). Vias pass through the layers, and by thermal compression, these vias allow the connection of two layers.

Although 3D IC systems based on TSVs have higher density, lower power consumption, and more heterogeneous design than traditional 2D IC systems, they are not an ideal solution for future large and complex SoC systems. This is due to several limitations on the reliability of TSV technology. First, the fabrication stage of TSVs is known for low yields due to stacking imperfections, accumulating yield rates from all layers (Non-Patent Documents 4, 5). Second, heat dissipation in 3D ICs is very difficult because the layers act as obstacles between the bottom layer and the heat sink (Non-Patent Document 6). Several methods such as thermal TSVs and microfluidic channels have been proposed. However, they are still insufficient at present.

A TSV defect is usually in one of three cases (open, short to substrate or bridge) (Non-Patent Document 7). An open defect electrically disconnects the two terminals of the TSV (partially or fully) and can be modeled as a high resistance TSV. Depending on the resistance of the defective TSV, a large delay may cause an open circuit or a timing violation. A short to substrate causes a leakage from the TSV to the substrate (ground) that brings the voltage of the output terminal closer to ground and can be modeled as an additional resistance between the TSV and ground. If this resistance is small enough, it forces the output of the TSV to ground (0 in binary). Also, a large resistance may cause timing violations. A TSV-to-TSV bridge defect is when two or more TSVs are connected with a conductive material. As a result, it becomes difficult to make these TSVs have different outputs. For example, if one TSV is a "1" and one TSV is a "0" and a bridge defect connects them, the output will be close to a floating voltage and metastability will occur. Nevertheless, these three major TSV defects are very critical because they destroy signal integrity and lead to incorrect values. Therefore, the system needs to detect these defects to maintain reliability.

To improve the reliability of TSVs, we classify the fault tolerance process into three main phases: detection, localization (diagnosis), and recovery. For detection and localization, built-in/self-test (BIST) (Non-Patent Documents 8, 9) and external testing (Non-Patent Document 10) are two common ways to determine whether a TSV is defective. Error correction code (ECC) (Non-Patent Document 11) or dedicated circuits (Non-Patent Documents 12, 13, 14, 15) also support fault detection and correction. Meanwhile, recent research focuses on recovery, of which there are several approaches, such as hardware fault tolerance (correction circuits (Non-Patent Document 13), redundancy (Non-Patent Document 16), reliability mapping (Non-Patent Document 17)), information redundancy (coding techniques (Non-Patent Document 11)), and algorithm-based fault tolerance (fault-tolerant routing (Non-Patent Document 18), run-time repair (Non-Patent Document 19), or remapping (Non-Patent Document 16)). Commercial CAD tools and existing solutions are mature for locating and detecting defects, but having an online, non-blocking solution would help prevent the costly consequences of a faulty operating system.

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Ben Abdallah. Architecture and Design of Highthroughput, Low-Latency, and Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip (3DNoC). The Jnl. of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532. J. Wang, M. Ebrahimi, L. Huang, X. Xie, Q. Li, G. Li, and A. Jantsch, “Efficient design-for-test approach for networks-on-chip,” IEEE Trans. Comput., vol. 68, no. 2, pp. 198- 213, Feb. 2018. G. C. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications. Cham, Switzerland: Springer, 2011, vol. 24. D. Gizopoulos et al., “Architectures for online error detection and recovery in multicore processors,” in Proc. Design, Autom. Test Eur., Mar. 2011, pp. 1-6. M. Y. Hsiao, “A class of optimal minimum odd-weight-column SEC-DED codes,” IBM J. Res. Develop., vol. 14, no. 4, pp. 395-401,Jul. 1970. D. Bertozzi, L. Benini, and G. De Micheli, “Error control schemes for on-chip communication links: the energy-reliability tradeoff,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 818-831, June 2005 L.-C. Li, W.-H. Hsu, K.-J. Lee, and C.-L. Hsu, “An efficient 3D-IC onchip test framework to embed TSV testing in memory BIST,” in Proc. 20th Asia South Pacific Design Autom. Conf., Jan. 2015, pp. 520-525. C. Serafy and A. Srivastava, “Online TSV health monitoring and builtin selfrepair to overcome aging,” in Proc. Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst., Oct. 2013, pp. 224-229. I. Loi, S. Mitra, T. H. Lee, S. Fujita, and L. Benini, “A low-overhead fault tolerance scheme for TSV-based 3D network on chip links,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, Nov. 2008, pp. 598-602. K. Manna, S. Singh, S. Chattopadhyay, and I. Sengupta, “Preemptive test scheduling for network-on-chip using particle swarm optimization,” in VLSI Design Test. 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To maintain a reliable real-time system, fault detection and recovery are important tasks. Therefore, it is necessary to maintain the operation of other tasks based on deadlines (Non-Patent Document 20). However, most of the existing methods to solve the TSV reliability problem focus on production test and recovery, but online lifetime reliability has not been adequately addressed. Since the consequences of silent defects can be expensive, the fault detection task requires short response times and little performance degradation. To reuse the existing test infrastructure, the system can perform the test process periodically using BIST (Non-Patent Documents 8, 9, 19) or external testing (Non-Patent Document 10). Hereafter, we use the term Periodic BIST (P-BIST) (Non-Patent Document 10) for this type of test. ECC also serves as a nearly instantaneous fault detection and location method.

The object of the present invention is therefore to identify multiple faults in a group of TSVs without degrading performance.

In one aspect of the present invention, an on-chip three-dimensional system is provided with a TSV group consisting of multiple TSVs connecting multiple layers, and identifies a first candidate TSV from the TSV group that may be a defective TSV having a predetermined defect based on a first bit transmitted from each TSV included in the TSV group, identifies a second candidate TSV from the TSV group from which the first candidate TSV has been excluded that may be the defective TSV based on a second bit transmitted from each TSV included in the TSV group from which the first candidate TSV has been excluded, and determines for each of the first and second candidate TSVs whether each TSV is the defective TSV based on a third bit transmitted from each TSV included in the TSV group from which each TSV has been excluded, and identifies one or more TSVs determined to be the defective TSV from the first and second candidate TSVs.

That is, in one aspect of the present invention, a communication-over-silicon-via test (TSV-OCT) mechanism is presented based on a statistical detection and post-isolation check method to solve the detection and localization challenges for operating 3D ICs. Since open/short/bridge defects are not consistent in terms of operation (usually due to hidden faults), statistical detection is applied to monitor a group of TSVs to capture as many defective locations as possible in a certain number of cycles. Then, to further detect more fault locations, TSV-OCT isolates the detected suspect TSVs to perform more checks. Isolation, which removes these TSVs from the encoding/decoding process, allows TSV-OCT to detect more defect locations that may be hidden by multiple defects. Due to the possibility of false positives, TSV-OCT performs rechecks on the suspect TSVs before drawing a conclusion due to the need to confirm the accuracy of the localization process. Considered from a time perspective, the response time to a new fault is very important, especially for real-time systems, so that the system can react appropriately to the new fault. Typically, when a new defect is localized, the system indicates that the integrity of the data that passed through that connection has been corrupted. Depending on the usefulness of the corrupted data, the system must either accept it or perform a rollback. In either case, knowing the failure location is crucial for real-time systems.

Thus, from a locality perspective, it is important to find out the fault locations where faults occur more frequently by analyzing the fault behavior of various components of the system.

Identify multiple faults in a group of TSVs without performance degradation.

FIG. 1 is a diagram showing sequences of data and test traffic under different strategies. FIG. 2 is a diagram showing a conventional TSV organization configuration in a three-dimensional IC system. FIG. 3 is a diagram showing a conventional test strategy. FIG. 4 is a block diagram showing a fault location specification according to this embodiment. FIG. 5 is a diagram showing a time chart for identifying a fault location in this embodiment. FIG. 6 is a diagram showing statistical detection of TSV regions in this embodiment. FIG. 7 is a diagram showing algorithm 1 in this embodiment. FIG. 8 is a diagram showing algorithm 2 in this embodiment. FIG. 9 is a diagram showing steps 1 to 3 of the separation and checking in this embodiment. FIG. 10 is a diagram showing steps 4 and 5 of the separation and checking in this embodiment.

The following describes embodiments of the present invention with reference to the drawings. Each embodiment is prepared for a better understanding of the present invention. However, such embodiments do not limit the technical scope of the present invention. The scope of the present invention also includes the claims and their equivalents.

Unlike the prior art, the system in the present embodiment identifies multiple failures in a group of TSVs without performance degradation. Furthermore, failure to identify the failure location can indicate an undetected failure that helps the system realize that communication through this TSV group is unreliable. Also, using a time constraint mechanism described below, the system ensures that execution times are within certain bounds so that checkpoints and rollbacks can be performed appropriately.

This embodiment is composed of the following:

1. Statistical detection mechanism to capture fault locations within TSVs.

2. Isolation and checking techniques that increase the detectability of mechanisms that can catch more faults.

3. In addition, reconnecting and checking can eliminate false positive cases (cases where the TSV is normal but is deemed to be faulty).

[Prior Art]
First, the prior art will be described. Figure 1 shows sequences of data and test traffic under various strategies. Specifically, Figure 1(a) shows application traffic; Figure 1(b) shows block testing; Figure 1(c) shows traffic injection for free-time testing; Figure 1(d) shows split free-time testing (Non-Patent Document 9); and Figure 1(e) shows error correction code.

Although research into 3D ICs has been conducted in recent years, little research has been done to address TSV failures in 3D IC systems.

EDC/ECC (Non-Patent Documents 11, 22) detects and locates faults in TSVs as normal wires. For example, SECDED can correct one and detect two inverted bits of data (Non-Patent Document 22). When used on TSVs, SECDED can locate up to one defect. Other ECC/EDC methods include SEC (single error correction), SECDED (single error correction and double error detection), ED (error detection), PAR (parity code), CRC-4 (cyclic redundancy check), OLSC (orthogonal Latin squares code) and CRC-8 (Non-Patent Document 23). EDC/ECC usually provides a fast response time but is limited by the number of defects that can be detected/corrected.

Other approaches use test circuits or BIST. Non-Patent Documents 12 and 13 present a fine-grained method to detect open defects using simple circuits. Non-Patent Document 12 further inserts test patterns into TSVs, captures the output, and uses NAND gates with logic threshold voltages to detect open defects. Non-Patent Documents 8 and 9 also present other methods of TSV BIST for pinhole and void defects. Non-Patent Document 24 reuses memory BIST for TSVs to reduce test time. Rigorous probing before coupling with an external tester (Non-Patent Document 10) also helps to improve the overall yield.

For online detection/recovery, Non-Patent Document 25 presents resistance tracking and BIST to overcome TSV degradation.

The work published in Non-Patent Document 6 also proposes a test pattern generator for testing open TSV defects, and Non-Patent Document 26 uses test access points to inject and collect test vectors. In Non-Patent Documents 16 and 27, tests are scheduled in advance to ensure correctness.

[Conventional testing method]
P-BIST is a method of periodically activating BIST. Here, the explanation focuses mainly on NoC testing. In Non-Patent Document 19 and Non-Patent Document 28, the tester is periodically active, but only during idle times to avoid inactivating the router of the NoC under test. It also provides easy access to the cores during testing. Non-Patent Document 29 also presents non-blocking testing of NoC, which is a similar idea. In Non-Patent Document 30, testing of NoC fabrics that can be used for 3D NoC is presented by using dedicated test data and structures. The common goal of these methods is to provide a smart schedule so that congestion/degradation does not occur in the system. These experiments are limited in terms of size, which may increase the execution time by complicating the system.

Redundant implementations have been presented in split-link transmission (NPL 31) and channel coding (NPL 32). Dynamic verification has been presented in NPL 33 with some invariants for online testing of NoCs. Dynamic verification has also been presented in NPL 34 with end-to-end monitoring. Anomaly detection (NPL 25) uses low-cost hardware or software to indicate abnormal behavior of TSVs. These methods are efficient because they are deeply integrated in the system, but they require careful attention to the vulnerability of TSVs in the location and real-time detection of defects. Figure 1 shows various test strategies. The blocking test (P-BIST) shown in the strategy in Figure 1(b) requires blocking data traffic to transmit test traffic, while the strategies in Figures 1(c) and (d) schedule the test traffic, resulting in less congestion. The strategy in Figure 1(e) represents an error-correcting code, where the test is performed together with the data transaction, causing neither congestion nor performance degradation.

[Conventional System]
Conventional systems are described below. Despite the various existing solutions addressing the problem of TSV detection and location in 3D IC systems as described above, several problems still exist:

First, failures of certain TSV-based 3D ICs can be caused by faults that are transient, persistent, or intermittent. While eliminating transient effects, no work provides complete fault detection and localization of TSV defects that are persistent or intermittent.

Second, most conventional solutions for fault detection and localization focus on partially or completely addressing offline faults. In other words, the device under test must be removed from operation for testing. However, this leads to reduced performance and less frequent testing (longer test duration). As a result, transient defects are hidden at test time and response times are longer.

Third, all previous architectures assume that TSV defects completely corrupt data. However, opens/shorts/bridges to the substrate all have inconsistent behavior, resulting in hidden defects. This work helps address this behavior.

Fourth, in a real-time system, each task requires a certain response time, and fault detection and localization must follow this rule. No test schedule takes this constraint into account, but in this work we handle deadlines appropriately.

[TSV Group Error Correction Code]
A conventional TSV organization in a 3D IC system is shown in Figure 2. As shown in Figure 2, there are two types of TSVs.

The first type is the data bits b _i,j , which are the data that needs to be transmitted over the TSV connection. Typically in bus-based or network-on-chip based systems, the data is a small amount of data (8, 16, 32 or 64 bits). Synchronization and control signals are considered to be this type of data.

The second type is the parity-check TSV (r _i , u _j and u), which helps in fault detection and localization. For example, the parity product code is encoded as follows:

Row and column parity checks are used for decoding.

The location of the defect can be indicated by checking the defective row and column.

The cases for fault detection are as follows:

Here, the PPC code detects two TSV defect cases and can identify at most one defect location. Since the number of defects can be multiple, the PPC may not be able to identify the location.

[Test Scheduling]
3 is a diagram showing a conventional test strategy. Specifically, FIG. 3(a) is a diagram showing application traffic. FIG. 3(b) is a diagram showing block testing. FIG. 3(c) is a diagram showing traffic injection for free-time testing. FIG. 3(d) is a diagram showing split free-time testing (Non-Patent Document 9). FIG. 3(e) is a diagram showing error correction code.

Figure 3 shows various test strategies. The strategy in Figure 3(b) shows blocking test (P-BIST) which requires blocking data traffic to transmit test traffic, while the strategies in Figures 3(c) and (d) schedule test traffic which results in less congestion. The strategy in Figure 3(e) represents an OCT method where tests are performed alongside data transactions, causing neither congestion nor performance degradation.

Obviously, blocking testing using P-BIST can provide more accurate and higher coverage test results since it isolates the device under test for testing. However, the trade-off in this case is performance degradation. In some critical systems, it is difficult to remove the device for testing. On the other hand, non-blocking such as ECC can be performed together with communication/operation. The drawback of ECC is the location limitation. As already shown, ECC such as PPC can only locate a single defect.

[Fault localization in TSV of 3D-IC]
A block diagram and a time chart of fault location identification in this embodiment are shown in Fig. 4 and Fig. 5, respectively. Fig. 4 is a diagram showing a block diagram of fault location identification in this embodiment. Fig. 5 is a diagram showing a time chart of fault location identification in this embodiment.

As shown in FIG. 4, in the fault-tolerant system of this embodiment, data is sent to the separation module 11 and then to the ECC encoder 12. The controller 13 manages the separation module 11 to perform separation and checking. The encoded data (codeword) is sent to the TSV group 21 to perform inter-layer communication. The received data is sent to the ECC decoder 32, and the result of the decoding is sent to the controller 33, and the data is merged by the merge module 31 to obtain the output data.

As shown in FIG. 5, the system in this embodiment solves the above problem in three steps: (1) statistical detection (S41-S44), (2) isolation and detection (S51-S55), and (3) reconnection and check (S61-S68). In the first step, statistical detection is used to capture as many suspect locations as possible (S41-S43). Then, in the second step, the suspect TSV is isolated (S44) and statistics are run again to capture more faults (S51-S53). The second step is run until no faults are detected (S54) or until a timeout (deadline) is reached (S55). Then, in the final step, each suspect TSV is reconnected to check for normal/fault status (S61). By running statistical detection with each suspect TSV connected (S62-S64), the system can conclude the status of that TSV (S65-S68).

[Impact of hidden errors]
One natural behavior of open and short defects is the paradox of bit flipping. If a TSV has a short to the substrate and transmits a value of "0", no error occurs at the receiver. However, transmitting a value of "1" through a TSV with a short to the substrate will result in a bit flip. If a timing violation occurs due to an open fault, transmitting the same value as the last transmitted value will not result in an error, but transmitting a different value may result in a bit flip. Due to this property, a TSV region with N defects may have up to N defects present at the same time.

Statistical Detection
FIG. 6 illustrates the statistical detection of a TSV region. FIG. 6 illustrates the operation of a statistical detector for a TSV region with 16 data bits, PPC (4×4), and 3 defects. A flipped-bit defective TSV outputs “0” when the input is “1”, and a hidden defective TSV outputs “0” when the input is “0”. Specifically, FIG. 6(a) corresponds to the case where there are zero hidden defects. FIG. 6(b) corresponds to the case where there is one hidden defect. FIG. 6(c) corresponds to the case where there are two hidden defects (case 1). FIG. 6(d) corresponds to the case where there are two hidden defects (case 2). FIG. 6(e) corresponds to the case where there are two hidden defects (case 3). FIG. 6(f) corresponds to the case where there are three hidden defects. FIG. 6(g) illustrates the waveform of the statistical detector for 32 transactions. The setting here is 16 data bits using a conventional PPC (4×4). Additionally, the inspection defect type is a short to the substrate.

As described in the conventional system, PPC is capable of locating one fault and detecting two faults. Here, we exploit the possibility that hidden faults reduce the number of affected TSVs. Once the data is received, the decoder attempts to detect and localize the faulty location. Naturally, the detector can correct up to J faults and detect up to K faults (J≦K). In T transmissions, the detector accumulates faults of the localization limit (less than J). After T transmissions, the accumulated number of faults is compared with a threshold (Thres_Loc) to detect possible corruption. To reduce the cost, we simply set the threshold to 1. However, to eliminate soft errors that may cause bit flips, Thres_Loc can be set to a higher value. The details of this method are described in Algorithm 1 shown in Figure 7.

Here, we use greedy location (Opt.=2). As long as the row and column checks fail, we consider the corresponding index location to be bad. For example, in the scenario shown in Figure 6(b), four locations ((2,0), (2,4), (3,0) and (3,4)) are considered to be faulty. This result consists of false positive cases, but the impact on reliability is insignificant.

Figure 6 shows the operation of the statistical detector for a TSV region with 16 data bits, PPC (4x4) and three defects ((0,3), (2,0) and (3,4)). Due to hidden effects, there are four possible cases:

(1) When there are zero hidden defects (Figure 6(a)): The detector fails to correct because all three defects cause bit flips.

(2) Case where there is one hidden defect (Figure 6(b)): Two defects cause a bit to be flipped, so the detector fails to correct it but may alert the system.

(3) When there are two hidden defects (Figures 6 (c) to (e)): The detector successfully identifies the location of one defect.

(4) When there are three hidden defects (Figure 6(f)): The system cannot issue a warning due to the hidden errors.

Here, we choose to use the greedy version (Opt. = 2) since the false positive cases are not a critical issue. As shown in Fig. 6(g), the greedy localization option tries to cover as many faulty locations as possible. A hit on one hidden defect (Fig. 6(b)) indicates that four locations ((2,0), (2,4), (3,0) and (3,4)) are bad. These false positives can be removed using a separation and checking algorithm, as described below.

[Separation and Checks]
The isolate and check shown in Algorithm 2 of Fig. 8 is used to solve both false positive and false negative cases. Since it may be difficult to have a dedicated tester close by, the isolate and check method aims to solve this problem based on reusing PPC. The algorithm follows the steps below:

(Step 1) Detect fault locations using a statistical detector. These locations are considered as suspect TSVs. Use greedy localization to capture as many suspect TSVs as possible. False positive TSVs are rechecked and later fixed.

(Step 2) The system effectively isolates the suspect TSVs from the encoding/decoding process, although they are still used in data transactions. In other words, the suspect TSVs are removed from the parity bit functions of (1) and (2). Although the column, row and final parity bits cannot be removed, the system can switch the parity bits to different positions if necessary.

(Step 3) Rerun steps 1 to 3 until the failure is no longer detected or the deadline has elapsed.

(Step 4) Reassign each separated TSV. The TSV is reattached to the encoding and decoding process. If a dedicated test is available, it can be used to reduce the test time.

(Step 5) After step 4, if the TSV region with isolated TSVs is still detected as faulty, there is a fault that cannot be recognized by the isolation and check. Here, the entire TSV region is considered to be defective. The system can also repeat the isolation and check to have higher coverage.

By invalidating all suspect TSVs and rerunning the statistical detector, the system can identify more faults. Consider the case of FIG. 9, after one use of the statistical detector, two TSVs (0,1) and (2,3) are removed from the decode and encode as shown in FIG. 9(a). After isolating the suspect TSVs, the system continues to run until the check time is over (T=32 transactions). When one hidden defect case (FIG. 9(a)) is hit again, the system can detect (2,1), as shown in D7 in FIG. 9(f). After concluding that (2,1) is suspect, the system isolates it for the next run. Once (0,1), (2,1) and (2,3) are isolated, a hit in the case of zero hidden defects can indicate the last defect (0,3) (D55 in FIG. 9(d) and FIG. 9(f)). If no location is detected at the end of step 3, the isolation and checking can cover all bad locations. However, there are still false positive cases remaining.

Steps 4 and 5 in the isolation and checking algorithm are shown in Figure 10. At the end of step 3 (see Figure 9), four locations are shown as suspect. In steps 4 and 5, the algorithm re-enables each of the suspected TSVs and checks their validity. The algorithm first enables (0,1) in TSV and executes a data transaction. Since this TSV is faulty and causes a faulty output at D11 in Figure 10(f), the system can easily conclude that it is faulty after T transmission. When the false positive case ((2,3) in TSV) is re-enabled, no faulty output is found. The system can determine it as non-faulty and remove it from the list. After testing each of the suspected TSVs, the system can finally conclude the faulty location.

11: Separation module 12: ECC encoder 13: Controller 21: TSV group 31: Merge module 32: ECC decode 33: Controller

Claims (4)

A three-dimensional system on a chip having a TSV group including a plurality of TSVs connecting a plurality of layers, the system comprising:
Identifying a first candidate TSV among the group of TSVs that may be a defective TSV having a predetermined defect based on a first bit transmitted from each of the TSVs included in the group of TSVs;
Identifying a second candidate TSV that may be the defective TSV from the group of TSVs from which the first candidate TSV has been excluded based on a second bit transmitted from each of the TSVs included in the group of TSVs from which the first candidate TSV has been excluded;
For each of the first and second candidate TSVs, determine whether or not each TSV is the defective TSV based on a third bit transmitted from each of the TSVs included in the TSV group from which each TSV is excluded;
identifying one or more TSVs determined to be the defective TSV from the first and second candidate TSVs;
An on-chip three-dimensional system comprising: In claim 1,
In the step of identifying the first candidate TSV,
When there is an inconsistency in the first bits transmitted from each of a plurality of TSVs located in the same row among the TSV group, it is determined that the first candidate TSV is included in the plurality of TSVs located in the same row;
When there is an inconsistency in the first bits transmitted from each of a plurality of TSVs located in the same column among the TSV group, it is determined that the first candidate TSV is included in the plurality of TSVs located in the same column.
An on-chip three-dimensional system comprising: In claim 1,
In the step of identifying the second candidate TSV,
When there is an inconsistency in the second bits transmitted from each of a plurality of TSVs located in the same row among the group of TSVs from which the first candidate TSV has been excluded, it is determined that the second candidate TSV is included in the plurality of TSVs located in the same row;
When there is an inconsistency in the second bits transmitted from each of a plurality of TSVs located in the same column among the group of TSVs from which the first candidate TSV has been excluded, it is determined that the second candidate TSV is included in the plurality of TSVs located in the same column.
An on-chip three-dimensional system comprising: In claim 1,
In the step of determining whether or not the TSV is defective,
For each of the first and second candidate TSVs, when there is an inconsistency in the third bits transmitted from each of a plurality of TSVs located in the same row among the group of TSVs from which each TSV has been excluded, it is determined that the defective TSV is included in the plurality of TSVs located in the same row;
For each of the first and second candidate TSVs, when there is an inconsistency in the third bits transmitted from each of a plurality of TSVs located in the same column among the group of TSVs from which each TSV has been excluded, it is determined that the defective TSV is included in the plurality of TSVs located in the same column.
An on-chip three-dimensional system comprising:

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