JP7472687B2 - Information processing device, information processing program, and information processing method - Google Patents

Description

The present invention relates to an information processing device, an information processing program, and an information processing method.

Information processing devices such as servers and storage devices may be equipped with a power supply device such as an uninterruptible power supply (UPS) or a built-in battery (hereinafter referred to as a "battery") to prevent data loss due to a sudden power outage or other power failure.

In an information processing device, if a power outage occurs while the processor is operating, the data can be protected by writing the data in the memory back to a storage device such as a disk while power is being supplied by such a battery.

In recent years, with an increase in the number of processor cores and the number of processors, the power consumption of information processing devices when operating at full capacity using the processor's performance is increasing. For this reason, the amount of power that the battery can supply may not be enough to ensure the operating time for the processor to write back data in the memory to the storage device, which may result in data loss.

When it is difficult to address the issue at the hardware level, such as by increasing (changing) the battery capacity, or to reduce costs, it is possible to use software control to ensure that the processor has enough operating time to write data in memory back to the storage device.

For example, a first method can be used in which, when a power outage is detected, all running processes are moved to one processor and the other processors are put into an idle state, or a second method can be used in which the other processors are stopped in an emergency except for one processor for saving data. The idle state is a state in which the processors are not performing any processing.

Japanese Patent Application Laid-Open No. 11-194846 Japanese Patent Application Laid-Open No. 08-087365

In the first method, it takes time to move all processes to one processor for safety reasons, and this can lengthen the period from when a power outage is detected until the server's power consumption starts to decrease. The power supplied by a battery is often smaller than the power supplied from a power source (e.g., an AC power source such as a distribution board).

As a result, the reduction in the server's power consumption does not keep up with the reduction in the amount of power supplied when the server switches to battery power. In other words, the battery capacity may be insufficient, causing the server to shut down and resulting in data loss.

In the second method, by bringing another processor to an emergency stop, various resources such as locks for processes running on that other processor may not be released. Examples of resources include shared resources such as memory or cache, or information (e.g., a flag) indicating the use of the shared resource. As a result, the remaining processor may not be able to shut down the system normally while waiting for the resource to be released, and may fail to write back data from memory.

In one aspect, the present invention aims to reduce the power consumption of an information processing device in a short period of time.

In one aspect, an information processing apparatus may include a plurality of processors, and a power supply unit that supplies, in response to a power outage of a power supply source, power output from a battery that accumulates power from the power supply source to each of the plurality of processors. A first processor of the plurality of processors may include a control unit that executes a first control and a second control. The first control may transition, in response to the detection of the power outage, each of one or more second processors of the plurality of processors to the second power mode out of a first power mode in which a process can be executed and a second power mode in which power consumption is smaller than that of the first power mode. When each of the one or more second processors transitions to the second power mode, the second control may transition each of the one or more second processors to the first power mode in a predetermined order, release resources used by the process executed by the second processor that transitioned to the first power mode, and transition to the second power mode.

In one aspect, the power consumption of an information processing device can be reduced in a short period of time.

FIG. 2 is a block diagram showing an example of a hardware configuration of a server according to an embodiment. FIG. 13 is a diagram illustrating an example of power consumption of a system when a power outage occurs. FIG. 13 is a diagram illustrating an example of power consumption of a system when a power outage occurs. FIG. 4 is a diagram illustrating an example of power consumption of a server system according to an embodiment. FIG. 2 is a block diagram illustrating an example of a functional configuration of a server according to an embodiment. 11 is a diagram for explaining an example of an operation of power consumption reduction control of a server according to an embodiment; FIG. 11 is a flowchart illustrating an example of an operation of a generation unit of a server according to an embodiment. 10 is a flowchart illustrating an example of an operation of power consumption reduction control of a server according to an embodiment. FIG. 2 is a block diagram illustrating an example of a hardware configuration of a computer.

Below, an embodiment of the present invention will be described with reference to the drawings. However, the embodiment described below is merely an example, and is not intended to exclude various modifications or application of techniques not explicitly described below. For example, this embodiment can be modified in various ways without departing from the spirit of the invention. In the drawings used in the following description, parts with the same reference numerals represent the same or similar parts unless otherwise specified.

1 is a block diagram showing an example of a hardware (HW) configuration of a server 1 according to an embodiment. The server 1 is an example of an information processing device or computer including a plurality of processors 2a.

As shown in FIG. 1, when focusing on the HW configuration related to the control of reducing power consumption in the event of a power outage, the server 1 may, for example, include a processor group 2, a memory 3, a storage device 4, a power supply unit 5, and an internal battery 6. In addition, an uninterruptible power supply (hereinafter sometimes referred to as "UPS") 7 and a power source 8 may be connected to the power supply unit 5.

The processor group 2 may include multiple (four in FIG. 1) processors 2a (represented as "processor #0" to "processor #3" respectively). The processor 2a is an integrated circuit (IC) that operates using power supplied to the server 1 and performs various controls and calculations, and is an example of a calculation processing device. The processor 2a may be a multi-core processor equipped with multiple cores.

The processor 2a may be, for example, any one of integrated circuits such as a CPU, MPU, GPU, DSP, ASIC, and PLD (e.g., FPGA), or a combination of two or more of these. Note that CPU is an abbreviation for Central Processing Unit, MPU is an abbreviation for Micro Processing Unit, GPU is an abbreviation for Graphics Processing Unit, and DSP is an abbreviation for Digital Signal Processor. ASIC is an abbreviation for Application Specific Integrated Circuit, PLD is an abbreviation for Programmable Logic Device, and FPGA is an abbreviation for Field Programmable Gate Array.

The memory 3 is an example of a volatile storage area, and may include a storage area for storing programs and data executed by the processor 2a. Examples of the memory 3 include volatile memories such as dynamic random access memory (DRAM).

The storage device 4 is an example of a non-volatile storage area, and is a device that stores various programs, data, and other information. Examples of the storage device 4 include various storage devices such as magnetic disk devices such as HDDs (Hard Disk Drives), semiconductor drive devices such as SSDs (Solid State Drives), and non-volatile memories. Examples of non-volatile memories include flash memories, SCMs (Storage Class Memory), and ROMs (Read Only Memory).

Each of the multiple components (multiple modules) in the server 1, including the processor group 2 (multiple processors 2a), memory 3, and storage device 4, may be communicatively connected to each other via a bus.

The power supply unit 5 may be a power supply device such as a PSU (Power Supply Unit). For example, the power supply unit 5 may convert the power supplied from at least one of the built-in battery 6, the UPS 7, and the power source 8 into AC/DC and a voltage suitable for each component, and supply it to each component via a power supply path (see the dashed dotted line in Figure 1). For example, the power supply unit 5 may supply the voltage-converted power to each component via the mounting board (e.g., a system board) of each component.

The built-in battery 6 is a power storage device that stores power, and is an example of a power supply device (battery). For example, the built-in battery 6 stores power supplied from the power supply unit 5, and when the supply of power from the power supply unit 5 stops (for example, when the supply of power from the power source 8 to the power supply unit 5 stops), it supplies the stored power to the power supply unit 5.

UPS7 is a power storage device that stores power, and is an example of a power supply device (battery). For example, UPS7 stores power supplied from power source 8 and supplies the power to power supply unit 5. If the supply of power from power source 8 is stopped, UPS7 supplies the stored power to power supply unit 5.

The power source 8 is an example of a power supply source, for example, a source of AC power such as a distribution board. In the example of FIG. 1, the power source 8 supplies power to the power supply unit 5 and the UPS 7 via a power supply path.

The server 1 can operate for a certain period of time using power supplied from the battery via the power supply unit 5, even if a sudden power outage (stoppage of power supply from the power source 8) occurs due to a power supply device (battery) such as an internal battery 6 and a UPS 7.

In other words, the power supply unit 5 is an example of a power supply unit that supplies power output from a battery that stores power from the power source 8 to each of the multiple processors 2a in response to a power outage of the power source 8.

In the example of FIG. 1, both the built-in battery 6 and the UPS 7 are connected to the power supply unit 5, but either the built-in battery 6 or the UPS 7 may be connected to the power supply unit 5, and the other may be omitted. Also, the connection between the power supply unit 5 and the power source 8 may be omitted.

Figures 2 and 3 are diagrams showing an example of the power consumption of a system when a power outage occurs. With reference to Figures 2 and 3, an example of a server 1 system that operates with power supplied from a power source 8 and starts battery operation at time t1 due to a power outage will be described.

As shown in FIG. 2, if the processor 2a continues to operate at power consumption p1 that exceeds the battery supply power (power amount) p2 after time t1, it becomes difficult to continue the shutdown process to shut down the system. The shutdown process may include a write-back process to write (save) the data (user data and system data) stored in the memory 3 back to the storage device 4.

As shown in FIG. 3, when processor 2a operates at power consumption p3 that is equal to or less than battery power supply p2 after time t1, processor 2a can appropriately perform the shutdown process using the battery power supply.

When all processes are moved to one processor 2a and then the stop process is executed as in the first method described above, the process of moving all processes continues after time t1, as shown in the example of FIG. 2. This may result in data loss due to insufficient battery capacity and the server 1 stopping with the stop process incomplete.

Furthermore, as in the second method described above, when the other processor 2a is stopped urgently, the power consumption of the system may drop to p3, which is equal to or less than the battery power supply p2, as shown in FIG. 3. However, if the resources of the other processor 2a cannot be released, the remaining processor 2a cannot complete the stop process because it has to wait for the resources to be released, and will continue to operate at the power consumption p3. Even in this case, the continued operation of the processor 2a may cause the battery capacity to run out, and the server 1 may stop with the stop process incomplete, resulting in data loss.

In one embodiment, a method is described for reducing power consumption in a short time by controlling it using software. This allows the shutdown process to be properly performed within the power supply of the battery, for example, and data protection to be achieved.

[1-2] Example of Processing by the Server According to an Embodiment First, an example of processing by the server 1 according to an embodiment will be briefly described.

The server 1 may execute, for example, the following processes (i) and (ii). In the following description, the processor 2a among the multiple processors 2a that has detected a power outage (power failure) is referred to as the parent processor 2a, and each of the one or more other processors 2a is referred to as a child processor 2a. The parent processor 2a is an example of a first processor, and the child processor 2a is an example of a second processor.

(i) In response to detection of a power outage, the parent processor 2a executes a first control to transition each of the one or more child processors 2a to a second power mode among a first power mode capable of executing a process and a second power mode that consumes less power than the first power mode.

The first power mode is, for example, a power mode in which the processor 2a operates in the system before the power is turned off, and the second power mode is, for example, a low power consumption mode, for example, a minimum power consumption mode.

For example, the parent processor 2a may notify one or more child processors 2a that it will reduce power consumption. Each child processor 2a that receives the notification transitions its power-related operating mode to the second power mode.

(ii) When each of the one or more child processors 2a transitions to the second power mode, the parent processor 2a executes a second control to transition each child processor 2a to the first power mode in a predetermined order, release resources used by a process executed by the child processor 2a, and transition to the second power mode.

For example, the parent processor 2a may return one or more child processors 2a one by one to their original operating mode (state) and release OS (Operating System) resources such as locks that are being used by the process. Examples of resources include shared resources in memory 3, or information (e.g., a flag) indicating that the shared resources will be used. After releasing the OS resources, the child processor 2a may transition its operating mode back to the low power consumption mode.

Figure 4 is a diagram showing an example of the power consumption of the system of server 1 by the above-described exemplary process. The example of Figure 4 shows an example of a case where battery operation is initiated due to a power outage in a system that operates with power consumption p1 using power supplied from power source 8. Note that in the example of Figure 4, processor #0 is the parent processor 2a, and processors #1 to #3 are child processors 2a.

As shown in FIG. 4, the above process (i) is executed at the timing indicated by A, and upon notification from parent processor #0, child processors #1 to #3 transition to the low power consumption mode during the period indicated by B. When child processors #1 to #3 transition to the low power consumption mode, parent processor #0 starts the above process (ii).

Child processors #1 to #3 release OS resources and transition back to low power consumption mode by executing process (ii) above at the times indicated by symbols C to E, respectively.

As described above, according to the server 1 of one embodiment, the above process (i) transitions one or more child processors 2a to the second power mode, so that, unlike the first method described above, the power consumption of the system can be reduced to or below the supply power p2 before switching to battery power.

Furthermore, by the above process (ii), each of the one or more child processors 2a is switched to the first power mode in a predetermined order (e.g., one by one in turn), the resources executed by the processes on the child processors 2a are released, and the processors are switched to the second power mode. This makes it possible to avoid a situation in which resources cannot be released and the stop process cannot be completed, as occurs with the second method described above.

Therefore, according to the technique of one embodiment, power consumption can be reduced in a short time. This allows, for example, the shutdown process to be appropriately performed within the power supply of the battery, thereby realizing data protection.

When executing the stop process, the server 1 may perform the following processes (iii) and (iv).

(iii) After the above process (ii), the parent processor 2a executes a third control in which it transmits an instruction to terminate the process executed by each of the one or more child processors 2a, transitions each child processor 2a to the first power mode in a predetermined order, and terminates the process executed by its own child processor 2a in response to the termination instruction.

This allows the parent processor 2a to reliably terminate the processes being executed by each child processor 2a during the stop process.

(iv) After the above process (iii), the parent processor 2a executes a fourth control to write the data stored in the memory 3 to the storage device 4 and shut down the system of the server 1.

For example, parent processor #0 may execute the above process (iv) at the timing indicated by symbol F in FIG. 4.

In this way, processors #0 to #3, which are respectively indicated by the two-dot chain line, dotted line, dashed line, and dot-dash line in Figure 4, transition one by one from the low power consumption mode to their original operating mode, for example an operating mode in which a program (process, thread) can be executed, at symbols C to F.

As a result, as shown in FIG. 4, the power consumption of the entire system, indicated by the solid line, can be reduced to approximately the power consumption p3 of one processor 2a, which is smaller than the maximum power supply p2 of the battery, and the shutdown process can be executed at the power consumption p3.

[1-3] Example of Functional Configuration Next, an example of the functional configuration of the server 1 that performs the above-mentioned processing will be described. Fig. 5 is a block diagram showing an example of the functional configuration of the server 1 according to one embodiment, and Fig. 6 is a diagram for explaining an example of the operation of the power consumption reduction control. In Fig. 6, the hatched section indicates the period during which the operation mode of the processor 2a is the low power consumption mode, and the diagonal line section indicates the operation period of the process termination unit 23 described later.

As shown in FIG. 5, when focusing on functions related to controlling the reduction of power consumption in the event of a power outage, the server 1 may illustratively include a processing unit 20 and a memory unit 30.

The processing unit 20 is an example of a control unit, and may be realized by the multiple processors 2a expanding a program into the memory 3 and executing it. For example, the processing unit 20 may be at least a part of the functions of an OS (Operating System) executed by the multiple processors 2a. Therefore, at least a part of the functions of the processing unit 20 may be realized by a process executed by one or more processors 2a, or a thread executed by each of the multiple processors 2a.

The memory unit 30 may be a storage area of at least one of the memory 3 and the storage device 4. In one embodiment, the memory unit 30 is a storage area of the memory 3.

In one embodiment, the memory unit 30 may store a whitelist 31. The memory unit 30 may also include a storage area used as a process execution queue 32. The process execution queue 32 is, for example, a queue in which processes to be executed by the OS are registered, and is a list of candidates for the next process to be executed that is managed by the kernel scheduler. The process execution queue 32 may also be referred to as a "run queue."

The whitelist 31 is information about the process used in the write-back process in which the parent processor 2a writes back data stored in the memory 3 to the storage device 4 in the above process (iii).

In the above process (ii), the parent processor 2a terminates the processes executed by each child processor 2a. At this time, if the process used for the write-back process is terminated (stopped), the execution of the write-back process may be hindered.

Therefore, in one embodiment, the processes used in the write-back process are registered in advance in the whitelist 31, so that they are not subject to the process termination process performed by the above-mentioned process (ii). Processes registered in the whitelist 31 include, for example, the processes used in the write-back process described above, as well as daemons that manage the entire system of server 1 and daemons that monitor the processes used in the write-back process.

As shown in FIG. 5, the processing unit 20 may illustratively include a generation unit 21, an interrupt communication unit 22, a process termination unit 23, a termination control unit 24, and a write-back processing unit 25.

The generation unit 21 generates a whitelist 31 and a process termination unit 23. For example, the generation unit 21 is a functional unit that executes a preparation phase for power consumption reduction control of the server 1, and may operate as an initial setting process during or after the startup process of the server 1, for example.

The whitelist 31 may be created in advance by, for example, a system administrator, in which case the generation unit 21 may read the whitelist 31 from the storage device 4 to the memory 3 (memory unit 30).

The process termination unit 23 is a functional unit that executes the process of terminating (stopping) the process in the child processor 2a in the above process (ii), and may be, for example, a plurality of threads, for example, a kernel thread for each processor 2a.

The generation unit 21 sets the generated process termination unit 23 to an execution priority higher than the execution priority of other processes in the OS, removes it from the process execution queue 32, and sets it to a sleep state.

For example, the generation unit 21 may set the execution priority of the generated process termination unit 23 to a value higher than the execution priority of other processes (e.g., the highest value). The execution priority of the process termination unit 23 may be set, for example, as the priority of a process in the OS, as an example, a nice value. The smaller the nice value, the higher the priority, and the larger the nice value, the lower the priority. For this reason, the generation unit 21 may set the nice value of the process termination unit 23 to a value lower than the nice values of other processes (e.g., the lowest value).

In this way, the process termination unit 23 (kernel thread) generated for each child processor 2a can be said to be a thread for terminating the process, with an execution priority set higher than that of the process executed by its own child processor 2a.

The interrupt communication unit 22 detects power outages and handles interrupt communication related to communication between processors 2a.

Here, as a method for detecting a power interruption by the processor 2a according to one embodiment, for example, an interrupt notification such as an NMI (Non-Maskable Interrupt) may be used. An NMI is an example of an interrupt that cannot be masked, and is an interrupt that can be notified to the processor 2a regardless of the convenience of the OS (Operating System) (for example, interrupt processing cannot be prohibited in the OS).

In the following description, the interrupt communication unit 22 is assumed to include at least part of the functionality of an NMI handler that is activated in response to receiving an NMI and processes the received NMI.

For example, in server 1, when power supply unit 5 detects a power outage from power source 8, power supply unit 5 transmits a power outage notification to HW such as a controller of server 1. The HW or FW (firmware) management daemon that receives the notification transmits an interrupt notification (NMI) to the OS.

The interrupt communication unit 22 may detect a power outage in the server 1 by receiving an NMI sent to the OS (see symbol (a) in FIG. 6). Hereinafter, the processor 2a that receives the NMI and starts the HMI handler is referred to as the parent processor 2a, and the other processors 2a other than the parent processor 2a are referred to as one or more child processors 2a.

The interrupt communication unit 22 may also transmit, for example broadcast, an interrupt notification (NMI) from the parent processor 2a to one or more child processors 2a instructing them to transition to the low power consumption mode (see symbol (b) in FIG. 6). The low power consumption mode is an example of the second power mode.

Furthermore, the interrupt communication unit 22 may transition the operating mode of each child processor 2a that receives an NMI from the parent processor 2a to a low power consumption mode in response to the received NMI (see symbol (c) in Figure 6).

The low power consumption mode may be, for example, any of the states defined as C-States, and one example is the C6 state. The C6 state is a state in which all cores of the processor 2a are stopped, and the internal state of the processor 2a, such as the registers, is stored externally, for example in a storage area of the memory 3.

Here, the reasons why the parent processor 2a transitions one or more child processors 2a to the low power consumption mode include the following:

For example, the interrupt communication unit 22 may send an interrupt notification (NMI) from the parent processor 2a to one or more child processors 2a to instruct them to terminate (stop) a process. In this case, the process termination process is executed by an NMI handler that is started in each child processor 2a in response to receiving the NMI.

However, when the OS executes process termination processing due to the operation of the NMI handler executed by child processor 2a, there is a possibility that a deadlock or the like may occur. This is because the timing of receiving the NMI may be unintended by the OS, such as when the OS is holding a lock on a resource. In this case, the OS may take actions such as attempting to hold the lock in order to terminate the process, and there is a possibility that the process termination processing may not be performed normally.

Therefore, in one embodiment, a process termination unit 23 that performs process termination processing, such as a kernel thread, is provided for each processor 2a in addition to the NMI handler that serves as the interrupt communication unit 22, so that the OS can start the termination processing at the timing intended.

For this reason, the interrupt communication unit 22 temporarily transitions all of the one or more child processors 2a to a low power consumption mode in order to have the process termination unit 23 execute termination processing in each child processor 2a.

For example, when all child processors 2a have transitioned to the low power consumption mode, the interrupt communication unit 22 transmits a return notification from the parent processor 2a to each of the child processors 2a in sequence. In response to the return notification, each child processor 2a transitions from the low power consumption mode to the original operating mode, for example, C0 state, in sequence (see symbol (d) in FIG. 6). The operating mode to which the transition is made in response to the return notification is an example of the first power mode.

The order in which the child processors 2a are returned may be in ascending or descending order of the identification information (e.g., number) of the processors 2a, or in the order in which the processes are terminated in the termination process. The order in which the child processors 2a are returned may be determined, for example, by a kernel scheduler.

The interrupt communication unit 22 wakes up the kernel thread serving as the process termination unit 23 corresponding to each child processor 2a from a sleep state by the NMI handler operating in each child processor 2a, and transitions it to an executable state. For example, the interrupt communication unit 22 may add the kernel thread to the process execution queue 32. Then, the interrupt communication unit 22 terminates the NMI handler in the child processor 2a in which the process termination unit 23 has become executable (see symbol (e) in FIG. 6).

When each child processor 2a returns to execution of the original process from the interrupt processing by the NMI handler, it releases resources such as locks.

When the process termination unit 23 receives control from the NMI handler in each child processor 2a (see symbol (e) in Figure 6), it transitions the child processor 2a to a low power consumption mode (see symbol (f) in Figure 6).

As described above, the process termination unit 23 has a high level (e.g., the highest level) of process execution priority. This allows each child processor 2a to reliably execute the process termination unit 23 (pass control to the process termination unit 23) after the NMI handler has finished.

For example, when all child processors 2a have transitioned to the low power consumption mode, the termination control unit 24 transmits a process termination instruction (termination instruction) from the parent processor 2a to each of the child processors 2a in sequence (see symbol (g) in FIG. 6). An example of a process termination instruction is a SIGKILL command (signal).

For example, the termination control unit 24 may refer to the whitelist 31 and send a process termination instruction to each process that is not registered in the whitelist 31. In other words, by referring to the whitelist 31, the termination control unit 24 excludes processes that execute a stop process (e.g., the above process (iv)) from the processes that are the target of the process termination instruction. This makes it possible to leave the processes that execute the stop process and to reliably terminate the other processes.

After sending the process termination instruction, the termination control unit 24 sequentially sends a notification of return from the low power consumption mode to the original operating mode to the process termination unit 23 of each child processor 2a from the parent processor 2a (see symbol (h) in FIG. 6). Note that, since the NMI handler is terminated in each child processor 2a, the return notification sent by the termination control unit 24 may be by a method other than NMI.

When the process termination unit 23 returns to the original operating mode from the low power consumption mode in response to receiving a return notification from the termination control unit 24, it removes (deletes) itself from the process execution queue 32 and passes control to the scheduler (see symbol (i) in Figure 6).

In the child processor 2a, processes other than the process termination unit 23 registered in the process execution queue 32 are executed (dispatched) sequentially.

As described above, a process termination instruction is issued by the termination control unit 24. Therefore, in the child processor 2a, the dispatched process terminates its own process upon receiving the process termination instruction.

In this way, the process termination unit 23 executed by each child processor 2a and the termination control unit 24 executed by the parent processor 2a work together to safely terminate (stop) the process executed by each child processor 2a.

In addition, when a process registered in the process execution queue 32 is executed according to the kernel scheduler, the process performs its own termination process in response to receiving a process termination instruction sent in advance from the parent processor 2a. This allows the child processor 2a to terminate the processes executed on its own processor 2a in the order in which they return from the low power consumption mode.

In addition, a child processor 2a that has terminated all processes running on its own processor 2a may transition itself to the C6 state.

When all processes not registered in the whitelist 31 have ended, the write-back processing unit 25 executes a write-back process to write back the data stored in the memory 3 to the storage device 4, and stops the system of the server 1, for example shutting it down.

[1-4] Operation Example Next, an operation example of the server 1 according to one embodiment configured as described above will be described with reference to Fig. 7 and Fig. 8. Fig. 7 is a flowchart for explaining an operation example of processing by the generation unit 21 of the server 1, and Fig. 8 is a flowchart for explaining an operation example of power consumption reduction control by the server 1.

[1-4-1] Processing by the Generation Unit As illustrated in Figure 7, the generation unit 21 creates a whitelist 31 that registers processes that are not subject to process termination instructions, such as a SIGKILL command, sent from the termination control unit 24 (step S1), and stores it in the memory unit 30.

The generation unit 21 also creates a process termination unit 23, for example a kernel thread, in each processor 2a (step S2). The generation unit 21 sets the process priority of the created process termination unit 23 to the highest level, puts the process termination unit 23 to sleep (step S3), and the processing ends.

8, when an NMI notifying a power cut occurs in the server 1 (step S11), the processor 2a that receives the NMI starts an NMI handler as the interrupt communication unit 22 in response to the reception of the NMI. The processor 2a, as the parent processor 2a, detects the power cut by recognizing the received NMI with the started NMI handler.

The interrupt communication unit 22 broadcasts an NMI from the parent processor 2a to all child processors 2a (step S12). The NMI is an example of an instruction to transition to the low power consumption mode.

The process from step S13 onwards branches into two cases: if the processor 2a is the parent processor 2a (YES in step S13, steps S21 to S27), and if the processor 2a is the child processor 2a (NO in step S13, steps S31 to S39). The process will be explained below according to the flow of processing on the server 1.

Each child processor 2a activates an NMI handler as the interrupt communication unit 22 in response to receiving the NMI broadcast in step S12, and the activated NMI handler recognizes the received NMI and detects an instruction to transition to the low power consumption mode. The interrupt communication unit 22 transitions each child processor 2a to the C6 state (step S31) and waits in the C6 state (step S32).

The interrupt communication unit 22 operating in the parent processor 2a waits until the operating mode of all child processors 2a transitions to the C6 state (step S21, NO in step S21). When the transition to the C6 state occurs (YES in step S21), the interrupt communication unit 22 transmits a return notification from the C6 state to each child processor 2a in turn (step S22).

The child processor 2a returns from the C6 state by the NMI handler in the order in which it received the return notification from the parent processor 2a (step S33). The interrupt communication unit 22 wakes up the process termination unit 23 and terminates the NMI handler (step S34). With the termination of the NMI handler, the child processor 2a releases resources such as locks (step S35).

The started process termination unit 23 transitions the power mode of the child processor 2a to the C6 state and waits (step S36).

The termination control unit 24 operating in the parent processor 2a waits for the execution of the process termination unit 23 (including waiting in C6 state) in all child processors 2a (step S23, NO in step S23).

When the process termination unit 23 is executed in all child processors 2a (YES in step S23), the termination control unit 24 refers to the whitelist 31 generated in step S1 of FIG. 7. The termination control unit 24 sends a process termination instruction, for example a SIGKILL command, to processes not registered in the whitelist 31 (step S24), and sends a return notification from the C6 state to each child processor 2a in turn (step S25).

The child processors 2a are returned from the C6 state by the process termination unit 23 in the order in which they received the return notification from the parent processor 2a (step S37). The process termination unit 23 removes itself from the process execution queue 32 and passes control to the kernel scheduler (step S38).

In the child processor 2a, the kernel scheduler executes the processes in the process execution queue 32. When the executed process receives the process end instruction sent in step S24, it ends its own process (step S39). When all processes targeted by the process end instruction are ended in each child processor 2a, the processing in the child processor 2a ends. When the processing in the child processor 2a ends, the child processor 2a may transition itself to the C6 state.

The termination control unit 24 of the parent processor 2a waits until all processes not registered in the whitelist 31 have terminated (step S26).

When all processes not registered in the whitelist 31 have been completed, the write-back processing unit 25 executes a write-back process to write the data stored in the memory 3 back to the storage device 4 (step S27), and the process ends. After the write-back process ends, the parent processor 2a may execute a shutdown sequence to stop the system of the server 1.

[1-5] Example of Hardware Configuration of Server Fig. 9 is a block diagram showing the HW configuration of the computer 10. The HW configuration of the computer 10, which is an example of the server 1, will be described below.

As shown in FIG. 9, the computer 10 may, as a HW configuration, illustratively include a processor 10a, a memory 10b, a storage unit 10c, an IF (Interface) unit 10d, an IO (Input/Output) unit 10e, and a reading unit 10f.

Processor 10a is an example of a processing unit that performs various controls and calculations. Processor 10a may be connected to each block in computer 10 via bus 10i so that they can communicate with each other. Processor 10a is an example of the processor group 2 shown in FIG. 1, and is a multiprocessor having multiple processors 2a. Processor 2a may be a multicore processor having multiple cores.

Memory 10b is an example of HW that stores various data, programs, and other information. Memory 10b is an example of memory 3 shown in FIG. 1, and may be, for example, one or both of a volatile memory such as DRAM and a non-volatile memory such as PM (Persistent Memory).

The storage unit 10c is an example of HW that stores various data, programs, and other information. The storage unit 10c is an example of the storage device 4 shown in FIG. 1, and examples of such storage devices include magnetic disk devices such as HDDs, semiconductor drive devices such as SSDs, and non-volatile memories.

The storage unit 10c may also store a program 10g (information processing program) that realizes all or part of the various functions of the computer 10. For example, each of the processors 2a can realize the function of the processing unit 20 illustrated in FIG. 5 by expanding the program 10g stored in the storage unit 10c into the memory 10b and executing it. The program 10g may be included in, for example, the OS or at least a part of the OS (e.g., a kernel).

The IF unit 10d is an example of a communication IF that controls the connection and communication with the network. For example, the IF unit 10d may include an adapter that complies with optical communications such as Ethernet (registered trademark), InfiniBand, Myrinet, or FC (Fibre Channel). The adapter may support one or both of wireless and wired communication methods. For example, the server 1 may be connected to a terminal device (not shown) used by an operator or system administrator via the IF unit 10d so that they can communicate with each other. Also, for example, the program 10g may be downloaded from the network to the computer 10 via the communication IF and stored in the storage unit 10c.

The IO unit 10e may include one or both of an input device and an output device. Examples of input devices include a keyboard, a mouse, a touch panel, etc. Examples of output devices include a monitor, a projector, a printer, etc.

The reading unit 10f is an example of a reader that reads data and program information recorded on the recording medium 10h. The reading unit 10f may include a connection terminal or device to which the recording medium 10h can be connected or inserted. Examples of the reading unit 10f include an adapter that complies with USB (Universal Serial Bus) or the like, a drive device that accesses a recording disk, and a card reader that accesses a flash memory such as an SD card. The recording medium 10h may store a program 10g, and the reading unit 10f may read the program 10g from the recording medium 10h and store it in the memory unit 10c.

Examples of the recording medium 10h include non-transitory computer-readable recording media such as magnetic/optical disks and flash memories. Examples of magnetic/optical disks include flexible disks, CDs (Compact Discs), DVDs (Digital Versatile Discs), Blu-ray Discs, and HVDs (Holographic Versatile Discs). Examples of flash memories include semiconductor memories such as USB memories and SD cards.

The above-described HW configuration of the computer 10 is an example. Therefore, the HW in the computer 10 may be increased or decreased (for example, adding or deleting any block), divided, or integrated in any combination, or buses may be added or deleted, as appropriate. For example, in the server 1, at least one of the IO unit 10e and the reading unit 10f may be omitted.

The computer 10 may also include a power supply unit 5 and an internal battery 6 as shown in FIG. 1, and a UPS 7 may be connected to the power supply unit 5. Note that one of the internal battery 6 and the UPS 7 may be omitted.

[2] Others The technology according to the embodiment described above can be modified and changed as follows.

For example, in the server 1 shown in FIG. 5, the functions of the generation unit 21, the interrupt communication unit 22, the process termination unit 23, the termination control unit 24, and the write-back processing unit 25 may be combined in any combination, or may be separated.

In addition, each of the interrupt communication unit 22 and the termination control unit 24 executed by the parent processor 2a is assumed to send a return notification to the child processors 2a in the C6 state one by one in sequence, but this is not limited to the above.

For example, if the relationship between the maximum power supply of the battery and the processing time of the stop process allows, a restore notification may be sent in parallel to two or more child processors 2a, and two or more child processors 2a may be restored in parallel. Alternatively, if the relationship between the maximum power supply of the battery and the processing time of the stop process allows, the parent processor 2a may restore one child processor 2a while the other child processor 2a is operating in the original operating mode. In other words, the parent processor 2a may overlap at least a portion of the period in which the original operating mode is in place between two or more child processors 2a.

In addition, the return notification is described as an instruction to transition the child processor 2a from the low power consumption mode to the original operating mode, but is not limited to this and may be an instruction to transition to an operating mode that consumes less power than the original operating mode.

[3] Supplementary Notes The following supplementary notes are further disclosed with respect to the above-described embodiment.

(Appendix 1)
A plurality of processors;
a power supply unit that supplies, in response to a power outage of a power supply source, power output from a battery that stores power from the power supply source to each of the plurality of processors;
A first processor of the plurality of processors,
a first control for transitioning each of one or more second processors among the plurality of processors to a second power mode among a first power mode capable of executing a process and a second power mode having lower power consumption than the first power mode in response to the detection of the power outage;
a second control for, when each of the one or more second processors has transitioned to the second power mode, transitioning each of the one or more second processors to the first power mode in a predetermined order, releasing resources used by the process executed by the second processor, and transitioning the second processor to the second power mode;
A control unit that executes
An information processing device comprising:

(Appendix 2)
The control unit is
a third control is executed to transmit an instruction to terminate a process executed by each of the one or more second processors after the second control, to cause each of the one or more second processors to transition to the first power mode in a predetermined order, and to terminate the process executed by the second processor in response to the instruction to terminate the process;
2. The information processing device according to claim 1.

(Appendix 3)
A volatile storage area;
A non-volatile storage area,
The control unit is
executing a fourth control to write the data stored in the volatile storage area to the non-volatile storage area and to shut down the information processing device after the third control;
3. The information processing device according to claim 2.

(Appendix 4)
the control unit excludes a process that executes the fourth control from processes that are subject to the termination instruction.
4. The information processing device according to claim 3.

(Appendix 5)
the first processor is a processor among the plurality of processors that receives an interrupt notification notifying the occurrence of the power outage detected by the power supply unit;
the control unit, in the first control, transmits an interrupt notification to each of the one or more second processors instructing the second processor to transition to the second power mode;
5. The information processing device according to claim 1 .

(Appendix 6)
Each of the one or more second processors:
In the first control, a transition to the second power mode is made by a handler activated in response to reception of the interrupt notification;
when receiving an instruction to transition to the first power mode under the second control, the handler is terminated, the resource is released, a thread for terminating the process, the thread having an execution priority set higher than that of the process executed by the second processor of the processor, is started, and the power mode is transitioned to the second power mode.
6. The information processing device according to claim 5.

(Appendix 7)
A computer including a plurality of processors and a power supply unit that supplies, in response to a power outage of a power supply source, power output from a battery that stores power from the power supply source to each of the plurality of processors,
A first control that transitions each of one or more processors among the plurality of processors to a second power mode among a first power mode capable of executing a process and a second power mode having lower power consumption than the first power mode in response to the detection of the power outage;
a second control for, when each of the one or more processors has transitioned to the second power mode, transitioning each of the one or more processors to the first power mode in a predetermined order, releasing resources used by the process executed by the processor, and transitioning the processor to the second power mode;
An information processing program that causes processing including the above to be performed.

(Appendix 8)
The computer includes:
a third control of transmitting an instruction to terminate a process executed by each of the one or more processors after the second control, transitioning each of the one or more processors to the first power mode in a predetermined order, and terminating the process executed by the processor in response to the instruction to terminate the process;
8. The information processing program according to claim 7, which causes a process including the steps of:

(Appendix 9)
The computer includes:
a fourth control for writing the data stored in the volatile storage area to a non-volatile storage area and shutting down the computer after the third control;
9. The information processing program according to claim 8, which causes a process including the steps of:

(Appendix 10)
The computer includes:
excluding a process that executes the fourth control from processes that are subject to the termination instruction;
10. The information processing program according to claim 9, which causes a process to be executed.

(Appendix 11)
The computer includes:
causing a processor, among the plurality of processors, that receives an interrupt notification notifying the occurrence of the power outage detected by the power supply unit to execute the first control and the second control;
the first control includes sending an interrupt notification to each of the one or more processors instructing the processor to transition to the second power mode;
The information processing program according to any one of claims 7 to 10.

(Appendix 12)
The computer includes:
In each of the one or more processors,
In the first control, a transition to the second power mode is made by a handler activated in response to reception of the interrupt notification;
when receiving an instruction to transition to the first power mode under the second control, the handler is terminated, the resource is released, a thread for terminating the process, the thread having an execution priority set higher than that of the process executed by the processor itself, is started, and the power mode is transitioned to the second power mode.
Execute the process,
12. The information processing program according to claim 11.

(Appendix 13)
A computer including a plurality of processors and a power supply unit that supplies, in response to a power outage of a power supply source, power output from a battery that stores power from the power supply source to each of the plurality of processors,
A first control that transitions each of one or more processors among the plurality of processors to a second power mode among a first power mode capable of executing a process and a second power mode having lower power consumption than the first power mode in response to the detection of the power outage;
a second control for, when each of the one or more processors has transitioned to the second power mode, transitioning each of the one or more processors to the first power mode in a predetermined order, releasing resources used by the process executed by the processor, and transitioning the processor to the second power mode;
An information processing method for performing a process including the steps of:

(Appendix 14)
The computer,
a third control of transmitting an instruction to terminate a process executed by each of the one or more processors after the second control, transitioning each of the one or more processors to the first power mode in a predetermined order, and terminating the process executed by the processor in response to the instruction to terminate the process;
14. The information processing method according to claim 13, further comprising:

(Appendix 15)
The computer,
a fourth control for writing the data stored in the volatile storage area to a non-volatile storage area and shutting down the computer after the third control;
15. The information processing method according to claim 14, further comprising:

(Appendix 16)
The computer,
excluding a process that executes the fourth control from processes that are subject to the termination instruction;
16. The information processing method according to claim 15, further comprising:

(Appendix 17)
The computer,
causing a processor, among the plurality of processors, that receives an interrupt notification notifying the occurrence of the power outage detected by the power supply unit to execute the first control and the second control;
the first control includes sending an interrupt notification to each of the one or more processors instructing the processor to transition to the second power mode;
17. An information processing method according to any one of claims 13 to 16.

(Appendix 18)
The computer,
In each of the one or more processors,
In the first control, a transition to the second power mode is made by a handler activated in response to reception of the interrupt notification;
when receiving an instruction to transition to the first power mode under the second control, the handler is terminated, the resource is released, a thread for terminating the process, the thread having an execution priority set higher than that of the process executed by the own processor, is started, and the power mode is transitioned to the second power mode.
Execute the process,
18. The information processing method according to claim 17.

REFERENCE SIGNS LIST 1 Server 10 Computer 2 Processor group 2a Processor 20 Processing section 21 Generation section 22 Interrupt communication section 23 Process termination section 24 Termination control section 25 Write-back processing section 3 Memory 30 Memory section 31 White list 32 Process execution queue 4 Storage device 5 Power supply section 6 Built-in battery 7 Uninterruptible power supply (UPS)
8. Power Source

Claims (8)

A plurality of processors;
a power supply unit that supplies, in response to a power outage of a power supply source, power output from a battery that stores power from the power supply source to each of the plurality of processors;
A first processor of the plurality of processors,
a first control for transitioning each of one or more second processors among the plurality of processors to a second power mode among a first power mode capable of executing a process and a second power mode having lower power consumption than the first power mode in response to the detection of the power outage;
a second control for, when each of the one or more second processors has transitioned to the second power mode, transitioning each of the one or more second processors to the first power mode in a predetermined order, releasing resources used by the process executed by the second processor that has been transitioned to the first power mode , and transitioning the second processor to the second power mode;
A control unit that executes
An information processing device comprising: The control unit is
executing a third control of transmitting, after the second control, an instruction to terminate a process executed by each of the one or more second processors , transitioning each of the one or more second processors to the first power mode in a predetermined order, and terminating , in response to the termination instruction, the process executed by the second processor that has been transitioned to the first power mode ;
The information processing device according to claim 1 . A volatile storage area;
A non-volatile storage area,
The control unit is
executing a fourth control to write the data stored in the volatile storage area to the non-volatile storage area and to shut down the information processing device after the third control;
The information processing device according to claim 2 . the control unit excludes a process that executes the fourth control from processes that are subject to the termination instruction.
The information processing device according to claim 3 . the first processor is a processor among the plurality of processors that receives an interrupt notification notifying the occurrence of the power outage detected by the power supply unit;
the control unit, in the first control, transmits an interrupt notification to each of the one or more second processors instructing the second processor to transition to the second power mode;
The information processing device according to any one of claims 1 to 4. Each of the one or more second processors:
In the first control, a transition to the second power mode is made by a handler activated in response to reception of the interrupt notification;
when receiving an instruction to transition to the first power mode under the second control, the handler is terminated, the resource is released, a thread for terminating the process, the thread having an execution priority set higher than that of the process executed by the second processor, is started, and the power mode is transitioned to the second power mode.
The information processing device according to claim 5 . A computer including a plurality of processors and a power supply unit that supplies, in response to a power outage of a power supply source, power output from a battery that stores power from the power supply source to each of the plurality of processors,
A first control that transitions each of one or more processors among the plurality of processors to a second power mode among a first power mode capable of executing a process and a second power mode having lower power consumption than the first power mode in response to the detection of the power outage;
a second control for switching each of the one or more processors to the first power mode in a predetermined order when each of the one or more processors has switched to the second power mode, releasing resources used by the process executed by the processor that has been switched to the first power mode , and switching the processor to the second power mode;
An information processing program that causes processing including the above to be performed. A computer including a plurality of processors and a power supply unit that supplies, in response to a power outage of a power supply source, power output from a battery that stores power from the power supply source to each of the plurality of processors,
A first control that transitions each of one or more processors among the plurality of processors to a second power mode among a first power mode capable of executing a process and a second power mode having lower power consumption than the first power mode in response to the detection of the power outage;
a second control for switching each of the one or more processors to the first power mode in a predetermined order when each of the one or more processors has switched to the second power mode, releasing resources used by the process executed by the processor that has been switched to the first power mode , and switching the processor to the second power mode;
An information processing method for performing a process including the steps of:

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