JP7457589B2 - Information processing device, information processing method, and information processing system - Google Patents

Description

The present invention relates to an information processing apparatus, an information processing method, and an information processing system that process information.

Patent Document 1 listed below discloses a multi-core arithmetic device having a plurality of CPU cores. This multi-core arithmetic device includes a first core, a second core that operates independently of the first core, and a shared memory, and both cores communicate via the shared memory. The first core executes a behavior schedule application that determines a behavior schedule that indicates the order of behavior changes of a vehicle drive transmission device that is a controlled object. The second core executes an actuator control application that controls an actuator that operates the vehicle drive transmission device, and a sensing application that acquires and provides physical information.

Patent Document 2 below discloses a processing system included in a computer system that is integrated with a vehicle user interface. The processing system includes a multi-core processor. The processing system is configured to provide virtualization to a first guest operating system on one or more first cores of the multi-core processor. The processing system is also configured to provide virtualization to a second guest operating system on one or more second different cores of the multi-core processor. The first guest operating system is configured for reliable operation. Virtualization prevents the operation of the second guest operating system from disrupting the reliable operation of the first guest operating system.

JP 2018-013843 A Special table 2017-507401 publication

However, in Patent Document 1 and Patent Document 2 mentioned above, real-time performance required of an embedded system is not considered. In particular, in an on-vehicle ECU (Electronic Control Unit), it is necessary to transmit control calculation results to a downstream controller or actuator within a certain period of time. Therefore, there is a time constraint from the start to the end of ECU processing.

In order for the ECU to complete a process within a predetermined time, it is necessary to accurately predict the execution time of all the tasks that make up the process, and to perform scheduling so that the total execution time meets the time requirement. be. However, in a multi-core processor, contention occurs when multiple cores use the cache memory at the same time, causing fluctuations in execution time. Cache behavior is complex and difficult to model, and variations in execution time due to cache contention are difficult to predict.

Furthermore, if there is a lot of cache contention, the processing efficiency of the cores drops significantly. Therefore, the allocation and scheduling of tasks to be executed by a multi-core processor must be designed to reduce cache contention.

The present invention aims to improve the processing efficiency of multi-core processors while maintaining real-time performance.

An information processing device that is one aspect of the invention disclosed in this application includes a processor that executes a program, and a storage device that stores the program, and is shared by a core group and a plurality of cores in the core group. An information processing device that generates a schedule for a multi-core processor having memory resources including a shared memory to execute a processing group, the information processing device being able to access processing group information and execution time fluctuation rate information, and having access to processing group information and execution time fluctuation rate information. defines, for each process in the process group, the independent execution time on one core in the core group, the control cycle of the process, and the dependence relationship with other processes, and The rate information defines an execution time variation rate when the core executes parallel execution with other cores, and the processor determines the control cycle of the process and the independent execution of the process for each process of the process group. time, the rate of variation in the execution time of the process by the core when the core that executes the process is executed in parallel with another core that executes another process, and the subsequent process that is executed after the process in the dependency relationship. a calculation step of calculating grace time until the start of execution of the process based on the execution time fluctuation rate of , and a grace time for each process calculated by the calculation process, an allocation step for determining the execution order for each core based on the allocation result of the allocation step, and an execution order for each core determined by the determination step and the execution time fluctuation rate information. A specific step of identifying an execution time variation rate of the first process by the first core when a first core that executes the first process executes the second core that executes the second process in parallel with the second core that executes the second process. , the execution time variation rate of the first core, and the independent execution time when the first core independently executes the first process in the processing group information, the first core in the execution order A generation step of calculating an execution time for executing the first process and generating the schedule.

According to a typical embodiment of the present invention, it is possible to improve multi-core processing efficiency while maintaining real-time performance. Problems, configurations, and effects other than those described above will become clear from the description of the following examples.

FIG. 1 is an explanatory diagram showing an example of scheduling a group of tasks to a multi-core processor by the schedule generation device according to the first embodiment. FIG. 2 is a block diagram showing an example of a hardware configuration of the mobile object control device. FIG. 3 is a block diagram showing an example of the hardware configuration of the ECU. FIG. 4 is a block diagram showing an example of a hardware configuration of a multi-core processor. FIG. 5 is an explanatory diagram showing an example of a processing configuration of an automatic driving application executed by a multi-core processor. FIG. 6 is an explanatory diagram showing an example of a task set. FIG. 7 is a block diagram showing an example of the hardware configuration of the schedule generation device. FIG. 8 is a block diagram of an example of a functional configuration of the information processing system according to the first embodiment. FIG. 9 is an explanatory diagram showing an example of an execution time fluctuation rate table according to the first embodiment. FIG. 10 is a flowchart illustrating an example of a schedule generation processing procedure by the generation unit according to the first embodiment. FIG. 11 is a block diagram showing an example of the functional configuration of the ECU according to the first embodiment. FIG. 12 is a block diagram showing a functional configuration example 1 of the information processing system according to the second embodiment. FIG. 13 is a flowchart illustrating an example of a core allocation processing procedure by the allocation unit according to the second embodiment. FIG. 14 is an explanatory diagram showing an example 1 of core allocation processing by the allocation unit. FIG. 15 is a diagram illustrating a second example of a core allocation process performed by the allocation unit. FIG. 16 is a flowchart illustrating an example of a schedule generation processing procedure by the generation unit according to the second embodiment. FIG. 17 is a block diagram showing a functional configuration example 2 of the information processing system according to the second embodiment. FIG. 18 is a block diagram showing an example of the functional configuration of the ECU according to the second embodiment. FIG. 19 is an explanatory diagram showing the definition of resource attributes. FIG. 20 is a diagram illustrating an example of an execution time variation rate table according to the third embodiment. FIG. 21 is an explanatory diagram showing an example of the execution order determined in the third embodiment. FIG. 22 is an explanatory diagram showing an example of a task execution result based on the worst execution time during independent execution. FIG. 23 is an explanatory diagram showing a schedule that takes into account the execution time fluctuation rate due to cache contention based on the execution time fluctuation rate table of the third embodiment. FIG. 24 is an explanatory diagram showing an example of an execution time fluctuation rate table according to the fourth embodiment.

<Scheduling example>
FIG. 1 is an explanatory diagram showing an example of scheduling a group of tasks to a multi-core processor by the schedule generation device according to the first embodiment. In FIG. 1, a multi-core processor 100 including core #0 and core #1 to which tasks A to H are assigned will be exemplified and explained. In multi-core processor 100, core #0 and core #1 may compete in shared memory (for example, secondary cache) due to parallel execution of tasks A to H. Tasks A to H are, for example, processing units that can be executed in parallel within an application or a process that constitutes the application.

The schedule generation device is an information processing device that generates a schedule 102 for a multi-core processor 100 in a vehicle-mounted ECU that is a scheduling target. Specifically, for example, the schedule generation device (a) calculates a grace period for each task A to H, taking into account contention for the secondary cache due to parallel execution with other tasks; Cores are assigned to each task in order of the shortest grace time, and (c) an execution order 101 indicating the start point of execution of tasks A to H for each core #0 and #1 based on the assignment in (b) is determined. As a result, schedule 102 is generated. The generated schedule 102 is implemented in the multi-core processor 100.

In (a), the schedule generation device calculates the grace period until the start of execution for each of tasks A to H. The grace period is set to be shorter than the individual execution time when tasks A to H are executed alone, in order to take into account secondary cache contention due to parallel execution with other tasks.

In (b), the schedule generation device performs tasks A to H in (a) in order of shortest grace time (A⇒G⇒B⇒E⇒H⇒D⇒F⇒C. Note that if the grace times are the same, In alphabetical order), tasks A to H are preferentially assigned to cores with a low cumulative core usage rate. The cumulative core usage rate is the cumulative value of the core usage rates of tasks that have been assigned by being assigned tasks A to H in each core #0 and #1.

For example, first, the schedule generation device assigns task A to core #0. The core usage rate of task A is assumed to be "0.2". As a result, the cumulative core usage rate of core #0 is updated from "0" to "0.2".

Next, the schedule generation device assigns task G to core #1 with a lower cumulative core usage rate. The core usage rate of task G is assumed to be "0.2". As a result, the cumulative core usage rate of core #1 is updated from "0" to "0.2".

Next, the schedule generation device assigns task B to the core #0 with the smaller cumulative core usage rate (if the cumulative core usage rates are the same, the core number #0 is smaller). The core usage rate of task B is assumed to be "0.3". As a result, the cumulative core usage rate of core #0 is updated from "0.2" to "0.5". The schedule generation device executes such allocation up to task C with the longest grace period, and generates an execution order 101 of tasks A to H for each core #0 and #1 as shown in (c).

In (c), the execution order 101 indicates an order in which core #0 executes tasks A, B, and H assigned in the order of shortest grace time, and core #1 executes tasks G, E, F, and C assigned in the order of shortest grace time. Note that if tasks with the same grace time are assigned to the same core, the schedule generation device may adjust the grace time to be different.

(c) Next, the schedule generation device generates the schedule 102, taking into account the individual execution times of tasks A to H and variations in execution times. The independent execution time is the execution time during which a core executing a task executes the task without cache memory contention with other cores executing other tasks. For example, it is the execution time of a task that uses only the primary cache.

Fluctuation in execution time means that the execution time increases or decreases due to consideration of cache memory contention due to parallel execution with other tasks. Specifically, for example, when tasks A to H are executed in parallel with other tasks, the execution time becomes longer than when the tasks are executed alone. Therefore, the schedule generation device generates the schedule 102 by predicting and scheduling the execution times of tasks A to H, taking into account variations in execution time due to parallel execution of each of tasks A to H with other tasks. .

Then, the schedule generation device performs deadline verification. Deadlines are the control periods of tasks A to H. For example, the deadline for tasks A and G is DL1 (for example, 50 ms), and the deadline for tasks B to F and H is DL2 (for example, 100 ms).

Since tasks A and G meet the deadline DL1, and tasks B to F and H also meet the deadline DL2, the schedule 102 is finalized and implemented in the multi-core processor 100. In this way, it is possible to improve the real-time performance of the processing of tasks A to H in the multi-core processor 100, and to improve the processing efficiency of tasks A to H.

<Example of hardware configuration of mobile object control device>
FIG. 2 is a block diagram showing an example of the hardware configuration of the mobile object control device. The mobile object control device 200 is an information processing device that is mounted on the mobile objects V1 and V2 such as vehicles to be controlled and controls the mobile objects V1 and V2, and the schedule 102 shown in FIG. 1 is implemented.

The mobile control device 200 includes an ECU group 210s, a gateway 211, and a communication module 212. The ECU group 210s includes various ECUs such as an automatic driving ECU 210A, a sensor ECU 210B, a brake ECU 210C, a door ECU 210D, a display ECU 210E, and a car navigation ECU 210F (if these are not distinguished, they are simply referred to as ECU 210). ECU 210 includes multi-core processor 100 shown in FIG. Each ECU 210 can communicate with other ECUs 210 directly or via gateway 211.

Gateway 211 enables communication between ECUs 210. Further, the gateway 211 enables communication between the ECU 210 and the cloud 201 and the mobile body control device 200 of the other mobile body V2 in order to avoid traffic accidents and traffic jams, obtain map information, and calculate optimal routes. The mobile control device 200 includes a group of ECUs 210s and a gateway 211 to form a CAN (Controller Area Network).

<ECU hardware configuration example>
FIG. 3 is a block diagram showing an example of the hardware configuration of the ECU 210. ECU 210 includes an MCU (Micro Controller Unit) 301, a power supply circuit 302, an input/output processing circuit 303, and a communication circuit 304. MCU 301 includes a multi-core processor 100 and external memory 310.

The power supply circuit 302 supplies and cuts off power to the MCU 301, the input/output processing circuit 303, and the communication circuit 304. The input/output processing circuit 303 processes input signals to the MCU 303 and output signals from the MCU 303. The communication circuit 304 receives data from other ECUs 210 to MCU 301, and transmits data from MCU 301 to other ECUs 210.

<Example of hardware configuration of multi-core processor 100>
FIG. 4 is a block diagram showing an example of the hardware configuration of the multi-core processor 100. The multi-core processor 100 includes a core group (in FIG. 4, for example, core #0 to core #3, ...) 401, a primary cache 402, a secondary cache 403 used between the cores, and an internal bus 404. , has.

The primary cache 402 is a cache memory that is provided for each core, can be accessed by only one core, and is not shared with other cores. The secondary cache 403 is a cache memory that can be shared and accessed by a plurality of cores via the primary cache 402. Although two secondary caches 403 are provided in FIG. 4, one secondary cache 403 may be shared by core #0 to core #3.

The internal bus 404 communicably connects the core group 401 and peripheral devices (external memory 310, input/output processing circuit 303, communication circuit 304, sensor 410). For example, a detection signal from sensor 410 is written to external memory 310 via input/output processing circuit 303 and internal bus 404. Similarly, communication data from other ECUs 210 is also written to external memory 310 via communication circuit 304 and internal bus 404.

Note that, like the secondary cache 403, the external memory 310 is also a memory that can be shared and accessed by a plurality of cores. The primary cache 402, secondary cache 403, and external memory 310 are collectively referred to as memory resources. Furthermore, the secondary cache 403 and external memory 310 are collectively referred to as shared memory. Note that memory resources closer to the core have shorter access times and smaller sizes.

Note that although FIG. 3 shows an example in which one multi-core processor 100 is installed in the MCU 301, a plurality of multi-core processors 100 may be installed. Further, a processor group in which a plurality of single-core processors are mounted in the MCU 301 may also be used as the multi-core processor 100.

<Example of processing configuration of automatic driving application>
FIG. 5 is an explanatory diagram showing an example of a processing configuration of an automatic driving application executed by the multi-core processor 100. In FIG. 5, the automatic driving application 500 is composed of tasks A to H, for example. For example, task A is sensor data reception, task B is map integration, task C is route planning, task D is HMI (Human Machine Interface) display, task E is image processing, task F is cloud communication, and task G is sensor diagnosis. (reception), and task H is sensor diagnosis (check).

The arrows indicate dependencies 606 between tasks. The direction from the start of the arrow to the end indicates writing (write) data to the shared memory (secondary cache 403 or external memory), and the direction from the end of the arrow to the start indicates reading (read) data from the shared memory (secondary cache 403 or external memory 310).

Of the 100 KB of sensor data that task A received, 90 KB of data 501AB is used by task B, and 10 KB of data 501AD is used by task D. Further, among the map integration result data of task B, 501 KB of data 501BC is used for route planning in task C.

Further, 3 MB of image data 501EF from task E is shared by task F, and a portion of it is sent to cloud 201. In sensor diagnosis, 1 KB of sensor data 501GH acquired in task G is used in task H for diagnosis.

<Task set>
FIG. 6 is an explanatory diagram showing an example of a task set. The task set 600 is a data table having information regarding tasks A to H. The task set 600 is stored in, for example, the schedule generation device or the mobile object control device 200.

The task set 600 has the following fields: task name 601, control period 602, worst execution time when executed alone 603, core usage rate 604, memory consumption 605, and dependency relationship 606. The task name 601 is a name that acts as identification information to uniquely identify tasks A to H. Hereinafter, any one of tasks A to H will be referred to as task X.

The control period 602 is a period for controlling the task X, and is a period during which the task X starts executing and must end, that is, the deadlines DL1 and DL2. The worst execution time 603 during independent execution is the worst execution time when the task X is executed independently without conflicting with the secondary cache 403. The worst execution time is the longest execution time when the individual execution time of the task X is measured multiple times. Note that instead of the worst execution time, the average value or median of individual execution times may be used.

The core usage rate 604 is the usage rate of the core when the task X is executed by the core. The core usage rate 604 is obtained, for example, by dividing the worst execution time 603 during single execution by the control period 602.

The memory consumption amount 605 is the consumption amount of the memory (primary cache 402, secondary cache 403, external memory 310) used when the task X is executed, that is, the amount of memory written to the memory from the core that executed the task This is the amount of data that can be stored.

The dependency relationship 606 defines other tasks to which task X receives or receives data, that is, other tasks that share data. In the dependency relationship 606, "(w)" defines another task to which task X will receive data. That is, it shows the task at the end of the arrow between tasks in FIG.

“(r)” defines another task from which data is delivered to task X. That is, it shows the task on the starting end side of the arrow between tasks in FIG. For example, in the case of task B, task A is the source of data transfer to task B, and task C is the destination of data transfer from task B.

As shown in FIGS. 5 and 6, in the automatic driving application 500 (which may also be an ADAS (Advanced Driver-Assistance Systems) application), a large amount of data is exchanged between tasks. Furthermore, there are time constraints on the series of processes from sensing to vehicle control.

When the automatic driving application 500 shown in FIG. 5 is executed on the multi-core processor 100, the behavior of the secondary cache 403 has a strong influence on processing efficiency. If core allocation can be performed so that data is shared between tasks via the secondary cache 403, the efficiency of use of the secondary cache 403 will improve.

On the other hand, if the core group 401 simultaneously uses the secondary cache 403, contention occurs and the external memory 310 is frequently accessed, resulting in a decrease in the processing performance of the multi-core processor 100. Therefore, by applying the schedule 102 generated by the schedule generating device to the multi-core processor 100, contention for the secondary cache 403 is reduced and the utilization efficiency of the secondary cache 403 is improved. This makes it possible to improve processing efficiency while maintaining the real-time nature of processing by the multi-core processor 100.

<Example of hardware configuration of schedule generation device>
7 is a block diagram showing an example of a hardware configuration of a schedule generating device. The schedule generating device 700 includes a processor 701, a storage device 702, an input device 703, an output device 704, and a communication interface (communication IF) 705. The processor 701, the storage device 702, the input device 703, the output device 704, and the communication IF 705 are connected by a bus 706. The processor 701 controls the schedule generating device 700. The storage device 702 is a working area for the processor 701. The storage device 702 is a non-transient or temporary recording medium that stores various programs and data. Examples of the storage device 702 include a ROM (Read Only Memory), a RAM (Random Access Memory), a HDD (Hard Disk Drive), and a flash memory. The input device 703 inputs data. The input device 703 may be, for example, a keyboard, a mouse, a touch panel, a numeric keypad, or a scanner. The output device 704 outputs data. The output device 704 may be, for example, a display, a printer, or a speaker. The communication IF 705 connects to a network and transmits and receives data.

<Example of functional configuration of information processing system>
FIG. 8 is a block diagram showing an example of the functional configuration of the information processing system according to the first embodiment. Information processing system 800 includes schedule generation device 700 and ECU 210. As shown in FIG. 1, the schedule generation device 700 (a) allocates a core to each task The information processing apparatus generates (c) a schedule 102 in which each core executes task X based on an execution order 101.

The schedule generation device 700 and the ECU 210 may be connected to be able to communicate with each other, or may not be connected to be able to communicate with each other as long as data can be transferred manually. For example, when designing a task for the ECU 210, the schedule generation device 700 does not need to be connected to be able to communicate with the ECU 210.

When manufacturing the ECU 210, the external memory 310 storing the schedule 102 may be mounted on the ECU 210. Further, when manufacturing the ECU 210, the schedule generation device 700 and the ECU 210 may be communicably connected, and the schedule 102 may be transmitted from the schedule generation device 700 to the ECU 210.

The schedule generation device 700 may be one of the servers that make up the cloud 201. In this case, for example, after ECU 210 is installed in mobile body V1, schedule generation device 700 regenerates schedule 102 and transmits it to mobile body control device 200, for example, in accordance with the update of task X. The mobile control device 200 overwrites the received latest schedule 102 in the external memory 310 of the ECU 210 that executes the task X.

ECU 210 includes a task set 600 and an operating system 810. Task set 600 is stored in external memory 310, for example. Operating system 810 is executed by, for example, cores to which tasks AH are not assigned. Specifically, for example, if tasks A to H are assigned to core #0 and core #1, the operating system 810 selects core #0 and core #1 that do not conflict with the secondary cache 403. 2 or core #3.

Furthermore, if tasks A to H are assigned to cores #0 to #3, the operating system 810 runs on a core (not shown) where there is no contention between cores #0 to #3 and the secondary cache 403. If the operating system 810 runs on cores #0 to #3 to which task X is assigned, the cumulative core usage rates of cores #0 to #3 will include the core usage rate by the operating system 810.

The operating system 810 includes a scheduler 811 and a resource monitoring unit 812. When designing tasks for the ECU 210, the operating system 810 assigns each task A to H included in the input task set 600 to the core, and the scheduler 811 assigns each task A to H assigned to the core. Set the execution start time.

The resource monitoring unit 812 records resource usage information such as the execution time of task It is saved in the external memory 310 as a file.

The schedule generating device 700 has a task set 600, an execution time variation rate table 820, and a generating unit 830. Specifically, the task set 600 and the execution time variation rate table 820 are stored in, for example, the storage device 702 shown in FIG. 6. Specifically, the generating unit 830 is realized by, for example, having the processor 701 execute a program stored in the storage device 702 shown in FIG. 6.

As shown in FIG. 1, the generation unit 830 refers to the task set 600 and (a) calculates grace time for each task A to H, and (b) executes core assignment for each task A to H. (c) determine an execution order 101 indicating the start point of execution of tasks A to H for each core, and (d) predict and schedule the execution time for each core to execute tasks A to H according to the execution order 101. 102 is generated.

Specifically, for example, in order to execute (a) to (d) above, the generation unit 830 executes parallel execution of the task X and another task (referred to as Y) based on the memory consumption amount 605 of the task X. It has an execution time prediction model that predicts the parallel execution time of the task X when the task X is executed in parallel. The execution time prediction model is created based on the resource usage information obtained from the resource monitoring unit 812. The generation unit 830 predicts the execution time of the task X by inputting the memory consumption amount 605 of the task X into the execution time prediction model.

The cache memory usage status by the core group 401 changes depending on the memory size used by the task X executed by each core. By using the memory consumption amount 605 of task X, the generation unit 830 can predict fluctuations in execution time caused by cache contention.

The generation unit 830 takes such fluctuations in execution time into account and determines the grace time, core allocation, and execution start time for each task X that will reduce the increase in parallel execution time, and creates the schedule 102 generate. This makes it possible to schedule a group of tasks while maintaining real-time performance.

The execution time prediction model described above is a model that predicts the execution time variation that occurs when the prediction target task X is executed simultaneously with another task Y, compared to the independent execution time when only the prediction target task be. The generation unit 830 acquires a wide variety of resource usage information, and creates an execution time prediction model based on the resource usage information. This improves the execution time prediction accuracy. The generation unit 830 uses the execution time prediction model to predict the execution time of the task X using the execution time variation rate table 820 due to cache contention.

<Execution time fluctuation rate table 820>
FIG. 9 is an explanatory diagram showing an example of the execution time fluctuation rate table 820 according to the first embodiment. The execution time fluctuation rate table 820 refers to the resource usage information and calculates the memory consumption amount 605 of core #j (j is an integer greater than or equal to 0) that executes task X, and the memory consumption amount 605 of core #j that executes task Y (≠X). This is execution time fluctuation rate information that defines the execution time fluctuation ^rate _α For example, ^the execution time variation rate _α Ru.

α _X ^Y = e _X ^Y / e _X ...(1)

In the above formula (1), e _X is the execution time (independent execution time) when core _#j executes task ^X , and e This is the execution time (parallel execution time) of task X by core #j when executed. The execution time variation rate α _X ^Y takes a value of 1 or more. In other words, if α _X ^Y = 1, the execution time of task X on core #j does not change even if core #j executes task means.

On the other hand, if α _X ^Y _> 1, when tasks X and Y are executed in parallel by core #j and core ^#k , the parallel execution time _e means it will be longer than For example ^, if the memory consumption 605 _of task >1).

The execution time variation rate table 820 can be used for a combination of cores with the same performance as the combination of core #j and core #k. A separate execution time variation rate table 820 is prepared for a combination of cores with the same performance as the combination of core #j and core #k. Furthermore, although the execution time variation rate table 820 defines the execution time variation rate α _X ^Y for a combination of two cores, the execution time variation rate α _X ^Y may be defined for a combination of three or more cores.

In the execution time variation rate table 820, the memory consumption amount 605 of the core #j and the memory consumption amount 605 of the core #k are specified as discrete values, but may be specified as ranges. For example, "10 KB" may mean 10 KB or less, and "20 KB" may mean 20 KB or less (excluding 10 KB or less). The same applies to 30 KB, ..., 8 MB. In addition, the execution time variation rate information may be a function that outputs the execution time variation rate α _XY when the memory consumption amount 605 of the core #j and the memory consumption amount 605 of the core #k are given, instead of a table format like the execution time variation rate table 820.

When predicting parallel execution time, the generation unit 830 reads the memory consumption amount 605 of task X executed by core #j from the task set 600, and reads the memory consumption amount 605 of task Y executed by core #k from the task set 600 Then, from the execution time fluctuation rate table 820, the execution time fluctuation rate α _X ^Y specified by the read memory consumption amount 605 is read out. The generation unit 830 also reads out the worst execution time 603 of the individual execution of the task X executed by the core #j from the task set 600 as the individual execution time _eX .

By substituting ^the read execution _time variation rate _α The execution time e _X ^Y is calculated as a predicted value of the execution time of the task X.

<Example of schedule generation processing procedure>
FIG. 10 is a flowchart illustrating an example of a schedule generation processing procedure by the generation unit 830 according to the first embodiment. The generation unit 830 calculates the grace time until the start of execution for each task X based on the subsequent task Z and the execution time fluctuation rate α _X ^Y (step S1001). The successor task (referred to as Z) is a task on one route to which data from task X is directly or indirectly transferred.

For example, on the path from task A⇒B⇒C, task C has no successor task Z, task B's successor task Z is task C, and task A's one successor task Z is B and C. be. Further, on the path from task A to D, task D does not have a successor task Z, and task A's successor task Z is task D. In step S1001, the core to which any task X is assigned has not been determined, and it is not known which task X will be executed in parallel.

Therefore, assuming that task X ^is assigned to core #j, which of the execution time fluctuation rates _α For example, the worst value (here, the maximum value) is used. For example, if the memory consumption amount 605 of task X assigned to core #j is 8 MB, "1.7" is the worst value of the execution time variation rate α _X ^Y. Note that the value is not limited to the worst value, but may be a statistical value such as an average value or a median value.

In addition, when there are multiple execution time fluctuation rate tables 820 for core #j, in the multiple execution time fluctuation rate tables 820, the execution time fluctuation rate in the row of memory consumption 605 of task X executed on core #j Any value of α _X ^Y , for example, the worst value (here, the maximum value) is used.

Then, the generation unit 830 calculates the grace period Tg(X) of the task X using the following equation (2).

Tg(X)=DL(X)−{α _wst (X)×T _wst (X)+Σ(α _wst (Z _i )×T _wst (Z _i ))}
However, if Tg(X)<0, Tg(X)=0
...(2)

DL(X) is the control period 602 of task X. α _wst (X) is any value (for example, the worst value) of the execution time fluctuation rate α _X ^Y in the row of the memory consumption amount 605 of task It is. T _wst (X) is the worst execution time 603 when task X is executed alone.

α _wst (Z _i ) is the worst value of the execution time variation rate α _XY in the row of the memory consumption 605 of the i-th succeeding task Z _i of task X executed on core ^#j in the execution time variation rate table 820. Here, the number of succeeding tasks i is an integer satisfying 0≦i≦n. When i=0, there is no succeeding task Z _i .

Specifically, for example, the generation unit 830 refers to the dependency relationship 606 of the task set 600 and sequentially selects the task X to be executed last. For example, the generation unit 830 selects task C. Since task C has no successor task Z _i (i=0), the generation unit 830 calculates the grace time Tg(C) until the start of execution of task C using the above equation (2) with i=0. .

In this case, the control period 602 of task C is DL(C)=100 [ms], and the worst execution time 603 during independent execution is T _wst (C)=10 [ms]. If the worst value α _wst (C) of task C referenced from the execution time variation rate table 820 is, for example, "1.2", the grace period Tg(C) of task C is expressed by the following formula (3).

Tg(C) = 100 - (1.2 x 10) = 88 [ms] ... (3)

Next, the generation unit 830 selects task B on which task C depends. The control cycle 602 of task B is DL(B)=100 [ms], and the worst execution time 603 when task B is executed alone is T _wst (B)=30 [ms]. Task B's successor task is task C. Therefore, i=1. If the worst value α _wst (B) of task B referred to from the execution time fluctuation rate table 820 is, for example, “1.0”, the grace time Tg (B) of task B is calculated by the following formula (4). become that way.

Tg(B)=100-{(1.0×30)+(1.2×10)}=58[ms]
...(4)

Next, the generation unit 830 selects task A on which task B depends. The control cycle 602 of task A is DL(A)=50 [ms], and the worst execution time 603 when task A is executed alone is T _wst (A)=10 [ms]. Task A's successor tasks are tasks B and C. Therefore, i=2. When the worst value α _wst (A) of task A referred to from the execution time fluctuation rate table 820 is, for example, “1.1”, the grace time Tg (A) of task A is calculated by the following formula (5). become that way.

Tg(A)=50-{(1.1×10)+(1.0×30)+(1.2×10)}
=-3[ms]...(5)
Since grace time Tg(A) has become a negative value, Tg(A) is set to 0.

Next, the generation unit 830 selects task D. Since task D has no successor task Z _i (i=0), the generation unit 830 calculates the grace time Tg(D) until the start of execution of task D using the above equation (2) with i=0. . In this case, the control period 602 of task D is DL(D)=100 [ms], and the worst execution time 603 when executed alone is T _wst (D)=20 [ms]. When the worst value α _wst (C) of task D referred to from the execution time fluctuation rate table 820 is, for example, “1.3”, the grace time Tg (D) of task D is calculated by the following formula (6). become that way.

Tg(D)=100-(1.3×20)=74[ms]...(6)

Next, the generation unit 830 selects task A on which task D depends. The control cycle 602 of task A is DL(A)=50 [ms], and the worst execution time 603 when task A is executed alone is T _wst (A)=10 [ms]. Task A's successor task is task D. Therefore, i=1. When the worst value α _wst (A) of task A referred to from the execution time fluctuation rate table 820 is, for example, “1.1”, the grace time Tg (A) of task A is calculated by the following formula (7). become that way.

Tg(A)=50-{(1.1×10)+(1.3×20)}=13[ms]
・・・・・・(7)

However, since the grace period Tg(A) of task A is also calculated by the above equation (5), the generation unit 830 selects the shorter grace period. In this case, grace time Tg(A)=0 for task A in equation (5) above is selected. The generation unit 830 similarly calculates grace times Tg(E) to Tg(H) for tasks E to H. In this way, grace times Tg(A) to Tg(H) for tasks A to H are calculated, and step S1001 ends.

Next, the generation unit 830 allocates the task X to the core with the lowest cumulative core usage rate in order from the task X with the shortest grace time Tg(X) (step S1002). Specifically, for example, the generation unit 830 assigns tasks A to H to cores as shown in FIGS. 1A and 1B.

Next, the generation unit 830 determines the execution order of tasks X based on the grace period Tg(X) for each core (step S1003). Specifically, for example, as shown in FIG. 1B, the generation unit 830 determines the execution order 101 of tasks A to H from the assignment result in FIG. 1A.

Next, the generation unit 830 identifies the memory consumption amount 605 of the tasks X and Y that are executed in parallel from the execution order 101 from the task set 600, and determines the execution time variation rate of the task X when the tasks X and Y are executed in parallel. α _X ^Y is specified from the execution time variation rate table 820 (step S1004).

Next, the generation unit 830 predicts the execution time of task X in core #j based on the worst execution time 603 when task _X is executed alone and the execution time fluctuation rate ^αXY of task X (step S1005). Specifically, for example, the generation unit 830 calculates the parallel execution time eXY of core #j when task Y is executed in parallel by core ^#k as a predicted value by substituting the execution time fluctuation rate _αXY and the independent execution time _eX of the execution time fluctuation rate table 820 into the above formula ( ¹ ) as described above. The parallel execution time _eXY of task X is the time length from the start of execution of task X in the execution order 101. As a _result ^, a schedule 102 as shown in FIG. 1C is generated.

Finally, the generation unit 830 verifies whether the deadlines for all tasks A to H are exceeded (step S1006). Specifically, for example, the generation unit 830 refers to the schedule 102 and determines whether the execution end point of each task X does not exceed the control cycle 602 of that task X. If none of the tasks X exceeds the control period 602, the generation unit 830 finalizes the schedule 102.

The determined schedule 102 is implemented, for example, when the multi-core processor 100 is manufactured. Furthermore, during operation of the multi-core processor 100 in the mobile control device 200, the schedule generation device 700 may transmit the latest schedule 102 to the multi-core processor 100. Thereby, the multi-core processor 100 receives and updates the latest schedule 102, executes the automatic driving application 500 according to the latest schedule 102, and controls the mobile object V1. In this way, it is possible to improve the real-time performance of the processing of tasks A to H in the multi-core processor 100, and to improve the processing efficiency of tasks A to H.

Note that if there is any task X that exceeds the control period 602, the user refers to the execution time variation rate table 820 to search for an execution order 101 of tasks A to H that improves processing performance. , the generation unit 830 regenerates the schedule 102 using the searched execution order 101. Furthermore, within the grace period up to the control cycle 602 obtained from the execution time variation rate table 820, the user can share data with other tasks Y that are executed in parallel on other cores #k and avoid cache conflicts. In consideration, an offset of the execution start time in the execution order 101 may be set.

As described above, according to the first embodiment, by calculating backwardly the grace time Tg (X) from the worst execution time T _wst (X) in parallel execution to the start of execution from the succeeding task Z _n with a slow execution order, Highly accurate deadline verification becomes possible, and it is possible to improve the real-time performance of the schedule 102 and the processing efficiency of tasks A to H.

Note that in FIG. 8, the generation unit 830 and the execution time fluctuation rate table 820 are installed in the schedule generation device 700, but the generation unit 830 and the execution time fluctuation rate table 820 may be installed in the ECU 210. This case will be explained using FIG. 11 as an example.

<Functional configuration example of ECU 210>
FIG. 11 is a block diagram showing an example of the functional configuration of the ECU 210 according to the first embodiment. ECU 210 in FIG. 11 includes a generation unit 830 and an execution time fluctuation rate table 820. For example, when the ECU 210 adds, deletes, or updates a task X through the cloud 201 during operation of the mobile control device 200, the ECU 210 can generate and update the schedule 102.

Specifically, for example, the resource monitoring unit 812 sequentially acquires resource usage information by each task X that is being executed in the automatic driving application 500 and feeds it back to the generation unit 830. The generation unit 830 updates the execution time fluctuation rate α _X ^Y in the execution time fluctuation rate table 820 based on the received resource usage information. Thereby, the generation unit 830 can change the core allocation and execution start time of each task X.

Next, Example 2 will be explained. The second embodiment is an example in which assignment of task X to a core is performed prior to generation of the schedule 102 by the generation unit 830. Note that in the second embodiment, since the explanation will focus on the differences from the first embodiment, the explanation of the common parts with the first embodiment will be omitted.

<Functional configuration example of information processing system 800>
FIG. 12 is a block diagram showing a functional configuration example 1 of an information processing system 800 according to the second embodiment. The difference from FIG. 8 is that in FIG. 12, schedule generation device 700 includes an allocation unit 1200 that allocates task X to a core. Therefore, in the second embodiment, the generation unit 830 does not perform the assignment of task X to the cores as shown in FIG. 1(b). Note that the allocation unit 1200 is specifically realized, for example, by causing the processor 701 to execute a program stored in the storage device 702 shown in FIG. 6.

<Core allocation processing procedure by allocation unit 1200>
FIG. 13 is a flowchart illustrating an example of a core allocation processing procedure by the allocation unit 1200 according to the second embodiment. FIG. 14 is an explanatory diagram showing example 1 of core allocation processing by the allocation unit 1200, and FIG. 15 is an explanatory diagram showing example 2 of core allocation processing by the allocation unit 1200.

The allocation unit 1200 adds tasks A to H in the task set 600 to the ungrouped task set 1400 shown in FIG. 14(a) (step S1301). As shown in FIG. 14(a), the ungrouped task set 1400 includes tasks A to H before grouping.

Next, the allocation unit 1200 determines whether a task set with the dependency relationship 606 exists in the ungrouped task set 1400 (step S1302). If the task set exists, the allocation unit 1200 executes steps S1303 to S1305, and if the task set does not exist, the process moves to step S1306.

In step S1303, the allocation unit 1200 refers to the task set 600, selects one set of tasks connected by the dependency relationship 606, and groups them. For example, as shown in FIG. 14(b), tasks A to D are grouped as a task set (group 1401) that are connected by a dependency relationship 606, and tasks E and F are connected by a dependency relationship 606. They are grouped as a task set (group 1402), and tasks G and H are grouped as a task set connected by a dependency relationship 606 (group 1403).

In step S1304, the allocation unit 1200 calculates the intra-group core usage rate for each of the groups 1401-1403. The in-group core usage rate is the sum of the core usage rates of tasks X in groups 1401 to 1403. As shown in FIG. 14(c), the group 1401 is "0.8", the group 1402 is "0.4", and the group 1403 is "0.6".

Then, for groups where the intra-group core usage rate exceeds 1, the allocation unit 1200 excludes the task X with the minimum core usage rate from the group until the intra-group core usage rate becomes 1 or less. Since the intra-group core usage rates of groups 1401 to 1403 in FIG. 14(c) are all less than or equal to 1, task X is not excluded. After this, in step S1305, all tasks in groups 1401 to 1403 are excluded from the ungrouped task set 1400. Note that the groups 1401 to 1403 excluded in step S1305 are used in step S1306.

After that, the allocation unit 1200 rearranges the groups 1401 to 1403 in descending order of intra-group core usage rate (1401⇒1403⇒1402) as shown in FIG. 15 (step S1306). Then, the allocation unit 1200 allocates the core with the lowest cumulative core usage rate from the group with the highest intra-group core usage rate (step S1307).

For example, as shown in FIG. 15, the cumulative core usage rates of core #0 and core #0 before allocation are both "0". First, the allocation unit 1200 allocates the group 1401 with the highest in-group core usage rate to core #0. As a result, the cumulative core usage rate of core #0 is updated from "0" to "0.8".

Next, the allocation unit 1200 allocates the group 1403 with the second highest intra-group core usage rate to core #1 with the smaller cumulative core usage rate. As a result, the cumulative core usage rate of core #1 is updated from "0" to "0.6". Next, the allocation unit 1200 allocates the group 1402 with the third highest intra-group core usage rate to core #1 with the smaller cumulative core usage rate. As a result, the cumulative core usage rate of core #1 is updated from "0.6" to "1.0".

As a result, tasks A to D in group 1401 are assigned to core #0, tasks E and F in group 1402 are assigned to core #1, and tasks G and H in group 1403 are assigned to core #1. .

<Example of schedule generation processing procedure>
FIG. 16 is a flowchart illustrating an example of a schedule generation processing procedure by the generation unit 830 according to the second embodiment. In FIG. 16, among steps S1001 to S1006 shown in FIG. 10, steps S1001 and S1003 to S1006 are executed.

Specifically, for example, the generation unit 830 calculates the grace time for each task X using the execution time fluctuation rate table 820 shown in FIG. 9, as in the first embodiment (step S1001). As shown in FIGS. 13 to 15, the core allocation has already been performed, so the generation unit 830 uses the allocation result (FIG. 15) by the allocation unit 1200 to perform step S1003 as in the first embodiment. - Execute S1006.

The determined schedule 102 is implemented, for example, when the multi-core processor 100 is manufactured. Furthermore, during operation of the multi-core processor 100 in the mobile control device 200, the schedule generation device 700 may transmit the latest schedule 102 to the multi-core processor 100. Thereby, the multi-core processor 100 receives and updates the latest schedule 102, executes the automatic driving application 500 according to the latest schedule 102, and controls the mobile object V1. In this way, it is possible to improve the real-time performance of the processing of tasks A to H in the multi-core processor 100, and to improve the processing efficiency of tasks A to H.

In this way, according to the second embodiment, a task set that shares data can be assigned to the same core, so it is possible to suppress the occurrence of cache contention among a plurality of cores. In addition, the task set with a higher core usage rate within a group is assigned to the core with the lowest cumulative core usage rate, which alleviates the imbalance in processing load among multiple cores and improves the usage efficiency of each core. Can be done.

In addition, in the second embodiment, the schedule generating device 700 is configured to include the generating unit 830 and the allocating unit 1200, but the generating unit 830 and the allocating unit 1200 may be provided in separate information processing devices. This case will be described with reference to FIG. 17 as an example.

<Functional configuration example of information processing system 800>
FIG. 17 is a block diagram showing a second functional configuration example of an information processing system 800 according to the second embodiment. Information processing system 800 in FIG. 17 is configured by allocation device 1700 and ECU 210. The allocation device 1700 includes a task set 600 and an allocation unit 1200. The generation unit 830 and the execution time variation rate table 820 are provided in the ECU 210, and the generation process by the generation unit 830 is executed by any one of cores #0 to #3 or a core (not shown) in the core group 401. The allocation device 1700 is an information processing device that executes core allocation processing by the allocation unit 1200 shown in FIGS. 13 to 15.

The allocation device 1700 may be provided in the cloud 201. As a result, for example, when the addition, deletion, or update of task The ECU 210 can generate and update the schedule 102 by executing the core allocation process by the allocation unit 1200 shown in FIG.

In FIG. 11, the allocation unit 1200 is implemented in the allocation device 1700, but the allocation unit 1200 may be implemented in the ECU 210. This case will be explained using FIG. 18 as an example.

<Functional configuration example of ECU 210>
FIG. 18 is a block diagram showing an example of the functional configuration of the ECU 210 according to the second embodiment. ECU 210 in FIG. 18 includes an allocation section 1200, a generation section 830, and an execution time fluctuation rate table 820. The generation process by the generation unit 830 and the allocation process by the allocation unit 1200 are executed by any one of cores #0 to #3 or a core (not shown) in the core group 401. In the ECU 210 of FIG. 18, for example, when adding, deleting, or updating a task to be executed by the ECU 210 is performed through the cloud 201 during operation of the mobile control device 200, the ECU 210 assigns the assignments shown in FIGS. 13 to 15. The core allocation process by the allocation unit 1200 is executed, and the schedule 102 is generated and updated using the allocation result (FIG. 15) by the allocation unit 1200.

Specifically, for example, the resource monitoring unit 812 sequentially acquires resource usage information by each task A to H during execution of the automatic driving application 500, and feeds it back to the allocation unit 1200 and the generation unit 830. Based on the received resource usage information, the allocation unit 1200 executes core allocation that improves cache utilization efficiency than the current core allocation, and recommends the allocation result to the generation unit 830. The generation unit 830 receives the received resource usage information and recommended allocation results and updates the execution time fluctuation rate table 820. Thereby, the generation unit 830 can change the core allocation and execution start time of each task.

As described above, according to the second embodiment, the number of surrounding recognized objects changes depending on the driving scene, such as when driving on a highway or in traffic jams, and the memory consumption 605 of a task and the data shared between tasks change. This is effective even when the size changes. For example, it is possible to follow the task grouping results in the allocation unit 1200 and predictions of execution time fluctuations during cache contention, making it possible to perform effective processing that takes into account the actual behavior of the cache memory and to predict execution times with high precision. .

Next, Example 3 will be explained. In the first and second embodiments described above, the grace period was calculated and the task execution time was predicted using the execution time fluctuation rate table 820 shown in FIG. On the other hand, in the third embodiment, in place of the execution time variation rate table 820 shown in FIG. 9 in the first and second embodiments, task 403 and external memory 310) are defined, and the execution time fluctuation rate table 820 is defined by a combination of the defined resource attributes.

This reduces the table size of the execution time variation rate table 820, making it possible to save memory at the storage location and shorten update time. Note that in the third embodiment, since the explanation will focus on the differences from the first embodiment and the second embodiment, the explanation of the common parts with the first embodiment and the second embodiment will be omitted.

FIG. 19 is an explanatory diagram showing the definition of resource attribute L#. The smaller the layer number of the resource attribute L#, the closer the memory resource is to the core (shorter access time and smaller size). In FIG. 19, c _worst is the worst value of memory resource usage when executing task X (for example, memory consumption 605). c _L1 is the cache size of the primary cache 402, and c _L2 is the cache size of the secondary cache 403. c _L2 > c _L1 .

If c _worst ≦c _L1 , task X uses up to the primary cache 402, so the resource attribute of task X becomes L1. If c _L1 ≦c _worst ≦c _L2 , task X uses up to the secondary cache 403, so the resource attribute of task X becomes L2. If c _worst > c _L2 , task X uses up to the external memory 310, so the resource attribute of task X becomes L3.

In the third embodiment, as an example, c _L1 =32KB and c _L2 =2MB. Therefore, referring to the task set 600, tasks D, G, and H belong to resource attribute L1, tasks A and C belong to resource attribute L2, and tasks B, E, and F belong to resource attribute L3.

<Execution time fluctuation rate table>
20 is an explanatory diagram showing an example of an execution time variation rate table according to the third embodiment. In the execution time variation rate table 2000, the execution time variation rate α Lx Ly is defined by the resource attribute of the core #j (j is an integer equal to or greater than 0) that executes task X and the resource attribute of the core #k (k is an integer equal to or greater than 0, k ≠ j) that executes task Y (≠ X) with reference to the resource usage information. The execution time variation rate α _Lx ^Ly is set, for example, by the above formula (8) for each combination of the resource attribute of task ^X in core #j and _the resource attribute of task Y in core #k.

α _Lx ^Ly =e _Lx ^Ly /e _Lx ...(8)

In the third embodiment, e _Lx in the above formula (8) is the execution time (single execution time) when core #j executes task X with resource attribute Lx, and e _Lx ^Ly is the execution time when core #j executes task k is the execution time (parallel execution time) of task X by core #j when tasks X and Y with resource attributes Lx and Ly are executed in parallel. For example, if _the ^resource attribute Lx of task ).

Note that the execution time variation rate table 2000 can be used for a combination of cores with the same performance as the combination of core #j and core #k. A separate execution time variation rate table 2000 is prepared for the combination of cores with the same performance as the combination of core #j and core #k. Further, although the execution time variation rate table 2000 defines the execution time variation rate α _Lx ^Ly for a combination of two cores, the execution time variation rate may be defined for a combination of three or more cores.

<Example of calculating grace time>
An example of calculating the grace period for task X by the generation unit 830 according to the third embodiment will be described. In the third embodiment, in step S1001 shown in FIGS. 10 and 16, the generation unit 830 refers to the execution time fluctuation rate table 2000 and calculates the grace period of task X using the above equation (2).

In the case of the third embodiment, α _wst (X) is ^one of _the values ( For example, the worst value) α _Lx ^W. For example, if ^the _resource attribute _Lx of ^task α _L2 ^L3 is “2.2”. Therefore, the worst value α _L2 ^W is “2.2” of α _L2 ^L3 .

Similarly, α _wst (Z _i ) is the intra-row execution time fluctuation rate α of the resource attribute Lz of the i-th successor task Z _i that follows task X executed on core #j in the execution time fluctuation rate table 2000. It is any value (for example, the worst value) of _Lx ^Ly . However, the number of subsequent tasks i is an integer satisfying 0≦i≦n. If i=0, there is no subsequent task Z _i .

The generation unit 830 refers to the dependency relationships 606 of the task set 600 and sequentially selects the task X to be executed last. For example, the generation unit 830 selects task C. Since task C has no successor task Z _i (i=0), the generation unit 830 calculates the grace time Tg(C) until the start of execution of task C using the above equation (2) with i=0. .

In this case, the control cycle 602 of task C is DL(C)=100 [ms], and the worst execution time 603 when executed alone is T _wst (C)=10 [ms]. Since the resource attribute of task C is L2, "2.2" is read from the execution time variation rate table 2000 as the worst value α _L2 ^W of L2. Therefore, the grace time Tg(C) of task C is expressed by the following equation (9).

Tg(C) = 100 - (2.2 x 10) = 78 [ms] ... (9)

Next, the generation unit 830 selects task B on which task C depends. The control cycle 602 of task B is DL(B)=100 [ms], and the worst execution time 603 when task B is executed alone is T _wst (B)=30 [ms]. Task B's successor task is task C. Therefore, i=1. Since the resource attribute of task B is L3, "1.2" is read from the execution time variation rate table 2000 as the worst value α _L3 ^W of L3. Therefore, the grace time Tg(B) for task B is expressed by the following equation (10).

Tg(B)=100-{(1.2×30)+(2.2×10)}=42[ms]
...(10)

Next, the generation unit 830 selects task A on which task B depends. The control cycle 602 of task A is DL(A)=50 [ms], and the worst execution time 603 when task A is executed alone is T _wst (A)=10 [ms]. Task A's successor tasks are tasks B and C. Therefore, i=2. Since the resource attribute of task A is L2, "2.2" is read from the execution time variation rate table 2000 as the worst value α _L2 ^W of L2. Therefore, the grace period Tg(A) for task A is expressed by the following equation (11).

Tg(A)=50-{(2.2×10)+(1.2×30)+(2.2×10)}
=-30[ms]...(11)
Since grace time Tg(A) has become a negative value, Tg(A) is set to 0.

Next, the generation unit 830 selects task D. Since task D has no successor task Z _i (i=0), the generation unit 830 calculates the grace time Tg(D) until the start of execution of task D using the above equation (2) with i=0. . In this case, the control period 602 of task D is DL(D)=100 [ms], and the worst execution time 603 when executed alone is T _wst (D)=20 [ms]. Since the resource attribute of task D is L1, "1.0" is read from the execution time variation rate table 820 as the worst value α _L1 ^W of L1. Therefore, the grace time Tg(D) of task D is expressed as the following equation (12).

Tg(D)=100-(1.0×20)=80[ms]...(12)

Next, the generation unit 830 selects task A on which task D depends. The control cycle 602 of task A is DL(A)=50 [ms], and the worst execution time 603 when task A is executed alone is T _wst (A)=10 [ms]. Task A's successor task Z is task D. Therefore, i=1. Since the resource attribute of task A is L2, "2.2" is read from the execution time variation rate table 820 as the worst value α _L2 ^W of L2. Therefore, the grace time Tg(A) of task A is expressed as the following equation (13).

Tg(A)=50-{(2.2×10)+(1.0×20)}=8[ms]
...(13)

However, since the grace period Tg(A) of task A is also calculated by the above equation (11), the generation unit 830 selects the shorter grace period. In this case, grace time Tg(A)=0 for task A in equation (11) above is selected. The generation unit 830 similarly calculates grace times Tg(E) to Tg(H) for tasks E to H. In this way, grace times Tg(A) to Tg(H) for tasks A to H are calculated, and step S1001 ends.

FIG. 21 is an explanatory diagram showing an example of the execution order determined in the third embodiment. The execution order 2101 is determined by the grace time of task X before core allocation. The execution order 2102 is determined based on the execution order 2101 after core allocation by the generation unit 830 of the first embodiment or the allocation unit 1200 of the second embodiment.

The execution order 2102 in FIG. 21 is, for example, the execution order determined after the allocation unit 1200 of the second embodiment allocates cores. Therefore, tasks A to D belonging to group 1401 are assigned to core #0, and tasks E to H belonging to groups 1402 and 1403 are assigned to core #1.

FIG. 22 is an explanatory diagram showing an example of a task execution result based on the worst execution time 603 during single execution. The task execution result 2200 is the execution result when the tasks A to H are executed in descending order of grace period until the control cycle 602 based on the worst execution time 603 when executing them alone in the execution order 2102 of FIG. 21. . However, the execution time of task X is an execution time based on the execution time variation rate table 2000 of the third embodiment, taking into consideration the execution time variation rate α _Lx ^Ly due to cache contention. In particular, it can be seen that the execution time of task C increases significantly due to parallel execution with task E.

FIG. 23 is an explanatory diagram showing a schedule 2300 based on the execution time fluctuation rate table 2000 of the third embodiment, taking into consideration the execution time fluctuation rate α _Lx ^Ly due to cache contention. In schedule 2300, task C and task G are executed in parallel compared to task execution result 2200. Since the resource attribute of task G is L1, that is, it is used up to the first level cache 402, even if it is executed in parallel with task C, there will be no conflict with the second level cache 403. Therefore, the execution time of task C is shorter than that of task execution result 2200. Therefore, the execution time of core #0 is reduced from 83 [ms] in the task execution result 2200 to 74 [ms], improving processing efficiency.

Next, Example 4 will be explained. The fourth embodiment is a modification of the execution time fluctuation rate table 2000 shown in the third embodiment. Note that in the fourth embodiment, since the explanation will focus on the differences from the first to third embodiments, the explanation of the common parts with the first to third embodiments will be omitted.

FIG. 24 is an explanatory diagram showing an example of an execution time fluctuation rate table according to the fourth embodiment. The difference from the execution time fluctuation rate table 2000 of the third embodiment is that in the execution time fluctuation rate table 2400, the resource attribute L2 is divided into L2' and L2''.

Specifically, for example, the memory consumption amount 605 of task X when core #j is executed alone and the total memory consumption amount of tasks The resource attribute of task X smaller than the memory size c _L2 (for example, 2 MB) is assumed to be L2'. The memory consumption amount 605 of task X when core #j is executed independently is smaller than the memory size c _L2 of the secondary cache 403, and the total memory consumption amount of tasks X and Y when core #j and #k are executed in parallel. _The resource attribute of task

Compared to the execution time variation rate table 2000 of the third embodiment, the execution time variation rate table 2400 reflects the usage status of the secondary cache 403 during parallel execution of cores #j and #k in more detail. In other words, for the resource attribute L2', the influence of parallel execution due to cache contention is smaller than for the resource attribute L2'', so the execution time variation rate α _Lx ^Ly of the line with the resource attribute L2'' is The execution time variation rate α _Lx ^Ly is specified to be less than or equal to the value. Therefore, the accuracy of predicting execution time based on execution time fluctuations due to cache contention is improved.

Note that, as shown in FIG. 8 of the first embodiment and FIGS. 12 and 17 of the second embodiment, the generation unit 830 and the assignment In a configuration in which the unit 1200 executes the processing, it is possible to sample information that contributes to improving the prediction accuracy of execution time from resource usage information collected both when designing the ECU 210 and when operating the ECU 210. This enables efficient scheduling.

Furthermore, the execution time fluctuation rate table 820 used by the generation unit 830 is a model that inputs the memory usage and execution start time deviation of each task executed simultaneously and outputs the execution time fluctuation rate α of each task. It can be replaced by Such a model can be obtained by machine learning or the like.

Furthermore, the information processing apparatuses according to the first to fourth embodiments described above can also be configured as shown in (1) to (11) below.

(1) A multi-core processor that has a processor 701 that executes a program, a storage device 702 that stores the program, and has a core group 401 and memory resources including a shared memory shared by multiple cores in the core group 401 The information processing device (schedule generation device 700, mobile object control device 200) that generates the schedule 102 in which 100 executes the processing group calculates the worst execution of each task A to H of the task group when executed alone in the core group 401. The processor 701 can access the task set 600 that defines the time 603 and the execution time variation rate table 820 that defines the execution time variation rate when a core executes in parallel with other cores. The first core #j that executes the first task X executes the second core #k that executes the second task Y in parallel with the execution order 101 assigned to each task The ^{identification} step (step S1004) of specifying the execution time variation rate _{α X} ^Y of the first task X by the first core #j in the case of Calculate the execution time for the first core #j to execute the first task X in the execution order 101 based on the independent execution time e _X when the first core #j independently executes the first task X. , a generation step (step S1005) of generating the schedule 102.

Thereby, it is possible to predict the execution time of the first task X in consideration of parallel execution with the second core #k that executes the second task Y, and it is possible to improve real-time performance.

(2) In the information processing apparatus of (1) above, the task set 600 also includes, for each task A to H of the task group, a control period 602 of the task X, a dependency relationship 606 with another task Y, For each task A to H of the task group, the processor 701 determines the task control period 602, the worst execution time 603 when the task is executed alone, and the time when the core executing the task executes other tasks. The grace period until the start of execution of task A calculation step of calculating the time (step S1001), an allocation step of allocating the task group to the core group 401 based on the grace time for each task X calculated in the calculation step (step S1002), and Based on the determination step (step S1003), the processor 701 determines the execution order 101 for each core based on the execution order 101 for each core determined by the determination step (step S1004). With reference to the time variation rate table 820, the execution time variation rate α _X ^Y of the first task X by the first core #j is specified.

Thereby, it is possible to predict the grace period of the first task X in consideration of parallel execution with the second core #k that executes the second task Y, and it is possible to improve real-time performance.

(3) In the information processing apparatus of (1) above, the task set 600 defines the memory consumption amount 605 when the core executes the task for each task A to H of the task group, and ), the processor 701 calculates the memory consumption amount 605 of the first task X when the first core #j executes the first task X, and the memory consumption amount 605 of the first task X when the first core #j executes the second task Based on the memory consumption amount 605 of the task Y, the execution time variation rate α _X ^Y of the first task X by the first core #j is specified.

This makes it possible to more accurately predict the execution time of the first task can be achieved.

(4) In the information processing device of (1) above, the task set 600 includes the memory consumption 605 when the core executes the task and the dependency relationship with other tasks for each task A to H of the task group. 606, the processor 701 specifies the execution time variation ^rate _α Based on the memory consumption amount 605 of Z, the execution time fluctuation rate α _Z ^Y of the subsequent task Z is specified, and for each task A to H of the task group, the control period 602 of task X and the time when task X is executed independently are determined. Based on ^the worst execution time ₆₀₃ ^of , the specified execution time variation rate _α Execute the calculation process to calculate.

As a result, it is possible to more accurately predict the grace period of task X, taking into consideration parallel execution with core #k that executes task Y according to memory consumption, and improve real-time performance.

(5) In the information processing apparatus of (1) above, the task set 600 defines the dependency relationship 606 with other tasks and the core usage rate 604 for each task A to H of the task group, and 701 divides tasks into groups with dependencies 606, calculates for each group an in-group core usage rate which is the sum of core usage rates 604 by tasks in the group, and calculates the intra-group core usage rate based on the in-group core usage rate. , an assignment process (steps S1301 to S1307) that assigns the task group to the core group 401, and a determination process (step S1003) that determines the execution order 101 for each core based on the assignment result of the assignment process, and In the step (step S1004), the processor 701 refers to the execution order 101 for each core determined in the determination step and the execution time variation rate table 820, and determines the execution time variation of the first task X by the first core #j. Identify the rate α _X ^Y.

As a result, prior to task assignment, tasks with dependencies 606 are grouped and the tasks in the group are collectively assigned to cores, which makes it possible to more efficiently suppress the occurrence of cache contention among multiple cores. Can be done. In addition, the task set with a higher core usage rate within a group is assigned to the core with the lowest cumulative core usage rate, which alleviates the imbalance in processing load among multiple cores and improves the usage efficiency of each core. Can be done.

(6) In the information processing apparatus of (5) above, the task set 600 defines a task control period 602 for each of the tasks A to H of the task group, and the processor 701 defines the task control period 602 for each of the tasks A to H of the task group. Regarding H, it depends on the control period 602 of task X, the independent execution time of task X, and core #j when core #j that executes task Based on the execution time variation rate α _X ^Y of task X and the execution time variation rate α _Z ^Y of the subsequent task Z that is executed after task The processor 701 executes the calculation step (step S1001) to calculate, and in the determination step (step S1003), the processor 701 determines whether the core The execution order 101 for each is determined.

This makes it possible to more accurately predict the grace period for task X, taking into account parallel execution with core #k that executes task Y according to memory consumption, thereby improving real-time performance.

(7) Furthermore, in the information processing apparatus of (1) above, the execution time variation rate table 820 is defined for each combination of the performance of a core (clock frequency, etc.) and the performance of other cores. As a result, it is possible to apply an execution time variation rate that matches the performance of the core, and it is possible to improve the real-time nature of the predicted execution time.

(8) In the information processing device of (1) above, the task set 600 defines the memory consumption amount 605 when the core executes the task for each task A to H of the task group, and The rate table 2000 shows the resource attribute Lx of core #j indicating to what extent core #j uses the secondary cache 403 due to task The execution time variation rate α _Lx ^Ly when core #j executes parallel execution with other core #k is defined and specified by the combination of resource attribute Ly of other core #k indicating whether to use the cache 403. In the step, the processor 701 calculates the resource attribute Lx of the first core #j corresponding to the memory consumption amount 605 of the first task X when the first core #j executes the first task X, and the resource attribute Lx of the second core #k. The execution time of the first task X by the first core #j is based on the resource attribute Ly of the second core #k corresponding to the memory consumption amount 605 of the second task Y when Specify the fluctuation rate α _Lx ^Ly .

In this way, by defining the execution time variation rate α _Lx ^Ly based on the resource attribute, it is possible to predict the execution time according to the usage amount of the secondary cache 403.

(9) Furthermore, in the information processing apparatus of (8) above, the execution time fluctuation rate table 2000 includes a resource attribute indicating that the memory consumption is less than or equal to the memory size of the non-shared memory, and a memory consumption and a resource attribute indicating that the memory size is larger than the memory size of non-shared memory.

This makes it possible to predict the execution time of the resource attribute corresponding to the memory size of the secondary cache 403 as an execution time that reflects cache contention rather than the resource attribute corresponding to the memory size of the primary cache 402.

(10) In the information processing apparatus of (8) above, the execution time variation rate table 2400 shows that both the memory consumption amount 605 of the task and the total memory consumption amount of the task and other tasks are The resource attribute L2' indicates that the memory size is smaller than the memory size of the cache 403, and the memory consumption amount 605 of the task is smaller than the memory size of the secondary cache 403, but the total memory consumption is greater than or equal to the memory size of the secondary cache 403. resource attribute L2''.

This allows for improved prediction accuracy of execution time based on execution time fluctuations due to cache contention compared to the execution time fluctuation rate table 2000.

(11) In the information processing device of (1) above, the processor 701 may be any one of the cores in the core group 401 of the multi-core processor 100. This allows the information processing device, as the mobile object control device 200, to execute the processing by the generation unit 830 (steps S1001 to S1006).

(12) It has a processor 701 that executes a program, a storage device 702 that stores the program, and a memory resource that includes a core group 401 and a secondary cache 403 shared by a plurality of cores in the core group 401. The information processing device (assignment device 1700) that allocates a task group to the core group 401 of the multi-core processor 100 calculates the dependency relationship 606 with other tasks and the core usage rate 604 for each task A to H in the task group. The processor 701 can access the defined task set 600, and performs a grouping step (steps S1303 to S1305) in which tasks are grouped into groups with dependency relationships 606, and a grouping step for each group divided by the grouping step. A calculation step (step S1306) of calculating the intra-group core usage rate which is the sum of the core usage rates 604 by the tasks in the group, and a task group to the core group 401 based on the intra-group core usage rate calculated in the calculation step. An assignment step (step S1307) is performed.

As a result, prior to task assignment, tasks with dependencies 606 are grouped and the tasks in the group are collectively assigned to cores, which makes it possible to more efficiently suppress the occurrence of cache contention among multiple cores. Can be done. In addition, the task set with a higher core usage rate within a group is assigned to the core with the lowest cumulative core usage rate, which alleviates the imbalance in processing load among multiple cores and improves the usage efficiency of each core. Can be done.

Note that the present invention is not limited to the embodiments described above, and includes various modifications and equivalent configurations within the scope of the appended claims. For example, the embodiments described above have been described in detail to explain the present invention in an easy-to-understand manner, and the present invention is not necessarily limited to having all the configurations described. Further, a part of the configuration of one embodiment may be replaced with the configuration of another embodiment. Further, the configuration of one embodiment may be added to the configuration of another embodiment. Furthermore, other configurations may be added to, deleted from, or replaced with some of the configurations of each embodiment.

Further, each of the above-described configurations, functions, processing units, processing means, etc. may be realized in part or in whole by hardware, for example, by designing an integrated circuit, and the processor 701 may implement each function. It may be realized by software by interpreting and executing a program to be realized.

Information such as programs, tables, and files that realize each function is stored in storage devices such as memory, hard disks, and SSDs (Solid State Drives), or on IC (Integrated Circuit) cards, SD cards, and DVDs (Digital Versatile Discs). It can be stored on a medium.

Furthermore, the control lines and information lines shown are those considered necessary for explanation, and do not necessarily show all the control lines and information lines necessary for implementation. In reality, almost all configurations can be considered interconnected.

A to H, X Task Y Other task Z Subsequent task Tg Grace time T _Wst Worst execution time V1, V2 Mobile object e _X independent execution time e _X ^Y parallel execution time α _X ^Y execution time fluctuation rate 100 Multi-core processor 101 Execution order 102 Schedule 200 Mobile object control device 201 Cloud 210s ECU group 211 Gateway 212 Communication module 310 External memory 401 Core group 402 Primary cache 403 Secondary cache 500 Autonomous driving application 600 Task set 602 Control period 603 Worst execution time 604 Core usage rate 605 Memory consumption 606 Dependency relationship 700 Schedule generation device 701 Processor 702 Storage device 800 Information processing system 820, 2000, 2400 Execution time fluctuation rate table 830 Generation unit 1200 Allocation unit 1401 to 1403 Group 1700 Allocation Device

Claims (14)

A multi-core processor having a processor that executes a program, a storage device that stores the program, and a memory resource including a core group and a shared memory shared by a plurality of cores in the core group executes a processing group. An information processing device that generates a schedule for
Processing group information and execution time variation rate information can be accessed,
The processing group information defines, for each process in the processing group, an independent execution time on one core in the core group, a control cycle of the process, and a dependency relationship with other processes,
The execution time variation rate information defines an execution time variation rate when the core executes in parallel with other cores,
The processor includes:
For each process in the process group, the control cycle of the process, the independent execution time of the process, and the dependence of the core when the core that executes the process is executed in parallel with another core that executes another process. a calculation step of calculating a grace period until the start of execution of the process based on an execution time variation rate of the process and an execution time variation rate of a subsequent process executed after the process in the dependency relationship;
an allocation step of allocating the processing group to the core group based on the grace time for each processing calculated in the calculation step;
a determining step of determining an execution order for each core based on the allocation result of the allocation step;
A first core that executes a first process executes the second core that executes a second process in parallel with reference to the execution order for each core determined in the determination step and the execution time variation rate information. a specifying step of specifying an execution time variation rate of the first process by the first core in the case;
Based on the execution time variation rate of the first core and the independent execution time when the first core independently executes the first process in the processing group information, the first core executes the first process in the execution order. a generation step of calculating the execution time for executing the first process and generating the schedule;
An information processing device characterized by executing. A multi-core processor having a processor that executes a program, a storage device that stores the program, and a memory resource including a core group and a shared memory shared by a plurality of cores in the core group executes a processing group. An information processing device that generates a schedule for
Processing group information and execution time variation rate information can be accessed,
The processing group information specifies, for each process of the processing group, an independent execution time on one core in the core group and a memory consumption when the core executes the process;
The execution time variation rate information defines an execution time variation rate when the core executes in parallel with other cores,
The processor includes:
The processing group refers to the execution order assigned to each core and the execution time variation rate information, and calculates the memory consumption amount of the first process when the first core executes the first process, and the second process. Based on the memory consumption of the second process when the core executes the second process, the first core that executes the first process is executed in parallel with the second core that executes the second process. a specifying step of specifying an execution time variation rate of the first process by the first core in the case;
a generating step of calculating an execution time for the first core to execute the first process in the execution sequence based on an execution time variation rate of the first core and an independent execution time for the first core to independently execute the first process in the process group information, to generate the schedule;
An information processing device characterized by executing. A multi-core processor having a processor that executes a program, a storage device that stores the program, and a memory resource including a core group and a shared memory shared by a plurality of cores in the core group executes a processing group. An information processing device that generates a schedule for
Processing group information and execution time variation rate information can be accessed,
The processing group information includes, for each process in the processing group, the independent execution time on one core in the core group, the memory consumption when the core executes the process, and the comparison with other processes. Specify the dependencies and,
The execution time variation rate information defines an execution time variation rate when the core executes in parallel with other cores,
The processor includes:
When the processing group refers to the execution order assigned to each core and the execution time variation rate information, and the first core that executes the first process executes in parallel with the second core that executes the second process. identifying an execution time variation rate of the first process by the first core;
a generating step of calculating an execution time for the first core to execute the first process in the execution sequence based on an execution time variation rate of the first core and an independent execution time for the first core to independently execute the first process in the process group information, to generate the schedule;
The execution time fluctuation rate of the third process is specified based on the memory consumption of the third process by the third core, and the execution time variation rate of the third process is determined based on the memory consumption of the fourth process executed after the third process in the dependency relationship. The execution time fluctuation rate of the fourth process is specified, and the control period of the third process, the independent execution time of the third process, and the specified execution time fluctuation rate of the third process are specified. a calculation step of calculating a grace period until the start of execution of the third process based on the execution time fluctuation rate of the fourth process;
2. An information processing device comprising: A multi-core processor having a processor that executes a program, a storage device that stores the program, and a memory resource including a core group and a shared memory shared by a plurality of cores in the core group executes a processing group. An information processing device that generates a schedule for
Processing group information and execution time variation rate information can be accessed,
The processing group information defines, for each process in the processing group, an independent execution time on one core in the core group, a dependency relationship with other processes, and a core usage rate,
The execution time variation rate information defines an execution time variation rate when the core executes in parallel with other cores,
The processor,
The processing group is divided into groups having the dependency relationship, and for each group, an in-group core usage rate, which is the sum of the core usage rates by the processes in the group, is calculated, and based on the in-group core usage rate. an assignment step of assigning the processing group to the core group;
a determining step of determining an execution order for each core based on the allocation result of the allocation step;
A first core that executes a first process executes the second core that executes a second process in parallel with reference to the execution order for each core determined in the determination step and the execution time variation rate information. a specifying step of specifying an execution time variation rate of the first process by the first core in the case;
Based on the execution time variation rate of the first core and the independent execution time when the first core independently executes the first process in the processing group information, the first core executes the first process in the execution order. a generation step of calculating the execution time for executing the first process and generating the schedule;
An information processing device characterized by executing. The information processing device according to claim 4,
The processing group information defines a control cycle of the processing for each processing of the processing group,
The processor includes:
For each process in the process group, the control cycle of the process, the independent execution time of the process, and the dependence of the core when the core that executes the process is executed in parallel with another core that executes another process. a calculation step of calculating a grace period until the start of execution of the process based on an execution time variation rate of the process and an execution time variation rate of a subsequent process to be executed after the process in the dependency relationship; ,
In the determination step, the processor determines the execution order for each of the cores based on a result of the allocation step and the grace time for each of the processes calculated in the calculation step.
23. An information processing apparatus comprising: The information processing device according to claim 1,
The execution time variation rate information is defined for each combination of the performance of the core and the performance of the other core,
An information processing device characterized by: A multi-core processor having a processor that executes a program, a storage device that stores the program, and a memory resource including a core group and a shared memory shared by a plurality of cores in the core group executes a processing group. An information processing device that generates a schedule for
Processing group information and execution time variation rate information can be accessed,
The processing group information defines, for each process in the processing group, an independent execution time on one core in the core group and a memory consumption amount when the core executes the process,
The execution time variation rate information includes a resource attribute of the core indicating to what extent the shared memory is used by the core due to the process, and a resource attribute of the core indicating how much the shared memory is used by the other core due to the other process. A resource attribute of the other core indicating whether to use the resource attribute of the other core, and defining an execution time fluctuation rate when the core executes in parallel with other cores,
The processor includes:
a step of referring to the execution order assigned to each of the cores by the process group and the execution time variation information, and based on a resource attribute of the first core corresponding to the memory consumption of the first process when the first core executes the first process and a resource attribute of the second core corresponding to the memory consumption of the second process when the second core executes the second process, the step of identifying a variation in execution time of the first process by the first core when the first core executes the first process in parallel with the second core executing the second process;
Based on the execution time variation rate of the first core and the independent execution time when the first core independently executes the first process in the processing group information, the first core executes the first process in the execution order. a generation step of calculating the execution time for executing the first process and generating the schedule;
An information processing device characterized by executing. The information processing device according to claim 7,
The execution time fluctuation rate information includes a resource attribute indicating that the memory consumption amount is less than or equal to the memory size of the non-shared memory, and a resource attribute indicating that the memory consumption amount is larger than the memory size of the non-shared memory. a resource attribute indicating;
23. An information processing apparatus comprising: The information processing device according to claim 7,
The execution time variation rate information includes a resource attribute indicating that both the memory consumption of the process and the total memory consumption of the process and the other processes are smaller than the memory size of the shared memory; a resource attribute indicating that the memory consumption of the process is smaller than the memory size of the shared memory, but the total memory consumption is greater than or equal to the memory size of the shared memory;
An information processing device characterized by: 2. The information processing device according to claim 1,
The processor is one of the cores of the core group of the multi-core processor,
An information processing device characterized by: A multi-core processor having a processor that executes a program, a storage device that stores the program, and a memory resource including a core group and a shared memory shared by a plurality of cores in the core group executes a processing group. An information processing method executed by an information processing device that generates a schedule for
Processing group information and execution time variation rate information can be accessed,
The processing group information defines, for each process in the processing group, an independent execution time on one core in the core group, a control cycle of the process, and a dependency relationship with other processes,
The execution time variation rate information defines an execution time variation rate when the core executes in parallel with other cores,
The information processing method includes:
The processor,
For each process in the process group, the control cycle of the process, the independent execution time of the process, and the dependence of the core when the core that executes the process is executed in parallel with another core that executes another process. a calculation step of calculating a grace period until the start of execution of the process based on an execution time variation rate of the process and an execution time variation rate of a subsequent process executed after the process in the dependency relationship;
an allocating step of allocating the processing groups to the core groups based on the grace time for each processing calculated in the calculating step;
a determination step of determining an execution order for each of the cores based on a result of the allocation step;
A first core that executes a first process executes the second core that executes a second process in parallel with reference to the execution order for each core determined in the determination step and the execution time variation rate information. a specifying step of specifying an execution time variation rate of the first process by the first core in the case;
Based on the execution time variation rate of the first core and the independent execution time when the first core independently executes the first process in the processing group information, the first core executes the first process in the execution order. a generation step of calculating the execution time for executing the first process and generating the schedule;
An information processing method characterized by performing the following. A multi-core processor having a processor that executes a program, a storage device that stores the program, and a memory resource including a core group and a shared memory shared by a plurality of cores in the core group executes a processing group. An information processing method executed by an information processing device that generates a schedule for
Processing group information and execution time variation rate information can be accessed,
The processing group information defines, for each process in the processing group, an independent execution time on one core in the core group and a memory consumption amount when the core executes the process,
The execution time variation rate information defines an execution time variation rate when the core executes in parallel with other cores,
The information processing method includes:
The processor,
The processing group refers to the execution order assigned to each core and the execution time variation rate information, and calculates the memory consumption amount of the first process when the first core executes the first process, and the second process. Based on the memory consumption of the second process when the core executes the second process, the first core that executes the first process is executed in parallel with the second core that executes the second process. a specifying step of specifying an execution time variation rate of the first process by the first core in the case of
Based on the execution time variation rate of the first core and the independent execution time when the first core independently executes the first process in the processing group information, the first core executes the first process in the execution order. a generation step of calculating the execution time for executing the first process and generating the schedule;
An information processing method characterized by performing the following. a schedule generation device that generates a schedule for executing a processing group by a multi-core processor having a core group and a memory resource including a shared memory shared by a plurality of cores in the core group; An information processing system capable of communicating with a control device that controls a controlled object,
The schedule generation device includes:
Processing group information and execution time variation rate information can be accessed,
The processing group information defines, for each process in the processing group, an independent execution time on one core in the core group, a control cycle of the process, and a dependency relationship with other processes,
The execution time variation rate information defines an execution time variation rate when the core executes in parallel with other cores,
For each process in the process group, the control cycle of the process, the independent execution time of the process, and the dependence of the core when the core that executes the process is executed in parallel with another core that executes another process. a calculation step of calculating a grace period until the start of execution of the process based on an execution time variation rate of the process and an execution time variation rate of a subsequent process executed after the process in the dependency relationship;
an allocation step of allocating the processing group to the core group based on the grace time for each processing calculated in the calculation step;
a determining step of determining an execution order for each core based on the allocation result of the allocation step;
A first core that executes a first process executes the second core that executes a second process in parallel with reference to the execution order for each core determined in the determination step and the execution time variation rate information. a specifying step of specifying an execution time variation rate of the first process by the first core in the case;
Based on the execution time variation rate of the first core and the independent execution time when the first core independently executes the first process in the processing group information, the first core executes the first process in the execution order. a generation step of calculating the execution time for executing the first process and generating the schedule;
a transmission step of transmitting the schedule generated in the generation step to the control device;
Run
The control device includes:
a receiving step of receiving the schedule transmitted by the transmitting step;
a control step of controlling the control target by the multi-core processor based on the schedule received by the receiving step;
An information processing system characterized by executing. an allocation device that allocates a processing group to the core group of a multi-core processor having a core group and a memory resource including a shared memory shared by a plurality of cores in the core group; An information processing system capable of communicating with a control device that controls the
The allocation device includes:
For each process in the process group, it is possible to access process group information that defines dependencies with other processes and core usage rate;
a grouping step of grouping the processing group into groups having the dependency relationship;
a calculation step of calculating an in-group core usage rate, which is the sum of the core usage rates by the processing in the group, for each group divided by the grouping step;
an allocation step of allocating the processing group to the core group based on the in-group core usage rate calculated by the calculation step;
a transmitting step of transmitting the allocation result of the allocation step to the control device;
The control device includes:
Processing group information that defines the independent execution time on one core in the core group for each process in the processing group, and execution time that defines the execution time fluctuation rate when the core executes in parallel with other cores. Volatility information is accessible to
a receiving step of receiving the allocation result transmitted by the transmitting step;
a determining step of determining an execution order in which the processing group is allocated to each core based on the allocation result received by the receiving step;
When a first core that executes a first process executes parallel execution with a second core that executes a second process with reference to the execution order for each core determined in the determination step and the execution time variation rate information. identifying an execution time variation rate of the first process by the first core;
Based on the execution time variation rate of the first core and the independent execution time when the first core independently executes the first process in the processing group information, the first core executes the first process in the execution order. a generation step of calculating an execution time for executing a first process and generating a schedule for the multi-core processor to execute the process group;
a control step of controlling the control target by the multi-core processor based on the schedule received by the generation step;
An information processing system characterized by executing.

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