JP7439883B2 - Transmission device and transmission method - Google Patents

Description

The present technology relates to a transmitting device and a transmitting method, and particularly relates to a transmitting device and a transmitting method that can ensure good communication quality in data transmission using, for example, an LDPC code.

LDPC (Low Density Parity Check) codes have high error correction ability, and in recent years, for example, DVB (Digital Video Broadcasting)-S.2 in Europe, DVB-T.2, DVB-C.2, It is widely adopted in transmission systems such as digital broadcasting such as ATSC (Advanced Television Systems Committee) 3.0 in the United States (see, for example, Non-Patent Document 1).

Recent research has revealed that LDPC codes, like turbo codes, can achieve performance close to the Shannon limit as the code length increases. In addition, since LDPC codes have the property that the minimum distance is proportional to the code length, their characteristics include good block error probability characteristics, and the so-called error floor phenomenon observed in the decoding characteristics of turbo codes etc. Another advantage is that it hardly occurs.

ATSC Standard:Physical Layer Protocol(A/322), 7 September 2016

In data transmission using an LDPC code, for example, the LDPC code is converted into a symbol for orthogonal modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and the symbol is converted into a symbol for orthogonal modulation signal points. mapped and sent.

Data transmission using LDPC codes as described above is spreading worldwide, and there is a need to ensure good communication (transmission) quality.

The present technology has been developed in view of this situation, and is intended to ensure good communication quality in data transmission using LDPC codes.

A first transmission method/device of the present technology includes an encoding step/unit that performs LDPC encoding based on a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 2/16; A group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of bit groups of 360 bits, and a group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360 bits, and 64 signal points of UC (Uniform Constellation) of 64QAM in units of 6 bits. In the groupwise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the bits of the 69120-bit LDPC code are mapped to any of the bits of the LDPC code. The sequence of groups 0 to 191 is bit grouped.
10, 61, 30, 88, 33, 60, 1, 102, 45, 103, 119, 181, 82, 112, 12, 67, 69, 171, 108, 26, 145, 156, 81, 152, 8, 16, 68, 13, 99, 183, 146, 27, 158, 147, 132, 118, 180, 120, 173, 59, 186, 49, 7, 17, 35, 104, 129, 75, 54, 72, 18, 48, 15, 177, 191, 51, 24, 93, 106, 22, 71, 29, 141, 32, 143, 128, 175, 86, 190, 74, 36, 43, 144, 46, 63, 65, 133, 31, 87, 44, 20, 117, 76, 187, 80, 101, 151, 47, 130, 116, 162, 127, 153, 100, 94, 2, 41, 138, 125, 131, 11, 50, 40, 21, 184, 167, 172, 85, 160, 105, 73, 38, 157, 53, 39, 97, 107, 165, 168, 89, 148, 126, 3, 4, 114, 161, 155, 182, 136, 149, 111, 98, 113, 139, 92, 109, 174, 185, 95, 56, 135, 37, 163, 154, 0, 96, 78, 122, 5, 179, 140, 83, 123, 77, 9, 19, 66, 42, 137, 14, 23, 159, 189, 110, 142, 84, 169, 166, 52, 91, 164, 28, 124, 121, 70, 115, 90, 170, 58, 6, 178, 176, 64, 188, 57, 34, 79, 62, 25, 134, 150, 55
The parity check matrix is formed by interleaving the upper left A matrix of the parity check matrix with M1 rows and K columns, which is expressed by a predetermined value M1 and the information length K=N×r of the LDPC code, and A step-structured B matrix that is adjacent to the right of the A matrix in the column, a Z matrix that is a zero matrix that is adjacent to the right of the B matrix in M1 rows and NK-M1 columns, and NK-M1 rows and K+M1 columns. , a C matrix adjacent below the A matrix and the B matrix, and a D matrix which is a unit matrix adjacent to the right of the C matrix with NK-M1 rows and NK-M1 columns, and the predetermined value M1 is 1800, and the A matrix and C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of 1 element of the A matrix and C matrix every 360 columns. And,
1617 1754 1768 2501 6874 12486 12872 16244 18612 19698 21649 30954 33221 33723 34495 37587 38542 41510 42268 52159 59780
206 610 991 2665 4994 5681 12371 17343 25547 26291 26678 27791 27828 32437 33153 35429 39943 45246 46732 53342 60451
119 682 963 3339 6794 7021 7295 8856 8942 10842 11318 14050 14474 27281 28637 29963 37861 42536 43865 48803 59969
175 201 355 5418 7990 10567 10642 12987 16685 18463 21861 24307 25274 27515 39631 40166 43058 47429 55512 55519 59426
117 839 1043 1960 6896 19146 24022 26586 29342 29906 33129 33647 33883 34113 34550 38720 40247 45651 51156 53053 56614
135 236 257 7505 9412 12642 19752 20201 26010 28967 31146 37156 44685 45667 50066 51283 54365 55475 56501 58763 59121
109 840 1573 5523 19968 23924 24644 27064 29410 31276 31526 32173 38175 43570 43722 46655 46660 48353 54025 57319 59818
522 1236 1573 6563 11625 13846 17570 19547 22579 22584 29338 30497 33124 33152 35407 36364 37726 41426 53800 57130
504 1330 1481 13809 15761 20050 26339 27418 29630 32073 33762 34354 36966 43315 47773 47998 48824 50535 53437 55345
348 1244 1492 9626 9655 15638 22727 22971 28357 28841 31523 37543 41100 42372 48983 50354 51434 54574 55031 58193
742 1223 1459 20477 21731 23163 23587 30829 31144 32186 32235 32593 34130 40829 42217 42294 42753 44058 49940 51993
841 860 1534 5878 7083 7113 9658 10508 12871 12964 14023 21055 22680 23927 32701 35168 40986 42139 50708 55350
657 1018 1690 6454 7645 7698 8657 9615 16462 18030 19850 19857 33265 33552 42208 44424 48965 52762 55439 58299
14 511 1376 2586 6797 9409 9599 10784 13076 18509 27363 27667 30262 34043 37043 38143 40246 53811 58872 59250
315 883 1487 2067 7537 8749 10785 11820 15702 20232 22850 23540 30247 41182 44884 50601 52140 55970 57879 58514
256 1442 1534 2342 9734 10789 15334 15356 20334 20433 22923 23521 29391 30553 35406 35643 35701 37968 39541 58097
260 1238 1557 14167 15271 18046 20588 23444 25820 26660 30619 31625 33258 38554 40401 46471 53589 54904 56455 60016
591 885 1463 3411 14043 17083 17372 23029 23365 24691 25527 26389 28621 29999 40343 40359 40394 45685 46209 54887
1119 1411 1664 7879 17732 27000 28506 32237 32445 34100 34926 36470 42848 43126 44117 48780 49519 49592 51901 56580
147 1333 1560 6045 11526 14867 15647 19496 26626 27600 28044 30446 35920 37523 42907 42974 46452 52480 57061 60152
304 591 680 5557 6948 13550 19689 19697 22417 23237 25813 31836 32736 36321 36493 36671 46756 53311 59230 59248
586 777 1018 2393 2817 4057 8068 10632 12430 13193 16433 17344 24526 24902 27693 39301 39776 42300 45215 52149
684 1425 1732 2436 4279 7375 8493 10023 14908 20703 25656 25757 27251 27316 33211 35741 38872 42908 55079 58753
962 981 1773 2814 3799 6243 8163 12655 21226 31370 32506 35372 36697 47037 49095 55400 57506 58743 59678 60422
6229 6484 8795 8981 13576 28622 35526 36922 37284 42155 43443 44080 44446 46649 50824 52987 59033
2742 5176 10231 10336 16729 17273 18474 25875 28227 34891 39826 42595 48600 52542 53023 53372 57331
3512 4163 4725 8375 8585 19795 22844 28615 28649 29481 41484 41657 53255 54222 54229 57258 57647
3358 5239 9423 10858 15636 17937 20678 22427 31220 37069 38770 42079 47256 52442 55152 56964 59169
2243 10090 12309 15437 19426 23065 24872 36192 36336 36949 41387 49915 50155 54338 54422 56561 57984
This is a transmission method/device.

A first receiving device/method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code whose code length N is 69120 bits and whose encoding rate r is 2/16; A groupwise interleaving unit performs groupwise interleaving that interleaves the code in units of 360-bit bit groups, and the LDPC code is interleaved in units of 6 bits at any of the 64 signal points of UC (Uniform Constellation) of 64QAM. In the group-wise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is , bit group
10, 61, 30, 88, 33, 60, 1, 102, 45, 103, 119, 181, 82, 112, 12, 67, 69, 171, 108, 26, 145, 156, 81, 152, 8, 16, 68, 13, 99, 183, 146, 27, 158, 147, 132, 118, 180, 120, 173, 59, 186, 49, 7, 17, 35, 104, 129, 75, 54, 72, 18, 48, 15, 177, 191, 51, 24, 93, 106, 22, 71, 29, 141, 32, 143, 128, 175, 86, 190, 74, 36, 43, 144, 46, 63, 65, 133, 31, 87, 44, 20, 117, 76, 187, 80, 101, 151, 47, 130, 116, 162, 127, 153, 100, 94, 2, 41, 138, 125, 131, 11, 50, 40, 21, 184, 167, 172, 85, 160, 105, 73, 38, 157, 53, 39, 97, 107, 165, 168, 89, 148, 126, 3, 4, 114, 161, 155, 182, 136, 149, 111, 98, 113, 139, 92, 109, 174, 185, 95, 56, 135, 37, 163, 154, 0, 96, 78, 122, 5, 179, 140, 83, 123, 77, 9, 19, 66, 42, 137, 14, 23, 159, 189, 110, 142, 84, 169, 166, 52, 91, 164, 28, 124, 121, 70, 115, 90, 170, 58, 6, 178, 176, 64, 188, 57, 34, 79, 62, 25, 134, 150, 55
The parity check matrix is formed by interleaving the upper left A matrix of the parity check matrix with M1 rows and K columns, which is expressed by a predetermined value M1 and the information length K=N×r of the LDPC code, and A step-structured B matrix that is adjacent to the right of the A matrix in the column, a Z matrix that is a zero matrix that is adjacent to the right of the B matrix in M1 rows and NK-M1 columns, and NK-M1 rows and K+M1 columns. , a C matrix adjacent below the A matrix and the B matrix, and a D matrix which is a unit matrix adjacent to the right of the C matrix with NK-M1 rows and NK-M1 columns, and the predetermined value M1 is 1800, and the A matrix and C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of 1 element of the A matrix and C matrix every 360 columns. And,
1617 1754 1768 2501 6874 12486 12872 16244 18612 19698 21649 30954 33221 33723 34495 37587 38542 41510 42268 52159 59780
206 610 991 2665 4994 5681 12371 17343 25547 26291 26678 27791 27828 32437 33153 35429 39943 45246 46732 53342 60451
119 682 963 3339 6794 7021 7295 8856 8942 10842 11318 14050 14474 27281 28637 29963 37861 42536 43865 48803 59969
175 201 355 5418 7990 10567 10642 12987 16685 18463 21861 24307 25274 27515 39631 40166 43058 47429 55512 55519 59426
117 839 1043 1960 6896 19146 24022 26586 29342 29906 33129 33647 33883 34113 34550 38720 40247 45651 51156 53053 56614
135 236 257 7505 9412 12642 19752 20201 26010 28967 31146 37156 44685 45667 50066 51283 54365 55475 56501 58763 59121
109 840 1573 5523 19968 23924 24644 27064 29410 31276 31526 32173 38175 43570 43722 46655 46660 48353 54025 57319 59818
522 1236 1573 6563 11625 13846 17570 19547 22579 22584 29338 30497 33124 33152 35407 36364 37726 41426 53800 57130
504 1330 1481 13809 15761 20050 26339 27418 29630 32073 33762 34354 36966 43315 47773 47998 48824 50535 53437 55345
348 1244 1492 9626 9655 15638 22727 22971 28357 28841 31523 37543 41100 42372 48983 50354 51434 54574 55031 58193
742 1223 1459 20477 21731 23163 23587 30829 31144 32186 32235 32593 34130 40829 42217 42294 42753 44058 49940 51993
841 860 1534 5878 7083 7113 9658 10508 12871 12964 14023 21055 22680 23927 32701 35168 40986 42139 50708 55350
657 1018 1690 6454 7645 7698 8657 9615 16462 18030 19850 19857 33265 33552 42208 44424 48965 52762 55439 58299
14 511 1376 2586 6797 9409 9599 10784 13076 18509 27363 27667 30262 34043 37043 38143 40246 53811 58872 59250
315 883 1487 2067 7537 8749 10785 11820 15702 20232 22850 23540 30247 41182 44884 50601 52140 55970 57879 58514
256 1442 1534 2342 9734 10789 15334 15356 20334 20433 22923 23521 29391 30553 35406 35643 35701 37968 39541 58097
260 1238 1557 14167 15271 18046 20588 23444 25820 26660 30619 31625 33258 38554 40401 46471 53589 54904 56455 60016
591 885 1463 3411 14043 17083 17372 23029 23365 24691 25527 26389 28621 29999 40343 40359 40394 45685 46209 54887
1119 1411 1664 7879 17732 27000 28506 32237 32445 34100 34926 36470 42848 43126 44117 48780 49519 49592 51901 56580
147 1333 1560 6045 11526 14867 15647 19496 26626 27600 28044 30446 35920 37523 42907 42974 46452 52480 57061 60152
304 591 680 5557 6948 13550 19689 19697 22417 23237 25813 31836 32736 36321 36493 36671 46756 53311 59230 59248
586 777 1018 2393 2817 4057 8068 10632 12430 13193 16433 17344 24526 24902 27693 39301 39776 42300 45215 52149
684 1425 1732 2436 4279 7375 8493 10023 14908 20703 25656 25757 27251 27316 33211 35741 38872 42908 55079 58753
962 981 1773 2814 3799 6243 8163 12655 21226 31370 32506 35372 36697 47037 49095 55400 57506 58743 59678 60422
6229 6484 8795 8981 13576 28622 35526 36922 37284 42155 43443 44080 44446 46649 50824 52987 59033
2742 5176 10231 10336 16729 17273 18474 25875 28227 34891 39826 42595 48600 52542 53023 53372 57331
3512 4163 4725 8375 8585 19795 22844 28615 28649 29481 41484 41657 53255 54222 54229 57258 57647
3358 5239 9423 10858 15636 17937 20678 22427 31220 37069 38770 42079 47256 52442 55152 56964 59169
2243 10090 12309 15437 19426 23065 24872 36192 36336 36949 41387 49915 50155 54338 54422 56561 57984
The present invention is a receiving device/method including a groupwise deinterleaving unit/step for restoring the LDPC code sequence after groupwise interleaving obtained from data transmitted from a transmitting device to the original sequence.

A second transmission method/device of the present technology includes an encoding step/unit that performs LDPC encoding based on a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 4/16; A group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of bit groups of 360 bits, and a group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360 bits, and 64 signal points of UC (Uniform Constellation) of 64QAM in units of 6 bits. In the groupwise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the bits of the 69120-bit LDPC code are mapped to any of the bits of the LDPC code. The sequence of groups 0 to 191 is bit grouped.
8, 165, 180, 182, 189, 61, 7, 140, 105, 78, 86, 75, 15, 28, 82, 1, 136, 130, 35, 24, 70, 152, 121, 11, 36, 66, 83, 57, 164, 111, 137, 128, 175, 156, 151, 48, 44, 147, 18, 64, 184, 42, 159, 3, 6, 162, 170, 98, 101, 29, 102, 21, 188, 79, 138, 45, 124, 118, 155, 125, 34, 27, 5, 97, 109, 145, 54, 56, 126, 187, 16, 149, 160, 178, 23, 141, 30, 117, 25, 69, 116, 131, 94, 65, 191, 99, 181, 185, 115, 67, 93, 106, 38, 71, 76, 113, 132, 172, 103, 95, 92, 107, 4, 163, 139, 72, 157, 0, 12, 52, 68, 88, 161, 183, 39, 14, 32, 49, 19, 77, 174, 47, 154, 17, 134, 133, 51, 120, 74, 177, 41, 108, 142, 143, 13, 26, 59, 100, 123, 55, 158, 62, 104, 148, 135, 9, 179, 53, 176, 33, 169, 129, 186, 43, 167, 87, 119, 84, 90, 150, 20, 10, 122, 114, 80, 50, 146, 144, 96, 171, 40, 73, 81, 168, 112, 190, 37, 173, 46, 110, 60, 85, 153, 2, 63, 91, 127, 89, 31, 58, 22, 166
The parity check matrix is formed by interleaving the upper left A matrix of the parity check matrix with M1 rows and K columns, which is expressed by a predetermined value M1 and the information length K=N×r of the LDPC code, and A step-structured B matrix that is adjacent to the right of the A matrix in the column, a Z matrix that is a zero matrix that is adjacent to the right of the B matrix in M1 rows and NK-M1 columns, and NK-M1 rows and K+M1 columns. , a C matrix adjacent below the A matrix and the B matrix, and a D matrix which is a unit matrix adjacent to the right of the C matrix with NK-M1 rows and NK-M1 columns, and the predetermined value M1 is 1800, and the A matrix and C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of 1 element of the A matrix and C matrix every 360 columns. And,
561 825 1718 4745 7515 13041 13466 18039 19065 21821 32596 32708 35323 36399 36450 41124 43036 43218 43363 44875 49948
56 102 1779 2427 5381 8768 15336 26473 35717 38748 39066 45002 50720
694 1150 1533 2177 5801 6610 7601 16657 18949 33472 47746 49581 50668
90 1122 1472 2085 2593 4986 8200 9175 15502 44084 46057 48546 50487
521 619 708 6915 8978 14211 17426 23058 23463 27440 29822 33443 42871
449 912 1471 8058 9344 11928 20533 20600 20737 26557 26970 27616 33791
355 700 1528 6478 9588 10790 20992 33122 34283 41295 43439 46249 47763
997 1543 1679 5874 7973 7975 11113 28275 28812 29864 35070 36864 50676
85 326 1392 4186 10855 11005 12913 19263 22984 31733 33787 37567 48173
986 1144 1508 19864 28918 29117 33609 36452 47975 48432 48842 49274 51533
437 1190 1413 3814 6695 17541 22060 25845 28431 37453 38912 44170 49231
327 1171 1204 6952 11880 16469 25058 28956 31523 36770 40189 43422 46481
123 605 619 8118 8455 19550 20529 21762 21950 28485 30946 34755 34765
113 896 971 6400 27059 33383 34537 35827 38796 40582 42594 43098 48525
162 854 1015 2938 10659 12085 13040 32772 33023 35878 49674 51060 51333
100 452 1703 1932 4208 5127 12086 14549 16084 17890 20870 41364 48498
1569 1633 1666 12957 18611 22499 38418 38719 42135 46815 48274 50947 51387
119 691 1190 2457 3865 7468 12512 30782 31811 33508 36586 41789 47426
867 1117 1666 4376 13263 13466 33524 37440 38136 39800 41454 41620 42510
378 900 1754 16303 25369 27103 28360 30958 35316 44165 46682 47016 50004
1321 1549 1570 16276 17284 19431 23482 23920 27386 27517 46253 48617 50118
37 383 1418 15792 22551 28843 36532 36718 38805 39226 45671 47712 51769
150 787 1441 17828 19396 21576 21805 24048 31868 32891 42486 43020 45492
1095 1214 1744 2445 5773 10209 11526 29604 30121 36526 45786 47376 49366
412 448 1281 11164 14501 15538 15773 23305 31960 32721 40744 45731 50269
183 626 837 4491 12237 13705 15177 15973 21266 25374 41232 44147 50529
618 1550 1594 5474 9260 16552 18122 26061 30420 30922 32661 34390 43236
135 496 757 9327 15659 20738 24327 26688 29063 38993 46155 49532 50001
64 126 1714 5561 8921 11300 12688 14454 16857 19585 20528 24107 27252
528 687 1730 9735 11737 16396 19200 33712 34271 38241 42027 44471 45581
69 646 1447 8603 19706 22153 22398 23840 24638 27254 29107 30368 41419
673 845 1285 9100 11064 14804 15425 17357 27248 31223 32410 35444 48018
124 1531 1677 3672 3673 3786 8886 9557 10003 11053 13053 22458 25413
102 1154 1758 5721 6034 14567 17772 28670 33380 34284 35356 47480 48123
48 351 760 2078 9797 22956 26120 34119 39658 41039 45237 47861 49022
254 445 841 6835 18340 19021 20053 22874 32639 36679 42004 45696 49530
16 802 903 6218 16206 22068 23049 28201 30377 33947 44358 44739 49303
153 1542 1629 7992 29900 34931 36927 38651 39981 41085 41327 50185 51484
525 1291 1765 9425 20271 31229 37444 38996 39145 41711 43188 45203 51255
2 244 1648 12321 14991 17426 18456 20126 29915 32581 38880 39516 49013
23 452 705 9414 11862 13764 18179 35458 37892 40471 46041 46494 48746
509 1201 1328 8921 9867 10947 19476 22693 32636 34301 38356 39238 51797
246 249 1390 12438 13266 24060 33628 37130 42923 43298 43709 43721 45413
117 257 748 9419 9461 11350 12790 16724 33147 34168 34683 37884 42699
619 646 740 7468 7604 8152 16296 19120 27614 27748 40170 40289 49366
914 1360 1716 10817 17672 18919 26146 29631 40903 46716 49502 51576 51657
68 702 1552 10431 10925 12856 24516 26440 30834 31179 32277 35019 44108
588 880 1524 6641 9453 9653 13679 14488 20714 25865 42217 42637 48312
6380 12240 12558 12816 21460 24206 26129 28555 41616 51767
8889 16221 21629 23476 33954 40572 43494 44666 44885 49813
16938 17727 17913 18898 21754 32515 35686 36920 39898 43560
9170 11747 14681 22874 24537 24685 26989 28947 33592 34621
2427 10241 29649 30522 37700 37789 41656 44020 49801 51268
This is a transmission method/device.

A second receiving device/method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code whose code length N is 69120 bits and whose encoding rate r is 4/16; A groupwise interleaving unit performs groupwise interleaving that interleaves the code in units of 360-bit bit groups, and the LDPC code is interleaved in units of 6 bits at any of the 64 signal points of UC (Uniform Constellation) of 64QAM. In the group-wise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is , bit group
8, 165, 180, 182, 189, 61, 7, 140, 105, 78, 86, 75, 15, 28, 82, 1, 136, 130, 35, 24, 70, 152, 121, 11, 36, 66, 83, 57, 164, 111, 137, 128, 175, 156, 151, 48, 44, 147, 18, 64, 184, 42, 159, 3, 6, 162, 170, 98, 101, 29, 102, 21, 188, 79, 138, 45, 124, 118, 155, 125, 34, 27, 5, 97, 109, 145, 54, 56, 126, 187, 16, 149, 160, 178, 23, 141, 30, 117, 25, 69, 116, 131, 94, 65, 191, 99, 181, 185, 115, 67, 93, 106, 38, 71, 76, 113, 132, 172, 103, 95, 92, 107, 4, 163, 139, 72, 157, 0, 12, 52, 68, 88, 161, 183, 39, 14, 32, 49, 19, 77, 174, 47, 154, 17, 134, 133, 51, 120, 74, 177, 41, 108, 142, 143, 13, 26, 59, 100, 123, 55, 158, 62, 104, 148, 135, 9, 179, 53, 176, 33, 169, 129, 186, 43, 167, 87, 119, 84, 90, 150, 20, 10, 122, 114, 80, 50, 146, 144, 96, 171, 40, 73, 81, 168, 112, 190, 37, 173, 46, 110, 60, 85, 153, 2, 63, 91, 127, 89, 31, 58, 22, 166
The parity check matrix is formed by interleaving the upper left A matrix of the parity check matrix with M1 rows and K columns, which is expressed by a predetermined value M1 and the information length K=N×r of the LDPC code, and A step-structured B matrix that is adjacent to the right of the A matrix in the column, a Z matrix that is a zero matrix that is adjacent to the right of the B matrix in M1 rows and NK-M1 columns, and NK-M1 rows and K+M1 columns. , a C matrix adjacent below the A matrix and the B matrix, and a D matrix which is a unit matrix adjacent to the right of the C matrix with NK-M1 rows and NK-M1 columns, and the predetermined value M1 is 1800, and the A matrix and C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of 1 element of the A matrix and C matrix every 360 columns. And,
561 825 1718 4745 7515 13041 13466 18039 19065 21821 32596 32708 35323 36399 36450 41124 43036 43218 43363 44875 49948
56 102 1779 2427 5381 8768 15336 26473 35717 38748 39066 45002 50720
694 1150 1533 2177 5801 6610 7601 16657 18949 33472 47746 49581 50668
90 1122 1472 2085 2593 4986 8200 9175 15502 44084 46057 48546 50487
521 619 708 6915 8978 14211 17426 23058 23463 27440 29822 33443 42871
449 912 1471 8058 9344 11928 20533 20600 20737 26557 26970 27616 33791
355 700 1528 6478 9588 10790 20992 33122 34283 41295 43439 46249 47763
997 1543 1679 5874 7973 7975 11113 28275 28812 29864 35070 36864 50676
85 326 1392 4186 10855 11005 12913 19263 22984 31733 33787 37567 48173
986 1144 1508 19864 28918 29117 33609 36452 47975 48432 48842 49274 51533
437 1190 1413 3814 6695 17541 22060 25845 28431 37453 38912 44170 49231
327 1171 1204 6952 11880 16469 25058 28956 31523 36770 40189 43422 46481
123 605 619 8118 8455 19550 20529 21762 21950 28485 30946 34755 34765
113 896 971 6400 27059 33383 34537 35827 38796 40582 42594 43098 48525
162 854 1015 2938 10659 12085 13040 32772 33023 35878 49674 51060 51333
100 452 1703 1932 4208 5127 12086 14549 16084 17890 20870 41364 48498
1569 1633 1666 12957 18611 22499 38418 38719 42135 46815 48274 50947 51387
119 691 1190 2457 3865 7468 12512 30782 31811 33508 36586 41789 47426
867 1117 1666 4376 13263 13466 33524 37440 38136 39800 41454 41620 42510
378 900 1754 16303 25369 27103 28360 30958 35316 44165 46682 47016 50004
1321 1549 1570 16276 17284 19431 23482 23920 27386 27517 46253 48617 50118
37 383 1418 15792 22551 28843 36532 36718 38805 39226 45671 47712 51769
150 787 1441 17828 19396 21576 21805 24048 31868 32891 42486 43020 45492
1095 1214 1744 2445 5773 10209 11526 29604 30121 36526 45786 47376 49366
412 448 1281 11164 14501 15538 15773 23305 31960 32721 40744 45731 50269
183 626 837 4491 12237 13705 15177 15973 21266 25374 41232 44147 50529
618 1550 1594 5474 9260 16552 18122 26061 30420 30922 32661 34390 43236
135 496 757 9327 15659 20738 24327 26688 29063 38993 46155 49532 50001
64 126 1714 5561 8921 11300 12688 14454 16857 19585 20528 24107 27252
528 687 1730 9735 11737 16396 19200 33712 34271 38241 42027 44471 45581
69 646 1447 8603 19706 22153 22398 23840 24638 27254 29107 30368 41419
673 845 1285 9100 11064 14804 15425 17357 27248 31223 32410 35444 48018
124 1531 1677 3672 3673 3786 8886 9557 10003 11053 13053 22458 25413
102 1154 1758 5721 6034 14567 17772 28670 33380 34284 35356 47480 48123
48 351 760 2078 9797 22956 26120 34119 39658 41039 45237 47861 49022
254 445 841 6835 18340 19021 20053 22874 32639 36679 42004 45696 49530
16 802 903 6218 16206 22068 23049 28201 30377 33947 44358 44739 49303
153 1542 1629 7992 29900 34931 36927 38651 39981 41085 41327 50185 51484
525 1291 1765 9425 20271 31229 37444 38996 39145 41711 43188 45203 51255
2 244 1648 12321 14991 17426 18456 20126 29915 32581 38880 39516 49013
23 452 705 9414 11862 13764 18179 35458 37892 40471 46041 46494 48746
509 1201 1328 8921 9867 10947 19476 22693 32636 34301 38356 39238 51797
246 249 1390 12438 13266 24060 33628 37130 42923 43298 43709 43721 45413
117 257 748 9419 9461 11350 12790 16724 33147 34168 34683 37884 42699
619 646 740 7468 7604 8152 16296 19120 27614 27748 40170 40289 49366
914 1360 1716 10817 17672 18919 26146 29631 40903 46716 49502 51576 51657
68 702 1552 10431 10925 12856 24516 26440 30834 31179 32277 35019 44108
588 880 1524 6641 9453 9653 13679 14488 20714 25865 42217 42637 48312
6380 12240 12558 12816 21460 24206 26129 28555 41616 51767
8889 16221 21629 23476 33954 40572 43494 44666 44885 49813
16938 17727 17913 18898 21754 32515 35686 36920 39898 43560
9170 11747 14681 22874 24537 24685 26989 28947 33592 34621
2427 10241 29649 30522 37700 37789 41656 44020 49801 51268
The present invention is a receiving device/method including a groupwise deinterleaving unit/step for restoring the LDPC code arrangement after groupwise interleaving to the original arrangement obtained from data transmitted from a transmitting device.

A third transmission method/device of the present technology includes an encoding step/unit that performs LDPC encoding based on a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 6/16; A group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of bit groups of 360 bits, and a group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360 bits, and 64 signal points of UC (Uniform Constellation) of 64QAM in units of 6 bits. In the groupwise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the bits of the 69120-bit LDPC code are mapped to any of the bits of the LDPC code. The sequence of groups 0 to 191 is bit grouped.
17, 84, 125, 70, 134, 63, 68, 162, 61, 31, 74, 137, 7, 138, 5, 60, 76, 105, 160, 12, 114, 81, 155, 112, 153, 191, 82, 148, 118, 108, 58, 159, 43, 161, 149, 96, 71, 30, 145, 174, 67, 77, 47, 94, 48, 156, 151, 141, 131, 176, 183, 41, 35, 83, 164, 55, 169, 98, 187, 124, 100, 54, 104, 40, 2, 72, 8, 85, 182, 103, 6, 37, 107, 39, 42, 123, 57, 106, 13, 150, 129, 46, 109, 188, 45, 113, 44, 90, 20, 165, 142, 110, 22, 28, 173, 38, 52, 16, 34, 0, 3, 144, 27, 49, 139, 177, 132, 184, 25, 87, 152, 119, 158, 78, 186, 167, 97, 24, 99, 69, 120, 122, 133, 163, 21, 51, 101, 185, 111, 26, 18, 10, 33, 170, 95, 65, 14, 130, 157, 59, 115, 127, 92, 56, 1, 80, 66, 126, 178, 147, 75, 179, 171, 53, 146, 88, 4, 128, 121, 86, 117, 19, 23, 168, 181, 11, 102, 93, 73, 140, 89, 136, 9, 180, 62, 36, 79, 91, 190, 143, 29, 154, 32, 64, 166, 116, 15, 189, 175, 50, 135, 172
The parity check matrix is formed by interleaving the upper left A matrix of the parity check matrix with M1 rows and K columns, which is expressed by a predetermined value M1 and the information length K=N×r of the LDPC code, and A step-structured B matrix that is adjacent to the right of the A matrix in the column, a Z matrix that is a zero matrix that is adjacent to the right of the B matrix in M1 rows and NK-M1 columns, and NK-M1 rows and K+M1 columns. , a C matrix adjacent below the A matrix and the B matrix, and a D matrix which is a unit matrix adjacent to the right of the C matrix with NK-M1 rows and NK-M1 columns, and the predetermined value M1 is 1800, and the A matrix and C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of 1 element of the A matrix and C matrix every 360 columns. And,
608 1394 3635 14404 15203 19848 22161 23175 26651 31945 41227
481 570 11088 11673 11866 17145 17247 17564 21607 25992 31286
1207 1257 1870 8472 8855 10511 15656 17064 22720 28352 30914
1171 1585 6218 7621 10121 11374 13184 22714 27207 27959 38572
244 548 2073 4937 7509 11840 12850 18762 25618 27902 37150
15 1352 7060 7886 8151 10574 14172 15258 24838 30827 35337
1009 1651 13300 13958 26240 29983 32340 40743 41553 42475 42873
638 1405 5544 6797 10001 14934 24766 35758 40719 41787 42342
1467 1481 3202 11324 14048 15217 17608 22544 26736 32073 33405
1274 1343 3576 4166 8712 10756 21175 26866 37021 40341 42064
1232 1590 4409 8705 13307 28481 30893 36031 36780 37697 39149
189 1678 9943 10774 11765 25520 26133 27351 27353 40664 41534
125 1421 5009 9365 12792 15933 16231 25975 27076 27997 32429
1361 1764 5376 11071 14456 16324 20318 26168 28445 30392 34235
1017 1303 3312 6738 7813 18149 25506 29032 36789 38742 43116
463 967 10876 13874 14303 16789 21656 26555 38738 39195 40668
630 1104 3029 3165 5157 12880 14175 16498 35121 38917 40944
716 1054 10011 11739 16913 19396 20892 23370 24392 27614 38467
1081 1238 2872 10259 13618 16943 17363 23570 29721 32411 38969
775 1002 2978 9202 16618 22697 30716 31750 36517 37294 40454
25 497 10687 13308 15302 17525 17539 21865 22279 24516 26992
781 878 6426 8551 12328 21375 27626 28192 29731 35423 35606
729 1734 3479 6850 14347 14776 21998 33617 34690 38597 38704
122 1378 1660 7448 7659 11900 13039 13796 19908
504 716 1551 5655 6245 8365 9825 16627 29100
88 900 1057 2620 16729 17278 17444 26106 26587
30 1697 1736 8718 11664 20885 27043 42569 42913
293 634 1188 4005 5266 6205 26756 30207 37757
254 755 1187 4631 13433 25055 28354 28583 30446
316 1381 1522 3131 4340 27284 28246 28282 43174
84 293 645 2148 7925 13104 25010 36836 39033
982 1486 1660 4287 5335 18350 26913 30774 31280
418 1028 1039 3334 4577 6553 7011 17259 31922
1324 1361 1690 5991 7740 16880 18479 25713 31823
735 1322 1727 8629 14655 15815 16762 23263 36859
19 928 1561 11161 12894 14226 21331 41128 41883
327 940 1004 13616 15894 31400 34106 34443 37957
576 953 1226 2122 4900 5002 10248 25476 30787
249 632 1240 5432 23019 29225 31719 36658 41360
980 1154 1783 4351 10245 23347 27442 28328 38555
581 863 1552 5057 7572 14544 20482 29482 31672
4 502 1450 4883 5176 6824 10430 32680 39581
81 761 1558 2269 5391 13213 24184 25523 39429
1085 1163 1244 7694 9125 17387 22223 26343 37933
204 1127 1483 18302 19939 20576 31599 32619 42911
345 387 591 8727 18080 20628 32251 34562 42821
957 1126 1133 4099 12272 15595 20906 23606 34564
409 1310 1335 2761 11952 26853 27941 29262 31647
329 818 1527 3890 5238 8742 15586 28739 43015
231 1158 1677 4314 15937 17526 18391 22963 39232
34 275 526 2975 4742 16109 17346 29145 37673
497 735 1261 7468 8769 17342 19763 32646 33497
879 1233 1633 11612 22941 23723 31969 35571 39510
886 954 1355 5532 8283 26965 29267 30820 40402
356 1199 1452 8833 14845 21722 23840 26539 27970
553 1570 1732 8249 16820 23181 23234 30754 40399
457 1304 1698 2774 11357 32906 34484 38700 41799
456 579 1155 23844 27261 29172 30980 35000 40984
301 1290 1782 6798 9735 23655 31040 35554 36366
228 483 561 12346 16698 32688 34518 38648 41677
35 184 997 4915 7077 9878 16772 26263 27270
181 193 1255 7548 17103 34511 36590 38107 42065
697 1024 1541 2164 15638 20061 32499 32667 32732
654 968 1632 3215 4901 6286 12414 13963 29636
89 150 450 5771 10863 29809 36886 37914 42983
517 1046 1153 5458 18093 25579 31084 37779 42050
345 914 1372 4548 6720 13678 13755 15422 41938
301 518 1107 3603 6076 9265 19580 41645 42621
155 1013 1441 10166 10545 22042 30084 33026 34505
899 1308 1766 22228 24520 24589 30833 32126 37147
177 230 349 6309 9642 25713 30455 34964 40524
802 1364 1703 3573 17317 20364 22849 24265 24925
3952 10609 11011 16296 31430 39995 40207 41606 42424
16548 19896 22579 23043 23126 24141 34331 34959 37990
12197 15244 22990 23110 25507 30011 37681 38902 39432
2292 11871 15562 22304 33059 35126 39158 41206 41866
3497 7847 11510 16212 19408 26780 27967 33953 34451
This is a transmission method/device.

A third receiving device/method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code whose code length N is 69120 bits and whose encoding rate r is 6/16; A groupwise interleaving unit performs groupwise interleaving that interleaves the code in units of 360-bit bit groups, and the LDPC code is interleaved in units of 6 bits at any of the 64 signal points of UC (Uniform Constellation) of 64QAM. In the group-wise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is , bit group
17, 84, 125, 70, 134, 63, 68, 162, 61, 31, 74, 137, 7, 138, 5, 60, 76, 105, 160, 12, 114, 81, 155, 112, 153, 191, 82, 148, 118, 108, 58, 159, 43, 161, 149, 96, 71, 30, 145, 174, 67, 77, 47, 94, 48, 156, 151, 141, 131, 176, 183, 41, 35, 83, 164, 55, 169, 98, 187, 124, 100, 54, 104, 40, 2, 72, 8, 85, 182, 103, 6, 37, 107, 39, 42, 123, 57, 106, 13, 150, 129, 46, 109, 188, 45, 113, 44, 90, 20, 165, 142, 110, 22, 28, 173, 38, 52, 16, 34, 0, 3, 144, 27, 49, 139, 177, 132, 184, 25, 87, 152, 119, 158, 78, 186, 167, 97, 24, 99, 69, 120, 122, 133, 163, 21, 51, 101, 185, 111, 26, 18, 10, 33, 170, 95, 65, 14, 130, 157, 59, 115, 127, 92, 56, 1, 80, 66, 126, 178, 147, 75, 179, 171, 53, 146, 88, 4, 128, 121, 86, 117, 19, 23, 168, 181, 11, 102, 93, 73, 140, 89, 136, 9, 180, 62, 36, 79, 91, 190, 143, 29, 154, 32, 64, 166, 116, 15, 189, 175, 50, 135, 172
The parity check matrix is formed by interleaving the upper left A matrix of the parity check matrix with M1 rows and K columns, which is expressed by a predetermined value M1 and the information length K=N×r of the LDPC code, and A step-structured B matrix that is adjacent to the right of the A matrix in the column, a Z matrix that is a zero matrix that is adjacent to the right of the B matrix in M1 rows and NK-M1 columns, and NK-M1 rows and K+M1 columns. , a C matrix adjacent below the A matrix and the B matrix, and a D matrix which is a unit matrix adjacent to the right of the C matrix with NK-M1 rows and NK-M1 columns, and the predetermined value M1 is 1800, and the A matrix and C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of 1 element of the A matrix and C matrix every 360 columns. And,
608 1394 3635 14404 15203 19848 22161 23175 26651 31945 41227
481 570 11088 11673 11866 17145 17247 17564 21607 25992 31286
1207 1257 1870 8472 8855 10511 15656 17064 22720 28352 30914
1171 1585 6218 7621 10121 11374 13184 22714 27207 27959 38572
244 548 2073 4937 7509 11840 12850 18762 25618 27902 37150
15 1352 7060 7886 8151 10574 14172 15258 24838 30827 35337
1009 1651 13300 13958 26240 29983 32340 40743 41553 42475 42873
638 1405 5544 6797 10001 14934 24766 35758 40719 41787 42342
1467 1481 3202 11324 14048 15217 17608 22544 26736 32073 33405
1274 1343 3576 4166 8712 10756 21175 26866 37021 40341 42064
1232 1590 4409 8705 13307 28481 30893 36031 36780 37697 39149
189 1678 9943 10774 11765 25520 26133 27351 27353 40664 41534
125 1421 5009 9365 12792 15933 16231 25975 27076 27997 32429
1361 1764 5376 11071 14456 16324 20318 26168 28445 30392 34235
1017 1303 3312 6738 7813 18149 25506 29032 36789 38742 43116
463 967 10876 13874 14303 16789 21656 26555 38738 39195 40668
630 1104 3029 3165 5157 12880 14175 16498 35121 38917 40944
716 1054 10011 11739 16913 19396 20892 23370 24392 27614 38467
1081 1238 2872 10259 13618 16943 17363 23570 29721 32411 38969
775 1002 2978 9202 16618 22697 30716 31750 36517 37294 40454
25 497 10687 13308 15302 17525 17539 21865 22279 24516 26992
781 878 6426 8551 12328 21375 27626 28192 29731 35423 35606
729 1734 3479 6850 14347 14776 21998 33617 34690 38597 38704
122 1378 1660 7448 7659 11900 13039 13796 19908
504 716 1551 5655 6245 8365 9825 16627 29100
88 900 1057 2620 16729 17278 17444 26106 26587
30 1697 1736 8718 11664 20885 27043 42569 42913
293 634 1188 4005 5266 6205 26756 30207 37757
254 755 1187 4631 13433 25055 28354 28583 30446
316 1381 1522 3131 4340 27284 28246 28282 43174
84 293 645 2148 7925 13104 25010 36836 39033
982 1486 1660 4287 5335 18350 26913 30774 31280
418 1028 1039 3334 4577 6553 7011 17259 31922
1324 1361 1690 5991 7740 16880 18479 25713 31823
735 1322 1727 8629 14655 15815 16762 23263 36859
19 928 1561 11161 12894 14226 21331 41128 41883
327 940 1004 13616 15894 31400 34106 34443 37957
576 953 1226 2122 4900 5002 10248 25476 30787
249 632 1240 5432 23019 29225 31719 36658 41360
980 1154 1783 4351 10245 23347 27442 28328 38555
581 863 1552 5057 7572 14544 20482 29482 31672
4 502 1450 4883 5176 6824 10430 32680 39581
81 761 1558 2269 5391 13213 24184 25523 39429
1085 1163 1244 7694 9125 17387 22223 26343 37933
204 1127 1483 18302 19939 20576 31599 32619 42911
345 387 591 8727 18080 20628 32251 34562 42821
957 1126 1133 4099 12272 15595 20906 23606 34564
409 1310 1335 2761 11952 26853 27941 29262 31647
329 818 1527 3890 5238 8742 15586 28739 43015
231 1158 1677 4314 15937 17526 18391 22963 39232
34 275 526 2975 4742 16109 17346 29145 37673
497 735 1261 7468 8769 17342 19763 32646 33497
879 1233 1633 11612 22941 23723 31969 35571 39510
886 954 1355 5532 8283 26965 29267 30820 40402
356 1199 1452 8833 14845 21722 23840 26539 27970
553 1570 1732 8249 16820 23181 23234 30754 40399
457 1304 1698 2774 11357 32906 34484 38700 41799
456 579 1155 23844 27261 29172 30980 35000 40984
301 1290 1782 6798 9735 23655 31040 35554 36366
228 483 561 12346 16698 32688 34518 38648 41677
35 184 997 4915 7077 9878 16772 26263 27270
181 193 1255 7548 17103 34511 36590 38107 42065
697 1024 1541 2164 15638 20061 32499 32667 32732
654 968 1632 3215 4901 6286 12414 13963 29636
89 150 450 5771 10863 29809 36886 37914 42983
517 1046 1153 5458 18093 25579 31084 37779 42050
345 914 1372 4548 6720 13678 13755 15422 41938
301 518 1107 3603 6076 9265 19580 41645 42621
155 1013 1441 10166 10545 22042 30084 33026 34505
899 1308 1766 22228 24520 24589 30833 32126 37147
177 230 349 6309 9642 25713 30455 34964 40524
802 1364 1703 3573 17317 20364 22849 24265 24925
3952 10609 11011 16296 31430 39995 40207 41606 42424
16548 19896 22579 23043 23126 24141 34331 34959 37990
12197 15244 22990 23110 25507 30011 37681 38902 39432
2292 11871 15562 22304 33059 35126 39158 41206 41866
3497 7847 11510 16212 19408 26780 27967 33953 34451
The present invention is a receiving device/method including a groupwise deinterleaving unit/step for restoring the LDPC code arrangement after groupwise interleaving to the original arrangement obtained from data transmitted from a transmitting device.

A fourth transmission method/device of the present technology includes an encoding step/unit that performs LDPC encoding based on a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 8/16; A group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of bit groups of 360 bits, and a group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360 bits, and 64 signal points of UC (Uniform Constellation) of 64QAM in units of 6 bits. In the groupwise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the bits of the 69120-bit LDPC code are mapped to any of the bits of the LDPC code. The sequence of groups 0 to 191 is bit grouped.
157, 20, 116, 115, 49, 178, 148, 152, 174, 130, 171, 81, 60, 146, 182, 72, 46, 22, 93, 101, 9, 55, 40, 163, 118, 30, 52, 181, 151, 31, 87, 117, 120, 82, 95, 190, 23, 36, 67, 62, 14, 167, 80, 27, 24, 43, 94, 0, 63, 5, 74, 78, 158, 88, 84, 109, 147, 112, 124, 110, 21, 47, 45, 68, 184, 70, 1, 66, 149, 105, 140, 170, 56, 98, 135, 61, 79, 123, 166, 185, 41, 108, 122, 92, 16, 26, 37, 177, 173, 113, 136, 89, 162, 85, 54, 39, 73, 58, 131, 134, 188, 127, 3, 164, 13, 132, 129, 179, 25, 18, 57, 32, 119, 111, 53, 155, 28, 107, 133, 144, 19, 160, 71, 186, 153, 103, 2, 12, 91, 106, 64, 175, 75, 189, 128, 142, 187, 76, 180, 34, 59, 169, 90, 11, 172, 97, 141, 38, 191, 17, 114, 126, 145, 83, 143, 125, 121, 10, 44, 137, 86, 29, 104, 154, 168, 65, 159, 15, 99, 35, 50, 48, 138, 96, 100, 102, 7, 42, 156, 8, 4, 69, 183, 51, 165, 6, 150, 77, 161, 33, 176, 139
The LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is , and the parity check matrix initial value table is a table representing the position of one element of the information matrix section for every 360 columns,
1850 4176 4190 7294 8168 8405 9258 9710 13440 16304 16600 18184 18834 19899 22513 25068 26659 27137 27232 29186 29667 30549 31428 33634
2477 2543 5094 8081 9573 10269 11276 11439 13016 13327 16717 18042 19362 19721 20089 20425 20503 21396 24677 24722 28703 32 486 32759 33630
1930 2158 2315 2683 3818 4883 5252 5505 8760 9580 11867 13117 14566 15639 17273 18820 21069 24945 25667 26785 30678 31271 3 3003 33244
1279 1491 2038 2347 2432 4336 4905 6588 7507 7666 8775 9172 10405 12249 12270 12373 12936 13046 13364 15130 17597 22855 275 48 32895
620 1897 3775 5552 6799 7621 10167 10172 10615 11367 12093 13241 15426 16623 19467 19792 22069 22370 24472 24594 25205 2595 4 27800 29422
582 1618 4673 5809 6318 6883 8051 12335 12409 13176 14078 15206 17580 18624 18876 19079 20786 21177 25894 26395 27377 27757 30167 31971
1157 2189 4160 4480 5055 8961 9171 9444 10533 11581 12904 14256 14620 15773 16232 17598 19756 21134 21443 22559 23258 25137 25555 28150
987 1258 1269 2394 4859 5642 5705 6093 6408 7734 8804 10657 11946 16132 20267 25402 26505 26548 27060 29767 29780 31915 319 66 33590
1010 1363 1626 5283 6356 10961 12418 14332 14362 16288 16303 16592 17096 20115 20285 20478 21774 22165 22425 23198 25048 25 596 31540 32841
895 2743 2912 4971 8803 11183 14500 14617 14638 16776 17901 18622 20244 20845 22214 25676 26161 26281 29978 30392 30922 315 42 32038 32443
188 260 411 2823 5512 5645 10019 11856 12671 14273 14673 16091 16169 22333 22934 22945 23542 26503 27159 27279 28277 30114 31626 32722
357 516 3530 4317 8587 9491 10348 11330 13446 14533 15423 17003 17217 19127 20088 20750 21767 22386 24021 27749 29008 29376 30329 32940
2909 3036 4875 9967 10632 12069 12410 14004 14628 15605 15852 18231 18657 19705 20620 22241 29575 29656 31246 32190 32781 3 3489 33842 34492
4242 5461 5577 7662 11130 13663 17240 17773 18339 19400 22905 24219 25464 25890 26359 27121 27318 27840 30800 32587 32924 3 3427 33940 34058
421 2222 3457 5257 5600 10147 12754 17380 18854 20333 20345 20752 24578 25196 25638 25725 25822 27610 28006 28563 29632 299 73 29991 34166
41 207 1043 4650 5387 6826 7261 8687 9092 10775 11446 12596 16613 19463 20923 24155 24927 25384 26064 27377 28094 32578 326 39 34115
1050 5731 15820 16281 26130 29314
5980 6161 14479 22181 22537 32924
7828 9134 11297 17143 25449 29674
8299 10457 14486 21548 22510 32039
1527 7792 10424 19166 29302 29768
5823 13974 21254 21506 25658 29491
6285 9873 12846 14474 17005 29377
1740 4929 8285 20994 32271 34522
12862 16827 22427 23369 27051 30378
4787 10372 10408 12091 20349 26162
6659 22752 24697 28261 28917 32536
6788 15367 21778 28916 30324 33927
7181 12373 21912 24703 28680 34045
2238 4945 14336 19270 29574 33459
10283 15311 17440 24599 24867 28293
324 5264 5375 6581 24348 30288
3112 7656 23825
21624 22318 22633
5284 19790 22758
2700 4039 12576
17028 17520 19579
11914 17834 33989
2199 5502 7184
22 20701 26497
5551 27014 32876
4019 26547 28521
7580 10016 33855
4328 11674 34018
8491 9956 10029
6167 11267 24914
5317 9049 29657
20717 28724 33012
16841 21647 31096
11931 16278 20287
9402 10557 11008
11826 15349 34420
14369 17031 20597
19164 27947 29775
15537 18796 33662
5404 21027 26757
6269 12671 24309
8601 29048 29262
10099 20323 21457
15952 17074 30434
7597 20987 33095
11298 24182 29217
12055 16250 16971
5350 9354 31390
8168 14168 18570
5448 13141 32381
3921 21113 28176
8756 19895 27917
9391 16617 25586
3357 18527 34238
2378 16840 28948
7470 27466 32928
8366 19376 30916
3116 7267 18016
15309 18445 21799
4731 23773 34546
260 4898 5180
8897 22266 29587
2539 23717 33142
19233 28750 29724
9937 15384 16599
10234 17089 26776
8869 9425 13658
6197 24086 31929
9237 20931 27785
10403 13822 16734
20038 21196 26868
13170 27813 28875
1110 20329 24508
11844 22662 28987
2891 2918 14512
15707 27399 34135
8687 20019 26178
6847 8903 16307
23737 23775 27776
17388 27970 31983
This is a transmission method/device.

A fourth receiving device/method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code whose code length N is 69120 bits and whose encoding rate r is 8/16; A groupwise interleaving unit performs groupwise interleaving that interleaves the code in units of 360-bit bit groups, and the LDPC code is interleaved in units of 6 bits at any of the 64 signal points of UC (Uniform Constellation) of 64QAM. In the group-wise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is , bit group
157, 20, 116, 115, 49, 178, 148, 152, 174, 130, 171, 81, 60, 146, 182, 72, 46, 22, 93, 101, 9, 55, 40, 163, 118, 30, 52, 181, 151, 31, 87, 117, 120, 82, 95, 190, 23, 36, 67, 62, 14, 167, 80, 27, 24, 43, 94, 0, 63, 5, 74, 78, 158, 88, 84, 109, 147, 112, 124, 110, 21, 47, 45, 68, 184, 70, 1, 66, 149, 105, 140, 170, 56, 98, 135, 61, 79, 123, 166, 185, 41, 108, 122, 92, 16, 26, 37, 177, 173, 113, 136, 89, 162, 85, 54, 39, 73, 58, 131, 134, 188, 127, 3, 164, 13, 132, 129, 179, 25, 18, 57, 32, 119, 111, 53, 155, 28, 107, 133, 144, 19, 160, 71, 186, 153, 103, 2, 12, 91, 106, 64, 175, 75, 189, 128, 142, 187, 76, 180, 34, 59, 169, 90, 11, 172, 97, 141, 38, 191, 17, 114, 126, 145, 83, 143, 125, 121, 10, 44, 137, 86, 29, 104, 154, 168, 65, 159, 15, 99, 35, 50, 48, 138, 96, 100, 102, 7, 42, 156, 8, 4, 69, 183, 51, 165, 6, 150, 77, 161, 33, 176, 139
The LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is , and the parity check matrix initial value table is a table representing the position of one element of the information matrix section for every 360 columns,
1850 4176 4190 7294 8168 8405 9258 9710 13440 16304 16600 18184 18834 19899 22513 25068 26659 27137 27232 29186 29667 30549 31428 33634
2477 2543 5094 8081 9573 10269 11276 11439 13016 13327 16717 18042 19362 19721 20089 20425 20503 21396 24677 24722 28703 32 486 32759 33630
1930 2158 2315 2683 3818 4883 5252 5505 8760 9580 11867 13117 14566 15639 17273 18820 21069 24945 25667 26785 30678 31271 3 3003 33244
1279 1491 2038 2347 2432 4336 4905 6588 7507 7666 8775 9172 10405 12249 12270 12373 12936 13046 13364 15130 17597 22855 275 48 32895
620 1897 3775 5552 6799 7621 10167 10172 10615 11367 12093 13241 15426 16623 19467 19792 22069 22370 24472 24594 25205 2595 4 27800 29422
582 1618 4673 5809 6318 6883 8051 12335 12409 13176 14078 15206 17580 18624 18876 19079 20786 21177 25894 26395 27377 27757 30167 31971
1157 2189 4160 4480 5055 8961 9171 9444 10533 11581 12904 14256 14620 15773 16232 17598 19756 21134 21443 22559 23258 25137 25555 28150
987 1258 1269 2394 4859 5642 5705 6093 6408 7734 8804 10657 11946 16132 20267 25402 26505 26548 27060 29767 29780 31915 319 66 33590
1010 1363 1626 5283 6356 10961 12418 14332 14362 16288 16303 16592 17096 20115 20285 20478 21774 22165 22425 23198 25048 25 596 31540 32841
895 2743 2912 4971 8803 11183 14500 14617 14638 16776 17901 18622 20244 20845 22214 25676 26161 26281 29978 30392 30922 315 42 32038 32443
188 260 411 2823 5512 5645 10019 11856 12671 14273 14673 16091 16169 22333 22934 22945 23542 26503 27159 27279 28277 30114 31626 32722
357 516 3530 4317 8587 9491 10348 11330 13446 14533 15423 17003 17217 19127 20088 20750 21767 22386 24021 27749 29008 29376 30329 32940
2909 3036 4875 9967 10632 12069 12410 14004 14628 15605 15852 18231 18657 19705 20620 22241 29575 29656 31246 32190 32781 3 3489 33842 34492
4242 5461 5577 7662 11130 13663 17240 17773 18339 19400 22905 24219 25464 25890 26359 27121 27318 27840 30800 32587 32924 3 3427 33940 34058
421 2222 3457 5257 5600 10147 12754 17380 18854 20333 20345 20752 24578 25196 25638 25725 25822 27610 28006 28563 29632 299 73 29991 34166
41 207 1043 4650 5387 6826 7261 8687 9092 10775 11446 12596 16613 19463 20923 24155 24927 25384 26064 27377 28094 32578 326 39 34115
1050 5731 15820 16281 26130 29314
5980 6161 14479 22181 22537 32924
7828 9134 11297 17143 25449 29674
8299 10457 14486 21548 22510 32039
1527 7792 10424 19166 29302 29768
5823 13974 21254 21506 25658 29491
6285 9873 12846 14474 17005 29377
1740 4929 8285 20994 32271 34522
12862 16827 22427 23369 27051 30378
4787 10372 10408 12091 20349 26162
6659 22752 24697 28261 28917 32536
6788 15367 21778 28916 30324 33927
7181 12373 21912 24703 28680 34045
2238 4945 14336 19270 29574 33459
10283 15311 17440 24599 24867 28293
324 5264 5375 6581 24348 30288
3112 7656 23825
21624 22318 22633
5284 19790 22758
2700 4039 12576
17028 17520 19579
11914 17834 33989
2199 5502 7184
22 20701 26497
5551 27014 32876
4019 26547 28521
7580 10016 33855
4328 11674 34018
8491 9956 10029
6167 11267 24914
5317 9049 29657
20717 28724 33012
16841 21647 31096
11931 16278 20287
9402 10557 11008
11826 15349 34420
14369 17031 20597
19164 27947 29775
15537 18796 33662
5404 21027 26757
6269 12671 24309
8601 29048 29262
10099 20323 21457
15952 17074 30434
7597 20987 33095
11298 24182 29217
12055 16250 16971
5350 9354 31390
8168 14168 18570
5448 13141 32381
3921 21113 28176
8756 19895 27917
9391 16617 25586
3357 18527 34238
2378 16840 28948
7470 27466 32928
8366 19376 30916
3116 7267 18016
15309 18445 21799
4731 23773 34546
260 4898 5180
8897 22266 29587
2539 23717 33142
19233 28750 29724
9937 15384 16599
10234 17089 26776
8869 9425 13658
6197 24086 31929
9237 20931 27785
10403 13822 16734
20038 21196 26868
13170 27813 28875
1110 20329 24508
11844 22662 28987
2891 2918 14512
15707 27399 34135
8687 20019 26178
6847 8903 16307
23737 23775 27776
17388 27970 31983
The present invention is a receiving device/method including a groupwise deinterleaving unit/step for restoring the LDPC code arrangement after groupwise interleaving to the original arrangement obtained from data transmitted from a transmitting device.

A fifth transmission method/device of the present technology includes an encoding step/unit that performs LDPC encoding based on a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 10/16; A group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360-bit bit groups, and a group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360-bit bit groups, and 64 signal points of UC (Uniform Constellation) of 64QAM in which the LDPC code is interleaved in units of 6 bits. In the groupwise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the bits of the 69120-bit LDPC code are mapped to one of the bits of the LDPC code. The sequence of groups 0 to 191 is bit grouped.
42, 168, 36, 37, 152, 118, 14, 83, 105, 131, 26, 120, 92, 130, 158, 132, 49, 72, 137, 100, 88, 24, 53, 142, 110, 102, 74, 188, 113, 121, 12, 173, 5, 126, 127, 3, 93, 46, 164, 109, 151, 2, 98, 153, 116, 89, 101, 136, 35, 80, 0, 133, 183, 162, 185, 56, 17, 87, 117, 184, 54, 70, 176, 91, 134, 51, 38, 73, 165, 99, 169, 43, 167, 86, 11, 144, 78, 58, 64, 13, 119, 33, 166, 6, 75, 31, 15, 28, 125, 148, 27, 114, 82, 45, 55, 191, 160, 115, 1, 69, 187, 122, 177, 32, 172, 52, 112, 171, 124, 180, 85, 150, 7, 57, 60, 94, 181, 29, 97, 128, 19, 149, 175, 50, 140, 10, 174, 68, 59, 39, 106, 44, 62, 71, 18, 107, 156, 159, 146, 48, 81, 111, 96, 103, 34, 161, 141, 154, 76, 61, 135, 20, 84, 77, 108, 23, 145, 182, 170, 139, 157, 47, 9, 63, 123, 138, 155, 79, 4, 30, 143, 25, 90, 66, 147, 186, 179, 129, 21, 65, 41, 95, 67, 22, 163, 190, 16, 8, 104, 189, 40, 178
The LDPC code includes information bits and parity bits, the check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is , and the parity check matrix initial value table is a table representing the position of one element of the information matrix section for every 360 columns,
200 588 3305 4771 6288 8400 11092 11126 14245 14255 17022 17190 19241 20350 20451 21069 25243
80 2914 4126 5426 6129 7790 9546 12909 14660 17357 18278 19612 21168 22367 23314 24801 24907
1216 2713 4897 6540 7016 7787 8321 9717 9934 12295 18749 20344 21386 21682 21735 24205 24825
6784 8163 8691 8743 10045 10319 10767 11141 11756 12004 12463 13407 14682 15458 20771 21060 22914
463 1260 1897 2128 2908 5157 7851 14177 16187 17463 18212 18221 19212 21864 24198 25318 25450
794 835 1163 4551 4597 5792 6092 7809 8576 8862 10986 12164 13053 14459 15978 23829 25072
144 4258 4342 7326 8165 9627 11432 12552 17582 17621 18145 19201 19372 19718 21036 25147 25774
617 2639 2749 2898 3414 4305 4802 6183 8551 9850 13679 20759 22501 24244 24331 24631 25587
1622 2258 4257 6069 10343 10642 11003 12520 13993 17086 18236 18522 24679 25361 25371 25595
1826 3926 5021 5905 6192 6839 7678 9136 9188 9716 10986 11191 12551 14648 16169 16234
2175 2396 2473 8548 9753 12115 12208 13469 15438 16985 19350 20424 21357 22819 22830 25671
265 397 6675 7152 8074 13030 13161 13336 15843 16917 17930 18014 18660 19218 22236 24940
5744 6883 7780 7839 8485 10016 10548 12131 12158 16211 16793 18749 20570 21757 22255 24489
2082 4768 7025 8803 10237 10932 13885 14266 14370 14982 16411 18443 18773 19570 21420 23311
1040 1376 2823 2998 3789 6636 7755 9819 13705 13868 14176 16202 16247 24943 25196 25489
223 1967 3289 4541 7420 9881 11086 12868 13550 14760 15434 18287 19098 20909 22905 25887
1906 2049 2147 2756 2845 4773 8337 8832 9363 12375 13651 16366 17546 20486 21624 22664
1619 1955 2393 3078 3208 3593 5246 8565 10956 11335 11865 14837 15006 15544 18820 22687
2086 3409 3586 4269 6587 8650 10165 11241 15624 16728 17814 18392 18667 19859 21132 25339
382 1160 1912 3700 3783 12069 14672 16842 18053 19626 20724 21244 21792 22679 23873 24517
1217 1486 5139 6774 7413 10622 11571 11697 13406 13487 20713 22436 22610 22806 23522 23632
1225 2927 6221 6247 8197 9322 11826 11948 12230 13899 15820 16791 17444 23155 24543 24650
1056 2975 6018 7698 7736 7940 11870 12964 17498 17577 19541 20124 20705 22693 23151 25627
658 790 1559 3683 6060 9059 12347 12990 13095 16317 17801 18816 20050 20979 23584 25472
1133 3343 6895 7146 7261 8340 9115 11248 14543 16030 16291 17972 22369 22479 24388 25280
1907 4021 8277 17631
7807 8063 10076 24958
5455 8638 13801 18832
15525 24030 24978
7854 21083 21197
8416 15614 24639
9382 13998 24091
1244 19468 24804
5100 14187 21263
12267 18441 22757
185 23294 23412
5136 24218 25509
6159 12323 19472
7490 9770 19813
1457 2204 4186
14200 15609 18700
4544 6337 17759
3697 13810 14537
10853 16611 23001
504 12709 23116
1338 21523 22880
1098 8530 23846
13699 19776 25783
3299 3629 16222
1821 2402 12416
11177 20793 24292
21580 24038 24094
11769 13819 13950
5388 9428 13527
20320 23996 24752
2923 14906 18768
911 10059 17607
1535 3090 22968
3398 8243 12265
9801 10001 20184
11839 15703 16757
1834 13797 14101
4469 11503 14694
4047 8684 23737
15682 21342 21898
7345 8077 22245
4108 20676 24406
8787 19625 22194
8536 15518 20879
3339 15738 19592
2916 13483 23680
3853 12107 18338
16962 21265 25429
10181 18667 25563
2867 21873 23535
8601 19728 23807
4484 17647 22060
6457 17641 23777
17432 18680 20224
3046 14453 19429
807 2064 12639
17630 20286 21847
13703 13720 24044
8382 9588 10339
18818 23311 24714
5397 13213 24988
4077 9348 21707
10628 15352 21292
1075 7625 18287
5771 20506 20926
13545 18180 21566
12022 19203 25134
86 12306 20066
7797 10752 15305
2986 4186 9128
9099 17285 24986
3530 17904 21836
2283 20216 25272
22562 24667 25143
1673 3837 5198
4188 13181 22061
17800 20341 22591
3466 4433 24958
145 7746 23940
4718 15618 19372
2735 11877 13719
3560 6483 10536
4167 7567 8558
4511 5862 16331
3268 6965 25578
5552 20627 24489
1425 2331 4414
3352 12606 19595
4653 8383 20029
9163 22097 24174
7324 16151 20228
280 4353 25404
5173 7657 25604
6910 13531 22225
18274 19994 21778
This is a transmission method/device.

A fifth receiving device/method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code whose code length N is 69120 bits and whose encoding rate r is 10/16; A groupwise interleaving unit performs groupwise interleaving that interleaves the code in units of 360-bit bit groups, and the LDPC code is interleaved in units of 6 bits at any of the 64 signal points of UC (Uniform Constellation) of 64QAM. In the group-wise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is , bit group
42, 168, 36, 37, 152, 118, 14, 83, 105, 131, 26, 120, 92, 130, 158, 132, 49, 72, 137, 100, 88, 24, 53, 142, 110, 102, 74, 188, 113, 121, 12, 173, 5, 126, 127, 3, 93, 46, 164, 109, 151, 2, 98, 153, 116, 89, 101, 136, 35, 80, 0, 133, 183, 162, 185, 56, 17, 87, 117, 184, 54, 70, 176, 91, 134, 51, 38, 73, 165, 99, 169, 43, 167, 86, 11, 144, 78, 58, 64, 13, 119, 33, 166, 6, 75, 31, 15, 28, 125, 148, 27, 114, 82, 45, 55, 191, 160, 115, 1, 69, 187, 122, 177, 32, 172, 52, 112, 171, 124, 180, 85, 150, 7, 57, 60, 94, 181, 29, 97, 128, 19, 149, 175, 50, 140, 10, 174, 68, 59, 39, 106, 44, 62, 71, 18, 107, 156, 159, 146, 48, 81, 111, 96, 103, 34, 161, 141, 154, 76, 61, 135, 20, 84, 77, 108, 23, 145, 182, 170, 139, 157, 47, 9, 63, 123, 138, 155, 79, 4, 30, 143, 25, 90, 66, 147, 186, 179, 129, 21, 65, 41, 95, 67, 22, 163, 190, 16, 8, 104, 189, 40, 178
The LDPC code includes information bits and parity bits, the check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is , and the parity check matrix initial value table is a table representing the position of one element of the information matrix section for every 360 columns,
200 588 3305 4771 6288 8400 11092 11126 14245 14255 17022 17190 19241 20350 20451 21069 25243
80 2914 4126 5426 6129 7790 9546 12909 14660 17357 18278 19612 21168 22367 23314 24801 24907
1216 2713 4897 6540 7016 7787 8321 9717 9934 12295 18749 20344 21386 21682 21735 24205 24825
6784 8163 8691 8743 10045 10319 10767 11141 11756 12004 12463 13407 14682 15458 20771 21060 22914
463 1260 1897 2128 2908 5157 7851 14177 16187 17463 18212 18221 19212 21864 24198 25318 25450
794 835 1163 4551 4597 5792 6092 7809 8576 8862 10986 12164 13053 14459 15978 23829 25072
144 4258 4342 7326 8165 9627 11432 12552 17582 17621 18145 19201 19372 19718 21036 25147 25774
617 2639 2749 2898 3414 4305 4802 6183 8551 9850 13679 20759 22501 24244 24331 24631 25587
1622 2258 4257 6069 10343 10642 11003 12520 13993 17086 18236 18522 24679 25361 25371 25595
1826 3926 5021 5905 6192 6839 7678 9136 9188 9716 10986 11191 12551 14648 16169 16234
2175 2396 2473 8548 9753 12115 12208 13469 15438 16985 19350 20424 21357 22819 22830 25671
265 397 6675 7152 8074 13030 13161 13336 15843 16917 17930 18014 18660 19218 22236 24940
5744 6883 7780 7839 8485 10016 10548 12131 12158 16211 16793 18749 20570 21757 22255 24489
2082 4768 7025 8803 10237 10932 13885 14266 14370 14982 16411 18443 18773 19570 21420 23311
1040 1376 2823 2998 3789 6636 7755 9819 13705 13868 14176 16202 16247 24943 25196 25489
223 1967 3289 4541 7420 9881 11086 12868 13550 14760 15434 18287 19098 20909 22905 25887
1906 2049 2147 2756 2845 4773 8337 8832 9363 12375 13651 16366 17546 20486 21624 22664
1619 1955 2393 3078 3208 3593 5246 8565 10956 11335 11865 14837 15006 15544 18820 22687
2086 3409 3586 4269 6587 8650 10165 11241 15624 16728 17814 18392 18667 19859 21132 25339
382 1160 1912 3700 3783 12069 14672 16842 18053 19626 20724 21244 21792 22679 23873 24517
1217 1486 5139 6774 7413 10622 11571 11697 13406 13487 20713 22436 22610 22806 23522 23632
1225 2927 6221 6247 8197 9322 11826 11948 12230 13899 15820 16791 17444 23155 24543 24650
1056 2975 6018 7698 7736 7940 11870 12964 17498 17577 19541 20124 20705 22693 23151 25627
658 790 1559 3683 6060 9059 12347 12990 13095 16317 17801 18816 20050 20979 23584 25472
1133 3343 6895 7146 7261 8340 9115 11248 14543 16030 16291 17972 22369 22479 24388 25280
1907 4021 8277 17631
7807 8063 10076 24958
5455 8638 13801 18832
15525 24030 24978
7854 21083 21197
8416 15614 24639
9382 13998 24091
1244 19468 24804
5100 14187 21263
12267 18441 22757
185 23294 23412
5136 24218 25509
6159 12323 19472
7490 9770 19813
1457 2204 4186
14200 15609 18700
4544 6337 17759
3697 13810 14537
10853 16611 23001
504 12709 23116
1338 21523 22880
1098 8530 23846
13699 19776 25783
3299 3629 16222
1821 2402 12416
11177 20793 24292
21580 24038 24094
11769 13819 13950
5388 9428 13527
20320 23996 24752
2923 14906 18768
911 10059 17607
1535 3090 22968
3398 8243 12265
9801 10001 20184
11839 15703 16757
1834 13797 14101
4469 11503 14694
4047 8684 23737
15682 21342 21898
7345 8077 22245
4108 20676 24406
8787 19625 22194
8536 15518 20879
3339 15738 19592
2916 13483 23680
3853 12107 18338
16962 21265 25429
10181 18667 25563
2867 21873 23535
8601 19728 23807
4484 17647 22060
6457 17641 23777
17432 18680 20224
3046 14453 19429
807 2064 12639
17630 20286 21847
13703 13720 24044
8382 9588 10339
18818 23311 24714
5397 13213 24988
4077 9348 21707
10628 15352 21292
1075 7625 18287
5771 20506 20926
13545 18180 21566
12022 19203 25134
86 12306 20066
7797 10752 15305
2986 4186 9128
9099 17285 24986
3530 17904 21836
2283 20216 25272
22562 24667 25143
1673 3837 5198
4188 13181 22061
17800 20341 22591
3466 4433 24958
145 7746 23940
4718 15618 19372
2735 11877 13719
3560 6483 10536
4167 7567 8558
4511 5862 16331
3268 6965 25578
5552 20627 24489
1425 2331 4414
3352 12606 19595
4653 8383 20029
9163 22097 24174
7324 16151 20228
280 4353 25404
5173 7657 25604
6910 13531 22225
18274 19994 21778
The present invention is a receiving device/method including a groupwise deinterleaving unit/step for restoring the LDPC code arrangement after groupwise interleaving to the original arrangement obtained from data transmitted from a transmitting device.

A sixth transmission method/device of the present technology includes an encoding step/unit that performs LDPC encoding based on a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 12/16; A group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360-bit bit groups, and a group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360-bit bit groups, and 64 signal points of UC (Uniform Constellation) of 64QAM in which the LDPC code is interleaved in units of 6 bits. In the groupwise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the bits of the 69120-bit LDPC code are mapped to one of the bits of the LDPC code. The sequence of groups 0 to 191 is bit grouped.
92, 132, 39, 44, 190, 21, 70, 146, 48, 13, 17, 187, 119, 43, 94, 157, 150, 98, 96, 47, 86, 63, 152, 158, 84, 170, 81, 7, 62, 191, 174, 99, 116, 10, 85, 113, 135, 28, 53, 122, 83, 141, 77, 23, 131, 4, 40, 168, 129, 109, 51, 130, 188, 147, 29, 50, 26, 78, 148, 164, 167, 103, 36, 134, 2, 177, 20, 123, 27, 90, 176, 5, 33, 133, 189, 138, 76, 41, 89, 35, 72, 139, 32, 73, 68, 67, 101, 166, 93, 54, 52, 42, 110, 59, 8, 179, 34, 171, 143, 137, 9, 126, 155, 108, 142, 120, 163, 12, 3, 75, 159, 107, 65, 128, 87, 6, 22, 57, 100, 24, 64, 106, 117, 19, 58, 95, 74, 180, 125, 136, 186, 154, 121, 161, 88, 37, 114, 102, 105, 160, 80, 185, 82, 124, 184, 15, 16, 18, 118, 173, 151, 11, 91, 79, 46, 140, 127, 1, 169, 0, 61, 66, 45, 162, 149, 115, 144, 30, 25, 175, 153, 183, 60, 38, 31, 111, 182, 49, 55, 145, 56, 181, 104, 14, 71, 178, 112, 172, 165, 69, 97, 156
The LDPC code includes information bits and parity bits, the check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is , and the parity check matrix initial value table is a table representing the position of one element of the information matrix section for every 360 columns,
1507 1536 2244 4721 6374 7839 11001 12684 13196 13602 14245 14383 14398 16182 17248
623 696 1186 1370 4409 5237 5911 8278 9539 12139 12810 13422 15525 16232 16252
530 1953 3745 5512 6676 9069 9433 10683 11530 12263 12519 14931 15326 15581 16208
273 685 3132 5872 6388 7149 7316 7367 9041 11102 11211 12059 15189 15973 16435
814 1297 1896 6018 7801 8810 9701 9992 10314 13618 13771 14934 15198 16340 16742
58 803 2553 3967 6032 8374 9168 10047 10073 10909 12701 12748 13543 14111 17043
1082 1577 2108 2344 5035 5051 10038 10356 12156 12308 13815 15453 15830 16305 17234
1882 3731 5182 5554 6330 6605 7126 10195 10508 12151 12191 12241 12288 13755 16472
85 604 1278 3768 4831 6820 9471 10773 10873 12785 12973 13623 14562 14697 16811
928 1864 6027 7023 7644 8279 8580 9221 9417 9883 12032 12483 12734 14335 15842
2104 2752 4530 4820 5662 9197 9464 9972 10057 11079 12408 13005 13684 15507 16295
82 752 3374 4026 7265 8112 12236 12434 12460 13110 13495 15110 15299 15359 17221
1137 1411 1546 1614 1835 6053 6151 8618 9059 14057 14941 15670 16321 16965
447 1960 2369 2861 3047 3508 4077 4358 4370 5806 12517 13658 14371 14749
420 981 1657 2313 3353 4699 5094 5184 10076 10530 11521 13040 15960 16853
3572 3851 3870 5218 6400 6780 9167 9603 10328 10543 12892 13722 16910 16929
203 2588 4522 4692 5399 6840 7417 8896 9045 9188 10390 12507 12615 16386
543 1262 2536 4358 7658 7714 9392 11079 12283 12694 14734 16195 16317 16751
905 1059 3393 4347 4554 4758 5568 8652 9991 10717 10975 11146 12824 16373
1229 2308 4876 5329 5424 5906 6227 6667 7141 7697 12055 12969 13582 16638
697 1864 2560 4190 5097 5288 6565 9150 9282 9519 10727 12492 13292 16924
363 3152 3715 3722 4582 5050 8399 9413 9851 10305 12116 13471 15318 16018
338 2342 2404 4733 6189 6792 7251 7921 8509 8579 8729 11921 12900 15546
1630 1867 2018 3038 3202 6364 7648 8692 9496 9705 10433 13508 14583 16341
1041 2754 3015 3427 3512 4351 5174 6539 8100 8639 9912 11911 12666 14187
1134 1619 4758 5545 6842 7045 8421 10373 10390 12672 13484 15178 16697 16727
589 652 1174 2157 3951 4733 5278 5859 7619 9488 11665 12335 15516 16024
1457 1832 2525 3690 5093 6000 6276 7974 8652 9759 10434 15025 15267 16448
932 3328 3349 3511 4776 6266 6711 7761 8674 9748 11167 12134 12942 14354
1939 1979 3141 4238 6715 7148 7673 12025 12455 14829 14989 15081 16491 17242
1363 2451
1953 10230
6218 7655
9302 15856
10461 10503
9005 16075
878 14223 15181
3535 5327 14405
8116 8396 9828
2864 6306 14832
24 11009 16377
7064 11014 16139
4318 8353 14997
583 5626 10217
11196 13669 16585
6123 7518 9304
2258 8250 12082
7564 14195 15236
10104 10233 13778
2044 7801 11705
10906 11443 13227
1592 7853 14796
3054 8887 13077
6486 7003 9238
424 9055 13390
618 4077 11120
11159 13405 16070
2927 8689 17210
723 5842 12062
4817 9269 10820
208 6947 12903
2987 10116 11520
3522 6321 15637
148 3087 12764
262 1613 14121
7236 10798 11759
3193 4958 11292
7537 12439 15202
8000 9580 17269
9665 9691 15654
5946 14246 16040
4283 8145 10944
1082 1829 11267
1272 6119 13182
20 11943 14128
4591 8403 16530
2212 13724 13933
2079 10365 14633
1269 11307 16370
2467 4744 10714
6256 7915 9724
8799 11433 16880
459 6799 10102
3795 6930 13350
1295 13018 14967
3542 7310 10974
6905 15080 16105
2673 3143 12349
4698 4801 14770
7512 15844 15965
3276 4069 10099
1893 4676 6679
1985 7244 10163
6333 12760 12912
852 5954 11771
6958 9242 10613
5651 10089 12309
4124 7455 13224
503 6787 10720
10594 12717 14007
4501 5311 8067
4507 5620 13932
9133 11025 13866
5021 16201 16217
6166 7438 17185
1324 5671 11586
2266 6335 7716
512 9515 11595
869 6096 13886
10049 12536 14474
470 8286 8306
1268 5478 6424
8178 8817 14506
11460 15128 16761
6364 10121 16806
9347 15211 16915
1587 3591 15546
17 4132 17071
1677 8810 15764
3862 7633 13685
3855 11931 12792
2652 13909 17080
5581 13919 16126
7129 8976 11152
6662 7845 13424
9751 9965 13847
3662 9308 9534
4283 7474 7682
2418 8774 13433
508 3864 6859
12098 13920 15326
1129 3271 16892
5072 8819 10323
4749 4984 6390
212 13603 14893
4966 8895 9320
1012 3677 5711
6654 9969 15178
4596 5147 5905
1541 4149 15594
8005 8604 15147
2519 10882 11961
190 8417 13600
3543 4639 14618
This is a transmission method/device.

A sixth receiving device/method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code whose code length N is 69120 bits and whose encoding rate r is 12/16; A groupwise interleaving unit performs groupwise interleaving that interleaves the code in units of 360-bit bit groups, and the LDPC code is interleaved in units of 6 bits at any of the 64 signal points of UC (Uniform Constellation) of 64QAM. In the group-wise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is , bit group
92, 132, 39, 44, 190, 21, 70, 146, 48, 13, 17, 187, 119, 43, 94, 157, 150, 98, 96, 47, 86, 63, 152, 158, 84, 170, 81, 7, 62, 191, 174, 99, 116, 10, 85, 113, 135, 28, 53, 122, 83, 141, 77, 23, 131, 4, 40, 168, 129, 109, 51, 130, 188, 147, 29, 50, 26, 78, 148, 164, 167, 103, 36, 134, 2, 177, 20, 123, 27, 90, 176, 5, 33, 133, 189, 138, 76, 41, 89, 35, 72, 139, 32, 73, 68, 67, 101, 166, 93, 54, 52, 42, 110, 59, 8, 179, 34, 171, 143, 137, 9, 126, 155, 108, 142, 120, 163, 12, 3, 75, 159, 107, 65, 128, 87, 6, 22, 57, 100, 24, 64, 106, 117, 19, 58, 95, 74, 180, 125, 136, 186, 154, 121, 161, 88, 37, 114, 102, 105, 160, 80, 185, 82, 124, 184, 15, 16, 18, 118, 173, 151, 11, 91, 79, 46, 140, 127, 1, 169, 0, 61, 66, 45, 162, 149, 115, 144, 30, 25, 175, 153, 183, 60, 38, 31, 111, 182, 49, 55, 145, 56, 181, 104, 14, 71, 178, 112, 172, 165, 69, 97, 156
The LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is , and the parity check matrix initial value table is a table representing the position of one element of the information matrix section for every 360 columns,
1507 1536 2244 4721 6374 7839 11001 12684 13196 13602 14245 14383 14398 16182 17248
623 696 1186 1370 4409 5237 5911 8278 9539 12139 12810 13422 15525 16232 16252
530 1953 3745 5512 6676 9069 9433 10683 11530 12263 12519 14931 15326 15581 16208
273 685 3132 5872 6388 7149 7316 7367 9041 11102 11211 12059 15189 15973 16435
814 1297 1896 6018 7801 8810 9701 9992 10314 13618 13771 14934 15198 16340 16742
58 803 2553 3967 6032 8374 9168 10047 10073 10909 12701 12748 13543 14111 17043
1082 1577 2108 2344 5035 5051 10038 10356 12156 12308 13815 15453 15830 16305 17234
1882 3731 5182 5554 6330 6605 7126 10195 10508 12151 12191 12241 12288 13755 16472
85 604 1278 3768 4831 6820 9471 10773 10873 12785 12973 13623 14562 14697 16811
928 1864 6027 7023 7644 8279 8580 9221 9417 9883 12032 12483 12734 14335 15842
2104 2752 4530 4820 5662 9197 9464 9972 10057 11079 12408 13005 13684 15507 16295
82 752 3374 4026 7265 8112 12236 12434 12460 13110 13495 15110 15299 15359 17221
1137 1411 1546 1614 1835 6053 6151 8618 9059 14057 14941 15670 16321 16965
447 1960 2369 2861 3047 3508 4077 4358 4370 5806 12517 13658 14371 14749
420 981 1657 2313 3353 4699 5094 5184 10076 10530 11521 13040 15960 16853
3572 3851 3870 5218 6400 6780 9167 9603 10328 10543 12892 13722 16910 16929
203 2588 4522 4692 5399 6840 7417 8896 9045 9188 10390 12507 12615 16386
543 1262 2536 4358 7658 7714 9392 11079 12283 12694 14734 16195 16317 16751
905 1059 3393 4347 4554 4758 5568 8652 9991 10717 10975 11146 12824 16373
1229 2308 4876 5329 5424 5906 6227 6667 7141 7697 12055 12969 13582 16638
697 1864 2560 4190 5097 5288 6565 9150 9282 9519 10727 12492 13292 16924
363 3152 3715 3722 4582 5050 8399 9413 9851 10305 12116 13471 15318 16018
338 2342 2404 4733 6189 6792 7251 7921 8509 8579 8729 11921 12900 15546
1630 1867 2018 3038 3202 6364 7648 8692 9496 9705 10433 13508 14583 16341
1041 2754 3015 3427 3512 4351 5174 6539 8100 8639 9912 11911 12666 14187
1134 1619 4758 5545 6842 7045 8421 10373 10390 12672 13484 15178 16697 16727
589 652 1174 2157 3951 4733 5278 5859 7619 9488 11665 12335 15516 16024
1457 1832 2525 3690 5093 6000 6276 7974 8652 9759 10434 15025 15267 16448
932 3328 3349 3511 4776 6266 6711 7761 8674 9748 11167 12134 12942 14354
1939 1979 3141 4238 6715 7148 7673 12025 12455 14829 14989 15081 16491 17242
1363 2451
1953 10230
6218 7655
9302 15856
10461 10503
9005 16075
878 14223 15181
3535 5327 14405
8116 8396 9828
2864 6306 14832
24 11009 16377
7064 11014 16139
4318 8353 14997
583 5626 10217
11196 13669 16585
6123 7518 9304
2258 8250 12082
7564 14195 15236
10104 10233 13778
2044 7801 11705
10906 11443 13227
1592 7853 14796
3054 8887 13077
6486 7003 9238
424 9055 13390
618 4077 11120
11159 13405 16070
2927 8689 17210
723 5842 12062
4817 9269 10820
208 6947 12903
2987 10116 11520
3522 6321 15637
148 3087 12764
262 1613 14121
7236 10798 11759
3193 4958 11292
7537 12439 15202
8000 9580 17269
9665 9691 15654
5946 14246 16040
4283 8145 10944
1082 1829 11267
1272 6119 13182
20 11943 14128
4591 8403 16530
2212 13724 13933
2079 10365 14633
1269 11307 16370
2467 4744 10714
6256 7915 9724
8799 11433 16880
459 6799 10102
3795 6930 13350
1295 13018 14967
3542 7310 10974
6905 15080 16105
2673 3143 12349
4698 4801 14770
7512 15844 15965
3276 4069 10099
1893 4676 6679
1985 7244 10163
6333 12760 12912
852 5954 11771
6958 9242 10613
5651 10089 12309
4124 7455 13224
503 6787 10720
10594 12717 14007
4501 5311 8067
4507 5620 13932
9133 11025 13866
5021 16201 16217
6166 7438 17185
1324 5671 11586
2266 6335 7716
512 9515 11595
869 6096 13886
10049 12536 14474
470 8286 8306
1268 5478 6424
8178 8817 14506
11460 15128 16761
6364 10121 16806
9347 15211 16915
1587 3591 15546
17 4132 17071
1677 8810 15764
3862 7633 13685
3855 11931 12792
2652 13909 17080
5581 13919 16126
7129 8976 11152
6662 7845 13424
9751 9965 13847
3662 9308 9534
4283 7474 7682
2418 8774 13433
508 3864 6859
12098 13920 15326
1129 3271 16892
5072 8819 10323
4749 4984 6390
212 13603 14893
4966 8895 9320
1012 3677 5711
6654 9969 15178
4596 5147 5905
1541 4149 15594
8005 8604 15147
2519 10882 11961
190 8417 13600
3543 4639 14618
The present invention is a receiving device/method including a groupwise deinterleaving unit/step for restoring the LDPC code arrangement after groupwise interleaving to the original arrangement obtained from data transmitted from a transmitting device.

A seventh transmission method/device of the present technology includes an encoding step/unit that performs LDPC encoding based on a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 14/16; A group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360-bit bit groups, and a group-wise interleaving step/unit that performs group-wise interleaving to interleave the LDPC code in units of 360-bit bit groups, and 64 signal points of UC (Uniform Constellation) of 64QAM in which the LDPC code is interleaved in units of 6 bits. In the groupwise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the bits of the 69120-bit LDPC code are mapped to one of the bits of the LDPC code. The sequence of groups 0 to 191 is bit grouped.
133, 96, 46, 148, 78, 109, 149, 161, 55, 39, 183, 54, 186, 73, 150, 180, 189, 190, 22, 135, 12, 80, 42, 130, 164, 70, 126, 107, 57, 67, 15, 157, 52, 88, 5, 23, 123, 66, 53, 147, 177, 60, 131, 108, 171, 191, 44, 140, 98, 154, 37, 118, 176, 92, 124, 138, 132, 167, 173, 13, 79, 32, 145, 14, 113, 30, 2, 0, 165, 182, 153, 24, 144, 87, 82, 75, 141, 89, 137, 33, 100, 106, 128, 168, 29, 36, 172, 11, 111, 68, 16, 10, 34, 188, 35, 160, 77, 83, 178, 58, 59, 7, 56, 110, 104, 61, 76, 85, 121, 93, 19, 134, 179, 155, 163, 115, 185, 125, 112, 71, 8, 119, 18, 47, 151, 26, 103, 122, 9, 170, 146, 99, 49, 72, 102, 31, 40, 43, 158, 142, 4, 69, 139, 28, 174, 101, 84, 129, 156, 74, 62, 91, 159, 41, 38, 45, 136, 169, 21, 51, 181, 97, 166, 175, 90, 27, 86, 65, 105, 143, 127, 17, 6, 116, 94, 117, 48, 50, 25, 64, 95, 63, 184, 152, 120, 1, 187, 162, 114, 3, 81, 20
The LDPC code includes information bits and parity bits, the check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is , and the parity check matrix initial value table is a table representing the position of one element of the information matrix section for every 360 columns,
387 648 945 3023 3889 4856 5002 5167 6868 7477 7590 8165 8354
42 406 1279 1968 3016 4196 4599 4996 5019 6350 6785 7051 8529
534 784 1034 1160 2530 5033 5171 5469 6167 6372 6913 7718 8621
944 2506 2806 3149 3559 5101 6076 6083 6092 6147 6866 7908 8155
308 1869 1888 2569 3297 4742 5232 5442 6135 6814 7284 8238 8405
34 464 667 899 2421 3425 5382 6258 6373 6399 6489 7367 7922
2276 3014 3525 3829 4135 4276 4611 4733 4738 4956 6025 7152 8155
1047 1370 2406 2819 4600 4991 5017 5590 6199 6483 6556 6834 7760
66 380 2033 3698 4068 6096 6223 6238 6757 7541 7641 7677 8595
562 697 782 808 921 1703 3032 4300 7027 7481 7839 8160 8526
236 962 1557 2023 2135 2190 2892 3072 4523 6254 6838 7209 7381
196 1167 1179 1426 1675 1763 2345 2560 2613 5024 5761 6522 7973
512 822 1778 1924 2610 3445 4570 4805 5263 5299 8439 8448 8464
1923 2270 3204 3698 4456 4522 4601 5161 5207 6260 6310 6441 6851
104 281 622 1276 2172 2334 2731 3417 3854 4698 8095 8195 8333
451 528 1269 2169 2274 2393 3853 5002 5543 6121 6351 7364 8139
1685 2675 2790 2953 3103 3560 4336 5372 5495 5568 6429 6492 8206
604 1190 1279 2427 2714 3283 3312 3855 4566 6045 6664 6788 8317
338 917 1873 2102 2561 2655 4635 4765 5370 6249 6724 7668 8456
184 1166 1583 1859 2376 2521 3093 4181 4713 4926 5146 6070 8004
175 1227 2367 3402 3628 3982 4265 4282 4355 5972 6434 7280 7765
801 922 1029 1531 1606 3170 3824 4358 4732 4849 5225 6759 8183
509 1507 1704 1765 2183 2574 3271 4050 4299 4964 5968 6324 7091
567 795 1376 2390 2767 3424 5195 6355 6726 7607 8346 8352
308 1060 1973 2364 2937 3526 4221 4745 5185 5845 6146 7762
323 590 732 917 2636 3008 3792 3990 4322 4893 5211 8014
471 1249 1674 1841 2567 3124 3130 4885 5575 7521 7648 8227
1582 1669 1772 2386 3340 3387 3881 4322 6018 6055 6488 7177
976 1003 2127 3575 3816 6225 7404 7499 7542 8237 8421 8630
675 961 1957 3825 3858 4646 5248 5801 5940 6533 7040 8037
79 639 1363 1436 1763 2570 3874 4876 6870 6886 7104 8399
20 297 1330 2264 3287 3534 4441 4746 6569 6971 6976 8179
482 1125 1589 2892 3759 3871 4635 6038 6214 6796 6816 7621
1127 3336 3867 3929 4269 4794 5054 5842 6471 6547 7039 8560
217 1521
1983 8283
3731 4402
208 6703
242 4988
4170 5038
4108 8035
3301 8543
3168 8249
5028 5838
3470 8597
2901 5264
2505 4505
934 5117
1712 5819
3165 7273
3274 6115
4576 6330 7327
5380 6732 8439
2474 3723 7782
384 2783 5846
1453 4436 6625
3220 4261 4835
163 3117 7554
502 2119 4059
2200 4263 4930
2378 6294 7713
743 5501 6809
1364 6062 7808
4680 6468 7895
3469 3602 7304
1609 5386 5647
267 2921 3206
2565 3020 6269
1651 5224 5718
1128 5058 8579
286 3396 7660
1497 5171 6519
1894 6349 7924
1306 7744 8083
3096 3438 3836
2556 7409 8570
3273 4245 7935
1633 2023 3125
584 4914 6062
2015 2915 3435
1457 6366 6461
23 3576 8132
5322 6300 6520
5715 7113 7822
2044 5053 6607
63 5432 7850
5353 6355 8637
346 590 2648
4780 5997 6991
2556 2583 6537
661 2497 8350
7610 8307 8441
671 860 5986
1133 3158 5891
4360 5802 6547
4782 5688 6955
447 5030 6268
1501 5163 7232
1133 2743 3214
959 4100 7554
5712 7643 8385
1442 3180 8008
697 3078 8421
137 922 5123
597 2879 6340
824 2071 7882
1827 4411 5941
3846 5970 6398
1561 1580 7668
4335 6936 8042
4504 5309 6737
1846 3273 3333
272 4885 6718
1835 4761 6931
2141 3760 5129
3975 5012 6504
1258 2822 6030
242 4947 7668
559 6100 8425
1655 1962 4401
2369 2476 2765
114 156 3195
1651 4154 4448
4669 6064 7317
4988 5567 6697
2963 5578 5679
2064 2286 7790
289 4639 7582
1258 4312 5340
2428 4219 7268
1752 2321 6806
118 7302 8603
4170 4280 4445
2207 5067 7257
2 55 7413
1141 4791 7149
3407 5649 8075
2773 3198 3720
6970 7222 8633
2498 4764 5281
1048 2093 5031
2500 2851 8396
1694 3795 6666
2565 3343 4688
4228 4374 5947
2267 6745 7172
175 2662 3926
90 1517 6056
4069 5439 7648
1679 3394 4707
2136 4553 8265
482 2100 2302
3306 3729 8063
5263 7710 8240
1001 1335 4500
576 6736 7250
181 3601 3755
5899 7515 7714
1181 5332 7197
542 1150 1196
1386 2156 5873
656 3019 3213
263 1117 5957
4495 5904 6462
2547 2786 4215
4954 5848 6225
940 4478 7633
2124 3347 7069
This is a transmission method/device.

A seventh receiving device/method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code whose code length N is 69120 bits and whose encoding rate r is 14/16; A groupwise interleaving unit performs groupwise interleaving that interleaves the code in units of 360-bit bit groups, and the LDPC code is interleaved in units of 6 bits at any of the 64 signal points of UC (Uniform Constellation) of 64QAM. In the group-wise interleaving, the i+1-th bit group from the beginning of the LDPC code is set as bit group i, and the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is , bit group
133, 96, 46, 148, 78, 109, 149, 161, 55, 39, 183, 54, 186, 73, 150, 180, 189, 190, 22, 135, 12, 80, 42, 130, 164, 70, 126, 107, 57, 67, 15, 157, 52, 88, 5, 23, 123, 66, 53, 147, 177, 60, 131, 108, 171, 191, 44, 140, 98, 154, 37, 118, 176, 92, 124, 138, 132, 167, 173, 13, 79, 32, 145, 14, 113, 30, 2, 0, 165, 182, 153, 24, 144, 87, 82, 75, 141, 89, 137, 33, 100, 106, 128, 168, 29, 36, 172, 11, 111, 68, 16, 10, 34, 188, 35, 160, 77, 83, 178, 58, 59, 7, 56, 110, 104, 61, 76, 85, 121, 93, 19, 134, 179, 155, 163, 115, 185, 125, 112, 71, 8, 119, 18, 47, 151, 26, 103, 122, 9, 170, 146, 99, 49, 72, 102, 31, 40, 43, 158, 142, 4, 69, 139, 28, 174, 101, 84, 129, 156, 74, 62, 91, 159, 41, 38, 45, 136, 169, 21, 51, 181, 97, 166, 175, 90, 27, 86, 65, 105, 143, 127, 17, 6, 116, 94, 117, 48, 50, 25, 64, 95, 63, 184, 152, 120, 1, 187, 162, 114, 3, 81, 20
The LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is , and the parity check matrix initial value table is a table representing the position of one element of the information matrix section for every 360 columns,
387 648 945 3023 3889 4856 5002 5167 6868 7477 7590 8165 8354
42 406 1279 1968 3016 4196 4599 4996 5019 6350 6785 7051 8529
534 784 1034 1160 2530 5033 5171 5469 6167 6372 6913 7718 8621
944 2506 2806 3149 3559 5101 6076 6083 6092 6147 6866 7908 8155
308 1869 1888 2569 3297 4742 5232 5442 6135 6814 7284 8238 8405
34 464 667 899 2421 3425 5382 6258 6373 6399 6489 7367 7922
2276 3014 3525 3829 4135 4276 4611 4733 4738 4956 6025 7152 8155
1047 1370 2406 2819 4600 4991 5017 5590 6199 6483 6556 6834 7760
66 380 2033 3698 4068 6096 6223 6238 6757 7541 7641 7677 8595
562 697 782 808 921 1703 3032 4300 7027 7481 7839 8160 8526
236 962 1557 2023 2135 2190 2892 3072 4523 6254 6838 7209 7381
196 1167 1179 1426 1675 1763 2345 2560 2613 5024 5761 6522 7973
512 822 1778 1924 2610 3445 4570 4805 5263 5299 8439 8448 8464
1923 2270 3204 3698 4456 4522 4601 5161 5207 6260 6310 6441 6851
104 281 622 1276 2172 2334 2731 3417 3854 4698 8095 8195 8333
451 528 1269 2169 2274 2393 3853 5002 5543 6121 6351 7364 8139
1685 2675 2790 2953 3103 3560 4336 5372 5495 5568 6429 6492 8206
604 1190 1279 2427 2714 3283 3312 3855 4566 6045 6664 6788 8317
338 917 1873 2102 2561 2655 4635 4765 5370 6249 6724 7668 8456
184 1166 1583 1859 2376 2521 3093 4181 4713 4926 5146 6070 8004
175 1227 2367 3402 3628 3982 4265 4282 4355 5972 6434 7280 7765
801 922 1029 1531 1606 3170 3824 4358 4732 4849 5225 6759 8183
509 1507 1704 1765 2183 2574 3271 4050 4299 4964 5968 6324 7091
567 795 1376 2390 2767 3424 5195 6355 6726 7607 8346 8352
308 1060 1973 2364 2937 3526 4221 4745 5185 5845 6146 7762
323 590 732 917 2636 3008 3792 3990 4322 4893 5211 8014
471 1249 1674 1841 2567 3124 3130 4885 5575 7521 7648 8227
1582 1669 1772 2386 3340 3387 3881 4322 6018 6055 6488 7177
976 1003 2127 3575 3816 6225 7404 7499 7542 8237 8421 8630
675 961 1957 3825 3858 4646 5248 5801 5940 6533 7040 8037
79 639 1363 1436 1763 2570 3874 4876 6870 6886 7104 8399
20 297 1330 2264 3287 3534 4441 4746 6569 6971 6976 8179
482 1125 1589 2892 3759 3871 4635 6038 6214 6796 6816 7621
1127 3336 3867 3929 4269 4794 5054 5842 6471 6547 7039 8560
217 1521
1983 8283
3731 4402
208 6703
242 4988
4170 5038
4108 8035
3301 8543
3168 8249
5028 5838
3470 8597
2901 5264
2505 4505
934 5117
1712 5819
3165 7273
3274 6115
4576 6330 7327
5380 6732 8439
2474 3723 7782
384 2783 5846
1453 4436 6625
3220 4261 4835
163 3117 7554
502 2119 4059
2200 4263 4930
2378 6294 7713
743 5501 6809
1364 6062 7808
4680 6468 7895
3469 3602 7304
1609 5386 5647
267 2921 3206
2565 3020 6269
1651 5224 5718
1128 5058 8579
286 3396 7660
1497 5171 6519
1894 6349 7924
1306 7744 8083
3096 3438 3836
2556 7409 8570
3273 4245 7935
1633 2023 3125
584 4914 6062
2015 2915 3435
1457 6366 6461
23 3576 8132
5322 6300 6520
5715 7113 7822
2044 5053 6607
63 5432 7850
5353 6355 8637
346 590 2648
4780 5997 6991
2556 2583 6537
661 2497 8350
7610 8307 8441
671 860 5986
1133 3158 5891
4360 5802 6547
4782 5688 6955
447 5030 6268
1501 5163 7232
1133 2743 3214
959 4100 7554
5712 7643 8385
1442 3180 8008
697 3078 8421
137 922 5123
597 2879 6340
824 2071 7882
1827 4411 5941
3846 5970 6398
1561 1580 7668
4335 6936 8042
4504 5309 6737
1846 3273 3333
272 4885 6718
1835 4761 6931
2141 3760 5129
3975 5012 6504
1258 2822 6030
242 4947 7668
559 6100 8425
1655 1962 4401
2369 2476 2765
114 156 3195
1651 4154 4448
4669 6064 7317
4988 5567 6697
2963 5578 5679
2064 2286 7790
289 4639 7582
1258 4312 5340
2428 4219 7268
1752 2321 6806
118 7302 8603
4170 4280 4445
2207 5067 7257
2 55 7413
1141 4791 7149
3407 5649 8075
2773 3198 3720
6970 7222 8633
2498 4764 5281
1048 2093 5031
2500 2851 8396
1694 3795 6666
2565 3343 4688
4228 4374 5947
2267 6745 7172
175 2662 3926
90 1517 6056
4069 5439 7648
1679 3394 4707
2136 4553 8265
482 2100 2302
3306 3729 8063
5263 7710 8240
1001 1335 4500
576 6736 7250
181 3601 3755
5899 7515 7714
1181 5332 7197
542 1150 1196
1386 2156 5873
656 3019 3213
263 1117 5957
4495 5904 6462
2547 2786 4215
4954 5848 6225
940 4478 7633
2124 3347 7069
The present invention is a receiving device/method including a groupwise deinterleaving unit/step for restoring the LDPC code arrangement after groupwise interleaving to the original arrangement obtained from data transmitted from a transmitting device.

In the first transmission method/device of the present technology, LDPC encoding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 2/16, and the LDPC code is , group-wise interleaving is performed in which interleaving is performed in units of 360-bit bit groups. Then, the LDPC code is mapped to one of 64 signal points of 64QAM UC (Uniform Constellation) in units of 6 bits. In the groupwise interleaving, the i+1th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is defined as a bit group.
10, 61, 30, 88, 33, 60, 1, 102, 45, 103, 119, 181, 82, 112, 12, 67, 69, 171, 108, 26, 145, 156, 81, 152, 8, 16, 68, 13, 99, 183, 146, 27, 158, 147, 132, 118, 180, 120, 173, 59, 186, 49, 7, 17, 35, 104, 129, 75, 54, 72, 18, 48, 15, 177, 191, 51, 24, 93, 106, 22, 71, 29, 141, 32, 143, 128, 175, 86, 190, 74, 36, 43, 144, 46, 63, 65, 133, 31, 87, 44, 20, 117, 76, 187, 80, 101, 151, 47, 130, 116, 162, 127, 153, 100, 94, 2, 41, 138, 125, 131, 11, 50, 40, 21, 184, 167, 172, 85, 160, 105, 73, 38, 157, 53, 39, 97, 107, 165, 168, 89, 148, 126, 3, 4, 114, 161, 155, 182, 136, 149, 111, 98, 113, 139, 92, 109, 174, 185, 95, 56, 135, 37, 163, 154, 0, 96, 78, 122, 5, 179, 140, 83, 123, 77, 9, 19, 66, 42, 137, 14, 23, 159, 189, 110, 142, 84, 169, 166, 52, 91, 164, 28, 124, 121, 70, 115, 90, 170, 58, 6, 178, 176, 64, 188, 57, 34, 79, 62, 25, 134, 150, 55
are interleaved with each other. The parity check matrix initial value table that defines the parity check matrix is as described above.

In the first receiving device/method of the present technology, the arrangement of the LDPC codes after groupwise interleaving obtained from the data transmitted from the first transmitting device implementing the first transmission method is the original arrangement. be returned.

In the second transmission method/device of the present technology, LDPC encoding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 4/16, and the LDPC code is , group-wise interleaving is performed in which interleaving is performed in units of 360-bit bit groups. Then, the LDPC code is mapped to one of 64 signal points of 64QAM UC (Uniform Constellation) in units of 6 bits. In the groupwise interleaving, the i+1th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is defined as a bit group.
8, 165, 180, 182, 189, 61, 7, 140, 105, 78, 86, 75, 15, 28, 82, 1, 136, 130, 35, 24, 70, 152, 121, 11, 36, 66, 83, 57, 164, 111, 137, 128, 175, 156, 151, 48, 44, 147, 18, 64, 184, 42, 159, 3, 6, 162, 170, 98, 101, 29, 102, 21, 188, 79, 138, 45, 124, 118, 155, 125, 34, 27, 5, 97, 109, 145, 54, 56, 126, 187, 16, 149, 160, 178, 23, 141, 30, 117, 25, 69, 116, 131, 94, 65, 191, 99, 181, 185, 115, 67, 93, 106, 38, 71, 76, 113, 132, 172, 103, 95, 92, 107, 4, 163, 139, 72, 157, 0, 12, 52, 68, 88, 161, 183, 39, 14, 32, 49, 19, 77, 174, 47, 154, 17, 134, 133, 51, 120, 74, 177, 41, 108, 142, 143, 13, 26, 59, 100, 123, 55, 158, 62, 104, 148, 135, 9, 179, 53, 176, 33, 169, 129, 186, 43, 167, 87, 119, 84, 90, 150, 20, 10, 122, 114, 80, 50, 146, 144, 96, 171, 40, 73, 81, 168, 112, 190, 37, 173, 46, 110, 60, 85, 153, 2, 63, 91, 127, 89, 31, 58, 22, 166
are interleaved with each other. The parity check matrix initial value table that defines the parity check matrix is as described above.

In the second receiving device/method of the present technology, the arrangement of the LDPC codes after groupwise interleaving obtained from the data transmitted from the second transmitting device implementing the second transmission method is the original arrangement. be returned.

In the third transmission method/device of the present technology, LDPC encoding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 6/16, and the LDPC code is , group-wise interleaving is performed in which interleaving is performed in units of 360-bit bit groups. Then, the LDPC code is mapped to one of 64 signal points of 64QAM UC (Uniform Constellation) in units of 6 bits. In the groupwise interleaving, the i+1th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is defined as a bit group.
17, 84, 125, 70, 134, 63, 68, 162, 61, 31, 74, 137, 7, 138, 5, 60, 76, 105, 160, 12, 114, 81, 155, 112, 153, 191, 82, 148, 118, 108, 58, 159, 43, 161, 149, 96, 71, 30, 145, 174, 67, 77, 47, 94, 48, 156, 151, 141, 131, 176, 183, 41, 35, 83, 164, 55, 169, 98, 187, 124, 100, 54, 104, 40, 2, 72, 8, 85, 182, 103, 6, 37, 107, 39, 42, 123, 57, 106, 13, 150, 129, 46, 109, 188, 45, 113, 44, 90, 20, 165, 142, 110, 22, 28, 173, 38, 52, 16, 34, 0, 3, 144, 27, 49, 139, 177, 132, 184, 25, 87, 152, 119, 158, 78, 186, 167, 97, 24, 99, 69, 120, 122, 133, 163, 21, 51, 101, 185, 111, 26, 18, 10, 33, 170, 95, 65, 14, 130, 157, 59, 115, 127, 92, 56, 1, 80, 66, 126, 178, 147, 75, 179, 171, 53, 146, 88, 4, 128, 121, 86, 117, 19, 23, 168, 181, 11, 102, 93, 73, 140, 89, 136, 9, 180, 62, 36, 79, 91, 190, 143, 29, 154, 32, 64, 166, 116, 15, 189, 175, 50, 135, 172
are interleaved with each other. The parity check matrix initial value table that defines the parity check matrix is as described above.

In the third receiving device/method of the present technology, the arrangement of the LDPC codes after groupwise interleaving obtained from the data transmitted from the third transmitting device implementing the third transmission method is the original arrangement. be returned.

In the fourth transmission method/device of the present technology, LDPC encoding is performed based on a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 8/16, and the LDPC code is , group-wise interleaving is performed in which interleaving is performed in units of 360-bit bit groups. Then, the LDPC code is mapped to one of 64 signal points of 64QAM UC (Uniform Constellation) in units of 6 bits. In the groupwise interleaving, the i+1th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is defined as a bit group.
157, 20, 116, 115, 49, 178, 148, 152, 174, 130, 171, 81, 60, 146, 182, 72, 46, 22, 93, 101, 9, 55, 40, 163, 118, 30, 52, 181, 151, 31, 87, 117, 120, 82, 95, 190, 23, 36, 67, 62, 14, 167, 80, 27, 24, 43, 94, 0, 63, 5, 74, 78, 158, 88, 84, 109, 147, 112, 124, 110, 21, 47, 45, 68, 184, 70, 1, 66, 149, 105, 140, 170, 56, 98, 135, 61, 79, 123, 166, 185, 41, 108, 122, 92, 16, 26, 37, 177, 173, 113, 136, 89, 162, 85, 54, 39, 73, 58, 131, 134, 188, 127, 3, 164, 13, 132, 129, 179, 25, 18, 57, 32, 119, 111, 53, 155, 28, 107, 133, 144, 19, 160, 71, 186, 153, 103, 2, 12, 91, 106, 64, 175, 75, 189, 128, 142, 187, 76, 180, 34, 59, 169, 90, 11, 172, 97, 141, 38, 191, 17, 114, 126, 145, 83, 143, 125, 121, 10, 44, 137, 86, 29, 104, 154, 168, 65, 159, 15, 99, 35, 50, 48, 138, 96, 100, 102, 7, 42, 156, 8, 4, 69, 183, 51, 165, 6, 150, 77, 161, 33, 176, 139
are interleaved with each other. The parity check matrix initial value table that defines the parity check matrix is as described above.

In the fourth receiving device/method of the present technology, the arrangement of the LDPC codes after groupwise interleaving obtained from the data transmitted from the fourth transmitting device implementing the fourth transmission method is the original arrangement. be returned.

In the fifth transmission method/device of the present technology, LDPC encoding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 10/16, and the LDPC code is , group-wise interleaving is performed in which interleaving is performed in units of 360-bit bit groups. Then, the LDPC code is mapped to one of 64 signal points of 64QAM UC (Uniform Constellation) in units of 6 bits. In the groupwise interleaving, the i+1th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is defined as a bit group.
42, 168, 36, 37, 152, 118, 14, 83, 105, 131, 26, 120, 92, 130, 158, 132, 49, 72, 137, 100, 88, 24, 53, 142, 110, 102, 74, 188, 113, 121, 12, 173, 5, 126, 127, 3, 93, 46, 164, 109, 151, 2, 98, 153, 116, 89, 101, 136, 35, 80, 0, 133, 183, 162, 185, 56, 17, 87, 117, 184, 54, 70, 176, 91, 134, 51, 38, 73, 165, 99, 169, 43, 167, 86, 11, 144, 78, 58, 64, 13, 119, 33, 166, 6, 75, 31, 15, 28, 125, 148, 27, 114, 82, 45, 55, 191, 160, 115, 1, 69, 187, 122, 177, 32, 172, 52, 112, 171, 124, 180, 85, 150, 7, 57, 60, 94, 181, 29, 97, 128, 19, 149, 175, 50, 140, 10, 174, 68, 59, 39, 106, 44, 62, 71, 18, 107, 156, 159, 146, 48, 81, 111, 96, 103, 34, 161, 141, 154, 76, 61, 135, 20, 84, 77, 108, 23, 145, 182, 170, 139, 157, 47, 9, 63, 123, 138, 155, 79, 4, 30, 143, 25, 90, 66, 147, 186, 179, 129, 21, 65, 41, 95, 67, 22, 163, 190, 16, 8, 104, 189, 40, 178
are interleaved with each other. The parity check matrix initial value table that defines the parity check matrix is as described above.

In the fifth receiving device/method of the present technology, the arrangement of the LDPC codes after groupwise interleaving obtained from the data transmitted from the fifth transmitting device implementing the fifth transmission method is the original arrangement. be returned.

In the sixth transmission method/device of the present technology, LDPC encoding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 12/16, and the LDPC code is , group-wise interleaving is performed in which interleaving is performed in units of 360-bit bit groups. Then, the LDPC code is mapped to one of 64 signal points of 64QAM UC (Uniform Constellation) in units of 6 bits. In the groupwise interleaving, the i+1th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is defined as a bit group.
92, 132, 39, 44, 190, 21, 70, 146, 48, 13, 17, 187, 119, 43, 94, 157, 150, 98, 96, 47, 86, 63, 152, 158, 84, 170, 81, 7, 62, 191, 174, 99, 116, 10, 85, 113, 135, 28, 53, 122, 83, 141, 77, 23, 131, 4, 40, 168, 129, 109, 51, 130, 188, 147, 29, 50, 26, 78, 148, 164, 167, 103, 36, 134, 2, 177, 20, 123, 27, 90, 176, 5, 33, 133, 189, 138, 76, 41, 89, 35, 72, 139, 32, 73, 68, 67, 101, 166, 93, 54, 52, 42, 110, 59, 8, 179, 34, 171, 143, 137, 9, 126, 155, 108, 142, 120, 163, 12, 3, 75, 159, 107, 65, 128, 87, 6, 22, 57, 100, 24, 64, 106, 117, 19, 58, 95, 74, 180, 125, 136, 186, 154, 121, 161, 88, 37, 114, 102, 105, 160, 80, 185, 82, 124, 184, 15, 16, 18, 118, 173, 151, 11, 91, 79, 46, 140, 127, 1, 169, 0, 61, 66, 45, 162, 149, 115, 144, 30, 25, 175, 153, 183, 60, 38, 31, 111, 182, 49, 55, 145, 56, 181, 104, 14, 71, 178, 112, 172, 165, 69, 97, 156
are interleaved with each other. The parity check matrix initial value table that defines the parity check matrix is as described above.

In the sixth receiving device/method of the present technology, the arrangement of the LDPC codes after groupwise interleaving obtained from the data transmitted from the sixth transmitting device implementing the sixth transmission method is the original arrangement. be returned.

In the seventh transmission method/device of the present technology, LDPC encoding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 14/16, and the LDPC code is , group-wise interleaving is performed in which interleaving is performed in units of 360-bit bit groups. Then, the LDPC code is mapped to one of 64 signal points of 64QAM UC (Uniform Constellation) in units of 6 bits. In the groupwise interleaving, the i+1th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is defined as a bit group.
133, 96, 46, 148, 78, 109, 149, 161, 55, 39, 183, 54, 186, 73, 150, 180, 189, 190, 22, 135, 12, 80, 42, 130, 164, 70, 126, 107, 57, 67, 15, 157, 52, 88, 5, 23, 123, 66, 53, 147, 177, 60, 131, 108, 171, 191, 44, 140, 98, 154, 37, 118, 176, 92, 124, 138, 132, 167, 173, 13, 79, 32, 145, 14, 113, 30, 2, 0, 165, 182, 153, 24, 144, 87, 82, 75, 141, 89, 137, 33, 100, 106, 128, 168, 29, 36, 172, 11, 111, 68, 16, 10, 34, 188, 35, 160, 77, 83, 178, 58, 59, 7, 56, 110, 104, 61, 76, 85, 121, 93, 19, 134, 179, 155, 163, 115, 185, 125, 112, 71, 8, 119, 18, 47, 151, 26, 103, 122, 9, 170, 146, 99, 49, 72, 102, 31, 40, 43, 158, 142, 4, 69, 139, 28, 174, 101, 84, 129, 156, 74, 62, 91, 159, 41, 38, 45, 136, 169, 21, 51, 181, 97, 166, 175, 90, 27, 86, 65, 105, 143, 127, 17, 6, 116, 94, 117, 48, 50, 25, 64, 95, 63, 184, 152, 120, 1, 187, 162, 114, 3, 81, 20
are interleaved with each other. The parity check matrix initial value table that defines the parity check matrix is as described above.

In the seventh receiving device/method of the present technology, the arrangement of the LDPC codes after groupwise interleaving obtained from the data transmitted from the seventh transmitting device implementing the seventh transmission method is the original arrangement. be returned.

Note that the transmitting device and the receiving device may be independent devices or may be internal blocks forming one device.

According to the present technology, good communication quality can be ensured in data transmission using LDPC codes.

Note that the effects described here are not necessarily limited, and may be any of the effects described in this disclosure.

FIG. 3 is a diagram illustrating a parity check matrix H of an LDPC code. 3 is a flowchart illustrating a procedure for decoding an LDPC code. FIG. 3 is a diagram showing an example of a parity check matrix of an LDPC code. FIG. 3 is a diagram showing an example of a Tanner graph of a parity check matrix. FIG. 3 is a diagram illustrating an example of a variable node. FIG. 3 is a diagram showing an example of a check node. 1 is a diagram illustrating a configuration example of an embodiment of a transmission system to which the present technology is applied. 1 is a block diagram showing a configuration example of a transmitting device 11. FIG. 2 is a block diagram showing an example of the configuration of a bit interleaver 116. FIG. FIG. 3 is a diagram showing an example of a parity check matrix. FIG. 3 is a diagram showing an example of a parity matrix. FIG. 2 is a diagram illustrating a parity check matrix of an LDPC code specified in the DVB-T.2 standard. FIG. 2 is a diagram illustrating a parity check matrix of an LDPC code specified in the DVB-T.2 standard. FIG. 3 is a diagram showing an example of a Tanner graph for decoding an LDPC code. 3 is a diagram showing an example of a parity matrix H _T having a staircase structure and a Tanner graph corresponding to the parity matrix H _T. FIG. FIG. 3 is a diagram showing an example of a parity matrix H _T of a parity check matrix H corresponding to an LDPC code after parity interleaving. 3 is a flowchart illustrating an example of processing performed by a bit interleaver 116 and a mapper 117. 2 is a block diagram showing a configuration example of an LDPC encoder 115. FIG. 3 is a flowchart illustrating an example of processing by the LDPC encoder 115. FIG. 7 is a diagram showing an example of a parity check matrix initial value table with a coding rate of 1/4 and a code length of 16200. FIG. 3 is a diagram illustrating a method for obtaining a parity check matrix H from a parity check matrix initial value table. FIG. 3 is a diagram showing the structure of a parity check matrix. FIG. 3 is a diagram showing an example of a parity check matrix initial value table. FIG. 3 is a diagram illustrating an A matrix generated from a parity check matrix initial value table. FIG. 3 is a diagram illustrating parity interleaving of a B matrix. FIG. 3 is a diagram illustrating a C matrix generated from a parity check matrix initial value table. FIG. 3 is a diagram illustrating parity interleaving of a D matrix. FIG. 3 is a diagram showing a check matrix obtained by performing column permutation as parity deinterleaving to restore parity interleaving to the original check matrix. FIG. 7 is a diagram showing a transformed check matrix obtained by performing row permutation on the check matrix. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=2/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=3/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=3/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=4/16. FIG. 4 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=5/16. FIG. 4 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=5/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=6/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=6/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=7/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=7/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=8/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type A code with N=69120 bits and r=8/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=7/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=7/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=7/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=7/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=8/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=8/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=8/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=8/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=9/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=9/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=9/16. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=9/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=9/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=9/16. FIG. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=10/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=10/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=10/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=10/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=10/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=10/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=11/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=11/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=11/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=11/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=11/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=11/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=12/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=12/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=12/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=12/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=12/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=12/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=13/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=13/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=13/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=13/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=13/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=13/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=14/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=14/16. FIG. 7 is a diagram showing an example of a parity check matrix initial value table for a type B code with N=69120 bits and r=14/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=14/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=14/16. FIG. 7 is a diagram showing another example of a parity check matrix initial value table for a type B code with N=69120 bits and r=14/16. FIG. 4 is a diagram illustrating an example of a Tanner graph of an ensemble of degree sequences with column weights of 3 and row weights of 6. FIG. 3 is a diagram illustrating an example of a Tanner graph of a multi-edge type ensemble. FIG. 3 is a diagram illustrating a check matrix of type A method. FIG. 3 is a diagram illustrating a check matrix of type A method. FIG. 3 is a diagram illustrating a check matrix of type B method. FIG. 3 is a diagram illustrating a check matrix of type B method. FIG. 7 is a diagram showing an example of coordinates of UC signal points when the modulation method is QPSK. FIG. 3 is a diagram showing an example of coordinates of signal points of a 2D NUC when the modulation method is 16QAM. FIG. 7 is a diagram showing an example of coordinates of signal points of a 1D NUC when the modulation method is 1024QAM. 10 is a diagram showing the relationship between a 1024QAM symbol y and a complex real part Re(z _s ) and an imaginary part Im(z _s ) as the coordinates of a signal point z _s of a 1D NUC corresponding to the symbol y. FIG. FIG. 3 is a diagram showing an example of the coordinates _zq of a signal point in QPSK-UC. FIG. 3 is a diagram showing an example of the coordinates _zq of a signal point in QPSK-UC. FIG. 3 is a diagram showing an example of the coordinates _zq of a signal point of 16QAM-UC. FIG. 3 is a diagram showing an example of the coordinates _zq of a signal point of 16QAM-UC. FIG. 3 is a diagram showing an example of coordinates _zq of signal points of 64QAM-UC. FIG. 3 is a diagram showing an example of coordinates _zq of signal points of 64QAM-UC. FIG. 3 is a diagram showing an example of coordinates _zq of signal points of 256QAM-UC. FIG. 3 is a diagram showing an example of coordinates _zq of signal points of 256QAM-UC. FIG. 3 is a diagram showing an example of coordinates _zq of signal points of 1024QAM-UC. FIG. 3 is a diagram showing an example of coordinates _zq of signal points of 1024QAM-UC. FIG. 4 is a diagram showing an example of coordinates _zq of signal points of 4096QAM-UC. FIG. 4 is a diagram showing an example of coordinates _zq of signal points of 4096QAM-UC. 2 is a diagram illustrating block interleaving performed by a block interleaver 25. FIG. 2 is a diagram illustrating block interleaving performed by a block interleaver 25. FIG. 3 is a diagram illustrating group-wise interleaving performed by a group-wise interleaver 24. FIG. FIG. 3 is a diagram showing a first example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 7 is a diagram showing a second example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 7 is a diagram showing a third example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 7 is a diagram showing a fourth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 7 is a diagram showing a fifth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 7 is a diagram showing a sixth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 7 is a diagram showing a seventh example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing an eighth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 11 is a diagram showing a ninth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 7 is a diagram showing a tenth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing an eleventh example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a twelfth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 13 is a diagram showing a thirteenth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 14 is a diagram showing a fourteenth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a fifteenth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 16 is a diagram showing a 16th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 17 is a diagram showing a seventeenth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing an 18th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 11 is a diagram showing a nineteenth example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 20th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 21st example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 22nd example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 23rd example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 24th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 25th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 26th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 27th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 28th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 29th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 30th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 31st example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 32nd example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 33rd example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 34th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 35th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 36th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 37th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 38th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 39th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 40th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 41st example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 42nd example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 12 is a diagram showing a 43rd example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 14 is a diagram showing a 44th example of a GW pattern for an LDPC code with a code length N of 69120 bits. FIG. 14 is a diagram showing a 45th example of a GW pattern for an LDPC code with a code length N of 69120 bits. 1 is a block diagram showing a configuration example of a receiving device 12. FIG. 2 is a block diagram illustrating a configuration example of a bit deinterleaver 165. FIG. 3 is a flowchart illustrating an example of processing performed by a demapper 164, a bit deinterleaver 165, and an LDPC decoder 166. FIG. 3 is a diagram showing an example of a parity check matrix of an LDPC code. FIG. 7 is a diagram illustrating an example of a matrix (transformed check matrix) obtained by performing row permutation and column permutation on a check matrix. It is a figure which shows the example of the conversion check matrix divided|segmented into 5x5 units. FIG. 2 is a block diagram showing a configuration example of a decoding device that collectively performs P node operations. 3 is a block diagram showing a configuration example of an LDPC decoder 166. FIG. 5 is a diagram illustrating block deinterleaving performed by a block deinterleaver 54. FIG. 3 is a block diagram showing another example of the configuration of the bit deinterleaver 165. FIG. 1 is a block diagram showing a first configuration example of a receiving system to which a receiving device 12 can be applied. FIG. FIG. 2 is a block diagram showing a second configuration example of a receiving system to which the receiving device 12 can be applied. FIG. 3 is a block diagram showing a third configuration example of a receiving system to which the receiving device 12 can be applied. 1 is a block diagram showing a configuration example of an embodiment of a computer to which the present technology is applied.

Embodiments of the present technology will be described below, but before that, LDPC codes will be described.

<LDPC code>

Although the LDPC code is a linear code and does not necessarily have to be binary, it will be described here assuming that it is binary.

The biggest feature of LDPC codes is that the parity check matrix that defines the LDPC code is sparse. Here, a sparse matrix is a matrix in which the number of "1" elements in the matrix is very small (a matrix in which most elements are 0).

FIG. 1 is a diagram showing an example of a parity check matrix H of an LDPC code.

In the check matrix H in Figure 1, the weight of each column (column weight) (number of "1") (weight) is "3", and the weight of each row (row weight) is "6". .

In encoding using LDPC codes (LDPC encoding), for example, a generator matrix G is generated based on a parity check matrix H, and by multiplying binary information bits by this generator matrix G, a code word (LDPC code) is generated. ) is generated.

Specifically, an encoding device that performs LDPC encoding first calculates a generation matrix G that satisfies the expression GH ^T =0 between the check matrix H and the transposed matrix H ^T . Here, when the generator matrix G is a K×N matrix, the encoding device multiplies the generator matrix G by a bit string (vector u) of information bits consisting of K bits, and encodes the information bits consisting of N bits. Generate word c(=uG). The code word (LDPC code) generated by this encoding device is received at the receiving side via a predetermined communication channel.

Decoding of LDPC codes is an algorithm proposed by Gallager called probabilistic decoding, which uses variable nodes (also called message nodes) and check nodes. This can be done using a message passing algorithm using belief propagation on a so-called Tanner graph. Hereinafter, the variable node and the check node will also be simply referred to as a node.

FIG. 2 is a flowchart showing the procedure for decoding an LDPC code.

In the following, we will use a real value (received LLR ) is also called the received value u _0i . Also, let u _j be the message output from the check node, and v _i be the message output from the variable node.

First, in decoding the LDPC code, as shown in FIG. 2, in step S11, the LDPC code is received, the message (check node message) u _j is initialized to "0", and the counter A variable k that takes an integer is initialized to "0", and the process advances to step S12. In step S12, a message (variable node message) v _i is obtained by performing the calculation (variable node calculation) shown in equation (1) based on the received value u _0i obtained by receiving the LDPC code, and further, Based on this message v _i , message u _j is obtained by performing the calculation (check node calculation) shown in equation (2).

・・・（１）

...(1)

・・・（２）

...(2)

Here, d _v and d _c in equations (1) and (2) can be arbitrarily selected and represent the number of "1"s in the vertical direction (columns) and horizontal direction (rows) of the parity check matrix H, respectively. This is the parameter to be used. For example, in the case of an LDPC code ((3,6)LDPC code) for the parity check matrix H with a column weight of 3 and a row weight of 6 as shown in Figure 1, d _v = 3, d _c = 6. Become.

Note that in the variable node operation in equation (1) and the check node operation in equation (2), the message input from the edge (the line connecting the variable node and the check node) to which the message is to be output, respectively. is not subject to calculation, so the range of calculation is 1 to d _v -1 or 1 to d _c -1. In addition, the check node operation in equation (2) actually involves creating a table in advance of the function R(v ₁ , v ₂ ) shown in equation (3), which is defined by one output for two inputs v ₁ and v ₂ . This is done by using this continuously (recursively) as shown in equation (4).

・・・（３）

...(3)

・・・（４）

...(4)

In step S12, the variable k is further incremented by "1", and the process proceeds to step S13. In step S13, it is determined whether the variable k is larger than a predetermined number C of repeated decoding. If it is determined in step S13 that the variable k is not larger than C, the process returns to step S12, and the same process is repeated thereafter.

If it is determined in step S13 that the variable k is larger than C, the process proceeds to step S14, where the message v _i as the decoding result to be finally output is obtained by performing the operation shown in equation (5). is output, and the LDPC code decoding process ends.

・・・（５）

...(5)

Here, the calculation in equation (5) is different from the variable node calculation in equation (1), and is performed using messages u _j from all branches connected to the variable node.

FIG. 3 is a diagram showing an example of a parity check matrix H of a (3,6)LDPC code (coding rate 1/2, code length 12).

In the parity check matrix H in FIG. 3, the column weight is 3 and the row weight is 6, as in FIG. 1.

FIG. 4 is a diagram showing a Tanner graph of the parity check matrix H in FIG. 3.

Here, in FIG. 4, a check node is represented by a plus "+", and a variable node is represented by an equal "=". Check nodes and variable nodes correspond to rows and columns of parity check matrix H, respectively. The connection between the check node and the variable node is an edge and corresponds to "1" in the element of the parity check matrix.

That is, if the element in the jth row and ith column of the parity check matrix is 1, in FIG. +" nodes) are connected by branches. An edge represents that a code bit corresponding to a variable node has a constraint condition corresponding to a check node.

In the Sum Product Algorithm, which is a method for decoding LDPC codes, variable node operations and check node operations are repeatedly performed.

FIG. 5 is a diagram illustrating variable node operations performed on variable nodes.

In the variable node, the message v _i corresponding to the branch to be calculated is the variable node of formula (1) using the messages u ₁ and u ₂ from the remaining branches connected to the variable node and the received value u _0i . Determined by calculation. Messages corresponding to other branches are similarly sought.

FIG. 6 is a diagram illustrating check node operations performed at check nodes.

Here, the check node operation in equation (2) uses the relationship of equation a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b), It can be rewritten as equation (6). However, sign(x) is 1 when x≧0, and -1 when x<0.

・・・（６）

...(6)

When x≧0, if we define the function φ(x) as the formula φ(x)=ln(tanh(x/2)), then the formula φ ^-1 (x)=2tanh ^-1 (e ^-x ) holds true. , Equation (6) can be transformed into Equation (7).

・・・（７）

...(7)

At the check node, the check node operation of equation (2) is performed according to equation (7).

That is, at the check node, as shown in FIG. 6, the message u _j corresponding to the branch to be calculated is the message v ₁ , v ₂ , v ₃ , v ₄ , v from the remaining branches connected to the check node. It is obtained by the check node operation of equation (7) using ₅ . Messages corresponding to other branches are similarly sought.

Note that the function φ(x) in equation (7) can be expressed as the equation φ(x)=ln((e ^x +1)/(e ^x -1)), and when x>0, φ(x )=φ ^-1 (x). When implementing the functions φ(x) and φ ⁻¹ (x) in hardware, they may be implemented using a LUT (Look Up Table), but both are the same LUT.

<Example of configuration of a transmission system applying this technology>

Figure 7 shows an example of a transmission system to which this technology is applied (a system refers to a logical collection of multiple devices, and it does not matter whether the devices of each configuration are in the same casing). FIG. 1 is a diagram showing a configuration example of an embodiment.

In FIG. 7, the transmission system includes a transmitting device 11 and a receiving device 12.

The transmitting device 11 transmits (broadcasts) (transmits) television broadcast programs, etc., for example. That is, the transmitting device 11 encodes the target data to be transmitted, such as image data and audio data as a program, into an LDPC code, and transmits the data through, for example, a satellite line, terrestrial wave, cable (wired line), etc. It is transmitted via the communication path 13.

The receiving device 12 receives the LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into target data, and outputs it.

Here, it is known that the LDPC code used in the transmission system of FIG. 7 exhibits extremely high performance in an AWGN (Additive White Gaussian Noise) communication channel.

On the other hand, in the communication path 13, burst errors and erasures may occur. For example, especially when the communication channel 13 is terrestrial, in an OFDM (Orthogonal Frequency Division Multiplexing) system, the D/U (Desired to Undesired Ratio) is 0 dB (Undesired = echo power is equal to Desired = main path power) ), the power of a specific symbol may become 0 depending on the delay of the echo (path other than the main path).

Also, even in flutter (a communication channel where the delay is 0 and echoes multiplied by the Doppler frequency are added), if the D/U is 0 dB, the OFDM signal at a specific time depends on the Doppler frequency. There are cases where the power of the entire symbol becomes 0 (erasure).

Furthermore, burst errors may occur due to the condition of the wiring from the receiving unit (not shown) such as an antenna that receives signals from the transmitting device 11 on the receiving device 12 side to the receiving device 12 or the instability of the power source of the receiving device 12. may occur.

On the other hand, in the decoding of an LDPC code, as shown in _FIG . Since the variable node operation of equation (1) that involves addition is performed, if an error occurs in the sign bit used for the variable node operation, the accuracy of the required message will decrease.

In decoding of an LDPC code, the check node operation of equation (7) is performed at the check node using the message obtained from the variable nodes connected to the check node. When the number of check nodes in which the code bits of the LDPC code corresponding to the LDPC code simultaneously become errors (including erasures) increases, the decoding performance deteriorates.

That is, for example, if two or more variable nodes connected to the check node become erasures at the same time, a check node sends a message to all variable nodes in which the probability that the value is 0 is equal to the probability that the value is 1. return. In this case, the check nodes that return messages with equal probability do not contribute to one decoding process (one set of variable node operations and check node operations), and as a result, the decoding process requires a large number of repetitions. As a result, the decoding performance deteriorates, and furthermore, the power consumption of the receiving device 12 that decodes the LDPC code increases.

Therefore, in the transmission system shown in FIG. 7, it is possible to improve resistance to burst errors and erasures while maintaining the performance of the AWGN communication path (AWGN channel).

<Example of configuration of transmitting device 11>

FIG. 8 is a block diagram showing a configuration example of the transmitting device 11 of FIG. 7. As shown in FIG.

In the transmitting device 11, one or more input streams as target data are supplied to a mode adaptation/multiplexer 111.

The mode adaptation/multiplexer 111 performs processing such as mode selection and multiplexing of one or more input streams supplied thereto as necessary, and supplies the resulting data to a padder 112. .

The padder 112 performs necessary zero padding (null insertion) on the data from the mode adaptation/multiplexer 111 and supplies the resulting data to the BB scrambler 113.

The BB scrambler 113 performs BB scrambling (Base-Band Scrambling) on the data from the padder 112 and supplies the resulting data to the BCH encoder 114.

BCH encoder 114 performs BCH encoding on the data from BB scrambler 113, and supplies the resulting data to LDPC encoder 115 as LDPC target data to be subjected to LDPC encoding.

The LDPC encoder 115 performs LDPC encoding on the LDPC target data from the BCH encoder 114 according to, for example, a parity check matrix in which a parity matrix, which is a part corresponding to the parity bits of the LDPC code, has a dual diagonal structure. and outputs an LDPC code that uses the LDPC target data as information bits.

That is, the LDPC encoder 115 converts the LDPC target data into a check matrix defined in a predetermined standard such as DVB-S.2, DVB-T.2, DVB-C.2, ATSC3.0, etc. Corresponding) LDPC code and other LDPC codes are performed, and the resulting LDPC code is output.

Here, the LDPC code specified in the DVB-S.2 and ATSC3.0 standards, and the LDPC code scheduled to be adopted in ATSC3.0, is an IRA (Irregular Repeat Accumulate) code, and the check matrix of the LDPC code is (Part or all) of the parity matrix in has a staircase structure. The parity matrix and staircase structure will be described later. Regarding IRA codes, see, for example, "Irregular Repeat-Accumulate Codes," H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. Listed in 2000.

The LDPC code output from the LDPC encoder 115 is supplied to a bit interleaver 116.

The bit interleaver 116 performs bit interleaving, which will be described later, on the LDPC code from the LDPC encoder 115 and supplies the bit interleaved LDPC code to a mapper 117.

The mapper 117 maps the LDPC code from the bit interleaver 116 to a signal point representing one symbol of orthogonal modulation in units of code bits (symbol units) of one or more bits of the LDPC code. value modulation).

That is, the mapper 117 maps the LDPC code from the bit interleaver 116 onto a constellation that is an IQ plane defined by an I axis representing an I component that is in phase with the carrier wave, and a Q axis representing a Q component orthogonal to the carrier wave. Orthogonal modulation is performed by mapping to the signal points determined by the modulation method that performs orthogonal modulation of the LDPC code.

When the number of constellation signal points used in the modulation method of orthogonal modulation performed by the mapper 117 is 2 ^m , the mapper 117 uses the m code bits of the LDPC code as a symbol (1 symbol). The LDPC code from the bit interleaver 116 is mapped, symbol by symbol, to a signal point representing a symbol among the 2 ^m signal points.

Here, the modulation method of the orthogonal modulation performed by the mapper 117 includes, for example, the modulation method specified in the DVB-S.2 and ATSC3.0 standards, and other modulation methods, such as BPSK (Binary Phase Shift Keying), QPSK(Quadrature Phase Shift Keying), 8PSK(Phase-Shift Keying), 16APSK(Amplitude Phase-Shift Keying), 32APSK, 16QAM(Quadrature Amplitude Modulation), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, There are 4PAM (Pulse Amplitude Modulation), etc. Which modulation method is used for orthogonal modulation in the mapper 117 is set in advance, for example, according to an operation by the operator of the transmitting device 11.

Data obtained by processing in the mapper 117 (mapping result of mapping symbols to signal points) is supplied to a time interleaver 118.

The time interleaver 118 performs time interleaving (interleaving in the time direction) on the data from the mapper 117 on a symbol-by-symbol basis, and transfers the resulting data to a SISO/MISO encoder (SISO/MISO (Single Input Single Output/Multiple Input Single Output/Multiple Input Single Output) encoder) 119.

The SISO/MISO encoder 119 performs space-time encoding on the data from the time interleaver 118 and supplies the data to a frequency interleaver 120 .

The frequency interleaver 120 performs frequency interleaving (interleaving in the frequency direction) on the data from the SISO/MISO encoder 119 on a symbol-by-symbol basis, and supplies the data to a frame builder/resource allocation unit (Frame Builder & Resource Allocation) 131 .

On the other hand, the BCH encoder 121 is supplied with control data (signalling) for transmission control such as BB signaling (Base Band Signalling) (BB Header).

The BCH encoder 121 BCH-encodes the control data supplied thereto in the same manner as the BCH encoder 114, and supplies the resulting data to the LDPC encoder 122.

The LDPC encoder 122 performs LDPC encoding on the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115, and supplies the resulting LDPC code to the mapper 123.

Similar to the mapper 117, the mapper 123 maps the LDPC code from the LDPC encoder 122 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol units) of the LDPC code. performs orthogonal modulation, and the resulting data is supplied to the frequency interleaver 124.

Similar to the frequency interleaver 120, the frequency interleaver 124 performs frequency interleaving on the data from the mapper 123 in units of symbols, and supplies the data to the frame builder/resource allocation unit 131.

The frame builder/resource allocation unit 131 inserts pilot symbols into necessary positions of the data (symbols) from the frequency interleavers 120 and 124, and from the resulting data (symbols), a predetermined A frame (for example, a PL (Physical Layer) frame, a T2 frame, a C2 frame, etc.) consisting of several symbols is configured and supplied to an OFDM generation section (OFDM generation) 132.

The OFDM generation unit 132 generates an OFDM signal corresponding to the frame from the frame from the frame builder/resource allocation unit 131, and transmits it via the communication path 13 (FIG. 7).

Note that the transmitting device 11 may be configured without providing some of the blocks illustrated in FIG. 8, such as the time interleaver 118, the SISO/MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, for example. I can do it.

<Configuration example of bit interleaver 116>

FIG. 9 is a block diagram showing a configuration example of the bit interleaver 116 of FIG. 8.

The bit interleaver 116 has a function of interleaving data, and is composed of a parity interleaver 23, a group-wise interleaver 24, and a block interleaver 25.

The parity interleaver 23 performs parity interleaving to interleave the parity bits of the LDPC code from the LDPC encoder 115 at other parity bit positions, and supplies the LDPC code after parity interleaving to the groupwise interleaver 24 .

Groupwise interleaver 24 performs groupwise interleaving on the LDPC code from parity interleaver 23 and supplies the LDPC code after groupwise interleaving to block interleaver 25 .

Here, in group-wise interleaving, the LDPC code for one code is divided into 360-bit units equal to the unit size P, which will be described later, from the beginning, and the 360 bits of one division are treated as a bit group by the parity interleaver 23. The LDPC codes from are interleaved on a bit group basis.

When groupwise interleaving is performed, the error rate can be improved compared to when groupwise interleaving is not performed, and as a result, good communication quality can be ensured in data transmission.

The block interleaver 25 performs block interleaving to demultiplex the LDPC codes from the groupwise interleaver 24, thereby converting one code's worth of LDPC codes into m-bit symbols, which are the units of mapping. and supplies it to the mapper 117 (FIG. 8).

Here, in block interleaving, for example, the number of columns as storage areas that store a predetermined number of bits in the column (vertical) direction is equal to the number of symbol bits m in the row (horizontal) direction. The LDPC code from the groupwise interleaver 24 is written in the column direction and read out in the row direction in the storage area arranged in rows, thereby symbolizing the LDPC code into an m-bit symbol.

<LDPC code check matrix>

FIG. 10 is a diagram showing an example of a parity check matrix H used for LDPC encoding by the LDPC encoder 115 of FIG. 8.

The parity check matrix H has an LDGM (Low-Density Generation Matrix) structure, and includes an information matrix H _A corresponding to the information bits among the code bits of the LDPC code, and a parity matrix H _T corresponding to the parity bits. Accordingly, it can be expressed by the formula H = [H _A | H _T ] (a matrix in which the elements of the information matrix H _A are the left elements and the elements of the parity matrix H _T are the right elements).

Here, the number of information bits and the number of parity bits among the code bits of one LDPC code (one code word) are respectively referred to as information length K and parity length M. The number of code bits of the LDPC code (code word) is called code length N (=K+M).

The information length K and parity length M for an LDPC code with a certain code length N are determined by the coding rate. In addition, the parity check matrix H is a matrix with M×N rows and columns (a matrix with M rows and N columns). Then, the information matrix H _A becomes an M×K matrix, and the parity matrix H _T becomes an M×M matrix.

FIG. 11 is a diagram showing an example of the parity matrix H _T of the parity check matrix H used for LDPC encoding by the LDPC encoder 115 of FIG.

As the parity matrix H _T of the check matrix H used for LDPC encoding in the LDPC encoder 115, for example, a parity matrix H _T similar to the check matrix H of the LDPC code specified in standards such as DVB-T.2 can be used. Can be adopted.

As shown in FIG. 11, the parity matrix H _T of the parity check matrix H of the LDPC code specified in standards such as DVB-T.2 is a lower bidiagonal matrix in which the elements of 1 are arranged in a stepwise manner. matrix). The row weight of the parity matrix H _T is 1 for the first row and 2 for all remaining rows. Further, the column weight is 1 for the last column and 2 for all remaining columns.

As described above, the LDPC code of the check matrix H in which the parity matrix H _T has a stepped structure can be easily generated using the check matrix H.

That is, an LDPC code (one code word) is represented by a row vector c, and a column vector obtained by transposing the row vector is represented by c ^T. Also, of the row vector c, which is an LDPC code, the information bit part is represented by a row vector A, and the parity bit part is represented by a row vector T.

In this case, the row vector c is defined by the row vector A as the information bit and the row vector T as the parity bit. can be expressed as a row vector with the elements on the right as the elements on the right.

The parity check matrix H and the row vector c=[A|T] as an LDPC code must satisfy the formula Hc ^T =0, and the row vector c=[A|T] that satisfies the formula Hc ^T =0 is When the parity matrix H T of the parity check matrix H = [H _A |H _T ] has the stepped structure shown in FIG. 11, the row vector _T as the constituent parity ^bits is By sequentially setting the elements of each row to 0 starting from the first row element of the column vector Hc ^T , it is possible to obtain the values sequentially (in order).

FIG. 12 is a diagram illustrating a parity check matrix H of an LDPC code specified in standards such as DVB-T.2.

For the KX columns from the first column of the parity check matrix H of the LDPC code specified in standards such as DVB-T.2, the column weight is set to X, and for the subsequent K3 columns, the column weight is set to 3, and then The column weight is 2 for column M-1, and the column weight is 1 for the last column.

Here, KX+K3+M-1+1 is equal to code length N.

FIG. 13 is a diagram showing the number of columns KX, K3, and M and the column weight X for each coding rate r of the LDPC code specified in standards such as DVB-T.2.

Standards such as DVB-T.2 specify LDPC codes with code lengths N of 64,800 bits and 16,200 bits.

For the LDPC code with a code length N of 64800 bits, 11 coding rates (nominal rates) 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/ 4, 4/5, 5/6, 8/9, and 9/10 are defined, and for an LDPC code with a code length N of 16200 bits, the 10 coding rates are 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are specified.

Hereinafter, the code length N of 64800 bits will also be referred to as 64k bits, and the code length N of 16200 bits will also be referred to as 16k bits.

Regarding LDPC codes, code bits that correspond to columns with higher column weights in parity check matrix H tend to have lower error rates.

In the parity check matrix H specified in standards such as DVB-T.2 shown in FIGS. 12 and 13, the column weight tends to be larger as the columns are closer to the head (on the left side). Regarding the LDPC code corresponding to H, the code bits at the beginning tend to be more resistant to errors (resistance to errors), and the code bits at the end tend to be less resistant to errors.

<Parity interleave>

Parity interleaving by the parity interleaver 23 of FIG. 9 will be described with reference to FIGS. 14 to 16.

FIG. 14 is a diagram illustrating an example of (part of) a Tanner graph of a parity check matrix of an LDPC code.

As shown in Figure 14, when a check node causes an error such as erasure in two or more of the variable nodes (corresponding code bits) connected to the check node at the same time, all the variable nodes connected to the check node Returns a message to the variable node in which the probability that the value is 0 is equal to the probability that the value is 1. Therefore, if multiple variable nodes connected to the same check node become erasures or the like at the same time, decoding performance deteriorates.

By the way, the LDPC code output by the LDPC encoder 115 in FIG. 8 is an IRA code similar to the LDPC code specified in standards such as DVB-T.2, and the parity matrix H _T of the parity check matrix H is , as shown in FIG. 11, has a staircase structure.

FIG. 15 is a diagram showing an example of a parity matrix H _T having a step-like structure as shown in FIG. 11, and a Tanner graph corresponding to the parity matrix H _T.

15A shows an example of a parity matrix H _T having a staircase structure, and FIG. 15B shows a Tanner graph corresponding to the parity matrix H _T of FIG. 15A.

In the parity matrix H _T having a staircase structure, elements of 1 are adjacent in each row (except for the first row). Therefore, in the Tanner graph of the parity matrix H _T , two adjacent variable nodes corresponding to the columns of two adjacent elements where the value of the parity matrix H _T is 1 are connected to the same check node. There is.

Therefore, if the parity bits corresponding to the two adjacent variable nodes mentioned above become errors at the same time due to a burst error or erasure, the two variable nodes corresponding to the two errored parity bits (using parity bits) A check node connected to a variable node that requests a message returns a message with an equal probability of being 0 and 1 to the variable node connected to that check node, so the decoding performance is low. to degrade. As the burst length (the number of parity bits that result in consecutive errors) increases, the number of check nodes that return messages with equal probability increases, and the decoding performance further deteriorates.

Therefore, the parity interleaver 23 (FIG. 9) performs parity interleaving in which the parity bit of the LDPC code from the LDPC encoder 115 is interleaved at the position of other parity bits in order to prevent the deterioration of the decoding performance described above. .

FIG. 16 is a diagram showing the parity matrix H _T of the parity check matrix H corresponding to the LDPC code after parity interleaving performed by the parity interleaver 23 of FIG.

Here, the information matrix H _A of the parity check matrix H corresponding to the LDPC code output by the LDPC encoder 115 is the same as the information matrix of the parity check matrix H corresponding to the LDPC code specified in standards such as DVB-T.2. It has a circular structure.

A cyclic structure is a structure in which one column corresponds to a cyclic shift of another column. For example, for each P column, the position of 1 in each row of that P column is the first position of that P column. It also includes a structure in which the column is cyclically shifted in the column direction by a predetermined value, such as a value proportional to the value q obtained by dividing the parity length M. Hereinafter, the P column in the cyclic structure will be referred to as the unit size.

As explained in Figures 12 and 13, there are two types of LDPC codes specified in standards such as DVB-T.2, with code length N of 64800 bits and 16200 bits. For both of the two types of LDPC codes, the unit size P is defined as 360, which is one of the divisors of the parity length M excluding 1 and M.

Further, the parity length M is a value other than a prime number expressed by the formula M=q×P=q×360 using a value q that varies depending on the coding rate. Therefore, like the unit size P, the value q is also one of the divisors of the parity length M excluding 1 and M, and the parity length M is divided by the unit size P. (The product of P and q, which are divisors of parity length M, is the parity length M.)

As mentioned above, the parity interleaver 23 uses an N-bit LDPC as parity interleaving, where the information length is K, x is an integer between 0 and less than P, and y is an integer between 0 and less than q. Of the code bits of the code, the K+qx+y+1-th code bit is interleaved at the position of the K+Py+x+1-th code bit.

The K+qx+y+1st sign bit and the K+Py+x+1st sign bit are both sign bits after the K+1st, so they are parity bits, and therefore parity bits. According to interleaving, the position of the parity bit of the LDPC code is moved.

According to such parity interleaving, variable nodes (corresponding parity bits) connected to the same check node are separated by unit size P, that is, 360 bits in this case, so the burst length is less than 360 bits. In this case, it is possible to avoid a situation where a plurality of variable nodes connected to the same check node have errors at the same time, and as a result, resistance to burst errors can be improved.

Note that the LDPC code after parity interleaving in which the K+qx+y+1st code bit is interleaved at the position of the K+Py+x+1th code bit is the K+qx+ It matches the LDPC code of a check matrix (hereinafter also referred to as a transformed check matrix) obtained by column permutation in which the y+1st column is replaced with the K+Py+x+1st column.

Furthermore, as shown in FIG. 16, a pseudo-cyclic structure having P columns (360 columns in FIG. 16) as a unit appears in the parity matrix of the conversion check matrix.

Here, the pseudo-cyclic structure means a structure in which all but one part is a cyclic structure.

The conversion check matrix obtained by performing column permutation corresponding to parity interleaving on the check matrix of the LDPC code specified in standards such as DVB-T.2 is the 360 rows in the upper right corner of the conversion check matrix × The 360-column part (shift matrix described later) is missing one element of 1 (it becomes an element of 0), and in that point, it is not a (complete) cyclic structure, but a pseudo-cyclic structure. ing.

The conversion check matrix for the LDPC code check matrix output by the LDPC encoder 115 has a pseudo-cyclic structure, for example, similar to the conversion check matrix for the LDPC code check matrix specified in standards such as DVB-T.2. ing.

Note that the transformation check matrix in FIG. 16 includes column permutation corresponding to parity interleaving with respect to the original check matrix H, as well as row permutation so that the transformation check matrix is composed of constituent matrices, which will be described later. (Row permutation) has also been applied to the matrix.

FIG. 17 is a flowchart illustrating the processing performed by the LDPC encoder 115, bit interleaver 116, and mapper 117 in FIG. 8.

The LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, and in step S101 encodes the LDPC target data into an LDPC code, and supplies the LDPC code to the bit interleaver 116. , the process proceeds to step S102.

In step S102, the bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115, supplies symbols obtained by the bit interleaving to the mapper 117, and the process proceeds to step S103.

That is, in step S102, the parity interleaver 23 in the bit interleaver 116 (FIG. 9) performs parity interleaving on the LDPC code from the LDPC encoder 115, and converts the parity-interleaved LDPC code into a group-wise interleaver. It is supplied to the lever 24.

The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23 and supplies it to the block interleaver 25 .

The block interleaver 25 performs block interleaving on the LDPC code after group-wise interleaving by the group-wise interleaver 24, and supplies the resulting m-bit symbol to the mapper 117.

In step S103, the mapper 117 performs orthogonal modulation by mapping the symbol from the block interleaver 25 to one of 2 ^m signal points determined by the orthogonal modulation method performed by the mapper 117, and obtains the resultant The data is provided to time interleaver 118.

As described above, by performing parity interleaving and groupwise interleaving, it is possible to improve the error rate when multiple code bits of an LDPC code are transmitted as one symbol.

Here, in FIG. 9, for convenience of explanation, the parity interleaver 23, which is a block that performs parity interleaving, and the group-wise interleaver 24, which is a block that performs group-wise interleaving, are configured separately. , the parity interleaver 23 and the groupwise interleaver 24 can be configured integrally.

In other words, both parity interleaving and groupwise interleaving can be performed by writing and reading code bits to and from memory, and the address where the code bits are written (write address) is set to the address where the code bits are read. (read address).

Therefore, if you find a matrix obtained by multiplying a matrix representing parity interleaving and a matrix representing groupwise interleaving, you can perform parity interleaving by converting the sign bits using these matrices, and then A result of groupwise interleaving of the LDPC code after parity interleaving can be obtained.

Further, in addition to the parity interleaver 23 and the groupwise interleaver 24, the block interleaver 25 can also be configured integrally.

That is, the block interleaving performed by the block interleaver 25 can also be expressed by a matrix that converts a write address of a memory storing an LDPC code into a read address.

Therefore, if you obtain a matrix obtained by multiplying a matrix representing parity interleaving, a matrix representing groupwise interleaving, and a matrix representing block interleaving, you can use these matrices to perform parity interleaving, groupwise interleaving, and block interleaving. Interleaving can be performed all at once.

Note that one or the amount of parity interleaving and groupwise interleaving may not be performed.

<Configuration example of LDPC encoder 115>

FIG. 18 is a block diagram showing a configuration example of the LDPC encoder 115 of FIG. 8.

Note that the LDPC encoder 122 in FIG. 8 is also configured in a similar manner.

As explained with reference to FIGS. 12 and 13, standards such as DVB-T.2 define two LDPC codes of code length N: 64,800 bits and 16,200 bits.

For the LDPC code with a code length N of 64800 bits, there are 11 coding rates: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/ 5, 5/6, 8/9, and 9/10 are specified, and for the LDPC code with a code length N of 16200 bits, the 10 coding rates are 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined (Figures 12 and 13).

For example, the LDPC encoder 115 performs encoding (error correction encoding) using an LDPC code of each encoding rate with a code length N of 64800 bits or 16200 bits for each code length N and each encoding rate. This can be done according to the prepared parity check matrix H.

In addition, the LDPC encoder 115 can perform LDPC encoding according to the parity check matrix H of an LDPC code with an arbitrary code length N and an arbitrary coding rate r.

The LDPC encoder 115 includes an encoding processing section 601 and a storage section 602.

The encoding processing section 601 includes a coding rate setting section 611, an initial value table reading section 612, a parity check matrix generation section 613, an information bit reading section 614, an encoding parity calculation section 615, and a control section 616. The LDPC target data supplied to the bit interleaver 115 is subjected to LDPC encoding, and the resulting LDPC code is supplied to the bit interleaver 116 (FIG. 8).

That is, the coding rate setting unit 611 sets the code length N and coding rate r of the LDPC code, and other specific information for specifying the LDPC code, for example, in response to an operator's operation or the like.

Initial value table reading unit 612 reads from storage unit 602 a parity check matrix initial value table, which will be described later, that represents the parity check matrix of the LDPC code specified by the specific information set by coding rate setting unit 611.

Parity check matrix generation unit 613 generates parity check matrix H based on the parity check matrix initial value table read by initial value table reading unit 612, and stores it in storage unit 602. For example, the parity check matrix generation unit 613 generates the information matrix _H A parity check matrix H is generated by arranging elements of 1 in the column direction at a period of every 360 columns (unit size P), and stored in the storage unit 602.

The information bit reading unit 614 reads (extracts) information bits corresponding to the information length K from the LDPC target data supplied to the LDPC encoder 115.

Encoding parity calculation unit 615 reads parity check matrix H generated by parity check matrix generation unit 613 from storage unit 602, and uses the parity check matrix H to set parity bits for the information bits read by information bit reading unit 614 to predetermined values. A code word (LDPC code) is generated by calculating based on the formula.

The control unit 616 controls each block that constitutes the encoding processing unit 601.

The storage unit 602 stores, for example, a plurality of parity check matrix initial value tables corresponding to a plurality of coding rates, etc. shown in FIGS. 12 and 13 for each code length N such as 64800 bits and 16200 bits. has been done. Furthermore, the storage unit 602 temporarily stores data necessary for processing by the encoding processing unit 601.

FIG. 19 is a flowchart illustrating an example of processing by the LDPC encoder 115 of FIG. 18.

In step S201, the coding rate setting unit 611 sets the code length N and coding rate r for performing LDPC encoding, and other specific information for specifying the LDPC code.

In step S202, the initial value table reading unit 612 reads a predetermined parity check matrix initial value table specified by the code length N and the coding rate r as specific information set by the coding rate setting unit 611. , read from the storage unit 602.

In step S203, the parity check matrix generation unit 613 uses the parity check matrix initial value table read out from the storage unit 602 by the initial value table reading unit 612 to generate the code length N and the coding rate set by the coding rate setting unit 611. A parity check matrix H of the LDPC code of r is obtained (generated) and supplied to the storage unit 602 for storage.

In step S204, the information bit reading unit 614 extracts the information length K (=N ×r) information bits are read out, and the parity check matrix H obtained by the parity check matrix generation unit 613 is read out from the storage unit 602 and supplied to the encoding parity calculation unit 615.

In step S205, the encoded parity calculation unit 615 uses the information bits from the information bit reading unit 614 and the parity check matrix H to sequentially calculate the parity bits of the code word c that satisfy equation (8).

Hc ^T = 0
...(8)

In equation (8), c represents a row vector as a code word (LDPC code), and c ^T represents the transposition of the row vector c.

Here, as mentioned above, when the information bit part of the row vector c as an LDPC code (one code word) is represented by the row vector A, and the parity bit part is represented by the row vector T, The row vector c can be expressed by the formula c = [A|T] using the row vector A as the information bit and the row vector T as the parity bit.

The check matrix H and the row vector c=[A|T] as an LDPC code must satisfy the formula Hc ^T =0, and the row vector c=[A|T] that satisfies the formula Hc ^T =0 When the parity matrix H T of the parity check matrix H = [H _A |H _T ] has the staircase structure shown in FIG. 11, the row vector _T as the constituent parity ^bits is It can be obtained sequentially by sequentially setting the elements of each row to 0 starting from the first row element of the column vector Hc ^T.

The encoded parity calculation unit 615 obtains a parity bit T for the information bit A from the information bit reading unit 614, and calculates a code word c = [A|T] expressed by the information bit A and the parity bit T. is output as the LDPC encoding result of information bit A.

After that, in step S206, the control unit 616 determines whether to end the LDPC encoding. In step S206, if it is determined that the LDPC encoding is not finished, that is, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204), and the following steps are performed. The processes of S201 (or steps S204) to S206 are repeated.

Further, if it is determined in step S206 that LDPC encoding is to be terminated, that is, for example, if there is no LDPC target data to be LDPC encoded, the LDPC encoder 115 terminates the process.

Regarding the LDPC encoder 115, check matrix initial value tables (representing check matrices) of LDPC codes with various code lengths N and coding rates r can be prepared in advance. The LDPC encoder 115 can perform LDPC encoding into LDPC codes with various code lengths N and coding rates r using a parity check matrix H generated from a parity check matrix initial value table prepared in advance.

<Example of check matrix initial value table>

For example, the parity check matrix initial value table is an information matrix H _A ( This is a table that represents the position of one element in FIG. 10) for each 360 columns (unit size P), and is created in advance for each parity check matrix H of each code length N and each coding rate r.

That is, the parity check matrix initial value table represents at least the position of one element of the information matrix H _A every 360 columns (unit size P).

In addition, the check matrix H includes a check matrix in which the entire parity matrix H _T has a staircase structure, a part of the parity matrix H _T in which the parity matrix H T has a staircase structure, and the remaining part is a diagonal matrix (unit matrix ) is the check matrix.

Hereinafter, the method of representing a parity check matrix initial value table representing a parity check matrix in which a part of the parity matrix H _T has a staircase structure and the remaining part has a diagonal matrix is also referred to as a type A method. Furthermore, the method of representing a parity check matrix initial value table representing a parity check matrix in which all of the parity matrices H _T have a staircase structure is also referred to as a type B method.

Furthermore, the LDPC code for the parity check matrix represented by the parity check matrix initial value table of the type A method is also referred to as a type A code, and the LDPC code for the parity check matrix represented by the parity check matrix initial value table of the type B method is also referred to as a type B code.

The names "Type A" and "Type B" are based on the ATSC 3.0 standard. For example, ATSC3.0 uses both type A code and type B code.

Note that DVB-T.2 and other standards use type B codes.

FIG. 20 is a diagram illustrating an example of a parity check matrix initial value table for the type B method.

In other words, FIG. 20 shows a case where the code length N is 16200 bits and the coding rate (notation coding rate of DVB-T.2) r is 1/4, as specified in the DVB-T.2 standard. A parity check matrix initial value table (representing parity check matrix H) for a type B code is shown.

The parity check matrix generation unit 613 (FIG. 18) uses the type B type parity check matrix initial value table to obtain the parity check matrix H as follows.

FIG. 21 is a diagram illustrating a method for obtaining the parity check matrix H from the parity check matrix initial value table of the type B method.

That is, FIG. 21 shows a parity check matrix initial value table for a type B code with a code length N of 16200 bits and a coding rate r of 2/3, which is defined in the DVB-T.2 standard.

The parity check matrix initial value table for the type B method stores the position of the entire 1 element of the information matrix H _A corresponding to the information length K according to the code length N and coding rate r of the LDPC code in 360 columns (unit size P), and the i-th row is the row number of the 1st element in the 1+360×(i-1)th column of the parity check matrix H (the row number of the 1st row of the parity check matrix H is 0 row number) are lined up as many times as the column weight of the 1+360×(i-1)th column.

Here, the parity matrix H _T (FIG. 10) corresponding to the parity length M of the parity check matrix H of the type B method is determined to have a staircase structure as shown in FIG. If the information matrix H _A (FIG. 10) corresponding to the information length K can be determined, the parity check matrix H can be determined.

The number of rows k+1 of the parity check matrix initial value table of the type B method differs depending on the information length K.

The relationship expressed by equation (9) holds between the information length K and the number of rows k+1 of the parity check matrix initial value table.

K=(k+1)×360
...(9)

Here, 360 in equation (9) is the unit size P explained in FIG. 16.

In the parity check matrix initial value table of FIG. 21, 13 numbers are arranged from the 1st row to the 3rd row, and 3 numbers are arranged from the 4th row to the k+1th row (30th row in FIG. 21). The numbers are lined up.

Therefore, the column weights of the parity check matrix H obtained from the parity check matrix initial value table in FIG. 21 are 13 from the first column to the 1+360×(3-1)-1st column, From column (3-1) to column K, it is 3.

The first line of the parity check matrix initial value table in FIG. In the first column of is 0).

In addition, the second row of the parity check matrix initial value table in FIG. In the (=1+360×(2-1))th column, the row numbers 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108 indicate that the element in the row is 1. ing.

As described above, the parity check matrix initial value table represents the position of one element of the information matrix H _A of the parity check matrix H for every 360 columns.

The columns other than the 1+360×(i-1)th column of the parity check matrix H, that is, the columns from the 2+360×(i-1)th column to the 360×ith column, are the parity check matrix initial value table. The element 1 in the 1+360×(i-1) column determined by is periodically cyclically shifted downward (downward in the column) according to the parity length M and arranged.

In other words, for example, the 2+360×(i-1) column is the 1+360×(i-1) column cyclically shifted downward by M/360(=q). , the next 3+360×(i-1) column is the 1+360×(i-1) column cyclically shifted downward by 2×M/360 (=2×q) ( 2+360×(i-1) column cyclically shifted downward by M/360 (=q)).

Now, the value in the i-th row (i-th from the top) and the j-th column (j-th from the left) of the parity check matrix initial value table is expressed as h _i,j , and the j value in the w-th column of the parity check matrix H is expressed as h i,j. If the row number of the 1st element is expressed as H _wj , then the row number H of the 1st element in the wth column, which is a column other than the 1+360×(i-1)th column of the parity check matrix H. _wj can be determined using equation (10).

H _wj ＝mod{h _i,j ＋mod((w-1),P)×q,M)
...(10)

Here, mod (x, y) means the remainder when x is divided by y.

Further, P is the above-mentioned unit size, and in this embodiment, it is 360, for example, similar to the DVB-T.2 and ATSC3.0 standards. Further, q is a value M/360 obtained by dividing the parity length M by the unit size P (=360).

The parity check matrix generation unit 613 (FIG. 18) specifies the row number of the 1st element in the 1+360×(i-1)th column of the parity check matrix H using the parity check matrix initial value table.

Further, the parity check matrix generation unit 613 (FIG. 18) calculates the row number H _wj of the 1st element in the wth column, which is a column other than the 1+360×(i-1)th column of the parity check matrix H, by the formula ( 10), and generate a parity check matrix H in which the element of the row number obtained above is set to 1.

FIG. 22 is a diagram showing the structure of the parity check matrix H of the type A method.

The check matrix of the type A method is composed of an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.

The A matrix is the upper left matrix of the parity check matrix H with M1 rows and K columns, which is expressed by a predetermined value M1 and the information length K of the LDPC code=code length N×coding rate r.

The B matrix is a staircase-structured matrix with M1 rows and M1 columns adjacent to the right of the A matrix.

The C matrix is a matrix of N-K-M1 rows and K+M1 columns that is adjacent below the A matrix and the B matrix.

The D matrix is a unit matrix with N-K-M1 rows and N-K-M1 columns adjacent to the right of the C matrix.

The Z matrix is a zero matrix (0 matrix) adjacent to the right of the B matrix, with M1 rows and N-K-M1 columns.

In the type A check matrix H composed of the A to D matrices and the Z matrix as described above, part of the A matrix and the C matrix constitutes an information matrix, and the B matrix, The remaining part of the C matrix, the D matrix, and the Z matrix constitute a parity matrix.

Note that the B matrix is a matrix with a staircase structure, and the D matrix is a unit matrix, so a part of the parity matrix of the check matrix H in the type A method (the part of the B matrix) has a staircase structure. , the remaining part (D matrix part) is a diagonal matrix (identity matrix).

The A matrix and the C matrix have a cyclic structure for each column of unit size P (for example, 360 columns), similar to the information matrix of the check matrix H of the type B method, and the check matrix initial value table of the type A method represents the position of 1 element of matrix A and matrix C every 360 columns.

Here, as mentioned above, since part of the A matrix and C matrix constitutes an information matrix, a type A check matrix that represents the position of element 1 of the A matrix and C matrix every 360 columns is used. It can be said that the initial value table represents at least the position of one element of the information matrix every 360 columns.

In addition, since the check matrix initial value table of the type A method represents the position of the element 1 of the A matrix and the C matrix every 360 columns, the check matrix initial value table of the check matrix It is also possible to say that the position is expressed every 360 columns.

FIG. 23 is a diagram illustrating an example of a parity check matrix initial value table for the type A method.

That is, FIG. 23 shows an example of a parity check matrix initial value table representing a parity check matrix H having a code length N of 35 bits and a coding rate r of 2/7.

The parity check matrix initial value table of the type A method is a table that represents the position of one element of the A matrix and C matrix for each unit size P, and the i-th row contains 1+P×( The row number of the element 1 in the i-1) column (the row number with the row number of the first row of the parity check matrix H as 0) is the column that the 1+P×(i-1) column has. They are lined up by the number of weights.

Note that here, in order to simplify the explanation, it is assumed that the unit size P is, for example, 5.

For the check matrix H of the type A method, there are M1, M2, Q1, and Q2 as parameters.

M1 (FIG. 22) is a parameter that determines the size of the B matrix, and takes a value that is a multiple of the unit size P. By adjusting M1, the performance of the LDPC code changes, and when determining the parity check matrix H, it is adjusted to a predetermined value. Here, it is assumed that 15, which is three times the unit size P=5, is adopted as M1.

M2 (FIG. 22) takes the value M-M1 obtained by subtracting M1 from the parity length M.

Here, the information length K is N×r=35×2/7=10, and the parity length M is N-K=35-10=25, so M2 is M-M1=25-15=10. becomes.

Q1 is obtained according to the formula Q1=M1/P and represents the number of shifts (number of rows) of the cyclic shift in the A matrix.

In other words, columns other than the 1+P×(i-1)th column of the A matrix of the check matrix H of the type A method, that is, from the 2+P×(i-1)th column to the P×ith column Each column is arranged by periodically cyclically shifting the 1st element of the 1+P×(i-1)th column downward (downwards of the column) determined by the parity check matrix initial value table. , and Q1 represents the shift number of the cyclic shift in the A matrix.

Q2 is determined according to the formula Q2=M2/P and represents the number of cyclic shifts (number of rows) in the C matrix.

In other words, columns other than the 1+P×(i-1)th column of the C matrix of the check matrix H of the type A method, that is, from the 2+P×(i-1)th column to the P×ith column Each column is arranged by periodically cyclically shifting the 1st element of the 1+P×(i-1)th column downward (downwards of the column) determined by the parity check matrix initial value table. , and Q2 represents the shift number of the cyclic shift in the C matrix.

Here, Q1 is M1/P=15/5=3 and Q2 is M2/P=10/5=2.

In the parity check matrix initial value table of FIG. 23, three numerical values are arranged in the first and second rows, and one numerical value is arranged in the third to fifth rows. For example, the column weights of the A matrix and C matrix part of the parity check matrix H obtained from the parity check matrix initial value table in FIG. 23 are from 1=1+5×(1-1) column to 10=5×2 column It is 3 up to the 1st column, and 1 from the 11=1+5×(3-1) column to the 25=5×5th column.

In other words, the first row of the parity check matrix initial value table in FIG. This indicates that the element is 1 (and other elements are 0).

Here, in this case, the A matrix (Figure 22) is a matrix with 15 rows and 10 columns (M1 rows and K columns), and the C matrix (Figure 22) is a matrix with 10 rows and 25 columns (N-K-M1 rows and K+M1 (columns), the rows with row numbers 0 to 14 of the parity check matrix H are the rows of the A matrix, and the rows with row numbers 15 to 24 of the parity check matrix H are the rows of the C matrix.

Therefore, among the rows with row numbers 2, 6, and 18 (hereinafter described as rows #2, #6, and #18), rows #2 and #6 are rows of the A matrix, and the rows #18 is the row of the C matrix.

The second row of the parity check matrix initial value table in FIG. 23 is 2, 10, 19. It shows that the elements of 2, #10, and #19 are 1.

Here, in the 6th (=1+5×(2-1)) column of check matrix H, rows #2 and #10 of rows #2, #10, and #19 are rows of matrix A. Yes, row #19 is a row of the C matrix.

The third row of the parity check matrix initial value table in FIG. 1.

Here, in the 11th (=1+5×(3-1)) column of the parity check matrix H, row #22 is a row of the C matrix.

Similarly, in the 4th row 19 of the parity check matrix initial value table in FIG. 23, the element in row #19 is 1 in the 16th (=1+5×(4-1)) column of the parity check matrix H. 15 in the 5th row of the check matrix initial value table in FIG. 23 indicates that the element in row #15 is 1 in the 21st (=1+5×(5-1)) column of the check matrix It shows that.

As described above, the parity check matrix initial value table represents the position of one element of the A matrix and C matrix of the parity check matrix H for each unit size P=5 columns.

Columns other than the 1+5×(i-1)th column of the A matrix and C matrix of the check matrix H, that is, each column from the 2+5×(i-1)th column to the 5×ith column are , the element 1 in column 1+5×(i-1) determined by the check matrix initial value table is periodically cyclically shifted downward (downward in the column) according to parameters Q1 and Q2 and arranged. It has become a thing.

That is, for example, the 2+5×(i-1)th column of the A matrix is the 1+5×(i-1)th column cyclically shifted downward by Q1 (=3). The next 3+5×(i-1) column is the result of cyclically shifting the 1+5×(i-1) column downward by 2×Q1 (=2×3) ( 2+5×(i-1) column cyclically shifted downward by Q1).

Also, for example, the 2+5×(i-1)th column of the C matrix is the result of cyclically shifting the 1+5×(i-1)th column downward by Q2 (=2). The next 3+5×(i-1) column is the result of cyclically shifting the 1+5×(i-1) column downward by 2×Q2 (=2×2) ( 2+5×(i-1) column cyclically shifted downward by Q2).

FIG. 24 is a diagram showing the A matrix generated from the parity check matrix initial value table of FIG. 23.

In matrix A in FIG. 24, elements in rows #2 and #6 of the 1st (=1+5×(1-1)) column are set to 1 according to the first row of the parity check matrix initial value table in FIG. ing.

Then, each column from the 2nd (= 2 + 5 × (1-1)) column to the 5th (= 5 + 5 × (1-1)) column moves the previous column downward by Q1 = 3. It has been cyclically shifted to.

Furthermore, in the A matrix of FIG. 24, according to the second row of the parity check matrix initial value table of FIG. It has become.

Then, each column from the 7th (= 2 + 5 × (2-1)) column to the 10th (= 5 + 5 × (2-1)) column moves the previous column downward by Q1 = 3. It has been cyclically shifted to.

FIG. 25 is a diagram showing parity interleaving of the B matrix.

The parity check matrix generation unit 613 (FIG. 18) generates an A matrix using the parity check matrix initial value table, and arranges a step-structured B matrix to the right of the A matrix. Then, the parity check matrix generation unit 613 regards the B matrix as a parity matrix and performs parity interleaving such that adjacent elements of the B matrix having a staircase structure are spaced apart by the unit size P=5 in the row direction.

FIG. 25 shows the A matrix and B matrix after parity interleaving of the B matrix in FIG. 24.

FIG. 26 is a diagram showing a C matrix generated from the parity check matrix initial value table of FIG. 23.

In the C matrix of FIG. 26, the element in row #18 of the 1st (=1+5×(1-1)) column of the parity check matrix H is set to 1 according to the first row of the parity check matrix initial value table of FIG. It has become.

Then, each column from the 2nd (= 2 + 5 × (1-1)) column to the 5th (= 5 + 5 × (1-1)) column of the C matrix replaces the previous column with Q2 = 2 is cyclically shifted downward.

Furthermore, in the C matrix of FIG. 26, according to the second to fifth rows of the parity check matrix initial value table of FIG. 23, the 6th (=1+5×(2-1)) row # 19th, 11th(=1+5×(3-1)) row #22, 16th(=1+5×(4-1))th row #19, and 21(=1+5) The element in row #15 of the ×(5-1)) column is 1.

Then, each column from the 7th (= 2 + 5 × (2-1)) column to the 10th (= 5 + 5 × (2-1)) column, 12 (= 2 + 5 × (3-1)) ) column to the 15th (=5+5×(3-1)) column, and from the 17th (=2+5×(4-1)) column to the 20th (=5+5×(4- 1)), and each column from 22nd (= 2 + 5 × (5-1)) to 25th (= 5 + 5 × (5-1)) The column is cyclically shifted downward by Q2=2.

The parity check matrix generation unit 613 (FIG. 18) uses the parity check matrix initial value table to generate a C matrix, and places the C matrix below the A matrix and the B matrix (after parity interleaving).

Furthermore, the parity check matrix generation unit 613 places the Z matrix to the right of the B matrix and the D matrix to the right of the C matrix, thereby generating the parity check matrix H shown in FIG. 26.

FIG. 27 is a diagram showing parity interleaving of the D matrix.

After generating the check matrix H shown in FIG. 26, the check matrix generation unit 613 regards the D matrix as a parity matrix, and generates elements of 1 in the odd row and the next even row of the D matrix, which is the unit matrix, in the row direction. , perform parity interleaving (of only the D matrix) so that they are separated by a unit size of P=5.

FIG. 27 shows the parity check matrix H of FIG. 26 after performing parity interleaving of the D matrix.

The LDPC encoder 115 (encoding parity calculation unit 615 (FIG. 18)) performs LDPC encoding (generation of an LDPC code) using, for example, check matrix H in FIG.

Here, the LDPC code generated using the parity check matrix H in FIG. 27 is an LDPC code that has undergone parity interleaving. Therefore, the LDPC code generated using the parity check matrix H in FIG. There is no need to perform parity interleaving in the parity interleaver 23 (FIG. 9). In other words, the LDPC code generated using the parity check matrix H after parity interleaving of the D matrix is an LDPC code that has undergone parity interleaving. is skipped.

FIG. 28 shows how parity interleaving is restored to the B matrix, a part of the C matrix (the part of the C matrix located below the B matrix), and the D matrix of the check matrix H in FIG. 27. FIG. 3 is a diagram showing a parity check matrix H that has undergone column permutation as parity deinterleaving.

The LDPC encoder 115 can perform LDPC encoding (generation of an LDPC code) using the parity check matrix H shown in FIG.

When performing LDPC encoding using check matrix H in FIG. 28, an LDPC code without parity interleaving is obtained according to the LDPC encoding. Therefore, when performing LDPC encoding using check matrix H in FIG. 28, parity interleaving is performed in parity interleaver 23 (FIG. 9).

FIG. 29 is a diagram showing a transformed check matrix H obtained by performing row permutation on the check matrix H of FIG. 27.

As described later, the conversion check matrix is a P×P unit matrix, a quasi-identity matrix in which one or more of the 1's in the unit matrix is 0, a shift matrix obtained by cyclically shifting the unit matrix or the quasi-unit matrix, The matrix is a combination of a sum matrix that is the sum of two or more of the unit matrix, quasi-unit matrix, or shift matrix, and a P×P 0 matrix.

By using a transformation check matrix for decoding an LDPC code, it is possible to adopt an architecture in which P check node operations and variable node operations are performed simultaneously in decoding the LDPC code, as will be described later.

<New LDPC code>

One way to ensure good communication quality in data transmission using LDPC codes is to use LDPC codes with good performance.

In the following, a new LDPC code with good performance (hereinafter also referred to as new LDPC code) will be explained.

As a new LDPC code, for example, it is possible to adopt a type A code or a type B code that has a unit size P of 360, similar to DVB-T.2 or ATSC3.0, and that corresponds to a check matrix H with a cyclic structure. can.

The LDPC encoder 115 (FIGS. 8 and 18) has a code length N longer than 64k bits, for example, 69120 bits, and a coding rate r of, for example, 2/16, 3/16, Any of 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, or 14/16 LDPC encoding to a new LDPC code can be performed using the parity check matrix initial value table (parity check matrix H obtained from) of the new LDPC code.

In this case, the storage unit 602 of the LDPC encoder 115 (FIG. 8) stores a parity check matrix initial value table of the new LDPC code.

Figure 30 shows the check matrix H of a type A code (hereinafter also referred to as type A code with r=2/16) as a new LDPC code with a code length N of 69120 bits and a coding rate r of 2/16. FIG. 3 is a diagram showing an example of a parity check matrix initial value table (of type A method).

Figures 31 and 32 show a type A code (hereinafter also referred to as a type A code with r=3/16) as a new LDPC code with a code length N of 69120 bits and a coding rate r of 3/16. 3 is a diagram illustrating an example of a parity check matrix initial value table representing a parity check matrix H. FIG.

Note that FIG. 32 is a diagram following FIG. 31.

Figure 33 shows the check matrix H of a type A code (hereinafter also referred to as a type A code with r=4/16) as a new LDPC code with a code length N of 69120 bits and a coding rate r of 4/16. FIG. 3 is a diagram showing an example of a parity check matrix initial value table.

Figures 34 and 35 show a type A code (hereinafter also referred to as a type A code with r=5/16) as a new LDPC code with a code length N of 69120 bits and a coding rate r of 5/16. 3 is a diagram illustrating an example of a parity check matrix initial value table representing a parity check matrix H. FIG.

Note that FIG. 35 is a diagram following FIG. 34.

Figures 36 and 37 show a type A code (hereinafter also referred to as a type A code with r=6/16) as a new LDPC code with a code length N of 69120 bits and a coding rate r of 6/16. 3 is a diagram illustrating an example of a parity check matrix initial value table representing a parity check matrix H. FIG.

Note that FIG. 37 is a diagram following FIG. 36.

Figures 38 and 39 show a type A code (hereinafter also referred to as a type A code with r=7/16) as a new LDPC code with a code length N of 69120 bits and a coding rate r of 7/16. 3 is a diagram illustrating an example of a parity check matrix initial value table representing a parity check matrix H. FIG.

Note that FIG. 39 is a diagram following FIG. 38.

40 and 41 show a type A code (hereinafter also referred to as a type A code with r=8/16) as a new LDPC code with a code length N of 69120 bits and a coding rate r of 8/16. 3 is a diagram illustrating an example of a parity check matrix initial value table representing a parity check matrix H. FIG.

Note that FIG. 41 is a diagram following FIG. 40.

42 and 43 show a type B code (hereinafter also referred to as a type B code with r=7/16) as a new LDPC code with a code length N of 69120 bits and a coding rate r of 7/16. 3 is a diagram showing an example of a parity check matrix initial value table (of type B method) representing parity check matrix H; FIG.

Note that FIG. 43 is a diagram following FIG. 42.

44 and 45 are diagrams showing other examples of parity check matrix initial value tables representing parity check matrix H of type B code with r=7/16.

Note that FIG. 45 is a diagram following FIG. 44. The type B code with r=7/16 obtained from the parity check matrix initial value table (the parity check matrix H represented by) in FIGS. 44 and 45 is hereinafter also referred to as another type B code with r=7/16.

46 and 47 show a type B code (hereinafter also referred to as a type B code with r=8/16) as a new LDPC code with a code length N of 69120 bits and a coding rate r of 8/16. 3 is a diagram illustrating an example of a parity check matrix initial value table representing a parity check matrix H. FIG.

Note that FIG. 47 is a diagram following FIG. 46.

48 and 49 are diagrams showing other examples of parity check matrix initial value tables representing parity check matrix H of type B code with r=8/16.

Note that FIG. 49 is a diagram following FIG. 48. The type B code with r=8/16 obtained from the parity check matrix initial value tables in FIGS. 48 and 49 is also referred to hereinafter as another type B code with r=8/16.

Figures 50, 51, and 52 show type B codes (hereinafter also referred to as type B codes with r=9/16) as new LDPC codes with a code length N of 69120 bits and a coding rate r of 9/16. FIG. 3 is a diagram showing an example of a parity check matrix initial value table representing the parity check matrix H of (1).

Note that FIG. 51 is a diagram following FIG. 50, and FIG. 52 is a diagram following FIG. 51.

53, FIG. 54, and FIG. 55 are diagrams showing other examples of parity check matrix initial value tables representing parity check matrix H of type B code with r=9/16.

Note that FIG. 54 is a diagram following FIG. 53, and FIG. 55 is a diagram following FIG. 54. The type B code with r=9/16 obtained from the parity check matrix initial value tables of FIGS. 53 to 55 is hereinafter also referred to as another type B code with r=9/16.

Figures 56, 57, and 58 show type B codes (hereinafter also referred to as type B codes with r=10/16) as new LDPC codes with a code length N of 69120 bits and a coding rate r of 10/16. FIG. 3 is a diagram showing an example of a parity check matrix initial value table representing the parity check matrix H of (1).

Note that FIG. 57 is a diagram following FIG. 56, and FIG. 58 is a diagram following FIG. 57.

FIG. 59, FIG. 60, and FIG. 61 are diagrams showing other examples of parity check matrix initial value tables representing parity check matrix H of type B code with r=10/16.

Note that FIG. 60 is a diagram following FIG. 59, and FIG. 61 is a diagram following FIG. 60. The type B code with r=10/16 obtained from the parity check matrix initial value tables of FIGS. 59 to 61 is hereinafter also referred to as other type B code with r=10/16.

Figures 62, 63, and 64 show a type B code as a new LDPC code with a code length N of 69120 bits and a coding rate r of 11/16 (hereinafter also referred to as a type B code with r=11/16). FIG. 3 is a diagram showing an example of a parity check matrix initial value table representing the parity check matrix H of (1).

Note that FIG. 63 is a diagram following FIG. 62, and FIG. 64 is a diagram following FIG. 63.

65, 66, and 67 are diagrams showing other examples of parity check matrix initial value tables representing parity check matrix H of type B code with r=11/16.

Note that FIG. 66 is a diagram following FIG. 65, and FIG. 67 is a diagram following FIG. 66. The type B code with r=11/16 obtained from the parity check matrix initial value tables of FIGS. 65 to 67 is hereinafter also referred to as another type B code with r=11/16.

Figures 68, 69, and 70 show type B codes (hereinafter also referred to as r=12/16 type B codes) as new LDPC codes with a code length N of 69120 bits and a coding rate r of 12/16. FIG. 3 is a diagram showing an example of a parity check matrix initial value table representing the parity check matrix H of (1).

Note that FIG. 69 is a diagram following FIG. 68, and FIG. 70 is a diagram following FIG. 69.

71, FIG. 72, and FIG. 73 are diagrams showing other examples of parity check matrix initial value tables representing parity check matrix H of type B code with r=12/16.

Note that FIG. 72 is a diagram following FIG. 71, and FIG. 73 is a diagram following FIG. 72. The type B code with r=12/16 obtained from the parity check matrix initial value tables of FIGS. 71 to 73 is hereinafter also referred to as other type B code with r=12/16.

Figures 74, 75, and 76 show type B codes (hereinafter also referred to as r=13/16 type B codes) as new LDPC codes with a code length N of 69120 bits and a coding rate r of 13/16. FIG. 3 is a diagram showing an example of a parity check matrix initial value table representing the parity check matrix H of (1).

Note that FIG. 75 is a diagram following FIG. 74, and FIG. 76 is a diagram following FIG. 75.

77, FIG. 78, and FIG. 79 are diagrams showing other examples of parity check matrix initial value tables representing parity check matrix H of type B code with r=13/16.

Note that FIG. 78 is a diagram following FIG. 77, and FIG. 79 is a diagram following FIG. 78. The type B code with r=13/16 obtained from the parity check matrix initial value tables of FIGS. 77 to 79 is hereinafter also referred to as another type B code with r=13/16.

Figures 80, 81, and 82 show type B codes (hereinafter also referred to as r=14/16 type B codes) as new LDPC codes with a code length N of 69120 bits and a coding rate r of 14/16. FIG. 3 is a diagram showing an example of a parity check matrix initial value table representing the parity check matrix H of (1).

Note that FIG. 81 is a diagram following FIG. 80, and FIG. 82 is a diagram following FIG. 81.

FIGS. 83, 84, and 85 are diagrams showing other examples of parity check matrix initial value tables representing parity check matrix H of type B code with r=14/16.

Note that FIG. 84 is a diagram following FIG. 83, and FIG. 85 is a diagram following FIG. 84. The type B code with r=14/16 obtained from the parity check matrix initial value tables of FIGS. 83 to 85 is hereinafter also referred to as another type B code with r=14/16.

The new LDPC code is an LDPC code with good performance.

Here, an LDPC code with good performance is an LDPC code obtained from an appropriate parity check matrix H.

An appropriate parity check matrix H is, for example, when the LDPC code obtained from the parity check matrix H is transmitted with low E _s /N ₀ or E _b /N _o (signal power to noise power ratio per bit). , is a parity check matrix that satisfies predetermined conditions and reduces BER (bit error rate) (and FER (frame error rate)).

An appropriate check matrix H can be found, for example, by performing a simulation to measure the BER when LDPC codes obtained from various check matrices that satisfy predetermined conditions are transmitted at a low E _s /N _o .

The predetermined conditions that an appropriate check matrix H must satisfy include, for example, that the analysis result obtained by the code performance analysis method called Density Evolution is good, and that the analysis result of one element called cycle 4 is good. There are no loops, etc.

Here, it is known that the decoding performance of the LDPC code deteriorates when elements of 1 are crowded together like in cycle 4 in the information matrix _H. It is desirable that 4 does not exist.

In the parity check matrix H, the minimum length of a loop (loop length) made up of 1 elements is called a girth. The absence of cycle 4 means that girth is greater than 4.

Note that the predetermined conditions that should be satisfied by the appropriate parity check matrix H can be determined as appropriate from the viewpoint of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, and the like.

FIGS. 86 and 87 are diagrams illustrating density evolution in which an analysis result is obtained as a predetermined condition that an appropriate parity check matrix H should satisfy.

Density evolution is a code analysis method that calculates the expected value of the error probability for the entire LDPC code (ensemble) with a code length N of ∞, which is characterized by a degree sequence (described later). It is.

For example, on an AWGN channel, when the variance of the noise is gradually increased from 0, the expected value of the error probability of a certain ensemble is 0 at first, but the variance of the noise is greater than or equal to a certain threshold. Then, it will no longer be 0.

According to density evolution, the performance of the ensemble (the appropriateness of the check matrix) can be determined by comparing the threshold value of the noise variance value (hereinafter also referred to as the performance threshold) at which the expected value of the error probability is no longer 0. can be determined.

Note that for a specific LDPC code, by determining the ensemble to which the LDPC code belongs and performing density evolution on that ensemble, it is possible to roughly predict the performance of the LDPC code.

Therefore, if an ensemble with good performance is found, an LDPC code with good performance can be found among the LDPC codes belonging to that ensemble.

Here, the above-mentioned degree sequence represents the ratio of variable nodes and check nodes having weights of each value to the code length N of the LDPC code.

For example, a regular(3,6) LDPC code with a coding rate of 1/2 has a degree in which all variable nodes have a weight (column weight) of 3 and all check nodes have a weight (row weight) of 6. Belongs to an ensemble characterized by a sequence.

FIG. 86 shows a Tanner graph of such an ensemble.

In the Tanner bluff of FIG. 86, there are N variable nodes indicated by circles (○ marks) equal to the code length N, and check nodes indicated by rectangles (□ marks) in the figure have a coding rate equal to the code length N. There are only N/2 equal to the multiplication value multiplied by 1/2.

Three edges equal to the column weight are connected to each variable node, and therefore there are a total of 3N edges connected to N variable nodes.

Furthermore, six branches equal to the row weight are connected to each check node, and therefore there are a total of 3N branches connected to N/2 check nodes.

Furthermore, in the Tanner graph of FIG. 86, there is one interleaver.

The interleaver randomly rearranges 3N branches connected to N variable nodes, and each rearranged branch is divided into 3N branches connected to N/2 check nodes. Connect to one of them.

The interleaver has (3N)!(=(3N)×(3N-1)×・・・×1) possible sorting patterns for 3N branches connected to N variable nodes. There are only Therefore, an ensemble characterized by degree resequences in which all variable nodes have a weight of 3 and all check nodes have a weight of 6 is a set of (3N)! LDPC codes.

In the simulation to find a high-performance LDPC code (appropriate check matrix), a multi-edge type ensemble was used in density evolution.

In the multi-edge type, the interleaver through which the branch connected to the variable node and the branch connected to the check node pass is divided into multiple (multi-edge), which allows for better characterization of the ensemble. strictly conducted.

FIG. 87 shows an example of a Tanner graph for a multi-edge type ensemble.

In the Tanner graph of FIG. 87, there are two interleavers, a first interleaver and a second interleaver.

In addition, in the Tanner graph in Figure 87, there is one branch connected to the first interleaver, only v1 variable nodes with zero branches connected to the second interleaver, and one edge connected to the first interleaver. , there are only v2 variable nodes with two branches connected to the second interleaver, only v3 variable nodes with zero branches connected to the first interleaver, and two branches connected to the second interleaver, respectively. exist.

Furthermore, in the Tanner graph of Fig. 87, there are two edges connected to the first interleaver, only c1 check nodes with zero edges connected to the second interleaver, and two edges connected to the first interleaver. , there are only c2 check nodes with 2 branches connected to the second interleaver, 0 branches connected to the first interleaver, and only c3 check nodes with 3 branches connected to the second interleaver, respectively. exist.

For density evolution and its implementation, see, for example, "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", S.Y.Chung, G.D.Forney, T.J.Richardson,R.Urbanke, IEEE Communications Leggers, VOL.5, NO.2, Feb 2001.

In a simulation to find a new LDPC code (check matrix), the BER starts to drop (becomes smaller) due to multi-edge type density evolution at E _b /N ₀ (signal power to noise power ratio per bit). Find an ensemble whose performance threshold is less than a predetermined value, and select an LDPC code from among the LDPC codes belonging to that ensemble that reduces the BER when using one or more orthogonal modulations such as QPSK as a high-performance LDPC code. Selected.

The new LDPC code (parity check matrix initial value table representing the check matrix of the new LDPC code) was obtained through the simulation described above.

Therefore, according to the new LDPC code, good communication quality can be ensured in data transmission.

FIG. 88 is a diagram illustrating the column weights of the parity check matrix H of the type A code as the new LDPC code.

For the check matrix H of type A code, as shown in Figure 88, the column weights of the first to K1 columns of the A matrix are Y1, the column weights of the subsequent K2 column of the A matrix are Y2, and the column weights of the C matrix are The column weight of the K1 column from the first column is expressed as X1, the column weight of the subsequent K2 column of the C matrix is expressed as X2, and the column weight of the subsequent M1 column of the C matrix is expressed as X3.

Note that K1+K2 is equal to the information length K, and M1+M2 is equal to the parity length M. Therefore, K1+K2+M1+M2 is equal to code length N=69120 bits.

Furthermore, for the check matrix H of the type A code, the column weights of the first to M1-1 columns of the B matrix are 2, and the column weights of the M1th column (last column) of the B matrix are 1. Furthermore, the column weights of the D matrix are 1 and the column weights of the Z matrix are 0.

FIG. 89 is a diagram showing the parameters of the parity check matrix H of the type A code (represented by the parity check matrix initial value table) in FIGS. 30 to 41.

X1, Y1, K1, X2, Y2 as parameters of check matrix H of type A code with r=2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16 , K2, X3, M1, M2, and the performance threshold are as shown in FIG.

The parameters X1, Y1, K1 (or K2), X2, Y2, X3, M1 (or M2) are set so that the performance (for example, error rate, etc.) of the LDPC code is further improved.

FIG. 90 is a diagram illustrating the column weights of the parity check matrix H of the type B code as the new LDPC code.

For the check matrix H of type B code, as shown in Figure 90, the column weights of the first to KX1 columns are X1, the column weights of the subsequent KX2 columns are X2, and the column weights of the subsequent KY1 columns are Y1. and the column weight of the subsequent KY2 column as Y2.

Note that KX1+KX2+KY1+KY2 is equal to the information length K, and KX1+KX2+KY1+KY2+M is equal to the code length N=69120 bits.

Furthermore, for the parity check matrix H of the type B code, among the last M columns, the column weights of M-1 columns excluding the last one are 2, and the column weight of the last one column is 1.

FIG. 91 is a diagram showing the parameters of the parity check matrix H of the type B code (represented by the parity check matrix initial value table) in FIGS. 42 to 85.

As a parameter of the check matrix H of type B codes of r=7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16 and other type B codes X1, KX1, X2, KX2, Y1, KY1, Y2, KY2, M and the performance threshold are as shown in FIG.

Parameters X1, KX1, X2, KX2, Y1, KY1, Y2, and KY2 are set to further improve the performance of the LDPC code.

According to the new LDPC code, good BER/FER is achieved and capacity (communication channel capacity) close to the Shannon limit is achieved.

<Constellation>

92 to 107 are diagrams showing examples of constellations that can be employed in the transmission system of FIG. 7.

In the transmission system of FIG. 7, for example, for MODCOD, which is a combination of a modulation method (MODulation) and an LDPC code (CODe), a constellation to be used in the MODCOD can be set.

One or more constellations can be set for one MODCOD.

There are two types of constellations: UC (Uniform Constellation), in which the signal points are arranged uniformly, and NUC (Non Uniform Constellation), in which the arrangement of signal points is not uniform.

Furthermore, the NUC includes, for example, a constellation called 1D NUC (1-dimensional M ² -QAM non-uniform constellation), a constellation called 2D NUC (2-dimensional QQAM non-uniform constellation), and the like.

In general, 1D NUC has better BER than UC, and 2D NUC has better BER than 1D NUC.

A constellation whose modulation method is QPSK becomes UC. For example, UC or 2D NUC can be used as a constellation with a modulation method of 16QAM, 64QAM, or 256QAM, and for a constellation with a modulation method of 1024QAM or 4096QAM, for example, UC or 1D NUC can be used. can be adopted.

The transmission system of FIG. 7 can use various constellations such as those defined in ATSC3.0, DVB-C.2, etc., for example.

That is, when the modulation method is QPSK, for example, the same UC can be used for each coding rate r of the LDPC code.

Further, when the modulation method is 16QAM, 64QAM, or 256QAM, the same UC can be used for each coding rate r of the LDPC code, for example. Furthermore, when the modulation method is 16QAM, 64QAM, or 256QAM, different 2D NUCs can be used for each coding rate r of the LDPC code, for example.

Further, when the modulation method is 1024QAM or 4096QAM, for example, the same UC can be used for each coding rate r of the LDPC code. Further, when the modulation method is 1024QAM or 4096QAM, for example, a different 1D NUC can be used for each coding rate r of the LDPC code.

Here, the UC of QPSK is also referred to as QPSK-UC, and the UC of 2 ^m QAM is also referred to as 2 ^m QAM-UC. In addition, 2 ^m QAM 1D NUC and 2D NUC are also written as 2 ^m QAM-1D NUC and 2 ^m QAM-2D NUC, respectively.

Some of the constellations specified in ATSC3.0 will be explained below.

FIG. 92 is a diagram showing coordinates of signal points of QPSK-UC used for all coding rates of the LDPC code defined in ATSC3.0 when the modulation method is QPSK.

In FIG. 92, "Input Data cell y" represents a 2-bit symbol mapped to QPSK-UC, and "Constellation point z _s " represents the coordinates of signal point z _s . Note that the index s of the signal point _zs (same as the index q of the signal point _zq , which will be described later) represents the discrete time of the symbol (the time interval between one symbol and the next symbol).

In FIG. 92, the coordinates of the signal point _zs are expressed in the form of a complex number, and j represents an imaginary unit (√(-1)).

Figure 93 shows that when the modulation method is 16QAM, the coding rate r (CR) of the LDPC code specified in ATSC3.0 = 2/15, 3/15, 4/15, 5/15, 6/ 15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15 are diagrams showing the coordinates of signal points of 16QAM-2D NUC used.

In FIG. 93, similarly to FIG. 92, the coordinates of the signal point _zs are expressed in the form of a complex number, and j represents an imaginary unit.

In FIG. 93, w#k represents the coordinates of the signal point in the first quadrant of the constellation.

In a 2D NUC, the signal point in the second quadrant of the constellation is placed at a position symmetrically moved from the signal point in the first quadrant with respect to the Q axis, and the signal point in the third quadrant of the constellation is placed at a position symmetrically moved from the signal point in the first quadrant to the first quadrant. The signal points of the quadrants are placed at positions symmetrically moved with respect to the origin. The signal points in the fourth quadrant of the constellation are arranged at positions symmetrically moved from the signal points in the first quadrant with respect to the I-axis.

Here, when the modulation method is 2 ^m QAM, m bits are treated as one symbol, and that one symbol is mapped to the signal point corresponding to that symbol.

For example, an m-bit symbol can be expressed as an integer value between 0 and 2 ^m -1, but if b = 2 ^m /4, a symbol can be expressed as an integer value between 0 and 2 ^m -1. y(0), y(1), ..., y(2 ^m -1) are symbols y(0) to y(b-1), y(b) to y(2b-1), y( It can be classified into four types: 2b) to y(3b-1), and y(3b) to y(4b-1).

In FIG. 93, the suffix k of w#k takes an integer value in the range of 0 to b-1, and w#k is the symbol y(k) in the range of symbols y(0) to y(b-1). represents the coordinates of the signal point corresponding to .

The coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are expressed as -conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are The coordinates of the signal point corresponding to symbol y(k+2b) in the range of y(3b-1) are expressed as conj(w#k). Further, the coordinates of the signal point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are expressed as -w#k.

Here, conj(w#k) represents the complex conjugate of w#k.

For example, if the modulation method is 16QAM, the m = 4-bit symbols y(0), y(1), ..., y(15) are converted into symbols y(0), y(1), ..., y(15) with b = 2 ⁴ /4 = 4. It is classified into four categories: (0) to y(3), y(4) to y(7), y(8) to y(11), and y(12) to y(15).

Among symbols y(0) to y(15), for example, symbol y(12) is a symbol y(k+3b)=y( 0+3×4) and k=0, the coordinates of the signal point corresponding to symbol y(12) are -w#k=-w0.

Now, if the coding rate r(CR) of the LDPC code is, for example, 9/15, then according to FIG. 93, w0 when the modulation method is 16QAM and the coding rate r is 9/15. is 0.2386+j0.5296, so the coordinates -w0 of the signal point corresponding to symbol y(12) are -(0.2386+j0.5296).

Figure 94 shows that when the modulation method is 1024QAM, the coding rate r (CR) of the LDPC code specified in ATSC3.0 = 2/15, 3/15, 4/15, 5/15, 6/ 15 is a diagram showing an example of coordinates of signal points of 1024QAM-1D NUC used for 15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15.

In FIG. 94, u#k represents the real part Re(z _s ) and the imaginary part Im(z _s ) of a complex number as the coordinates of the signal point z _s of the 1D NUC.

Figure 95 shows a 1024QAM symbol y and u#k as the real part Re(z _s ) and imaginary part Im(z _s ) of complex numbers representing the coordinates of the signal point z _s of the 1D NUC corresponding to the symbol y. FIG.

Now, the 10-bit symbol y of 1024QAM is expressed as y _0,s , y _1,s , y _2,s , y _3,s , y _4,s , y _5, from the first bit (most significant bit). Let them be expressed as _s , y _6,s , y _7,s , y _8,s , y _9,s .

A in FIG. 95 shows the even 5 bits y _1,s , y _3,s , y _5,s , y _7,s , y _9,s of the symbol y and the signal point z _s corresponding to the symbol y. It represents the correspondence relationship with u#k representing the (coordinate) real part Re(z _s ) of .

B of FIG. 95 shows the odd-numbered 5 bits y _0,s , y _2,s , y _4,s , y _6,s , y _8,s of the symbol y and the signal point z _s corresponding to the symbol y. represents the correspondence relationship with u#k representing the imaginary part Im(z _s ).

1024QAM 10-bit symbol y = (y _0,s , y _1,s , y _{2,s , y 3,s} , y _4,s , y _5,s , y _{6,s ,} y _7,s , y For example, if _8,s , y _9,s ) is (0,0,1,0,0,1,1,1,0,0), then the odd 5 bits (y _0,s , y _2,s , y _4,s , y _6,s , y _8,s ) is (0,1,0,1,0), and the even 5 bits (y _1,s , y _3,s , y _5,s , y _7,s , y _9,s ) are (0,0,1,1,0).

In FIG. 95A, the even-numbered 5 bits (0,0,1,1,0) are associated with u11, and therefore the symbol y=(0,0,1,0,0,1, The real part Re(z _s ) of the signal point z _s corresponding to 1,1,0,0) becomes u11.

In FIG. 95B, the odd-numbered 5 bits (0,1,0,1,0) are associated with u3, and therefore the symbol y=(0,0,1,0,0,1, The imaginary part Im(z _s ) of the signal point z _s corresponding to 1,1,0,0) becomes u3.

On the other hand, if the coding rate r of the LDPC code is, for example, 6/15, then according to FIG. For the 1D NUC used in one case, u3 is 0.1295 and u11 is 0.7196.

Therefore, the real part Re(z _s ) of the signal point z _s corresponding to symbol y = (0,0,1,0,0,1,1,1,0,0) is u11 = 0.7196, which is imaginary. Part Im(z _s ) becomes u3=0.1295. As a result, the coordinates of the signal point _zs corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) are expressed as 0.7196+j0.1295.

Note that the signal points of the 1D NUC are arranged in a grid pattern on straight lines parallel to the I-axis and on straight lines parallel to the Q-axis in the constellation. However, the intervals between signal points are not constant. Furthermore, when transmitting signal points (data mapped to them), the average power of the signal points on the constellation can be normalized. For normalization, if the root mean square value of the absolute values of all the signal points (coordinates) on the constellation is expressed as P _ave , then the square root of the root mean square value P _ave √ The reciprocal of P _ave 1/(√ P _ave ) by multiplying each signal point z _s on the constellation.

The transmission system shown in FIG. 7 can use the constellation defined in ATSC3.0 as described above.

96 to 107 are diagrams showing the coordinates of UC signal points defined in DVB-C.2.

That is, FIG. 96 is a diagram showing the real part Re(z _q ) of the coordinates z _q of the signal point of QPSK-UC (UC of QPSK) defined in DVB-C.2. FIG. 97 is a diagram showing the imaginary part Im(z _q ) of the coordinates z _q of the QPSK-UC signal point defined in DVB-C.2.

FIG. 98 is a diagram showing the real part Re(z _q ) of the coordinates z _q of the signal point of 16QAM-UC (UC of 16QAM) defined in DVB-C.2. FIG. 99 is a diagram showing the imaginary part Im(z _q ) of the coordinates z _q of the signal point of 16QAM-UC defined in DVB-C.2.

FIG. 100 is a diagram showing the real part Re(z _q ) of the coordinates z _q of the signal point of 64QAM-UC (UC of 64QAM) defined in DVB-C.2. FIG. 101 is a diagram showing the imaginary part Im(z _q ) of the coordinates z _q of the signal point of 64QAM-UC defined in DVB-C.2.

FIG. 102 is a diagram showing the real part Re(z _q ) of the coordinates z _q of the signal point of 256QAM-UC (256QAM UC) defined in DVB-C.2. FIG. 103 is a diagram showing the imaginary part Im(z _q ) of the coordinates z _q of the signal point of 256QAM-UC defined in DVB-C.2.

FIG. 104 is a diagram showing the real part Re(z _q ) of the coordinates z _q of the signal point of 1024QAM-UC (UC of 1024QAM) defined in DVB-C.2. FIG. 105 is a diagram showing the imaginary part Im(z _q ) of the coordinates z _q of the signal point of 1024QAM-UC defined in DVB-C.2.

FIG. 106 is a diagram showing the real part Re(z _q ) of the coordinates z _q of the signal point of 4096QAM-UC (UC of 4096QAM) defined in DVB-C.2. FIG. 107 is a diagram showing the imaginary part Im(z _q ) of the coordinates z _q of the signal point of 4096QAM-UC defined in DVB-C.2.

Note that in FIGS. 96 to 107, y _i,q represents the i+1-th bit from the beginning of the m-bit (for example, 2 bits in QPSK) symbol of 2 ^m QAM. Furthermore, when transmitting UC signal points (data mapped to them), the average power of the signal points on the constellation can be normalized. For normalization, if the root mean square value of the absolute values of all the signal points (coordinates) on the constellation is expressed as P _ave , then the square root of the root mean square value P _ave √ The reciprocal of P _ave 1/(√ P _ave ) by multiplying each signal point z _q on the constellation.

The transmission system shown in FIG. 7 can use the UC defined in DVB-C.2 as described above.

That is, in FIGS. 30 to 85, the code length N is 69120 bits and the coding rate r is 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, The new LDPC codes corresponding to (parity check matrix initial value tables) for 9/16, 10/16, 11/16, 12/16, 13/16, and 14/16 are shown in Figures 96 to 107. UC can be used.

<Block interleaver 25>

FIG. 108 is a diagram illustrating block interleaving performed by block interleaver 25 in FIG. 9.

Block interleaving is performed by dividing the LDPC code of one code word into a part called part 1 and a part called part 2 from the beginning.

If the length (number of bits) of part 1 is expressed as Npart1, and the length of part 2 is expressed as Npart2, then Npart1+Npart2 is equal to code length N.

Conceptually, in block interleaving, a column (vertical) as one direction is a storage area that stores Npart1/m bits, and a column (column) as a storage area that stores Npart1/m bits is stored in a row direction that is orthogonal to the column direction. A number m equal to m is arranged, and each column is divided into small units of 360 bits each having a unit size P from the top. This small column unit is also called a column unit.

In block interleaving, as shown in Figure 108, part 1 of the LDPC code of one code word is written from the top to the bottom (column direction) of the first column unit of the column, and from the left to the right column. It is carried out towards.

Then, when writing to the first column unit in the rightmost column is completed, as shown in FIG. Part 1 of the LDPC code for one code word is written in the same way in the right column.

When writing of part 1 of the LDPC code for one code word is completed, part 1 of the LDPC code is read out in units of m bits in the row direction from the first row of all m columns, as shown in Figure 108. .

This m-bit unit of part 1 is supplied from the block interleaver 25 to the mapper 117 (FIG. 8) as an m-bit symbol.

Part 1 is read in units of m bits sequentially toward the rows below the m columns, and when reading of part 1 is completed, part 2 is divided into units of m bits from the beginning, and m bits are read out in units of m bits. is supplied from the block interleaver 25 to the mapper 117 as a symbol.

Therefore, part 1 is interleaved and symbolized, and part 2 is not interleaved but sequentially divided into m bits and symbolized.

The column length Npart1/m is a multiple of the unit size P 360, and so that Npart1/m is a multiple of 360, the LDPC code of one code word is divided into part 1 and part 2. It can be divided into

FIG. 109 is a diagram showing examples of part 1 and part 2 of an LDPC code with a code length N of 69120 bits when the modulation method is QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM, respectively.

In Figure 109, when the modulation method is 1024QAM, part 1 is 68400 bits and part 2 is 720 bits, and when the modulation method is QPSK, 16QAM, 64QAM, 256QAM, and 4096QAM, In the case of , part 1 is 69120 bits and part 2 is 0 bits.

<Group wise interleave>

FIG. 110 is a diagram illustrating group-wise interleaving performed by the group-wise interleaver 24 of FIG. 9.

In group-wise interleaving, as shown in Figure 110, the LDPC code of one code word is divided into 360-bit units equal to the unit size P from the beginning, and the 360 bits of one division are treated as a bit group for one code. The word LDPC codes are interleaved in bit group units according to a predetermined pattern (hereinafter also referred to as GW pattern).

Here, when the LDPC code of one code word is divided into bit groups, the i+1-th bit group from the beginning is hereinafter also referred to as bit group i.

When the unit size P is 360, for example, an LDPC code with a code length N of 1800 bits is divided into 5 (=1800/360) bit groups of bit groups 0, 1, 2, 3, and 4. Furthermore, for example, an LDPC code with a code length N of 69120 bits is divided into 192 (=69120/360) bit groups of bit groups 0, 1, . . . , 191.

Further, in the following, the GW pattern will be expressed as a sequence of numbers representing bit groups. For example, for an LDPC code with a code length N of 1800 bits, for example, the GW pattern 4,2,0,3,1 changes the order of bit groups 0,1,2,3,4 to bit groups 4,2,0. ,3,1 represents interleaving (reordering).

For example, let x _i represent the i+1-th code bit from the beginning of an LDPC code with a code length N of 1800 bits.

In this case, according to groupwise interleaving with GW pattern 4,2,0,3,1, the 1800-bit LDPC code {x ₀ ,x ₁ ,...,x ₁₇₉₉ } becomes {x ₁₄₄₀ ,x ₁₄₄₁ , ...,x ₁₇₉₉ },{x ₇₂₀ ,x ₇₂₁ ,...,x ₁₀₇₉ },{x ₀ ,x ₁ ,...,x ₃₅₉ },{x ₁₀₈₀ ,x ₁₀₈₁ ,...,x ₁₄₃₉ }, {x ₃₆₀ ,x ₃₆₁ ,...,x ₇₁₉ } are interleaved.

The GW pattern can be set for each code length N of the LDPC code, for each coding rate r, for each modulation method, for each constellation, or for two or more of the code length N, coding rate r, modulation method, and constellation. Can be set for each combination.

<Example of GW pattern for LDPC code>

FIG. 111 is a diagram showing a first example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 111, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
12, 8, 132, 26, 3, 18, 19, 98, 37, 190, 123, 81, 95, 167, 76, 66, 27, 46, 105, 28, 29, 170, 20, 96, 35, 177, 24, 86, 114, 63, 52, 80, 119, 153, 121, 107, 97, 129, 57, 38, 15, 91, 122, 14, 104, 175, 150, 1, 124, 72, 90, 32, 161, 78, 44, 73, 134, 162, 5, 11, 179, 93, 6, 152, 180, 68, 36, 103, 160, 100, 138, 146, 9, 82, 187, 147, 7, 87, 17, 102, 69, 110, 130, 42, 16, 71, 2, 169, 58, 33, 136, 106, 140, 84, 79, 143, 156, 139, 55, 116, 4, 21, 144, 64, 70, 158, 48, 118, 184, 50, 181, 120, 174, 133, 115, 53, 127, 74, 25, 49, 88, 22, 89, 34, 126, 61, 94, 172, 131, 39, 99, 183, 163, 111, 155, 51, 191, 31, 128, 149, 56, 85, 109, 10, 151, 188, 40, 83, 41, 47, 178, 186, 43, 54, 164, 13, 142, 117, 92, 113, 182, 168, 165, 101, 171, 159, 60, 166, 77, 30, 67, 23, 0, 65, 141, 185, 112, 145, 135, 108, 176, 45, 148, 137, 125, 62, 75, 189, 59, 173, 154, 157
are interleaved with each other.

FIG. 112 is a diagram showing a second example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 112, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
14, 119, 182, 5, 127, 21, 152, 11, 39, 164, 25, 69, 59, 140, 73, 9, 104, 148, 77, 44, 138, 89, 184, 35, 112, 150, 178, 26, 123, 133, 91, 76, 70, 0, 176, 118, 22, 147, 96, 108, 109, 139, 18, 157, 181, 126, 174, 179, 116, 38, 45, 158, 106, 168, 10, 97, 114, 129, 180, 52, 7, 67, 43, 50, 120, 122, 3, 13, 72, 185, 34, 83, 124, 105, 162, 87, 131, 155, 135, 42, 64, 165, 41, 71, 189, 159, 143, 102, 153, 17, 24, 30, 66, 137, 62, 55, 48, 98, 110, 40, 121, 187, 74, 92, 60, 101, 57, 33, 130, 173, 32, 166, 128, 54, 99, 111, 100, 16, 84, 132, 161, 4, 190, 49, 95, 141, 28, 85, 61, 53, 183, 6, 68, 2, 163, 37, 103, 186, 154, 171, 170, 78, 117, 93, 8, 145, 51, 56, 191, 90, 82, 151, 115, 175, 1, 125, 79, 20, 80, 36, 169, 46, 167, 63, 177, 149, 81, 12, 156, 142, 31, 47, 88, 65, 134, 94, 86, 160, 172, 19, 23, 136, 58, 146, 15, 75, 107, 188, 29, 113, 144, 27
are interleaved with each other.

FIG. 113 is a diagram showing a third example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 113, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
121, 28, 49, 4, 21, 191, 90, 101, 188, 126, 8, 131, 81, 150, 141, 152, 17, 82, 61, 119, 125, 145, 153, 45, 108, 22, 94, 48, 29, 12, 59, 140, 75, 169, 183, 157, 142, 158, 113, 79, 89, 186, 112, 80, 56, 120, 166, 15, 43, 2, 62, 115, 38, 123, 73, 179, 155, 171, 185, 5, 168, 172, 190, 106, 174, 96, 116, 91, 30, 147, 19, 149, 37, 175, 124, 156, 14, 144, 86, 110, 40, 68, 162, 66, 130, 74, 165, 180, 13, 177, 122, 23, 109, 95, 42, 117, 65, 3, 111, 18, 32, 52, 97, 184, 54, 46, 167, 136, 1, 134, 189, 187, 16, 36, 84, 132, 170, 34, 57, 24, 137, 100, 39, 127, 6, 102, 10, 25, 114, 146, 53, 99, 85, 35, 78, 148, 9, 143, 139, 92, 173, 27, 11, 26, 104, 176, 98, 129, 51, 103, 160, 71, 154, 118, 67, 33, 181, 87, 77, 47, 159, 178, 83, 70, 164, 44, 69, 88, 63, 161, 182, 133, 20, 41, 64, 76, 31, 50, 128, 105, 0, 135, 55, 72, 93, 151, 107, 163, 60, 138, 7, 58
are interleaved with each other.

FIG. 114 is a diagram showing a fourth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 114, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
99, 59, 95, 50, 122, 15, 144, 6, 129, 36, 175, 159, 165, 35, 182, 181, 189, 29, 2, 115, 91, 41, 60, 160, 51, 106, 168, 173, 20, 138, 183, 70, 24, 127, 47, 5, 119, 171, 102, 135, 116, 156, 120, 105, 117, 136, 149, 128, 85, 46, 186, 113, 73, 103, 52, 82, 89, 184, 22, 185, 155, 125, 133, 37, 27, 10, 137, 76, 12, 98, 148, 109, 42, 16, 190, 84, 94, 97, 25, 11, 88, 166, 131, 48, 161, 65, 9, 8, 58, 56, 124, 68, 54, 3, 169, 146, 87, 108, 110, 121, 163, 57, 90, 100, 66, 49, 61, 178, 18, 7, 28, 67, 13, 32, 34, 86, 153, 112, 63, 43, 164, 132, 118, 93, 38, 39, 17, 154, 170, 81, 141, 191, 152, 111, 188, 147, 180, 75, 72, 26, 177, 126, 179, 55, 1, 143, 45, 21, 40, 123, 23, 162, 77, 62, 134, 158, 176, 31, 69, 114, 142, 19, 96, 101, 71, 30, 140, 187, 92, 80, 79, 0, 104, 53, 145, 139, 14, 33, 74, 157, 150, 44, 172, 151, 64, 78, 130, 83, 167, 4, 107, 174
are interleaved with each other.

FIG. 115 is a diagram showing a fifth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 115, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
170, 45, 67, 94, 110, 153, 19, 38, 112, 176, 49, 138, 35, 114, 184, 159, 17, 41, 47, 189, 65, 125, 154, 57, 83, 6, 97, 167, 51, 59, 23, 81, 54, 46, 168, 178, 148, 5, 122, 129, 155, 179, 95, 102, 8, 119, 29, 113, 14, 60, 43, 66, 55, 103, 111, 88, 56, 7, 118, 63, 134, 108, 61, 187, 124, 31, 133, 22, 79, 52, 36, 144, 89, 177, 40, 116, 121, 135, 163, 92, 117, 162, 149, 106, 173, 181, 11, 164, 185, 99, 18, 158, 16, 12, 48, 9, 123, 147, 145, 169, 130, 183, 28, 151, 71, 126, 69, 165, 21, 13, 15, 62, 80, 182, 76, 90, 180, 50, 127, 131, 109, 3, 115, 120, 161, 82, 34, 78, 128, 142, 136, 75, 86, 137, 26, 25, 44, 91, 42, 73, 140, 146, 152, 27, 101, 93, 20, 166, 171, 100, 70, 84, 53, 186, 24, 98, 4, 37, 141, 190, 68, 150, 1, 72, 39, 87, 188, 191, 156, 33, 30, 160, 143, 64, 132, 77, 0, 58, 174, 157, 105, 175, 10, 172, 104, 2, 96, 139, 32, 85, 107, 74
are interleaved with each other.

FIG. 116 is a diagram showing a sixth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 116, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
111, 156, 189, 11, 132, 114, 100, 154, 77, 79, 95, 161, 47, 142, 36, 98, 3, 125, 159, 120, 40, 160, 29, 153, 16, 39, 101, 58, 191, 46, 76, 4, 183, 176, 62, 60, 74, 7, 37, 127, 19, 186, 71, 50, 139, 27, 188, 113, 38, 130, 124, 26, 146, 131, 102, 110, 105, 147, 86, 150, 94, 162, 175, 88, 104, 55, 89, 181, 34, 69, 22, 92, 133, 1, 25, 0, 158, 10, 24, 116, 164, 165, 112, 72, 106, 129, 81, 66, 54, 49, 136, 118, 83, 41, 2, 56, 145, 28, 177, 168, 117, 9, 157, 173, 115, 149, 42, 103, 14, 84, 155, 187, 99, 6, 43, 70, 140, 73, 32, 78, 75, 167, 148, 48, 134, 178, 59, 15, 63, 91, 82, 33, 135, 166, 190, 152, 96, 137, 12, 182, 61, 107, 128, 119, 179, 45, 184, 65, 172, 138, 31, 57, 174, 17, 180, 5, 30, 170, 23, 85, 185, 35, 44, 123, 90, 20, 122, 8, 64, 141, 169, 121, 97, 108, 80, 171, 18, 13, 87, 163, 109, 52, 51, 21, 93, 67, 126, 68, 53, 143, 144, 151
are interleaved with each other.

FIG. 117 is a diagram showing a seventh example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 117, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124 , 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149 , 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174 , 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191
are interleaved with each other.

FIG. 118 is a diagram showing an eighth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 118, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124 , 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149 , 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174 , 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191
are interleaved with each other.

FIG. 119 is a diagram showing a ninth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 119, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124 , 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149 , 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174 , 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191
are interleaved with each other.

FIG. 120 is a diagram showing a tenth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 120, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124 , 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149 , 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174 , 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191
are interleaved with each other.

FIG. 121 is a diagram showing an eleventh example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 121, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124 , 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149 , 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174 , 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191
are interleaved with each other.

FIG. 122 is a diagram showing a twelfth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 122, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124 , 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149 , 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174 , 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191
are interleaved with each other.

FIG. 123 is a diagram showing a thirteenth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 123, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124 , 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149 , 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174 , 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191
are interleaved with each other.

FIG. 124 is a diagram showing a fourteenth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 124, the order of bit groups 0 to 191 of the 69120-bit LDPC code is
154, 106, 99, 177, 191, 55, 189, 181, 22, 62, 80, 114, 110, 141, 83, 103, 169, 156, 130, 186, 92, 45, 68, 126, 112, 185, 160, 158, 17, 145, 162, 127, 152, 174, 134, 18, 157, 120, 3, 29, 13, 135, 173, 86, 73, 150, 46, 153, 33, 61, 142, 102, 171, 168, 78, 77, 139, 85, 176, 163, 128, 101, 42, 2, 14, 38, 10, 125, 90, 30, 63, 172, 47, 108, 89, 0, 32, 94, 23, 34, 59, 35, 129, 12, 146, 8, 60, 27, 147, 180, 100, 87, 184, 167, 36, 79, 138, 4, 95, 148, 72, 54, 91, 182, 28, 133, 164, 175, 123, 107, 137, 88, 44, 116, 69, 7, 31, 124, 144, 105, 170, 6, 165, 15, 161, 24, 58, 70, 11, 56, 143, 111, 104, 74, 67, 109, 82, 21, 52, 9, 71, 48, 26, 117, 50, 149, 140, 20, 57, 136, 113, 64, 151, 190, 131, 19, 51, 96, 76, 1, 97, 40, 53, 84, 166, 75, 159, 98, 81, 49, 66, 188, 118, 39, 132, 187, 25, 119, 41, 122, 16, 5, 93, 115, 178, 65, 121, 37, 155, 183, 43, 179
are interleaved with each other.

FIG. 125 is a diagram showing a fifteenth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 125, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
1, 182, 125, 0, 121, 47, 63, 154, 76, 99, 82, 163, 102, 166, 28, 189, 56, 67, 54, 39, 40, 185, 184, 65, 179, 4, 91, 87, 137, 170, 98, 71, 169, 49, 73, 37, 11, 143, 150, 123, 93, 62, 3, 50, 26, 140, 178, 95, 183, 33, 21, 53, 112, 128, 118, 120, 106, 139, 32, 130, 173, 132, 156, 119, 83, 176, 159, 13, 145, 36, 30, 113, 2, 41, 147, 174, 94, 88, 92, 60, 165, 59, 25, 161, 100, 85, 81, 61, 138, 48, 177, 77, 6, 22, 16, 43, 115, 23, 12, 66, 70, 9, 164, 122, 58, 105, 69, 42, 38, 19, 24, 180, 175, 74, 160, 34, 101, 72, 114, 142, 20, 8, 15, 190, 144, 104, 79, 172, 148, 31, 168, 10, 107, 14, 35, 52, 134, 126, 167, 149, 116, 186, 17, 162, 151, 5, 136, 55, 44, 110, 158, 46, 191, 29, 153, 155, 117, 188, 131, 97, 146, 103, 78, 109, 129, 57, 111, 45, 68, 157, 84, 141, 89, 64, 7, 108, 152, 75, 18, 96, 133, 171, 86, 181, 127, 27, 124, 187, 135, 80, 51, 90
are interleaved with each other.

FIG. 126 is a diagram showing a 16th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 126, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
35, 75, 166, 145, 143, 184, 62, 96, 54, 63, 157, 103, 32, 43, 126, 187, 144, 91, 78, 44, 39, 109, 185, 102, 10, 68, 29, 42, 149, 83, 133, 94, 130, 27, 171, 19, 51, 165, 148, 28, 36, 33, 173, 136, 87, 82, 100, 49, 120, 152, 161, 162, 147, 71, 137, 57, 8, 53, 132, 151, 163, 123, 47, 92, 90, 60, 99, 79, 59, 108, 115, 72, 0, 12, 140, 160, 61, 180, 74, 37, 86, 117, 191, 101, 52, 15, 80, 156, 127, 81, 131, 141, 142, 31, 95, 4, 73, 64, 16, 18, 146, 70, 181, 7, 89, 124, 77, 67, 116, 21, 34, 41, 105, 113, 97, 2, 6, 55, 17, 65, 38, 48, 158, 159, 179, 5, 30, 183, 170, 135, 125, 20, 106, 186, 182, 188, 114, 1, 14, 3, 134, 178, 189, 167, 40, 119, 22, 190, 58, 23, 155, 138, 98, 84, 11, 110, 88, 46, 177, 175, 25, 150, 118, 121, 129, 168, 13, 128, 104, 69, 112, 169, 9, 45, 174, 93, 26, 56, 76, 50, 154, 139, 66, 85, 153, 107, 111, 172, 176, 164, 24, 122
are interleaved with each other.

FIG. 127 is a diagram showing a seventeenth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 127, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
155, 188, 123, 132, 15, 79, 59, 119, 66, 68, 41, 175, 184, 78, 142, 32, 54, 111, 139, 134, 95, 34, 161, 150, 58, 141, 74, 112, 121, 99, 178, 179, 57, 90, 80, 21, 11, 29, 67, 104, 52, 87, 38, 81, 181, 160, 176, 16, 71, 13, 186, 171, 9, 170, 2, 177, 0, 88, 149, 190, 69, 33, 183, 146, 61, 117, 113, 6, 96, 120, 162, 23, 53, 140, 91, 128, 46, 93, 174, 126, 159, 133, 8, 152, 103, 102, 151, 143, 100, 4, 180, 166, 55, 164, 18, 49, 62, 20, 83, 7, 187, 153, 64, 37, 144, 185, 19, 114, 25, 116, 12, 173, 122, 127, 89, 115, 75, 101, 189, 124, 157, 108, 28, 165, 163, 65, 168, 77, 82, 27, 137, 86, 22, 110, 63, 148, 158, 97, 31, 105, 135, 98, 44, 70, 182, 191, 17, 156, 129, 39, 136, 169, 3, 145, 154, 109, 76, 5, 10, 106, 35, 94, 172, 45, 51, 60, 42, 50, 72, 85, 40, 118, 36, 14, 130, 131, 138, 43, 48, 125, 84, 24, 26, 1, 56, 107, 92, 147, 47, 30, 73, 167
are interleaved with each other.

FIG. 128 is a diagram showing an 18th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 128, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
152, 87, 170, 33, 48, 95, 2, 184, 145, 51, 94, 164, 38, 90, 158, 70, 124, 128, 66, 111, 79, 42, 45, 141, 83, 73, 57, 119, 20, 67, 31, 179, 123, 183, 26, 188, 15, 163, 1, 133, 105, 72, 81, 153, 69, 182, 101, 180, 185, 190, 77, 6, 127, 138, 75, 59, 24, 175, 30, 186, 139, 56, 100, 176, 147, 189, 116, 131, 25, 5, 16, 117, 74, 50, 171, 114, 76, 44, 107, 135, 71, 181, 13, 43, 122, 78, 4, 58, 35, 63, 187, 98, 37, 169, 148, 7, 10, 49, 80, 161, 167, 28, 142, 46, 97, 92, 121, 112, 88, 102, 106, 173, 19, 27, 41, 172, 91, 191, 34, 118, 108, 136, 166, 155, 96, 3, 165, 103, 84, 109, 104, 53, 23, 0, 178, 17, 86, 9, 168, 134, 110, 18, 32, 146, 129, 159, 55, 154, 126, 40, 151, 174, 60, 52, 22, 149, 156, 113, 143, 11, 93, 62, 177, 64, 61, 160, 150, 65, 130, 82, 29, 115, 137, 36, 8, 157, 54, 89, 99, 120, 68, 21, 140, 14, 39, 132, 125, 12, 85, 162, 47, 144
are interleaved with each other.

FIG. 129 is a diagram showing a nineteenth example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 129, the order of bit groups 0 to 191 of the 69120-bit LDPC code is
140, 8, 176, 13, 41, 165, 27, 109, 121, 153, 58, 181, 143, 164, 103, 115, 91, 66, 60, 189, 101, 4, 14, 102, 45, 124, 104, 159, 130, 133, 135, 77, 25, 59, 180, 141, 144, 62, 114, 182, 134, 148, 11, 20, 125, 83, 162, 75, 126, 67, 9, 178, 171, 152, 166, 69, 174, 15, 80, 168, 131, 95, 56, 48, 63, 82, 147, 51, 108, 52, 30, 139, 22, 37, 173, 112, 191, 98, 116, 149, 167, 142, 29, 154, 92, 94, 71, 117, 79, 122, 129, 24, 81, 105, 97, 137, 128, 1, 113, 170, 119, 7, 158, 76, 19, 183, 68, 31, 50, 118, 33, 72, 55, 65, 146, 185, 111, 145, 28, 21, 177, 160, 32, 61, 70, 106, 156, 78, 132, 88, 184, 35, 5, 53, 138, 47, 100, 10, 42, 36, 175, 93, 120, 190, 16, 123, 87, 54, 186, 18, 57, 84, 99, 12, 163, 157, 188, 64, 38, 26, 2, 136, 40, 169, 90, 107, 46, 172, 49, 6, 39, 44, 150, 85, 0, 17, 127, 155, 110, 34, 96, 74, 86, 187, 89, 151, 43, 179, 161, 73, 23, 3
are interleaved with each other.

FIG. 130 is a diagram showing a 20th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 130, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
10, 61, 30, 88, 33, 60, 1, 102, 45, 103, 119, 181, 82, 112, 12, 67, 69, 171, 108, 26, 145, 156, 81, 152, 8, 16, 68, 13, 99, 183, 146, 27, 158, 147, 132, 118, 180, 120, 173, 59, 186, 49, 7, 17, 35, 104, 129, 75, 54, 72, 18, 48, 15, 177, 191, 51, 24, 93, 106, 22, 71, 29, 141, 32, 143, 128, 175, 86, 190, 74, 36, 43, 144, 46, 63, 65, 133, 31, 87, 44, 20, 117, 76, 187, 80, 101, 151, 47, 130, 116, 162, 127, 153, 100, 94, 2, 41, 138, 125, 131, 11, 50, 40, 21, 184, 167, 172, 85, 160, 105, 73, 38, 157, 53, 39, 97, 107, 165, 168, 89, 148, 126, 3, 4, 114, 161, 155, 182, 136, 149, 111, 98, 113, 139, 92, 109, 174, 185, 95, 56, 135, 37, 163, 154, 0, 96, 78, 122, 5, 179, 140, 83, 123, 77, 9, 19, 66, 42, 137, 14, 23, 159, 189, 110, 142, 84, 169, 166, 52, 91, 164, 28, 124, 121, 70, 115, 90, 170, 58, 6, 178, 176, 64, 188, 57, 34, 79, 62, 25, 134, 150, 55
are interleaved with each other.

FIG. 131 is a diagram showing a 21st example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 131, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
8, 165, 180, 182, 189, 61, 7, 140, 105, 78, 86, 75, 15, 28, 82, 1, 136, 130, 35, 24, 70, 152, 121, 11, 36, 66, 83, 57, 164, 111, 137, 128, 175, 156, 151, 48, 44, 147, 18, 64, 184, 42, 159, 3, 6, 162, 170, 98, 101, 29, 102, 21, 188, 79, 138, 45, 124, 118, 155, 125, 34, 27, 5, 97, 109, 145, 54, 56, 126, 187, 16, 149, 160, 178, 23, 141, 30, 117, 25, 69, 116, 131, 94, 65, 191, 99, 181, 185, 115, 67, 93, 106, 38, 71, 76, 113, 132, 172, 103, 95, 92, 107, 4, 163, 139, 72, 157, 0, 12, 52, 68, 88, 161, 183, 39, 14, 32, 49, 19, 77, 174, 47, 154, 17, 134, 133, 51, 120, 74, 177, 41, 108, 142, 143, 13, 26, 59, 100, 123, 55, 158, 62, 104, 148, 135, 9, 179, 53, 176, 33, 169, 129, 186, 43, 167, 87, 119, 84, 90, 150, 20, 10, 122, 114, 80, 50, 146, 144, 96, 171, 40, 73, 81, 168, 112, 190, 37, 173, 46, 110, 60, 85, 153, 2, 63, 91, 127, 89, 31, 58, 22, 166
are interleaved with each other.

FIG. 132 is a diagram showing a 22nd example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 132, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
17, 84, 125, 70, 134, 63, 68, 162, 61, 31, 74, 137, 7, 138, 5, 60, 76, 105, 160, 12, 114, 81, 155, 112, 153, 191, 82, 148, 118, 108, 58, 159, 43, 161, 149, 96, 71, 30, 145, 174, 67, 77, 47, 94, 48, 156, 151, 141, 131, 176, 183, 41, 35, 83, 164, 55, 169, 98, 187, 124, 100, 54, 104, 40, 2, 72, 8, 85, 182, 103, 6, 37, 107, 39, 42, 123, 57, 106, 13, 150, 129, 46, 109, 188, 45, 113, 44, 90, 20, 165, 142, 110, 22, 28, 173, 38, 52, 16, 34, 0, 3, 144, 27, 49, 139, 177, 132, 184, 25, 87, 152, 119, 158, 78, 186, 167, 97, 24, 99, 69, 120, 122, 133, 163, 21, 51, 101, 185, 111, 26, 18, 10, 33, 170, 95, 65, 14, 130, 157, 59, 115, 127, 92, 56, 1, 80, 66, 126, 178, 147, 75, 179, 171, 53, 146, 88, 4, 128, 121, 86, 117, 19, 23, 168, 181, 11, 102, 93, 73, 140, 89, 136, 9, 180, 62, 36, 79, 91, 190, 143, 29, 154, 32, 64, 166, 116, 15, 189, 175, 50, 135, 172
are interleaved with each other.

FIG. 133 is a diagram showing a 23rd example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 133, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
157, 20, 116, 115, 49, 178, 148, 152, 174, 130, 171, 81, 60, 146, 182, 72, 46, 22, 93, 101, 9, 55, 40, 163, 118, 30, 52, 181, 151, 31, 87, 117, 120, 82, 95, 190, 23, 36, 67, 62, 14, 167, 80, 27, 24, 43, 94, 0, 63, 5, 74, 78, 158, 88, 84, 109, 147, 112, 124, 110, 21, 47, 45, 68, 184, 70, 1, 66, 149, 105, 140, 170, 56, 98, 135, 61, 79, 123, 166, 185, 41, 108, 122, 92, 16, 26, 37, 177, 173, 113, 136, 89, 162, 85, 54, 39, 73, 58, 131, 134, 188, 127, 3, 164, 13, 132, 129, 179, 25, 18, 57, 32, 119, 111, 53, 155, 28, 107, 133, 144, 19, 160, 71, 186, 153, 103, 2, 12, 91, 106, 64, 175, 75, 189, 128, 142, 187, 76, 180, 34, 59, 169, 90, 11, 172, 97, 141, 38, 191, 17, 114, 126, 145, 83, 143, 125, 121, 10, 44, 137, 86, 29, 104, 154, 168, 65, 159, 15, 99, 35, 50, 48, 138, 96, 100, 102, 7, 42, 156, 8, 4, 69, 183, 51, 165, 6, 150, 77, 161, 33, 176, 139
are interleaved with each other.

FIG. 134 is a diagram showing a 24th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 134, the order of bit groups 0 to 191 of the 69120-bit LDPC code is
42, 168, 36, 37, 152, 118, 14, 83, 105, 131, 26, 120, 92, 130, 158, 132, 49, 72, 137, 100, 88, 24, 53, 142, 110, 102, 74, 188, 113, 121, 12, 173, 5, 126, 127, 3, 93, 46, 164, 109, 151, 2, 98, 153, 116, 89, 101, 136, 35, 80, 0, 133, 183, 162, 185, 56, 17, 87, 117, 184, 54, 70, 176, 91, 134, 51, 38, 73, 165, 99, 169, 43, 167, 86, 11, 144, 78, 58, 64, 13, 119, 33, 166, 6, 75, 31, 15, 28, 125, 148, 27, 114, 82, 45, 55, 191, 160, 115, 1, 69, 187, 122, 177, 32, 172, 52, 112, 171, 124, 180, 85, 150, 7, 57, 60, 94, 181, 29, 97, 128, 19, 149, 175, 50, 140, 10, 174, 68, 59, 39, 106, 44, 62, 71, 18, 107, 156, 159, 146, 48, 81, 111, 96, 103, 34, 161, 141, 154, 76, 61, 135, 20, 84, 77, 108, 23, 145, 182, 170, 139, 157, 47, 9, 63, 123, 138, 155, 79, 4, 30, 143, 25, 90, 66, 147, 186, 179, 129, 21, 65, 41, 95, 67, 22, 163, 190, 16, 8, 104, 189, 40, 178
are interleaved with each other.

FIG. 135 is a diagram showing a 25th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 135, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
92, 132, 39, 44, 190, 21, 70, 146, 48, 13, 17, 187, 119, 43, 94, 157, 150, 98, 96, 47, 86, 63, 152, 158, 84, 170, 81, 7, 62, 191, 174, 99, 116, 10, 85, 113, 135, 28, 53, 122, 83, 141, 77, 23, 131, 4, 40, 168, 129, 109, 51, 130, 188, 147, 29, 50, 26, 78, 148, 164, 167, 103, 36, 134, 2, 177, 20, 123, 27, 90, 176, 5, 33, 133, 189, 138, 76, 41, 89, 35, 72, 139, 32, 73, 68, 67, 101, 166, 93, 54, 52, 42, 110, 59, 8, 179, 34, 171, 143, 137, 9, 126, 155, 108, 142, 120, 163, 12, 3, 75, 159, 107, 65, 128, 87, 6, 22, 57, 100, 24, 64, 106, 117, 19, 58, 95, 74, 180, 125, 136, 186, 154, 121, 161, 88, 37, 114, 102, 105, 160, 80, 185, 82, 124, 184, 15, 16, 18, 118, 173, 151, 11, 91, 79, 46, 140, 127, 1, 169, 0, 61, 66, 45, 162, 149, 115, 144, 30, 25, 175, 153, 183, 60, 38, 31, 111, 182, 49, 55, 145, 56, 181, 104, 14, 71, 178, 112, 172, 165, 69, 97, 156
are interleaved with each other.

FIG. 136 is a diagram showing a 26th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 136, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
133, 96, 46, 148, 78, 109, 149, 161, 55, 39, 183, 54, 186, 73, 150, 180, 189, 190, 22, 135, 12, 80, 42, 130, 164, 70, 126, 107, 57, 67, 15, 157, 52, 88, 5, 23, 123, 66, 53, 147, 177, 60, 131, 108, 171, 191, 44, 140, 98, 154, 37, 118, 176, 92, 124, 138, 132, 167, 173, 13, 79, 32, 145, 14, 113, 30, 2, 0, 165, 182, 153, 24, 144, 87, 82, 75, 141, 89, 137, 33, 100, 106, 128, 168, 29, 36, 172, 11, 111, 68, 16, 10, 34, 188, 35, 160, 77, 83, 178, 58, 59, 7, 56, 110, 104, 61, 76, 85, 121, 93, 19, 134, 179, 155, 163, 115, 185, 125, 112, 71, 8, 119, 18, 47, 151, 26, 103, 122, 9, 170, 146, 99, 49, 72, 102, 31, 40, 43, 158, 142, 4, 69, 139, 28, 174, 101, 84, 129, 156, 74, 62, 91, 159, 41, 38, 45, 136, 169, 21, 51, 181, 97, 166, 175, 90, 27, 86, 65, 105, 143, 127, 17, 6, 116, 94, 117, 48, 50, 25, 64, 95, 63, 184, 152, 120, 1, 187, 162, 114, 3, 81, 20
are interleaved with each other.

FIG. 137 is a diagram showing a 27th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 137, the order of bit groups 0 to 191 of the 69120-bit LDPC code is
59, 34, 129, 18, 137, 6, 83, 139, 47, 148, 147, 110, 11, 98, 62, 149, 158, 14, 42, 180, 23, 128, 99, 181, 54, 176, 35, 130, 53, 179, 39, 152, 32, 52, 69, 82, 84, 113, 79, 21, 95, 7, 126, 191, 86, 169, 111, 12, 55, 27, 182, 120, 123, 88, 107, 50, 144, 49, 38, 165, 0, 159, 10, 43, 114, 187, 150, 19, 65, 48, 124, 8, 141, 171, 173, 17, 167, 92, 74, 170, 184, 67, 33, 172, 16, 119, 66, 57, 89, 106, 26, 78, 178, 109, 70, 2, 157, 15, 105, 22, 174, 127, 100, 71, 97, 163, 9, 77, 87, 41, 183, 117, 46, 40, 131, 85, 136, 72, 122, 1, 45, 13, 44, 56, 61, 146, 25, 132, 177, 76, 121, 160, 112, 5, 134, 73, 91, 135, 68, 3, 80, 90, 190, 60, 75, 145, 115, 81, 161, 156, 116, 166, 96, 28, 138, 94, 162, 140, 102, 4, 133, 30, 155, 189, 143, 64, 185, 164, 104, 142, 154, 118, 24, 31, 153, 103, 51, 108, 29, 37, 58, 186, 175, 36, 151, 63, 93, 188, 125, 101, 20, 168
are interleaved with each other.

FIG. 138 is a diagram showing a 28th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 138, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
61, 110, 123, 127, 148, 162, 131, 71, 176, 22, 157, 0, 151, 155, 112, 189, 36, 181, 10, 46, 133, 75, 80, 88, 6, 165, 97, 54, 31, 174, 49, 139, 98, 4, 170, 26, 50, 16, 141, 187, 13, 109, 106, 120, 72, 32, 63, 59, 79, 172, 83, 100, 92, 24, 56, 130, 167, 81, 103, 111, 158, 159, 153, 175, 8, 41, 136, 70, 33, 45, 84, 150, 39, 166, 164, 99, 126, 190, 134, 40, 87, 64, 154, 140, 116, 184, 115, 183, 30, 35, 7, 42, 146, 86, 58, 12, 14, 149, 89, 179, 128, 160, 95, 171, 74, 25, 29, 119, 143, 178, 28, 21, 23, 90, 188, 96, 173, 93, 147, 191, 18, 62, 2, 132, 20, 11, 17, 135, 152, 67, 73, 108, 76, 91, 156, 104, 48, 121, 94, 125, 38, 65, 177, 68, 37, 124, 78, 118, 186, 34, 185, 113, 169, 9, 69, 82, 163, 114, 145, 168, 44, 52, 105, 51, 137, 1, 161, 3, 55, 182, 101, 57, 43, 77, 5, 47, 144, 180, 66, 53, 19, 117, 60, 138, 142, 107, 122, 85, 27, 129, 15, 102
are interleaved with each other.

FIG. 139 is a diagram showing a 29th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 139, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
8, 174, 121, 46, 70, 106, 183, 9, 96, 109, 72, 130, 47, 168, 1, 190, 18, 90, 103, 135, 105, 112, 23, 33, 185, 31, 171, 111, 0, 115, 4, 159, 25, 65, 134, 146, 26, 37, 16, 169, 167, 74, 67, 155, 154, 83, 117, 53, 19, 161, 76, 12, 7, 131, 59, 51, 189, 42, 114, 142, 126, 66, 164, 191, 55, 132, 35, 153, 137, 87, 5, 100, 122, 150, 2, 49, 32, 172, 149, 177, 15, 82, 98, 34, 140, 170, 56, 78, 188, 57, 118, 186, 181, 52, 71, 24, 81, 22, 11, 156, 86, 148, 97, 38, 48, 64, 40, 165, 180, 125, 127, 143, 88, 43, 61, 158, 28, 162, 187, 110, 84, 157, 27, 41, 39, 124, 85, 58, 20, 44, 102, 36, 77, 147, 120, 179, 21, 60, 92, 138, 119, 173, 160, 144, 91, 99, 107, 101, 145, 184, 108, 95, 69, 63, 3, 89, 128, 136, 94, 129, 50, 79, 68, 151, 104, 163, 123, 182, 93, 29, 133, 152, 178, 80, 62, 54, 14, 141, 166, 176, 45, 30, 10, 6, 75, 73, 116, 175, 17, 113, 139, 13
are interleaved with each other.

FIG. 140 is a diagram showing a 30th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 140, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
179, 91, 101, 128, 169, 69, 185, 35, 156, 168, 132, 163, 46, 28, 5, 41, 162, 112, 108, 130, 153, 79, 118, 102, 125, 176, 71, 20, 115, 98, 124, 75, 103, 21, 164, 173, 9, 36, 56, 134, 24, 16, 159, 34, 15, 42, 104, 54, 120, 76, 60, 33, 127, 88, 133, 137, 61, 19, 3, 170, 87, 190, 13, 141, 188, 106, 113, 67, 145, 146, 111, 74, 89, 62, 175, 49, 32, 99, 93, 107, 171, 66, 80, 155, 100, 152, 4, 10, 126, 109, 181, 154, 105, 48, 136, 161, 183, 97, 31, 12, 8, 184, 47, 142, 18, 14, 117, 73, 84, 70, 68, 0, 23, 96, 165, 29, 122, 81, 17, 131, 44, 157, 26, 25, 189, 83, 178, 37, 123, 82, 191, 39, 7, 72, 160, 64, 143, 149, 138, 65, 58, 119, 63, 166, 114, 95, 172, 43, 140, 57, 158, 186, 86, 174, 92, 45, 139, 144, 147, 148, 151, 59, 30, 85, 40, 51, 187, 78, 38, 150, 129, 121, 27, 94, 52, 177, 110, 182, 55, 22, 167, 90, 77, 6, 11, 1, 116, 53, 2, 50, 135, 180
are interleaved with each other.

FIG. 141 is a diagram showing a 31st example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 141, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
99, 59, 95, 50, 122, 15, 144, 6, 129, 36, 175, 159, 165, 35, 182, 181, 189, 29, 2, 115, 91, 41, 60, 160, 51, 106, 168, 173, 20, 138, 183, 70, 24, 127, 47, 5, 119, 171, 102, 135, 116, 156, 120, 105, 117, 136, 149, 128, 85, 46, 186, 113, 73, 103, 52, 82, 89, 184, 22, 185, 155, 125, 133, 37, 27, 10, 137, 76, 12, 98, 148, 109, 42, 16, 190, 84, 94, 97, 25, 11, 88, 166, 131, 48, 161, 65, 9, 8, 58, 56, 124, 68, 54, 3, 169, 146, 87, 108, 110, 121, 163, 57, 90, 100, 66, 49, 61, 178, 18, 7, 28, 67, 13, 32, 34, 86, 153, 112, 63, 43, 164, 132, 118, 93, 38, 39, 17, 154, 170, 81, 141, 191, 152, 111, 188, 147, 180, 75, 72, 26, 177, 126, 179, 55, 1, 143, 45, 21, 40, 123, 23, 162, 77, 62, 134, 158, 176, 31, 69, 114, 142, 19, 96, 101, 71, 30, 140, 187, 92, 80, 79, 0, 104, 53, 145, 139, 14, 33, 74, 157, 150, 44, 172, 151, 64, 78, 130, 83, 167, 4, 107, 174
are interleaved with each other.

FIG. 142 is a diagram showing a 32nd example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 142, the order of bit groups 0 to 191 of the 69120-bit LDPC code is
16, 133, 14, 114, 145, 191, 53, 80, 166, 68, 21, 184, 73, 165, 147, 89, 180, 55, 135, 94, 189, 78, 103, 115, 72, 24, 105, 188, 84, 148, 85, 32, 1, 131, 34, 134, 41, 167, 81, 54, 142, 141, 75, 155, 122, 140, 13, 17, 8, 23, 61, 49, 51, 74, 181, 162, 143, 42, 71, 123, 161, 177, 110, 149, 126, 0, 63, 178, 35, 175, 186, 52, 43, 139, 112, 10, 40, 150, 182, 164, 64, 83, 174, 38, 47, 30, 2, 116, 25, 128, 160, 144, 99, 5, 187, 176, 82, 60, 18, 185, 104, 169, 39, 183, 137, 22, 109, 96, 151, 46, 33, 29, 65, 132, 95, 31, 136, 159, 170, 168, 67, 79, 93, 111, 90, 97, 113, 92, 76, 58, 127, 26, 27, 156, 3, 6, 28, 77, 125, 173, 98, 138, 172, 86, 45, 118, 171, 62, 179, 100, 19, 163, 50, 57, 56, 36, 102, 121, 117, 154, 119, 66, 20, 91, 130, 69, 44, 70, 153, 152, 158, 88, 108, 12, 59, 4, 11, 120, 87, 101, 37, 129, 146, 9, 106, 48, 7, 15, 124, 190, 107, 157
are interleaved with each other.

FIG. 143 is a diagram showing a 33rd example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 143, the order of bit groups 0 to 191 of the 69120-bit LDPC code is
178, 39, 54, 68, 122, 20, 86, 137, 156, 55, 52, 72, 130, 152, 147, 12, 69, 48, 107, 44, 88, 23, 181, 174, 124, 81, 59, 93, 22, 46, 82, 110, 3, 99, 75, 36, 38, 119, 131, 51, 115, 78, 84, 33, 163, 11, 2, 188, 161, 34, 89, 50, 8, 90, 109, 136, 77, 103, 67, 41, 149, 176, 134, 189, 159, 184, 153, 53, 129, 63, 160, 139, 150, 169, 148, 127, 25, 175, 142, 98, 56, 144, 102, 94, 101, 85, 132, 76, 5, 177, 0, 128, 45, 162, 92, 62, 133, 30, 17, 9, 61, 70, 154, 4, 146, 24, 135, 104, 13, 185, 79, 138, 31, 112, 1, 49, 113, 106, 100, 65, 10, 83, 73, 26, 58, 114, 66, 126, 117, 96, 186, 14, 40, 164, 158, 118, 29, 121, 151, 168, 183, 179, 16, 105, 125, 190, 116, 165, 80, 64, 170, 140, 171, 173, 97, 60, 43, 123, 71, 182, 167, 95, 145, 141, 187, 166, 87, 143, 15, 74, 111, 157, 32, 172, 18, 57, 35, 191, 27, 47, 21, 6, 19, 155, 42, 120, 180, 37, 28, 91, 108, 7
are interleaved with each other.

FIG. 144 is a diagram showing a 34th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 144, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
139, 112, 159, 99, 87, 70, 175, 161, 51, 56, 174, 143, 12, 36, 77, 60, 155, 167, 160, 73, 127, 82, 123, 145, 8, 76, 164, 178, 144, 86, 7, 124, 27, 187, 130, 162, 191, 182, 16, 106, 141, 38, 72, 179, 111, 29, 59, 183, 66, 52, 43, 121, 20, 11, 190, 92, 55, 166, 94, 138, 1, 122, 171, 119, 109, 58, 23, 31, 163, 53, 13, 188, 100, 158, 156, 136, 34, 118, 185, 10, 25, 126, 104, 30, 83, 47, 146, 63, 134, 39, 21, 44, 151, 28, 22, 79, 110, 71, 90, 2, 103, 42, 35, 5, 57, 4, 0, 107, 37, 54, 18, 128, 148, 129, 26, 75, 120, 19, 116, 117, 147, 114, 48, 96, 61, 46, 88, 67, 135, 65, 180, 9, 74, 176, 6, 149, 49, 50, 125, 64, 169, 168, 157, 153, 24, 108, 89, 98, 33, 132, 93, 40, 154, 62, 142, 41, 69, 105, 189, 115, 152, 45, 133, 3, 95, 17, 186, 184, 85, 165, 32, 173, 113, 172, 78, 181, 150, 170, 102, 97, 140, 81, 91, 15, 137, 101, 80, 68, 14, 177, 131, 84
are interleaved with each other.

FIG. 145 is a diagram showing a 35th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 145, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
21, 20, 172, 86, 178, 25, 104, 133, 17, 106, 191, 68, 80, 190, 129, 29, 125, 108, 147, 23, 94, 167, 27, 61, 12, 166, 131, 120, 159, 28, 7, 62, 134, 59, 78, 0, 121, 149, 6, 5, 143, 171, 153, 161, 186, 35, 92, 113, 55, 163, 16, 54, 93, 79, 37, 44, 75, 182, 127, 148, 179, 95, 169, 141, 38, 168, 128, 56, 31, 57, 175, 140, 164, 24, 177, 88, 51, 112, 49, 185, 170, 87, 32, 60, 65, 77, 89, 3, 18, 116, 184, 45, 109, 53, 160, 9, 100, 8, 111, 69, 189, 36, 173, 33, 72, 144, 183, 115, 137, 98, 90, 142, 30, 154, 180, 122, 155, 130, 83, 138, 14, 41, 150, 132, 70, 152, 117, 11, 4, 124, 15, 42, 181, 58, 10, 22, 145, 99, 126, 107, 66, 174, 39, 13, 97, 63, 123, 84, 85, 67, 76, 158, 71, 46, 118, 81, 162, 146, 135, 2, 73, 50, 114, 82, 103, 188, 74, 101, 157, 151, 91, 119, 102, 48, 1, 40, 43, 64, 156, 34, 110, 52, 96, 136, 139, 165, 19, 176, 187, 47, 26, 105
are interleaved with each other.

FIG. 146 is a diagram showing a 36th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 146, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
160, 7, 29, 39, 110, 189, 140, 143, 163, 130, 173, 71, 191, 106, 60, 62, 149, 135, 9, 147, 124, 152, 55, 116, 85, 112, 14, 20, 79, 103, 156, 167, 19, 45, 73, 26, 159, 44, 86, 76, 56, 12, 109, 117, 128, 67, 150, 151, 31, 27, 133, 17, 120, 153, 108, 180, 52, 187, 98, 63, 176, 186, 179, 113, 161, 32, 24, 111, 41, 95, 38, 10, 154, 97, 141, 2, 127, 40, 105, 34, 11, 185, 155, 61, 114, 74, 158, 162, 5, 177, 43, 51, 148, 137, 28, 181, 171, 13, 104, 42, 168, 93, 172, 144, 80, 123, 89, 81, 68, 75, 78, 121, 53, 65, 122, 142, 157, 107, 136, 66, 90, 23, 8, 1, 77, 54, 125, 174, 35, 88, 82, 134, 101, 131, 33, 50, 87, 36, 15, 47, 83, 18, 6, 21, 30, 94, 72, 145, 138, 184, 69, 84, 58, 49, 16, 48, 70, 183, 3, 92, 25, 115, 0, 182, 139, 91, 146, 102, 96, 100, 119, 129, 178, 46, 37, 57, 118, 126, 59, 165, 170, 190, 188, 175, 166, 99, 4, 22, 132, 164, 64, 169
are interleaved with each other.

FIG. 147 is a diagram showing a 37th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 147, the order of bit groups 0 to 191 of the 69120-bit LDPC code is
167, 97, 86, 166, 11, 57, 187, 169, 104, 102, 108, 63, 12, 181, 1, 71, 134, 152, 45, 144, 124, 22, 0, 51, 100, 150, 179, 54, 66, 79, 25, 172, 59, 48, 23, 55, 64, 185, 164, 123, 56, 80, 153, 9, 177, 176, 81, 17, 14, 43, 76, 27, 175, 60, 133, 91, 61, 41, 111, 163, 72, 95, 84, 67, 129, 52, 88, 121, 7, 49, 168, 154, 74, 138, 142, 158, 132, 127, 40, 139, 20, 44, 6, 128, 75, 114, 119, 2, 8, 157, 98, 118, 89, 46, 160, 190, 5, 165, 28, 68, 189, 161, 112, 173, 148, 183, 33, 131, 105, 186, 156, 70, 117, 170, 174, 36, 19, 135, 125, 122, 50, 113, 141, 37, 38, 31, 94, 149, 78, 32, 178, 34, 107, 13, 182, 146, 93, 10, 106, 109, 4, 77, 87, 3, 184, 83, 30, 180, 96, 15, 155, 110, 145, 191, 151, 101, 65, 99, 115, 140, 26, 147, 42, 136, 137, 18, 53, 116, 171, 16, 21, 92, 162, 130, 85, 69, 47, 35, 82, 120, 24, 73, 39, 58, 62, 126, 29, 90, 143, 159, 188, 103
are interleaved with each other.

FIG. 148 is a diagram showing a 38th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 148, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
74, 151, 79, 49, 174, 180, 133, 106, 116, 16, 163, 62, 164, 45, 187, 128, 176, 2, 126, 136, 63, 28, 118, 173, 19, 46, 93, 121, 162, 88, 0, 147, 131, 54, 117, 138, 69, 182, 68, 143, 78, 15, 7, 59, 109, 32, 10, 179, 165, 90, 73, 71, 171, 135, 123, 125, 31, 22, 70, 185, 155, 60, 120, 113, 41, 154, 177, 85, 64, 55, 26, 129, 84, 38, 166, 44, 30, 183, 189, 191, 124, 77, 80, 98, 190, 167, 140, 52, 153, 43, 25, 188, 103, 152, 137, 76, 149, 34, 172, 122, 40, 168, 141, 96, 142, 58, 110, 65, 9, 36, 42, 50, 184, 105, 156, 127, 8, 61, 146, 169, 181, 5, 87, 150, 91, 17, 18, 24, 112, 81, 170, 95, 29, 100, 130, 48, 159, 72, 75, 160, 27, 108, 148, 66, 144, 97, 57, 115, 114, 1, 132, 4, 21, 92, 11, 107, 175, 67, 145, 14, 186, 20, 51, 39, 3, 86, 89, 47, 53, 102, 82, 139, 23, 104, 157, 99, 158, 12, 161, 35, 178, 37, 134, 83, 94, 101, 111, 119, 6, 33, 13, 56
are interleaved with each other.

FIG. 149 is a diagram showing a 39th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 149, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
20, 118, 185, 106, 82, 53, 41, 40, 121, 180, 45, 10, 145, 175, 191, 160, 177, 172, 13, 29, 133, 42, 89, 51, 141, 99, 7, 134, 52, 48, 169, 162, 124, 25, 165, 128, 95, 148, 98, 171, 14, 75, 59, 26, 76, 47, 34, 122, 69, 131, 105, 60, 132, 63, 81, 109, 43, 189, 19, 186, 79, 62, 85, 54, 16, 46, 27, 44, 139, 113, 11, 102, 130, 184, 119, 1, 152, 146, 37, 178, 61, 150, 32, 163, 92, 166, 142, 67, 140, 157, 188, 18, 87, 149, 65, 183, 161, 5, 31, 71, 173, 73, 15, 138, 156, 28, 66, 170, 179, 135, 86, 39, 104, 17, 154, 174, 56, 153, 0, 97, 9, 72, 23, 167, 190, 80, 3, 38, 120, 4, 24, 159, 12, 103, 22, 125, 83, 50, 6, 77, 168, 74, 93, 49, 57, 147, 2, 155, 181, 96, 114, 107, 110, 30, 117, 127, 101, 94, 129, 35, 58, 70, 126, 182, 151, 111, 91, 64, 88, 144, 137, 143, 176, 84, 136, 8, 112, 123, 164, 115, 78, 36, 90, 100, 55, 108, 21, 158, 68, 33, 116, 187
are interleaved with each other.

FIG. 150 is a diagram showing a 40th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 150, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
42, 43, 190, 119, 183, 103, 51, 28, 171, 20, 18, 25, 85, 22, 157, 99, 174, 5, 53, 62, 150, 128, 38, 153, 37, 148, 39, 24, 118, 102, 184, 49, 111, 48, 87, 76, 81, 40, 55, 82, 70, 105, 66, 115, 14, 86, 88, 135, 168, 139, 56, 80, 93, 95, 165, 13, 4, 100, 29, 104, 11, 72, 116, 83, 112, 67, 186, 169, 8, 57, 44, 17, 164, 31, 96, 84, 2, 125, 59, 3, 6, 173, 149, 78, 27, 160, 156, 187, 34, 129, 154, 79, 52, 117, 110, 0, 7, 113, 137, 26, 47, 12, 178, 46, 136, 97, 15, 188, 101, 58, 35, 71, 32, 16, 109, 163, 134, 75, 68, 98, 132, 90, 124, 189, 121, 123, 170, 158, 159, 77, 108, 63, 180, 36, 74, 127, 21, 146, 147, 54, 155, 10, 144, 130, 60, 1, 141, 23, 177, 133, 50, 126, 167, 151, 161, 191, 91, 114, 162, 30, 181, 182, 9, 94, 69, 176, 65, 142, 152, 175, 73, 140, 41, 179, 172, 145, 64, 19, 138, 131, 166, 33, 107, 185, 106, 122, 120, 92, 45, 143, 61, 89
are interleaved with each other.

FIG. 151 is a diagram showing a 41st example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 151, the order of bit groups 0 to 191 of the 69120-bit LDPC code is
111, 33, 21, 133, 18, 30, 73, 139, 125, 35, 77, 105, 122, 91, 41, 86, 11, 8, 55, 71, 151, 107, 45, 12, 168, 51, 50, 59, 7, 132, 144, 16, 190, 31, 108, 89, 124, 110, 94, 67, 159, 46, 140, 87, 54, 142, 185, 85, 84, 120, 178, 101, 180, 20, 174, 47, 28, 145, 70, 24, 131, 4, 83, 56, 79, 37, 27, 109, 92, 52, 96, 177, 141, 188, 155, 38, 156, 169, 136, 81, 137, 112, 95, 93, 106, 149, 138, 15, 39, 170, 146, 103, 184, 43, 5, 9, 189, 34, 19, 63, 90, 36, 23, 78, 100, 75, 162, 42, 161, 119, 64, 65, 152, 62, 173, 104, 88, 118, 48, 44, 40, 60, 102, 61, 74, 99, 53, 10, 6, 172, 186, 163, 134, 14, 148, 3, 26, 1, 157, 150, 25, 123, 115, 116, 57, 175, 127, 82, 117, 114, 160, 164, 153, 176, 76, 13, 181, 68, 128, 0, 183, 49, 22, 166, 17, 191, 135, 165, 72, 158, 130, 154, 167, 66, 2, 147, 69, 58, 98, 97, 143, 32, 29, 179, 113, 80, 182, 129, 126, 171, 121, 187
are interleaved with each other.

FIG. 152 is a diagram showing a 42nd example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 152, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
148, 32, 94, 31, 146, 15, 41, 7, 79, 58, 52, 167, 154, 4, 161, 38, 64, 127, 131, 78, 34, 125, 171, 173, 133, 122, 50, 95, 129, 57, 71, 37, 137, 69, 82, 107, 26, 10, 140, 156, 47, 178, 163, 117, 139, 174, 143, 138, 111, 11, 166, 43, 141, 114, 45, 39, 177, 103, 96, 123, 63, 23, 18, 20, 187, 27, 66, 130, 65, 142, 5, 135, 113, 90, 121, 54, 190, 134, 153, 147, 92, 157, 3, 97, 102, 106, 172, 91, 46, 89, 56, 184, 115, 99, 62, 93, 100, 88, 152, 109, 124, 182, 70, 74, 159, 165, 60, 183, 185, 164, 175, 108, 176, 2, 118, 72, 151, 0, 51, 33, 28, 80, 14, 128, 179, 84, 77, 42, 55, 160, 119, 110, 86, 22, 101, 13, 170, 36, 104, 189, 191, 169, 112, 12, 29, 30, 162, 136, 24, 68, 9, 81, 120, 145, 180, 144, 73, 21, 44, 1, 16, 67, 19, 158, 188, 181, 61, 35, 8, 53, 168, 150, 105, 59, 87, 6, 126, 75, 85, 17, 83, 98, 48, 132, 40, 76, 49, 25, 149, 186, 155, 116
are interleaved with each other.

FIG. 153 is a diagram showing a 43rd example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 153, the order of bit groups 0 to 191 of the 69120-bit LDPC code is
161, 38, 41, 138, 20, 24, 14, 35, 32, 179, 68, 97, 94, 142, 43, 53, 22, 28, 44, 81, 148, 187, 169, 89, 115, 144, 75, 40, 31, 152, 30, 124, 80, 135, 160, 8, 129, 147, 60, 112, 171, 0, 133, 100, 156, 180, 77, 110, 151, 69, 95, 25, 117, 127, 154, 64, 146, 143, 29, 168, 177, 183, 126, 10, 26, 3, 50, 92, 164, 163, 11, 109, 21, 37, 84, 122, 49, 71, 52, 15, 88, 149, 86, 61, 90, 155, 162, 9, 153, 67, 119, 189, 82, 131, 190, 4, 46, 118, 47, 178, 59, 150, 186, 123, 18, 79, 57, 120, 70, 62, 137, 23, 185, 167, 175, 16, 134, 73, 139, 166, 55, 165, 116, 76, 99, 182, 78, 93, 141, 33, 176, 101, 130, 58, 12, 17, 132, 45, 102, 7, 19, 145, 54, 91, 113, 36, 27, 114, 174, 39, 83, 140, 191, 74, 56, 87, 48, 158, 121, 159, 136, 63, 181, 34, 173, 103, 42, 125, 104, 107, 96, 65, 1, 13, 157, 184, 170, 105, 188, 108, 6, 2, 98, 72, 5, 66, 128, 106, 172, 111, 85, 51
are interleaved with each other.

FIG. 154 is a diagram showing a 44th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 154, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
57, 73, 173, 63, 179, 186, 148, 181, 160, 163, 4, 109, 137, 99, 118, 15, 5, 115, 44, 153, 185, 40, 12, 169, 2, 37, 188, 97, 65, 67, 117, 90, 66, 135, 154, 159, 146, 86, 61, 182, 59, 83, 91, 175, 58, 138, 93, 43, 98, 22, 152, 96, 45, 120, 180, 10, 116, 170, 162, 68, 3, 13, 41, 131, 21, 172, 55, 24, 1, 79, 106, 189, 52, 184, 112, 53, 136, 166, 29, 62, 107, 128, 71, 111, 187, 161, 101, 49, 155, 28, 94, 70, 48, 0, 33, 157, 151, 25, 89, 88, 114, 134, 75, 87, 142, 6, 27, 64, 69, 19, 150, 38, 35, 130, 127, 76, 102, 123, 158, 129, 133, 110, 141, 95, 7, 126, 85, 108, 174, 190, 165, 156, 171, 54, 17, 121, 103, 14, 36, 105, 82, 8, 178, 51, 23, 84, 167, 30, 100, 42, 72, 149, 92, 77, 104, 183, 39, 125, 80, 143, 144, 56, 119, 16, 132, 139, 191, 50, 164, 122, 46, 140, 31, 176, 60, 26, 32, 11, 177, 124, 74, 145, 20, 34, 18, 81, 168, 9, 78, 113, 147, 47
are interleaved with each other.

FIG. 155 is a diagram showing a 45th example of a GW pattern for an LDPC code with a code length N of 69120 bits.

According to the GW pattern in Figure 155, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is
89, 123, 13, 47, 178, 159, 1, 190, 53, 12, 57, 109, 115, 19, 36, 143, 82, 96, 163, 66, 154, 173, 49, 65, 131, 2, 78, 15, 155, 90, 38, 130, 63, 188, 138, 184, 166, 102, 139, 28, 50, 186, 17, 20, 112, 41, 11, 8, 59, 79, 45, 162, 146, 40, 43, 129, 119, 18, 157, 37, 126, 124, 110, 191, 85, 165, 60, 142, 135, 74, 187, 179, 141, 164, 34, 69, 26, 33, 113, 120, 95, 169, 30, 0, 175, 70, 91, 104, 140, 25, 132, 23, 105, 158, 171, 6, 121, 56, 22, 127, 54, 68, 107, 133, 84, 81, 150, 99, 73, 185, 67, 29, 151, 87, 10, 167, 148, 72, 147, 5, 31, 125, 145, 4, 52, 44, 134, 83, 46, 75, 152, 62, 7, 86, 172, 180, 111, 61, 9, 58, 14, 116, 92, 170, 93, 77, 88, 42, 21, 106, 97, 144, 182, 108, 55, 94, 122, 114, 153, 64, 24, 80, 117, 3, 177, 149, 76, 128, 136, 39, 181, 160, 103, 174, 156, 27, 183, 16, 137, 101, 161, 176, 35, 118, 98, 168, 48, 100, 71, 189, 32, 51
are interleaved with each other.

The above first to forty-fifth examples of GW patterns for LDPC codes with a code length N of 69120 bits are an LDPC code with a code length N of 69120 bits and an arbitrary coding rate r, an arbitrary modulation method, and It can be applied to any combination of arbitrary constellations.

However, for groupwise interleaving, by setting the applied GW pattern for each combination of LDPC code code length N, LDPC code coding rate r, modulation method, and constellation, the error can be reduced for each combination. The rate can be further improved.

The GW pattern in FIG. 111 is, for example, the LDPC code (corresponding to the parity check matrix initial value table) of N=69120, r=2/16 in FIG. A particularly good error rate can be achieved by applying this to the combination of QPSK (LDPC code), QPSK, and QPSK-UC shown in FIGS. 96 and 97.

For example, the GW pattern in FIG. 112 can be applied to the combination of N=69120, r=3/16 LDPC code and QPSK in FIGS. 31 and 32, and QPSK-UC in FIGS. 96 and 97. , a good error rate can be achieved.

The GW pattern in FIG. 113 can be applied to the combination of the N=69120, r=4/16 LDPC code and QPSK in FIG. 33, and the QPSK-UC in FIGS. 96 and 97, for example. error rate can be achieved.

The GW pattern in FIG. 114 can be applied, for example, to the combination of N=69120, r=5/16 LDPC code and QPSK in FIGS. 34 and 35, and QPSK-UC in FIGS. 96 and 97. , a good error rate can be achieved.

The GW pattern in FIG. 115 can be applied to the combination of N=69120, r=6/16 LDPC code and QPSK in FIGS. 36 and 37, and QPSK-UC in FIGS. 96 and 97, for example. , a good error rate can be achieved.

For example, the GW pattern in FIG. 116 can be applied to the combination of N=69120, r=7/16 LDPC code and QPSK in FIGS. 38 and 39, and QPSK-UC in FIGS. 96 and 97. , a good error rate can be achieved.

The GW pattern in FIG. 117 can be applied to the combination of N=69120, r=8/16 LDPC code and QPSK in FIGS. 46 and 47, and QPSK-UC in FIGS. 96 and 97, for example. , a good error rate can be achieved.

The GW pattern in FIG. 118 can be applied to the combination of the N=69120, r=9/16 LDPC code and QPSK in FIGS. 50 to 52, and the QPSK-UC in FIGS. 96 and 97, for example. , a good error rate can be achieved.

The GW pattern in FIG. 119 can be applied, for example, to the combination of N=69120, r=10/16 LDPC code and QPSK in FIGS. 56 to 58, and QPSK-UC in FIGS. 96 and 97. , a good error rate can be achieved.

The GW pattern in FIG. 120 can be applied, for example, to the combination of N=69120, r=11/16 LDPC code and QPSK in FIGS. 62 to 64, and QPSK-UC in FIGS. 96 and 97. , a good error rate can be achieved.

The GW pattern in FIG. 121 can be applied, for example, to the combination of N=69120, r=12/16 LDPC code and QPSK in FIGS. 68 to 70, and QPSK-UC in FIGS. 96 and 97. , a good error rate can be achieved.

The GW pattern in FIG. 122 can be applied to the combination of the N=69120, r=13/16 LDPC code and QPSK in FIGS. 74 and 76, and the QPSK-UC in FIGS. 96 and 97, for example. , a good error rate can be achieved.

The GW pattern in FIG. 123 can be applied, for example, to the combination of N=69120, r=14/16 LDPC code and QPSK in FIGS. 80 to 82, and QPSK-UC in FIGS. 96 and 97. , a good error rate can be achieved.

For example, the GW pattern in FIG. 124 can be applied to the combination of N=69120, r=3/16 LDPC code and 16QAM in FIGS. 31 and 32, and 16QAM-UC in FIGS. 98 and 99. , a good error rate can be achieved.

The GW pattern in FIG. 125 can be applied, for example, to the combination of N=69120, r=5/16 LDPC code and 16QAM in FIGS. 34 and 35, and 16QAM-UC in FIGS. 98 and 99. , a good error rate can be achieved.

The GW pattern in FIG. 126 can be applied, for example, to the combination of N=69120, r=7/16 LDPC code and 16QAM in FIGS. 38 and 39, and 16QAM-UC in FIGS. 98 and 99. , a good error rate can be achieved.

The GW pattern in FIG. 127 can be applied, for example, to the combination of N=69120, r=9/16 LDPC code and 16QAM in FIGS. 50 to 52, and 16QAM-UC in FIGS. 98 and 99. , a good error rate can be achieved.

The GW pattern in FIG. 128 can be applied, for example, to the combination of N=69120, r=11/16 LDPC code and 16QAM in FIGS. 62 to 64, and 16QAM-UC in FIGS. 98 and 99. , a good error rate can be achieved.

The GW pattern in FIG. 129 can be applied, for example, to the combination of N=69120, r=13/16 LDPC code and 16QAM in FIGS. 74 to 76, and 16QAM-UC in FIGS. 98 and 99. , a good error rate can be achieved.

The GW pattern in FIG. 130 can be applied to the combination of the N=69120, r=2/16 LDPC code and 64QAM in FIG. 30, and the 64QAM-UC in FIGS. 100 and 101, for example. error rate can be achieved.

The GW pattern in FIG. 131 can be applied to the combination of the N=69120, r=4/16 LDPC code and 64QAM in FIG. 33, and the 64QAM-UC in FIGS. 100 and 101, for example. error rate can be achieved.

For example, the GW pattern in FIG. 132 can be applied to the combination of N=69120, r=6/16 LDPC code and 64QAM in FIGS. 36 and 37, and 64QAM-UC in FIGS. 100 and 101. , a good error rate can be achieved.

The GW pattern in FIG. 133 can be applied, for example, to the combination of N=69120, r=8/16 LDPC code and 64QAM in FIGS. 46 and 47, and 64QAM-UC in FIGS. 100 and 101. , a good error rate can be achieved.

The GW pattern in FIG. 134 can be applied, for example, to the combination of N=69120, r=10/16 LDPC code and 64QAM in FIGS. 56 to 58, and 64QAM-UC in FIGS. 100 and 101. , a good error rate can be achieved.

The GW pattern in FIG. 135 can be applied, for example, to the combination of N=69120, r=12/16 LDPC code and 64QAM in FIGS. 68 to 70, and 64QAM-UC in FIGS. 100 and 101. , a good error rate can be achieved.

The GW pattern in FIG. 136 can be applied, for example, to the combination of N=69120, r=14/16 LDPC code and 64QAM in FIGS. 80 to 82, and 64QAM-UC in FIGS. 100 and 101. , a good error rate can be achieved.

The GW pattern in FIG. 137 can be applied, for example, to the combination of N=69120, r=3/16 LDPC code and 256QAM in FIGS. 31 and 32, and 256QAM-UC in FIGS. 102 and 103. , a good error rate can be achieved.

For example, the GW pattern in FIG. 138 can be applied to the combination of N=69120, r=5/16 LDPC code and 256QAM in FIGS. 34 and 35, and 256QAM-UC in FIGS. 102 and 103. , a good error rate can be achieved.

The GW pattern in FIG. 139 can be applied, for example, to the combination of N=69120, r=7/16 LDPC code and 256QAM in FIGS. 38 and 39, and 256QAM-UC in FIGS. 102 and 103. , a good error rate can be achieved.

The GW pattern in FIG. 140 can be applied, for example, to the combination of N=69120, r=9/16 LDPC code and 256QAM in FIGS. 50 to 52, and 256QAM-UC in FIGS. 102 and 103. , a good error rate can be achieved.

The GW pattern in FIG. 141 can be applied, for example, to the combination of N=69120, r=11/16 LDPC code and 256QAM in FIGS. 62 to 64, and 256QAM-UC in FIGS. 102 and 103. , a good error rate can be achieved.

The GW pattern in FIG. 142 can be applied, for example, to the combination of N=69120, r=13/16 LDPC code and 256QAM in FIGS. 74 to 76, and 256QAM-UC in FIGS. 102 and 103. , a good error rate can be achieved.

The GW pattern in FIG. 143 can be applied to the combination of the N=69120, r=2/16 LDPC code and 1024QAM in FIG. 30, and the 1024QAM-UC in FIGS. 104 and 105, for example. error rate can be achieved.

The GW pattern in FIG. 144 can be applied to the combination of the N=69120, r=4/16 LDPC code and 1024QAM in FIG. 33, and the 1024QAM-UC in FIGS. 104 and 105, for example. error rate can be achieved.

For example, the GW pattern in FIG. 145 can be applied to the combination of N=69120, r=6/16 LDPC code and 1024QAM in FIGS. 36 and 37, and 1024QAM-UC in FIGS. 104 and 105. , a good error rate can be achieved.

The GW pattern in FIG. 146 can be applied to, for example, the combination of N=69120, r=8/16 LDPC code and 1024QAM in FIGS. 46 and 47, and 1024QAM-UC in FIGS. 104 and 105. , a good error rate can be achieved.

The GW pattern in FIG. 147 can be applied, for example, to the combination of N=69120, r=10/16 LDPC code and 1024QAM in FIGS. 56 to 58, and 1024QAM-UC in FIGS. 104 and 105. , a good error rate can be achieved.

The GW pattern in FIG. 148 can be applied, for example, to the combination of N=69120, r=12/16 LDPC code and 1024QAM in FIGS. 68 to 70, and 1024QAM-UC in FIGS. 104 and 105. , a good error rate can be achieved.

For example, the GW pattern in FIG. 149 can be applied to the combination of N=69120, r=14/16 LDPC code and 1024QAM in FIGS. 80 and 82, and 1024QAM-UC in FIGS. 104 and 105. , a good error rate can be achieved.

The GW pattern in FIG. 150 can be applied, for example, to the combination of N=69120, r=3/16 LDPC code and 4096QAM in FIGS. 31 and 32, and 4096QAM-UC in FIGS. 106 and 107. , a good error rate can be achieved.

For example, the GW pattern in FIG. 151 can be applied to the combination of N=69120, r=5/16 LDPC code and 4096QAM in FIGS. 34 and 35, and 4096QAM-UC in FIGS. 106 and 107. , a good error rate can be achieved.

For example, the GW pattern in FIG. 152 can be applied to the combination of N=69120, r=7/16 LDPC code and 4096QAM in FIGS. 38 and 39, and 4096QAM-UC in FIGS. 106 and 107. , a good error rate can be achieved.

The GW pattern in FIG. 153 can be applied, for example, to the combination of N=69120, r=9/16 LDPC code and 4096QAM in FIGS. 50 to 52, and 4096QAM-UC in FIGS. 106 and 107. , a good error rate can be achieved.

The GW pattern in FIG. 154 can be applied, for example, to the combination of N=69120, r=11/16 LDPC code and 4096QAM in FIGS. 62 and 64, and 4096QAM-UC in FIGS. 106 and 107. , a good error rate can be achieved.

For example, the GW pattern in FIG. 155 can be applied to the combination of N=69120, r=13/16 LDPC code and 4096QAM in FIGS. 74 and 76, and 4096QAM-UC in FIGS. 106 and 107. , a good error rate can be achieved.

<Example of configuration of receiving device 12>

FIG. 156 is a block diagram showing a configuration example of the receiving device 12 of FIG. 7.

An OFDM processing unit (OFDM operation) 151 receives an OFDM signal from the transmitting device 11 (FIG. 7) and performs signal processing on the OFDM signal. Data obtained by signal processing performed by the OFDM processing section 151 is supplied to a frame management section (Frame Management) 152.

The frame management unit 152 processes (frame interpretation) a frame composed of data supplied from the OFDM processing unit 151, and converts the resulting target data signal and control data signal into a frequency deinterleaver. (Frequency Deinterleaver) 161 and 153, respectively.

The frequency deinterleaver 153 performs frequency deinterleaving on the data from the frame management unit 152 on a symbol-by-symbol basis, and supplies the data to a demapper 154 .

The demapper 154 demaps (signal point arrangement) the data (data on a constellation) from the frequency deinterleaver 153 based on a signal point arrangement (constellation) determined by orthogonal modulation performed on the transmitter 11 side. decoding) and orthogonal demodulation, and the resulting data (LDPC code (likelihood)) is supplied to an LDPC decoder 155.

The LDPC decoder 155 performs LDPC decoding of the LDPC code from the demapper 154 and supplies the resulting LDPC target data (here, BCH code) to a BCH decoder 156.

The BCH decoder 156 performs BCH decoding of the LDPC target data from the LDPC decoder 155, and outputs control data (signaling) obtained as a result.

On the other hand, the frequency deinterleaver 161 performs frequency deinterleaving on the data from the frame management unit 152 on a symbol-by-symbol basis, and supplies the data to a SISO/MISO decoder 162 .

The SISO/MISO decoder 162 performs spatiotemporal decoding of the data from the frequency deinterleaver 161 and supplies it to a time deinterleaver 163.

The time deinterleaver 163 performs time deinterleaving on the data from the SISO/MISO decoder 162 on a symbol-by-symbol basis, and supplies the data to a demapper 164 .

The demapper 164 demaps (signal point arrangement) the data (data on a constellation) from the time deinterleaver 163 based on the signal point arrangement (constellation) determined by orthogonal modulation performed on the transmitter 11 side. decoding) and orthogonal demodulation, and the resulting data is supplied to a bit deinterleaver 165.

The bit deinterleaver 165 performs bit deinterleaving on the data from the demapper 164, and supplies (the likelihood of) the LDPC code, which is the data after the bit deinterleaving, to the LDPC decoder 166.

LDPC decoder 166 performs LDPC decoding of the LDPC code from bit deinterleaver 165 and supplies the resulting LDPC target data (here, BCH code) to BCH decoder 167 .

The BCH decoder 167 performs BCH decoding of the LDPC target data from the LDPC decoder 155 and supplies the resulting data to a BB descrambler 168.

The BB descrambler 168 performs BB descrambling on the data from the BCH decoder 167 and supplies the resulting data to a null deletion unit (Null Deletion) 169.

The null deletion unit 169 deletes the null inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168, and supplies the data to a demultiplexer 170.

The demultiplexer 170 separates each of one or more streams (target data) multiplexed with the data from the null deletion unit 169, performs necessary processing, and outputs the stream as an output stream.

Note that the receiving device 12 can be configured without providing some of the blocks illustrated in FIG. 156. That is, for example, when transmitting device 11 (FIG. 8) is configured without providing time interleaver 118, SISO/MISO encoder 119, frequency interleaver 120, and frequency interleaver 124, receiving device 12: A time deinterleaver 163, a SISO/MISO decoder 162, and a frequency deinterleaver 161 are blocks that respectively correspond to the time interleaver 118, SISO/MISO encoder 119, frequency interleaver 120, and frequency interleaver 124 of the transmitting device 11. , and can be configured without providing the frequency deinterleaver 153.

<Configuration example of bit deinterleaver 165>

FIG. 157 is a block diagram showing a configuration example of bit deinterleaver 165 in FIG. 156.

The bit deinterleaver 165 includes a block deinterleaver 54 and a groupwise deinterleaver 55, and performs (bit) deinterleaving of symbol bits of symbols that are data from the demapper 164 (FIG. 156).

That is, the block deinterleaver 54 performs block deinterleaving (inverse processing of block interleaving) corresponding to the block interleaving performed by the block interleaver 25 in FIG. Block deinterleaving is performed to return the position of (the likelihood of) code bits of the LDPC code rearranged by interleaving to the original position, and the resulting LDPC code is supplied to the groupwise deinterleaver 55.

The groupwise deinterleaver 55 performs groupwise deinterleaving (reverse processing of groupwise interleaving) corresponding to the groupwise interleaving performed by the groupwise interleaver 24 in FIG. 9 on the LDPC code from the block deinterleaver 54. That is, for example, groupwise deinterleaving is performed to restore the original order by rearranging the code bits of the LDPC code whose arrangement has been changed in bit group units by the groupwise interleaving described in FIG. 110 in bit group units.

Here, if the LDPC code supplied from the demapper 164 to the bit deinterleaver 165 has been subjected to parity interleaving, groupwise interleaving, and block interleaving, the bit deinterleaver 165 uses the parity code corresponding to the parity interleaving. Deinterleaving (the reverse process of parity interleaving, i.e., parity deinterleaving that returns the code bits of an LDPC code whose order has been changed by parity interleaving to their original order), block deinterleaving corresponding to block interleaving, and groupwise interleaving All of the groupwise deinterleaving that corresponds to can be performed.

However, in the bit deinterleaver 165 in FIG. 157, the block deinterleaver 54 that performs block deinterleaving corresponding to block interleaving and the groupwise deinterleaver 55 that performs groupwise deinterleaving corresponding to groupwise interleaving are as follows. However, a block for performing parity deinterleaving corresponding to parity interleaving is not provided, and parity deinterleaving is not performed.

Therefore, from the bit deinterleaver 165 (the groupwise deinterleaver 55 of the bit deinterleaver 55), the LDPC decoder 166 receives the LDPC code that has undergone block deinterleaving and groupwise deinterleaving, and has not undergone parity deinterleaving. is supplied.

The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 and performs column permutation corresponding to parity interleaving on the type B check matrix H used by the LDPC encoder 115 in FIG. 8 for LDPC encoding. The conversion check matrix obtained by performing at least Output as data decryption result.

FIG. 158 is a flowchart illustrating the processing performed by the demapper 164, bit deinterleaver 165, and LDPC decoder 166 in FIG. 157.

In step S111, the demapper 164 demaps and orthogonally demodulates the data from the time deinterleaver 163 (data on the constellation mapped to the signal points), supplies it to the bit deinterleaver 165, and performs processing. , proceed to step S112.

In step S112, the bit deinterleaver 165 deinterleaves (bit deinterleave) the data from the demapper 164, and the process proceeds to step S113.

That is, in step S112, the block deinterleaver 54 in the bit deinterleaver 165 performs block deinterleaving on the data (symbols) from the demapper 164, and divides the code bits of the resulting LDPC code into groups. The signal is supplied to the wide deinterleaver 55.

Groupwise deinterleaver 55 performs groupwise deinterleaving on the LDPC code from block deinterleaver 54 and supplies (the likelihood of) the LDPC code obtained as a result to LDPC decoder 166 .

In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the groupwise deinterleaver 55 using the parity check matrix H used for LDPC encoding by the LDPC encoder 115 in FIG. This is performed using the conversion check matrix obtained from matrix H, and the resulting data is output to the BCH decoder 167 as the decoding result of the LDPC target data.

Note that in FIG. 157, as in the case of FIG. 9, for convenience of explanation, the block deinterleaver 54 that performs block deinterleaving and the groupwise deinterleaver 55 that performs groupwise deinterleaving are configured separately. However, the block deinterleaver 54 and the groupwise deinterleaver 55 can be configured integrally.

Further, when the transmitting device 11 does not perform groupwise interleaving, the receiving device 12 can be configured without providing the groupwise deinterleaver 55 that performs groupwise deinterleaving.

<LDPC decoding>

LDPC decoding performed by LDPC decoder 166 in FIG. 156 will be further described.

In the LDPC decoder 166 of FIG. 156, as described above, the LDPC code of the LDPC code is subjected to block deinterleaving and groupwise deinterleaving from the groupwise deinterleaver 55, and is not subjected to parity deinterleaving. For decoding, the LDPC encoder 115 in FIG. 8 performs at least column permutation corresponding to parity interleaving on the type B type check matrix H used for LDPC encoding, or a type A type check matrix. This is performed using a transformation check matrix (FIG. 29) obtained by performing row permutation on the matrix (FIG. 27).

Here, LDPC decoding has been previously proposed, which makes it possible to suppress the circuit scale and the operating frequency within a sufficiently feasible range by performing LDPC decoding using a transformation check matrix (for example, , see Patent No. 4224777).

First, the previously proposed LDPC decoding using a transformation check matrix will be described with reference to FIGS. 159 to 162.

FIG. 159 is a diagram showing an example of a parity check matrix H of an LDPC code with a code length N of 90 and a coding rate of 2/3.

Note that in FIG. 159 (the same applies to FIGS. 160 and 161 described later), 0 is expressed as a period (.).

In check matrix H in FIG. 159, the parity matrix has a staircase structure.

FIG. 160 is a diagram showing a parity check matrix H' obtained by subjecting the parity check matrix H of FIG. 159 to the row permutation of equation (11) and the column permutation of equation (12).

Line replacement: 6s+t+1st line → 5t+s+1st line
...(11)

Column replacement: 6x+y+61st column → 5y+x+61st column
...(12)

However, in formulas (11) and (12), s, t, x, and y are integers in the range of 0≦s<5, 0≦t<6, 0≦x<5, 0≦t<6, respectively. It is.

According to the row permutation in equation (11), the 1st, 7th, 13th, 19th, and 25th lines, which have a remainder of 1 when divided by 6, are replaced by 6 in the 1st, 2nd, 3rd, 4th, and 5th lines, respectively. The 2nd, 8th, 14th, 20th, and 26th lines, where the remainder is 2, are replaced with the 6th, 7th, 8th, 9th, and 10th lines, respectively, and so on.

Also, according to the column permutation of equation (12), for the 61st column and subsequent columns (parity matrix), the 61st, 67th, 73rd, 79th, and 85th columns whose remainder is 1 when divided by 6 are 61st, 67th, 73rd, 79th, and 85th columns, respectively. , 62, 63, 64, and 65th columns, and the 62nd, 68th, 74th, 80th, and 86th columns, which have a remainder of 2 when divided by 6, are the 66th, 67th, 68th, 69th, and 70th columns, respectively. The replacement will be performed accordingly.

The matrix obtained by permuting the rows and columns of the parity check matrix H in FIG. 159 in this way is the parity check matrix H' in FIG. 160.

Here, even if row permutation of parity check matrix H is performed, the arrangement of code bits of the LDPC code is not affected.

In addition, the column permutation of equation (12) is performed by using the information length K This corresponds to parity interleaving when the unit size P is 60, the unit size P is 5, and the divisor q (=M/P) of the parity length M (here, 30) is 6.

Therefore, the check matrix H' in FIG. 160 is the K+Py+x+1st column of the check matrix H in FIG. 159 (hereinafter referred to as the original check matrix). This is a transformation check matrix obtained by performing at least column permutation to replace the columns of .

When the transformed check matrix H′ in FIG. 160 is multiplied by the LDPC code of the original check matrix H in FIG. 159 that has been permuted in the same manner as in equation (12), a zero vector is output. In other words, if we represent the row vector obtained by performing the column permutation of equation (12) on the row vector c as the LDPC code (one code word) of the original parity check matrix H as c', then from the properties of the parity check matrix , Hc ^T are zero vectors, so naturally H'c' ^T is also a zero vector.

From the above, the converted parity check matrix H' in FIG. 160 is a parity check matrix of the LDPC code c' obtained by performing column permutation of equation (12) on the LDPC code c of the original parity check matrix H.

Therefore, the column permutation of equation (12) is performed on the LDPC code c of the original parity check matrix H, and the LDPC code c' after the column permutation is decoded using the transformed parity check matrix H' of FIG. 160 (LDPC decoding). Then, by applying the inverse column permutation of equation (12) to the decoding result, it is possible to obtain the same decoding result as when decoding the LDPC code of the original parity check matrix H using that parity check matrix H. I can do it.

FIG. 161 is a diagram showing the transformation check matrix H′ of FIG. 160, which is spaced in units of 5×5 matrices.

In FIG. 161, the conversion check matrix H' is a 5×5 (=P×P) unit matrix with unit size P, and a matrix in which one or more of the 1's in the unit matrix is 0 (hereinafter, as appropriate) , quasi-identity matrix), an identity matrix or a matrix obtained by cyclic shift of a quasi-identity matrix (hereinafter referred to as a shift matrix as appropriate), a sum of two or more of an identity matrix, a quasi-identity matrix, or a shift matrix (hereinafter referred to as a sum matrix) is expressed as a combination of 5×5 zero matrices.

It can be said that the transformation check matrix H' in FIG. 161 is composed of a 5×5 identity matrix, a quasi-identity matrix, a shift matrix, a sum matrix, and a 0 matrix. Therefore, these 5×5 matrices (identity matrix, quasi-identity matrix, shift matrix, sum matrix, and 0 matrix) that constitute the transformation check matrix H′ are hereinafter appropriately referred to as constituent matrices.

To decode an LDPC code of a parity check matrix represented by a P×P constituent matrix, an architecture that simultaneously performs P check node operations and variable node operations can be used.

FIG. 162 is a block diagram showing a configuration example of a decoding device that performs such decoding.

That is, in FIG. 162, the LDPC code is decoded using at least the transformed check matrix H' in FIG. 161 obtained by performing column permutation of equation (12) on the original check matrix H in FIG. 159. An example of the configuration of a decoding device is shown.

The decoding device in FIG. 162 includes an edge data storage memory 300 consisting of six FIFOs 300 ₁ to 300 ₆ , a selector 301 for selecting FIFOs 300 ₁ to 300 ₆ , a check node calculation unit 302 , two cyclic shift circuits 303 and 308 , A branch data storage memory 304 consisting of 18 FIFOs 304 ₁ to 304 ₁₈ , a selector 305 that selects FIFOs 304 ₁ to 304 ₁₈ , a received data memory 306 that stores received data, a variable node calculation section 307, and a decoded word calculation section 309. , a received data sorting section 310, and a decoded data sorting section 311.

First, a method of storing data in the edge data storage memories 300 and 304 will be explained.

The edge data storage memory 300 is composed of six FIFOs 300 ₁ to 300 ₆ , which is the number of rows 30 of the conversion check matrix H' in FIG. 161 divided by the number of rows of the constituent matrices (unit size P) 5. . The FIFO 300 _y (y = 1, 2, ..., 6) consists of storage areas with multiple stages, and the storage area of each stage is 5, which is the number of rows and columns (unit size P) of the constituent matrix. Messages corresponding to two branches can be read and written simultaneously. Further, the number of stages in the storage area of the FIFO 300 _y is 9, which is the maximum number of 1's (Hamming weight) in the row direction of the conversion parity check matrix in FIG. 161.

In the FIFO 300 ₁ , the data (message v _i from the variable node) corresponding to the 1 position from the 1st row to the 5th row of the conversion check matrix H' in FIG. 161 is packed horizontally in each row. It is stored in the form (ignoring 0). That is, if the j-th row and i-th column are expressed as (j,i), the first stage storage area of the FIFO 300 ₁ stores (1,1) to (5,5) of the conversion check matrix H'. Data corresponding to the 1 position of the 5×5 unit matrix is stored. The second stage storage area contains a shift matrix from (1,21) to (5,25) of the conversion check matrix H' (a shift matrix obtained by cyclically shifting a 5×5 unit matrix by three positions to the right) Data corresponding to position 1 is stored. Similarly, in the storage areas of the third to eighth stages, data is stored in association with the transformation check matrix H'. Then, in the storage area of the 9th stage, a shift matrix from (1,86) to (5,90) of the transformation check matrix H' (1 in the first row of the 5 × 5 unit matrix is replaced with 0) The data corresponding to the 1 position of the shift matrix (which is cyclically shifted by one position to the left) is stored.

The FIFO 300 ₂ stores data corresponding to the positions of 1 from the 6th row to the 10th row of the conversion check matrix H' in FIG. 161. That is, in the first stage storage area of FIFO 300 ₂ , the sum matrix (5 x 5 identity matrix cyclically shifted by one to the right) from (6,1) to (10,5) of the conversion check matrix H' is stored. The data corresponding to the position 1 of the first shift matrix constituting a sum matrix that is the sum of the first shift matrix that has been cyclically shifted to the right and the second shift matrix that has been cyclically shifted by two positions to the right is stored. In addition, the second stage storage area stores data corresponding to the position 1 of the second shift matrix that constitutes the sum matrix from (6,1) to (10,5) of the transformation check matrix H'. Ru.

In other words, for a constituent matrix with a weight of 2 or more, the constituent matrix is a P×P unit matrix with a weight of 1, a quasi-unit matrix in which one or more of the elements 1 of the unit matrix is 0, or Data corresponding to the position of 1 in the unit matrix, quasi-identity matrix, or shift matrix whose weight is 1 when expressed in the form of the sum of multiple shift matrices obtained by cyclically shifting the unit matrix or quasi-identity matrix. (Messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) are stored at the same address (the same FIFO among FIFOs 300 ₁ to 300 ₆ ).

Hereinafter, data is also stored in the third to ninth storage areas in association with the transformation parity check matrix H'.

FIFOs 300 ₃ to 300 ₆ also store data in association with the conversion check matrix H'.

The edge data storage memory 304 is composed of 18 FIFOs 304 ₁ to 304 ₁₈ obtained by dividing the number of columns of the conversion check matrix H′, 90, by 5, which is the number of columns of the constituent matrices (unit size P). The FIFO 304 _x (x = 1, 2, ..., 18) consists of storage areas with multiple stages, and the storage area of each stage is 5, which is the number of rows and columns (unit size P) of the constituent matrix. Messages corresponding to two branches can be read and written simultaneously.

In the FIFO 304 ₁ , the data (message u _j from the check node) corresponding to the 1 position from the 1st column to the 5th column of the conversion check matrix H' in FIG. 161 is packed vertically in each column. (ignoring 0). That is, the first stage storage area of the FIFO 304 ₁ stores data corresponding to position 1 of the 5×5 unit matrix from (1,1) to (5,5) of the conversion check matrix H'. . The second stage storage area contains the sum matrix (6,1) to (10,5) of the transformation check matrix H' (the first shift obtained by cyclically shifting the 5×5 identity matrix by one position to the right). Data corresponding to the position 1 of the first shift matrix constituting a sum matrix which is the sum of the matrix and the second shift matrix cyclically shifted by two positions to the right is stored. In addition, the third stage storage area stores data corresponding to the position 1 of the second shift matrix that constitutes the sum matrix from (6,1) to (10,5) of the transformation check matrix H'. Ru.

In other words, for a constituent matrix with a weight of 2 or more, the constituent matrix is a P×P unit matrix with a weight of 1, a quasi-unit matrix in which one or more of the elements 1 of the unit matrix is 0, or Data corresponding to the position of 1 in the unit matrix, quasi-identity matrix, or shift matrix whose weight is 1 when expressed in the form of the sum of multiple shift matrices obtained by cyclically shifting the unit matrix or quasi-identity matrix. (Messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) are stored at the same address (the same FIFO among FIFOs 304 ₁ to 304 ₁₈ ).

Thereafter, data is also stored in the storage areas of the fourth and fifth stages in association with the transformation parity check matrix H'. The number of stages of the storage area of this FIFO 304 ₁ is 5, which is the maximum number of 1's (Hamming weight) in the row direction in the first to fifth columns of the conversion check matrix H'.

The FIFOs 304 ₂ and 304 ₃ similarly store data in association with the conversion check matrix H', and each has a length (number of stages) of 5. Similarly, the FIFOs 304 ₄ to 304 ₁₂ store data in association with the conversion check matrix H', and each has a length of 3. Similarly, the FIFOs 304 ₁₃ to 304 ₁₈ store data in association with the conversion check matrix H', and each has a length of 2.

Next, the operation of the decoding device shown in FIG. 162 will be explained.

The edge data storage memory 300 is composed of six FIFOs 300 ₁ to 300 ₆ and is used to determine which row of the conversion check matrix H' in FIG. According to information (Matrix data) D312, a FIFO for storing data is selected from among FIFOs 300 ₁ to 300 ₆ , and five messages D311 are collectively stored in the selected FIFO in order. Furthermore, when reading data, the branch data storage memory 300 sequentially reads five messages D300 ₁ from the FIFO 300 ₁ and supplies them to the selector 301 at the next stage. After finishing reading messages from FIFO 300 ₁ , branch data storage memory 300 reads messages from FIFOs 300 ₂ to 300 ₆ in order and supplies them to selector 301 .

The selector 301 selects five messages from the FIFO from which data is currently being read out of the FIFOs 300 ₁ to 300 ₆ in accordance with the select signal D301, and supplies them to the check node calculation unit 302 as messages D302.

The check node calculation unit 302 consists of five check node calculators 302 ₁ to 302 ₅ , and uses messages D302 (D302 ₁ to D302 ₅ ) (message v _i in equation (7)) supplied through the selector 301 to calculate A check node operation is performed according to equation (7), and five messages D303 (D303 ₁ to D303 ₅ ) (message u _j of equation (7)) obtained as a result of the check node operation are supplied to the cyclic shift circuit 303.

The cyclic shift circuit 303 calculates the size of the five messages D303 ₁ to D303 ₅ obtained by the check node calculation unit 302 by how many unit matrices (or quasi-identity matrices) the corresponding edges are the source of in the transformation check matrix H'. The data is cyclically shifted based on the information (Matrix data) D305 as to whether it is click-shifted, and the result is supplied to the branch data storage memory 304 as a message D304.

The edge data storage memory 304 is made up of 18 FIFOs 304 ₁ to 304 ₁₈ , and is based on information D305 indicating to which row of the conversion check matrix H' the five messages D304 supplied from the cyclic shift circuit 303 in the previous stage belong. , a FIFO for storing data is selected from among FIFOs 304 ₁ to 304 ₁₈ , and five messages D 304 are collectively stored in the selected FIFO in order. Furthermore, when reading data, the branch data storage memory 304 sequentially reads five messages D306 ₁ from the FIFO 304 ₁ and supplies them to the selector 305 at the next stage. After the edge data storage memory 304 finishes reading data from the FIFO 304 ₁ , it also reads messages from the FIFOs 304 ₂ to 304 ₁₈ in order and supplies them to the selector 305 .

The selector 305 selects five messages from the FIFO from which data is currently being read out of the FIFOs 304 ₁ to 304 ₁₈ according to the select signal D307, and sends them to the variable node calculation unit 307 and the decoded word calculation unit as a message D308. 309.

On the other hand, the received data rearranging unit 310 rearranges the LDPC code D313 corresponding to the parity check matrix H in FIG. The data is supplied to the received data memory 306. The reception data memory 306 calculates and stores reception LLRs (log-likelihood ratios) from the reception data D314 supplied from the reception data rearrangement section 310, and collects five reception LLRs as reception values D309. , are supplied to the variable node calculation unit 307 and the decoded word calculation unit 309.

The variable node calculation unit 307 consists of five variable node calculators 307 ₁ to 307 ₅ , and receives the message D308 (D308 ₁ to D308 ₅ ) (message u _j in equation (1)) supplied through the selector 305 and the received data. Using the five received values D309 (received value u _0i of formula (1)) supplied from the memory 306, variable node calculation is performed according to formula (1), and the message D310 (D310 _{1 to D310 1} to D310 ₅ ) (message v _i of equation (1)) is supplied to the cyclic shift circuit 308 .

The cyclic shift circuit 308 cyclically shifts the messages D310 ₁ to D310 ₅ calculated by the variable node calculation unit 307 by how many unit matrices (or quasi-unit matrices) the corresponding branches are the source in the transformed check matrix H'. The data is cyclically shifted based on the information as to whether the data is the same or not, and the result is supplied to the edge data storage memory 300 as a message D311.

By repeating the above operations once, the LDPC code can be decoded once (variable node calculation and check node calculation). In the decoding device of FIG. 162, after decoding the LDPC code a predetermined number of times, a decoded word calculation unit 309 and a decoded data rearrangement unit 311 calculate and output a final decoding result.

That is, the decoded word calculation unit 309 consists of five decoded word calculators 309 ₁ to 309 ₅ , and the five messages D308 (D308 ₁ to D308 ₅ ) (message u _j in equation (5)) output by the selector 305. , using the five received values D309 (received value u _0i in formula (5)) supplied from the received data memory 306, the decoding result (decoded The decoded data D315 obtained as a result of the calculation is supplied to the decoded data rearrangement unit 311.

The decoded data rearrangement unit 311 performs inverse permutation of the column permutation of equation (12) on the decoded data D315 supplied from the decoded word calculation unit 309 to rearrange the order and obtain the final decoded result. Output as D316.

As described above, one or both of row permutation and column permutation is applied to the check matrix (original check matrix), resulting in a P×P unit matrix with one or more of its elements being 0. A quasi-identity matrix, a shift matrix obtained by cyclically shifting an identity matrix or a quasi-identity matrix, a sum matrix that is the sum of multiple identity matrices, quasi-identity matrices, or shift matrices, a combination of P×P 0 matrices, that is, By converting to a parity check matrix (transformed check matrix) that can be expressed as a combination of constituent matrices, decoding of LDPC codes, check node operations, and variable node operations can be performed using P whose number is smaller than the number of rows and columns of the check matrix. This makes it possible to adopt an architecture that performs multiple tasks simultaneously. When adopting an architecture that simultaneously performs P node operations (check node operations and variable node operations), the number of which is smaller than the number of rows and columns of the parity check matrix, the number of node operations (check node operations and variable node operations) is equal to the number of rows and columns of the check matrix. Compared to the case where decoding is performed simultaneously, it is possible to suppress the operating frequency to a feasible range and perform a large number of iterative decodings.

The LDPC decoder 166 constituting the receiving device 12 in FIG. 156 performs LDPC decoding by simultaneously performing P check node operations and P variable node operations, for example, similarly to the decoding device shown in FIG. 162.

That is, for the sake of simplicity, the parity check matrix of the LDPC code output by the LDPC encoder 115 that constitutes the transmitter 11 in FIG. 8 has a staircase structure, for example, as shown in FIG. 159. The parity interleaver 23 of the transmitter 11 performs parity interleaving to interleave the K+qx+y+1st code bit at the K+Py+x+1st code bit position. is performed by setting the information length K to 60, the unit size P to 5, and the divisor q (=M/P) of the parity length M to 6.

As described above, this parity interleaving corresponds to the column permutation of equation (12), so the LDPC decoder 166 does not need to perform the column permutation of equation (12).

Therefore, in the receiving device 12 of FIG. 156, as described above, the groupwise deinterleaver 55 sends the LDPC code to the LDPC decoder 166 for the LDPC code that has not undergone parity deinterleaving, that is, the sequence of equation (12). The permuted LDPC code is supplied, and the LDPC decoder 166 performs the same processing as the decoding device of FIG. 162, except that the column permutation of equation (12) is not performed.

That is, FIG. 163 is a diagram showing a configuration example of the LDPC decoder 166 of FIG. 156.

In FIG. 163, an LDPC decoder 166 has the same configuration as the decoding device in FIG. 162 except that the received data rearranging unit 310 in FIG. The decoding device performs the same processing as the decoding device shown in FIG. 162, except that the decoding device is not decoded, so a description thereof will be omitted.

As described above, the LDPC decoder 166 can be configured without providing the received data rearrangement section 310, so that the scale can be reduced compared to the decoding device shown in FIG. 162.

In addition, in FIGS. 159 to 163, in order to simplify the explanation, the code length N of the LDPC code is 90, the information length K is 60, and the unit size (number of rows and columns of the constituent matrix) P is 5. , the divisor q (=M/P) of the parity length M is 6, but the code length N, information length K, unit size P, and divisor q (=M/P) are as described above. It is not limited to the value.

That is, in the transmitter 11 of FIG. 8, the LDPC encoder 115 outputs, for example, the code length N as 64800, 16200, 69120, etc., the information length K as N-Pq (=N-M), and the unit size P. 360 and the divisor q is M/P, respectively.The LDPC decoder 166 in FIG. 163 simultaneously performs P check node operations and variable node operations on such LDPC codes. Therefore, it is applicable when performing LDPC decoding.

Further, after the LDPC code is decoded by the LDPC decoder 166, if the parity part of the decoding result is not necessary and only the information bits of the decoding result are output, the LDPC decoder 166 does not need the decoded data rearranging unit 311. can be configured.

<Configuration example of block deinterleaver 54>

FIG. 164 is a diagram illustrating block deinterleaving performed by block deinterleaver 54 of FIG. 157.

In block deinterleaving, the reverse processing of the block interleaving of the block interleaver 25 described in FIG. 108 is performed, so that the arrangement of code bits of the LDPC code is returned to the original arrangement (restored).

In other words, in block deinterleaving, for example, similarly to block interleaving, by writing and reading LDPC codes into m columns equal to the number of symbol bits m, the order of the code bits of the LDPC code is changed to the original order. be returned.

However, in block deinterleaving, writing of LDPC codes is performed in the order in which the LDPC codes are read in block interleaving. Furthermore, in block deinterleaving, reading of LDPC codes is performed in the order in which the LDPC codes are written in block interleaving.

That is, as shown in FIG. 164, part 1 of the LDPC code is written in units of m-bit symbols in the row direction from the first row of all m columns. That is, the code bits of the LDPC code, which are m-bit symbols, are written in the row direction.

The writing of part 1 in units of m bits is performed sequentially toward the rows below the m columns, and when the writing of part 1 is completed, as shown in FIG. Reading part 1 from left to right column downwards.

When the reading to the rightmost column is completed, as shown in Figure 164, return to the leftmost column and read part 1 from the top to the bottom of the second column unit of the column, and from the left to the right column. Thereafter, Part 1 of the LDPC code of one code word is read out in the same manner.

When reading part 1 of the LDPC code for one code word is completed, for part 2, which is made up of m-bit symbol units, the m-bit symbol units are sequentially concatenated after part 1. The LDPC code is returned to the order of code bits of the original LDPC code of one code word (LDCP code before block interleaving).

<Other configuration examples of the bit deinterleaver 165>

FIG. 165 is a block diagram showing another configuration example of the bit deinterleaver 165 shown in FIG. 156.

Note that in the figure, parts corresponding to those in FIG. 157 are denoted by the same reference numerals, and the description thereof will be omitted below as appropriate.

That is, the bit deinterleaver 165 in FIG. 165 has the same configuration as that in FIG. 157 except that a parity deinterleaver 1011 is newly provided.

In FIG. 165, the bit deinterleaver 165 includes a block deinterleaver 54, a groupwise deinterleaver 55, and a parity deinterleaver 1011, and performs bit deinterleaving of the code bits of the LDPC code from the demapper 164. .

That is, the block deinterleaver 54 performs block deinterleaving (inverse processing of block interleaving) corresponding to the block interleaving performed by the block interleaver 25 of the transmitting device 11 on the LDPC code from the demapper 164, that is, block interleaving. Block deinterleaving is performed to return the positions of the code bits swapped by , to their original positions, and the resulting LDPC code is supplied to the groupwise deinterleaver 55 .

The groupwise deinterleaver 55 performs groupwise deinterleaving on the LDPC code from the block deinterleaver 54, which corresponds to the groupwise interleaving as the sorting process performed by the groupwise interleaver 24 of the transmitting device 11.

The LDPC code obtained as a result of groupwise deinterleaving is supplied from the groupwise deinterleaver 55 to the parity deinterleaver 1011.

The parity deinterleaver 1011 performs parity deinterleaving (the inverse of parity interleaving) corresponding to the parity interleaving performed by the parity interleaver 23 of the transmitting device 11, targeting the code bits after the groupwise deinterleaving in the groupwise deinterleaver 55. In other words, parity deinterleaving is performed to restore the code bits of the LDPC code whose order has been changed by parity interleaving to their original order.

The LDPC code obtained as a result of parity deinterleaving is supplied from parity deinterleaver 1011 to LDPC decoder 166.

Therefore, in the bit deinterleaver 165 in FIG. 165, the LDPC decoder 166 receives an LDPC code that has been subjected to block deinterleaving, groupwise deinterleaving, and parity deinterleaving, that is, LDPC encoding according to check matrix H. The LDPC code obtained by

The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix H used by the LDPC encoder 115 of the transmitting device 11 for LDPC encoding.

That is, for the type B method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix H (of the type B method) used by the LDPC encoder 115 of the transmitter 11 for LDPC encoding. This is performed by using the check matrix H, or by using a transformed check matrix obtained by performing at least column permutation corresponding to parity interleaving on the check matrix H. In addition, for the type A method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix (of the type A method) used by the LDPC encoder 115 of the transmitter 11 for LDPC encoding. Using the check matrix (Figure 28) obtained by performing column permutation on the check matrix (Fig. 27), or the transformed check matrix (Fig. 29) obtained by performing row permutation on the check matrix used for LDPC encoding (Fig. 27). conduct.

Here, in FIG. 165, the bit deinterleaver 165 (the parity deinterleaver 1011) supplies the LDPC decoder 166 with an LDPC code obtained by LDPC encoding according to the parity check matrix H. The LDPC encoder 115 of the transmitting device 11 performs column replacement of the LDPC decoding of the code with the type B check matrix H itself used for LDPC encoding, or the type A check matrix (FIG. 27) used for LDPC encoding. In the case of using the parity check matrix (FIG. 28) obtained by applying It consists of a decoding device that performs LDPC decoding using a full serial decoding method, and a decoding device that performs LDPC decoding using a full parallel decoding method that performs message operations on all nodes simultaneously (in parallel). be able to.

In addition, the LDPC decoder 166 performs LDPC decoding of the LDPC code by performing at least column permutation corresponding to parity interleaving on the type B check matrix H used by the LDPC encoder 115 of the transmitting device 11 for LDPC encoding. In the case of using the obtained transformation check matrix or the transformation check matrix (FIG. 29) obtained by performing row permutation on the type A method check matrix (FIG. 27) used for LDPC encoding, the LDPC decoder 166 is a decoding device with an architecture that simultaneously performs P (or a divisor other than 1 of P) check node operations and variable node operations, and performs a similar process to column permutation (parity interleaving) to obtain a transformation check matrix. By applying column permutation to an LDPC code, it can be configured with a decoding device (FIG. 162) having a received data rearrangement section 310 that rearranges the code bits of the LDPC code.

Note that in FIG. 165, for convenience of explanation, the block deinterleaver 54 that performs block deinterleaving, the groupwise deinterleaver 55 that performs groupwise deinterleaving, and the parity deinterleaver 1011 that performs parity deinterleaving are shown respectively. , are configured separately, but two or more of the block deinterleaver 54, groupwise deinterleaver 55, and parity deinterleaver 1011 are the parity interleaver 23, groupwise interleaver 24, and And, like the block interleaver 25, it can be configured integrally.

<Example configuration of receiving system>

FIG. 166 is a block diagram showing a first configuration example of a receiving system to which the receiving device 12 can be applied.

In FIG. 166, the receiving system includes an acquisition section 1101, a transmission line decoding processing section 1102, and an information source decoding processing section 1103.

The acquisition unit 1101 acquires a signal containing an LDPC code obtained by at least LDPC encoding LDPC target data such as image data and audio data of a program, for example, from terrestrial digital broadcasting, satellite digital broadcasting, CATV network, the Internet, etc. is acquired via a transmission path (communication path) not shown, such as a network, and is supplied to the transmission path decoding processing unit 1102.

Here, when the signal acquired by the acquisition unit 1101 is broadcast from a broadcasting station via terrestrial waves, satellite waves, CATV (Cable Television) network, etc., the acquisition unit 1101 uses a tuner or It consists of STB (Set Top Box), etc. Further, when the signal acquired by the acquisition unit 1101 is transmitted from a web server by multicast such as IPTV (Internet Protocol Television), the acquisition unit 1101 transmits a signal such as a NIC (Network Interface Card), etc. It consists of network I/F (Interface).

The transmission path decoding processing section 1102 corresponds to the receiving device 12. Transmission path decoding processing section 1102 performs transmission path decoding processing, including at least processing for correcting errors occurring on the transmission path, on the signal acquired by acquisition section 1101 via the transmission path, and converts the resulting signal into The information is supplied to the information source decoding processing unit 1103.

That is, the signal acquired by the acquisition section 1101 via the transmission path is a signal obtained by at least performing error correction encoding to correct errors occurring on the transmission path, and the transmission path decoding processing section 1102 , For example, transmission line decoding processing such as error correction processing is performed on such signals.

Here, examples of error correction encoding include LDPC encoding and BCH encoding. Here, at least LDPC encoding is performed as error correction encoding.

Further, the transmission path decoding process may include demodulation of a modulated signal.

The information source decoding processing unit 1103 performs an information source decoding process, which includes at least a process of decompressing compressed information into original information, on the signal that has been subjected to the transmission path decoding process.

That is, the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression encoding to compress the information in order to reduce the amount of data such as images and audio as information. In this case, the information source decoding processing unit 1103 performs information source decoding processing, such as processing for expanding compressed information into original information (expansion processing), on the signal that has been subjected to transmission line decoding processing.

Note that if the signal acquired by the acquisition unit 1101 via the transmission path has not been compressed and encoded, the information source decoding unit 1103 does not decompress the compressed information into the original information. It won't happen.

Here, the decompression process includes, for example, MPEG decoding. Furthermore, the transmission path decoding process may include descrambling and the like in addition to decompression processing.

In the reception system configured as described above, the acquisition unit 1101 performs compression encoding such as MPEG encoding on data such as images and audio, and further applies error correction encoding such as LDPC encoding. The encoded signal is acquired via the transmission path and supplied to the transmission path decoding processing section 1102.

In the transmission path decoding processing section 1102, processing similar to that performed by the receiving device 12, for example, is performed on the signal from the acquisition section 1101 as transmission path decoding processing, and the resulting signal is used as the information source. The data is supplied to the decoding processing unit 1103.

The information source decoding processing unit 1103 performs information source decoding processing such as MPEG decoding on the signal from the transmission path decoding processing unit 1102, and outputs the resulting image or audio.

The reception system shown in FIG. 166 as described above can be applied to, for example, a television tuner that receives television broadcasts as digital broadcasts.

Note that the acquisition unit 1101, the transmission line decoding processing unit 1102, and the information source decoding processing unit 1103 are each configured as one independent device (hardware (IC (Integrated Circuit), etc.) or software module). It is possible to do so.

Furthermore, regarding the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, a set of the acquisition unit 1101 and the transmission path decoding processing unit 1102, a set of the transmission path decoding processing unit 1102 and the information source decoding processing It is possible to configure the set with the acquisition section 1101, the transmission line decoding processing section 1102, and the information source decoding processing section 1103 as one independent device.

FIG. 167 is a block diagram showing a second configuration example of a receiving system to which the receiving device 12 can be applied.

Note that in the figure, parts corresponding to those in FIG. 166 are denoted by the same reference numerals, and the description thereof will be omitted below as appropriate.

The reception system in FIG. 167 is similar to the case in FIG. 166 in that it includes an acquisition section 1101, a transmission line decoding processing section 1102, and an information source decoding processing section 1103, and an output section 1111 is newly provided. This is different from the case in FIG. 166.

The output unit 1111 is, for example, a display device that displays images or a speaker that outputs audio, and outputs images, audio, etc. as signals output from the information source decoding processing unit 1103. That is, the output unit 1111 displays an image or outputs audio.

The reception system shown in FIG. 167 as described above can be applied to, for example, a TV (television receiver) that receives television broadcasts as digital broadcasts, a radio receiver that receives radio broadcasts, and the like.

Note that if the signal acquired by the acquisition section 1101 has not been subjected to compression encoding, the signal output from the transmission path decoding processing section 1102 is supplied to the output section 1111.

FIG. 168 is a block diagram showing a third configuration example of a receiving system to which the receiving device 12 can be applied.

Note that in the figure, parts corresponding to those in FIG. 166 are denoted by the same reference numerals, and the description thereof will be omitted below as appropriate.

The reception system in FIG. 168 is similar to the case in FIG. 166 in that it includes an acquisition section 1101 and a transmission path decoding processing section 1102.

However, the reception system of FIG. 168 differs from the case of FIG. 166 in that the information source decoding processing section 1103 is not provided and a recording section 1121 is newly provided.

The recording unit 1121 records the signal (for example, TS packet of MPEG TS) output by the transmission path decoding processing unit 1102 on a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory. ).

The receiving system shown in FIG. 168 as described above can be applied to a recorder that records television broadcasts.

Note that in FIG. 168, the receiving system is configured with an information source decoding processing unit 1103, and the information source decoding processing unit 1103 receives a signal after the information source decoding process, that is, an image or an image obtained by decoding. Audio can be recorded by the recording unit 1121.

<One embodiment of computer>

Next, the series of processes described above can be performed by hardware or software. When a series of processes is performed using software, the programs that make up the software are installed on a general-purpose computer or the like.

Therefore, FIG. 169 shows a configuration example of an embodiment of a computer in which a program that executes the series of processes described above is installed.

The program can be recorded in advance on a hard disk 705 or ROM 703 as a recording medium built into the computer.

Alternatively, the program may be temporarily or It can be permanently stored (recorded). Such a removable recording medium 711 can be provided as so-called package software.

In addition to installing the program on the computer from the removable recording medium 711 as described above, the program may be wirelessly transferred to the computer from a download site via a digital satellite broadcasting satellite, or may be installed on a LAN (Local Area Network). The program can be transferred by wire to a computer via a network such as the Internet, and the computer can receive the transferred program at its communication unit 708 and install it on its built-in hard disk 705.

The computer has a built-in CPU (Central Processing Unit) 702. An input/output interface 710 is connected to the CPU 702 via a bus 701, and the CPU 702 is operated by a user via an input unit 707 consisting of a keyboard, mouse, microphone, etc. When a command is input by doing the same, a program stored in a ROM (Read Only Memory) 703 is executed in accordance with the command. Alternatively, the CPU 702 may receive a program stored in the hard disk 705, a program transferred from a satellite or a network, received by the communication unit 708, and installed on the hard disk 705, or a removable recording medium 711 attached to the drive 709. The program read out and installed on the hard disk 705 is loaded into a RAM (Random Access Memory) 704 and executed. Thereby, the CPU 702 performs processing according to the flowchart described above or processing performed according to the configuration of the block diagram described above. Then, the CPU 702 outputs the processing results as necessary, for example, via an input/output interface 710, from an output unit 706 composed of an LCD (Liquid Crystal Display), a speaker, etc., or from a communication unit 708. The information is transmitted and further recorded on the hard disk 705.

Here, in this specification, processing steps for writing programs for causing a computer to perform various processes do not necessarily have to be processed chronologically in the order described as a flowchart, but may be performed in parallel or individually. It also includes the processing to be executed (for example, parallel processing or processing by objects).

Further, the program may be processed by one computer, or may be distributed and processed by multiple computers. Furthermore, the program may be transferred to a remote computer and executed.

Note that the embodiments of the present technology are not limited to the embodiments described above, and various changes can be made without departing from the gist of the present technology.

For example, the above-described new LDPC code (parity check matrix initial value table) and GW pattern can be used for satellite lines, terrestrial waves, cables (wired lines), and other communication channels 13 (FIG. 7). Furthermore, the new LDPC code and GW pattern can be used for data transmission other than digital broadcasting.

Note that the effects described in this specification are merely examples and are not limited, and other effects may also exist.

11 transmitter, 12 receiver, 23 parity interleaver, 24 groupwise interleaver, 25 block interleaver, 54 block deinterleaver, 55 groupwise deinterleaver, 111 mode adaptation/multiplexer, 112 padder, 113 BB scrambler , 114 BCH encoder, 115 LDPC encoder, 116 bit interleaver, 117 mapper, 118 time interleaver, 119 SISO/MISO encoder, 120 frequency interleaver, 121 BCH encoder, 122 LDPC encoder, 123 mapper, 124 frequency interleaver, 131 Frame builder/resource allocation unit 132 OFDM generation unit, 151 OFDM processing unit, 152 frame management unit, 153 frequency deinterleaver, 154 demapper, 155 LDPC decoder, 156 BCH decoder, 161 frequency deinterleaver, 162 SISO/MISO decoder, 163 Time deinterleaver, 164 Demapper, 165 Bit deinterleaver, 166 LDPC decoder, 167 BCH decoder, 168 BB descrambler, 169 Null deletion unit, 170 Demultiplexer, 300 Edge data storage memory, 301 Selector, 302 Check node calculation unit, 303 cyclic shift circuit, 304 branch data storage memory, 305 selector, 306 received data memory, 307 variable node calculation unit, 308 cyclic shift circuit, 309 decoded word calculation unit, 310 received data rearrangement unit, 311 decoded data sorting section, 601 encoding processing section, 602 storage section, 611 coding rate setting section, 612 initial value table reading section, 613 parity check matrix generation section, 614 information bit reading section, 615 encoding parity calculation section, 616 control section, 701 bus, 702 CPU, 703 ROM, 704 RAM, 705 hard disk, 706 output section, 707 input section, 708 communication section, 709 drive, 710 input/output interface, 711, removable recording medium, 1001 reverse exchange section, 1002 memory, 1011 parity deinterleaver, 1101 acquisition unit, 1101 transmission path decoding processing unit, 1103 information source decoding processing unit, 1111 output unit, 1121 recording unit

Claims (2)

an encoding step of performing LDPC encoding based on a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 14/16;
a group-wise interleaving step of performing group-wise interleaving in which the LDPC code obtained by the LDPC encoding is interleaved in units of 360-bit bit groups;
a mapping step of mapping the groupwise interleaved LDPC code to any of 64 signal points of a 64QAM UC (Uniform Constellation) in 6-bit units;
In the groupwise interleaving, the i+1th bit group from the beginning of the LDPC code is set as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is set as bit group i.
133, 96, 46, 148, 78, 109, 149, 161, 55, 39, 183, 54, 186, 73, 150, 180, 189, 190, 22, 135, 12, 80, 42, 130, 164, 70, 126, 107, 57, 67, 15, 157, 52, 88, 5, 23, 123, 66, 53, 147, 177, 60, 131, 108, 171, 191, 44, 140, 98, 154, 37, 118, 176, 92, 124, 138, 132, 167, 173, 13, 79, 32, 145, 14, 113, 30, 2, 0, 165, 182, 153, 24, 144, 87, 82, 75, 141, 89, 137, 33, 100, 106, 128, 168, 29, 36, 172, 11, 111, 68, 16, 10, 34, 188, 35, 160, 77, 83, 178, 58, 59, 7, 56, 110, 104, 61, 76, 85, 121, 93, 19, 134, 179, 155, 163, 115, 185, 125, 112, 71, 8, 119, 18, 47, 151, 26, 103, 122, 9, 170, 146, 99, 49, 72, 102, 31, 40, 43, 158, 142, 4, 69, 139, 28, 174, 101, 84, 129, 156, 74, 62, 91, 159, 41, 38, 45, 136, 169, 21, 51, 181, 97, 166, 175, 90, 27, 86, 65, 105, 143, 127, 17, 6, 116, 94, 117, 48, 50, 25, 64, 95, 63, 184, 152, 120, 1, 187, 162, 114, 3, 81, 20
Interleave the sequence of
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix section corresponding to the information bits and a parity matrix section corresponding to the parity bits,
The information matrix section is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix section for every 360 columns,
387 648 945 3023 3889 4856 5002 5167 6868 7477 7590 8165 8354
42 406 1279 1968 3016 4196 4599 4996 5019 6350 6785 7051 8529
534 784 1034 1160 2530 5033 5171 5469 6167 6372 6913 7718 8621
944 2506 2806 3149 3559 5101 6076 6083 6092 6147 6866 7908 8155
308 1869 1888 2569 3297 4742 5232 5442 6135 6814 7284 8238 8405
34 464 667 899 2421 3425 5382 6258 6373 6399 6489 7367 7922
2276 3014 3525 3829 4135 4276 4611 4733 4738 4956 6025 7152 8155
1047 1370 2406 2819 4600 4991 5017 5590 6199 6483 6556 6834 7760
66 380 2033 3698 4068 6096 6223 6238 6757 7541 7641 7677 8595
562 697 782 808 921 1703 3032 4300 7027 7481 7839 8160 8526
236 962 1557 2023 2135 2190 2892 3072 4523 6254 6838 7209 7381
196 1167 1179 1426 1675 1763 2345 2560 2613 5024 5761 6522 7973
512 822 1778 1924 2610 3445 4570 4805 5263 5299 8439 8448 8464
1923 2270 3204 3698 4456 4522 4601 5161 5207 6260 6310 6441 6851
104 281 622 1276 2172 2334 2731 3417 3854 4698 8095 8195 8333
451 528 1269 2169 2274 2393 3853 5002 5543 6121 6351 7364 8139
1685 2675 2790 2953 3103 3560 4336 5372 5495 5568 6429 6492 8206
604 1190 1279 2427 2714 3283 3312 3855 4566 6045 6664 6788 8317
338 917 1873 2102 2561 2655 4635 4765 5370 6249 6724 7668 8456
184 1166 1583 1859 2376 2521 3093 4181 4713 4926 5146 6070 8004
175 1227 2367 3402 3628 3982 4265 4282 4355 5972 6434 7280 7765
801 922 1029 1531 1606 3170 3824 4358 4732 4849 5225 6759 8183
509 1507 1704 1765 2183 2574 3271 4050 4299 4964 5968 6324 7091
567 795 1376 2390 2767 3424 5195 6355 6726 7607 8346 8352
308 1060 1973 2364 2937 3526 4221 4745 5185 5845 6146 7762
323 590 732 917 2636 3008 3792 3990 4322 4893 5211 8014
471 1249 1674 1841 2567 3124 3130 4885 5575 7521 7648 8227
1582 1669 1772 2386 3340 3387 3881 4322 6018 6055 6488 7177
976 1003 2127 3575 3816 6225 7404 7499 7542 8237 8421 8630
675 961 1957 3825 3858 4646 5248 5801 5940 6533 7040 8037
79 639 1363 1436 1763 2570 3874 4876 6870 6886 7104 8399
20 297 1330 2264 3287 3534 4441 4746 6569 6971 6976 8179
482 1125 1589 2892 3759 3871 4635 6038 6214 6796 6816 7621
1127 3336 3867 3929 4269 4794 5054 5842 6471 6547 7039 8560
217 1521
1983 8283
3731 4402
208 6703
242 4988
4170 5038
4108 8035
3301 8543
3168 8249
5028 5838
3470 8597
2901 5264
2505 4505
934 5117
1712 5819
3165 7273
3274 6115
4576 6330 7327
5380 6732 8439
2474 3723 7782
384 2783 5846
1453 4436 6625
3220 4261 4835
163 3117 7554
502 2119 4059
2200 4263 4930
2378 6294 7713
743 5501 6809
1364 6062 7808
4680 6468 7895
3469 3602 7304
1609 5386 5647
267 2921 3206
2565 3020 6269
1651 5224 5718
1128 5058 8579
286 3396 7660
1497 5171 6519
1894 6349 7924
1306 7744 8083
3096 3438 3836
2556 7409 8570
3273 4245 7935
1633 2023 3125
584 4914 6062
2015 2915 3435
1457 6366 6461
23 3576 8132
5322 6300 6520
5715 7113 7822
2044 5053 6607
63 5432 7850
5353 6355 8637
346 590 2648
4780 5997 6991
2556 2583 6537
661 2497 8350
7610 8307 8441
671 860 5986
1133 3158 5891
4360 5802 6547
4782 5688 6955
447 5030 6268
1501 5163 7232
1133 2743 3214
959 4100 7554
5712 7643 8385
1442 3180 8008
697 3078 8421
137 922 5123
597 2879 6340
824 2071 7882
1827 4411 5941
3846 5970 6398
1561 1580 7668
4335 6936 8042
4504 5309 6737
1846 3273 3333
272 4885 6718
1835 4761 6931
2141 3760 5129
3975 5012 6504
1258 2822 6030
242 4947 7668
559 6100 8425
1655 1962 4401
2369 2476 2765
114 156 3195
1651 4154 4448
4669 6064 7317
4988 5567 6697
2963 5578 5679
2064 2286 7790
289 4639 7582
1258 4312 5340
2428 4219 7268
1752 2321 6806
118 7302 8603
4170 4280 4445
2207 5067 7257
2 55 7413
1141 4791 7149
3407 5649 8075
2773 3198 3720
6970 7222 8633
2498 4764 5281
1048 2093 5031
2500 2851 8396
1694 3795 6666
2565 3343 4688
4228 4374 5947
2267 6745 7172
175 2662 3926
90 1517 6056
4069 5439 7648
1679 3394 4707
2136 4553 8265
482 2100 2302
3306 3729 8063
5263 7710 8240
1001 1335 4500
576 6736 7250
181 3601 3755
5899 7515 7714
1181 5332 7197
542 1150 1196
1386 2156 5873
656 3019 3213
263 1117 5957
4495 5904 6462
2547 2786 4215
4954 5848 6225
940 4478 7633
2124 3347 7069
is the transmission method. an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code whose code length N is 69120 bits and whose encoding rate r is 14/16;
a group -wise interleaving unit that performs group-wise interleaving to interleave the LDPC code obtained by the LDPC encoding in units of 360-bit bit groups;
a mapping unit that maps the groupwise interleaved LDPC code to any one of 64 signal points of a 64QAM UC (Uniform Constellation) in 6-bit units;
In the groupwise interleaving, the i+1th bit group from the beginning of the LDPC code is set as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is set as bit group i.
133, 96, 46, 148, 78, 109, 149, 161, 55, 39, 183, 54, 186, 73, 150, 180, 189, 190, 22, 135, 12, 80, 42, 130, 164, 70, 126, 107, 57, 67, 15, 157, 52, 88, 5, 23, 123, 66, 53, 147, 177, 60, 131, 108, 171, 191, 44, 140, 98, 154, 37, 118, 176, 92, 124, 138, 132, 167, 173, 13, 79, 32, 145, 14, 113, 30, 2, 0, 165, 182, 153, 24, 144, 87, 82, 75, 141, 89, 137, 33, 100, 106, 128, 168, 29, 36, 172, 11, 111, 68, 16, 10, 34, 188, 35, 160, 77, 83, 178, 58, 59, 7, 56, 110, 104, 61, 76, 85, 121, 93, 19, 134, 179, 155, 163, 115, 185, 125, 112, 71, 8, 119, 18, 47, 151, 26, 103, 122, 9, 170, 146, 99, 49, 72, 102, 31, 40, 43, 158, 142, 4, 69, 139, 28, 174, 101, 84, 129, 156, 74, 62, 91, 159, 41, 38, 45, 136, 169, 21, 51, 181, 97, 166, 175, 90, 27, 86, 65, 105, 143, 127, 17, 6, 116, 94, 117, 48, 50, 25, 64, 95, 63, 184, 152, 120, 1, 187, 162, 114, 3, 81, 20
Interleave the sequence of
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix section corresponding to the information bits and a parity matrix section corresponding to the parity bits,
The information matrix section is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix section for every 360 columns,
387 648 945 3023 3889 4856 5002 5167 6868 7477 7590 8165 8354
42 406 1279 1968 3016 4196 4599 4996 5019 6350 6785 7051 8529
534 784 1034 1160 2530 5033 5171 5469 6167 6372 6913 7718 8621
944 2506 2806 3149 3559 5101 6076 6083 6092 6147 6866 7908 8155
308 1869 1888 2569 3297 4742 5232 5442 6135 6814 7284 8238 8405
34 464 667 899 2421 3425 5382 6258 6373 6399 6489 7367 7922
2276 3014 3525 3829 4135 4276 4611 4733 4738 4956 6025 7152 8155
1047 1370 2406 2819 4600 4991 5017 5590 6199 6483 6556 6834 7760
66 380 2033 3698 4068 6096 6223 6238 6757 7541 7641 7677 8595
562 697 782 808 921 1703 3032 4300 7027 7481 7839 8160 8526
236 962 1557 2023 2135 2190 2892 3072 4523 6254 6838 7209 7381
196 1167 1179 1426 1675 1763 2345 2560 2613 5024 5761 6522 7973
512 822 1778 1924 2610 3445 4570 4805 5263 5299 8439 8448 8464
1923 2270 3204 3698 4456 4522 4601 5161 5207 6260 6310 6441 6851
104 281 622 1276 2172 2334 2731 3417 3854 4698 8095 8195 8333
451 528 1269 2169 2274 2393 3853 5002 5543 6121 6351 7364 8139
1685 2675 2790 2953 3103 3560 4336 5372 5495 5568 6429 6492 8206
604 1190 1279 2427 2714 3283 3312 3855 4566 6045 6664 6788 8317
338 917 1873 2102 2561 2655 4635 4765 5370 6249 6724 7668 8456
184 1166 1583 1859 2376 2521 3093 4181 4713 4926 5146 6070 8004
175 1227 2367 3402 3628 3982 4265 4282 4355 5972 6434 7280 7765
801 922 1029 1531 1606 3170 3824 4358 4732 4849 5225 6759 8183
509 1507 1704 1765 2183 2574 3271 4050 4299 4964 5968 6324 7091
567 795 1376 2390 2767 3424 5195 6355 6726 7607 8346 8352
308 1060 1973 2364 2937 3526 4221 4745 5185 5845 6146 7762
323 590 732 917 2636 3008 3792 3990 4322 4893 5211 8014
471 1249 1674 1841 2567 3124 3130 4885 5575 7521 7648 8227
1582 1669 1772 2386 3340 3387 3881 4322 6018 6055 6488 7177
976 1003 2127 3575 3816 6225 7404 7499 7542 8237 8421 8630
675 961 1957 3825 3858 4646 5248 5801 5940 6533 7040 8037
79 639 1363 1436 1763 2570 3874 4876 6870 6886 7104 8399
20 297 1330 2264 3287 3534 4441 4746 6569 6971 6976 8179
482 1125 1589 2892 3759 3871 4635 6038 6214 6796 6816 7621
1127 3336 3867 3929 4269 4794 5054 5842 6471 6547 7039 8560
217 1521
1983 8283
3731 4402
208 6703
242 4988
4170 5038
4108 8035
3301 8543
3168 8249
5028 5838
3470 8597
2901 5264
2505 4505
934 5117
1712 5819
3165 7273
3274 6115
4576 6330 7327
5380 6732 8439
2474 3723 7782
384 2783 5846
1453 4436 6625
3220 4261 4835
163 3117 7554
502 2119 4059
2200 4263 4930
2378 6294 7713
743 5501 6809
1364 6062 7808
4680 6468 7895
3469 3602 7304
1609 5386 5647
267 2921 3206
2565 3020 6269
1651 5224 5718
1128 5058 8579
286 3396 7660
1497 5171 6519
1894 6349 7924
1306 7744 8083
3096 3438 3836
2556 7409 8570
3273 4245 7935
1633 2023 3125
584 4914 6062
2015 2915 3435
1457 6366 6461
23 3576 8132
5322 6300 6520
5715 7113 7822
2044 5053 6607
63 5432 7850
5353 6355 8637
346 590 2648
4780 5997 6991
2556 2583 6537
661 2497 8350
7610 8307 8441
671 860 5986
1133 3158 5891
4360 5802 6547
4782 5688 6955
447 5030 6268
1501 5163 7232
1133 2743 3214
959 4100 7554
5712 7643 8385
1442 3180 8008
697 3078 8421
137 922 5123
597 2879 6340
824 2071 7882
1827 4411 5941
3846 5970 6398
1561 1580 7668
4335 6936 8042
4504 5309 6737
1846 3273 3333
272 4885 6718
1835 4761 6931
2141 3760 5129
3975 5012 6504
1258 2822 6030
242 4947 7668
559 6100 8425
1655 1962 4401
2369 2476 2765
114 156 3195
1651 4154 4448
4669 6064 7317
4988 5567 6697
2963 5578 5679
2064 2286 7790
289 4639 7582
1258 4312 5340
2428 4219 7268
1752 2321 6806
118 7302 8603
4170 4280 4445
2207 5067 7257
2 55 7413
1141 4791 7149
3407 5649 8075
2773 3198 3720
6970 7222 8633
2498 4764 5281
1048 2093 5031
2500 2851 8396
1694 3795 6666
2565 3343 4688
4228 4374 5947
2267 6745 7172
175 2662 3926
90 1517 6056
4069 5439 7648
1679 3394 4707
2136 4553 8265
482 2100 2302
3306 3729 8063
5263 7710 8240
1001 1335 4500
576 6736 7250
181 3601 3755
5899 7515 7714
1181 5332 7197
542 1150 1196
1386 2156 5873
656 3019 3213
263 1117 5957
4495 5904 6462
2547 2786 4215
4954 5848 6225
940 4478 7633
2124 3347 7069
is a transmitting device.

Images