JP7437593B2 - Computing device and computing method - Google Patents

Description

Embodiments of the present invention relate to an arithmetic device and an arithmetic method.

Over the next 10 years, the amount of data managed in data centers is expected to increase by a factor of 50, while the number of processors is expected to increase by only a factor of 10. Furthermore, in recent computing applications, it is required to efficiently perform a wide variety of processing such as big data analysis, scientific calculation, media processing, signal processing, machine learning, and database processing.
However, the increase in performance demands is outpacing the increase in computer resources, making it difficult to maintain adequate services. Approximate computing (AC) is attracting attention as a means to solve this problem. AC is a calculation method that allows trade-offs between accuracy, speed, and energy for applications that can tolerate calculation errors. In other words, this is a method of increasing speed and reducing power consumption by reducing calculation accuracy.

In general, there are many applications such as image recognition that can derive the correct answer even if there are some bit errors. Current computer systems can perform calculations without making even a single bit error in such cases, but if there is no difference in the result even if some calculation errors are included, calculations may be performed quickly even if the accuracy is compromised. It may be more valuable to complete. In fact, there is a report that in neural network calculations, if an AC is used and an error of about 5% is allowed, the speed is 26 times faster than that of a GPU (for example, see Non-Patent Document 1).
AC can be roughly divided into two types: a software (algorithm) approach and a hardware approach. Software-based methods have long been established as approximate calculations and approximate algorithms. It has further developed in recent years. On the other hand, there is a lot of research into hardware approaches aimed at increasing the speed of arithmetic units, especially reducing latency.

BEAYNA GRIGORIAN and GLENN REINMAN, “Accelerating Divergent Applications on SIMD Architectures Using Neural Networks”, ACM T Transactions on Architecture and Code Optimization, Vol. 12, No. 1, Article 2, Publication date: March 2015.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide an arithmetic device and an arithmetic method capable of outputting rough calculation results.

One embodiment of the present invention includes a reception unit that receives error information required for a plurality of input values and calculation results, and a reception unit that receives error information required for a plurality of input values and calculation results , and a reception unit that receives error information required for a plurality of input values and calculation results, and a reception unit that receives a plurality of input values to be used for addition based on the error information received by the reception unit. a setting section that sets the number of digits from the most significant bit of each; and a setting section that sets the number of digits from the most significant bit of each of the plurality of input values based on the number of digits from the most significant bit set by the setting section. Up to the set number of digits, the reception unit outputs each of the plurality of input values every K bits (K is an integer where K>0) from the most significant bit. This is an arithmetic device including an arithmetic unit that performs the addition at each time, and an output unit that outputs the addition result by the arithmetic unit every K bits starting from the most significant bit after L clocks (L is an integer where L>0).
In one embodiment of the present invention, in the arithmetic device described above, the setting unit stores error information required for the arithmetic result and the number of digits from the most significant bit of each of the plurality of input values in association with each other. The number of digits from the most significant bit of each of the plurality of input values is obtained from the error information received by the reception unit.
In one embodiment of the present invention, in the arithmetic device described above, the arithmetic unit stops the addition when the addition result of the most significant bit is equal to or greater than a threshold value.

One embodiment of the present invention includes the step of receiving error information required for a plurality of input values and calculation results , and the step of receiving error information required for a plurality of input values and calculation results, and determining each of the plurality of input values used for addition based on the error information received in the receiving step. and setting the number of digits from the most significant bit of each of the plurality of input values based on the number of digits from the most significant bit set in the setting step . Up to the set number of digits, the reception unit outputs each of the plurality of input values every K bits (K is an integer where K>0) from the most significant bit. and a step of outputting the addition result from the addition step every K bits starting from the most significant bit after L (L is an integer where L>0) clocks later. This is a calculation method.

According to the embodiments of the present invention, it is possible to provide a calculation device and a calculation method that can output rough calculation results.

1 is a configuration diagram of a calculation system including a calculation device according to an embodiment. FIG. 3 is a diagram for explaining a calculation method executed by the calculation device according to the embodiment. It is a sequence chart which shows an example of operation of the calculation system concerning an embodiment. FIG. 2 is a diagram illustrating an example of a conventional calculation method. FIG. 2 is a diagram showing an example 1 of comparison results between the calculation method of the calculation device according to the embodiment and the conventional calculation method. It is a figure showing example 2 of the comparison result of the calculation method of the calculation device concerning an embodiment, and the conventional calculation method. FIG. 3 is a diagram illustrating an example of an absolute error of a calculation result by the calculation device according to the present embodiment. FIG. 3 is a diagram illustrating an example of a calculation unit of the calculation device according to the embodiment. FIG. 2 is a configuration diagram of a calculation system including a calculation device according to a modification of the embodiment. It is a sequence chart which shows an example of operation of a calculation system concerning a modification of an embodiment.

Next, a calculation device and a calculation method according to an embodiment of the present invention will be described with reference to the drawings. The embodiments described below are merely examples, and the embodiments to which the present invention is applied are not limited to the following embodiments.
In addition, in all the figures for explaining the embodiment, parts having the same functions are denoted by the same reference numerals, and repeated explanations will be omitted.
Furthermore, "based on XX" as used in the present application means "based on at least XX", and includes cases where it is based on another element in addition to XX. Furthermore, "based on XX" is not limited to the case where XX is used directly, but also includes the case where it is based on calculations and processing performed on XX. "XX" is an arbitrary element (for example, arbitrary information).

(Embodiment)
[overall structure]
FIG. 1 is a configuration diagram of a calculation system including a calculation device according to an embodiment. The computing system 1 of the embodiment includes a computing device 100 and a terminal device 200 used by one or more users U.
The computing device 100 and the terminal device 200 can communicate with each other via the network NW. The network NW includes the Internet, a WAN (Wide Area Network), a LAN (Local Area Network), a public line, a provider device, a private line, a wireless base station, and the like.

When the user U performs an operation on the terminal device 200 to connect to the computing device 100, the terminal device 200 connects to the computing device 100 via the network NW. The terminal device 200 accesses a calculation service website provided by the calculation device 100.
User U performs an operation to input a plurality of input values into terminal device 200 according to the display on the calculation service website.
The terminal device 200 acquires a plurality of input values input by the user U, and creates a calculation request that includes the acquired plurality of input values and is directed to the calculation device 100. The terminal device 200 transmits the created calculation request to the calculation device 100.

The computing device 100 receives the computing request transmitted by the terminal device 200. The arithmetic device 100 receives each of the plurality of input values included in the received arithmetic request. The arithmetic device 100 acquires a value corresponding to one or more digits from the most significant bit (MSB) of each of the plurality of received input values. Here, the number of digits starting from the most significant bit is set in advance based on an allowable error in the calculation result.
The arithmetic device 100 adds each of the plurality of input values from the most significant bit to the value corresponding to one or more digits among the acquired values corresponding to one or more digits, using serial transfer. Based on the number of bits K, the processing is performed every K bits (K is an integer where K>0) starting from the most significant bit. In other words, bits lower than one or more digits from the most significant bit are treated as zero. The arithmetic device 100 outputs the arithmetic result every K bits, based on the number L of delay clocks during addition, starting after L clocks (L is an integer where L>0). For example, the arithmetic device 100 outputs the arithmetic result every K bits starting from the most significant bit. The calculation device 100 creates a calculation response that includes the calculation result and is addressed to the terminal device 200, and transmits the created calculation response to the terminal device 200.
The terminal device 200 receives the calculation response transmitted by the calculation device 100, and acquires the calculation result included in the received calculation response. The terminal device 200 outputs the obtained calculation result.
Hereinafter, the arithmetic device 100 and the terminal device 200 included in the arithmetic system 1 will be sequentially explained.

[Arithmetic device 100]
The arithmetic device 100 included in the arithmetic system 1 is realized by a device such as a personal computer, a server, or an industrial computer. The calculation device 100 includes, for example, a communication section 110, a reception section 120, a calculation section 130, an output section 140, and a storage section 150.
The communication unit 110 is realized by a communication module. Specifically, the communication unit 110 is configured by a device that performs wired communication. Further, the communication unit 110 may be configured by a wireless device that performs wireless communication using a wireless communication technology such as LTE or wireless LAN. The communication unit 110 communicates with the terminal device 200 via the network NW.
Specifically, the communication unit 110 receives the calculation request transmitted by the terminal device 200. The communication unit 110 acquires the calculation response output by the output unit 140 and transmits the acquired calculation response to the terminal device 200.

The storage unit 150 is realized by a HDD (Hard Disk Drive), a flash memory, a RAM (Random Access Memory), a ROM (Read Only Memory), or the like. The storage unit 150 stores calculation digit number information 152. The calculation digit number information 152 is information indicating the number of digits used by the calculation device 100 in calculation, and stores a value corresponding to the number of digits from the most significant bit of the input value. The calculation digit number information 152 is set in advance based on the error allowed in the calculation result. The smaller the allowable error in the calculation result, the higher the precision required for the calculation result, so the value of the calculation digit number information 152 increases. Since the accuracy of calculation becomes smaller, the value of the calculation digit number information 152 becomes smaller.

The reception unit 120, the calculation unit 130, and the output unit 140 are realized, for example, by a hardware processor such as a CPU (Central Processing Unit) executing a program (software) stored in the storage unit 150. In addition, some or all of these functional units may be implemented using hardware (circuits) such as LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), and GPU (Graphics Processing Unit). (including circuitry), or may be realized by collaboration between software and hardware.
The program may be stored in advance in a storage device (a storage device with a non-transitory storage medium) such as an HDD (Hard Disk Drive) or flash memory, or may be stored in a removable storage device such as a DVD or CD-ROM. It is stored in a medium (non-transitory storage medium), and may be installed by loading the storage medium into a drive device.

The reception unit 120 receives a plurality of input values included in the calculation request received by the communication unit 110. The plurality of input values received by the reception unit 120 are output to the calculation unit 130. Here, if the received input values have different numbers of digits, the reception unit 120 performs digit alignment. The reception unit 120 outputs each of the plurality of input values to the calculation unit 130 in units of K bits starting from the most significant bit based on bit K of the serial transfer. Here, bit K for serial transfer is set in advance.
The calculation unit 130 acquires each of the plurality of input values received by the reception unit 120 in units of K bits starting from the most significant bit. The calculation unit 130 acquires the calculation digit number information 152 stored in the storage unit 150, and calculates the calculation digit number from the most significant bit of each of the plurality of input values based on the acquired calculation digit number information 152. The value corresponding to one or more digits indicated by the information 152 is obtained every K bits from the most significant bit.
The calculation unit 130 adds each of the plurality of input values from the most significant bit of the acquired value corresponding to one or more digits to the value corresponding to one or more digits. The calculation unit 130 outputs the result of adding each of the plurality of input values from the most significant bit to the value corresponding to one or more digits to the output unit 140 every K bits from the most significant bit. . The calculation unit 130 may process the lower bits of the value corresponding to one or more digits starting from the most significant bit as 0.

The output unit 140 outputs the calculation result by the calculation unit 130 every K bits starting after L clocks (L is an integer where L>0) based on the number L of delay clocks at the time of addition. Here, the number of delay clocks L at the time of addition is set in advance. Further, the output unit 140 creates a calculation response that includes the calculation result and is addressed to the terminal device 200, and outputs the created calculation response to the communication unit 110.

FIG. 2 is a diagram for explaining a calculation method executed by the calculation device according to the embodiment. Here, as an example, a case will be described in which the serial transfer bit K is 1 and the number of delay clocks L during addition is 1.
In FIG. 2, (a) shows a conventional calculation method, and (b) shows a calculation method by the calculation device 100 according to the present embodiment. Further, in FIG. 2, as an example, a case will be described in which input A and input B are added when input A is "a7a6a5a4a3a2a1a0" and input B is "b7b6b5b4b3b2b1b0". Here, "a7", "a6", "a5", "a4", "a3", "a2", "a1", "a0", "b7", "b6", "b5", "b4" ”, “b3”, “b2”, “b1”, and “b0” each indicate an input value, “a7” and “b7” are the most significant bits, and “a0” and “b0” are the most significant bits. ” is the least significant bit (LSB).

According to the conventional calculation method shown in FIG. , are added sequentially. One clock after "a0", the least significant bit of input A, and "b0", the least significant bit of input B, are input, "a0", the least significant bit of input A, and "b0", the least significant bit of input B, are input. The addition result "c0" with the bit "a0" is output. The calculation result is output two clocks after "a7" which is the most significant bit of input A and "b7" which is the most significant bit of input B are input. In other words, in the conventional calculation method, the calculation result cannot be determined unless the most significant bit is calculated.

According to the calculation method performed by the calculation device 100 according to the present embodiment shown in FIG. . One clock after "a7" which is the most significant bit of input A and "b7" which is the most significant bit of input B are input, "a7" which is the most significant bit of input A and "b7" which is the most significant bit of input B are input. The addition result "c8" with the bit "b7" is output. In other words, the timing at which the output of the calculation results starts is the same as in the conventional calculation method.
The operation result is output two clocks after "a0" which is the least significant bit of input A and "b0" which is the least significant bit of input B are input. By outputting the lower bits, the calculation accuracy increases compared to before the lower bits are output. That is, in the calculation method by the calculation device 100 according to the present embodiment, the calculation result is output from the most significant bit, so it is possible to obtain an outline of the calculation result without calculating up to the least significant bit.

As an example of arithmetic processing, a case will be described in which 146 and 150 expressed in decimal numbers are added.
146 and 150 expressed as decimal numbers are (10010010) ₂ and (10010110) ₂ when expressed as binary numbers, respectively. When adding 146 expressed as a decimal number and 150, the correct calculation result is 296 expressed as a decimal number ((100101000) ₂ when expressed as a binary number).
According to the conventional arithmetic method, when a serial adder is used, arithmetic processing is performed starting from the least significant bit, so (□□□□0010) ₂ and (□□□□0110) ₂ (□ is , bits not used in the operation), and (□□□□1000) ₂ is obtained as the result of the operation. This is 8 when expressed in decimal notation, which is a value far from an accurate calculation result.
Furthermore, when a 4-bit operation is performed, the 4 most significant bits of (10010010) ₂ are added to the 4 most significant bits of (10010110) ₂ , and the operation result is , (100101000) ₂ is obtained. This is 296 when expressed in decimal notation, which is an accurate calculation result. In other words, in the conventional calculation method, accurate calculation results can be obtained by calculating up to the most significant bit.

Regarding the calculation method of the calculation device according to the embodiment, a case where 4 is set in the calculation digit number information 152 and a value corresponding to 4 bits is acquired from the most significant bit will be described as an example. Here, as an example, a case will be described in which the serial transfer bit K is 1 and the number of delay clocks L during addition is 1. In this case, since the calculation process is performed bit by bit starting from the most significant bit, (1001□□□□) ₂ and (1001□□□□) ₂ are added, and the calculation result is (10010□ □□□) ₂ is obtained. This is 288 when expressed in decimal notation, which is a value closer to an accurate calculation result than the conventional calculation method.
Furthermore, when a 4-bit operation is performed, the 4 bits from the least significant bit of (10010010) ₂ are added to the 4 bits from the least significant bit of (10010110) ₂ , and the operation result is , (100101100) ₂ is obtained. This is 300 when expressed as a decimal number, and the result contains an error compared to an accurate calculation result.

From the above, when a serial adder is used as a conventional calculation method, since the calculation is performed from the lower bits, a small value can be obtained in the middle of the calculation compared to an accurate calculation result. When using the arithmetic method of the arithmetic device according to this embodiment, since the arithmetic operation is performed from the upper bits, even in the middle of the arithmetic operation, the accurate arithmetic result can be calculated with a value that is closer to that of the conventional arithmetic method. Obtainable. Returning to FIG. 1, the explanation will be continued.

[Terminal device]
The terminal device 200 is, for example, a smartphone, a tablet terminal, a personal computer, or the like. On the terminal device 200, an application program, a browser, or the like for using the computing system is started, and supports the above-mentioned services. An example of the terminal device 200 is a smartphone, and it is assumed that an application program (arithmetic processing application) is running.
The arithmetic processing application communicates with the arithmetic device 100 according to the operation of the user U, and accesses the arithmetic service website provided by the arithmetic device 100. The terminal device 200 transmits a calculation request to the calculation device 100 and performs processing based on the calculation response received from the calculation device 100.

(Operation of calculation system)
FIG. 3 is a sequence chart showing an example of the operation of the calculation system according to the embodiment.
In the example shown in FIG. 3, when the user U operates the terminal device 200, the terminal device 200 connects to the computing device 100 and accesses the computing service website provided by the computing device 100. The premise is that.
(Step S1)
When the user U performs an operation to input a plurality of input values to the terminal device 200, the terminal device 200 creates a calculation request that includes the input plurality of input values and is directed to the calculation device 100. do.
(Step S2)
The terminal device 200 transmits the created calculation request to the calculation device 100.
(Step S3)
In the computing device 100, the communication unit 110 receives the computing request transmitted by the terminal device 200.
(Step S4)
In the calculation device 100, the reception unit 120 acquires the calculation request received by the communication unit 110, and receives a plurality of input values included in the acquired calculation request. The reception unit 120 adjusts the digits of each of the plurality of input values as necessary. The reception unit 120 outputs each of the plurality of input values to the calculation unit 130 in units of K bits starting from the most significant bit based on the bit K of the serial transfer.

(Step S5)
In the arithmetic device 100, the arithmetic unit 130 acquires each of the plurality of input values received by the reception unit 120, every K bits, starting from the most significant bit. The calculation unit 130 acquires the calculation digit number information 152 from the storage unit 150. Based on the obtained calculation digit number information 152, the calculation unit 130 calculates the data every K bits from the most significant bit of each of the plurality of obtained input values to a value corresponding to one or more digits. get.
(Step S6)
In the arithmetic device 100, the arithmetic unit 130 adds each of the plurality of input values from the most significant bit of the obtained value corresponding to the one or more digits to the value corresponding to the one or more digits. I do. The calculation unit 130 outputs the result of adding each of the plurality of input values from the most significant bit to the value corresponding to one or more digits to the output unit 140 every K bits from the most significant bit. . The output unit 140 outputs the calculation result by the calculation unit 130 from the most significant bit every K bits starting after L clocks based on the number L of delay clocks during addition.
(Step S7)
In the calculation device 100 , the output unit 140 creates a calculation response that includes the calculation result and is addressed to the terminal device 200 , and outputs the created calculation response to the communication unit 110 .
(Step S8)
In the calculation device 100 , the communication unit 110 acquires the calculation response output by the output unit 140 and transmits the acquired calculation result to the terminal device 200 .
Thereafter, the terminal device 200 receives the calculation response transmitted by the calculation device 100, and acquires the calculation result included in the received calculation response. The terminal device 200 outputs the obtained calculation result.

The results of a comparison between the calculation method of the calculation device according to the embodiment and the conventional calculation method will be described.
FIG. 4 is a diagram showing an example of a conventional calculation method. 4(a) and 4(b) show an example of a parallel general adder, and FIG. 4(c) shows an example of a serial adder.
FIG. 4(a) shows an ESA (Equal Segmentation Adder).
In the example shown in FIG. 4(a), the ESA changes S _{n-1 to S n-k by inputting b n-1} to b _n-k and a _{n -1} to a _{n -k.} S n-2k is output from S n _{- k-1} by inputting the k-bit Adder to be output, b _n-2k from b n-k-1 and a _{n-2k from} a n- _k. It includes a k-bit Adder, and a k-bit Adder that outputs S 0 from S k-1 by inputting b ₀ from b _{k-1 and a 0 from} a _k-1 . ESA is an adder that achieves high speed even at the expense of accuracy by cutting off the propagation of carries that become critical paths and segmenting them.

FIG. 4(b) shows LOA (Lower-part-OR Adder).
In the example shown in FIG. 4(b), the LOA outputs S _{k from S n-1 by inputting b k} from b _n-1 and a _k from a _{n -1} (n- _k )-bit Adder, and a k-bit OR that outputs S 0 from S k _-1 by inputting b ₀ from b _{k -1} and _{a 0 from} a k-1. LOA utilizes the fact that the lower bits of the addition result have a lower influence on the overall error, and uses an OR gate instead of addition for the lower bits.
By doing so, the same effect as ESA can be obtained. Both ESA and LOA are methods that consider the trade-off between accuracy and calculation speed. The calculation method of the calculation device according to the embodiment differs from both ESA and LOA in that it performs rough calculations using serial calculations.

As described above, the serial adder shown in FIG. 4C receives input from the lower bits and outputs from the lower bits.
In the example shown in FIG. 4(c), the serial adder includes a flip-flop (FF: flip-flop) to which a _i (i=0...n) is input, and a flip-flop to which b _i is input. and a Full Adder to which the output of the flip-flop to which a _i is input and the output of the flip-flop to which b _i is input are input. Further, the serial adder includes two flip-flops to which the output of the Full Adder is input. Among the outputs of each of the two flip-flops, one output is Si, and the other output is input to the Full Adder.
In the calculation process by the serial adder shown in FIG. 4(c), the upper bits are not known. Therefore, in the serial adder shown in FIG. 4(c), the final addition result cannot be known until all bits are output. In contrast, the arithmetic device according to the embodiment can output an approximate value of the arithmetic result by performing the arithmetic operation from the upper bits and outputting the first bit. Furthermore, as the number of output bits increases, the calculation result approaches the correct calculation result, although it includes an error.

Comparisons were made regarding the computation time of the parallel general adder, serial adder, and the computation method of the embodiment described above. As an example, in order to obtain Equation (1), calculation times were compared using an application that derives the sum from a ₁ to a _N (N is an integer where N>0).

FIG. 5 is a diagram showing an example 1 of comparison results between the calculation method of the calculation device according to the embodiment and the conventional calculation method. FIG. 5 shows an example of the configuration of an adder used for comparison of calculation times. FIG. 5 shows, as an example, the case where the sum of a ₁₅ is derived from a ₀ . As shown in FIG. 5, 16 sums of inputs a ₀ to a ₁₅ are derived using 16 adders arranged in a tree shape.
FIG. 6 is a diagram showing example 2 of comparison results between the calculation method of the calculation device according to the embodiment and the conventional calculation method.
In FIG. 6, in general, the number of bits of the input value is set to M, the number of input values is set to N, and the calculation time when deriving the sum is calculated. In FIG. 6, as an example, M is set to 8, 16, 32, and 64, and N is set to 16, 32, 64, and 128. Furthermore, the calculation time was expressed in terms of the number of clocks.
According to FIG. 6, when a serial adder is used, the calculation is completed in M+2log ₂ N clocks. When a parallel adder is used, assuming that a significant calculation can be performed in one clock, the calculation is completed in M+log ₂ N clocks. On the other hand, according to the calculation method of the calculation device according to the embodiment, it takes at least log ₂ N clocks until the first bit of the calculation result is output. Further, according to the calculation method of the calculation device according to the embodiment, the calculation is completed in M+2log ₂ N clocks.
As described above, the calculation method of the calculation device according to the present embodiment allows approximate calculation to be performed with a smaller number of clocks than the conventional calculation method described above.

Next, we examined the absolute error of the calculation results output by the calculation device according to this embodiment.
FIG. 7 is a diagram showing an example of the absolute error of the calculation result by the calculation device according to the present embodiment. In FIG. 7, the horizontal axis is the absolute error value, and the vertical axis is the frequency. In the example shown in FIG. 7, the number of input values is two, and each of the two input values is 8 bits. Since an 8-bit input value expressed as a binary number can represent a number from 0 to 255, the result of addition of two input values is included in the range from 0 to 510. FIG. 7 is a graph of the frequency, which is a number indicating how many absolute error values appear for each of the absolute error values from 0 to 510.
According to FIG. 7, when the absolute error value is 0, the frequency is about 1800, and as the absolute error value increases, the frequency decreases. If the absolute error value becomes greater than 128, the frequency becomes 0. According to the calculation method by the calculation device according to the present embodiment, it can be seen that the absolute error values are distributed within 128. Therefore, when the number of input values is two, each of the two input values is 8 bits, and the absolute error value is allowed to be 128 or less, the calculation by the arithmetic device according to the present embodiment is It turns out that there is no problem using this method.

In the embodiment described above, a case has been described in which the calculation unit 130 derives the calculation result by the hardware processor executing the program (software) stored in the storage unit 150, but the present invention is not limited to this example. For example, the calculation unit 130 may be configured with hardware.
FIG. 8 is a diagram illustrating an example of a calculation unit of the calculation device according to the embodiment. FIG. 8 shows an example of the above-described calculation unit 130 configured by hardware.
The calculation unit 130 includes a flip-flop 11, a flip-flop 12, an OR gate 13, an XOR gate 14, an AND gate 15, a multiplexer 16, a flip-flop 17, a NOT gate 18, and a flip-flop 19. Consists of.

The input a _i (i=n...0) is input to the flip-flop 11 every K bits starting from the most significant bit. The input b _i is input to the flip-flop 12 every K bits starting from the most significant bit.
The output of the flip-flop 11 is branched, one being input to the OR gate 13 and the other being output to the XOR gate 14.
The output of the flip-flop 12 is branched, one being input to an OR gate 13 and the other being output to an XOR gate 14.
The OR gate 13 derives the logical sum of the output of the flip-flop 11 and the output of the flip-flop 12, and outputs the logical sum result to the AND gate 15.
The XOR gate 14 derives the exclusive OR of the output of the flip-flop 11 and the output of the flip-flop 12, and outputs the result of the exclusive OR to the multiplexer 16.

The multiplexer 16 outputs either the exclusive OR derivation result outputted by the XOR gate 14 or "1" to the flip-flop 17 based on the selection control input. The output of flip-flop 17 is branched, one input to multiplexer 16 as a selection control input, and the other output to NOT gate 18.
The NOT gate 18 derives the logical negation of the output of the flip-flop 12 and outputs the logical negation result to the AND gate 15.
The AND gate 15 derives the logical product of the output of the OR gate 13 and the output of the NOT gate 18 , and outputs the result of the logical product to the flip-flop 19 .
The flip-flop 19 outputs the calculation result Si every K bits starting after L clocks.

In the embodiment described above, a case has been described in which the arithmetic device 100 is caused to execute a computation by transmitting a computation request to the terminal device 200, but the present invention is not limited to this example. For example, a plurality of input values may be directly input to the arithmetic device 100. In this case, the arithmetic device 100 receives each of the plurality of input values, and transfers each of the plurality of input values from the most significant bit to one or every K bits based on the bit K of the serial transfer. Get values that correspond to multiple digits. The arithmetic device 100 calculates a plurality of values from the most significant bit to a value corresponding to one or more digits for every K bits among the values corresponding to one or more digits of each of the plurality of acquired input values. Add each input value. For example, the arithmetic device 100 outputs the arithmetic result every K bits starting from the most significant bit starting after L clocks based on the number L of delay clocks during addition. The calculation device 100 may display the calculation results on a display device (not shown).

In the embodiment described above, a case has been described in which the serial transfer bit K is 1 and the number of delay clocks L during addition is 1, but the present invention is not limited to this example. The calculation unit 130 may perform addition every K bits (K is an integer satisfying the value of the calculation digit number information 152≧K>0) from the most significant bit based on the bit K of the serial transfer. In this case, the output unit outputs the result of addition for every K bits starting from the most significant bit after L clocks (L is L>number of multiple input values) based on the number of delay clocks L during addition. do.
With this configuration, carry etc. can be reflected, so it is possible to obtain a value closer to the accurate calculation result than when the serial transfer bit K is 1 and the number of delay clocks L during addition is 1. can.
In the embodiment described above, a case has been described in which the serial transfer bit K and the number of delay clocks L during addition are set in the arithmetic device 100, but the present invention is not limited to this example. For example, when user U performs an operation to input serial transfer bit K and delay clock number L during addition to terminal device 200, terminal device 200 inputs serial transfer bit K , and information indicating the number of delay clocks L at the time of addition, and a computation request destined for the computation device 100 may be created.
In the embodiment described above, in the arithmetic device 100, the arithmetic unit 130 converts each of the plurality of acquired input values into the most significant value among the values corresponding to one or more digits based on the bit K of the serial transfer. Each of the plurality of input values is added up to a value corresponding to one or more digits for every K bits. Although a case has been described in which the output unit 140 outputs every K bits starting after L clocks based on the number L of delay clocks during addition, the present invention is not limited to this example. For example, the calculation unit 130 may stop the calculation when the addition result for every K bits starting from the most significant bit is equal to or greater than a threshold value. This is because, when determining whether or not the calculation result is equal to or greater than the threshold value, even if the calculation is continued after the calculation result is found to be equal to or greater than the threshold value, the calculation is unnecessary. With this configuration, unnecessary calculations can be reduced.

According to the arithmetic device according to the embodiment, the arithmetic device 100 includes the reception unit 120 that receives a plurality of input values, and the number of digits from the most significant bit that is set based on the allowable error in the calculation result. , from the most significant bit of each of the plurality of input values to the number of digits, add each of the plurality of input values output by the reception unit every K bits (K is an integer where K>0) from the most significant bit. , an arithmetic unit 130 that performs the operation every K bits from the most significant bit, and an output that outputs the addition result by the arithmetic unit 130 every K bits from the most significant bit after L (L is an integer where L>0) clocks later. 140.
With this configuration, the arithmetic device 100 receives an input value such as a plurality of bit serial data every K bits from the most significant bits, adds up every K bits before receiving all bits of the input value, Since the calculation result obtained by addition can be output every K bits after L clocks, a rough calculation result can be output. At this time, the calculation result includes an error, but in this embodiment, the range of the error can be determined, so that if the error is within the allowable error range, the result can be obtained with short latency.
Furthermore, since carry and the like can be reflected, a value closer to an accurate calculation result can be obtained than when addition is performed bit by bit starting from the most significant bit.
Further, the calculation unit 130 stops the addition when the addition result of the most significant bit is equal to or greater than the threshold value. With this configuration, unnecessary calculations can be reduced.

The arithmetic device according to the embodiment processes a large amount of data, such as a hardware accelerator, artificial intelligence, or neural network accelerator that solves a combinatorial optimization problem using an approximate solution method, but the calculation accuracy may include some error. Can be applied to various fields.
In particular, simulated annealing (SA), genetic algorithm (GA), particle optimization method (PSO), etc., which are approximate solutions for combinatorial optimization problems, perform a large amount of calculations, but each Accuracy does not significantly affect the results. Therefore, by applying such a general solution method, the range of application can be further expanded. Similarly, by applying deep neural network processing, especially to structures such as spiking neural networks, it is possible to achieve miniaturization and lower power consumption.

(Modified example of embodiment)
[overall structure]
FIG. 9 is a configuration diagram of a calculation system including a calculation device according to a modification of the embodiment. A computing system 1a according to a modification of the embodiment includes a computing device 100a and a terminal device 200 used by one or more users U.
The computing device 100a and the terminal device 200 can communicate with each other via the network NW.

When the user U performs an operation on the terminal device 200 to connect to the computing device 100a, the terminal device 200 connects to the computing device 100a via the network NW. The terminal device 200 accesses the calculation service website provided by the calculation device 100a.
The user U performs an operation on the terminal device 200 to input error information in addition to a plurality of input values, in accordance with the display on the calculation service website.
The terminal device 200 acquires a plurality of input values and error information input by the user U, and creates a calculation request that includes the plurality of acquired input values and error information and is addressed to the calculation device 100a. The terminal device 200 transmits the created calculation request to the calculation device 100a.

The calculation device 100a receives the calculation request sent by the terminal device 200. The arithmetic device 100 receives each of the plurality of input values included in the received arithmetic request and error information. The arithmetic device 100a acquires information indicating the number of digits stored in association with the received error information, and sets information indicating the acquired number of digits. Based on the information indicating the set number of digits, the arithmetic device 100a obtains a value corresponding to the number of digits from the most significant bit of each of the plurality of input values. The arithmetic device 100a adds each of the plurality of input values, from the most significant bit to the value corresponding to the number of digits, from the obtained value corresponding to the number of digits or one or more digits, to the number of bits K for serial transfer. Based on this, the processing is performed every K bits (K is an integer where K>0) starting from the most significant bit. In other words, from the most significant bit, bits lower than the number of digits are treated as zero. The arithmetic device 100a outputs the arithmetic result every K bits, based on the number L of delay clocks during addition, starting after L clocks (L is an integer where L>0). For example, the arithmetic device 100a outputs the arithmetic result every K bits starting from the most significant bit. The calculation device 100a creates a calculation response that includes the calculation result and is addressed to the terminal device 200, and transmits the created calculation response to the terminal device 200.
The terminal device 200 receives the calculation response transmitted by the calculation device 100a, and acquires the calculation result included in the received calculation response. The terminal device 200 outputs the obtained calculation result.
Hereinafter, among the arithmetic device 100a included in the arithmetic system 1a and the terminal device 200, the arithmetic device 100a that is different from the embodiment will be described.

[Arithmetic device 100a]
The arithmetic device 100a included in the arithmetic system 1a is realized by a device such as a personal computer, a server, or an industrial computer. The calculation device 100a includes, for example, a communication section 110, a reception section 120a, a calculation section 130a, an output section 140, a storage section 150, and a setting section 160.
The storage unit 150a is realized by an HDD, flash memory, RAM, ROM, or the like. The storage unit 150a stores an error information digit number related table 154.
The error information digit number related table 154 is information in a table format that associates error information with information indicating the number of digits from the most significant bit used in calculations. In the error information digit number related table 154, the smaller the error information value, the larger the value of the number of digits from the most significant bit used for calculation, and the smaller the error information value, the larger the value of the calculation digit number information 152. The error information and the information indicating the number of digits are stored so that the number of digits becomes small. This is because the smaller the value of the error information, the higher the accuracy required for the calculation result, and the larger the value of the error information, the lower the accuracy required for the calculation result.

The reception unit 120a, the calculation unit 130a, the output unit 140, and the setting unit 160 are realized, for example, by a hardware processor such as a CPU executing a program (software) stored in the storage unit 150a. Further, some or all of these functional units may be realized by hardware (including circuitry) such as LSI, ASIC, FPGA, or GPU, or may be realized by collaboration between software and hardware. may be done.
The program may be stored in advance in a storage device such as an HDD or flash memory (storage device equipped with a non-transitory storage medium), or may be stored in a removable storage medium (non-transitory storage medium) such as a DVD or CD-ROM. The software may be installed by attaching the storage medium to a drive device.

The reception unit 120a receives a plurality of input values and error information included in the calculation request received by the communication unit 110. The plurality of input values received by the reception unit 120a are output to the calculation unit 130, and error information is output to the setting unit 160. Here, if the received input values have different numbers of digits, the reception unit 120a performs digit alignment. The reception unit 120a outputs each of the plurality of input values to the calculation unit 130a in units of K bits starting from the most significant bit based on bit K of the serial transfer. Here, bit K for serial transfer is set in advance.
The setting unit 160 acquires the error information received by the receiving unit 120a. The setting unit 160 acquires information indicating the number of digits stored in association with the acquired error information from the error information digit number related table 154 stored in the storage unit 150a, and stores the information indicating the acquired number of digits. Set.
The calculation unit 130a acquires each of the plurality of input values received by the reception unit 120a, every K bits starting from the most significant bit. The calculation unit 130a acquires information indicating the number of digits set by the setting unit 160. Based on the acquired information indicating the number of digits, the calculation unit 130a acquires every K bits from the most significant bit of each of the plurality of acquired input values up to the value corresponding to the information indicating the number of digits. do.
The calculation unit 130a adds each of the plurality of input values from the most significant bit of the obtained value corresponding to the number of digits to the value corresponding to the information indicating the number of digits. The calculation unit 130a outputs the result of adding each of the plurality of input values from the most significant bit to the value corresponding to the number of digits to the output unit 140 every K bits from the most significant bit. The calculation unit 130a processes the lower bits starting from the most significant bit and treating the lower bits of the value corresponding to the information indicating the number of digits as 0.

(Operation of calculation system)
FIG. 10 is a sequence chart illustrating an example of the operation of the arithmetic system according to a modification of the embodiment.
In the example shown in FIG. 10, when the user U operates the terminal device 200, the terminal device 200 connects to the computing device 100a and accesses the computing service website provided by the computing device 100a. The premise is that.
(Step S11)
When the user U performs an operation to input a plurality of input values and error information to the terminal device 200, the terminal device 200 includes the input plurality of input values and error information, and performs a calculation. A computation request is created with the device 100a as the destination.
(Step S12)
The terminal device 200 transmits the created calculation request to the calculation device 100a.
(Step S13)
In the computing device 100a, the communication unit 110 receives the computing request transmitted by the terminal device 200.
(Step S14)
In the calculation device 100a, the reception unit 120a acquires the calculation request received by the communication unit 110, and receives a plurality of input values and error information included in the acquired calculation request. The reception unit 120a adjusts the digits of each of the plurality of input values as necessary. The reception unit 120a outputs each of the plurality of input values to the calculation unit 130a in units of K bits starting from the most significant bit based on bit K of the serial transfer.

(Step S15)
In the arithmetic device 100a, the setting unit 160 acquires the error information received by the receiving unit 120a, and stores information indicating the number of digits stored in association with the acquired error information in the error information digit number related table in the storage unit 150a. 154. The setting unit 160 sets information indicating the obtained number of digits.
(Step S16)
In the arithmetic device 100a, the arithmetic unit 130a acquires each of the plurality of input values accepted by the reception unit 120, every K bits, starting from the most significant bit. The calculation unit 130a acquires information indicating the number of digits set by the setting unit 160. Based on the acquired information indicating the number of digits, the calculation unit 130a acquires every K bits from the most significant bit of each of the plurality of acquired input values up to the value corresponding to the information indicating the number of digits. do.
(Step S17)
In the arithmetic device 100a, the arithmetic unit 130a adds each of the plurality of input values from the most significant bit of the value corresponding to the information indicating the number of digits obtained to the value corresponding to the information indicating the number of digits. . The calculation unit 130a outputs the result of adding each of the plurality of input values from the most significant bit to the value corresponding to the number of digits to the output unit 140 every K bits from the most significant bit. The output unit 140 outputs the calculation result by the calculation unit 130a every K bits starting from the most significant bit starting after L clocks based on the number L of delay clocks at the time of addition.
(Step S18)
In the calculation device 100a, the output unit 140 creates a calculation response that includes the calculation result and is addressed to the terminal device 200, and outputs the created calculation response to the communication unit 110.
(Step S19)
In the calculation device 100a, the communication unit 110 acquires the calculation response output by the output unit 140, and transmits the acquired calculation result to the terminal device 200.
Thereafter, the terminal device 200 receives the calculation response transmitted by the calculation device 100a, and acquires the calculation result included in the received calculation response. The terminal device 200 outputs the obtained calculation result.

In the modification of the embodiment described above, a case has been described in which the calculation device 100a is caused to execute a calculation by transmitting a calculation request to the terminal device 200, but the present invention is not limited to this example. For example, a plurality of input values and error information may be directly input to the arithmetic device 100a. In this case, the arithmetic device 100a receives each of the plurality of input values and the error information, and stores information indicating the digit stored in association with the received error information in the error information digit number of the storage unit 150a. Obtained from the related table 154. The arithmetic device 100a sets information indicating the obtained digit. The arithmetic device 100a acquires each of the plurality of input values from the most significant bit to the value corresponding to the information indicating the set number of digits for each K bit based on the bit K of the serial transfer. The arithmetic device 100a calculates the plurality of input values from the most significant bit to the value corresponding to the information indicating the number of digits for every K bits among the values corresponding to the information indicating the number of digits of each of the plurality of acquired input values. Perform the addition of each. For example, the arithmetic device 100a outputs the arithmetic result every K bits starting from the most significant bit after L clocks based on the number L of delay clocks during the arithmetic operation. The calculation device 100a may display the calculation results on a display device (not shown).
In the modification of the embodiment described above, a case has been described in which the serial transfer bit K is 1 and the number of delay clocks L during addition is 1, but the present invention is not limited to this example. The calculation unit 130a may perform addition every K bits (K is an integer of information indicating the number of digits≧K>0) from the most significant bit based on the bit K of the serial transfer. In this case, the output unit outputs the result of addition for every K bits starting from the most significant bit after L clocks (L is L>number of multiple input values) based on the number of delay clocks L during addition. do.
With this configuration, carry etc. can be reflected, so it is possible to obtain a value closer to the accurate calculation result than when the serial transfer bit K is 1 and the number of delay clocks L during addition is 1. can.
In the modification of the embodiment described above, a case has been described in which the serial transfer bit K and the number of delay clocks L during addition are set in the arithmetic device 100a, but the present invention is not limited to this example. For example, when user U performs an operation to input serial transfer bit K and delay clock number L during addition to terminal device 200, terminal device 200 inputs serial transfer bit K An arithmetic request may be created that includes information indicating , and information indicating the number of delay clocks L during addition, and is directed to the arithmetic device 100a.

In the modification of the embodiment described above, in the arithmetic device 100a, the arithmetic unit 130a converts each of the plurality of acquired input values into the most significant bit of the value corresponding to the number of digits based on the bit K of the serial transfer. Then, each of the plurality of input values is added up to a value corresponding to one or more digits for each K bit. Although a case has been described in which the output unit 140 outputs every K bits starting after L clocks based on the number L of delay clocks during addition, the present invention is not limited to this example. For example, the calculation unit 130a may stop the calculation when the addition result for every K bits starting from the most significant bit is equal to or greater than a threshold value. This is because, when determining whether or not the calculation result is equal to or greater than the threshold value, even if the calculation is continued after the calculation result is found to be equal to or greater than the threshold value, the calculation is unnecessary. With this configuration, unnecessary calculations can be reduced.
In the modification of the embodiment described above, the arithmetic device 100a receives error information and acquires information indicating digits stored in association with the received error information from the error information digit number related table 154 in the storage unit 150a. Although the case has been described, the present invention is not limited to this example. For example, an arithmetic expression for deriving the number of digits from the error information may be stored in the storage unit 150a. In this case, the calculation unit 130a may derive and set the number of digits based on the calculation formula.

According to the arithmetic device according to the modification of the embodiment, the arithmetic device 100a includes a reception unit 120a that receives a plurality of input values, and a number of digits from the most significant bit that is set based on an allowable error in the calculation result. From the most significant bit of each of the plurality of input values to the number of digits, the reception unit 120a outputs each of the plurality of input values every K bits (K is an integer where K>0) based on the most significant bit of each of the plurality of input values. An arithmetic unit 130a performs addition every K bits starting from the most significant bit, and outputs the addition result by the arithmetic unit 130a every K bits starting from the most significant bit after L (L is an integer where L>0) clocks later. and an output section 140.
With this configuration, the arithmetic device 100a receives input values such as a plurality of bit serial data every K bits from the most significant bits, adds them every K bits before receiving all bits of the input value, Since the calculation result obtained by addition can be output every K bits after L clocks, a rough calculation result can be output. At this time, the calculation result includes an error, but in this embodiment, the range of the error can be determined, so that if the error is within the allowable error range, the result can be obtained with short latency.

Furthermore, the reception unit 120a receives error information required for the calculation result, and the calculation device 100a selects the most significant bit of each of the plurality of input values used for addition based on the error information received by the reception unit 120a. The calculation unit 130a includes a setting unit 160 that sets the number of digits, and the calculation unit 130a allows the receiving unit 120a to calculate the number of digits set by the setting unit 160 from the most significant bit of each of the plurality of input values, based on the number of digits set by the setting unit. Addition of each of the plurality of input values outputted every K bits from the most significant bit is performed every K bits from the most significant bit up to the number of digits.
With this configuration, the number of digits from the most significant bit of each of the multiple input values used for addition can be set based on the error information required for the calculation result, which improves the flexibility of calculation. .
Further, the setting unit 160 stores the error information received by the reception unit 120a from the storage unit 150a that stores error information required for the calculation result in association with the number of digits from the most significant bit of each of the plurality of input values. The number of digits from the most significant bit of each of the plurality of input values is obtained based on .
With this configuration, the received error is determined based on the information that associates the error information required for the calculation result stored in the storage unit 150a with the number of digits from the most significant bit of each of the plurality of input values. Based on the information, the number of digits from the most significant bit of each of multiple input values can be obtained, which is simpler than calculating the number of digits from the most significant bit of each of multiple input values. can be converted into

Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, changes, and combinations can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.
Note that the arithmetic device 100, terminal device 200, and arithmetic device 100a described above each have a computer inside. The processes of each of the above-mentioned devices are stored in a computer-readable recording medium in the form of a program, and the above-mentioned processes are performed by reading and executing this program by the computer. Here, the computer-readable recording medium refers to a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, and the like. Alternatively, this computer program may be distributed to a computer via a communication line, and the computer receiving the distribution may execute the program.
Moreover, the above-mentioned program may be for realizing a part of the above-mentioned functions.
Furthermore, it may be a so-called difference file (difference program) that can realize the above-described functions in combination with a program already recorded in the computer system.

1, 1a... Arithmetic system, 11, 12, 17, 19... Flip-flop, 13... OR gate, 14... XOR gate, 15... AND gate, 16... Multiplexer, 18... NOT gate, 100, 100a... Arithmetic device, 110 ...Communication section, 120, 120a...Reception section, 130, 130a...Calculation section, 140...Output section, 150...Storage section, 160...Setting section, 152...Calculation digit number information, 154...Error information digit number related table, 200 …terminal device

Claims (4)

a reception unit that accepts error information required for multiple input values and calculation results ;
a setting unit that sets the number of digits from the most significant bit of each of the plurality of input values used for addition, based on the error information received by the reception unit;
Based on the number of digits from the most significant bit set by the setting unit , the reception unit calculates the number of digits from the most significant bit from the most significant bit of each of the plurality of input values to the number of digits set by the setting unit. an arithmetic unit that adds each of the plurality of input values outputted every K bits (K is an integer where K>0) every K bits from the most significant bit;
An arithmetic device comprising: an output section that outputs the addition result by the arithmetic section from the most significant bit every K bits after L (L is an integer where L>0) clocks. The setting section is configured to perform processing based on the error information received by the reception section from a storage section that stores error information required for the calculation result in association with the number of digits from the most significant bit of each of the plurality of input values. The arithmetic device according to claim 1 , wherein the number of digits from the most significant bit of each of the plurality of input values is acquired. The arithmetic device according to claim 1 or 2 , wherein the arithmetic unit stops the addition when the addition result of the most significant bit is equal to or greater than a threshold value. accepting error information required for multiple input values and calculation results ;
setting the number of digits from the most significant bit of each of the plurality of input values used for addition, based on the error information received in the accepting step;
Based on the number of digits from the most significant bit set in the setting step , K bits are added from the most significant bit from the most significant bit of each of the plurality of input values to the number of digits set in the setting step. (K is an integer where K>0), adding each of the plurality of input values output every K bits from the most significant bit;
An arithmetic method executed by an arithmetic device, comprising: outputting the addition result from the step of performing the addition from the most significant bit every K bits after L clocks (L is an integer where L>0).

Images