JP7434087B2 - Cancellation control device and communication device - Google Patents

Description

Embodiments of the present invention relate to a cancellation control device and a communication device.

In a communication device that uses an antenna for both transmission and reception, a part of the transmitted signal may be superimposed on the received signal and flow into the receiving system. The transmitted signal component superimposed on the received signal becomes a self-interference signal, which may cause saturation of the receiving system and an increase in noise, leading to deterioration in communication quality.
Therefore, a technique is known in which a cancellation signal having a phase opposite to that of the self-interference signal is generated from the transmission signal, and this cancellation signal is used to cancel the self-interference signal.

However, the setting of the attenuation amount and the phase shift amount for generating an appropriate cancellation signal has conventionally been performed by sweeping the phase shift amount and the attenuation amount, and the time required for the setting has become long.
Under these circumstances, it has been desired to shorten the time required for setting to generate a cancellation signal.

Japanese Patent Application Publication No. 2010-8313

The problem to be solved by the present invention is to provide a cancellation control device and a communication device that can reduce the time required for settings for generating a cancellation signal.

The cancellation control device of the embodiment includes a first detection section and a determination section. The first detection section detects the DC levels of the first I signal and the first Q signal output by the quadrature detector, respectively. The determination unit determines an attenuation amount and a phase shift amount for generating a cancellation signal from the transmission signal for canceling a component of the transmission signal included in the first orthogonal modulation signal input to the quadrature detector. It is determined by calculation based on the two DC levels detected by the detection unit and the amplitude and phase of the transmission signal.

FIG. 1 is a block diagram showing a main circuit configuration of a reading device according to a first embodiment. FIG. 2 is a diagram showing a configuration example of a quadrature detector and a DC detection circuit in FIG. 1; 5 is a flowchart of information processing for controlling the reduction of self-interference signals. FIG. 2 is a timing diagram regarding the operation of the reading device shown in FIG. 1; FIG. 2 is a block diagram showing a main circuit configuration of a reading device according to a second embodiment.

Some embodiments will be described below with reference to the drawings. In the following, a reading device that reads data stored in an RFID (radio frequency identification) tag will be described as an example. This reading device performs wireless communication with the RFID tag when reading the above data, and is an example of a communication device.

[First embodiment]
FIG. 1 is a block diagram showing the main circuit configuration of a reading device 100 according to the first embodiment.
The reading device 100 includes an oscillator 11, a phase shifter 12, a DA (digital to analog) converter 13, a quadrature modulator 14, a BPF (band-pass filter) 15, a power amplifier 16, an LPF (low-pass filter) 17, Antenna duplexer 18, feed line 19, antenna 20, variable attenuator 21, variable phase shifter 22, power combiner 23, low noise amplifier 24, quadrature detector 25, BPF 26, baseband amplifier 27, AD (analog to digital ) Contains a converter 28, a DC detection circuit 29, an AD converter 30, an arithmetic circuit 31, a control circuit 32, a CPU 33, and a memory 34. Note that the antenna 20 or the feeder line 19 and the antenna 20 may not be included in the reading device 100 and may be connected to any separate device.

The oscillator 11 generates a sine wave of a predetermined frequency as a carrier wave.
The phase shifter 12 shifts the phase of the carrier wave generated by the oscillator 11 by 90 degrees, and outputs the cosine wave as another carrier wave.
The DA converter 13 converts the two transmission baseband signals output in digital form from the CPU 33 into analogs. Note that hereinafter, the two systems of transmission baseband signals are referred to as an I signal and a Q signal, respectively.

The orthogonal modulator 14 receives the I signal and Q signal converted into analog signals by the DA converter 13 as modulated waves. The quadrature modulator 14 inputs the carrier wave generated by the oscillator 11 and the carrier wave output from the phase shifter 12 as carrier waves of the I system and the Q system, respectively. Then, the orthogonal modulator 14 obtains a transmission signal by orthogonal modulation. The I signal and Q signal converted into analog by the DA converter 13 correspond to a third I signal and a third Q signal. Therefore, the orthogonal modulator 14 is an example of a modulation unit that orthogonally modulates the carrier wave using the third I signal and the third Q signal.

The BPF 15 removes low frequency components and high frequency components from the transmission signal obtained by the quadrature modulator 14 in order to limit the band.
The power amplifier 16 amplifies the power of the transmission signal that has passed through the BPF 15 to a level suitable for wireless transmission.
The LPF 17 removes harmonic components from the transmission signal amplified by the power amplifier 16.
Through these processes in the BPF 15, power amplifier 16, and LPF 17, the transmission signal becomes a signal for wireless transmission. That is, the BPF 15, the power amplifier 16, and the LPF 17 constitute a first generation unit that generates a transmission signal for wireless transmission.

The antenna duplexer 18 includes an input end TI, an input/output end TIO, an output end TOA, and an output end TOB. The transmission signal that has passed through the LPF 17 is input to the input terminal TI. The antenna duplexer 18 outputs the transmission signal input to the input end TI from the input/output end TIO and the output end TOB. The antenna duplexer 18 outputs the signal input to the input/output terminal TIO from the output terminal TOA. The signal output from the output terminal TOA of the antenna duplexer 18 is a signal obtained by combining a received signal generated at the antenna 20 and a self-interference signal to be described later, and this signal will be simply referred to as a received signal below. The antenna duplexer 18 is an example of a shared part.

The feed line 19 supplies the antenna 20 with the transmission signal output from the input/output terminal TIO of the antenna duplexer 18 . The feed line 19 transmits the received signal generated at the antenna 20 to the input/output terminal TIO of the antenna duplexer 18.
The antenna 20 emits radio waves according to the transmission signal supplied by the feed line 19. The antenna 20 generates an electric signal as a received signal according to the incoming radio waves.

The variable attenuator 21 attenuates the transmission signal output from the output terminal TOB of the antenna duplexer 18 by an attenuation amount set under the control of the control circuit 32.
The variable phase shifter 22 changes the phase of the transmission signal after being attenuated by the variable attenuator 21 by a phase shift amount set under the control of the control circuit 32. The transmission signal after being phase-shifted by the variable phase shifter 22 is hereinafter referred to as a cancellation signal.
Thus, the variable attenuator 21 and the variable phase shifter 22 constitute a second generation section that generates a cancellation signal.
The power combiner 23 power-combines the reception signal output from the output end TOA of the antenna duplexer 18 with the cancellation signal output from the variable phase shifter 22 . Thereby, the power combiner 23 reduces the self-interference signal included in the received signal. The power combiner 23 is an example of a combiner.

The low noise amplifier 24 amplifies the received signal output from the power combiner 23 while suppressing noise generation.
The quadrature detector 25 quadrature-detects the received signal amplified by the low-noise amplifier 24 using two carrier waves output from the oscillator 11 and the phase shifter 12, respectively. The quadrature detector 25 outputs analog received baseband signals of two systems, an I system and a Q system, obtained by the quadrature detection in parallel. These two analog reception baseband signals correspond to a first I signal and a first Q signal. In other words, the quadrature detector 25 is an example of a second detection section.

The BPF 26 extracts components in a desired frequency band from each of the two systems of received baseband signals output from the quadrature detector 25.
The baseband amplifier 27 amplifies each of the two systems of received baseband signals that have passed through the BPF 26 to a level suitable for digitization by the AD converter 28.
The AD converter 28 digitizes each of the two systems of received baseband signals amplified by the baseband amplifier 27.

The DC detection circuit 29 detects DC signals included in each of the two systems of received baseband signals output from the quadrature detector 25. That is, the DC detection circuit 29 is an example of a first detection section.
The AD converter 30 digitizes the two systems of DC signals detected by the DC detection circuit 29, respectively.

The arithmetic circuit 31 calculates the amount of attenuation in the variable attenuator 21 and the amount of phase shift in the variable phase shifter 22 based on the DC signal digitized by the AD converter 30. The arithmetic circuit 31 is, for example, a hardware circuit that executes an arithmetic operation based on a predetermined mathematical formula. The arithmetic circuit 31 is an example of a determining section.
The control circuit 32 sets the amount of attenuation in the variable attenuator 21 to the amount of attenuation calculated by the calculation circuit 31. The control circuit 32 sets the amount of phase shift in the variable phase shifter 22 to the amount of phase shift calculated by the arithmetic circuit 31.

When communicating with the RFID tag 200, the CPU 33 outputs an I signal and a Q signal according to a predetermined sequence. The CPU 33 reconstructs the data sent from the RFID tag 200 based on the two systems of received signals digitized by the AD converter 28. The CPU 33 executes a control process described later for adjusting the amount of attenuation in the variable attenuator 21 and the amount of phase shift in the variable phase shifter 22.
The memory 34 stores an information processing program that describes information processing to be executed by the CPU 33. The memory 34 stores various data necessary for the CPU 33 to perform various information processing. The memory 34 stores various data generated or acquired when the CPU 33 executes various information processing.

FIG. 2 is a diagram showing a configuration example of the quadrature detector 25 and the DC detection circuit 29.
Quadrature detector 25 includes a power divider DIS and mixers MII and MIQ.
The power divider DIS divides the received signal output from the low noise amplifier 24 into two. The mixer MIQ extracts a Q-system received baseband signal by combining the carrier wave output from the oscillator 11 with one of the received signals distributed by the power divider DIS. The mixer MII extracts the received baseband signal of the I system by combining the carrier wave output from the phase shifter 12 with the other of the received signals distributed by the power divider DIS.

The DC detection circuit 29 includes two extraction circuits EXI and EXQ. The I-system received baseband signal output from the mixer MII of the quadrature detector 25 is input to the extraction circuit EXI. The Q-system received baseband signal output from the mixer MIQ of the quadrature detector 25 is input to the extraction circuit EXQ.

Both extraction circuits EXI and EXQ include an operational amplifier OA, resistors RS, RAC, RDC, and a capacitor CO. One end of the resistor RS is connected to one of the output ends of the mixers MII, MIQ, and the other end is connected to the junction point POA. One end of the resistor RDC is connected to the junction point POA, and the other end is connected to the junction point POB. One end of the resistor RAC is connected to the junction point POA, and the other end is connected to one end of the capacitor CO. Capacitor CO is connected at one end to resistor RAC and at the other end to junction POB. The operational amplifier OA has a non-inverting input terminal connected to ground, an inverting input terminal connected to a junction point POA, and an output terminal connected to a junction point POB. The potential of the junction point POB in the extraction circuit EXI is determined according to the level of the DC component included in the received baseband signal of the I system. Therefore, a DC signal extracted from the received baseband signal of the I system appears at the junction point POB in the extraction circuit EXI, and is input to the AD converter 30. Further, the potential of the junction point POB in the extraction circuit EXQ is determined according to the level of the DC component included in the received baseband signal of the Q system. Therefore, a DC signal extracted from the received baseband signal of the Q system appears at the junction point POB in the extraction circuit EXQ, and is input to the AD converter 30.

Next, the operation of the reading device 100 configured as above will be explained. Note that the operation for reading the RFID tag 200 may be any other known operation that uses, for example, an orthogonal modulation method as a modulation method for wireless communication. Therefore, the explanation of the operation will be omitted here, and the operation for adjusting the amount of attenuation in the variable attenuator 21 and the amount of phase shift in the variable phase shifter 22 will be explained.

Prior to explaining the operation, the self-interference signal will be explained.
The antenna duplexer 18 is designed so that the transmission signal input to the input end TI is not output from the output end TOA. However, in an actual circuit configuration, it is difficult to completely prevent the transmission signal input to the input terminal TI from leaking from the output terminal TOA. Therefore, a part of the transmission signal input to the input terminal TI is output as is from the output terminal TOA. Further, a part of the transmission signal output from the input/output terminal TIO of the antenna duplexer 18 is reflected at the feed point of the antenna 20 and transmitted to the antenna duplexer 18 via the feed line 19. Such a reflected signal is output from the output terminal TOA by the function of the antenna duplexer 18. In this way, the signal output from the output terminal TOA of the antenna duplexer 18 includes a component of the transmission signal that leaked out without being output from the input/output terminal TIO, and a component of the transmission signal that is input as a reflected signal to the input/output terminal TIO. and is included. A signal obtained by combining the components of such transmission signals is a self-interference signal. Note that the characteristics of reflection of the transmitted signal at the feeding point of the antenna 20 change depending on the environment around the antenna 20, such as the proximity of the RFID tag 200 and other objects to the antenna 20. Therefore, the amplitude and phase of the signal reflected at the feeding point of the antenna 20 also vary depending on the environment around the antenna 20. Due to this influence, the amplitude and phase of the self-interference signal also vary depending on the environment around the antenna 20.

Note that the self-interference signal is a signal derived from a transmission signal. Therefore, by changing the amplitude and phase of the signal branched from the transmission signal, it is possible to generate a signal that has the same frequency and amplitude as the self-interference signal, but has the opposite phase. By combining such a signal with the received signal output from the output end TOA of the antenna duplexer 18, the self-interference signal contained in the received signal can be canceled out. In the reading device 100, a cancellation signal obtained by varying the amplitude and phase with a variable attenuator 21 and a variable phase shifter 22 is combined with a received signal output from an output end TOA of an antenna duplexer 18 in a power combiner 23. By combining, the self-interference signal contained in the received signal is reduced.

Now, when the reading device 100 is in an operating state, the CPU 33 executes information processing for controlling the reduction of self-interference signals as described above according to an information processing program stored in the memory 34.
FIG. 3 is a flowchart of information processing for controlling the reduction of self-interference signals.

As ACT1, the CPU 33 instructs the control circuit 32 to initialize the attenuation amount of the variable attenuator 21 and the phase shift amount of the variable phase shifter 22. The initial values of the attenuation amount and the phase shift amount may be predetermined values, or may be values determined based on past setting results. It is assumed that the specified values are zero for the attenuation amount and 180 degrees for the phase shift amount. Alternatively, it is assumed that the predetermined value is determined based on the results of experiments or simulations, or empirical rules so as to increase the possibility of canceling out the self-interference signal. The specified value may be arbitrarily determined, for example, by the designer of the reading device 100. When determining the initial value based on past settings, it is assumed that the initial value is the value that was set when the reading device 100 stopped operating last time. Alternatively, it is assumed that a value frequently set during a past operation period of the reading device 100 is set as the initial value. The initial value can be determined based on past setting results by the control circuit 32 or the CPU 33. Rules for determining the initial value based on past setting results may be arbitrarily determined by, for example, the designer of the reading device 100.

In ACT2, the CPU 33 starts low power transmission. In low-power transmission, the CPU 33 sets the transmission power from the antenna 20 to be sufficiently lower than that during normal communication for reading the RFID tag 200. For example, the CPU 33 provides the DA converter 13 with a digital signal that converts the I signal and Q signal output from the DA converter 13 into DC signals of a predetermined low level. Note that the transmission power during low-power transmission is determined in advance by, for example, the designer of the reading device 100 so that the output of the quadrature detector 25 is not saturated by the self-interference signal.

FIG. 4 is a timing diagram regarding the operation of the reading device 100.
At time TIA, the attenuation amount of the variable attenuator 21 and the phase shift amount of the variable phase shifter 22 are initialized to ΔV-1 and Δφ-1, and low-power transmission is started at the transmission power value TPA. The transmission power value TPA corresponds to a suppression level. In other words, the CPU 33 inputs the I signal and the Q signal as the third I signal and the third Q signal from the DA converter 13 to the quadrature modulator 14 for low power transmission. In cooperation with the converter 13, it functions as an input section.

When low power transmission is started, the transmission signal is input to the input terminal TI of the antenna duplexer 18, so the received signal output from the output terminal TOA of the antenna duplexer 18 includes a self-interference signal. It becomes like this. Further, a transmission signal will be output from the output end TOB of the antenna duplexer 18. The variable attenuator 21 passes the transmission signal output from the output end TOB of the antenna duplexer 18 while attenuating it by a set amount of attenuation. Further, the variable phase shifter 22 passes the transmission signal that has been attenuated by the variable attenuator 21 while changing the phase by a set phase shift amount. As a result, the power combiner 23 enters a state in which both the received signal containing the self-interference signal and the cancellation signal are input.

If the cancellation signal has a completely opposite phase to the self-interference signal, the power combiner 23 combines the cancellation signal with the received signal, thereby canceling out the self-interference signal. However, in many cases, the self-interference signal component remains in the received signal output from the power combiner 23. When the received signal containing the self-interference signal is input to the quadrature detector 25, the self-interference signal of each system is included in the DC component of the two systems of received baseband signals output from the quadrature detector 25. Appears as. This DC component is detected by the DC detection circuit 29, digitized by the AD converter 30, and then input to the arithmetic circuit 31.

The calculation circuit 31 executes calculation for calculating the attenuation amount ΔV in the variable attenuator 21 using the following equation (1), assuming that the two DC levels detected by the DC detection circuit 29 are Vi and Vq.

Further, the arithmetic circuit 31 executes an arithmetic operation for calculating the phase shift amount Δφ in the variable phase shifter 22 using the following equation (2).

Here, Gc and Δφc are the attenuation amount and phase shift amount that occur in the received signal at the power combiner 23. Further, Gl and Δφl are the amount of attenuation and the amount of phase shift that occur in the received signal in the low noise amplifier 24. These attenuation amounts Gc, Gl and phase shift amounts Δφc, Δφl are fixed due to the characteristics of the power combiner 23 and the low noise amplifier 24.
Thus, the amplitude Va of the self-interference signal at the input end of the power combiner 23 is determined by the equation in the curly brackets in equation (1). Furthermore, the phase φa of the self-interference signal at the input end of the power combiner 23 is determined by the equation in the curly brackets in equation (2).

On the other hand, Vc and φc are the amplitude and phase of the transmission signal at the input end of the variable attenuator 21. Therefore, the difference between the amplitude Vc of the transmission signal at the input end of the variable attenuator 21 and the amplitude Va of the self-interference signal at the input end of the power combiner 23 is determined by equation (1). Also, from equation (2), the difference between the phase φc of the transmission signal at the input end of the variable attenuator 21 and the opposite phase of the phase φa of the self-interference signal at the input end of the power combiner 23 is determined.

Note that the transmission signal input to the input end of the variable attenuator 21 is the transmission signal generated by the orthogonal modulator 14, which is supplied via the BPF 15, the power amplifier 16, the LPF 17, and the antenna duplexer 18. . The amount of change in the amplitude and phase of the transmission signal in this process is approximately fixed depending on the characteristics of the BPF 15, power amplifier 16, LPF 17, and antenna duplexer 18. Therefore, there is no problem with the amplitude Vc and the phase φc being constants. The amplitude Vc and the phase φc may be set to appropriate values, for example, by a designer of the reading device 100. The amplitude Vc and the phase φc may be set from the CPU 33 to the arithmetic circuit 31, or may be incorporated into the arithmetic logic of the arithmetic circuit 31.

A period PEA in FIG. 4 is a calculation period by the calculation circuit 31. The CPU 33 waits for the calculation of the attenuation amount ΔV and the phase shift amount Δφ by the arithmetic circuit 31 to be completed, and then proceeds to ACT3 in FIG. 3.
In ACT3, the CPU 33 instructs the control circuit 32 to change the settings. In response to this instruction, the control circuit 32 sets the attenuation amount of the variable attenuator 21 to the attenuation amount ΔV calculated by the calculation circuit 31. Further, the control circuit 32 sets the phase shift amount of the variable phase shifter 22 to the phase shift amount Δφ calculated by the arithmetic circuit 31.

In FIG. 4, at time TIB after the end of period PEA, the attenuation amount of variable attenuator 21 and the phase shift amount of variable phase shifter 22 are changed to ΔV-2 and Δφ-2. The CPU 33 waits for the control circuit 32 to complete the change setting of the amount of attenuation and the amount of phase shift, and then proceeds to ACT4 in FIG. 3.
In ACT4, the CPU 33 starts normal communication. Transmission power during normal communication is sufficiently larger than transmission power during low-power transmission. Therefore, by shifting to normal communication, the transmission power increases as shown in FIG. 4. Note that the transmission power value TPA is, for example, about 1/10 of the power value TPB.
In this way, the period during which low power transmission is performed corresponds to the setting period for setting the attenuation amount ΔV and the phase shift amount Δφ.

In ACT5 in FIG. 3, the CPU 33 confirms whether resetting is necessary. For example, if a predetermined condition is not satisfied for either of the two output values of the AD converter 30, that is, the two DC levels detected by the DC detection circuit 29, the CPU 33 determines that resetting is not necessary and returns NO. Make a judgment and repeat ACT5. In other words, in ACT5, the CPU 33 waits until resetting becomes necessary. Note that if the CPU 33 determines NO in ACT5, it may wait for a predetermined standby time to elapse and then execute ACT5 again. Then, if a predetermined condition is satisfied for either one of the DC levels, the CPU 33 determines YES that resetting is necessary, returns to ACT2, and repeats the subsequent steps in the same manner as described above.

Now, even during normal communication, the DC components included in the two systems of received baseband signals output from the quadrature detector 25 cannot be canceled out by the power combiner 23, resulting in self-interference signals output from the power combiner 23. It originates from Therefore, the amplitude and phase of the self-interference signal change, and the greater the deviation of the attenuation amount of the variable attenuator 21 and the phase shift amount of the variable phase shifter 22 from the appropriate attenuation amount and phase shift amount, the more the direct current The DC level detected by the detection circuit 29 increases. The above conditions should be set so that YES is determined in ACT5 when the self-interference signal becomes larger than an allowable range. For example, the above conditions include "the DC level is above the threshold", "the DC level is greater than the threshold", "the threshold is below the DC level", or "the threshold is less than the DC level". Set arbitrarily. For example, the threshold value is appropriately set, for example, by a designer of the reading device 100, taking into consideration an allowable SNR (signal to noise ratio).

In FIG. 4, in response to an increase in either of the two DC levels at time TIC, the transmission power is reduced by shifting to low power transmission. Then, at time TID, the attenuation amount of the variable attenuator 21 and the phase shift amount of the variable phase shifter 22 are changed and set to ΔV-3 and Δφ-3 according to the result of the calculation in the calculation circuit 31 during the period PEB. . After that, the communication shifts to normal communication again and the transmission power is increased.
In this way, the CPU 33 starts the setting period when the two DC levels detected by the DC detection circuit 29 as the first detection unit match the predetermined conditions as described above, and performs the setting control. function as a department.

As described above, when using the orthogonal modulation method, the reading device 100 utilizes the fact that the DC levels Vi, Vq at the output of the orthogonal detector have a certain relationship with the self-interference signal input to the power combiner 23. Then, based on the DC levels Vi, Vq and the amplitude Vc and phase φc of the transmission signal at the input end of the variable attenuator 21, the amount of attenuation and the amount of phase shift are calculated by calculation. The time required for this calculation is significantly shorter than when searching for an appropriate attenuation amount and phase shift amount while sweeping the attenuation amount and phase shift amount of the variable attenuator 21 and the variable phase shifter 22. Therefore, according to the reading device 100, it is possible to reduce the time required for setting for generating a cancel signal.

Further, the reading device 100 reduces the transmission power during the period in which the DC levels Vi and Vq are detected for the above calculation. This prevents the output of the quadrature detector 25 from becoming saturated, and allows the DC levels Vi, Vq to be detected correctly.

Further, the reading device 100 monitors the DC levels Vi and Vq during normal communication, and when the DC levels Vi and Vq satisfy predetermined conditions, changes the attenuation amount and shift of the variable attenuator 21 and the variable phase shifter 22. Execute the process to set the phase amount again. As a result, when the attenuation amount and phase shift amount of the variable attenuator 21 and the variable phase shifter 22 become inappropriate due to changes in the level and phase shift of the self-interference signal, these attenuation amounts and phase shift amounts can be changed to appropriate values. The value can be quickly reset. Accordingly, the reading device 100 can maintain a state in which reading can be performed with a small SNR.

[Second embodiment]
FIG. 5 is a block diagram showing the main circuit configuration of a reading device 300 according to the second embodiment.
In FIG. 5, the same elements as those shown in FIG. 1 are given the same reference numerals. In the following, the differences between the reading device 300 and the reading device 100 will be mainly explained, and descriptions of the same configurations and operations will be omitted.

The reading device 300 includes an oscillator 11, a phase shifter 12, a DA converter 13, a quadrature modulator 14, a BPF 15, a power amplifier 16, an LPF 17, an antenna duplexer 18, a feed line 19, an antenna 20, a variable attenuator 21, and a variable shifter. Phase box 22, power combiner 23, low noise amplifier 24, quadrature detector 25, BPF 26, baseband amplifier 27, AD converter 28, DC detection circuit 29, AD converter 30, control circuit 32, CPU 33, memory 34, In other words, the reading device 300 including the quadrature detector 41, the DC detection circuit 42, the AD converter 43, and the calculation circuit 44 includes the calculation circuit 44 in place of the calculation circuit 31 among the elements included in the reading device 100, and further In addition, a quadrature detector 41, a DC detection circuit 42, and an AD converter 43 are provided. Note that in FIG. 5, illustration of the DA converter 13, quadrature modulator 14, BPF 15, power amplifier 16, LPF 17, BPF 26, baseband amplifier 27, AD converter 28, CPU 33, and memory 34 is omitted.

The quadrature detector 41 orthogonally detects the transmission signal output from the output terminal TOB of the antenna duplexer 18 using two carrier waves output from the oscillator 11 and the phase shifter 12, respectively. The quadrature detector 41 outputs analog baseband signals of two systems, an I system and a Q system, obtained by quadrature detection in parallel. The two analog baseband signals correspond to a second I signal and a second Q signal. Therefore, the quadrature detector 41 is an example of a first detection section.
The DC detection circuit 42 detects DC signals included in each of the two baseband signals output from the quadrature detector 41. The DC detection circuit 42 is an example of a second detection section.

The AD converter 43 digitizes the two systems of DC signals detected by the DC detection circuit 42, respectively.
The arithmetic circuit 44 determines the amount of attenuation in the variable attenuator 21 and the amount of attenuation in the variable phase shifter 22 based on the DC signal digitized by the AD converter 30 and the DC signal digitized by the AD converter 43. The amount of phase shift is calculated. The calculation circuit 44 is, for example, a hardware circuit that executes calculations based on predetermined mathematical formulas.

By orthogonally detecting the transmission signal output from the output terminal TOB of the antenna duplexer 18 using the quadrature detector 41, two systems of DC signals are obtained in which the amplitude Vc and phase φc of the transmission signal are reflected. Therefore, the levels Vci and Vcq of these two systems of DC signals are detected by the DC detection circuit 42, digitized by the AD converter 43, and used for calculations by the calculation circuit 44.
The arithmetic circuit 44 executes an arithmetic operation to calculate the attenuation amount ΔV in the variable attenuator 21 using the following equation (3).

Equation (3) is an equation modified so that the amplitude Vc in Equation (1) is calculated as the square root of the sum of the square of the level Vci and the square of the level Vcq.
Further, the arithmetic circuit 44 executes an arithmetic operation to calculate the phase shift amount Δφ in the variable phase shifter 22 using the following equation (4).

Equation (4) is an equation modified so that the phase φc in Equation (2) is calculated as the phase formed by the composite vector of level Vci and level Vcq.
That is, in the reading device 300, the amplitude Vc and phase φc of the transmission signal at the input end of the variable attenuator 21 are not determined in advance as in the reading device 100, but are determined by calculation. The other operations of the reading device 300 may be the same as those of the reading device 100.
The reading device 300 also provides the same effects as the reading device 100.

This embodiment can be modified in various ways as follows.
If saturation of the output of the orthogonal detector 25 does not pose a problem even with the transmission power during normal communication, low-power transmission may not be performed.

The attenuation amount ΔV and the phase shift amount Δφ may be reset at predetermined timings such as timings when communication with the RFID tag 200 is not performed.

The attenuation amount ΔV and the phase shift amount Δφ may be calculated by software processing.

Power reduction during low power transmission may be achieved in any other manner. For example, during low power transmission, the amplitude of the output of the oscillator 11 may be reduced, or the gain of the power amplifier 16 may be reduced. Alternatively, during low power transmission, the level of the transmitted signal may be reduced by an attenuator inserted at an arbitrary location upstream of the input end TI of the antenna duplexer 18.

It is also possible to realize it as a communication device that communicates with the RFID tag 200 in order to write to the RFID tag 200. Further, it is also possible to implement the RFID tag 200 as a communication device for communicating with a different communication device.

The first embodiment includes a DC detection circuit 29, an AD converter 30, and an arithmetic circuit 31, and the second embodiment includes a DC detection circuit 29, an AD converter 30, a quadrature detector 41, and a DC detection circuit. The present invention may be configured as an independent cancellation control device including the circuit 42, the AD converter 43, and the arithmetic circuit 44, and may be applied to a communication device that uses another method for setting the attenuation amount ΔV and the phase shift amount Δφ. Note that the cancellation control device may also include a control circuit 32.

Although several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

11... Oscillator, 12... Phase shifter, 13... DA converter, 14... Orthogonal modulator, 15... BPF, 16... Power amplifier, 17... LPF, 18... Antenna duplexer, 19... Feed line, 20... Antenna, 21... Variable attenuator, 22... Variable phase shifter, 23... Power combiner, 24... Low noise amplifier, 25... Quadrature detector, 26... BPF, 27... Baseband amplifier, 28... AD converter, 29... DC Detection circuit, 30... AD converter, 31... Arithmetic circuit, 32... Control circuit, 33... CPU, 34... Memory, 41... Quadrature detector, 42... DC detection circuit, 43... AD converter, 44... Arithmetic circuit, 100, 300...reader, 200...RFID tag.

Claims (6)

a first detection unit that detects the DC levels of the first I signal and the first Q signal output by the quadrature detector;
the first detection of an attenuation amount and a phase shift amount for generating a cancellation signal from the transmission signal for canceling a component of the transmission signal included in the first orthogonal modulation signal input to the quadrature detector; a determining unit that determines by calculation based on the two DC levels detected by the unit and the amplitude and phase of the transmission signal;
A cancellation control device equipped with. a first detection unit that orthogonally detects the transmission signal and outputs a second I signal and a second Q signal;
a second detection unit that detects the DC levels of the second I signal and the second Q signal output from the first detection unit, respectively;
further comprising;
The determining unit calculates the amplitude and phase of the transmission signal based on the two DC levels detected by the second detecting unit.
The cancellation control device according to claim 1. a first generation unit that generates a transmission signal for wireless transmission;
a common unit that inputs the transmission signal generated by the first generation unit from an input end and outputs it from an input/output end, and outputs the signal input from the input/output end from an output end;
a second generation unit that generates a cancellation signal by changing the amplitude and phase of the transmission signal generated by the first generation unit;
a combining unit that combines a cancellation signal with the signal output from the output end;
a second detection unit that orthogonally detects the combined output of the combining unit using a carrier wave and outputs a first I signal and a first Q signal;
a first detection unit that detects the DC levels of the first I signal and the first Q signal, respectively;
a determining unit that determines the amount of attenuation and the amount of phase shift by calculation based on the two DC levels detected by the first detecting unit and the amplitude and phase of the transmission signal;
Equipped with
The second generation unit generates the cancellation signal by changing the amplitude and phase of the transmission signal with the attenuation amount and phase shift amount determined by the determination unit.
Communication device. a first detection unit that orthogonally detects the transmission signal and outputs a second I signal and a second Q signal;
a second detection unit that detects the DC levels of the second I signal and the second Q signal output from the first detection unit, respectively;
further comprising;
The determining unit calculates the amplitude and phase of the transmission signal based on the two DC levels detected by the second detecting unit.
The communication device according to claim 3. a modulation unit that orthogonally modulates the carrier wave with a third I signal and a third Q signal;
an input section that inputs the third I signal and the third Q signal, which are predetermined so as to set the power level of the transmission signal to a predetermined suppression level, to the modulation section during a setting period;
Furthermore,
The determining unit determines the attenuation amount and the phase shift amount during the setting period,
The communication device according to claim 3 or 4. a setting control unit that starts the setting period when the two DC levels detected by the first detection unit meet a predetermined condition;
The communication device according to claim 5, further comprising:.