JP7428508B2 - information processing equipment - Google Patents

Description

The present invention relates to an information processing device.

In recent years, in the development of embedded systems that support industrial electronic control units (ECUs), applications such as improving control performance, responding to increasingly strict regulations, and increasing control calculation processing as equipment becomes autonomous have been increasing. The load on computers is increasing. In response to this, the performance of ECU hardware such as multi-core and many-core is progressing.

On the other hand, when looking at the development of software installed on these high-performance hardware, software development that supports the aforementioned multi-core and many-core technology is required, increasing the complexity of design, development, and verification. . The reason for this is that in the development of multi-core processors, multiple cores access shared resources such as the bus, memory, and cache, so unlike single-core processor development, software behavior can easily change depending on the processor state at runtime. This can be mentioned.

Furthermore, even after solving these issues and completing commercialization, the parameters related to shared resources (bus width, memory size, cache size) differ depending on the processor, so the development results from one processor cannot be directly transferred to another processor. It is also not simple to port the software, which similarly increases the number of man-hours for design, development, and verification.

As a measure to deal with the increasing complexity of processor configurations and the associated increase in development man-hours, AUTOSAR (AUTomotive Open System ARchitecture), a standard for in-vehicle software architecture, introduced a time-synchronized timing design method in 2018 for timing design. A new LET (Logical Execution Time) paradigm has been added.

This method is characterized in that timing is designed in the upstream process, and the middleware protects the designed timing during execution. This prevents the increase in development and verification patterns due to combinations of processor states, contributing to a reduction in man-hours. be able to.

Furthermore, when porting between different processors, if the timing design results for one processor can also meet performance requirements for another processor, they can be ported as is.

Patent Document 1 provides a design method that is expected to exhibit the same behavior as when performing such a design method. In the scheduling method disclosed in Patent Document 1, a plurality of chained processing elements are grouped into a first processing element group and a second processing element group. The first processing element group is periodically executed by, for example, a first processor, and the second processing element group is periodically executed by, for example, a second processor at a timing one cycle later than that of the first processing element group.

Japanese Patent Application Publication No. 2005-43959

On the other hand, in this method, even if there is a delay due to fluctuations in processing time with respect to the timing design result that has been determined once, the behavior according to the predetermined timing design is taken. That is, for example, even if there is a delay in the completion of the preceding process in two consecutive processes (preceding process/succeeding process), execution of the subsequent process is started without waiting for the completion of the preceding process.

In such a situation, the subsequent process refers to the memory area that stores the calculation results of the preceding process and starts processing, so if the preceding process is incomplete, the subsequent process will be started based on the previous process completion result. Ru. When adopting such a processing system, there is a risk that the previous input result will be used, especially when connecting to devices such as sensors and external terminals such as other ECUs, which are at risk of delays due to changes in communication load conditions. This leads to a decrease in responsiveness to external input.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an information processing device based on a time-synchronized timing design method that can improve responsiveness.

In order to solve the above problems, an information processing device according to one aspect of the present invention has a plurality of processing units that share storage resources, and processes in each processing unit are periodically executed at predetermined time intervals, and a specific When the first process in a processing unit uses the result of the second process in another process unit that precedes this process, the timing at which the result of the second process in the other process unit is written to the storage resource is If the process does not end within the time interval, the start time of the first process in a specific process unit is delayed until the time when the result of the second process in another process unit is written to the storage resource, and the result of the second process is specified. It is used for the first processing in the processing section.

According to the present invention, it is possible to realize an information processing device based on a time-synchronized timing design method that can improve responsiveness.

1 is a diagram showing the configuration of an information processing device according to a first embodiment. FIG. 7 is a diagram illustrating an example of the operation of each process based on time-synchronized timing design. FIG. 7 is a diagram illustrating an operation when the end of advance processing is delayed in time-synchronized timing design. FIG. 3 is a diagram illustrating the operation of each process based on a time-synchronized timing design in the first embodiment. 3 is a flowchart for explaining the operation of the information processing apparatus according to the first embodiment. 3 is a diagram illustrating a processing configuration of an assumed application in Example 2. FIG. 7 is a diagram illustrating an example of the operation of each process based on a time-synchronized timing design in the second embodiment. FIG. FIG. 7 is a diagram illustrating another example of the operation of each process based on the time-synchronized timing design in the second embodiment. 7 is a diagram illustrating still another example of the operation of each process based on the time-synchronized timing design in the second embodiment. FIG.

Embodiments of the present invention will be described below with reference to the drawings. The embodiments described below do not limit the claimed invention, and all of the elements and combinations thereof described in the embodiments are not necessarily essential to the solution of the invention. Not exclusively.

In the drawings explaining the embodiments, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.

Further, in the following description, an expression such as "xxx data" may be used as an example of information, but the information may have any data structure. That is, "xxx data" can be referred to as "xxx table" to indicate that the information is independent of data structure. Furthermore, "xxx data" is sometimes simply referred to as "xxx". In the following description, the configuration of each piece of information is merely an example, and the information may be held separately or may be combined and held.

FIG. 1 shows the configuration of a processor (information processing device) and peripheral devices targeted by this embodiment.

The processor 1 is a multi-core processor having multiple CPU cores 2. In such processors, a multi-stage cache configuration is mainly used, which has a level 1 cache (L1 cache) 21 that each CPU core 2 has, and a level 2 cache (L2 cache) 22 that is shared by multiple cores. Efforts have been made to increase the efficiency of instruction execution on the core. Each CPU core 2 is connected to an external memory 4 and a sensor 5 outside the processor 1 through an internal bus 3. Note that for the sake of simplicity, the detailed configuration (various mechanisms and detailed bus structure) inside the multi-core processor 1 will be omitted. In the following description, the L2 cache 22 and the external memory 4 will be referred to as shared memory in the sense that they are storage resources shared by the respective CPU cores 2.

When an application is executed on such a multi-core processor 1, when the CPU cores 2 are actually operated simultaneously to process the application, the multiple CPU cores 2 have access to the L2 cache 22 and external memory 4, which are shared resources. It is affected by changes in processing efficiency due to access contention, the load on the internal bus 3, and changes in the cache hit rate of the L2 cache 22 due to memory usage from multiple processes.

Therefore, in addition to the predefined execution order of each application, the system is configured to respond to changes in the state of the processor (the status of the L2 cache 22, the load status of the internal bus 3), which dynamically changes depending on the operation of each application. This changes the application processing status, order, and memory access timing.

Furthermore, since there are applications whose operation timings such as interrupt processing are uncertain, application development, debugging, and verification on the processor 1 must be done in consideration of the possible states of the processor 1. There are concerns that each task will become more complex and the number of man-hours will increase.

Also, when porting an application designed and verified on one processor 1 to another multi-core processor, changes in performance such as the operating speed and number of CPU cores, bus operating speed and bus width, and cache size etc. Since application behavior changes due to the influence, it is not easy to port a design intended for a certain processor 1 to other multi-core processors.

As a design method that takes into account the use of the processor 1 and portability to other multi-core processors, a time-synchronized design method is known in which applications are executed in a manner that specifies the processing start and completion timings of each application. .

FIG. 2 shows a configuration for executing application processing using a time-synchronized design concept.

In the following explanation, for the sake of simplicity, it is assumed that the application process consists of two consecutive processes (preceding process and subsequent process), each of which operates at a predetermined cycle (in this example, the same cycle). Further, the preceding processing reads data in area A from the shared memory, receives input from sensor 5, performs processing corresponding to the memory state, and stores the processing result in area B. In subsequent processing, data in area B is read and stored in area C (not shown), and the subscripts added to A and B are the labels given to A and B. Let us show the values stored in each area above. Further, this subscript indicates the correspondence between input and output, such that, for example, the value of B ₀ is output based on the input of A ₀ .

The two processes, pre-processing and subsequent processing, read the values necessary for the calculation from the shared memory at the beginning (for example, T0, T1) of a determined cycle (for example, T0-T1, T1-T2) (in and in the figure). (described part), the calculation result is written to the shared memory at the end of the cycle (out in the figure). Arithmetic processing is executed at any timing between reading and writing, and operates according to a model that clearly defines when application processing starts (data reading) and when processing ends (data writing).

By adopting such a processing configuration, although it is difficult to verify the timing at which arithmetic processing is actually performed and the processor state at that time, it is possible to , it is possible to confirm the completion of processing. At the same time, by limiting the interface with other processes to data exchange through shared memory, there is no need to be aware of changes in the data used between each process in a complex processor state, improving ease of verification. Based on this design concept, by specifying only the start and completion of processing at predetermined timings, even when an application is ported to another processor, the processing is sufficient for the destination processor to execute the same processing. Similar operation is expected as long as the performance is maintained. This improves application portability.

In the example shown in FIG. 2, the preceding process reads the data of _A0 at time T0, completes the calculation during the cycle starting from T0 (that is, until T1), and outputs _B0 . The output B ₀ is read by the subsequent process in a cycle starting at time T1, and the subsequent process is performed, and C ₀ is output when the calculation of the subsequent process is completed during the cycle starting from T1 (up to T2).

On the other hand, in such a configuration, a case is assumed in which the calculation time of the preceding process increases more than expected due to a delay in the input from the sensor 5 due to communication conditions or an increase in the load on the internal bus 3 due to other processes.

In the case shown in FIG. 3, the processing is not completed during the cycle starting from time T0 (up to T1) due to the delay in the end of the preceding processing. In such a case, the result stored in area B , which is the result of the processing performed by the preceding process upon receiving input A ₀ , will not be written in time to write back the processing result to the shared memory, so the result will not be written to the shared memory. Not done. On the other hand, subsequent processing starts by reading data B _-1 in area B on the shared memory in a cycle starting from time T1. Therefore, the subsequent processing is performed again using B _-1 as input. As a result, in the overall operation of the application that receives A ₀ and outputs C ₀ , processing based on B ₀ is carried over to subsequent cycles, resulting in poor processing responsiveness to input.

FIG. 4 shows the configuration of this embodiment corresponding to the above. In this embodiment, for the situation shown in FIG. 3, the start time of the subsequent process is delayed by using the designed grace time given to the subsequent process. This increases the time frame for waiting for input, makes it possible to set the input of subsequent processing in the cycle starting from time T1 to the latest value _B0 , and output the calculation result _C0 .

In order to realize such processing, it is necessary to add a data sharing method between the preceding process and the subsequent process and a function for starting the subsequent process to the OS or middleware. An example of a method for sharing data between the preceding processing and the subsequent processing is a method using double buffering.

As a result, while suppressing the increase in design, development, and verification man-hours and improving portability, which are the advantages of the time-synchronized timing design method, it is possible to reduce It also becomes possible to improve responsiveness or processing completion performance. However, if the preceding processing is not completed even after the grace period for the subsequent processing is exceeded, responsiveness deteriorates as in the conventional method.

FIG. 5 is a flowchart for explaining the operation of the information processing apparatus according to the first embodiment.

First, the processor 1 reads necessary data into the local memory of the preceding process (step S500). Next, processor 1 executes advance processing (step S501).

Next, the processor 1 determines whether the end of the preceding processing and the writing of data to the shared memory are completed by the deadline (the end of the calculation processing cycle) (step S502). If the determination is affirmative (YES in step S502), the process moves to step S503, and if the determination is negative (NO in step S502), the process moves to step S506.

In step S503, the processor 1 reads the processing results of the preceding process into the local memory of the subsequent process. Next, processor 1 executes subsequent processing (step S504). The processor 1 then writes the results of the subsequent processing to the shared memory (step S505).

On the other hand, in step S506, processor 1 delays the start of subsequent processing. Next, the processor 1 determines whether the completion delay time of the preceding process is within the grace period of the subsequent process (step S507). If the determination is affirmative (YES in step S507), the process moves to step S508, and if the determination is negative (NO in step S507), the process moves to step S511.

In steps S508 to S510, processing similar to steps S503 to S505 is performed. On the other hand, in step S511, the previous processing result of the preceding processing is read into the local memory of the subsequent processing. Thereafter, in steps S512 and S513, processing similar to steps S504 and S505 is performed.

In this embodiment, the result of the preceding process in the cycle starting from time T0 is not written to the shared memory at time T1, and the preceding process is not started in the next cycle starting from time T1. A configuration is assumed in which the value _B0 , which is the processing result, is written back to the shared memory at the end of the cycle at time T1.

In addition to this, depending on the processing configuration, a configuration may be adopted in which the processing of the time T0 period is forcibly terminated at time T1, the value _A0 on the shared memory is read, and the next processing is started. In this case, it is conceivable that a process using _B0 as an input will not be performed in the subsequent process. In such a case, the application processing will not be executed as expected, which will have a different effect on subsequent processing, resulting in a problem different from the above-mentioned deterioration of responsiveness.

Embodiment 2 In Embodiment 2, a configuration of a sensor processing application and a process application method will be described as an example of applying the processing configuration shown in Embodiment 1 to a control device that performs automatic driving processing.

The configuration of the application is shown in Figure 6. In this application, a series of process groups (B, C) and D perform two different recognition processes on the sensor data captured by process A, which stores the result of receiving sensor data from an external sensor in memory. , processing E which integrates two recognition processing results and outputs them to other application processing, and is executed using two CPU cores 2.

The execution core allocation and timing of each process included in the application are designed as shown in FIG. 7, and the timing design is similar to that of the first embodiment.

In this example, five processes with different start and completion times are arranged within one application cycle. For example, process A starts at time T0 and performs a copy-in, and at time T1 it performs a copy-in. Processing is performed between both times so that -out completes. In addition, the results of consecutive processes B and C and the results of process D are integrated in process E, and processes B, C, and D are started/finished in time for the start time of process E. A time is set.

Process A is a process of storing sensor data reception results in memory, and although a grace period is given in the design, data arrival may be delayed depending on the communication status between the control device and the sensor and the status of other communications. Delays may occur.

FIG. 8 shows a case where the end of process A is delayed due to a delay in sensor data arrival. In this case, similarly to the configuration of Example 1, by using the grace time of processing B and processing D to delay the start time of processing B and processing D, the latest result of processing A, that is, the latest sensor data Attempts to continue processing based on .

On the other hand, the latest start timings of processing B and processing D are different due to differences in execution time and processing completion time between processing B and processing D. Note that the latest start timing is the maximum timing that allows for a start delay in the processing configuration, taking into consideration the margin defined by design and execution time variations.

In such a case, since the same sensor input from process A is input to the same process E through two control paths, that is, the process B and process C path, and the process D path, A case may occur where it is undesirable for the input data used by processes B and C to be different from the input data used by process D.

In such a case, although the start delay grace time (time to the latest start timing) of process D with respect to the delay of process A has more margin than that of process B, the delay time of process D, which has less margin, It is constrained to match the start timing, and the latest end timing of process A as shown in FIG. 9 is defined. In this way, the grace period during which the latest processing results can be used varies depending on the processing configuration of the application.

Note that if Process A is not completed even after the latest end timing of Process A is exceeded, Process B and Process D are started using the previous processing result of Process A (that is, the sensor data reception result in the previous cycle). be done.

Although the invention made by the present inventor has been specifically explained based on the embodiments above, the present invention is not limited to the embodiments described above, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

For example, in the second embodiment, a case may be assumed in which a delay in the end of process B occurs in a chain reaction due to a delay in the end of process A. In such a case, a plurality of implementation methods can be envisaged, such as a case in which the start time of process C is also delayed, and a case in which the end time of process B is fixed.

Further, each of the above-mentioned configurations, functions, processing units, processing means, etc. may be partially or entirely realized in hardware by designing, for example, an integrated circuit. Further, the present invention can also be realized by software program codes that realize the functions of the embodiments. In this case, a storage medium on which a program code is recorded is provided to a computer, and a processor included in the computer reads the program code stored on the storage medium. In this case, the program code itself read from the storage medium realizes the functions of the embodiments described above, and the program code itself and the storage medium storing it constitute the present invention. Examples of storage media for supplying such program codes include flexible disks, CD-ROMs, DVD-ROMs, hard disks, SSDs (Solid State Drives), optical disks, magneto-optical disks, CD-Rs, magnetic tapes, A non-volatile memory card, ROM, etc. are used.

Further, the program code for realizing the functions described in this embodiment can be implemented in a wide range of program or script languages such as assembler, C/C++, Perl, Shell, PHP, and Java (registered trademark).

Furthermore, by distributing the software program code that realizes the functions of the embodiment via a network, it can be stored in a storage means such as a computer's hard disk or memory, or a storage medium such as a CD-RW or CD-R. Alternatively, a processor included in the computer may read and execute the program code stored in the storage means or the storage medium.

In the above-described embodiments, the control lines and information lines are those considered necessary for explanation, and not all control lines and information lines are necessarily shown in the product. All configurations may be interconnected.

1: Multi-core processor, 2: CPU core, 21: L1 cache, 22: L2 cache, 3: Internal bus, 4: External memory, 5: Sensor

Claims (9)

An information processing device that includes a plurality of processing units that share storage resources, and in which processing in each processing unit is periodically executed at predetermined time intervals,
When the first processing in a specific processing unit uses the result of the second processing in another processing unit that precedes this processing, the result of the second processing in the other processing unit is When the timing of writing to the storage resource does not end within the time interval, the start time of the first process in the specific processing unit is set to the start time of the other process within the process cycle in which the first process is executed. The information processing apparatus is characterized in that the result of the second processing in the section is delayed until a timing when the result of the second processing is written into the storage resource, and the result of the second processing is used for the first processing in the specific processing section. . The first process and the second process are configured to read a value to be processed from the storage resource at the start of a processing period, and write the result of the process to the storage resource at the end of the processing cycle. The information processing device according to claim 1, characterized in that: 2. The information processing apparatus according to claim 1, wherein the timing at which the start time of the first process is delayed is within a range that does not exceed a predetermined grace period for the first process. The specific processing section reads the result of the second processing from an area where the result of the second processing in the other processing section is stored in the storage resource, and executes the first processing. The information processing device according to claim 1. If the result of the second process is written to a specific area of the storage resource while the start time of the first process is delayed, the specific processing unit writes the result of the second process to the second process. If the result of the second process is not written to the storage resource even if the start time of the first process is delayed until the grace period, the specific process unit is used for the previous cycle. 4. The information processing apparatus according to claim 3 , wherein a result of the second processing is used for the first processing. The storage resource has a plurality of areas,
If the result of the second process is written to a specific area of the storage resource while delaying the start time of the first process, the specific processing unit writes the second process stored in the specific area. Even if the result of the second process is read and the result of the second process is used for the first process, and the start time of the first process is delayed until the grace period, the result of the second process is When the result of the second process is not written to the storage resource, the specific processing unit writes the result of the second process written to the area different from the specific area to which the result of the second process in the previous cycle was written. 6. The information processing apparatus according to claim 5 , wherein the information processing apparatus reads out and uses the read data for the first processing. There is a plurality of the first processes,
2. The timing of delaying the start time of each of the plurality of first processes is within a range that does not exceed a predetermined grace time for each of the plurality of first processes. information processing equipment. There are at least two of the first processes,
Among the at least two first processes, the latest start timing of the first process that has more margin in terms of the latest start timing is set to the latest start timing of the first process that has more margin in terms of the latest start timing. The information processing apparatus according to claim 1, wherein the information processing apparatus is constrained by matching timing. The information processing apparatus according to claim 1 , wherein the processing start timing of the first processing is indefinite within the time interval.

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