JP7423706B2 - micro light emitting diode display device - Google Patents

micro light emitting diode display device Download PDF

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JP7423706B2
JP7423706B2 JP2022119618A JP2022119618A JP7423706B2 JP 7423706 B2 JP7423706 B2 JP 7423706B2 JP 2022119618 A JP2022119618 A JP 2022119618A JP 2022119618 A JP2022119618 A JP 2022119618A JP 7423706 B2 JP7423706 B2 JP 7423706B2
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light emitting
conductive layer
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emitting diode
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JP2023029246A (en
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彦▲イエ▼ 陳
于▲ユエイ▼ 曾
志凌 呉
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▲ナイ▼創▲顕▼示科技股▲ふん▼有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

本開示は、表示装置に関するものであり、特に、マイクロ発光ダイオード表示装置に関するものである。 TECHNICAL FIELD This disclosure relates to display devices, and more particularly to micro light emitting diode displays.

マイクロ発光ダイオード表示装置の複数のピクセルは、半導体接続層上に複数の半導体発光メサを配置することによって形成することができる。半導体発光メサの各々はサブピクセルに対応し、半導体接続層上にアレイ状に配置される。半導体接続層は、接続層であることに加えて、各発光メサの共通電極としても機能することができ、接合金属層を介して回路基板に電気的に接続される。 Pixels of a micro-light-emitting diode display can be formed by placing semiconductor light-emitting mesas on a semiconductor connection layer. Each of the semiconductor light emitting mesas corresponds to a subpixel and is arranged in an array on the semiconductor connection layer. In addition to being a connection layer, the semiconductor connection layer can also function as a common electrode for each light emitting mesa, and is electrically connected to the circuit board via the bonding metal layer.

しかしながら、半導体接続層の抵抗値は、導体の抵抗値よりも高い。共通接地点から遠く離れた発光メサの方が再結合する電子正孔対の数が少なくなる。これに対し、共通接地点に近い発光メサの方が再結合する電子正孔対の数が多くなる。そのため、マイクロ発光ダイオードディスプレイの輝度が不均一になり得る。 However, the resistance value of the semiconductor connection layer is higher than the resistance value of the conductor. Emitting mesas farther away from a common ground point have fewer electron-hole pairs recombining. On the other hand, the number of electron-hole pairs that recombine increases in the light-emitting mesa that is closer to the common ground point. Therefore, the brightness of the micro-light emitting diode display may be non-uniform.

本開示は、均一な発光輝度を有するマイクロ発光ダイオード表示装置を提供する。 The present disclosure provides a micro light emitting diode display device with uniform emission brightness.

本開示の一実施形態によれば、回路基板、エピタキシー構造、および導電層を含むマイクロ発光ダイオード表示装置が提供される。エピタキシー構造は、回路基板に電気的に接続されており、接続層と複数の発光メサとを含む。発光メサは接続層上に配置され、接続層の厚さは発光メサの厚さよりも薄く、接続層は発光メサによって露出された第1の表面と、第1の表面の反対側の第2の表面を有する。導電層は接続層の第2の表面上に配置され、第2の表面の複数のサブ領域を露出し、接続層への導電層の垂直投影が接続層への第1の表面の垂直投影と重なり合う。 According to one embodiment of the present disclosure, a micro light emitting diode display is provided that includes a circuit board, an epitaxial structure, and a conductive layer. The epitaxy structure is electrically connected to the circuit board and includes a connection layer and a plurality of light emitting mesas. The light-emitting mesa is disposed on the connection layer, the thickness of the connection layer being less than the thickness of the light-emission mesa, and the connection layer having a first surface exposed by the light-emission mesa and a second surface opposite the first surface. Has a surface. A conductive layer is disposed on the second surface of the connection layer, exposing a plurality of sub-regions of the second surface, and a vertical projection of the conductive layer onto the connection layer is a vertical projection of the first surface onto the connection layer. overlap.

本開示の別の実施形態によれば、回路基板、エピタキシー構造、および透明導電層を含むマイクロ発光ダイオード表示装置が提供される。エピタキシー構造は、回路基板に電気的に接続されており、接続層と複数の発光メサとを含む。発光メサは、接続層上に配置され、接続層は、発光メサによって露出された第1の表面と、第1の表面の反対側の第2の表面とを有する。透明導電層は、接続層の第2の表面上に配置され、透明導電層は、第2の表面を完全に覆う。 According to another embodiment of the present disclosure, a micro light emitting diode display is provided that includes a circuit board, an epitaxial structure, and a transparent conductive layer. The epitaxy structure is electrically connected to the circuit board and includes a connection layer and a plurality of light emitting mesas. A light emitting mesa is disposed on the connection layer, the connection layer having a first surface exposed by the light emitting mesa and a second surface opposite the first surface. A transparent conductive layer is disposed on the second surface of the connection layer, and the transparent conductive layer completely covers the second surface.

上記に基づいて、本開示の実施形態によって提供されるマイクロ発光ダイオード表示装置では、導電層がエピタキシー構造の接続層上に配置されている。導電層の抵抗値は接続層の抵抗値よりも小さいので、回路基板の電流は導電層を通ってより均一に伝達され得る。この場合、共通の接地点からの距離が異なる発光メサにおいて、同じ電位差が同じ数の再結合電子正孔対を駆動することが可能になり、これにより、マイクロ発光ダイオード表示装置の輝度が不均一になるのを防ぐことができる。さらに、解像度の要件が高くなるにつれて、発光メサ(サブピクセル)の配置が密になる。導電層が接続層の第1の表面に配置される従来の状況とは対照的に、本開示の導電層は第2の表面に配置され、これは歩留まりを大幅に改善する。 Based on the above, in the micro light emitting diode display provided by the embodiments of the present disclosure, a conductive layer is disposed on the connection layer of the epitaxial structure. Since the resistance value of the conductive layer is smaller than the resistance value of the connection layer, the current of the circuit board can be transmitted more uniformly through the conductive layer. In this case, the same potential difference can drive the same number of recombining electron-hole pairs in the light-emitting mesas at different distances from a common ground point, which leads to non-uniform brightness in the micro-light emitting diode display. can be prevented from becoming. Furthermore, as resolution requirements increase, the arrangement of light-emitting mesas (sub-pixels) becomes denser. In contrast to the conventional situation where the conductive layer is disposed on the first surface of the connection layer, the conductive layer of the present disclosure is disposed on the second surface, which significantly improves yield.

本開示の上記の特徴および利点を理解可能にするために、図面を参照して幾つかの実施形態を以下に詳細に説明する。 In order to make the above features and advantages of the present disclosure understandable, some embodiments will be described in detail below with reference to the drawings.

本開示の一実施形態によるマイクロ発光ダイオード表示装置の平面概略図を示す。1 shows a top schematic view of a micro light emitting diode display according to an embodiment of the present disclosure; FIG. 図1Aに示される線I-I'に沿った断面概略図を示す。1A shows a cross-sectional schematic view along line II' shown in FIG. 1A; FIG. 本開示の一実施形態によるマイクロ発光ダイオード表示装置の平面概略図を示す。1 shows a top schematic view of a micro light emitting diode display according to an embodiment of the present disclosure; FIG. 図2Aに示される線II-II'に沿った断面概略図を示す。2A shows a cross-sectional schematic view along the line II-II' shown in FIG. 2A; FIG. 本開示の実施形態によるマイクロ発光ダイオード表示装置の断面概略図である。1 is a cross-sectional schematic diagram of a micro light emitting diode display according to an embodiment of the present disclosure; FIG. 本開示の実施形態によるマイクロ発光ダイオード表示装置の断面概略図である。1 is a cross-sectional schematic diagram of a micro light emitting diode display according to an embodiment of the present disclosure; FIG. 本開示の実施形態によるマイクロ発光ダイオード表示装置の断面概略図である。1 is a cross-sectional schematic diagram of a micro light emitting diode display according to an embodiment of the present disclosure; FIG.

発明を実施すための形態Mode for carrying out the invention

図1Aおよび図1Bを参照すると、マイクロ発光ダイオード表示装置1は、表示領域A1および非表示領域A2を有するとともに、回路基板C1、エピタキシー構造ES、および導電層30を含む。表示領域A1は、複数の表示サブピクセルPXが配置された領域を指し、非表示領域A2は表示領域A1の周囲に少なくとも部分的に配置され、複数の駆動要素(図示せず)が配置される領域とし得る。表示サブピクセルPXの各々は、マイクロ発光ダイオード表示装置1の画像光を提供する発光メサ20を有する。 Referring to FIGS. 1A and 1B, the micro light emitting diode display device 1 has a display area A1 and a non-display area A2, and includes a circuit board C1, an epitaxial structure ES, and a conductive layer 30. The display area A1 refers to an area where a plurality of display sub-pixels PX are arranged, and the non-display area A2 is arranged at least partially around the display area A1, and a plurality of driving elements (not shown) are arranged. It can be an area. Each of the display sub-pixels PX has a light emitting mesa 20 which provides the image light of the micro light emitting diode display 1.

エピタキシー構造ESは、接続層10および複数の発光メサ20を含む。図1Bに示されるように、複数の表示サブピクセルPXにそれぞれ対応する複数の発光メサ20は、接続層10上に配置され、発光メサ20の各々は、第1の型の半導体層201、第2の型の半導体層202、および発光層203を含み、発光層203は、多重量子井戸(MQW)である。接続層10は、第1の方向D1と第2の方向D2により形成される平面に平行な平面上に配置され、発光メサ20により露光される第1の表面101と、第1の表面101の反対側の第2の表面102とを有する。 The epitaxial structure ES includes a connection layer 10 and a plurality of light emitting mesas 20. As shown in FIG. 1B, a plurality of light emitting mesas 20 respectively corresponding to a plurality of display sub-pixels PX are disposed on the connection layer 10, and each of the light emitting mesas 20 includes a first type semiconductor layer 201, a first type semiconductor layer 201, 2 type semiconductor layer 202 and a light emitting layer 203, the light emitting layer 203 is a multiple quantum well (MQW). The connection layer 10 is arranged on a plane parallel to the plane formed by the first direction D1 and the second direction D2, and connects a first surface 101 exposed by the light emitting mesa 20 and a first surface 101 of the first surface 101. and an opposite second surface 102.

本開示の一実施形態によれば、接続層10はn型の半導体であり、第1の型の半導体層201はn型半導体であり、第2の型の半導体層202はp型半導体であるが、本開示はこれに限定されない。本開示の別の実施形態では、接続層10はp型半導体であり、第1の型の半導体層201はp型半導体であり、第2の型の半導体層202はn型半導体である。特に、接続層10と第1の型の半導体層201は一体に形成してもよい。すなわち、2つは同じ層としてもよい。例えば、エッチングプロセスによって、複数の分離された第1の型の半導体層201と連続接続層10とを形成することにより、回路基板C1への物質移動の歩留まりを向上させることができ、消費電力削減のために接続層10を共通の電極として使用することもできる。 According to an embodiment of the present disclosure, the connection layer 10 is an n-type semiconductor, the first type semiconductor layer 201 is an n-type semiconductor, and the second type semiconductor layer 202 is a p-type semiconductor. However, the present disclosure is not limited thereto. In another embodiment of the present disclosure, the connection layer 10 is a p-type semiconductor, the first type semiconductor layer 201 is a p-type semiconductor, and the second type semiconductor layer 202 is an n-type semiconductor. In particular, the connection layer 10 and the first type semiconductor layer 201 may be formed integrally. That is, the two layers may be the same layer. For example, by forming a plurality of separated first type semiconductor layers 201 and a continuous connection layer 10 by an etching process, the yield of material transfer to the circuit board C1 can be improved, and power consumption can be reduced. The connection layer 10 can also be used as a common electrode for this purpose.

回路基板C1は、例えば、相補型金属酸化膜半導体(CMOS)基板、リキッド・クリスタル・オン・シリコン(LCOS)基板、薄膜トランジスタ(TFT)基板、または動作回路を備えた他の基板とし得るが、これに限定されない。図1Bに示されるように、エピタキシー構造ESは、接合金属層120、接合金属層130、接合金属層140、および接合金属層150を介して回路基板C1に電気的に接続され、接合金属層140および接合金属層150は共通接地点である。回路基板C1を介して接合金属層120に電圧が印加されて接合金属層120と共通接地点との間に電位差が発生すると、電位差により電流が発生し、電圧が印加された接合金属層120を接続する発光メサ20において電子正孔対の再結合が生起し、それによって光が発生する。発光メサ20によって放出された光は、第3の方向D3に実質的に平行な方向に沿ってマイクロ発光ダイオード表示装置1から出て、ユーザの目に入る。ここで、第1の方向D1、第2の方向D2、そして第3の方向D3は互いに垂直である。 The circuit board C1 may be, for example, a complementary metal oxide semiconductor (CMOS) substrate, a liquid crystal on silicon (LCOS) substrate, a thin film transistor (TFT) substrate, or other substrate with operational circuitry. but not limited to. As shown in FIG. 1B, the epitaxial structure ES is electrically connected to the circuit board C1 via the bonding metal layer 120, the bonding metal layer 130, the bonding metal layer 140, and the bonding metal layer 150. and bonding metal layer 150 are a common ground point. When a voltage is applied to the bonding metal layer 120 via the circuit board C1 and a potential difference is generated between the bonding metal layer 120 and the common ground point, a current is generated due to the potential difference, and the bonding metal layer 120 to which the voltage is applied is generated. Recombination of electron-hole pairs occurs in the connected light-emitting mesa 20, thereby generating light. The light emitted by the light emitting mesa 20 exits the micro light emitting diode display 1 along a direction substantially parallel to the third direction D3 and enters the user's eyes. Here, the first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other.

共通電極として機能する接続層10は半導体であるため、接続層10の抵抗値は導体の抵抗値よりも高い。共通接地点と共通接地点から遠く離れた接合金属層120に所定の電位差が印加される場合、対応する発光メサ20での再結合電子正孔対の数は少なくなる。同じ電位差が共通接地点と共通接地点に近い接合金属層120に印加される場合、対応する発光メサ20での再結合電子正孔対の数は多くなる。上記の状況を回避するために、導電層30を接続層10の第2の表面102上に配置するとともに、接続層10の第3の方向D3の厚さを発光メサ20の厚さより薄く構成し、低い抵抗を有する導電層30を利用して電流の伝達を補助することによって、電流が均一に分配されるようにすることができる。共通接地点と共通接地点から遠く離れた接合金属層120に同じ電位差が印加されても、対応する発光メサ20内の再結合電子正孔対の数は低下しない。発光メサ20から放出された光は、接続層10の内部で反射されることが防止される。光損失が回避される。したがって、マイクロ発光ダイオード表示装置1の発光メサ20は、同じ電位差が印加されたときに同じ輝度を有することができ、マイクロ発光ダイオード表示装置1は、良好な輝度均一性を有し得る。 Since the connection layer 10 functioning as a common electrode is a semiconductor, the resistance value of the connection layer 10 is higher than the resistance value of the conductor. When a predetermined potential difference is applied between the common ground point and the bonding metal layer 120 far from the common ground point, the number of recombined electron-hole pairs in the corresponding light emitting mesa 20 will be reduced. If the same potential difference is applied to the common ground point and the bonding metal layer 120 close to the common ground point, the number of recombining electron-hole pairs in the corresponding light emitting mesa 20 will be large. In order to avoid the above situation, the conductive layer 30 is arranged on the second surface 102 of the connection layer 10, and the thickness of the connection layer 10 in the third direction D3 is made thinner than the thickness of the light emitting mesa 20. By utilizing a conductive layer 30 having a low resistance to assist in the transmission of current, the current can be distributed evenly. Even if the same potential difference is applied to the common ground point and the bonding metal layer 120 far from the common ground point, the number of recombined electron-hole pairs in the corresponding light emitting mesa 20 will not decrease. The light emitted from the light emitting mesa 20 is prevented from being reflected inside the connection layer 10. Light loss is avoided. Therefore, the light emitting mesas 20 of the micro light emitting diode display 1 can have the same brightness when the same potential difference is applied, and the micro light emitting diode display 1 can have good brightness uniformity.

導電層30の面積が大きいほど、電流がより均一に分配され、マイクロ発光ダイオード表示装置1の輝度均一性が向上する。接続層10への導電層30の垂直投影が第1の投影であり、接続層10への第1の表面101の垂直投影が第2の投影である場合、一実施形態では、第1の投影と第2の投影が重なり合う部分の面積は、第2の投影の面積の0.5倍以上である。一実施形態では、接続層10への第1の表面101の垂直投影(すなわち、第2の投影)は、接続層10への導電層30の垂直投影(すなわち、第1の投影)内に完全に含まれる。別の実施形態では、接続層10への第1の表面101の垂直投影(すなわち、第2の投影)は、接続層10への導電層30の垂直投影(すなわち、第1の投影)内に完全に含まれ、第1の投影と第2の投影の重なり合う部分の面積は、第2の投影の面積に等しい。 The larger the area of the conductive layer 30, the more uniformly the current is distributed and the brightness uniformity of the micro-light emitting diode display device 1 is improved. In one embodiment, if the vertical projection of the conductive layer 30 onto the connection layer 10 is the first projection and the vertical projection of the first surface 101 onto the connection layer 10 is the second projection, the first projection The area of the overlapping portion of the second projection is 0.5 times or more the area of the second projection. In one embodiment, the vertical projection (i.e., the second projection) of the first surface 101 onto the connection layer 10 is completely within the vertical projection (i.e., the first projection) of the conductive layer 30 onto the connection layer 10. include. In another embodiment, the vertical projection (i.e., the second projection) of the first surface 101 onto the connection layer 10 is within the vertical projection (i.e., the first projection) of the conductive layer 30 onto the connection layer 10. Completely contained, the area of the overlapping portion of the first and second projections is equal to the area of the second projection.

この実施形態では、導電層30は、金、チタン、アルミニウム、銀、白金、およびそれらの合金などの不透明な高導電性材料である。したがって、導電層30は、第2の表面102の複数のサブエリア102Sを露出するように構成され、サブエリア102Sは、それぞれ、発光メサ20に対応する。具体的には、図1Bに示されるように、接続層10へのサブエリア102Sの垂直投影は、それぞれ、接続層10への発光メサ20の垂直投影と重なり合い、その結果、発光メサ20の各々によって放出された光は、対応するサブエリア102Sを透過し、次いでマイクロ発光ダイオード表示装置1から出ることができる。接続層10への導電層30の垂直投影は、接続層10への第1の表面101の垂直投影と重なり合い、接続層10への発光メサ20の垂直投影と重なり合わないが、本開示はこれに限定されない。本開示の一実施形態では、接続層10への導電層30の垂直投影は、接続層10への発光メサ20の少なくとも一部の垂直投影と部分的に重なり合う。言い換えれば、接続層10へのサブエリア102Sの少なくとも一部の垂直投影の面積は、接続層10への対応する発光メサ20の垂直投影の面積よりも小さい。このような構成では、発光メサ20により放出された光が導電層30によってさらに制限され、光はより集中した方向に進み、これにより、表示サブピクセルPX間のクロストークが回避される。好ましくは、接続層10へのサブエリア102Sの少なくとも一部の垂直投影と、接続層10への対応する発光メサ20の垂直投影との間の比率は、0.5から1の間であり、その比率が0.5未満の場合、光抽出率が不十分になり得る。 In this embodiment, conductive layer 30 is an opaque, highly conductive material such as gold, titanium, aluminum, silver, platinum, and alloys thereof. Accordingly, conductive layer 30 is configured to expose a plurality of subareas 102S of second surface 102, each subarea 102S corresponding to a light emitting mesa 20. Specifically, as shown in FIG. 1B, the vertical projections of the subareas 102S onto the connection layer 10 overlap with the vertical projections of the light-emitting mesas 20 onto the connection layer 10, respectively, so that each of the light-emitting mesas 20 The light emitted by can pass through the corresponding sub-area 102S and then exit from the micro-light emitting diode display device 1. Although the vertical projection of conductive layer 30 onto connection layer 10 overlaps the vertical projection of first surface 101 onto connection layer 10 and does not overlap the vertical projection of light emitting mesa 20 onto connection layer 10, this disclosure but not limited to. In one embodiment of the present disclosure, the vertical projection of conductive layer 30 onto connection layer 10 partially overlaps the vertical projection of at least a portion of light emitting mesa 20 onto connection layer 10 . In other words, the area of the vertical projection of at least a portion of the subarea 102S onto the connection layer 10 is smaller than the area of the vertical projection of the corresponding light emitting mesa 20 onto the connection layer 10. In such a configuration, the light emitted by the light emitting mesa 20 is further restricted by the conductive layer 30 and the light travels in a more concentrated direction, thereby avoiding crosstalk between display sub-pixels PX. Preferably, the ratio between the vertical projection of at least a portion of the subarea 102S onto the connection layer 10 and the vertical projection of the corresponding light emitting mesa 20 onto the connection layer 10 is between 0.5 and 1; If the ratio is less than 0.5, the light extraction rate may be insufficient.

さらに、導電層30は不透明な高導電性材料であるため、導電層30の厚さは、導電層30によって吸収される光の量を低減するように、エピタキシー構造ESの厚さ以下になるように構成される。電流が表示領域A1の導電層30においてより均一に伝達されるように、表示領域A1に配置された導電層30の総面積は、非表示領域A2に配置された導電層30の総面積よりも大きいことにも留意されたい。発光メサ20の各々は、同じ電位差がそれに印加されるとき、同じ輝度を有する。 Furthermore, since the conductive layer 30 is an opaque highly conductive material, the thickness of the conductive layer 30 is adjusted to be less than or equal to the thickness of the epitaxial structure ES so as to reduce the amount of light absorbed by the conductive layer 30. It is composed of The total area of the conductive layers 30 disposed in the display area A1 is larger than the total area of the conductive layers 30 disposed in the non-display area A2 so that the current is transmitted more uniformly in the conductive layer 30 in the display area A1. Please also note that it is large. Each of the light emitting mesas 20 has the same brightness when the same potential difference is applied to it.

この実施形態では、マイクロ発光ダイオード表示装置1は、半導体パッド40をさらに含み、半導体パッド40および共通接地点として機能する接合金属層140、150は、すべて、非表示領域A2に配置され、発光メサ20は、表示領域A1に配置されている。 In this embodiment, the micro light emitting diode display device 1 further includes a semiconductor pad 40, and the semiconductor pad 40 and the bonding metal layers 140, 150, which function as a common ground point, are all located in the non-display area A2, and the light emitting diode display device 1 further includes a semiconductor pad 40. 20 is arranged in the display area A1.

半導体パッド40および発光メサ20は、同じプロセスで製造することができ、類似の構造を有するものとし得る。各発光メサ20の上面と接続層10から離れた側の半導体パッド40の上面は同一平面上にあるため、回路基板C1上の接合金属層150と接合金属層130を接合金属層140と接合金属層120にそれぞれ接合するプロセスの歩留まりを向上させることができる。さらに、接合金属層140はエピタキシャルセクション140Eを有し、接合金属層140を接続層10と接合金属層150との間に電気的に接続することができる。 Semiconductor pad 40 and light emitting mesa 20 may be manufactured in the same process and may have similar structures. Since the upper surface of each light emitting mesa 20 and the upper surface of the semiconductor pad 40 on the side away from the connection layer 10 are on the same plane, the bonding metal layer 150 and the bonding metal layer 130 on the circuit board C1 are connected to the bonding metal layer 140 and the bonding metal layer The yield of the process of bonding each layer 120 can be improved. Furthermore, the bonding metal layer 140 has an epitaxial section 140E, which allows the bonding metal layer 140 to be electrically connected between the connection layer 10 and the bonding metal layer 150.

本開示の様々な実施形態を十分に説明するために、本開示の他の実施形態を以下に記載する。以下の実施形態は、上記実施形態の参照番号および内容の一部を使用し、同じ参照番号は、同一または類似の要素を示すために使用され、同じ技術的内容の説明は省略されることに留意されたい。省略された部分の説明については、上記の実施形態を参照することができ、以下の実施形態には記載されない。 Other embodiments of the disclosure are described below in order to fully describe the various embodiments of the disclosure. The following embodiments use some of the reference numbers and content of the above embodiments, the same reference numbers are used to indicate the same or similar elements, and the description of the same technical content is omitted. Please note. For explanations of omitted parts, the above embodiments can be referred to and will not be described in the following embodiments.

図2Aおよび図2Bを参照すると、マイクロ発光ダイオード表示デバイス2は、表示領域A1および非表示領域A2を有し、回路基板C1、エピタキシー構造ES、および導電層30Aを含む。複数の発光メサ20は、4つの発光メサ20の単位で複数の発光メサグループ20Gにグループ化され、導電層30Aは、第2の表面102の複数のサブエリア102Gを露出するように構成され、サブエリア102Gは、それぞれ、発光メサグループ20Gに対応する。しかしながら、本開示はこれに限定されない。いくつかの実施形態では、マイクロ発光ダイオード表示装置2の発光メサ20は、少なくとも3つの発光メサ20の単位で複数の発光メサグループ20Gにグループ化される。その後、色変換要素(図示せず、例えば量子ドット)が少なくとも3つの発光メサ20に対応して第2の表面102上に配置されると、少なくとも3つの発光メサ20は、それぞれ、赤色光、緑色光、および青色光を放出し、フルカラー表示装置を形成することができる。 Referring to FIGS. 2A and 2B, the micro light emitting diode display device 2 has a display area A1 and a non-display area A2, and includes a circuit board C1, an epitaxial structure ES, and a conductive layer 30A. The plurality of light emitting mesas 20 are grouped into a plurality of light emitting mesa groups 20G in units of four light emitting mesas 20, and the conductive layer 30A is configured to expose the plurality of subareas 102G of the second surface 102, Each subarea 102G corresponds to a light emitting mesa group 20G. However, the present disclosure is not limited thereto. In some embodiments, the light emitting mesas 20 of the micro light emitting diode display 2 are grouped into a plurality of light emitting mesa groups 20G in units of at least three light emitting mesas 20. Thereafter, when color conversion elements (not shown, e.g. quantum dots) are disposed on the second surface 102 corresponding to the at least three light emitting mesas 20, the at least three light emitting mesas 20 are configured to emit red light, e.g. Green light and blue light can be emitted to form a full color display.

マイクロ発光ダイオード表示装置1と同様に、マイクロ発光ダイオード表示装置2の表示領域A1に配置された導電層30Aの総面積は、非表示領域A2に配置された導電層30Aの総面積よりも大きいため、電流が表示領域A1の導電層30Aにより均一に伝達され得る。発光メサ20の各々は、同じ電位差がそれに印加されるとき、同じ明るさを有する。 Similar to the micro-light-emitting diode display device 1, the total area of the conductive layers 30A arranged in the display area A1 of the micro-light-emitting diode display device 2 is larger than the total area of the conductive layers 30A arranged in the non-display area A2. , current can be uniformly transmitted by the conductive layer 30A in the display area A1. Each of the light emitting mesas 20 has the same brightness when the same potential difference is applied to it.

図3を参照すると、マイクロ発光ダイオード表示装置3は、表示領域と非表示領域を有し、回路基板C1、エピタキシー構造ES、導電層30B、導電層50、および絶縁層220を含む。導電層30Bは、表示領域に配置された導電層30B1と、非表示領域に配置された導電層30B2とを含む。 Referring to FIG. 3, the micro light emitting diode display device 3 has a display area and a non-display area, and includes a circuit board C1, an epitaxial structure ES, a conductive layer 30B, a conductive layer 50, and an insulating layer 220. The conductive layer 30B includes a conductive layer 30B1 arranged in the display area and a conductive layer 30B2 arranged in the non-display area.

導電層30B1の幅は、第2の表面102から離れる方向に(すなわち、第3の方向D3の正方向に沿って)減少し、導電層30B1は、底部が広く、上部が狭いビューを示す。図3に示す導電層30B1の断面図は円錐形を有するため、対応する発光メサ20により放出された光は反射されて、より中心に向けて集中され得る。その後、発光メサ20に対応する第2の表面102上に色変換要素(図示せず、例えば、量子ドット)が配置されると、導電層30B1に形成された溝Gは、そこに配置された色変換要素に対して、より大きな機械加工許容量を有する収容空間を提供する。他の実施形態では、導電層30B1の幅は、第2の表面102から離れる方向に減少し、導電層30B1は、断面図において台形の形状を有する。 The width of the conductive layer 30B1 decreases in the direction away from the second surface 102 (ie, along the positive direction of the third direction D3), and the conductive layer 30B1 presents a view that is wide at the bottom and narrow at the top. Since the cross-sectional view of the conductive layer 30B1 shown in FIG. 3 has a conical shape, the light emitted by the corresponding light emitting mesa 20 can be reflected and concentrated more toward the center. Thereafter, when a color conversion element (not shown, for example, a quantum dot) is placed on the second surface 102 corresponding to the light emitting mesa 20, the groove G formed in the conductive layer 30B1 Provides a housing space for color conversion elements with greater machining tolerances. In other embodiments, the width of conductive layer 30B1 decreases in a direction away from second surface 102, and conductive layer 30B1 has a trapezoidal shape in cross-section.

非表示領域の導電層30B2はまた、接続層10を貫通する貫通孔10H内に配置され、接合金属層140、接合金属層150、および回路基板C1に電気的に接続する。回路基板C1からの電流は、貫通孔10Hにおいて、接合金属層150、接合金属層140、導電層30B2に順次伝達され、より高い抵抗を有する接続層10を通過することなく第2の表面102上の導電層30B2、導電層30B1に到達する。表示領域に配置された導電層30B1の総面積は、非表示領域に配置された導電層30B2の総面積よりも大きいため、導電層30B1において電流がより均一に伝達されることが保証される。発光メサ20の各々は、同じ電位差がそれに印加されると、同じ輝度を有する。 The conductive layer 30B2 in the non-display area is also arranged in the through hole 10H penetrating the connection layer 10, and is electrically connected to the bonding metal layer 140, the bonding metal layer 150, and the circuit board C1. The current from the circuit board C1 is sequentially transmitted to the bonding metal layer 150, the bonding metal layer 140, and the conductive layer 30B2 in the through hole 10H, and is transferred onto the second surface 102 without passing through the connection layer 10 having a higher resistance. The conductive layer 30B2 and the conductive layer 30B1 are reached. Since the total area of the conductive layer 30B1 disposed in the display area is larger than the total area of the conductive layer 30B2 disposed in the non-display area, it is ensured that the current is transmitted more uniformly in the conductive layer 30B1. Each of the light emitting mesas 20 has the same brightness when the same potential difference is applied to it.

この実施形態のマイクロ発光ダイオード表示装置3は、接続層10の第1の表面101上に配置された別の導電層50をさらに含む。言い換えれば、導電層50は、発光メサ20の間に配置される。導電層50はまた、回路基板C1から電流を伝達するように構成され、導電層50と発光メサ20との間に絶縁層220が配置される。 The micro-light emitting diode display device 3 of this embodiment further comprises another conductive layer 50 arranged on the first surface 101 of the connection layer 10. In other words, the conductive layer 50 is arranged between the light emitting mesas 20. The conductive layer 50 is also configured to conduct current from the circuit board C1, and an insulating layer 220 is disposed between the conductive layer 50 and the light emitting mesa 20.

図4を参照すると、マイクロ発光ダイオード表示装置4は、回路基板C1、エピタキシー構造ES1、および導電層30Cを含む。 Referring to FIG. 4, the micro light emitting diode display device 4 includes a circuit board C1, an epitaxial structure ES1, and a conductive layer 30C.

エピタキシー構造ES1は、接続層10Aおよび複数の発光メサ20を含む。接続層10Aは、パターン化されたエピタキシャル基板上にエピタキシャル成長によって形成することができ、複数の三次元パターン102Pを含み、三次元パターン102Pは、第2の表面102A上に配置されている。すなわち、接続層10Aは、第2の表面102が平坦である図1Bに示される接続層10とは相違し、接続層10Aの第2の表面102Aは、複数の三次元パターン102Pを有する。導電層30Cは、三次元パターン102Pの複数の溝G'内に配置されている。このような状況では、三次元パターン102Pの上に配置された導電層30Cと第2の表面102Aとの間の接触面積は、図1Bに示される導電層30と第2の表面102との間の接触面積よりも大きくなり、接続層10Aと導電層30Cとの間の接合歩留まりが向上し、回路基板C1からの電流の伝達効率が向上する。 The epitaxial structure ES1 includes a connection layer 10A and a plurality of light emitting mesas 20. The connection layer 10A can be formed by epitaxial growth on a patterned epitaxial substrate, and includes a plurality of three-dimensional patterns 102P, the three-dimensional patterns 102P being arranged on the second surface 102A. That is, the connection layer 10A is different from the connection layer 10 shown in FIG. 1B in which the second surface 102 is flat, and the second surface 102A of the connection layer 10A has a plurality of three-dimensional patterns 102P. The conductive layer 30C is arranged within the plurality of grooves G' of the three-dimensional pattern 102P. In such a situation, the contact area between the conductive layer 30C disposed on the three-dimensional pattern 102P and the second surface 102A is the same as that between the conductive layer 30 and the second surface 102 shown in FIG. 1B. , the bonding yield between the connection layer 10A and the conductive layer 30C is improved, and the current transmission efficiency from the circuit board C1 is improved.

上記の導電層30、導電層30A、導電層30B、および導電層30Cは、不透明導電層である。しかしながら、本開示はこれに限定されない。いくつかの実施形態では、導電層30、導電層30A、導電層30B、および導電層30Cは、透明導電層である。 The above conductive layer 30, conductive layer 30A, conductive layer 30B, and conductive layer 30C are opaque conductive layers. However, the present disclosure is not limited thereto. In some embodiments, conductive layer 30, conductive layer 30A, conductive layer 30B, and conductive layer 30C are transparent conductive layers.

図5を参照すると、マイクロ発光ダイオード表示装置5は、回路基板C1、エピタキシー構造ES、および透明導電層30Tを含む。透明導電層30Tは、接続層10の第2の表面102上に配置され、第2の表面102を完全に覆う。透明導電層30Tの材料は、酸化インジウムスズ(ITO)または亜鉛(ZnO)などの酸化金属材料であってよい。光は透明導電層30Tを透過することができるので、前の実施形態におけるさまざまな不透明導電層のように、第2の表面の複数のサブ領域を露出させる必要はないため、透明導電層30Tと第2の表面との間の接触面積が最大になり、回路基板C1からの電流の伝達効率が大幅に改善される。 Referring to FIG. 5, the micro light emitting diode display device 5 includes a circuit board C1, an epitaxial structure ES, and a transparent conductive layer 30T. The transparent conductive layer 30T is disposed on the second surface 102 of the connection layer 10 and completely covers the second surface 102. The material of the transparent conductive layer 30T may be a metal oxide material such as indium tin oxide (ITO) or zinc (ZnO). Since light can pass through the transparent conductive layer 30T, there is no need to expose multiple sub-regions of the second surface as with various opaque conductive layers in previous embodiments; The contact area with the second surface is maximized and the efficiency of current transfer from the circuit board C1 is greatly improved.

要約すると、本開示の実施形態によって提供されるマイクロ発光ダイオード表示装置では、導電層がエピタキシー構造の接続層上に配置される。導電層の抵抗値は接続層の抵抗値よりも小さいので、回路基板からの電流は導電層内に伝達され得る。この場合、発光メサが共通の接地点からの距離が異なっていても、同じ電位差が同じ数の電子正孔対を駆動してそれらの発光メサで再結合することができ、これにより、マイクロ発光ダイオード表示装置の不均一輝度を避けることができる。さらに、導電層を接続層の第1の表面に配置する場合とは対照的に、導電層を接続層の第2の表面に配置する製造プロセスは、著しく高い歩留まりを有する。 In summary, in the micro-light emitting diode display provided by embodiments of the present disclosure, a conductive layer is disposed on a connecting layer of an epitaxial structure. Since the resistance of the conductive layer is smaller than the resistance of the connection layer, current from the circuit board can be transferred into the conductive layer. In this case, even if the emitting mesas are at different distances from a common ground point, the same potential difference can drive the same number of electron-hole pairs to recombine in their emitting mesas, which leads to micro-emitting Non-uniform brightness of diode display devices can be avoided. Moreover, a manufacturing process in which the conductive layer is placed on the second surface of the connection layer, as opposed to the case in which the conductive layer is placed on the first surface of the connection layer, has a significantly higher yield.

本開示のマイクロ発光ダイオード表示装置は、より高い歩留まりを有しながら、均一な発光輝度を有し得る。 The micro-light emitting diode display device of the present disclosure can have uniform emission brightness while having higher yield.

1、2、3、4、5:マイクロ発光ダイオード表示装置
10、10A:接続層
10H:貫通孔
20:発光メサ
20G:発光メサグループ
30、30A、30B、30B1、30B2、50、30C、30T:導電層
40:半導体パッド
101:第1の表面
102、102A:第2の表面
102P:3次元パターン
102S、102G:サブエリア
120、130、140、150:接合金属層
140E:エピタキシャルセクション
201:第1の型の半導体層
202:第2の型の半導体層
203:発光層
220:絶縁層
A1:表示領域
A2:非表示領域
C1:回路基板
D1:第1の方向
D2:第2の方向
D3:第3の方向
ES、ES1:エピタキシー構造
G、G’:溝
PX:表示サブピクセル
1, 2, 3, 4, 5: Micro light emitting diode display device 10, 10A: Connection layer 10H: Through hole 20: Light emitting mesa 20G: Light emitting mesa group 30, 30A, 30B, 30B1, 30B2, 50, 30C, 30T: Conductive layer 40: Semiconductor pad 101: First surface 102, 102A: Second surface 102P: Three-dimensional pattern 102S, 102G: Subarea 120, 130, 140, 150: Bonding metal layer 140E: Epitaxial section 201: First type semiconductor layer 202: second type semiconductor layer 203: light emitting layer 220: insulating layer A1: display area A2: non-display area
C1: Circuit board D1: First direction D2: Second direction D3: Third direction ES, ES1: Epitaxial structure G, G': Groove PX: Display subpixel

Claims (7)

回路基板と、
前記回路基板に電気的に接続されたエピタキシー構造であって、
接続層と、
前記接続層上に配置された複数の発光メサと、を備え、前記接続層の厚さが前記発光メサの厚さよりも薄く、前記接続層が前記発光メサによって露出された第1の表面と該第1の表面の反対側の第2の表面を有する、エピタキシー構造と、
前記接続層の前記第2表面に配置された第1の導電層であって、前記接続層への前記第1の導電層の垂直投影が、前記接続層への前記第1の表面の垂直投影と重なり合う、第1の導電層と、を備え、
前記第1の導電層の厚さが、前記エピタキシー構造の厚さ以下である、マイクロ発光ダイオード表示装置。
a circuit board;
an epitaxial structure electrically connected to the circuit board,
a connection layer;
a plurality of light-emitting mesas disposed on the connection layer, wherein the connection layer has a thickness thinner than the light-emission mesa, and the connection layer contacts a first surface exposed by the light-emission mesa. an epitaxial structure having a second surface opposite the first surface;
a first conductive layer disposed on the second surface of the connection layer, wherein a vertical projection of the first conductive layer onto the connection layer is a vertical projection of the first surface onto the connection layer; a first conductive layer overlapping the projection;
The micro light emitting diode display device, wherein the thickness of the first conductive layer is less than or equal to the thickness of the epitaxial structure.
前記接続層への前記第1の導電層の垂直投影が第1の投影であり、前記接続層への前記第1の表面の垂直投影が第2の投影であり、前記第1投影と前記第2の投影の重なり合う部分の面積が、前記第2の投影の面積の0.5倍以上である、請求項1に記載のマイクロ発光ダイオード表示装置。 The vertical projection of the first conductive layer onto the connection layer is a first projection, the vertical projection of the first surface onto the connection layer is a second projection, and the first projection and the The micro light emitting diode display device according to claim 1, wherein the area of the overlapping portion of the second projection is 0.5 times or more the area of the second projection. 前記第1の導電層が前記第2の表面の複数のサブエリアを露出し、前記サブエリアがそれぞれ前記発光メサに対応する、請求項1に記載のマイクロ発光ダイオード表示装置。 2. The micro light emitting diode display of claim 1, wherein the first conductive layer exposes a plurality of subareas of the second surface, each subarea corresponding to the light emitting mesa. 前記発光メサが複数の発光メサグループにグループ化され、前記第1の導電層が前記第2の表面の複数のサブエリアを露出し、前記サブエリアがそれぞれ前記発光メサグループに対応する、請求項1に記載のマイクロ発光ダイオード表示装置。 4. The light emitting mesa is grouped into a plurality of light emitting mesa groups, the first conductive layer exposing a plurality of subareas of the second surface, each subarea corresponding to the light emitting mesa group. 1. The micro light emitting diode display device according to 1. 前記第1の導電層は、前記接続層を貫通する貫通孔内に配置され、前記回路基板に電気的に接続している、請求項1に記載のマイクロ発光ダイオード表示装置。 The micro light emitting diode display device according to claim 1, wherein the first conductive layer is disposed in a through hole penetrating the connection layer and electrically connected to the circuit board. 前記接続層の前記第1の表面に配置された第2の導電層をさらに備える、請求項1に記載のマイクロ発光ダイオード表示装置。 The micro light emitting diode display of claim 1, further comprising a second conductive layer disposed on the first surface of the connection layer. 回路基板と、
前記回路基板に電気的に接続されたエピタキシー構造であって、接続層と、該接続層上に配置された複数の発光メサとを備え、前記接続層が前記発光メサによって露出された第1の表面および該第1の表面と反対側の第2の表面を有する、エピタキシー構造と、
前記接続層の第2の表面上に配置され、前記第2の表面を完全に覆う透明導電層と、を備え、
前記透明導電層の厚さが、前記エピタキシー構造の厚さ以下である、マイクロ発光ダイオード表示装置。
a circuit board;
an epitaxial structure electrically connected to the circuit board, the epitaxial structure comprising a connection layer and a plurality of light emitting mesas disposed on the connection layer, wherein the connection layer has a first structure exposed by the light emitting mesas; an epitaxial structure having a surface and a second surface opposite the first surface;
a transparent conductive layer disposed on the second surface of the connection layer and completely covering the second surface,
A micro light emitting diode display device, wherein the thickness of the transparent conductive layer is less than or equal to the thickness of the epitaxial structure.
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