JP7408312B2 - Semiconductor storage device, memory system, and writing method - Google Patents

Description

Embodiments of the present invention relate to a semiconductor memory device, a memory system, and a writing method.

A NAND flash memory is known as a semiconductor memory device.

US Patent No. 8,482,976 Patent No. 4928752

Provided are a semiconductor memory device, a memory system, and a writing method that can suppress an increase in chip area.

The semiconductor memory device according to the embodiment stores 1-bit data, and sets the threshold voltage to an erase level, a first write level higher than the erase level , a second write level higher than the first write level, and a threshold voltage higher than the second write level. A memory cell array including a first memory cell that can be set to either a third write level that is higher than the third write level and a fourth write level that is higher than the third write level, and a first flag cell , the first memory cell and the first flag cell. a first word line connected to the first flag cell , and a write operation is performed on the first memory cell at least four times between performing an erase operation and performing the next erase operation, and the threshold voltage of the first flag cell is set to the threshold voltage of the first flag cell. a sequencer configured to perform a read operation of the first memory cell based on the first memory cell. The sequencer sets the threshold voltage of the first flag cell to one of the erase level, the second write level, the third write level, and the fourth write level based on the number of executions of the write operation after the erase operation. When a read operation is performed based on the first condition, a first voltage higher than the erase level and lower than the first write level is applied to the first word line, and the read operation is performed based on the second condition. When a second voltage higher than the first write level and lower than the second write level is applied to the first word line, and when a read operation is performed based on the third condition, a second voltage is applied to the first word line. When a third voltage higher than the second write level and lower than the third write level is applied and a read operation is performed based on the fourth condition, a third voltage higher than the third write level and lower than the third write level is applied to the first word line. A fourth voltage lower than the write level is applied .

FIG. 1 is a block diagram of a memory system according to a first embodiment. FIG. 2 is a circuit diagram of a memory cell array in the semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing data allocation, threshold distribution, and read level of memory cell transistors in the semiconductor memory device according to the first embodiment. FIG. 4 is a diagram showing changes in the threshold distribution of memory cell transistors due to the first write operation in the semiconductor memory device according to the first embodiment. FIG. 5 is a diagram showing changes in the threshold distribution of memory cell transistors due to the second write operation in the semiconductor memory device according to the first embodiment. FIG. 6 is a diagram showing conversion from 4-bit data consisting of Lower bit, Middle bit, Upper bit, and Top bit to 2-bit data consisting of X1 bit and X2 bit in the memory system according to the first embodiment. FIG. 7 shows how 4-bit data is extracted from 2-bit data and internal read data corresponding to "0" level, "4" level, "8" level, and "C" level in the memory system according to the first embodiment. FIG. 6 is a diagram showing a case of restoration. FIG. 8 shows how 4-bit data is extracted from 2-bit data and internal read data corresponding to "1" level, "5" level, "9" level, and "D" level in the memory system according to the first embodiment. FIG. 6 is a diagram showing a case of restoration. FIG. 9 shows how 4-bit data is extracted from 2-bit data and internal read data corresponding to "2" level, "6" level, "A" level, and "E" level in the memory system according to the first embodiment. FIG. 6 is a diagram showing a case of restoration. FIG. 10 shows how 4-bit data is extracted from 2-bit data and internal read data corresponding to "3" level, "7" level, "B" level, and "F" level in the memory system according to the first embodiment. FIG. 6 is a diagram showing a case of restoration. FIG. 11 is a flowchart of a write operation in the memory system according to the first embodiment. FIG. 12 is a diagram showing a command sequence for a first write operation in the memory system according to the first embodiment. FIG. 13 is a diagram showing a command sequence of the second write operation of the first example in the memory system according to the first embodiment. FIG. 14 is a diagram illustrating a command sequence of a second write operation of a second example in the memory system according to the first embodiment. FIG. 15 is a diagram showing the data write order in the semiconductor memory device according to the first embodiment. FIG. 16 is a flowchart of a write operation showing the order of writing data in the memory system according to the first embodiment. FIG. 17 is a flowchart of a write operation showing the data write order in the memory system according to the first embodiment. FIG. 18 is a block diagram of a RAM included in the memory system according to the second embodiment. FIG. 19 is a flowchart of a normal state write operation in the memory system according to the second embodiment. FIG. 20 is a diagram showing a command sequence of a second write operation in a normal state in the memory system according to the second embodiment. FIG. 21 is a flowchart of a write operation in a normal state showing the data write order in the memory system according to the second embodiment. FIG. 22 is a flowchart of a write operation in a normal state showing the data write order in the memory system according to the second embodiment. FIG. 23 is a flowchart showing the overall flow when power is cut off in the memory system according to the second embodiment. FIG. 24 is a diagram illustrating a command sequence for an SLC write operation when power is cut off in the memory system according to the second embodiment. FIG. 25 is a flowchart showing the overall flow when power is restored in the first example in the memory system according to the second embodiment. FIG. 26 is a diagram illustrating the command sequence of the first example of the SLC read operation and the second write operation in the flow of the first example of power restoration in the memory system according to the second embodiment. FIG. 27 is a diagram illustrating a command sequence of a second example of the SLC read operation and a second write operation in the flow of the first example of power restoration in the memory system according to the second embodiment. FIG. 28 is a flowchart showing the overall flow when power is restored in the second example in the memory system according to the second embodiment. FIG. 29 is a diagram illustrating the command sequence of the first example of the SLC read operation and the second write operation in the second example of the flow when power is restored in the memory system according to the second embodiment. FIG. 30 is a diagram illustrating a command sequence of a second example of the SLC read operation and a second write operation in the flow of the second example of power restoration in the memory system according to the second embodiment. FIG. 31 is a flowchart of the SLC write operation when power is cut off, showing the data write order in the memory system according to the second embodiment. FIG. 32 is a diagram showing the data write order in the semiconductor memory device according to the third embodiment. FIG. 33 is a block diagram of a memory system according to the fourth embodiment. FIG. 34 is a flowchart of a write operation in the memory system according to the first example of the fourth embodiment. FIG. 35 is a diagram illustrating a command sequence of a first example write operation in a memory system according to a first example of the fourth embodiment. FIG. 36 is a diagram illustrating a command sequence of a second example write operation in the memory system according to the first example of the fourth embodiment. FIG. 37 is a flowchart of a write operation in the memory system according to the second example of the fourth embodiment. FIG. 38 is a diagram showing a command sequence of a write operation in a memory system according to a second example of the fourth embodiment. FIG. 39 is a diagram showing a command sequence of a write operation in a memory system according to the third example of the fourth embodiment. FIG. 40 is a diagram showing a command sequence of a write operation in a memory system according to the third example of the fourth embodiment. FIG. 41 is a block diagram of a memory cell array in a semiconductor memory device according to the fifth embodiment. FIG. 42 is a diagram showing a threshold distribution of write data in an SLC write operation corresponding to two write operations in the semiconductor memory device according to the fifth embodiment. FIG. 43 is a diagram showing a first example of the data write order corresponding to two write operations in the semiconductor memory device according to the fifth embodiment. FIG. 44 is a diagram showing a second example of the data write order corresponding to two write operations in the semiconductor memory device according to the fifth embodiment. FIG. 45 is a flowchart showing an SLC read operation corresponding to two write operations in the semiconductor memory device according to the fifth embodiment. FIG. 46 is a diagram showing the threshold distribution of write data in the first to fourth write operations in the SLC write operation corresponding to four write operations in the semiconductor memory device according to the first example of the fifth embodiment. FIG. 47 is a diagram showing the threshold distribution of flag cells in the first to fourth write operations in the SLC write operation corresponding to four write operations in the semiconductor memory device according to the first example of the fifth embodiment. FIG. 48 is a flowchart of an SLC read operation corresponding to four write operations in the semiconductor memory device according to the first example of the fifth embodiment. FIG. 49 is a diagram showing the threshold distribution of flag cells in the first to fourth write operations in the SLC write operation corresponding to four write operations in the semiconductor memory device according to the second example of the fifth embodiment. FIG. 50 is a flowchart of an SLC read operation corresponding to four write operations in the semiconductor memory device according to the second example of the fifth embodiment. FIG. 51 is a diagram showing the threshold distribution of the B flag cell in the first to fourth write operations in the SLC write operation corresponding to four write operations in the semiconductor memory device according to the third example of the fifth embodiment. FIG. 52 is a diagram showing threshold distributions of C flag cells in the first to fourth write operations in the SLC write operation corresponding to four write operations in the semiconductor memory device according to the third example of the fifth embodiment. FIG. 53 is a diagram showing threshold distributions of D flag cells in the first to fourth write operations in the SLC write operation corresponding to four write operations in the semiconductor memory device according to the third example of the fifth embodiment. FIG. 54 is a flowchart of an SLC read operation corresponding to four write operations in a semiconductor memory device according to the third example of the fifth embodiment. FIG. 55 is a circuit diagram of a memory cell array in a semiconductor memory device according to a sixth embodiment. FIG. 56 is a circuit diagram of a row decoder in a semiconductor memory device according to a sixth embodiment. FIG. 57 is a circuit diagram of a block decoder in a semiconductor memory device according to the sixth embodiment. FIG. 58 is a block diagram of a sense amplifier in a semiconductor memory device according to a sixth embodiment. FIG. 59 is a circuit diagram of a sense amplifier section in a semiconductor memory device according to a sixth embodiment. FIG. 60 is a cross-sectional view of a semiconductor memory device according to the sixth embodiment. FIG. 61 is a table showing the voltages of the P well and N well during erase operation, write operation, and read operation in the semiconductor memory device according to the sixth embodiment. FIG. 62 is a diagram showing the threshold distribution, read level, and verify level of memory cell transistors in the semiconductor memory device according to the sixth embodiment. FIG. 63 is a timing chart showing the voltage of each wiring during a read operation in the semiconductor memory device according to the sixth embodiment. FIG. 64 is a timing chart showing the voltages of each wiring during the erase pulse application operation in the semiconductor memory device according to the sixth embodiment. FIG. 65 is a timing chart showing the voltages of each wiring in the normal operation mode in the semiconductor memory device according to the sixth embodiment. FIG. 66 is a timing chart showing the voltage of each wiring in the negative voltage operation mode in the semiconductor memory device according to the sixth embodiment. FIG. 67 is a flowchart showing the flow of a first example write operation in the semiconductor memory device according to the sixth embodiment. FIG. 68 is a timing chart showing the voltage of the selected word line, bit line voltage, input data, and ready-busy signal in the first example write operation in the semiconductor memory device according to the sixth embodiment. FIG. 69 is a flowchart showing the flow of a second example write operation in the semiconductor memory device according to the sixth embodiment. FIG. 70 is a timing chart showing the voltage of the selected word line, bit line voltage, input data, and ready-busy signal in the second example of the write operation in the semiconductor memory device according to the sixth embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In this description, components having substantially the same functions and configurations are given the same reference numerals. In addition, each embodiment shown below exemplifies a device and a method for embodying the technical idea of this embodiment, and the technical idea of the embodiment is based on the materials, shapes, and structures of component parts. , arrangement etc. are not specified as below. The technical idea of the embodiments can be modified in various ways within the scope of the claims.

1. First Embodiment A semiconductor memory device according to a first embodiment will be described. In the following, a three-dimensionally stacked NAND flash memory in which memory cell transistors are stacked above a semiconductor substrate will be described as an example of a semiconductor memory device.

1.1 Configuration 1.1.1 Memory System Configuration First, the overall configuration of the memory system 1 will be described using FIG. 1. Note that in the example of FIG. 1, some of the connections between the blocks are shown by arrow lines, but the connections between the blocks are not limited to this.

As shown in FIG. 1, the memory system 1 includes a NAND flash memory 10 (hereinafter referred to as memory 10) and a controller 20, and is connected to an external host device 30.

The controller 20 instructs the memory 10 to perform data read operations, write operations, erase operations, etc. in response to requests (commands) from the host device 30. Further, the controller 20 manages the memory space of the memory 10.

The controller 20 includes a host interface circuit 21 , a built-in memory (RAM) 22 , a processor (CPU; central processing unit) 23 , a buffer memory 24 , an ECC circuit 25 , a NAND interface circuit 26 , and a data conversion circuit 27 .

The host interface circuit 21 is connected to the host device 30 via a host bus, and controls communication with the host device 30. For example, the host interface circuit 21 transfers commands and data received from the host device 30 to the CPU 23 and buffer memory 24, respectively. Further, the host interface circuit 21 transfers the data in the buffer memory 24 to the host device 30 in response to a command from the CPU 23.

The RAM 22 is, for example, a semiconductor memory such as a DRAM, and holds firmware for managing the memory 10, various management tables, and the like. Further, the RAM 22 is used as a work area for the CPU 23. More specifically, for example, the RAM 22 includes page clusters CL0 to CL(k-1) (k is an integer of 2 or more). The number of page clusters CL can be arbitrarily set depending on the writing order of data in the memory 10 and the like. In the present embodiment, a case will be described below in which eight page clusters CL0 to CL7 are provided. Further, each page cluster CL includes, for example, areas PG0 and PG1. Each area PG can hold one page of data. The definition of "page" will be described later. In other words, one page cluster CL can hold two pages of data. Note that the number of areas PG in the page cluster CL can be arbitrarily set depending on the method of writing data to the memory 10 and the like.

The CPU 23 controls the overall operation of the controller 20. For example, the CPU 23 issues a write command to the NAND interface circuit 26 in response to a write command received from the host device 30. This operation is similar for read commands and erase commands. The CPU 23 also executes various processes for managing the memory space of the memory 10, such as wear leveling.

The buffer memory 24 temporarily holds read data received by the controller 20 from the memory 10, write data received from the host device 30, and the like.

The ECC circuit 25 performs data error checking and correcting (ECC) processing. Specifically, the ECC circuit 25 generates parity based on the write data when writing data. Then, the ECC circuit 25 generates a syndrome from the parity when reading data, detects an error, and corrects the detected error.

The NAND interface circuit 26 is connected to the memory 10 via a NAND bus, and controls communication with the memory 10. For example, the NAND interface circuit 26 transmits various control signals to the memory 10 based on instructions received from the CPU 23, receives a ready-busy signal RBn from the memory 10, and transmits and receives input/output signals I/O to and from the memory 10. do.

The ready-busy signal RBn is a signal that notifies whether the memory 10 can receive instructions from the controller 20. For example, the ready-busy signal RBn is set to a High (“H”) level when the memory 10 is in a ready state in which it can receive commands from the controller 20, and is set to a Low (“L”) level when it is in a busy state where it cannot receive commands. be done.

The input/output signal I/O is, for example, an 8-bit signal, and includes command CMD, address ADD, data DAT, and the like. For example, during a write operation, the input/output signal I/O transferred to the memory 10 includes a write command CMD issued by the CPU 23, an address ADD, and write data DAT in the buffer memory 24. Further, during a read operation, the input/output signal I/O transferred to the memory 10 includes a read command CMD and address ADD, and the input/output signal I/O transferred to the controller 20 includes read data DAT.

For example, if the memory cell transistor included in the memory 10 is a QLC (quad level cell) that holds 4-bit (16-value) data, the data conversion circuit 27 converts 4-bit data corresponding to the QLC into 2-bit data. Convert. In other words, the data conversion circuit 27 generates 2-bit data from 4-bit data of QLC. The converted 2-bit data is stored in the RAM 22. Note that the data conversion circuit 27 may be provided within the CPU 23. Furthermore, the number of bits of data converted by the data conversion circuit 27 can be set arbitrarily. For example, 3-bit data may be converted to 1-bit data, and 5-bit data may be converted to 3-bit data or 2-bit data.

Examples of the host device 30 that uses the memory system 1 described above include a digital camera and a personal computer.

Next, the configuration of the memory 10 will be explained. The memory 10 includes a memory cell array 11, a command register 12, an address register 13, a sequencer 14, a driver circuit 15, a row decoder 16, a data register 17, a sense amplifier 18, and a data restoration control circuit 19.

The memory cell array 11 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). The block BLK is a collection of a plurality of nonvolatile memory cell transistors associated with bit lines and word lines, and is, for example, a data erase unit.

The memory cell array 11 includes a user area and a management area as memory space areas, and for example, a plurality of blocks BLK are allocated to the user area and the management area, respectively. The user area is an area used for writing and reading data received from the host device 30. The management area is, for example, an area where control programs or management data such as various setting parameters are saved. Furthermore, the management area stores, for example, backup data when the power is cut off.

The command register 12 holds the command CMD received from the controller 20. The address register 13 holds the address ADD received from the controller 20. This address ADD includes a column address CA, a page address PA, and a block address BA.

The sequencer 14 controls the overall operation of the memory 10 based on the command CMD held in the command register 12. Specifically, the sequencer 14 controls the driver circuit 15, row decoder 16, data register 17, sense amplifier 18, data restoration control circuit 19, etc. based on the command CMD, and performs data writing and reading operations. Execute an action, etc.

The driver circuit 15 generates necessary voltages based on instructions from the sequencer 14. The driver circuit 15 supplies the generated voltage to the row decoder 16 based on the page address PA held in the address register 13.

The row decoder 16 selects one of the blocks BLK0 to BLKn based on the block address BA held in the address register 13. Furthermore, the row decoder 16 selects the row direction in the selected block BLK, and applies the voltage supplied from the driver circuit 15 to the word line or the like.

Data register 17 includes a plurality of latch circuits. A latch circuit temporarily holds data. For example, in a write operation, the data register 17 temporarily holds write data received via an input/output circuit (not shown) and transmits it to the sense amplifier 18. Also, for example, in a read operation, the data register 17 temporarily holds read data received from the sense amplifier 18 and transmits it to the controller 20 via the input/output circuit.

The sense amplifier 18 senses data read from the memory cell array 11 during a read operation. The sense amplifier 18 then transmits the read data to the data register 17. The sense amplifier 18 transmits write data to the memory cell array 11 during a write operation. Furthermore, the sense amplifier 18 includes a plurality of latch circuits (not shown) to hold data.

The data restoration control circuit 19 stores the 2-bit conversion data received from the controller 20 and the data read from the memory cell array 11 (hereinafter also referred to as internal data) in the data register 17 and performs an operation. The 4-bit data corresponding to is restored. Note that the data restoration control circuit 19 may be provided within the sequencer 14.

1.1.2 Configuration of Memory Cell Array Next, the configuration of the memory cell array 11 will be described using FIG. 2. Although the example in FIG. 2 shows block BLK0, the configurations of other blocks BLK are also the same.

As shown in FIG. 2, block BLK0 includes, for example, four string units SU0 to SU3. Hereinafter, when the string units SU0 to SU3 are not limited, they will be expressed as string units SU or SUi (i is an integer from 0 to 3). Each string unit SU includes multiple NAND strings NS. Each NAND string NS includes, for example, 96 memory cell transistors MT0 to MT95 and selection transistors ST1 and ST2. Hereinafter, when the memory cell transistors MT0 to MT95 are not limited, they will be referred to as memory cell transistors MT. The memory cell transistor MT includes a control gate and a charge storage layer, and holds data in a non-volatile manner.

Note that the number of string units SU is not limited to four. Furthermore, the memory cell transistor MT may be of a MONOS type using an insulating film as a charge storage layer, or may be of an FG type using a conductive layer as a charge storage layer. The number of memory cell transistors MT is not limited to 96, and may be 8, 16, 32, 64, 128, etc., and the number is not limited. Further, the number of selection transistors ST1 and ST2 is arbitrary, and it is sufficient if each selection transistor is one or more.

Memory cell transistor MT is connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. More specifically, the current paths of memory cell transistors MT0 to MT95 are connected in series. The drain of the memory cell transistor MT95 is connected to the source of the selection transistor ST1, and the source of the memory cell transistor MT0 is connected to the drain of the selection transistor ST2.

The gates of selection transistors ST1 in each of string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. Similarly, the gates of selection transistors ST2 in each of string units SU0 to SU3 are connected to selection gate lines SGS0 to SGS3, respectively. Hereinafter, when the selection gate lines SGD0 to SGD3 are not limited, they will be referred to as selection gate lines SGD. When the selection gate lines SGS0 to SGS3 are not limited, they are referred to as selection gate lines SGS. Note that the selection gate lines SGS0 to SGS3 of each string unit SU may be connected in common.

The control gates of memory cell transistors MT0 to MT95 in block BLK are commonly connected to word lines WL0 to WL95, respectively. Hereinafter, when word lines WL0 to WL95 are not limited, they will be expressed as word lines WL or WLj (j is an integer from 0 to 95).

The drains of the selection transistors ST1 of each NAND string NS in the string unit SU are connected to different bit lines BL0 to BL(m-1) (m is an integer of 2 or more). Hereinafter, if the bit lines BL0 to BL(m-1) are not limited, they will be referred to as bit lines BL. Each bit line BL commonly connects one NAND string NS in each string unit SU between a plurality of blocks BLK. Furthermore, the sources of the plurality of selection transistors ST2 are commonly connected to the source line SL. In other words, the string unit SU is a collection of NAND strings NS connected to different bit lines BL and connected to the same selection gate lines SGD and SGS. Furthermore, the block BLK is a collection of a plurality of string units SU that share a common word line WL. The memory cell array 11 is an aggregation of a plurality of blocks BLK that share a common bit line BL.

Writing and reading of data is performed all at once to memory cell transistors MT connected to any one of the word lines WL in any one of the string units SU. Hereinafter, a group of memory cell transistors MT that are collectively selected during data write and read operations will be referred to as a "memory cell group MCG." In one memory cell group MCG, a collection of 1-bit data written to or read from each memory cell transistor MT is referred to as a "page". Therefore, when storing 4-bit data in one memory cell transistor MT, four pages of data are stored in the memory cell group MCG connected to one word line WL.

In this embodiment, one memory cell transistor MT in the user area can hold 4-bit data. That is, the memory cell transistor MT in the user area in this embodiment is a QLC (quad level cell) that holds 4-bit data. The 4-bit data held by the QLC is expressed as "Lower bit", "Middle bit", "Upper bit", and "Top bit" in order from the lower bit. Also, a set of Lower bits held by memory cell group MCG is referred to as a "Lower page", a set of Middle bits is referred to as a "Middle page", a set of Upper bits is referred to as an "Upper page", and a set of Upper bits is referred to as a "Top bit". A collection of pages is referred to as a "Top page".

Note that the number of bits of data that the memory cell transistor MT can hold is not limited to 4 bits. This embodiment can be applied as long as the memory cell transistor MT can hold data of 3 bits or more.

1.2 Threshold Distribution of Memory Cell Transistor MT Next, the threshold distribution of memory cell transistor MT will be described using FIG. 3. FIG. 3 shows the data that each memory cell transistor MT can take, the threshold distribution, and the voltage used during the read operation.

As shown in FIG. 3, when the memory cell transistor MT holds 4-bit data, its threshold voltage distribution is divided into 16 parts. These 16 threshold voltage distributions are arranged in descending order of threshold voltage: "0" level, "1" level, "2" level, "3" level, "4" level, "5" level, "6" level, They are expressed as "7" level, "8" level, "9" level, "A" level, "B" level, "C" level, "D" level, "E" level, and "F" level.

Further, voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF shown in FIG. 4 are respectively at "0" level and " 1” level, “2” level, “3” level, “4” level, “5” level, “6” level, “7” level, “8” level, “9” level, “A” level, “ It is used to verify the "B" level, "C" level, "D" level, "E" level, and "F" level. Voltage VREAD is a voltage applied to unselected word lines during a read operation. When a voltage VREAD is applied to the gate of the memory cell transistor MT, the memory cell transistor MT is turned on regardless of the data it holds. The relationship between these voltage values is V1<V2<V3<V4<V5<V6<V7<V8<V9<VA<VB<VC<VD<VE<VF<VREAD.

The “0” level in the threshold distribution described above corresponds to the erased state of the memory cell transistor MT. The threshold voltage at the "0" level is less than the voltage V1. The threshold voltage at the "1" level is greater than or equal to voltage V1 and less than voltage V2. The threshold voltage at the "2" level is greater than or equal to voltage V2 and less than voltage V3. The threshold voltage at the "3" level is greater than or equal to voltage V3 and less than voltage V4. The threshold voltage at the "4" level is greater than or equal to voltage V4 and less than voltage V5. The threshold voltage at the "5" level is greater than or equal to voltage V5 and less than voltage V6. The threshold voltage at the "6" level is greater than or equal to voltage V6 and less than voltage V7. The threshold voltage at the "7" level is greater than or equal to voltage V7 and less than voltage V8. The threshold voltage at the "8" level is greater than or equal to voltage V8 and less than voltage V9. The threshold voltage at the "9" level is greater than or equal to voltage V9 and less than voltage VA. The threshold voltage at the "A" level is greater than or equal to voltage VA and less than voltage VB. The threshold voltage at the "B" level is greater than or equal to voltage VB and less than voltage VC. The threshold voltage at the “C” level is greater than or equal to voltage VC and less than voltage VD. The threshold voltage at the "D" level is greater than or equal to voltage VD and less than VE. The threshold voltage at the "E" level is greater than or equal to voltage VE and less than VF. The threshold voltage at the "F" level is greater than or equal to voltage VE and less than voltage VREAD.

In the read operation in this example, in order to simplify the explanation, the case where the verify voltage is used as the read voltage will be described as an example. Read operations using voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF are described below as read operations 1R, 2R, and 2R, respectively. It is written as 3R, 4R, 5R, 6R, 7R, 8R, 9R, AR, BR, CR, DR, ER, and FR. In the read operation 1R, it is determined whether the threshold voltage of the memory cell transistor MT is less than the voltage V1. In the read operation 2R, it is determined whether the threshold voltage of the memory cell transistor MT is less than the voltage V2. In the read operation 3R, it is determined whether the threshold voltage of the memory cell transistor MT is less than the voltage V3. The same applies hereafter.

Further, the above-mentioned 16 threshold value distributions are formed by writing 4-bit data consisting of a Lower bit, a Middle bit, an Upper bit, and a Top bit. Each of the 16 threshold distributions corresponds to different 4-bit data. In this embodiment, data is allocated to "Top bit/Upper bit/Middle bit/Lower bit" as shown below for memory cell transistors MT included in each level.

The memory cell transistor MT included in the "0" level holds "1111" data. The memory cell transistor MT included in the "1" level holds "1110" data. Memory cell transistor MT included in the "2" level holds "1010" data. The memory cell transistor MT included in the "3" level holds "1000" data. Memory cell transistor MT included in the "4" level holds "1001" data. The memory cell transistor MT included in the "5" level holds "0001" data. The memory cell transistor MT included in the "6" level holds "0000" data. The memory cell transistor MT included in the "7" level holds "0010" data. Memory cell transistor MT included in the "8" level holds "0110" data. The memory cell transistor MT included in the "9" level holds "0100" data. Memory cell transistor MT included in the “A” level holds “1100” data. Memory cell transistor MT included in the “B” level holds “1101” data. Memory cell transistor MT included in the “C” level holds “0101” data. The memory cell transistor MT included in the "D" level holds "0111" data. Memory cell transistor MT included in the "E" level holds "0011" data. Memory cell transistor MT included in the "F" level holds "1011" data.

When reading data allocated in this manner, the Lower bit is determined by read operations 1R, 4R, 6R, and BR. The Middle bit is determined by read operations 3R, 7R, 9R, and DR. The Upper bit is determined by read operations 2R, 8R, and ER. The Top bit is determined by read operations 5R, AR, CR, and FR. That is, the values of the Lower bit, Middle bit, Upper bit, and Top bit are determined by reading operations four times, four times, three times, and four times, respectively. In the following, this data allocation will be referred to as a "4-4-3-4 code."

1.3 Write Operation Next, the write operation will be explained. The write operation roughly includes a program operation and a verify operation. Then, by repeating the combination of the program operation and the program verify operation (hereinafter referred to as "program loop"), the threshold voltage of the memory cell transistor MT is raised to the target level.

The programming operation is an operation of increasing the threshold voltage by injecting electrons into the charge storage layer (or maintaining the threshold voltage by inhibiting injection).

The program verify operation is an operation that reads data after a program operation and determines whether the threshold voltage of the memory cell transistor MT has reached a target level.

1.3.1 First and Second Write Operations Next, the write operations of this embodiment will be described in detail. In this embodiment, the write operation of 4 page data corresponding to QLC is executed in two steps. Hereinafter, the write operation executed for the first time in a certain memory cell group MCG will be referred to as a "first write operation", and the write operation executed for the second time will be referred to as a "second write operation". The first write operation and the second write operation are each performed based on four pages of write data. In this embodiment, in the first write operation, 4 page data is roughly written, and in the second write operation, 4 page data is written precisely. Note that the write operation may be divided into three or more times. For example, 4 page data may be written in three parts.

First, the first write operation will be explained using FIG. 4. FIG. 4 shows changes in the threshold distribution of the memory cell transistor MT due to the first write operation.

As shown in FIG. 4, the sequencer 14 executes the first write operation based on the 4-page data input from the controller 20.

The threshold voltage of the memory cell transistor MT before performing the first write operation is distributed at the "ER" level. The threshold voltage at the "ER" level is less than the voltage V1 and corresponds to the erased state of the memory cell transistor MT.

In the first write operation, the sequencer 14 uses voltages VM1, VM2, VM3, VM4, VM5, VM6, VM7, VM8, VM9, VMA, VMB, VMC, VMD, VME, and VMF as verify voltages. The voltages VM1, VM2, VM3, VM4, VM5, VM6, VM7, VM8, VM9, VMA, VMB, VMC, VMD, VME, and VMF are each “1111” (“Lower bit/Middle bit/Upper bit/Top bit ”) data, “1110” data, “1010” data, “1000” data, “1001” data, “0001” data, “0000” data, “0010” data, “0110” data, “0100” data, “ It is used when writing data "1100", "1101", "0101", "0111", "0011", and "1011". Voltage VM1 is less than voltage V1. Voltage VM2 is greater than or equal to voltage V1 and less than voltage V2. Voltage VM3 is greater than or equal to voltage V2 and less than voltage V3. Voltage VM4 is greater than or equal to voltage V3 and less than voltage V4. Voltage VM5 is greater than or equal to voltage V4 and less than voltage V5. Voltage VM6 is greater than or equal to voltage V5 and less than voltage V6. Voltage VM7 is greater than or equal to voltage V6 and less than voltage V7. Voltage VM8 is greater than or equal to voltage V7 and less than voltage V8. Voltage VM9 is greater than or equal to voltage V8 and less than voltage V9. Voltage VMA is greater than or equal to voltage V9 and less than voltage VA. Voltage VMB is greater than or equal to voltage VA and less than voltage VB. Voltage VMC is greater than or equal to voltage VB and less than voltage VC. Voltage VMD is greater than or equal to voltage VC and less than voltage VD. Voltage VME is greater than or equal to voltage VD and less than voltage VE. Voltage VMF is greater than or equal to voltage VE and less than voltage VF.

When the first write operation is executed, the threshold voltage of the memory cell transistor MT increases based on the data to be written, and 16 threshold voltage distributions are formed. In the first write operation, as shown in FIG. 4, the 16 threshold distributions may overlap with adjacent threshold distributions. The "M0" level shown in FIG. 4 is formed by a plurality of memory cell transistors MT into which "1111" data is written. The "M1" level is formed by a plurality of memory cell transistors MT into which "1110" data is written. The "M2" level is formed by a plurality of memory cell transistors MT into which "1010" data is written. The "M3" level is formed by a plurality of memory cell transistors MT into which "1000" data is written. The "M4" level is formed by a plurality of memory cell transistors MT into which "1001" data is written. The "M5" level is formed by a plurality of memory cell transistors MT into which "0001" data is written. The "M6" level is formed by a plurality of memory cell transistors MT into which "0000" data is written. The "M7" level is formed by a plurality of memory cell transistors MT into which "0010" data is written. The "M8" level is formed by a plurality of memory cell transistors MT into which "0110" data is written. The "M9" level is formed by a plurality of memory cell transistors MT into which "0100" data is written. The "MA" level is formed by a plurality of memory cell transistors MT into which "1100" data is written. The "MB" level is formed by a plurality of memory cell transistors MT into which "1101" data is written. The "MC" level is formed by a plurality of memory cell transistors MT into which "0101" data is written. The “MD” level is formed by a plurality of memory cell transistors MT into which “0111” data is written. The "ME" level is formed by a plurality of memory cell transistors MT into which "0011" data is written. The "MF" level is formed by a plurality of memory cell transistors MT into which "1011" data is written.

The threshold voltage at the "M0" level is less than the voltage V1 and corresponds to the erased state of the memory cell transistor MT, similar to the "0" level and the "ER" level described above. In other words, in the memory cell transistor MT in which data 1111" is written in the first write operation, the increase in the threshold voltage is suppressed. However, the more the "M0" level changes to the "1" level due to the first write operation, the more However, the threshold voltage increases somewhat.The threshold voltage at the "M1" level is greater than or equal to the voltage VM1 and less than the voltage V2.The threshold voltage at the "M2" level is greater than or equal to the voltage VM2 and less than the voltage V3. The threshold voltage at the "M3" level is greater than or equal to the voltage VM3 and less than the voltage V4. The threshold voltage at the "M4" level is greater than or equal to the voltage VM4 and less than the voltage V5. The threshold voltage at the "M5" level is greater than or equal to the voltage VM5 and less than the voltage V4. The threshold voltage at the "M6" level is greater than or equal to the voltage VM6 and less than the voltage V7.The threshold voltage at the "M7" level is greater than or equal to the voltage VM7 and less than the voltage V8.The threshold voltage at the "M8" level The voltage is greater than or equal to the voltage VM8 and less than the voltage V9.The threshold voltage at the "M9" level is greater than or equal to the voltage VM9 and less than the voltage VA.The threshold voltage at the "MA" level is greater than or equal to the voltage VMA and less than the voltage VB. The threshold voltage at the "MB" level is greater than or equal to the voltage VMB and less than the voltage VC.The threshold voltage at the "MC" level is greater than or equal to the voltage VMC and less than the voltage VD.The threshold voltage at the "MD" level is greater than or equal to the voltage VMD. The threshold voltage at the "ME" level is greater than or equal to the voltage VME and less than the voltage VF. The threshold voltage at the "MF" level is greater than or equal to the voltage VMF and less than the voltage VREAD.

In this way, the voltages VM1, VM2, VM3, VM4, VM5, VM6, VM7, VM8, VM9, VMA, VMB, VMC, VMD, VME, and VMF used for the program verify operation in the first write operation are respectively: The threshold voltages of memory cell transistors MT that have passed verification are set so as not to exceed voltages V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, VF, and VREAD. Ru.

Next, the second write operation will be explained using FIG. 5. FIG. 5 shows a change in the threshold distribution of the memory cell transistor MT due to the second write operation.

As shown in FIG. 5, the sequencer 14 executes the second write operation based on the 4-page data.

In the second write operation, the sequencer 14 uses voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF as verify voltages. When the second write operation is executed, the threshold voltage of the memory cell transistor MT increases based on the data to be written, and 16 narrow threshold distributions are formed from the 16 wide threshold distributions. For example, the “0” level threshold distribution is formed from the “M0” level threshold distribution, the “1” level threshold distribution is formed from the “M1” level threshold distribution, and the “2” level threshold distribution is formed from the “M2” level threshold distribution. ``A threshold distribution of levels is formed. The same applies hereafter.

1.3.2 Write Data Conversion Process Next, the write data conversion process will be described using FIG. 6. In this embodiment, after performing the first write using data of 4 pages (Top page/Upper page/Middle page/Lower page), the data conversion circuit 27 converts the 4 page data into 2 page data and stores the data in the RAM 22. is stored in one page cluster CL. That is, the data conversion circuit 27 converts 4-bit (Top bit/Upper bit/Middle bit/Lower bit) data into 2-bit data. Hereinafter, the upper bits of the converted 2-bit data will be referred to as "X1 bits" and the lower bits will be referred to as "X2 bits." Further, a set of X1 bits is written as "X1 page", and a set of X2 bits is written as "X2 page".

As shown in FIG. 6, the data conversion circuit 27 converts 4-bit data into 2-bit (X1 bit/X2 bit) data.

More specifically, "1111" data at the "0" level is converted to "11" data. “1110” data at the “1” level is converted to “01” data. “1010” data at “2” level is converted to “00” data. “1000” data at “3” level is converted to “10” data. “1001” data of “4” level is converted to “11” data. “0001” data at the “5” level is converted to “01” data. “0000” data at the “6” level is converted to “00” data. “0010” data at the “7” level is converted to “10” data. “0110” data of “8” level is converted to “11” data. “0100” data at the “9” level is converted to “01” data. “1100” data of “A” level is converted to “00” data. “1101” data of “B” level is converted to “10” data. “0101” data of “C” level is converted to “11” data. “0111” data at “D” level is converted to “01” data. “0011” data at “E” level is converted to “00” data. “1011” data of “F” level is converted to “10” data.

That is, "11" data is assigned to the "0" level, "4" level, "8" level, and "C" level. “01” data is assigned to the “1” level, “5” level, “9” level, and “D” level. “00” data is assigned to the “2” level, “6” level, “A” level, and “E” level. “10” data is assigned to the “3” level, “7” level, “B” level, and “F” level. Then, the 2-bit data of adjacent levels (threshold distribution) are "11" data, "01" data, "00" from "0" level to "F" level, so that they become gray codes with 1 bit difference. data, and “10” data are repeatedly allocated.

1.3.3 Restoration Processing of Written Data Next, the restoration processing of written data will be explained using FIGS. 7 to 10. In this embodiment, the data restoration control circuit 19 extracts four pages (Top page/ Upper page/Middle page/Lower page) data is restored. Then, the sequencer 14 executes the second write operation using the restored 4-page data. Hereinafter, the read operation for restoring the 4-page data will be referred to as "internal data read operation." Note that, for example, data read by the internal data read operation is not sent to the controller 20 but to the data restoration control circuit 19.

As shown in FIG. 7, "11" (X1 bit/X2 bit) data corresponds to any of the "0" level, "4" level, "8" level, and "C" level. In the memory cell transistor MT after the first write operation, the threshold distributions corresponding to the "0" level, "4" level, "8" level, and "C" level are "M0" level, "M4" level, and "C" level, respectively. They are the "M8" level and the "MC" level. These four levels of threshold distributions are separated from each other and do not overlap. In order to distinguish between these four levels, the sequencer 14 performs an internal data read operation between the "M0" level, "M4" level, "M8" level, and "MC" level.

More specifically, for example, the sequencer 14 performs an internal data read operation three times using read voltages VS2, VS6, and VSA. The voltage VS2 is a voltage higher than the threshold distribution of the "M0" level and lower than the threshold distribution of the "M4" level, that is, a voltage higher than the voltage V1 and lower than the voltage VM4. Voltage VS6 is a voltage higher than the "M4" level threshold distribution and lower than the "M8" level threshold distribution, that is, higher than voltage V5 and lower than voltage VM8. Voltage VSA is a voltage higher than the threshold distribution of the "M8" level and lower than the threshold distribution of the "MC" level, that is, higher than the voltage V9 and lower than the voltage VMC.

Based on the result of the internal data read operation, the data restoration control circuit 19 restores 4-bit data of "0" level, "4" level, "8" level, and "C" level.

As shown in FIG. 8, "01" (X1 bit/X2 bit) data corresponds to one of the "1" level, "5" level, "9" level, and "D" level. In the memory cell transistor MT after the first write operation, the threshold distributions corresponding to the "1" level, "5" level, "9" level, and "D" level are "M1" level, "M5" level, and "D" level, respectively. They are "M9" level and "MD" level. In order to distinguish between these four levels, the sequencer 14 performs an internal data read operation between the "M1" level, "M5" level, "M9" level, and "MD" level.

More specifically, for example, the sequencer 14 performs an internal data read operation three times using read voltages VS3, VS7, and VSB. The voltage VS3 is a voltage higher than the threshold distribution of the "M1" level and lower than the threshold distribution of the "M5" level, that is, a voltage higher than the voltage V2 and lower than the voltage VM5. The voltage VS7 is a voltage higher than the threshold distribution of the "M5" level and lower than the threshold distribution of the "M9" level, that is, a voltage higher than the voltage V6 and lower than the voltage VM9. Voltage VSB is a voltage higher than the threshold distribution of the "M9" level and lower than the threshold distribution of the "MD" level, that is, higher than the voltage VA and lower than the voltage VMD.

Based on the result of the internal data read operation, the data restoration control circuit 19 restores 4-bit data of "1" level, "5" level, "9" level, and "D" level.

As shown in FIG. 9, "00" (X1 bit/X2 bit) data corresponds to one of the "2" level, "6" level, "A" level, and "E" level. In the memory cell transistor MT after the first write operation, the threshold distributions corresponding to the "2" level, "6" level, "A" level, and "E" level are "M2" level, "M6" level, and "M6" level, respectively. They are "MA" level and "ME" level. In order to distinguish between these four levels, the sequencer 14 performs internal data read operations between the "M2" level, the "M6" level, the "MA" level, and the "ME" level.

More specifically, for example, the sequencer 14 performs an internal data read operation three times using read voltages VS4, VS8, and VSC. The voltage VS4 is a voltage higher than the "M2" level threshold distribution and lower than the "M6" level threshold distribution, that is, higher than the voltage V3 and lower than the voltage VM6. Voltage VS8 is a voltage higher than the threshold distribution of the "M6" level and lower than the threshold distribution of the "MA" level, that is, higher than the voltage V7 and lower than the voltage VMA. Voltage VSC is a voltage higher than the threshold distribution of the "MA" level and lower than the threshold distribution of the "ME" level, that is, higher than the voltage VB and lower than the voltage VME.

Based on the result of the internal data read operation, the data restoration control circuit 19 restores 4-bit data of "2" level, "6" level, "A" level, and "E" level.

As shown in FIG. 10, "10" (X1 bit/X2 bit) data corresponds to one of the "3" level, "7" level, "B" level, and "F" level. In the memory cell transistor MT after the first write operation, the threshold distributions corresponding to the "3" level, "7" level, "B" level, and "F" level are "M3" level, "M7" level, and "F" level, respectively. They are the "MB" level and the "MF" level. In order to distinguish between these four levels, the sequencer 14 performs internal data read operations between the "M3" level, "M7" level, "MB" level, and "MF" level.

More specifically, for example, the sequencer 14 performs an internal data read operation three times using read voltages VS5, VS9, and VSD. Voltage VS5 is a voltage higher than the "M3" level threshold distribution and lower than the "M7" level threshold distribution, that is, higher than voltage V4 and lower than voltage VM7. Voltage VS9 is a voltage higher than the threshold distribution of the "M7" level and lower than the threshold distribution of the "MB" level, that is, higher than the voltage V8 and lower than the voltage VMB. Voltage VSD is a voltage higher than the threshold distribution of the "MB" level and lower than the threshold distribution of the "MF" level, that is, higher than the voltage VC and lower than the voltage VMF.

Based on the result of the internal data read operation, the data restoration control circuit 19 restores 4-bit data of "3" level, "7" level, "B" level, and "F" level.

In the examples shown in FIGS. 7 to 10, the internal data read operation is executed three times for each data of "11" data, "01" data, "00" data, and "10" data, that is, a total of 12 times. For example, some of the read voltages VS2 to VSD may be set to the same voltage value to reduce the number of internal data reads. For example, voltage VS2 and voltage VS3 are assumed to be the same voltage VS23. Voltage VS23 is higher than voltage V2 and lower than voltage VM4. Thereby, the "M0" level in "11" data and the "M1" level in "01" data may be distinguished at the same time. The same applies to other read voltages.

1.3.4 Overall flow of write operation Next, the overall flow of write operation will be explained using FIG. 11. Note that the example in FIG. 11 shows a write operation to one memory cell group MCG, and write operations to other memory cell groups MCG are omitted.

As shown in FIG. 11, the host device 30 transmits a write request for four pages to the controller 20 (step S10).

When the CPU 23 receives a write request from the host device 30, it transmits a first write operation command including four page (Top page/Upper page/Middle page/Lower page) data to the memory 10 (Step S11).

The sequencer 14 executes the first write operation based on the command from the controller 20 (step S12).

After transmitting the 4-page data to the memory 10, the data conversion circuit 27 converts the 4-page data into 2-page (X1 page/X2 page) data (step S13), and stores 2 pages in one page cluster CL in the RAM 22. Store data. More specifically, for example, X1 page data is stored in area PG0 of page cluster CL0, and X2 page data is stored in area PG1.

After data conversion, the CPU 23 transmits a second write operation command including 2 pages (X1 page/X2 page) data to the memory 10 (step S14). Note that step S14 may be executed after data conversion and after executing a first write operation to another memory cell group MCG (not shown).

The sequencer 14 executes an internal data read operation based on the command from the controller 20 (step S15).

The data restoration control circuit 19 restores 4 page (Top page/Upper page/Middle page/Lower page) data from the 2 page data and the read data (step S16).

The sequencer 14 executes a second write operation using the restored 4-bit data (step S17).

1.3.5 Command Sequence Next, the command sequence sent from the controller 20 to the semiconductor storage device will be described.

1.3.5.1 Command Sequence in First Write Operation First, the command sequence in the first write operation will be described using FIG. 12. FIG. 12 shows the input/output signal I/O and the ready/busy signal RBn input to the memory 10. The command CMD input to the memory 10 is stored in the command register 12, the address ADD is stored in the address register 13, and the data DAT is stored in the data register 17. Note that in the following description, the combination of commands corresponding to the first write operation will be referred to as a "first command set."

As shown in FIG. 12, first, the CPU 23 issues a command “0Dh” and transmits it to the memory 10. The command “0Dh” is a command for recognizing the first write operation.

Next, the CPU 23 issues a command “80h” and transmits it to the memory 10. Command “80h” is a command to notify a write operation.

Next, the CPU 23 successively transmits the Lower page address "ADD_L" and data "DAT_L" to the memory 10. The sequencer 14 holds the received data “DAT_L” in the latch circuit of the data register 17.

Next, the CPU 23 issues a command “1Ah” and transmits it to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_L” held in the data register 17 to the sense amplifier 18. When the transfer of the data "DAT_L" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_M" of the Middle page, the data "DAT_M", and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_M” held in the data register 17 to the sense amplifier 18. When the transfer of data "DAT_M" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_U" of the Upper page, the data "DAT_U", and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_U” held in the data register 17 to the sense amplifier 18. When the transfer of the data "DAT_U" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address of the top page "ADD_T", the data "DAT_T", and the command "10h" to the memory 10. Command “10h” is a command that instructs execution of a write operation.

When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_T” held in the data register 17 to the sense amplifier 18. Then, the sequencer 14 executes the first write operation based on the data “DAT_L”, “DAT_M”, “DAT_U”, and “DAT_T” stored in the sense amplifier 18.

Note that the order in which the Lower page data, Middle page data, Upper page data, and Top page data are transmitted from the controller 20 to the memory 10 can be set arbitrarily. For example, the controller 20 may first send the Top page data to the memory 10.

1.3.5.2 Command Sequence in Second Write Operation Next, two examples of command sequences in the second write operation will be described. Note that in the following description, the combination of commands corresponding to the second write operation will be referred to as a "second command set."

1.3.5.2.1 Command Sequence of First Example First, the command sequence of the first example in the second write operation will be described using FIG. 13.

As shown in FIG. 13, first, the CPU 23 issues a command “XXh” and transmits it to the memory 10. The command “XXh” is a command that instructs the memory 10 to restore data and perform a second write operation.

Next, the CPU 23 sequentially transmits the command “80h”, the address “ADD_X1” of the X1 page, the data “DAT_X1”, and the command “1Ah” to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X1” held in the data register 17 to the sense amplifier 18. When the transfer of the data "DAT_X1" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

Next, when the CPU 23 receives the "H" level ready-busy signal RBn, the CPU 23 sequentially stores the command "80h", the address "ADD_X2" of the X2 page, the data "DAT_X2", and the command "10h" into the memory 10. Send.

When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X2” held in the data register 17 to the sense amplifier 18. Thereafter, the sequencer 14 executes an internal data read operation. Next, the data restoration control circuit 19 restores 4 page data from the X1 page data, X2 page data, and read data, and transfers it to the sense amplifier 18. Next, the sequencer 14 executes a second write operation based on the 4 page data stored in the sense amplifier 18.

Note that the order in which the X1 page data and the X2 page data are transmitted from the controller 20 to the memory 10 can be set arbitrarily.

1.3.5.2.2 Second Example Command Sequence Next, a second example command sequence in the second write operation will be described using FIG. 14.

As shown in FIG. 14, the CPU 23 sequentially transmits the command “80h”, the address “ADD_X1”, the data “DAT_X1”, and the command “1Ah” to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X1” held in the data register 17 to the sense amplifier 18. When the transfer of the data "DAT_X1" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

Next, upon receiving the "H" level ready-busy signal RBn, the CPU 23 sequentially transmits the command "80h", the address "ADD_X2", the data "DAT_X2", and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X2” held in the data register 17 to the sense amplifier 18. When the transfer of the data "DAT_X2" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

Next, when the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "YYh", the command "00h", the address "ADD", and the command "30h" to the memory 10. Command “YYh” is a command for recognizing internal data read operation and data restoration operation. Command “00h” is a command for notifying a read operation. Command “30h” is a command for instructing execution of a read operation. When the command "30h" is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to "L" level, executes an internal data read operation and a data restoration operation by the data restoration control circuit 19, and restores the restored 4. The bit data is stored in the sense amplifier 18. When the storage of the 4-bit data in the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

Next, upon receiving the "H" level ready-busy signal RBn, the CPU 23 sequentially transmits the command "ZZh", the command "80h", the address "ADD_X1", and the command "10h" to the memory 10. The command “ZZh” is a command for recognizing the second write operation using 4-bit data stored in the sense amplifier 18. Therefore, in this case, data transfer from the controller 20 to the memory 10 is not necessary. When the command “10h” is stored in the command register 12, the sequencer 14 executes the second write operation using the 4-bit data stored in the sense amplifier 18.

Note that the order in which the X1 page data and the X2 page data are transmitted from the controller 20 to the memory 10 can be set arbitrarily.

1.3.6 Data Writing Order Next, the data writing order will be explained using FIG. 15. FIG. 15 shows the selection order of string units SU in one block BLK. One solid-line rectangular frame divided into two upper and lower stages by a broken line indicates one memory cell group MCG, and the upper stage of the square frame indicates the second write operation (reference code "WRT2"). The lower row shows the first write operation (reference code “WRT1”).

As shown in FIG. 15, first, the sequencer 14 executes a first write operation in which the word line WL0 is selected and the string units SU0 to SU3 are sequentially selected as the 0th to 3rd operations.

Next, as the fourth to seventh operations, the sequencer 14 executes a first write operation in which the word line WL1 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the eighth to eleventh operations, the sequencer 14 executes a second write operation in which the word line WL0 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the 12th to 15th operations, the sequencer 14 executes a first write operation in which the word line WL2 is selected and the string units SU0 to SU3 are selected in order.

Next, as the 16th to 19th operations, the sequencer 14 executes a second write operation in which the word line WL1 is selected and the string units SU0 to SU3 are sequentially selected.

That is, the sequencer 14 executes a first write operation in which word line WL(j+1) and string units SU0 to SU3 are selected in order, and then executes a second write operation in which word line WLj and string units SU0 to SU3 are selected in order. do. Next, the sequencer 14 selects word line WLj+2 and repeats the same operation.

As the 756th to 759th operations, the sequencer 14 executes a first write operation in which word line WL95 is selected and string units SU0 to SU3 are sequentially selected. Next, the sequencer 14 performs a second write operation in which the word line WL94 is selected and the string units SU0 to SU3 are sequentially selected as the 760th to 763rd operations, and as the 764th to 767th operations. , a second write operation in which word line WL95 is selected and string units SU0 to SU3 are sequentially selected, and the write operation in block BLK is completed.

The sequencer 14 executes the write operation in the above order based on the address ADD and data DAT sent from the controller 20.

When performing a write operation in the above write order, eight or more page clusters CL are provided in the RAM 22. For example, when performing the second write operation (eighth write operation) on the memory cell group MCG corresponding to word line WL0 and string unit SU0, the 0th to seventh write operations (first write operation) Eight page clusters CL are used to store in the RAM 22 two page data corresponding to each of the eight memory cell groups MCG that have executed the process.

1.3.7 Detailed flow of write operation indicating data write order Next, a detailed flow of write operation indicating data write order will be described using FIGS. 16 and 17. In the following description, in order to simplify the description, a variable j is used for the number of the word line WL, and a variable i is used for the number of the string unit SU. The variables i and j are variables held by counters included in the controller 20, for example, and are incremented under the control of the controller 20. The sequencer 14 executes a write operation based on the address ADD and data DAT received from the controller 20.

As shown in FIG. 16, first, when executing a write operation for one block BLK, the CPU 23 selects j=0, that is, word line WL0 (step S100), and further selects i=0, that is, string unit SU0 is selected (step S101). Then, the CPU 23 transmits the first command set to the memory 10.

Based on the first command set, the sequencer 14 selects the word line WL0 and string unit SU0 and executes the first write operation (step S102).

Next, after the first write operation is completed, the CPU 23 checks whether the variable i of the string unit SUi is i=3 (step S103).

If i is not 3 (step S103_No), the CPU 23 increments the variable i to i=i+1 (step S104), and transmits the first command set to the memory 10. Returning to step S102, the sequencer 14 executes the first write operation.

If i=3 (step S103_Yes), the CPU 23 checks whether the variable j of the word line WLj is j=0 (step S105).

If j=0 (step S105_Yes), the CPU 23 increments the variable j to make j=j+1 (step S106). Then, the CPU 23 returns to step S101, selects the variable i=0, and transmits the first command set to the memory 10.

If j is not 0 (step S105_No), the CPU 23 sets the variable j to j=j-1 and sets the variable i to i=0 (step S107). Then, the CPU 23 transmits the second command set to the memory 10.

The sequencer 14 first executes an internal data read operation based on the second command set (step S108).

The data restoration control circuit 19 restores the 4-page data based on the 2-page data of the second command set and the read data (step S109).

The sequencer 14 executes a second write operation using the restored 4-page data (step S110).

Next, after the second write operation is completed, the CPU 23 checks whether the variable i of the string unit SUi is i=3 (step S111).

If i is not 3 (step S111_No), the CPU 23 increments the variable i to i=i+1 (step S112), and transmits the second command set to the memory 10. Returning to step S108, the sequencer 14 executes an internal data read operation.

If i=3 (step S111_Yes), the CPU 23 checks whether the variable j of the word line WLj is j=94 (step S113).

As shown in FIG. 17, if j is not 94 (step S113_No), the CPU 23 increments the variable j to make i=j+2 (step S114). Then, the CPU 23 returns to step S101, selects the variable i=0, and transmits the first command set to the memory 10.

If j=94 (step S113_Yes), the CPU 23 sets the variable j to j=j+1 and sets the variable i to i=0 (step S115). Then, the CPU 23 transmits the second command set to the memory 10.

The sequencer 14 first executes an internal data read operation based on the second command set (step S116).

The data restoration control circuit 19 restores the 4-page data based on the 2-page data of the second command set and the read data (step S117).

The sequencer 14 executes a second write operation using the restored 4-page data (step S118).

Next, after the second write operation is completed, the CPU 23 checks whether the variable i of the string unit SUi is i=3 (step S119).

If i is not 3 (step S119_No), the CPU 23 increments the variable i to i=i+1 (step S120), and transmits the second command set to the memory 10. Returning to step S116, the sequencer 14 executes an internal data read operation.

If i=3 (step S119_Yes), the CPU 23 ends the write operation in the block BLK.

1.4 Effects of this Embodiment With the configuration of this embodiment, an increase in chip area can be suppressed. This effect will be explained in detail.

For example, the threshold voltage of a memory cell transistor MT to which data has been written may fluctuate due to disturb during a write operation to an adjacent memory cell transistor MT or a write operation to another string unit SU. be. For this reason, the write operation of 4 page data to one memory cell group MCG may be performed twice, a first write operation and a second write operation. In this case, it is necessary to hold four page data of the plurality of memory cell groups MCG in which the first write operation has been performed in the RAM of the controller, depending on the selection order of the memory cell groups MCG. For example, the first write is performed on four memory cell groups MCG corresponding to word line WLj and string units SU0 to SU3, and four memory cell groups MCG corresponding to word line WL(j+1) and string units SU0 to SU3. When performing a second write operation to the memory cell group MCG corresponding to the word line WLj and string unit SU0 after performing the operation, 4 page data of the 8 memory cell groups MCG, that is, 32 pages worth of data is stored in the RAM. need to be stored in. Further, for example, when there are eight string units SU, the RAM needs a storage capacity to store data for 64 pages. As described above, when the storage capacity of the RAM is increased depending on the number of string units SU, the selection order of memory cell groups MCG, etc., the chip area tends to increase.

In contrast, with the configuration according to this embodiment, the memory system 1 includes the data conversion circuit 27 in the controller 20 and the data restoration control circuit 19 in the memory 10. Thereby, the memory system 1 can convert 4 pages (bits) of data after the first write operation into 2 pages (bits) of data. Furthermore, the memory system 1 can restore the 4-page data using the converted 2-page data and the data after the first write operation read from the memory cell group MCG, and execute the second write operation. can. Thereby, the amount of data stored in the RAM 22 corresponding to one memory cell group MCG can be reduced from four pages to two pages. For example, the RAM storage capacity required for eight memory cell groups MCG can be reduced from 32 pages to 16 pages. Therefore, an increase in the chip area of the memory system 1 can be suppressed. Therefore, an increase in the manufacturing cost of the memory system 1 can be suppressed.

Furthermore, in the configuration according to this embodiment, when performing the second write operation, it is sufficient to transmit two pages of data from the controller 20 to the memory 10, so the amount of data transferred can be reduced from four pages to two pages. Therefore, the time required to transfer data from the controller 20 to the memory 10 can be reduced.

Furthermore, with the configuration according to this embodiment, data can be allocated so that the converted 2-bit data of adjacent threshold distributions of memory cell transistors MT becomes a Gray code. Therefore, even if erroneous reading or erroneous writing occurs, fluctuations in 2-bit data can be contained in 1 bit, so data reliability can be improved.

2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, a case will be described in which, when the power of the memory system 1 is cut off, 4 page data held by the controller 20 is converted into 2 page data and saved in the memory 10. Hereinafter, differences from the first embodiment will be mainly described.

2.1 Configuration of RAM First, the configuration of the RAM 22 will be explained using FIG. 18.

As shown in FIG. 18, the page cluster CL of the RAM 22 in this embodiment includes areas PG0 to PG3. In other words, each page cluster CL can hold four pages of data. Note that in this embodiment, similarly to the first embodiment, a case will be described in which eight page clusters CL0 to CL7 are provided.

2.2 Write Operation Next, the write operation will be explained. In this embodiment, the data write operation is different between the normal state and the power-off state. In the normal state, the controller 20 does not convert 4-page data to 2-page data. That is, 4 page data is transmitted from the controller 20 to the memory 10 also in the second write operation. Then, when the power is turned off, the controller 20 converts the 4 page data that has been subjected to the first write operation out of the 4 page data stored in the RAM 22 into 2 page data. Then, the controller 20 saves the data in the controller 20 into, for example, a management area of the memory cell array 11 (writes data into the management area) using the charge stored in the capacitive element of the memory system 1. A memory cell transistor MT used for saving data in the management area functions as an SLC (single level cell) that holds 1-bit (binary) data. Then, the sequencer 14 executes a 1-bit (binary) data write operation (hereinafter referred to as an SLC write operation) in order to shorten the write time. That is, a plurality of page data are written to different memory cell groups MCG.

2.3 Write Operation in Normal State Next, the write operation in normal state will be explained, focusing on the differences from the first embodiment.

2.3.1 Overall flow of write operation The overall flow of write operation in the normal state will be explained using FIG. 19. Note that the example in FIG. 19 shows a write operation to one memory cell group MCG, and write operations to other memory cell groups MCG are omitted.

As shown in FIG. 19, a first write operation is performed similarly to steps S10 to S12 described in FIG. 11 of the first embodiment.

The four page data are stored in areas PG0 to PG3 within one page cluster CL in the RAM 22, respectively. After the first write operation is completed, the CPU 23 transmits a second write operation command including 4 page data to the memory 10 (step S20).

The sequencer 14 executes the second write operation using 4-bit data, similar to step S17 in FIG. 11.

2.3.2 Command Sequence of Second Write Operation Next, the command sequence of the second write operation in the normal state will be explained using FIG. 20. Note that the command sequence for the first write operation is the same as that in FIG. 12 of the first embodiment.

As shown in FIG. 20, first, the CPU 23 sequentially transmits the command “80h”, the lower page address ADD_L, the data DAT_L, and the command “1Ah” to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data DAT_L held in the data register 17 to the sense amplifier 18. When the transfer of the data "DAT_L" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

Next, upon receiving the "H" level ready-busy signal RBn, the CPU 23 sequentially transmits the command "80h", the address ADD_M of the Middle page, the data DAT_M, and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data DAT_M held in the data register 17 to the sense amplifier 18. When the transfer of data "DAT_M" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to "H" level.

Next, upon receiving the "H" level ready-busy signal RBn, the CPU 23 sequentially transmits the command "80h", the address ADD_U of the Upper page, the data DAT_U, and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data DAT_U held in the data register 17 to the sense amplifier 18. When the transfer of the data "DAT_U" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

Next, upon receiving the "H" level ready-busy signal RBn, the CPU 23 sequentially transmits the command "80h", the address ADD_T of the top page, the data DAT_T, and the command "10h" to the memory 10.

When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data DAT_T held in the data register 17 to the sense amplifier 18. Then, the sequencer 14 executes the second write operation based on the data DAT_L, DAT_M, DAT_U, and DAT_T stored in the sense amplifier 18.

Note that the order in which the Lower page data, Middle page data, Upper page data, and Top page data are transmitted from the controller 20 to the memory 10 can be set arbitrarily.

2.3.3 Detailed flow of write operation indicating data write order Next, a detailed flow of write operation indicating data write order will be described using FIGS. 21 and 22.

As shown in FIGS. 21 and 22, the difference from the first embodiment shown in FIGS. 16 and 17 is that steps S108, S109, S116, and S117 are omitted. That is, in this embodiment, after receiving the second command set from the controller 20, the sequencer 14 executes the second write operation, omitting the internal data read operation and the data restoration operation.

2.4 Write operation in a power-off state Next, a write operation in a power-off state, that is, a data saving operation will be described.

2.4.1 Flow when power is cut off First, the flow when the power is cut off will be explained using FIG. 23.

As shown in FIG. 23, when the CPU 23 detects a power cutoff (step S30), the CPU 23 checks whether there is any data held in the RAM 22 for which the first write operation has not been performed in the memory 10 (step S30). S31).

If there is data for which the first write operation has not been performed (step S31_Yes), the CPU 23 transmits SLC write operation commands for each of the Lower page data, Middle page data, Upper page data, and Top page data to the memory 10 ( Step S32). The sequencer 14 executes the SLC write operation for each of the Lower page data, Middle page data, Upper page data, and Top page data based on the command from the controller 20 (Step S33). Note that the order in which the Lower page data, Middle page data, Upper page data, and Top page data are transmitted from the controller 20 to the memory 10 can be set arbitrarily.

When the SLC write operation in step S33 is completed, the process returns to step S31, and the CPU 23 again checks whether there is any data for which the first write operation has not been performed. The loop of steps S31 to S33 is repeated until there is no data for which the first write operation has not been performed.

If there is no data for which the first write operation has been performed (step S31_No), the CPU 23 checks whether there is any data for which the first write operation has been performed (step S34).

If there is data for which the first write operation has been executed (step S34_Yes), the data conversion circuit 27 converts the 4 page data in one page cluster CL of the RAM 22 into 2 page (X1 page/X2 page) data ( Step S35).

After data conversion, the CPU 23 transmits SLC write operation commands for each of the X1 page data and the X2 page data to the memory 10 (step S36). The sequencer 14 executes the SLC write operation for each of the X1 page data and the X2 page data based on the command from the controller 20 (step S37). Note that the order in which the X1 page data and the X2 page data are transmitted from the controller 20 to the memory 10 can be set arbitrarily.

When the SLC write operation in step S37 is completed, the process returns to step S34, and the CPU 23 checks again whether there is any data for which the first write operation has been performed. The loop of steps S34 to S37 is repeated until there is no more data for which the first write operation has been performed.

If there is no data for which the first write operation has been performed (step S34_No), the CPU 23 ends the data saving (step S38).

2.4.2 Command Sequence Next, the command sequence sent from the controller 20 to the semiconductor storage device will be described using FIG. 24. The example in FIG. 24 is a command sequence that instructs the SLC write operation of X1 page data and X2 page data. Note that in the following description, a combination of commands corresponding to an SLC write operation will be referred to as an "SLC command set." The example in FIG. 24 shows an SLC command set that instructs an SLC write operation of X1 page data, and an SLC command set that instructs an SLC write operation of X2 page data.

As shown in FIG. 24, first, the CPU 23 issues a command “A2h” and transmits it to the memory 10. Command “A2h” is a command for SLC recognition.

Next, the CPU 23 sequentially transmits the command “80h”, the address “ADD_S1” in the management area, the data “DAT_X1”, and the command “10h” to the memory 10. The combination of command “80h”, address “ADD_S1”, data “DAT_X1”, and command “10h” is one SLC command set.

When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X1” held in the data register 17 to the sense amplifier 18. Then, the sequencer 14 executes the SLC write operation based on the data "DAT_X1" stored in the sense amplifier 18. When the SLC write operation is completed, the sequencer 14 sets the ready-busy signal RBn to "H" level.

Next, when the CPU 23 receives the "H" level ready-busy signal RBn, it sends the command "A2h", the command "80h", the address "ADD_S2" in the management area, the data "DAT_X2", and the command "10h". are sent to the memory 10 in order. When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X2” held in the data register 17 to the sense amplifier 18. Then, the sequencer 14 executes the SLC write operation based on the data “DAT_X2” stored in the sense amplifier 18.

2.5 Flow when power is restored Next, two examples of the flow when power is restored will be explained.

2.5.1 Flow when power is restored in the first example First, the flow when the power is restored in the first example will be explained.

2.5.1.1 Overall flow when power is restored The overall flow when power is restored in the first example will be explained using FIG. 25. In the example of FIG. 25, the controller 20 reads X1 page data and X2 page data saved in the SLC in the management area of the memory cell array 11 page by page (hereinafter referred to as SLC read operation), and performs the second write operation. We will explain the case when executing.

As shown in FIG. 25, when the power is restored (step S40), the CPU 23 first transmits an SLC read operation command for X1 page data to the memory 10 (step S41). The sequencer 14 executes the SLC read operation of the X1 page data based on the command from the controller 20 (step S42).

After receiving the X1 page data from the memory 10, the CPU 23 transmits an SLC read operation command for the X2 page data to the memory 10 (step S43). The sequencer 14 executes the SLC read operation of the X2 page data based on the command from the controller 20 (step S44).

After receiving the X2 page data from the memory 10, the CPU 23 executes ECC processing on the X1 page data and the X2 page data in the ECC circuit 25 (step S45).

The CPU 23 transfers the ECC-processed X1 page data to the memory 10 (step S46). The sequencer 14 stores the X1 page data in the sense amplifier 18 (step S47).

The CPU 23 transfers the ECC-processed X2 page data to the memory 10 (step S48). The sequencer 14 stores the X2 page data in the sense amplifier 18 (step S49).

When the transfer of the X2 page data is completed, the CPU 23 transmits a data restoration command to the memory 10 (step S50).

The sequencer 14 executes an internal data read operation based on the command from the controller 20 (step S51). Then, the data restoration control circuit 19 restores 4-bit data from the 2-bit data and the read data (step S52).

When the restoration of the 4-bit data is completed, the CPU 23 transmits a second write operation command to the memory 10 (step S53).

The sequencer 14 executes the second write operation using the restored 4-bit data based on the command from the controller 20 (step S54).

2.5.1.2 Command Sequence Next, two examples of command sequences sent from the controller 20 to the semiconductor storage device will be described.

2.5.1.2.1 Command Sequence of First Example First, the command sequence of the first example will be described using FIG. 26.

As shown in FIG. 26, first, the CPU 23 sequentially transmits the command “A2h”, the command “00h”, the address “ADD_S1”, and the command “30h” to the memory 10. When the command “30h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level, executes the SLC read operation of the X1 page data, and holds the data “DAT_X1” in the data register 17. do. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the “H” level ready-busy signal RBn, the CPU 23 reads the data “DAT_X1” held in the data register 17 from the memory 10.

When the SLC read operation of the X1 page data is completed, the CPU 23 sequentially transmits the command “A2h”, the command “00h”, the address “ADD_S2”, and the command “30h” to the memory 10. When the command “30h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level, executes the SLC read operation of the X2 page data, and holds the data “DAT_X2” in the data register 17. do. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the “H” level ready-busy signal RBn, the CPU 23 reads the data “DAT_X2” held in the data register 17 from the memory 10.

When the ECC processing of the X1 page data and the X2 page data is completed, the CPU 23 sequentially transmits the command "80h", the address "ADD_X1", the data "DAT_X1", and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X1” held in the data register 17 to the sense amplifier 18. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_X2", the data "DAT_X2", and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X2” held in the data register 17 to the sense amplifier 18. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "YYh", the command "00h", the address "ADD", and the command "30h" to the memory 10. When the command "30h" is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to "L" level, executes an internal data read operation and a data restoration operation by the data restoration control circuit 19, and restores the restored 4. The bit data is stored in the sense amplifier 18. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "ZZh", the command "80h", the address "ADD_X1", and the command "10h" to the memory 10. Therefore, in this case, data transfer from the controller 20 to the memory 10 is not necessary. When the command “10h” is stored in the command register 12, the sequencer 14 executes the second write operation using the 4-bit data stored in the sense amplifier 18.

2.5.1.2.2 Command Sequence of Second Example Next, the command sequence of the second example will be described using FIG. 27.

As shown in FIG. 27, the steps up to the ECC processing of X1 page data and X2 page data in the controller 20 are the same as in the first example shown in FIG. 26.

When the ECC processing is completed, the CPU 23 sequentially transmits the command “XXh”, the command “80h”, the address “ADD_X1”, the data “DAT_X1”, and the command “1Ah” to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X1” held in the data register 17 to the sense amplifier 18. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_X2", the data "DAT_X2", and the command "10h" to the memory 10.

When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X2” held in the data register 17 to the sense amplifier 18. Thereafter, the sequencer 14 executes an internal data read operation. Next, the data restoration control circuit 19 restores 4 page data from the X1 page data, X2 page data, and read data, and transfers it to the sense amplifier 18. Next, the sequencer 14 executes a second write operation based on the 4 page data stored in the sense amplifier 18.

Note that the order in which the X1 page data and the X2 page data are transmitted from the controller 20 to the memory 10 can be set arbitrarily.

2.5.2 Flow when power is restored in the second example Next, the overall flow when the power is restored in the second example will be described. In the second example, the ECC processing of the X1 page data and X2 page data in the first example is omitted.

2.5.2.1 Overall flow when power is restored First, the overall flow when power is restored in the second example will be explained using FIG. 28. As shown in FIG. 28, when the power is restored (step S40), the CPU 23 first transmits an internal data read operation command for the X1 page data to the memory 10 (step S60). The sequencer 14 executes an internal data read operation of the X1 page data based on the command from the controller 20, and stores the read data in the sense amplifier 18 (step S61).

When the internal data reading operation of the X1 page data in the memory 10 is completed, the CPU 23 transmits an internal data reading operation command of the X2 page data to the memory 10 (step S62). The sequencer 14 executes an internal data read operation of the X2 page data based on the command from the controller 20, and stores the read data in the sense amplifier 18 (step S63).

The subsequent operations are similar to steps S50 to S54 described in FIG. 25 of the first example.

2.5.2.2 Command Sequence Next, two examples of command sequences sent from the controller 20 to the semiconductor storage device will be described.

2.5.2.2.1 Command Sequence of First Example First, the command sequence of the first example will be described using FIG. 29.

As shown in FIG. 29, first, the CPU 23 sequentially transmits a command “AX1h”, a command “00h”, an address “ADD_S1”, and a command “30h” to the memory 10. The command “AX1h” is a command for recognizing the SLC internal data read operation of X1 page data. Command “00h” is a command for notifying a read operation. Command “30h” is a command for instructing execution of a read operation. When the command “30h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level, executes the SLC read operation of the X1 page data, and holds the data “DAT_X1” in the data register 17. do. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "AX2h", the command "00h", the address "ADD_S2", and the command "30h" to the memory 10. The command “AX2h” is a command for recognizing the SLC internal data read operation of X2 page data. When the command “30h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level, executes the SLC read operation of the X2 page data, and holds the data “DAT_X2” in the data register 17. do. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "YYh", the command "00h", the address "ADD", and the command "30h" to the memory 10. When the command "30h" is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to "L" level, executes an internal data read operation and a data restoration operation by the data restoration control circuit 19, and restores the restored 4. The bit data is stored in the sense amplifier 18. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "ZZh", the command "80h", the address "ADD_X1", and the command "10h" to the memory 10. In this case, data transfer from controller 20 to memory 10 is not necessary. When the command “10h” is stored in the command register 12, the sequencer 14 executes the second write operation using the 4-bit data stored in the sense amplifier 18.

2.5.2.2.2 Command Sequence of Second Example Next, the command sequence of the second example will be described using FIG. 30.

As shown in FIG. 30, the operations up to the SLC internal data reading operation of X1 page data and X2 page data in the memory 10 are the same as in the first example shown in FIG. 29.

When the SLC internal data reading operation is completed, the CPU 23 sequentially transmits the command “XXh”, the command “80h”, the address “ADD_X1”, and the command “10h” to the memory 10.

When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X2” held in the data register 17 to the sense amplifier 18. Thereafter, the sequencer 14 executes an internal data read operation. Next, the data restoration control circuit 19 restores 4 page data from the X1 page data, X2 page data, and read data, and transfers it to the sense amplifier 18. Next, the sequencer 14 executes a second write operation based on the 4 page data stored in the sense amplifier 18.

Note that the order in which the X1 page data and the X2 page data are transmitted from the controller 20 to the memory 10 can be set arbitrarily.

2.6 Detailed flow of SLC write operation Next, the detailed flow of SLC write operation will be explained using FIG. 31.

As shown in FIG. 31, when executing the SLC write operation to the block BLK corresponding to the SLC, the CPU 23 first selects j=0, that is, the word line WL0, and further selects i=0, that is, the string unit SU0. is selected (step S130). Then, the CPU 23 transmits the SLC command set to the memory 10.

Based on the SLC command set, the sequencer 14 selects the word line WL0 and string unit SU0 and executes the SLC write operation (step S131).

Next, after the SLC write operation is completed, the CPU 23 checks whether the variable i of the string unit SUi is i=3 (step S132).

If i is not 3 (step S132_No), the CPU 23 increments the variable i to i=i+1 (step S133), and transmits the SLC command set to the memory 10. Returning to step S131, the sequencer 14 executes the SLC write operation.

If i=3 (step S132_Yes), the CPU 23 checks whether the variable j of the word line WLj is j=95 (step S134).

If j is not 95 (step S134_No), the CPU 23 increments the variable j to make i=j+1 (step S135). Then, the CPU 23 returns to step S130, selects the variable i=0, and transmits the SLC command set to the memory 10.

If j=95 (step S134_Yes), the CPU 23 ends the SLC write operation in the target block BLK.

2.7 Effects of this Embodiment With the configuration of this embodiment, it is possible to suppress an increase in chip area. This effect will be explained in detail.

When a power interruption occurs, the memory system may save data stored in RAM using volatile memory to nonvolatile memory. In this case, data is written to the memory using charges stored in a capacitive element within the memory system. Therefore, as the number of pages of data stored in the RAM increases, the data transfer time becomes longer, so it is necessary to increase the capacity of the capacitive element accordingly, and the chip area tends to increase.

In contrast, with the configuration according to this embodiment, the memory system 1 includes the data conversion circuit 27 in the controller 20 and the data restoration control circuit 19 in the memory 10. As a result, when the memory system 1 enters the power-off state, it can convert the 4-page (bit) data after the first write operation into 2-page (bit) data and write it into the memory 10. Furthermore, the memory system 1 can restore the 4-page data using the converted 2-page data and the data after the first write operation read from the memory cell group MCG, and execute the second write operation. can. This makes it possible to reduce the amount of data written to the memory 10 in a power-off state. Therefore, an increase in the capacitance of the capacitive element can be suppressed, and an increase in the chip area of the memory system 1 can be suppressed. Therefore, an increase in the manufacturing cost of the memory system 1 can be suppressed.

Furthermore, in the configuration according to this embodiment, when performing the second write operation after power is restored, it is only necessary to send two pages of data from the controller 20 to the memory 10, so the amount of data transferred is reduced from four pages to two pages. can. Therefore, the time required to transfer data from the controller 20 to the memory 10 can be reduced.

Furthermore, with the configuration according to this embodiment, data can be allocated so that the converted 2-bit data becomes a Gray code for adjacent threshold distributions of memory cell transistors MT. Therefore, even if erroneous reading or erroneous writing occurs, fluctuations in 2-bit data can be contained in 1 bit, so data reliability can be improved.

Note that the first embodiment and the second embodiment may be combined. That is, 4-bit data may be converted to 2-bit data in both the normal state and the power-off state.

3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, a data writing order different from that in the first embodiment will be described. Hereinafter, differences from the first embodiment will be mainly explained.

3.1 Data Writing Order The data writing order will be explained using FIG. 32. FIG. 32 shows the selection order of string units SU in one block BLK.

As shown in FIG. 32, first, the sequencer 14 executes a first write operation in which the word line WL0 is selected and the string units SU0 to SU3 are sequentially selected as the 0th to 3rd operations.

Next, as the fourth and fifth operations, the sequencer 14 selects the string unit SU0 and executes a first write operation that selects the word line WL1 and a second write operation that selects the word line WL0. do. In addition, the sequencer 14 sequentially selects string units SU1 to SU3 as the sixth to eleventh operations, and selects the word line WL1 in the same procedure as the fourth and fifth operations. The first write operation and the second write operation in which word line WL0 is selected are performed alternately.

Next, as the 12th to 19th operations, the sequencer 14 performs a first write operation in which the word line WL2 is selected and a second write operation in which the word line WL1 is selected, similarly to the fourth to 11th operations. The write operation is executed in the order of string units SU0 to SU3.

That is, the sequencer 14 executes a first write operation in which word line WL(j+1) is selected and a second write operation in which word line WLj is selected in the order of string units SU0 to SU3.

As the 756th to 763rd operations, the sequencer 14 executes a first write operation in which word line WL95 is selected and a second write operation in which word line WL94 is selected in the order of string units SU0 to SU3.

Next, as the 764th to 767th operations, the sequencer 14 executes a second write operation in which word line WL95 is selected and string units SU0 to SU3 are selected in order, and the write operation in block BLK is completed. .

When performing a write operation in the above write order, the RAM 22 is provided with five or more page clusters CL. For example, when performing a second write operation (fifth write operation) on the memory cell group MCG corresponding to word line WL0 and string unit SU0, the 0th to fourth write operations (first write operation) Five page clusters CL are used to store in the RAM 22 two page data corresponding to each of the five memory cell groups MCG that have executed.

3.2 Effects of this embodiment The configuration of this embodiment can be applied to the first and second embodiments.

4. Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, three examples will be described regarding write operations when the memory 10 executes data conversion and restoration. Hereinafter, differences from the first embodiment will be mainly described.

4.1 First Example First, the write operation of the first example will be explained. In the first example, a case will be described in which two pages of data converted by the memory 10 are stored in the RAM 22.

4.1.1 Configuration of Memory System First, the overall configuration of the memory system 1 will be described using FIG. 33. Note that in the example of FIG. 33, some of the connections between the blocks are shown by arrow lines, but the connections between the blocks are not limited to this.

As shown in FIG. 33, the difference from the first embodiment shown in FIG. 1 is that the data conversion circuit 27 is omitted in the controller 20, and the memory 10 includes a data conversion/restoration control circuit 19B.

For example, if the memory cell transistor included in the memory 10 is a QLC (quad level cell) that holds 4-bit (16-value) data, the data conversion/restore control circuit 19B converts the 4-bit data corresponding to the QLC into 2 Convert to bit data. Further, the data conversion/restoration control circuit 19B restores 4-bit data corresponding to QLC by holding the 2-bit converted data and the data read from the memory cell array 11 in the data register 17 and performing arithmetic operations. Note that the data conversion/restoration control circuit 19B may be provided within the sequencer 14. Furthermore, the data conversion circuit and the data restoration control circuit may be provided separately. Furthermore, the number of bits of data converted by the data conversion/restoration control circuit 19B can be set arbitrarily.

4.1.2 Overall Flow of Write Operation Next, the overall flow of the write operation in the first example will be described using FIG. 34. Note that the example in FIG. 34 shows a write operation to one memory cell group MCG, and write operations to other memory cell groups MCG are omitted.

As shown in FIG. 34, a first write operation is performed similarly to steps S10 to S12 described in FIG. 11 of the first embodiment.

After performing the first write operation, the data conversion/restoration control circuit 19B converts the 4-page data into 2-page (X1 page/X2 page) data (step S70).

The converted X1 page data and X2 page data are sent to the controller 20 and stored in one page cluster CL in the RAM 22 (step S71).

Note that during the first write operation, the data conversion/restore control circuit 19B may execute data conversion, and the X1 page data and the X2 page data may be sent to the controller 20, and further, the X1 page data and The X2 page data may be stored in one page cluster CL within the RAM 22.

The operations after data storage are similar to steps S14 to S17 described in FIG. 11 of the first embodiment. The data conversion/restoration control circuit 19B restores 4 page (Top page/Upper page/Middle page/Lower page) data from the 2 page data and read data received from the controller 20. Note that after data storage, step S14 may be executed after performing the first write operation, data conversion, and data storage corresponding to another memory cell group MCG (not shown).

4.1.3 Command Sequence Next, two examples of command sequences sent from the controller 20 to the semiconductor storage device will be described.

4.1.3.1 Command Sequence of First Example First, the command sequence of the first example will be described using FIG. 35.

As shown in FIG. 35, the CPU 23 first sends the command “0Dh”, the command “80h”, the lower page address “ADD_L”, the data “DAT_L”, and the command “1Ah” to the memory 10. Send to. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_L” held in the data register 17 to the sense amplifier 18. After data transfer, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_M" of the Middle page, the data "DAT_M", and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_M” held in the data register 17 to the sense amplifier 18. After data transfer, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_U" of the Upper page, the data "DAT_U", and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_U” held in the data register 17 to the sense amplifier 18. After data transfer, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address of the top page "ADD_T", the data "DAT_T", and the command "10h" to the memory 10. When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_T” held in the data register 17 to the sense amplifier 18. The sequencer 14 executes the first write operation based on the data “DAT_L”, “DAT_M”, “DAT_U”, and “DAT_T” stored in the sense amplifier 18. After performing the first write operation, the data conversion/restore control circuit 19B converts the 4-page data into 2-page data. After conversion, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the “H” level ready-busy signal RBn, the CPU 23 reads the data “DAT_X1” and “DAT_X2” from the memory 10.

Note that the sequencer 14 may perform data conversion processing during the first write operation and output the data after data conversion.

Next, the second write operation will be explained.

After reading the data “DAT_X1” and “DAT_X2”, the CPU 23 reads the command “XXh”, the command “80h”, the address “ADD_X1” of the X1 page, the data “DAT_X1”, and the command “1Ah”. It is transmitted to the memory 10 in order. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X1” held in the data register 17 to the sense amplifier 18. After data transfer, the sequencer 14 sets the ready-busy signal RBn to "H" level.

Next, when the CPU 23 receives the "H" level ready-busy signal RBn, the CPU 23 sequentially stores the command "80h", the address "ADD_X2" of the X2 page, the data "DAT_X2", and the command "10h" in the memory 10. Send.

When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X2” held in the data register 17 to the sense amplifier 18. Thereafter, the sequencer 14 executes an internal data read operation. Next, the data restoration control circuit 19 restores 4 page data from the X1 page data, X2 page data, and read data, and transfers it to the sense amplifier 18. Next, the sequencer 14 executes a second write operation based on the 4 page data stored in the sense amplifier 18.

4.1.3.2 Command Sequence of Second Example Next, the command sequence of the second example will be described using FIG. 36.

As shown in FIG. 36, the process is the same as the first example shown in FIG. 35 until the CPU 23 reads out data "DAT_X1" and "DAT_X2" from the memory 10.

After reading the data “DAT_X1” and “DAT_X2”, the CPU 23 sequentially transmits the command “80h”, the address “ADD_X1” of the X1 page, the data “DAT_X1”, and the command “1Ah” to the memory 10. . When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X1” held in the data register 17 to the sense amplifier 18. After data transfer, the sequencer 14 sets the ready-busy signal RBn to "H" level.

Next, upon receiving the “H” level ready-busy signal RBn, the CPU 23 sequentially stores the command “80h”, the address “ADD_X2” of the X2 page, the data “DAT_X2”, and the command “1Ah” in the memory 10. Send. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_X2” held in the data register 17 to the sense amplifier 18. After data transfer, the sequencer 14 sets the ready-busy signal RBn to "H" level.

Next, when the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "YYh", the command "00h", the address "ADD", and the command "30h" to the memory 10. When the command "30h" is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to "L" level, executes an internal data read operation and a data restoration operation by the data restoration control circuit 19, and restores the restored 4. The bit data is stored in the sense amplifier 18. After storing the data, the sequencer 14 sets the ready-busy signal RBn to "H" level.

Next, upon receiving the "H" level ready-busy signal RBn, the CPU 23 sequentially transmits the command "ZZh", the command "80h", the address "ADD_X1", and the command "10h" to the memory 10. When the command “10h” is stored in the command register 12, the sequencer 14 executes the second write operation using the 4-bit data stored in the sense amplifier 18.

Note that the order in which the X1 page data and the X2 page data are transmitted from the controller 20 to the memory 10 can be set arbitrarily.

4.2 Second Example Next, a write operation in a second example will be described. In a second example, a case will be described in which two pages of data converted by the memory 10 are stored, for example, in the SLC of the management area of the memory cell array 11.

4.2.1 Configuration of Memory System First, the overall configuration of the memory system of the second example will be explained. The overall configuration of the memory system 1 is the same as the first example shown in FIG. 33.

4.2.2 Overall Flow of Write Operation Next, the overall flow of the write operation in the second example will be described using FIG. 37. Note that the example in FIG. 37 shows a write operation to one memory cell group MCG, and write operations to other memory cell groups MCG are omitted.

As shown in FIG. 37, a first write operation is performed similarly to steps S10 to S12 described in FIG. 11 of the first embodiment.

After performing the first write operation, the data conversion/restoration control circuit 19B converts the 4-page data into 2-page (X1 page/X2 page) data (step S70).

The sequencer 14 executes the SLC write operation of the converted X1 page data and X2 page data, and stores the respective data, for example, in different memory cell groups MCG in the management area of the memory cell array 11 (step S72).

After completing the SLC write operation, the CPU 23 transmits a second write operation command to the memory 10 (step S73). At this time, 2-page data is not added to the second command set. Note that after the SLC write operation is completed, step S73 may be executed after performing the first write operation, data conversion, and SLC write operation corresponding to another memory cell group MCG (not shown).

Based on the command from the controller 20, the sequencer 14 first executes the SLC internal data read operation of the X1 page data and the X2 page data in the management area (step S74), and then reads the memory in which the first write operation was performed. An internal data read operation of cell group MCG is executed (step S15).

The data conversion/restoration control circuit 19B restores four page (Top page/Upper page/Middle page/Lower page) data from the read data (step S16).

The sequencer 14 executes a second write operation using the restored 4-bit data (step S17).

4.2.3 Command Sequence Next, the command sequence sent from the controller 20 to the semiconductor storage device will be described using FIG. 38.

As shown in FIG. 38, the CPU 23 transmits the same first command set as in the first example to the memory 10. Upon receiving the first command set, the sequencer 14 executes the first write operation, causes the data conversion/restore control circuit 19B to execute the data conversion, and then executes the SLC write operation of the converted data. Note that the sequencer 14 may cause the data conversion/restoration control circuit 19B to execute data conversion, and after executing the SLC write operation of the converted data, execute the first write operation.

After the SLC write operation is completed, the CPU 23 sequentially transmits the command “AAh”, the command “80h”, the address “ADD_X1”, and the command “10h” to the memory 10. The command “AAh” is a command for data restoration and second write operation recognition. When the command "10h" is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to "L" level, performs an internal data read operation and a data restoration operation by the data conversion/restoration control circuit 19B, and then A second write operation is performed based on the restored 4-bit data.

4.3 Third Example Next, the write operation of the third example will be explained. In the third example, a command sequence in the case where the first write operation is executed after executing the SLC write operation of the converted data in the second example will be described. Hereinafter, the differences from the second example will be mainly explained.

4.3.1 Command Sequence The command sequence sent from the controller 20 to the semiconductor storage device will be explained using FIGS. 39 and 40.

As shown in FIG. 39, the CPU 23 first sends the command “0Dh”, the command “80h”, the lower page address “ADD_L”, the data “DAT_L”, and the command “1Ah” to the memory 10. Send to. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_L” held in the data register 17 to the sense amplifier 18. After data transfer, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_M" of the Middle page, the data "DAT_M", and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_M” held in the data register 17 to the sense amplifier 18. After data transfer, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_U" of the Upper page, the data "DAT_U", and the command "1Ah" to the memory 10. When the command “1Ah” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and transfers the data “DAT_U” held in the data register 17 to the sense amplifier 18. After data transfer, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address of the top page "ADD_T", the data "DAT_T", and the command "1Xh" to the memory 10. The command “1Xh” is a command to convert 4-page data to 2-page data. When the command “1Xh” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to the “L” level and transfers the data “DAT_T” held in the data register 17 to the sense amplifier 18. Then, the data conversion/restoration control circuit 19B converts the 4-page data into 2-page data. The converted 2-page data and the 4-page data input from the outside are held in the data register 17 and the sense amplifier 18. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_X1", and the command "10h" to the memory 10. When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and executes, for example, an SLC write operation of the data “DAT_X1” held in the data register 17. . After the SLC write operation, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD_X2", and the command "10h" to the memory 10. When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level and executes, for example, an SLC write operation of the data “DAT_X2” held in the data register 17. . After the SLC write operation, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD", and the command "10h" to the memory 10. When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to the “L” level and, for example, sets the data “DAT_L”, “DAT_M”, and “DAT_U” held in the data register 17 to the “L” level. ” and “DAT_T” data, the QLC first write operation is executed.

Next, for example, after performing a write operation on adjacent cells and other strings, a second write operation is performed on the memory cell transistor MT that has performed the first write operation.

The second write operation will be specifically explained.

As shown in FIG. 40, first, the CPU 23 sequentially transmits the command “AX1h”, the command “00h”, the address “ADD_X1”, and the command “30h” to the memory 10. When the command “30h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level, executes the SLC read operation of the X1 page data, and holds the data “DAT_X1” in the data register 17. do. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "AX2h", the command "00h", the address "ADD_X2", and the command "30h" to the memory 10. When the command “30h” is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to “L” level, executes the SLC read operation of the X2 page data, and holds the data “DAT_X2” in the data register 17. do. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "YYh", the command "00h", the address "ADD", and the command "30h" to the memory 10. When the command "30h" is stored in the command register 12, the sequencer 14 sets the ready-busy signal RBn to "L" level, executes an internal data read operation and a data restoration operation by the data conversion/restoration control circuit 19B, and restores the data. The resulting 4-bit data is stored in the sense amplifier 18. After that, the sequencer 14 sets the ready-busy signal RBn to "H" level.

When the CPU 23 receives the "H" level ready-busy signal RBn, it sequentially transmits the command "80h", the address "ADD", and the command "10h" to the memory 10. When the command “10h” is stored in the command register 12, the sequencer 14 executes the second write operation using the 4-bit data stored in the sense amplifier 18.

4.4 Effects of this Embodiment With the configuration of this embodiment, the same effects as the first embodiment can be obtained.

Furthermore, with the configuration of the second example according to the present embodiment, it is not necessary to store data after the first write operation is executed in the RAM 22, so that the storage capacity of the RAM 22 can be reduced.

5. Fifth embodiment
Next, a fifth embodiment will be described. In the fifth embodiment, an example of an SLC write operation and an SLC read operation will be described. Hereinafter, differences from the first to fourth embodiments will be mainly described.

5.1 Configuration of Memory System First, the configuration of the memory system 1 will be explained. In the memory system 1 according to this embodiment, the data conversion circuit 27 and data restoration control circuit 19 described in FIG. 1 of the first embodiment may be omitted. The other configurations are the same as those in FIG. 1 of the first embodiment.

5.2 Configuration of Memory Cell Array First, the configuration of the memory cell array 11 will be described using FIG. 41.

As shown in FIG. 41, the memory cell array 11 includes, for example, 20 QLC blocks BLK (QB0 to QB19) corresponding to QLC and 6 SLC blocks BLK (SB0 to SB5) corresponding to SLC. .

For example, when writing data to one QLC block QB, two corresponding SLC blocks SB are required. However, if the number of SLC blocks SB is increased, the effective storage capacity will be reduced, so the area of the SLC blocks SB may be limited. Therefore, the number of write/erase operations in SLC block SB tends to be greater than in QLC block QB.

5.3 SLC write operation corresponding to two write operations Next, an example of the SLC write operation corresponding to two write operations will be described using FIG. 42. In this example, data can be written twice to one memory cell group MCG corresponding to the SLC write operation.

In this embodiment, in the programming operation, the operation of increasing the threshold voltage is referred to as "0" writing. On the other hand, the operation of maintaining the threshold voltage is referred to as "writing "1". Hereinafter, data corresponding to "0" writing will be referred to as "0" data, and data corresponding to "1" writing will be referred to as "1" data.

As shown in FIG. 42, in the first write operation, data is written so that the threshold voltage of the memory cell transistor MT to be written increases from the "Er" level to the "A" level. If the verify voltage at this time is VfyA, the threshold voltage of the memory cell transistor MT at the "Er" level ("1" writing) is less than the voltage VfyA. The threshold voltage of the memory cell transistor MT at the “A” level (“0” writing) is equal to or higher than the voltage VfyA.

In the second write operation, data is written so that the threshold voltage of the memory cell transistor MT to be written rises to the "B" level. If the verify voltage at this time is VfyB, the threshold voltage ("1" writing) of the memory cell transistor MT at the "Er" level and the "A" level is less than the voltage VfyB. The threshold voltage of the memory cell transistor MT at the “B” level (“0” writing) is equal to or higher than the voltage VfyB.

When the second data is written, the first data cannot be read, but in this embodiment, the SLC data becomes unnecessary after the QLC second write operation is completed. Therefore, the second data is written to the memory cell group MCG in which the first data is no longer needed.

5.4 Data writing order corresponding to two write operations Next, two examples will be described regarding the data write order corresponding to two write operations.

5.4.1 First Example First, the first example will be described using FIG. 43. FIG. 43 shows the selection order of string units SU in one block BLK. One solid rectangular frame divided into two upper and lower stages by a broken line indicates one memory cell group MCG, the upper stage of the square frame indicates the second write operation, and the lower stage of the square frame indicates the first write operation. This shows the write operation.

As shown in FIG. 43, the sequencer 14 first performs a first write operation in which the word line WL0 is selected and the string units SU0 to SU3 are sequentially selected as the 0th to 3rd operations.

Next, as the fourth to seventh operations, the sequencer 14 executes a second write operation in which the word line WL0 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the eighth to eleventh operations, the sequencer 14 executes the first write operation in which the word line WL1 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the 12th to 15th operations, the sequencer 14 executes a second write operation in which the word line WL1 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the 16th to 19th operations, the sequencer 14 executes the first write operation in which the word line WL2 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the 20th to 23rd operations, the sequencer 14 executes a second write operation in which the word line WL2 is selected and the string units SU0 to SU3 are sequentially selected.

That is, the sequencer 14 executes a first write operation in which word line WLj and string units SU0 to SU3 are selected in order, and then executes a second write operation in which word line WLj and string units SU0 to SU3 are selected in order. . Next, the sequencer 14 selects word line WL(j+1) and repeats the same operation.

As the 752nd to 755th operations, the sequencer 14 executes the first write operation in which the word line WL94 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the 756th to 759th operations, the sequencer 14 executes a second write operation in which the word line WL94 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the 760th to 763rd operations, the sequencer 14 executes a first write operation in which the word line WL95 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the 764th to 767th operations, the sequencer 14 executes a second write operation in which word line WL95 is selected and string units SU0 to SU3 are selected in order, and the write operation in block BLK is performed. finish.

The sequencer 14 executes the write operation in the above order based on the address ADD and data DAT sent from the controller 20.

After the first write and before the second write, perform an erase operation on the cell to which the first data has been written, or perform a weak erase operation to slightly change the threshold level to the erase side. You may do so. In this case, an erase operation or a weak erase operation may be performed for each word line WL.

5.4.2 Second Example Next, a second example will be described using FIG. 44. FIG. 44 shows the selection order of string units SU in one block BLK.

As shown in FIG. 44, the sequencer 14 first performs a first write operation in which the word line WL0 is selected and the string units SU0 to SU3 are sequentially selected as the 0th to 3rd operations.

Next, as the fourth to seventh operations, the sequencer 14 executes the first write operation in which the word line WL1 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the eighth to eleventh operations, the sequencer 14 executes the first write operation in which the word line WL2 is selected and the string units SU0 to SU3 are sequentially selected.

That is, the sequencer 14 executes the first write operation in which the word line WLj and the string units SU0 to SU3 are sequentially selected, and then selects the word line WL(j+1) and repeats the same operation.

As the 376th to 379th operations, the sequencer 14 executes the first write operation in which the word line WL94 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the 380th to 383rd operations, the sequencer 14 executes the first write operation in which the word line WL95 is selected and the string units SU0 to SU3 are sequentially selected.

When the first write operation is completed in each memory cell group MCG corresponding to word lines WL0 to WL95, the sequencer 14 executes a second write operation in each memory cell group MCG corresponding to word lines WL0 to WL95. do.

More specifically, as the 384th to 387th operations, the sequencer 14 executes a second write operation in which the word line WL0 is selected and the string units SU0 to SU3 are sequentially selected.

Next, the sequencer 14 executes a second write operation in which the word line WL1 is selected and the string units SU0 to SU3 are sequentially selected as the 388th to 391st operations.

Next, as the 392nd to 395th operations, the sequencer 14 executes a second write operation in which the word line WL1 is selected and the string units SU0 to SU3 are sequentially selected.

That is, the sequencer 14 executes the second write operation in which the word line WLj and the string units SU0 to SU3 are sequentially selected, and then selects the word line WL(j+1) and repeats the same operation.

As the 760th to 763rd operations, the sequencer 14 executes a second write operation in which the word line WL94 is selected and the string units SU0 to SU3 are sequentially selected.

Next, as the 764th to 767th operations, the sequencer 14 executes a second write operation in which word line WL95 is selected and string units SU0 to SU3 are selected in order, and the write operation in block BLK is performed. finish.

The sequencer 14 executes the write operation in the above order based on the address ADD and data DAT sent from the controller 20.

Note that in this example, after the first write operation is performed on each memory cell group MCG corresponding to word lines WL0 to WL95, the second write operation is performed. For this reason, when writing "1" data in the second write operation, there is a possibility that the boost efficiency of the channel of the memory cell transistor MT will decrease. In this case, the voltage value of the voltage Vpass in the second write operation may be higher than the voltage value in the first write operation.

Further, the voltage values of the selected word line WL and the selected gate line SGD may be different between the first writing and the second writing.

In addition, after the first write and before the second write, perform an erase operation on the cell to which the first data has been written, or perform a weak erase operation to slightly change the threshold level to the erase side. You may do so. In this case, the erase operation or weak erase operation may be performed on a block-by-block basis.

Furthermore, in the first and second examples, the sequencer 14 sequentially selected the string units SU0 to SU3 corresponding to one word line WL and executed the write operation, but the sequencer 14 selected one string unit SU and executed the write operation on the word line WL. A write operation may be performed in which WL0 to WL95 are selected in order, and then another string unit SU may be selected and the same operation may be repeated.

Furthermore, in the first and second examples, the sequencer 14 executed the write operation based on the address ADD and data DAT transmitted from the controller 20, but when the second write operation was performed, A command may be issued indicating that a write operation is to be performed. The controller 20 may have a table for managing the write state and issue commands based on information in this table. In this case, the controller 20 may perform a pseudo erase operation by updating the information in the table after the first write operation is completed for a certain block BLK and before performing the second write operation. good. This pseudo erasing operation does not need to be notified from the controller 20 to the memory 10, and may be processed within the controller 20.

5.5 SLC read operation corresponding to two write operations Next, an example of the SLC read operation corresponding to two write operations will be described using FIG. 45. The example in FIG. 45 describes a case where the written data includes a flag cell for distinguishing between the first data and the second data. Note that in order to ensure reliability, there may be a plurality of flag cells. In this case, the flag cell may be written as a result of majority vote or when the number of "0"s is written in a predetermined value or more. Alternatively, the flag cell may not be provided, and the controller 20 may distinguish between the first data and the second data and issue different read commands. In this case, for example, before the second data write operation, an "A" level read operation is performed, and after the second data write operation, a "B" level read operation is performed.

As shown in FIG. 45, upon receiving the SLC read command (step S300), the sequencer 14 executes the "A" level read operation (step S301). That is, the sequencer 14 executes the SLC read operation corresponding to the voltage VfyA.

If there is no writing to the flag cell in the data resulting from the "A" level read operation (hereinafter referred to as "A" level data) (step S302_No), the sequencer 14 outputs "A" level data (step S303). .

Further, if the flag cell is written in the "A" level data (step S302_Yes), the sequencer 14 executes the "B" level read operation (step S304). That is, the sequencer 14 executes the SLC read operation corresponding to the voltage VfyB.

When the "B" level read operation is completed, the sequencer 14 outputs "B" level data (step S305).

5.6 Example of four write operations Next, in this example, three SLC write operations and SLC read operations are performed when data is written four times to one memory cell group MCG corresponding to the SLC write operation. Explain an example.

5.6.1 First example 5.6.1.1 SCL write operation corresponding to four write operations First, an example of the SLC write operation corresponding to four write operations will be explained using FIGS. 46 and 47. I will explain. FIG. 46 is a diagram showing the threshold distribution of write data in the first to fourth write operations. FIG. 47 is a diagram showing the threshold value distribution of flag cells in the first to fourth write operations. In this example, data with different threshold distributions corresponding to the first to fourth write operations are written into one flag cell, for example.

As shown in FIG. 46, the process up to the second write operation is the same as that in FIG.

In the third write operation, data is written so that the threshold voltage of the memory cell transistor MT to be written rises to the "C" level. If the verify voltage at this time is VfyC, then the threshold voltage ("1" writing) of the memory cell transistor MT at the "Er" level to "B" level is less than the voltage VfyC. The threshold voltage of the memory cell transistor MT at the “C” level (“0” writing) is equal to or higher than the voltage VfyC.

In the fourth write operation, data is written so that the threshold voltage of the memory cell transistor MT to be written rises to the "D" level. Assuming that the verify voltage at this time is VfyD, the threshold voltage (“1” writing) of the memory cell transistor MT at the “Er” level to “C” level is less than the voltage VfyD. The threshold voltage of the memory cell transistor MT at the “D” level (“0” writing) is equal to or higher than the voltage VfyD.

After the first write and before the second write, perform an erase operation on the cell to which the first data has been written, or perform a weak erase operation to slightly change the threshold level to the erase side. You may do so. In addition, after the second write and before the third write, perform an erase operation on the cell to which the second data has been written, or perform a weak erase operation to slightly change the threshold level to the erase side. You may do so. Furthermore, after the third write and before the fourth write, perform an erase operation on the cell to which the third data has been written, or perform a weak erase operation to slightly change the threshold level to the erase side. You may do so.

Next, the threshold distribution of flag cells corresponding to the first to fourth write operations will be explained.

As shown in FIG. 47, after the first write operation, the threshold distribution of the flag cells is set to the "Er" level. After the second write operation, the threshold distribution of the flag cells is set to the "A" level. After the third write operation, the threshold distribution of the flag cells is set to the "B" level. After the fourth write operation, the threshold distribution of the flag cells is set to the "C" level.

5.6.1.2 SCL read operation corresponding to four write operations Next, the SCL read operation corresponding to four write operations will be described using FIG. 48. FIG. 48 shows a flowchart of the read operation.

As shown in FIG. 48, upon receiving the SLC read command (step S300), the sequencer 14 executes the "A" level read operation (step S310). That is, the sequencer 14 executes the SLC read operation corresponding to the voltage VfyA.

In the "A" level read operation, if the flag cell is at the "Er" level (step S311_Yes), the sequencer 14 outputs "A" level data (step S312).

In the "A" level read operation, if the flag cell is not at the "Er" level (step S311_No), the sequencer 14 executes the "B" level read operation (step S313). That is, the sequencer 14 executes the SLC read operation corresponding to the voltage VfyB.

In the “B” level read operation, if the flag cell is at the “A” level (step S314_Yes), that is, in the “B” level read operation, if the threshold voltage of the flag cell is less than the voltage VfyB, the sequencer 14: "B" level data is output (step S315).

In the “B” level read operation, if the flag cell is not at the “A” level (step S311_No), that is, in the “B” level read operation, if the threshold voltage of the flag cell is equal to or higher than the voltage VfyB, the sequencer 14: A “C” level read operation is executed (step S316). That is, the sequencer 14 executes the SLC read operation corresponding to the voltage VfyC.

In the “C” level read operation, if the flag cell is at the “B” level (step S317_Yes), that is, in the “C” level read operation, if the threshold voltage of the flag cell is less than the voltage VfyC, the sequencer 14: "C" level data is output (step S318).

In the “C” level read operation, if the flag cell is not at the “B” level (step S317_No), that is, in the “C” level read operation, if the threshold voltage of the flag cell is equal to or higher than the voltage VfyC, the sequencer 14: A “D” level read operation is executed (step S319). That is, the sequencer 14 executes the SLC read operation corresponding to the voltage VfyD.

When the "D" level read operation is completed, the sequencer 14 outputs "D" level data (step S320).

5.6.2 Second Example 5.6.2.1 SCL Write Operation Corresponding to Four Write Operations Next, the SCL write operation of the second example will be described using FIG. 49. FIG. 49 is a diagram showing the threshold value distribution of flag cells in the first to fourth write operations. Hereinafter, the differences from the first example will be mainly explained.

The threshold distribution of write data in this example is the same as that in FIG. 46 of the first example.

Next, the threshold distribution of flag cells corresponding to the first to fourth write operations will be explained.

As shown in FIG. 49, after the first write operation, the threshold distribution of the flag cells is set to the "Er" level. After the second write operation, the threshold distribution of the flag cells is set to "B" level. After the third write operation, the threshold distribution of the flag cells is set to the "C" level. After the fourth write operation, the threshold distribution of the flag cells is set to the "D" level.

5.6.2.2 SCL read operation corresponding to four write operations Next, the SCL read operation corresponding to four write operations will be described using FIG. 50. FIG. 50 shows a flowchart of the read operation.

As shown in FIG. 50, upon receiving the SLC read command (step S300), the sequencer 14 first executes a "B" level read operation (step S330).

In the “B” level read operation, if the flag cell is at the “Er” level (step S311_Yes), the sequencer 14 executes the “A” level read operation (step S332).

When the "A" level read operation is completed, the sequencer 14 outputs "A" level data (step S333).

In the "B" level read operation, if the flag cell is not at the "Er" level (step S331_No), the sequencer 14 executes the "C" level read operation (step S334).

In the “C” level read operation, if the flag cell is at the “B” level (step S335_Yes), that is, in the “C” level read operation, if the threshold voltage of the flag cell is less than the voltage VfyC, the sequencer 14: "B" level data is output (step S336).

In the “C” level read operation, if the flag cell is not at the “B” level (step S335_No), that is, in the “C” level read operation, if the threshold voltage of the flag cell is equal to or higher than the voltage VfyC, the sequencer 14: A “D” level read operation is executed (step S337).

In the “D” level read operation, if the flag cell is at the “C” level (step S338_Yes), that is, in the “D” level read operation, if the threshold voltage of the flag cell is less than the voltage VfyD, the sequencer 14: "C" level data is output (step S339).

In the “D” level read operation, if the flag cell is not at the “C” level (step S338_No), that is, in the “D” level read operation, if the threshold voltage of the flag cell is equal to or higher than the voltage VfyD, the sequencer 14: "D" level data is output (step S340).

5.6.3 Third Example 5.6.3.1 SCL Write Operation Corresponding to Four Write Operations Next, the SCL write operation of the second example will be described. In this example, if the write data includes a B flag cell corresponding to the second write operation, a C flag cell corresponding to the third write operation, and a D flag cell corresponding to the fourth write data, This will be explained using FIGS. 51 to 53. FIG. 51 is a diagram showing the threshold value distribution of the B flag cell in the first to fourth write operations. FIG. 52 is a diagram showing the threshold distribution of C flag cells in the first to fourth write operations. FIG. 53 is a diagram showing the threshold distribution of D flag cells in the first to fourth write operations. Hereinafter, the differences from the first example and the second example will be mainly explained.

The threshold distribution of write data in this example is the same as that in FIG. 46 of the first example.

Next, the threshold distribution of the B to D flag cells corresponding to the first to fourth write operations will be explained.

As shown in FIG. 51, the threshold distribution of the B flag cell changes from the "Er" level to the "B" level in the second write operation. In the third and fourth write operations, the threshold distribution of the B flag cells is maintained at the "B" level. That is, the B flag cell is set to the "Er" level in the first write operation, and set to the "B" level in the second to fourth write operations.

As shown in FIG. 52, the threshold distribution of the C flag cell changes from the "Er" level to the "C" level in the third write operation. In the fourth write operation, the threshold distribution of the C flag cells is maintained at the "C" level. That is, the C flag cell is set to the "Er" level in the first and second write operations, and is set to the "C" level in the third and fourth write operations.

As shown in FIG. 53, the threshold distribution of the D flag cells changes from the "Er" level to the "D" level in the fourth write operation. That is, the D flag cell is set to the "Er" level in the first to third write operations, and is set to the "D" level in the fourth write operation.

5.6.3.2 SCL read operation corresponding to four write operations Next, the SCL read operation corresponding to four write operations will be described using FIG. 54. FIG. 54 shows a flowchart of the read operation.

As shown in FIG. 54, upon receiving the SLC read command (step S300), the sequencer 14 executes the "A" level read operation (step S350).

In the "A" level read operation, if the B flag cell is at the "Er" level (step S351_Yes), the sequencer 14 outputs "A" level data (step S352).

In the “A” level read operation, if the B flag cell is not at the “Er” level (step S311_No), that is, if the B flag cell is at the “B” level, the sequencer 14 checks the C flag cell (step S353). .

In the “A” level read operation, if the C flag cell is “Er” (step S353_Yes), the sequencer 14 executes the “B” level read operation (step S354).

When the "B" level read operation is completed, the sequencer 14 outputs "B" level data (step S355).

In the “A” level read operation, if the C flag cell is not at the “Er” level (step S353_No), that is, if the C flag cell is at the “C” level, the sequencer 14 checks the D flag cell (step S356). .

In the “A” level read operation, if the D flag cell is “Er” (step S356_Yes), the sequencer 14 executes the “C” level read operation (step S357).

When the "C" level read operation is completed, the sequencer 14 outputs "C" level data (step S358).

In the “A” level read operation, if the D flag cell is not at the “Er” level (step S356_No), that is, if the D flag cell is at the “D” level, the sequencer 14 executes the “D” level read operation. (Step S359).

When the "D" level read operation is completed, the sequencer 14 outputs "D" level data (step S360).

5.7 Effects of this Embodiment The configuration of this embodiment can be applied to the first to fourth embodiments.

Furthermore, with the configuration according to this embodiment, data can be written two or more times to one memory cell transistor MT corresponding to the SLC write operation, so the number of times data is erased in the SLC block can be reduced. For example, when writing 4-bit data to one QLC block, the number of write/erase cycles in the SLC block can be reduced. This makes it possible to increase the number of times that an SLC block can be written.

Note that in the example of four write operations, flag cells are used, but when distinguishing by command, the flag cells can be omitted.

For example, in the four write operations, the sequencer 14 performs the first write operation on each memory cell group MCG corresponding to the word lines WL0 to WL95, and then performs the second write operation in the same procedure. A second write operation and a fourth write operation may be performed.

In addition, when writing "1" data in the second and subsequent write operations, there is a possibility that the boost efficiency of the channel of the memory cell transistor MT will decrease. In this case, the voltage value of the voltage VPASS in the second write operation may be higher than the voltage value in the first write operation, and the voltage value of the voltage VPASS in the third write operation may be set higher than the voltage value in the second write operation. The voltage value of the voltage VPASS during the fourth write operation may be set higher than the voltage value during the third write operation.

Furthermore, when writing to a relatively high threshold level, there is a possibility that, for example, memory cell transistor MT at the "Er" level may be erroneously written to the "A" level. In contrast, in this embodiment, for example, in the fourth write operation, "0" data is set to the "D" level, and "1" data is set to the "C" level or lower. Therefore, this erroneous writing can be suppressed.

Further, the verify level in the second write operation is higher than the verify level in the first write operation. Therefore, the write voltage VPGM in the second write operation may be set to a higher voltage value than that in the first write operation. Similarly, the verify level in the third write operation is higher than the verify level in the second write operation. Therefore, the write voltage VPGM in the third write operation may be set to a higher voltage value than that in the second write operation. Furthermore, the verify level in the fourth write operation is higher than the verify level in the third write operation. Therefore, the write voltage VPGM in the fourth write operation may be set to a higher voltage value than that in the third write operation.

Further, the step-up voltage DVPGM of the write voltage may be different in the first to fourth write operations.

Further, the voltage values of the selected word line WL and the selected gate line SGD may be different in the first to fourth write operations.

Furthermore, in the four write operations, similarly to the first and second examples of the data write order corresponding to the two write operations, the sequencer 14 stores the string units SU0 to SU3 corresponding to one word line WL. may be selected in order to execute the write operation. Alternatively, a write operation may be performed in which one string unit SU is selected and word lines WL0 to WL95 are selected in order, and then another string unit SU may be selected and the same operation may be repeated.

Note that in this embodiment, a case has been described in which data is written two or four times to one memory cell transistor MT corresponding to the SLC write operation, but it is also possible to write data three times or five times or more. Good too.

In addition, the memory cell transistor MT is not limited to the SLC write operation, and is compatible with a 2-bit data write operation (hereinafter referred to as an MLC write operation) or a 3-bit data write operation (hereinafter referred to as a TLC write operation). Data may be written two or more times.

Furthermore, in a plurality of data write operations, an SLC write operation, an MLC write operation, and a TLC write operation may be combined. For example, the MLC write operation may be executed the first time, and the SLC write operation may be executed the second time and thereafter. Furthermore, for example, the SLC write operation may be executed the first time, and the MLC or TLC write operation may be executed the second time and thereafter.

6. Sixth Embodiment Next, a sixth embodiment will be described. In the sixth embodiment, a case will be described in which a negative voltage is used in write operation, read operation, and erase operation. Hereinafter, differences from the first embodiment will be mainly described.

6.1 Configuration First, the configuration of the memory system 1 will be explained. In the memory system 1 according to this embodiment, the data conversion circuit 27 and data restoration control circuit 19 described in FIG. 1 of the first embodiment are eliminated. The other configurations are the same as those in FIG. 1 of the first embodiment.

6.1.1 Configuration of Memory Cell Array Next, the configuration of the memory cell array 11 will be described using FIG. 55. Although the example in FIG. 55 shows block BLK0, the configurations of other blocks BLK are also the same.

As shown in FIG. 55, each NAND string NS includes, for example, 64 memory cell transistors MT0 to MT63, dummy memory cell transistors MTDS and MTDD, and selection transistors ST1 and ST2. Dummy memory cell transistors MTDS and MTDD have the same configuration as memory cell transistors MT0 to MT63, but are not used for writing data. Hereinafter, if the memory cell transistors MT0 to MT63 and dummy memory cell transistors MTDS and MTDD are not limited, they will be referred to as memory cell transistors MT.

Memory cell transistor MT is connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. More specifically, the current paths of dummy memory cell transistor MTDS, memory cell transistors MT0 to MT63, and dummy memory cell transistor MTDD are connected in series. The drain of the dummy memory cell transistor MTDD is connected to the source of the selection transistor ST1, and the source of the dummy memory cell transistor MTDS is connected to the drain of the selection transistor ST2.

The control gates of memory cell transistors MT0 to MT63 and dummy memory cell transistors MTDS and MTDD in block BLK are commonly connected to word lines WL0 to WL63, WLDS, and WLDD, respectively. Hereinafter, unless the word lines WL0 to WL63, WLDS, and WLDD are limited, they will be referred to as word lines WL.

In this embodiment, a case will be described in which the memory cell transistor MT is an MLC (multi level cell) capable of holding 2-bit data. The 2-bit data held by the MLC is expressed as "Lower bit" and "Upper bit" in order from the least significant bit. Further, a set of Lower bits held by the memory cell group MCG is referred to as a "Lower page", and a set of Upper bits is referred to as an "Upper page".

Note that the number of bits of data that the memory cell transistor MT can hold is not limited to 2 bits. This embodiment can be applied as long as the memory cell transistor MT can hold data of 1 bit or more.

6.1.2 Configuration of Row Decoder Next, the configuration of the row decoder 16 will be described using FIG. 56. In the following explanation, when the source and drain of a transistor are not limited, either the source or the drain of the transistor will be referred to as "one end of the transistor", and the other of the source or drain of the transistor will be referred to as "the other end of the transistor". It is written as "edge".

As shown in FIG. 56, the row decoder 16 includes row decoder units 16-0 to 16-n respectively associated with blocks BLK0 to BLKn. Note that although the example in FIG. 56 shows details of the row decoder unit 16-0, the other row decoder units 16-1 to 16-n have the same configuration.

The row decoder unit 16-0 includes a block decoder 40 and high voltage N-channel enhancement type (E type: positive threshold) MOS transistors 41 (41-0 to 41-63, 41-DS, and 41-DD), 42 ( 42-0 to 42-3), 43 (43-0 to 43-3), 44 (44-0 to 44-3), and 45 (45-0 to 45-3). All of the transistors 41 to 45 are of a high breakdown voltage type, and, for example, the impurity concentrations in their channel regions are the same, and their threshold voltages are also the same.

Block decoder 40 decodes block address BA. Then, according to the result, a voltage is applied to the signal line TG and the signal line RDECn to control the on/off states of the transistors 41 to 45.

For example, when writing, reading, or erasing data, if the block address BA matches the corresponding block BLK0, the block decoder 40 applies an "H" level voltage (voltage VRDEC) to the signal line TG. , applies an "L" level voltage (for example, ground voltage VSS) to signal line RDECn. On the other hand, if the block address BA does not match the corresponding block BLK0, the block decoder 40 applies a "L" level voltage (for example, ground voltage VSS) to the signal line TG, and applies an "H" level voltage to the signal line RDECn. A level voltage (voltage at which transistors 43 and 45 are turned on) is applied. The voltage VRDEC is a voltage for turning on the transistors 41, 42, and 44, and different voltage values are set depending on write operation, read operation, and erase operation. The voltage VRDEC is higher than the voltage applied from the driver circuit 15 to the transistors 41, 42, and 44 by at least the threshold voltages of the transistors 41, 42, and 44. For example, voltage VRDEC is applied from driver circuit 15 to block decoder 40 .

The transistors 41-0 to 41-63, 41-DS, and 41-DD function as switching elements that connect the driver circuit 15 and the word lines WL0 to WL63, WLDS, and WLDD of the corresponding block BLK, respectively. One ends of the transistors 41-0 to 41-63, 41-DS, and 41-DD are each connected to a corresponding word line WL. The other ends of the transistors 41-0 to 41-63, 41-DS, and 41-DD are connected to the driver circuit 15, respectively. The gates of the transistors 41-0 to 41-63, 41-DS, and 41-DD are commonly connected to the signal line TG.

The transistors 42-0 to 42-3 function as switching elements that connect the driver circuit 15 and the selection gate lines SGD0 to SGD3 of the corresponding block BLK, respectively. One ends of the transistors 42-0 to 42-3 are connected to corresponding selection gate lines SGD0 to SGD3. The other ends of the transistors 42-0 to 42-3 are connected to the driver circuit 15, respectively. The gates of transistors 42-0 to 42-3 are commonly connected to signal line TG.

The transistors 43-0 to 43-3 function as switching elements that connect, for example, the ground voltage (VSS) wiring or the power supply voltage (VDD) wiring and the selection gate lines SGD0 to SGD3 of the corresponding block BLK, respectively. One ends of the transistors 43-0 to 43-3 are connected to corresponding selection gate lines SGD0 to SGD3, respectively. The other ends of the transistors 43-0 to 43-3 are connected to the VSS wiring or the VDD wiring. The gates of transistors 43-0 to 43-3 are commonly connected to signal line RDECn.

The transistors 44-0 to 44-3 function as switching elements that connect the driver circuit 15 and the selection gate lines SGS0 to SGS3 of the corresponding block BLK, respectively. One ends of the transistors 44-0 to 44-3 are connected to corresponding selection gate lines SGS0 to SGS3, respectively. The other ends of the transistors 44-0 to 44-3 are connected to the driver circuit 15, respectively. The gates of transistors 44-0 to 44-3 are commonly connected to signal line TG.

The transistors 45-0 to 45-3 function as switching elements that connect, for example, the VSS wiring or the VDD wiring and the selection gate lines SGS0 to SGS3 of the corresponding block BLK, respectively. One ends of the transistors 45-0 to 45-3 are connected to corresponding selection gate lines SGS0 to SGS3, respectively. The other ends of the transistors 45-0 to 45-3 are connected to the VSS wiring or the VDD wiring. The gates of transistors 45-0 to 45-3 are commonly connected to signal line RDECn.

Note that in the example of FIG. 56, transistors 44-0 to 44-3 and 45-0 to 45-3 are provided corresponding to selection gate lines SGS0 to SGS3 provided for each string unit SU. shown, but is not limited to this. For example, similarly to the word line WL, in one block BLK, the gates of the selection transistors ST2 in each string unit SU may be commonly connected to one selection gate line SGS. In this case, one transistor 44 and one transistor 45 are provided in the row decoder unit 16-0 corresponding to one selection gate line SGS.

6.1.3 Configuration of Block Decoder Next, the configuration of the block decoder 40 will be described using FIG. 57.

As shown in FIG. 57, the block decoder 40 includes a NAND circuit 51, an inverter 52, a high voltage N-channel E type MOS transistor 53, a high voltage P channel E type MOS transistor 54, and a high voltage N channel depletion type (D type: The MOS transistor 55 has a negative threshold value.

The NAND circuit 51 performs a NAND operation on each bit of the block address BA. The output signal of NAND circuit 51 is transmitted to signal line RDECn.

Inverter 52 inverts the output of NAND circuit 51.

One end of the transistor 53 is connected to the output node of the inverter 52, the other end of the transistor 53 is connected to the signal line TG, and the signal BSTON is input to the gate of the transistor 53. Signal BSTON is a signal that is asserted (to "H" level) when the block decoder 40 takes in address information, and is provided by the sequencer 14, for example.

One end of the transistor 54 is connected to the signal line TG, the other end of the transistor 54 is connected to the back gate, and the signal line RDECn is connected to the gate of the transistor 54.

A voltage VRDEC is applied to one end of the transistor 55, the other end of the transistor 55 is connected to the other end of the transistor 54, and the gate of the transistor 55 is connected to the signal line TG.

In a write operation, a read operation, and an erase operation, when the block address BA matches the corresponding block BLK, the NAND circuit 51 outputs an "L" level signal. That is, the "L" level voltage of the signal line RDECn is applied. The inverter 52 inverts the output signal of the NAND circuit 51 and outputs an "H" level signal. The transistor 53 is turned on by receiving the "H" level signal BSTON. Furthermore, the transistors 54 and 55 are turned on, thereby applying the "H" level voltage VRDEC to the signal line TG.

On the other hand, if the block address BA does not match the corresponding block BLK, the NAND circuit 51 outputs an "H" level signal. That is, an "H" level voltage is applied to the signal line RDECn. Transistors 54 and 55 are turned off, and an "L" level voltage is applied to signal line TG.

6.1.4 Configuration of Data Register and Sense Amplifier Next, the configuration of the data register 17 and sense amplifier 18 will be explained using FIGS. 58 and 59.

As shown in FIG. 58, the sense amplifier 18 includes a plurality of sense amplifier units SAU provided for each bit line BL. The data register 17 includes a plurality of latch circuits XDL provided for each sense amplifier unit SAU.

Sense amplifier unit SAU includes, for example, a sense amplifier section SA, latch circuits SDL, ADL, and BDL. The latch circuit XDL, the sense amplifier section SA, and the latch circuits SDL, ADL, and BDL are connected to each other so as to be able to transmit and receive data.

During a read operation, the sense amplifier section SA senses the data read to the corresponding bit line BL and determines whether the read data is "0" or "1". Furthermore, during a write operation, the sense amplifier section SA applies a voltage to the bit line BL based on write data.

The latch circuits SDL, ADL, and BDL temporarily hold read data and write data. The read data determined by the sense amplifier unit SA during the read operation and the write data transferred to the latch circuit XDL during the write operation are transferred to, for example, one of the latch circuits SDL, ADL, and BDL.

The latch circuit XDL is used for data input/output between the sense amplifier unit SAU and the controller 20. That is, data received from the controller 20 is transferred to the latch circuit SDL, ADL, or BDL, or the sense amplifier section SA via the latch circuit XDL. Further, data in the latch circuit SDL, ADL, or BDL or the sense amplifier section SA is transferred to the controller 20 via the latch circuit XDL.

Note that the configuration of the sense amplifier unit SAU is not limited to this, and various changes are possible. For example, the number of latch circuits included in the sense amplifier unit SAU is designed based on the number of bits of data held by one memory cell transistor MT.

Next, the configuration of the sense amplifier section SA will be explained.

As shown in FIG. 59, sense amplifier section SA includes high voltage N-channel MOS transistors 60 to 62, low voltage P-channel MOS transistor 63, and level shifter 64.

A signal BLS is input to the gate of transistor 60. One end of the transistor 60 is connected to the corresponding bit line BL, and the other end of the transistor 60 is connected to the node SCOM. Transistor 60 functions as a clamp transistor that clamps the voltage on bit line BL according to signal BLC.

The gate of transistor 61 is connected to the output terminal of level shifter 64. One end of transistor 61 is connected to node SCOM, and the other end of transistor 61 is connected to node SRCGND. In this embodiment, for example, ground voltage VSS or negative voltage VBB (<0V) is applied to node SRCGND.

A signal BLX is input to the gate of the transistor 62. One end of transistor 62 is connected to node SCOM, and the other end of transistor 62 is connected to node SSRC.

The gate of transistor 63 is connected to node INV. Voltage VBIT is applied to one end of transistor 63, and the other end of transistor 63 is connected to node SSRC. Voltage VBIT is a power supply voltage supplied to the sense amplifier section SA, and for example, power supply voltage VDD is applied. Node INV is connected to latch circuit SDL. The latch circuit SDL holds the inverted data of the held data at the node INV.

An input terminal of level shifter 64 is connected to node INV. The level shifter 64 converts and outputs the voltage at the node INV according to the control of the sequencer 14. For example, when a negative voltage VBB is applied to the node SRCGND and an "L" level voltage (for example, voltage VSS) is applied to the node INV, the level shifter 64 applies the negative voltage to turn off the transistor 61. Output VBB.

6.1.5 Cross-sectional configuration of memory cell array and semiconductor substrate Next, the cross-sectional configuration of the memory cell array 11 and semiconductor substrate will be described using FIG. 60. Note that in the example of FIG. 60, the interlayer insulating film is omitted.

As shown in FIG. 60, near the surface of the P-type semiconductor substrate 70, N well regions 71a, 71b, 71c, and 71d and a P well region 72c are formed.

Memory cell array 11 is provided on N-well region 71a. A P well region 72a is formed near the surface of the N well region 71a, and an N+ diffusion layer 73 is formed in a part near the surface of the P well region 72a. Above the semiconductor substrate 70, a plurality of wiring layers functioning as a selection gate line SGS, word lines WLDS, WL0 to WL63, and WLDD, and a selection gate line SGD are formed from the bottom layer with an interlayer insulating film (not shown) interposed therebetween. A memory pillar MP is formed which is stacked, passes through these plurality of wiring layers, and whose bottom surface reaches the N+ diffusion layer 73. One memory pillar MP corresponds to one NAND string NS. An insulating layer 90 is formed on the side surface of the memory pillar MP, and a semiconductor layer 91 whose bottom surface is in contact with the N+ diffusion layer 73 is formed within the insulating layer 90. More specifically, as the insulating layer 90, an insulating layer functioning as a block insulating film, an insulating layer functioning as a charge storage layer, and an insulating layer functioning as a tunnel insulating film are laminated in order from the side surface of the memory pillar MP. .

A high voltage N-channel MOS transistor 76 (reference numeral "HV NMOS") used, for example, as the row decoder 16 and the sense amplifier 18 is formed in the N well region 71b. More specifically, a P well region 72b and an N+ diffusion layer 73 are formed near the surface of the N well region 71b. A transistor 76 is formed on the P well region 72b. Further, a P+ diffusion layer 74 is formed near the surface of the P well region 72b, and the P+ diffusion layer 74 is used, for example, when applying a voltage to the back gate of the transistor 76. Transistor 76 includes an N+ diffusion layer 73 that functions as a source and a drain, and a gate electrode 75.

In the P well region 72c, there are low voltage N-channel MOS transistors used in peripheral circuits (for example, command register 12, address register 13, sequencer 14, driver circuit 15, row decoder 16, data register 17, sense amplifier 18, etc.). 77 (reference numeral "LV NMOS") is formed. More specifically, a transistor 77 is formed on the P well region 72c. Further, a P+ diffusion layer 74 is formed near the surface of the P well region 72c, and the P+ diffusion layer 74 is used, for example, when applying a voltage to the back gate of the transistor 77. Transistor 77 includes an N+ diffusion layer 73 that functions as a source and a drain, and a gate electrode 75.

A low breakdown voltage P-channel MOS transistor 78 (reference numeral "LV PMOS") used in the peripheral circuit is formed in the N-well region 71c. More specifically, a transistor 78 is formed on the N well region 71c. Further, an N+ diffusion layer 73 is formed near the surface of the N well region 71c, and the N+ diffusion layer 73 is used, for example, when applying a voltage to the back gate of the transistor 78. Transistor 78 includes a P+ diffusion layer 74 that functions as a source and a drain, and a gate electrode 75.

A high-voltage P-channel MOS transistor 79 (reference numeral "HV PMOS") used, for example, as the row decoder 16 and the sense amplifier 18 is formed in the N-well region 71d. More specifically, a transistor 79 is formed on the N well region 71d. Further, an N+ diffusion layer 73 is formed near the surface of the N well region 71d. For example, the N+ diffusion layer 73 is used when applying a voltage to the back gate of the transistor 79. Transistor 79 includes a P+ diffusion layer 74 that functions as a source and a drain, and a gate electrode 75.

Note that the thicknesses of gate oxide films (not shown) of the transistors 76 to 79 may be different from each other.

6.2 Voltage of well region in erase operation, write operation, and read operation Next, FIG. Explain using.

As shown in FIG. 61, first, the voltage in the well region in the erase operation will be explained.

A voltage VERA is applied to the P well region 72a and the N well region 71a in which the memory cell array 11 is formed. Voltage VERA is a high voltage applied to the source line SL of the memory cell transistor MT when applying the erase pulse.

A negative voltage VBB is applied to the P well region 72b in which the high voltage N-channel MOS transistors 76 (for example, transistors 41 to 45) used for the row decoder 16 etc. are formed, and a voltage VSS is applied to the N well region 71b. be done.

Voltage VSS is applied to P-well region 72c in which low-voltage N-channel MOS transistor 77 used in the peripheral circuit is formed.

Voltage VDD is applied to N-well region 71c in which low-voltage P-channel MOS transistor 78 used in the peripheral circuit is formed.

A voltage VERAH or a voltage |-VthD| is applied to the N-well region 71d in which a high-voltage P-channel MOS transistor 79 (eg, transistor 54) used in the block decoder 40 and the like is formed. For example, in FIG. 56, voltage VERAH turns on a high voltage N-channel MOS transistor in order to transfer a predetermined voltage (voltage VERASGD, etc.) to word lines WLDD and WLDS, selection gate lines SGD and SGS, etc. It is voltage.

In block decoder 40 corresponding to selected block BLK, voltage VERAH is applied to N-well region 71d of high voltage P-channel MOS transistor 79 (for example, transistor 54). On the other hand, in the block decoder 40 corresponding to the non-selected block BLK, a voltage corresponding to the threshold voltage of the high voltage N-channel D-type MOS transistor 55 is applied to the N well region 71d of the high voltage P-channel MOS transistor 79 (for example, the transistor 54). |−VthD| is applied.

A voltage VSS is applied to the P-well region 72b and the N-well region 71b in which high-voltage N-channel MOS transistors 76 (for example, transistors 60, 61, and 62) used in the sense amplifier unit SAU and the like are formed.

Next, the voltage in the well region in the write operation will be explained. The write operation in this embodiment has two operation modes: a normal operation mode and a negative voltage operation mode, and the voltage of the well region differs depending on the operation mode. The operation mode will be explained in detail.

In the normal operation mode, a voltage VSS is applied to the P-well region 72a where the memory cell array 11 is formed, and in the negative voltage operation mode, a negative voltage VBB is applied. Alternatively, voltage VSS is applied to N-well region 71a.

In the normal operation mode, a voltage VSS is applied to the P well region 72b in which a high voltage N-channel MOS transistor 76 used for the row decoder 16 etc. is formed, and in the negative voltage operation mode, a negative voltage VBB is applied. be done. Furthermore, voltage VSS is applied to N-well region 71b.

Voltage VSS is applied to P-well region 72c in which low-voltage N-channel MOS transistor 77 used in the peripheral circuit is formed.

Voltage VDD is applied to N-well region 71c in which low-voltage P-channel MOS transistor 78 used in the peripheral circuit is formed.

A voltage VPGMH or a voltage |-VthD| is applied to the N-well region 71d in which a high voltage P-channel MOS transistor 79 (for example, the transistor 54) used for the block decoder 40 and the like is formed. For example, the voltage VPGMH is a voltage larger than the voltage VPGM, and in FIG. 56, a high withstand voltage This is the voltage that turns on the N-channel MOS transistor.

In block decoder 40 corresponding to selected block BLK, voltage VPGMH is applied to N-well region 71d of high voltage P-channel MOS transistor 79 (for example, transistor 54). On the other hand, in the block decoder 40 corresponding to the non-selected block BLK, a voltage corresponding to the threshold voltage of the high voltage N-channel D-type MOS transistor 55 is applied to the N well region 71d of the high voltage P-channel MOS transistor 79 (for example, the transistor 54). |−VthD| is applied.

In the normal operation mode, a voltage VSS is applied to the P well region 72b in which a high voltage N-channel MOS transistor 76 used in the sense amplifier unit SAU etc. is formed, and in the negative voltage operation mode, a negative voltage VBB is applied. applied. Furthermore, voltage VSS is applied to N-well region 71b.

Next, the voltage in the well region in the read operation will be explained.

A voltage VSS is applied to the P well region 72a and the N well region 71a in which the memory cell array 11 is formed.

A negative voltage VBB is applied to the P-well region 72b in which a high-voltage N-channel MOS transistor 76 used for the row decoder 16 and the like is formed, and a voltage VSS is applied to the N-well region 71b.

Voltage VSS is applied to P-well region 72c in which low-voltage N-channel MOS transistor 77 used in the peripheral circuit is formed.

Voltage VDD is applied to N-well region 71c in which low-voltage P-channel MOS transistor 78 used in the peripheral circuit is formed.

A voltage VREADH or a voltage |-VthD| is applied to the N-well region 71d in which a high voltage P-channel MOS transistor 79 (for example, the transistor 54) used for the block decoder 40 and the like is formed. For example, the voltage VREADH is a voltage larger than the voltage VREAD, and in FIG. This is the voltage that turns on the N-channel MOS transistor.

In block decoder 40 corresponding to selected block BLK, voltage VREADH is applied to N-well region 71d of high voltage P-channel MOS transistor 79 (for example, transistor 54). On the other hand, in the block decoder 40 corresponding to the non-selected block BLK, a voltage corresponding to the threshold voltage of the high voltage N-channel D-type MOS transistor 55 is applied to the N well region 71d of the high voltage P-channel MOS transistor 79 (for example, the transistor 54). |−VthD| is applied.

A voltage VSS is applied to the P well region 72b and the N well region 71b in which a high voltage N-channel MOS transistor 76 used for the sense amplifier unit SAU and the like is formed.

6.3 Threshold Distribution of Memory Cell Transistor MT Next, the threshold distribution of memory cell transistor MT will be explained using FIG. 62.

As shown in FIG. 62, when the memory cell transistor MT holds 2-bit data, its threshold voltage distribution is divided into four. These four threshold voltage distributions are expressed as "Er" level, "A" level, "B" level, and "C" level in descending order of threshold voltage. In this embodiment, threshold distributions of "Er" level and "A" level are provided on the negative voltage side, and threshold distributions of "B" level and "C" level are provided on the positive voltage side. The read level voltages corresponding to the "A" level, "B" level, and "C" level are VRA, VRB, and VRC, respectively. Further, verify level voltages corresponding to the "A" level, "B" level, and "C" level are VA, VB, and VC, respectively. Voltages VRA and VA are negative voltages, for example, higher voltages than negative voltage VBB. Voltages VRB and VB are near 0V. Voltages VRC and VC are positive voltages. The relationship between voltages VRA to VRC, VA to VC, and VREAD is VRA<VA<VRB<VB<VRC<VC<VREAD.

6.4 Read Operation The read operation will be explained. In this embodiment, a case will be described in which, for example, two page data, that is, the "Er" level to "A" level are read out at once.

Next, the voltage of the word line WL during the read operation will be explained using FIG. 63.

As shown in FIG. 63, when performing an "A" level read operation during the period from time t0 to t1, voltage VREAD is applied to the unselected word line WL, and a negative voltage VREAD is applied to the selected word line WL. VRA is applied. At this time, memory cell transistor MT holding data at "Er" level is turned on, and memory cell transistor MT holding data at level "A" to "C" is turned off.

When performing a "B" level read operation during the period from time t1 to t2, voltage VREAD is applied to the unselected word line WL, and voltage VRB is applied to the selected word line WL. At this time, memory cell transistors MT that hold data at the "Er" level and "A" level are turned on, and memory cell transistors MT that hold data at the "B" and "C" levels are turned off. Ru.

When performing a "C" level read operation during the period from time t2 to t3, voltage VREAD is applied to the unselected word line WL, and voltage VRC is applied to the selected word line WL. At this time, memory cell transistors MT that hold data at the "Er" level to "B" level are turned on, and memory cell transistors MT that hold data at the "C" level are turned off.

6.5 Erase operation The erase operation will be explained. The erase operation roughly includes an erase pulse application operation and an erase verify operation. The erase pulse application operation is an operation of applying an erase pulse to lower the threshold voltage of the memory cell transistor MT. The erase verify operation is an operation for determining whether the threshold voltage of the memory cell transistor MT has become lower than a target value as a result of applying the erase pulse application operation. By repeating the combination of the erase pulse application operation and the erase verify operation, the threshold voltage of the memory cell transistor MT is lowered to the "Er" level, that is, lower than the voltage VRA.

Next, the voltage of each wiring during the erase pulse application operation will be explained using FIG. 64. Note that in the following example, a case will be described in which an erase operation is performed for block BLK0, but the same applies to other blocks BLK.

As shown in FIG. 64, at time t0, the block decoder 40 of the row decoder unit 16-0 corresponding to the selected block BLK (block BLK0) applies the voltage VERAH as the "H" level voltage VRDEC to the signal line TG. For example, a voltage VSS is applied as an "L" level voltage to the signal line RDECn. As a result, transistors 41, 42, and 44 in row decoder unit 16-0 are turned on, and transistors 43 and 45 are turned off. As a result, the row decoder unit 16-0 applies the voltage VERASGD to the selection gate lines SGD (SGD0 to SGD3) and SGS (SGS0 to SGS3), and applies a negative voltage to the word lines WL (WL0 to WL63, WLDS, and WLDD). Apply VBB. The voltage VERASGD is a high voltage for turning on the selection transistors ST1 and ST2 to generate a GIDL (gate induced drain leakage) current, and has a relationship of VERA>VERASGD. Further, the voltage VERAH and the voltage VERASGD have a relationship of VERAH>VERASGD. At this time, negative voltage VBB is applied to P well region 72b where transistors 41 to 45 of row decoder unit 16-0 are formed.

Note that the row decoder unit 16-0 applies the voltage VERASGD to any one of the selection gate lines SGD (SGD0 to SGD3) and SGS (SGS0 to SGS3), and the corresponding selection transistor ST1 or ST2 is activated. It may be turned on.

Furthermore, the voltage applied to the word line WL is not limited to the negative voltage VBB. Since the negative voltage VBB is applied to the P-well region 72b in which the transistor 41 in the row decoder 16 is formed, the voltage applied to the word line WL need only be a negative voltage equal to or higher than the negative voltage VBB. That is, it is sufficient that the relationship is VBB≦voltage of word line WL<0V.

In addition, the block decoders 40 of the row decoder units 16-1 to 16-n corresponding to the unselected blocks BLK (blocks BLK1 to BLKn) apply, for example, the voltage VSS as an “L” level voltage to the signal line TG, and For example, voltage VDD is applied to line RDECn as an "H" level voltage. As a result, transistors 41, 42, and 44 in row decoder unit 16-0 are turned off, and transistors 43 and 45 are turned on. At this time, voltage VDD is applied to one ends of transistors 43 and 45. As a result, the row decoder units 16-1 to 16-n put the word line WL in a floating state and apply a voltage (VDD-Vth) (Vth is the threshold voltage of the transistors 43 and 45) to the selection gate lines SGD and SGD. . Furthermore, the P well regions 72b in which the transistors 41 to 45 of the row decoder units 16-0 to 16-n are formed are separated from each other, and the transistors 41 to 45 of the row decoder units 16-1 to 16-n are For example, a voltage VSS may be applied to the P well region 72b in which the P well region 72b is formed.

At time t1, voltage VERA is applied to source line SL. Then, the voltages of the selection gate lines SGD and SGS and the word line WL of the unselected block BLK rise to the voltage VCPLG due to coupling with the source line SL. Voltage VCPLG is higher than voltage (VDD-Vth). Note that the coupling voltages VCPLG on the selection gate lines SGD and SGS and the word line WL may be the same or different from each other.

At time t2, when the voltage of the source line SL reaches the voltage VERA, in the selected block BLK, the memory cells connected to the word line WL are selected according to the potential difference between the voltage VERA and the negative voltage VBB applied to the word line WL. Electrons are extracted from the charge storage layer of the transistor MT (or holes are supplied to the charge storage layer), and data is erased.

At time t3, voltage VSS is applied to source line SL. As a result, the voltage of the selection gate lines SGD and SGS of the unselected block BLK decreases to the voltage (VDD-Vth), and the voltage of the word line WL decreases to the voltage VSS.

At time t4, row decoder unit 16-0 of selected block BLK applies voltage VSS to word line WL.

At time t5, recovery processing is performed and the erase pulse application operation ends.

6.6 Write Operation Next, the write operation will be explained. Note that in the present embodiment, in the program operation, the operation of increasing the threshold voltage is referred to as "'0'write" or simply "write." On the other hand, the operation of maintaining the threshold voltage is referred to as "'1'writing" or "non-writing." Hereinafter, the bit line corresponding to "0" writing will be referred to as BL ("0"), and the bit line corresponding to "1" writing will be referred to as BL ("1").

The write operation in this embodiment includes two operation modes: a normal operation mode and a negative voltage operation mode. The normal operation mode is an operation mode in which the voltage applied to each wiring is higher than the voltage VSS, and the negative voltage operation mode is an operation mode in which the voltage applied to each wiring is higher than the negative voltage VBB.

6.6.1 Voltage of each wiring during programming operation Next, the voltage of each wiring during programming operation will be explained.

6.6.1.1 Voltage of each wiring in normal operation mode First, the voltage of each wiring in normal operation mode will be explained using FIG. 65. Note that in the following example, a case will be described in which string unit SU0 of block BLK0 is selected, but the same applies to other blocks BLK and string units SU.

As shown in FIG. 65, when "H" level data is held in the node INV in the sense amplifier unit SAU, "0" is to be written, and when "L" level data is held, “1” is to be written.

At time t0, voltage VSRC is applied to source line SL. Voltage VSRC is higher than voltage VSS.

Row decoder units 16-1 to 16-n corresponding to non-selected blocks BLK1 to BLKn apply voltage VSS to selection gate lines SGD and SGS to turn off the corresponding selection transistors ST1 and ST2.

Row decoder unit 16-0 corresponding to selected block BLK0 applies voltage VSS to selection gate lines SGS0 to SGS3. As a result, the selection transistors ST2 of the string units SU0 to SU3 are turned off. Furthermore, the row decoder unit 16-0 applies voltage VSG1 to the selection gate line SGD0 corresponding to the selected string unit SU0, and applies voltage VSS to the selection gate lines SGD1 to SGD3 corresponding to the unselected string units SU1 to SU3. . The voltage VSG1 is a voltage that turns on the selection transistor ST1 regardless of the voltage of the corresponding bit line BL. As a result, the selection transistor ST1 of the selected string unit SU0 is turned on, and the selection transistors ST1 of the non-selected string units SU1 to SU3 are turned off.

The sense amplifier 18 applies a voltage VBL to the bit line BL (“1”) and a voltage VSS to the bit line BL (“0”). Voltage VBL is higher than voltage VSS. More specifically, in the sense amplifier section SA, voltage VXX is applied as an "H" level voltage as signals BLC and BLX. Voltage VXX is higher than voltage VSS. At this time, if the node INV holds the "L" level voltage, the transistor 61 is turned off and the transistor 63 is turned on. Therefore, in the transistors 62 and 60, the voltage VBL obtained by clamping the voltage VBIT with the voltage VXX is applied to the bit line BL (“1”). That is, the relationship between voltage VBL and voltage VXX is VBL=VXX-Vthn (Vthn is the threshold voltage of transistors 60 and 62). However, the voltage VBIT may be transferred to the bit line BL by setting the voltage VXX to a voltage equal to or higher than the voltage (VBIT+Vth). Further, when the node INV holds a voltage at the "H" level, the transistor 61 is turned on and the transistor 63 is turned off. Therefore, voltage VSS of node SRCGND is applied to bit line BL (“0”).

Therefore, in the selected string unit SU0, the voltage VBL is applied to the channel of the NAND string NS corresponding to the bit line BL (“1”), and the voltage VBL is applied to the channel of the NAND string NS corresponding to the bit line BL (“0”). VSS is applied.

Since a voltage higher than the voltage VSS is applied to the source line SL, the selection gate lines SGD and SGS, the word line WL, and the bit lines BL (“0”) and BL (“1”), the P well region 72a, Voltage VSS is applied to 72b and 72d.

At time t1, row decoder unit 16-0 applies voltage VSG2 to selection gate line SGD0 of selected string unit SU0. The voltage VSG2 is a voltage that turns the selection transistor ST1 corresponding to the bit line BL (“1”) into a cutoff state and turns the selection transistor ST1 corresponding to the bit line BL (“0”) into an on state. Therefore, for example, the relationship between voltages VSG1 and VSG2 and voltage VBL is (VSG1-Vths)>VBL>(VSG2-Vths) (voltage Vths is the threshold voltage of selection transistor ST1). As a result, the channel of the NAND string NS of the selected string unit SU0 to which the bit line BL (“1”) is connected is placed in a floating state.

At time t2, row decoder unit 16-0 applies voltage VPASS to word line WL. Voltage VPASS is a voltage that turns on the corresponding memory cell transistor MT regardless of the threshold voltage of the memory cell transistor MT.

At time t3, row decoder unit 16-0 applies voltage VPGM to selected word line WL.

In the NAND string NS corresponding to the bit line BL (“0”), the selection transistor ST1 is in an on state. Therefore, the potential of the channel of memory cell transistor MT is maintained at VSS. Therefore, the potential difference (VPGM-VSS) between the control gate and the channel increases, and as a result, electrons are injected into the charge storage layer, increasing the threshold voltage of the memory cell transistor MT.

Further, in the NAND string NS corresponding to the bit line BL (“1”), the selection transistor ST1 is in a cut-off state. Therefore, the channel potential increases due to capacitive coupling with the selected word line WL. Therefore, the potential difference between the control gate and the channel becomes smaller. As a result, few electrons are injected into the charge storage layer, and the threshold voltage of memory cell transistor MT is maintained.

At time t4, row decoder unit 16-0 applies voltage VSS to selected word line WL. Further, a voltage VSS is applied to the source line SL.

At time t5, recovery processing is performed and the program operation in the normal operation mode ends.

6.6.1.2 Voltage of each wiring in negative voltage operation mode Next, the voltage of each wiring in negative voltage operation mode will be explained using FIG. 66. In the example of FIG. 66, the voltages of the selection gate lines SGD and SGS, the word line, and the bit lines BL (“0”) and BL (“1”) are lower overall (negative (shifted to the voltage side). Hereinafter, the differences from FIG. 65 will be mainly explained.

As shown in FIG. 66, at time t0, voltage VSRC is applied to source line SL. Note that the voltage VSRC may be set to a lower voltage than in the normal operation mode.

Row decoder units 16-1 to 16-n corresponding to non-selected blocks BLK1 to BLKn apply negative voltage VBB to selection gate lines SGD and SGS to turn off the corresponding selection transistors ST1 and ST2.

Row decoder unit 16-0 corresponding to selected block BLK0 applies negative voltage VBB to selection gate lines SGS0 to SGS3. As a result, the selection transistors ST2 of the string units SU0 to SU3 are turned off. Further, the row decoder unit 16-0 applies a voltage (VSG1+VBB) lower than the voltage VSG1 to the selection gate line SGD0 corresponding to the selected string unit SU0, and applies a voltage (VSG1+VBB) lower than the voltage VSG1 to the selection gate line SGD1 to SGD0 corresponding to the unselected string units SU1 to SU3. By applying a negative voltage VBB to SGD3, the selection transistor ST1 of the selected string unit SU0 is turned on, and the selection transistors ST1 of the non-selected string units SU1 to SU3 are turned off.

The sense amplifier 18 applies a voltage (VBL−VB1) lower than the voltage VBL to the bit line BL (“1”), and applies a negative voltage VBB to the bit line BL (“0”). The relationship between voltage VB1 and negative voltage VBB is VBB≦(−VB1)≦0. At this time, in the sense amplifier section SA, a voltage (VXX-VB1) is applied to the signals BLC and BLX as an "H" level voltage. However, the voltage (VXX-VB1) may be set to be higher than the voltage (VBIT+Vth), and the voltage VBIT may be transferred to the bit line BL.

Note that the voltage applied to the bit line BL (“0”) is not limited to the negative voltage VBB. Since the negative voltage VBB is applied to the P-well region 72b in which the transistors 60 to 62 in the sense amplifier section SA are formed, the voltage applied to the bit line BL (“0”) is higher than the negative voltage VBB. Any negative voltage is sufficient.

Therefore, in the selected string unit SU0, voltage (VBL-VB1) is applied to the channel of the NAND string NS corresponding to the bit line BL (“1”), and the voltage (VBL−VB1) is applied to the channel of the NAND string NS corresponding to the bit line BL (“0”). A negative voltage VBB is applied to the channel of.

Since a voltage equal to or higher than the negative voltage VBB is applied to the source line SL, selection gate lines SGD and SGS, word line WL, and bit line BL, the negative voltage VBB is applied to the P well regions 72a, 72b, and 72d. be done.

At time t1, row decoder unit 16-0 applies a voltage (VSG2+VBB) lower than voltage VSG2 to selection gate line SGD0 of selected string unit SU0. As a result, the channel of the NAND string NS of the selected string unit SU0 to which the bit line BL (“1”) is connected is placed in a floating state.

At time t2, row decoder unit 16-0 applies a voltage (VPASS+VBB) lower than voltage VPASS to word line WL.

At time t3, row decoder unit 16-0 applies a voltage (VPGM+VBB) lower than voltage VPGM to selected word line WL.

As a result, the threshold voltage of the memory cell transistor MT increases in the NAND string NS corresponding to the bit line BL (“0”), and the threshold voltage of the memory cell transistor MT increases in the NAND string NS corresponding to the bit line BL (“1”). voltage is maintained.

At time t4, row decoder unit 16-0 applies voltage VSS to selected word line WL. A voltage VSS is applied to the source line SL.

At time t5, recovery processing is performed and the program operation in the negative voltage operation mode ends.

6.6.2 Overall Flow of Write Operation Next, two examples will be shown regarding the overall flow of write operation.

6.6.2.1 First Example First, the overall flow of the write operation in the first example will be described using FIGS. 67 and 68. FIG. 67 shows a flowchart of the write operation of the first example. FIG. 68 is a timing chart showing the voltage of the selected word line WL, the voltage of the bit line BL (“0”), input data, and ready-busy signal RBn in the write operation of the first example.

In the example of FIG. 68, in order to simplify the explanation, the voltage of the bit line BL (“0”) indicates the voltage during the program operation, and the voltage of the bit line BL during the program verify operation is omitted. has been done. Furthermore, in the example of FIG. 68, input of commands and addresses is omitted.

As shown in FIG. 67, the memory 10 first receives a write operation command from the controller 20 (step S200).

Upon receiving the write command, the sequencer 14 selects the normal operation mode and executes the program operation (step S201).

After the program operation is completed, the sequencer 14 executes a program verify operation (step S202).

If the verification is passed (step S203_Yes), the sequencer 14 ends the write operation.

If the verification has not been passed (step S203_No), the sequencer 14 checks whether the number of program loops has reached the preset upper limit (step S204).

If the number of program loops has reached the upper limit (step S204_Yes), the sequencer 14 ends the write operation and reports to the controller 20 that the write operation did not end normally.

If the number of program loops has not reached the upper limit number (step S204_No), the sequencer 14 checks whether the number of program loops has reached the negative voltage setting number (step S205).

If the number of program loops has reached the negative voltage setting number (step S205_Yes), the sequencer 14 selects the negative voltage operation mode. Then, the sequencer 14 checks whether the voltage parameters corresponding to the negative voltage operation mode have been set (step S206). That is, the sequencer 14 checks whether the negative voltage operation mode has been selected in the previous program loop.

If the voltage parameters corresponding to the negative voltage operation mode have not been set (step S206_No), that is, if the negative voltage operation mode has not been selected in the previous program loop, the sequencer 14 sets the voltage parameters corresponding to the negative voltage operation mode. Parameter settings are performed (step S207). That is, the sequencer 14 changes the voltage parameters of each wiring to correspond to the negative voltage operation mode. More specifically, the sequencer 14 applies a negative voltage VBB to the set voltage values of the selection gate lines SGD and SGS, the word line, the P well regions 72a, 72b, and 72d, and the bit line BL (“0”) in the program operation. , and lower the set voltage value. Further, the sequencer 14 adds a voltage (-VB1) to the set voltage values of the bit line BL (“1”) and the signals BLC and BLX to lower the set voltage values.

If the negative voltage setting count has not been reached (step S205_No), if the voltage parameters corresponding to the negative voltage operation mode have already been set (step S206_Yes), or if the voltage parameters corresponding to the negative voltage operation mode have not been set in step S207. After finishing, the sequencer 14 steps up the program voltage (step S208). More specifically, the sequencer 14 adds the step-up voltage DVPGM to the set voltage value of the program voltage to step up the set voltage value. Voltage DVPGM is higher than voltage VSS.

After stepping up the program voltage, the sequencer 14 returns to step S201 and executes the program operation.

Next, the voltage of the selected word line WL, the voltage of the bit line BL (“0”), input data, and ready-busy signal RBn during a write operation will be explained.

As shown in FIG. 68, upon receiving the command “80h”, the lower page address, the lower page data (reference symbol “LP”), and the command “1Ah” from the controller 20, the sequencer 14 transmits the ready-busy signal as “ The input data "LP" is set to "L" level and transferred to the sense amplifier 18. When the transfer of the data "LP" to the sense amplifier 18 is completed, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

Next, upon receiving the command “80h”, the address of the Upper page, the data of the Upper page (reference symbol “UP”), and the command “10h” from the controller 20, the sequencer 14 sets the ready-busy signal RBn to the “L” level. After input data "UP" is transferred to the sense amplifier 18, a write operation is executed.

In the first program loop, in the program operation, the row decoder 16 applies voltage VPGM to the selected word line WL as a program voltage, and the sense amplifier 18 applies voltage VSS to the bit line BL (“0”). There is. Further, for example, in the program verify operation, the row decoder 16 applies a voltage VA corresponding to the "A" level to the selected word line WL. For example, in the first program loop, the sequencer 14 fails to verify the "A" level.

In the second program loop, in the program operation, the row decoder 16 applies a voltage (VPGM+DVPGM) that is the voltage VPGM stepped up by the voltage DVPGM to the selected word line WL, and the sense amplifier 18 ”) is applied with voltage VSS. Further, for example, in the program verify operation, the row decoder 16 applies a voltage VA corresponding to the "A" level to the selected word line WL. For example, in the second program loop, the sequencer 14 fails to verify the "A" level.

In the third program loop, in the program operation, the row decoder 16 applies voltage (VPGM+2DVPGM) to the selected word line WL, and the sense amplifier 18 applies voltage VSS to the bit line BL (“0”). . Further, for example, in the program verify operation, the row decoder 16 applies the voltage VA and the voltage VB corresponding to the "B" level to the selected word line WL. For example, in the third program loop, the sequencer 14 fails to verify the "A" level and the "B" level.

In the fourth program loop, in the program operation, the row decoder 16 applies voltage (VPGM+3DVPGM) to the selected word line WL, and the sense amplifier 18 applies voltage VSS to the bit line BL (“0”). . Further, for example, in the program verify operation, the row decoder 16 applies voltages VA and VB to the selected word line WL. For example, in the fourth program loop, the sequencer 14 fails to verify the "A" level and the "B" level.

In the fifth program loop, in the program operation, the row decoder 16 applies voltage (VPGM+4DVPGM) to the selected word line WL, and the sense amplifier 18 applies voltage VSS to the bit line BL (“0”). . Further, for example, in the program verify operation, the row decoder 16 applies voltages VA and VB to the selected word line WL. For example, in the fifth program loop, the sequencer 14 passes the "A" level verification and fails the "B" level verification.

In the sixth program loop, in the program operation, the row decoder 16 applies voltage (VPGM+5DVPGM) to the selected word line WL, and the sense amplifier 18 applies voltage VSS to the bit line BL (“0”). . Further, for example, in the program verify operation, the row decoder 16 applies the voltage VB and VC corresponding to the "C" level to the selected word line WL. For example, in the sixth program loop, the sequencer 14 fails to verify the "B" level and the "C" level.

In the seventh program loop, in the program operation, the row decoder 16 applies voltage (VPGM+6DVPGM) to the selected word line WL, and the sense amplifier 18 applies voltage VSS to the bit line BL (“0”). . Further, for example, in the program verify operation, the row decoder 16 applies voltages VB and VC to the selected word line WL. For example, in the seventh program loop, the sequencer 14 fails to verify the "B" level and the "C" level.

In the eighth program loop, in the program operation, the row decoder 16 applies voltage (VPGM+7DVPGM) to the selected word line WL, and the sense amplifier 18 applies voltage VSS to the bit line BL (“0”). . Further, for example, in the program verify operation, the row decoder 16 applies voltages VB and VC to the selected word line WL. For example, in the eighth program loop, the sequencer 14 passes the "B" level verification and fails the "C" level verification.

In the ninth program loop, the number of program loops reaches the number of negative voltage settings, so the sequencer 14 selects the negative voltage operation mode and sets voltage parameters corresponding to the negative voltage operation mode. Therefore, in the program operation, the row decoder 16 applies a voltage (VPGM+8DVPGM+VBB) to the selected word line WL, and the sense amplifier 18 applies a negative voltage VBB to the bit line BL (“0”). In the example of FIG. 68, when the voltage in the 8th program loop (VPGM+7DVPGM) and the voltage in the 9th program loop (VPGM+8DVPGM+VBB) are compared, the relationship is (VPGM+7DVPGM)>(VPGM+8DVPGM+VBB). Further, for example, in the program verify operation, the row decoder 16 applies the voltage VC to the selected word line WL. For example, in the ninth program loop, the sequencer 14 fails to verify the "C" level.

In the tenth program loop, in the program operation, the row decoder 16 applies a voltage stepped up by the voltage DVPGM (VPGM+9DVPGM+VBB) to the selected word line WL, and the sense amplifier 18 applies a voltage stepped up by the voltage DVPGM to the selected word line WL, and the sense amplifier 18 applies a voltage stepped up by the voltage DVPGM to the selected word line WL. A negative voltage VBB is applied. Further, for example, in the program verify operation, the row decoder 16 applies the voltage VC to the selected word line WL. For example, in the tenth program loop, the sequencer 14 fails to verify the "C" level.

In the 11th program loop, in the program operation, the row decoder 16 applies a voltage stepped up by the voltage DVPGM (VPGM+10DVPGM+VBB) to the selected word line WL, and the sense amplifier 18 applies a voltage stepped up by the voltage DVPGM to the selected word line WL, and the sense amplifier 18 applies a voltage stepped up by the voltage DVPGM to the selected word line WL. A negative voltage VBB is applied. Further, for example, in the program verify operation, the row decoder 16 applies the voltage VC to the selected word line WL. For example, in the eleventh program loop, the sequencer 14 passes the "C" level verification. After completing the write operation, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

6.6.2.2 Second Example Next, the overall flow of the write operation in the second example will be described using FIGS. 69 and 70. FIG. 69 shows a flowchart of the write operation of the second example. FIG. 70 is a timing chart showing the voltage of the selected word line WL, the voltage of the bit line BL (“0”), input data, and ready-busy signal RBn in the write operation of the second example. Hereinafter, the differences from the first example will be mainly explained.

Note that in the example of FIG. 70, as in the example of FIG. 68, to simplify the explanation, the voltage of the bit line BL (“0”) indicates the voltage during the program operation, and the voltage during the program verify operation. The voltage of the bit line BL in is omitted. Furthermore, in the example of FIG. 70, input of commands and addresses is omitted.

As shown in FIG. 69, steps S200 to S204 are the same as in FIG. 67 of the first example.

If the set number of negative voltages has not been reached (step S205_No), that is, in the normal operation mode, the sequencer 14 steps up the program voltage (step S208). After stepping up the program voltage, the sequencer 14 returns to step S201.

When the negative voltage setting number of times has been reached (step S205_Yes), the sequencer 14 selects the negative voltage operation mode. Then, instead of adding the voltage DVPGM to step up the program voltage, the sequencer 14 steps down the voltage parameter of the bit line BL (“0”) to the negative voltage side (step S210). More specifically, the selection gate lines SGD and SGS, the unselected word line WL, the P well regions 72a, 72b, and 72d, the bit lines BL (“0”) and BL (“1”), and the signal Add voltage (-DVPGM) to the set voltage values of BLC and BLX to lower the set voltage values. After stepping down the voltage parameter to the negative voltage side, the sequencer 14 returns to step S201.

Next, the voltage of the selected word line WL, the voltage of the bit line BL (“0”), input data, and ready-busy signal RBn during a write operation will be explained.

As shown in FIG. 70, the operation up to the eighth program loop is the same as that in the first example shown in FIG. 68.

In the ninth program loop, the number of program loops has reached the negative voltage setting number, so the sequencer 14 selects the negative voltage operation mode and changes the voltage parameter of the bit line BL (“0”) to the negative voltage side by the voltage DVPGM. It's shifting. Therefore, in the program operation, the row decoder 16 applies the same voltage (VPGM+7DVPGM) as in the eighth program loop to the selected word line WL, and the sense amplifier 18 applies the voltage (VSS -DVPGM) is applied. Further, for example, in the program verify operation, the row decoder 16 applies the voltage VC to the selected word line WL. For example, in the ninth program loop, the sequencer 14 fails to verify the "C" level.

In the 10th program loop, in the program operation, the row decoder 16 applies a voltage (VPGM+7DVPGM) to the selected word line WL, and the sense amplifier 18 sets the bit line BL (“0”) from the 9th program loop. A voltage (VSS-2DVPGM) whose voltage value is shifted to the negative voltage side by the voltage DVPGM is applied. Further, for example, in the program verify operation, the row decoder 16 applies the voltage VC to the selected word line WL. For example, in the tenth program loop, the sequencer 14 fails to verify the "C" level.

In the 11th program loop, in the program operation, the row decoder 16 applies a voltage (VPGM+7DVPGM) to the selected word line WL, and the sense amplifier 18 sets the bit line BL (“0”) from the 10th program loop. A voltage (VSS-3DVPGM) whose voltage value is shifted to the negative voltage side by the voltage DVPGM is applied. Further, for example, in the program verify operation, the row decoder 16 applies the voltage VC to the selected word line WL. For example, in the 11th program loop, the sequencer 14 passes the "C" level verification. When the sequencer 14 completes the write operation, the sequencer 14 sets the ready-busy signal RBn to the "H" level.

6.7 Effects of this Embodiment With the configuration of this embodiment, it is possible to reduce the voltage applied to each wiring in a write operation, a read operation, and an erase operation. Therefore, power consumption in the semiconductor memory device can be reduced.

For example, in the erase operation of the prior art, a voltage of 0V to 0.5V is applied to the word line WL, and a voltage of 18V to 24V is applied to the channel of the memory cell transistor MT. In contrast, with the configuration according to this embodiment, for example, by applying a voltage of -1V to -0.5V to the word line WL, the voltage of the channel of the memory cell transistor MT can be reduced to 17V to 23V. That is, the voltage value of voltage VERA can be reduced. For example, in a booster circuit, lowering the voltage from 0V to 0.5V to a voltage of -1V to -0.5V reduces power consumption than boosting a voltage from 17V to 23V to a voltage from 18V to 24V. can.

Furthermore, with the configuration according to this embodiment, by providing a part of the threshold distribution of the memory cell transistor MT on the negative voltage side, the width of each threshold level can be made wider than when the threshold distribution is provided only on the positive voltage side. Can be made wider. As a result, it is possible to suppress erroneous reading due to effects such as a shift in the threshold voltage or a widening of the threshold distribution. Therefore, reliability of the semiconductor memory device can be improved.

Furthermore, with the configuration according to this embodiment, the width of each threshold level can be widened, so the width of the step-up voltage in the program operation can be made relatively large. Therefore, the number of program loops can be reduced. Therefore, an increase in write operation time can be suppressed. Therefore, the processing capacity of the semiconductor memory device can be improved.

Furthermore, with the configuration according to this embodiment, the normal operation mode is selected in the first half of the write operation, that is, when the number of program loops is small, and the normal operation mode is selected in the second half of the write operation, that is, when the number of program loops is set in advance. If the voltage is higher than the set value, negative voltage operation mode can be selected. More specifically, in the first half of the write operation, the proportion of bit lines BL (“0”) in all bit lines BL is greater than the proportion of bit lines (“1”). In this case, the normal operation mode is selected and the voltage VSS is applied to the bit line BL (“0”). On the other hand, in the latter half of the write operation, most of the cell writes are completed and the proportion of bit lines BL (“0”) decreases. In this case, the negative voltage operation mode is selected and a negative voltage VBB is applied to the bit line BL (“0”). That is, by selecting the negative voltage mode in a state where the number of bit lines BL to which the negative voltage VBB is applied is relatively small, an increase in power consumption can be suppressed.

7. Modifications, etc. The memory system according to the above embodiment includes a semiconductor storage device (10) having a memory cell array (11) including memory cells (MT) capable of holding at least 4-bit data (Top/Upper/Middle/Lower). , and a controller (20) that controls a first write operation and a second write operation based on 4-bit data in the semiconductor memory device. The controller includes a conversion circuit (27) that converts 4-bit data into 2-bit data (X1/X2). The semiconductor memory device includes a restoration control circuit (19) that restores 4-bit data based on the converted 2-bit data and the data written to the memory cell by the first write operation. The first write operation is performed based on 4-bit data received from the controller, and the second write operation is performed based on 4-bit data restored by the restoration control circuit.

By applying the above embodiments, it is possible to provide a semiconductor memory device that can suppress an increase in chip area.

Note that the embodiment is not limited to the form described above, and various modifications are possible.

For example, in this embodiment, a memory cell capable of holding data using a 16-value threshold distribution has been described, but the present invention is not limited to 16 values and can be applied to any number of threshold distributions. Furthermore, in this embodiment, the 2-bit data (X1 page data and It is also possible to memorize it.

Furthermore, in the fourth embodiment, a case has been described in which the data conversion/restore control circuit 19B is provided within the memory 10, but it may also be provided within the controller 20. That is, data conversion and restoration operations may be performed within the controller 20.

Furthermore, in the fifth embodiment, a configuration using a negative voltage has been described, but the negative voltage operation mode may be used in any one of write operation, read operation, or erase operation, or in a combination of any two operations. may be implemented.

Furthermore, the above embodiments can be combined as much as possible.

Furthermore, in the above embodiments, the semiconductor memory device is not limited to a three-dimensionally stacked NAND flash memory. The present invention may be a planar NAND flash memory, or may be applied to a nonvolatile memory having memory cells capable of holding data of 3 bits or more.

Furthermore, "connection" in the above embodiments also includes a state in which they are indirectly connected with something else interposed therebetween, such as a transistor or a resistor.

Furthermore, in the above embodiment, the 4-bit data before being converted by the data conversion circuit 27 and the 4-bit data restored by the data restoration control circuit 19 have errors within a range that can be corrected by the ECC circuit 25, for example. May contain.

Although several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

DESCRIPTION OF SYMBOLS 1...Memory system, 10...Memory, 11...Memory cell array, 12...Command register, 13...Address register, 14...Sequencer, 15...Driver circuit, 16...Row decoder, 17...Data register, 18...Sense amplifier, 19... Data restoration control circuit, 19B...Data conversion/restoration control circuit, 20...Controller, 21...Host interface circuit, 22...RAM, 23...CPU, 24...Buffer memory, 25...ECC circuit, 26...NAND interface circuit, 27... Data conversion circuit, 30... Host device, 41-45, 53-55, 60-63, 76-79... Transistor, 51... NAND circuit, 52... Inverter, 64... Level shifter, 70... Semiconductor substrate, 71a-71d...N well region, 72a to 72c...P well region, 73...N ⁺ diffusion layer, 74...P ⁺ diffusion layer, 75...gate electrode, 90...insulating layer, 91...semiconductor layer.

Claims (10)

1-bit data is stored, and the threshold voltage is set to an erase level, a first write level higher than the erase level , a second write level higher than the first write level, a third write level higher than the second write level , and a memory cell array including a first memory cell that can be set to any one of a fourth write level higher than the third write level , and a first flag cell ;
a first word line connected to the first memory cell and the first flag cell ;
A write operation is performed on the first memory cell four times after an erase operation is performed and before the next erase operation is performed, and the first memory cell is read based on the threshold voltage of the first flag cell. a sequencer configured to perform the operations;
The sequencer sets the threshold voltage of the first flag cell to the erase level, the second write level, the third write level, and the fourth write level based on the number of executions of the write operation after the erase operation. Set to one of
When the read operation is performed based on a first condition, a first voltage higher than the erase level and lower than the first write level is applied to the first word line, and the first voltage is applied to the first word line based on the second condition. When a read operation is performed, a second voltage higher than the first write level and lower than the second write level is applied to the first word line , and the read operation is performed based on a third condition. In the case where a third voltage higher than the second write level and lower than the third write level is applied to the first word line and the read operation is performed based on a fourth condition, the third voltage is applied to the first word line. A fourth voltage higher than the third write level and lower than the fourth write level is applied to one word line ;
Semiconductor storage device. The sequencer executes the read operation based on the second condition, and when the threshold voltage of the first flag cell is at the erase level, further executes the read operation based on the first condition , further performing the read operation based on the third condition when the threshold voltage of the flag cell is at the second write level ;
The semiconductor memory device according to claim 1 . The sequencer performs a pseudo erase operation of the first memory cell between the first write operation and the second write operation after the erase operation .
The semiconductor memory device according to claim 1 . In the read operation based on the first condition, the first voltage is applied to the first word line, and the second voltage is not applied to the first word line.
In the read operation based on the second condition, the second voltage is applied to the first word line, and the first voltage is not applied.
A semiconductor memory device according to any one of claims 1 to 3 . Due to the first write operation after the erase operation , the threshold voltage of the first memory cell is included in either the erase level or the first write level,
Due to the second write operation after the erase operation , the threshold voltage of the first memory cell is included in one of the erase level, the first write level, and the second write level,
By the third write operation after the erase operation, the threshold voltage of the first memory cell is set to one of the erase level, the first write level, the second write level, and the third write level. Includes
By the fourth write operation after the erase operation, the threshold voltage of the first memory cell is set to the erase level, the first write level, the second write level, the third write level, and the fourth write level. Included in any of the writing levels ,
The semiconductor memory device according to claim 1. the sequencer is configured to receive a first read command and a second read command;
If the sequencer receives the first read command, the read operation based on the first condition is performed;
If the sequencer receives the second read command, the read operation based on the second condition is performed;
A semiconductor memory device according to any one of claims 1 to 5 . After the first write operation after the erase operation, the threshold voltage of the first flag cell is set to the erase level ,
After the second write operation after the erase operation, the threshold voltage of the first flag cell is set to the second write level,
After the third write operation after the erase operation, the threshold voltage of the first flag cell is set to the third write level,
After the fourth write operation after the erase operation, the threshold voltage of the first flag cell is set to the fourth write level ;
The semiconductor memory device according to claim 1. The memory cell array further includes a second flag cell and a third flag cell,
The sequencer executes the read operation based on the first condition ,
If the threshold voltage of the first flag cell is included in the second write level and the threshold voltage of the second flag cell is included in the erase level, further performing the read operation based on the second condition;
If the threshold voltage of the second flag cell is included in the third write level and the threshold voltage of the third flag cell is included in the erase level, further performing the read operation based on the third condition;
further performing the read operation based on the fourth condition when the threshold voltage of the third flag cell is included in the fourth write level ;
The semiconductor memory device according to claim 1 . In the first write operation after the erase operation, a first write voltage is applied to the first memory cell,
In the second write operation after the erase operation, a second write voltage higher than the first write voltage is applied to the first memory cell,
In the third write operation after the erase operation, a third write voltage higher than the second write voltage is applied to the first memory cell,
In the fourth write operation after the erase operation, a fourth write voltage higher than the third write voltage is applied to the first memory cell.
The semiconductor memory device according to claim 1. The memory cell array includes a plurality of the first flag cells,
The sequencer executes the read operation of the first memory cell based on a majority vote of the plurality of first flag cells.
The semiconductor memory device according to claim 1.