JP7392477B2 - Calibration method and information processing device - Google Patents

Description

The present invention relates to a calibration method and an information processing device.

Calibration is performed on the system board to adjust decision points used for writing to and reading from memory by a CPU (Central Processing Unit). For example, the optimum value of the timing of the data signal and the data decision signal and the reference voltage for determining the value of the data signal is set as the decision point. As a technique related to such calibration, a technique using a so-called eye pattern is known.

Japanese Patent Application Publication No. 2016-197275 US Patent No. 7991098

However, the above techniques only assume that the silhouette shape of the eye pattern is a circle or ellipse that is vertically and horizontally symmetrical, so there is a limit to the ability to appropriately set decision points. .

In one aspect, an object of the present invention is to provide a calibration method and an information processing apparatus that can appropriately set a decision point.

In one aspect of the calibration method, a transmission result of the signal is obtained for each combination of a reference value used to determine the value of the signal and a delay value for memory access of the signal, and the transmission result is a successful transmission. The difference between the combinations of the combinations in which the transmission result is a transmission success and the combination in which the transmission result is a transmission failure, and the minimum value of the difference in the reference value and the difference in the delay value is the maximum value. A processor executes a process of extracting a maximum point and setting the maximum point among the maximum points at which a balance between the difference in the reference value and the difference in the delay value satisfies a predetermined criterion as a decision point.

Decision points can be set appropriately.

FIG. 1 is a schematic diagram showing an example of the appearance of a system board. FIG. 2 is a diagram illustrating an example of memory access topology. FIG. 3 is a diagram showing an example of an eye pattern. FIG. 4 is a diagram showing an example of an eye pattern. FIG. 5 is a diagram showing an example of an eye pattern. FIG. 6 is a diagram showing an example of a common eye pattern. FIG. 7 is a flowchart showing the procedure of calibration processing according to Prior Art 1. FIG. 8 is a diagram showing an example of an eye pattern. FIG. 9 is a diagram showing an example of an eye pattern. FIG. 10 is a diagram showing an example of an eye pattern. FIG. 11 is a diagram showing an example of a common eye pattern. FIG. 12 is a diagram illustrating an example of a method for setting decision points. FIG. 13 is a diagram showing another example of the common eye pattern. FIG. 14 is a flowchart showing the procedure of calibration processing according to Prior Art 2. FIG. 15 is a diagram illustrating an example of a method for extracting the first center point. FIG. 16 is a diagram illustrating an example of a method for extracting the second center point. FIG. 17 is a diagram illustrating an example of a method for setting decision points. FIG. 18 is a diagram illustrating an example of calibration failure in Prior Art 1. FIG. 19 is a diagram illustrating an example of calibration failure in Prior Art 2. FIG. 20 is a flowchart showing the procedure of calibration processing according to the first embodiment. FIG. 21 is a diagram illustrating an example of setting a decision point in Prior Art 1 and Example 1. FIG. 22 is a diagram illustrating an example of setting a decision point in Prior Art 2 and Example 1. FIG. 23 is a diagram illustrating an example of the number of margins on the top, bottom, left and right sides. FIG. 24 is a diagram illustrating a configuration example of an information processing apparatus according to the first embodiment. FIG. 25 is a detailed flow (1) showing the procedure of the calibration process according to the first embodiment. FIG. 26 is a detailed flow (2) showing the procedure of the calibration process according to the first embodiment. FIG. 27 is a diagram illustrating an example of a method for calculating the number of blank spaces. FIG. 28 is a diagram showing an example of a map of the number of upper codes. FIG. 29 is a diagram showing an example of a map of the number of lower codes. FIG. 30 is a diagram illustrating an example of a map of the number of taps on the left side. FIG. 31 is a diagram illustrating an example of a map of the number of taps on the right side. FIG. 32 is a diagram showing an example of a map of the minimum margin value. FIG. 33 is a diagram showing an example of a map of upper and lower balance values. FIG. 34 is a diagram showing an example of a map of left and right balance values. FIG. 35 is a diagram showing an example of a map of vertical and horizontal balance values. FIG. 36 is a diagram showing another example of a common eye pattern. FIG. 37 is a diagram illustrating an example of a map of minimum margin values. FIG. 38 is a diagram showing an example of a map of upper and lower balance values. FIG. 39 is a diagram showing an example of a map of left and right balance values. FIG. 40 is a diagram showing an example of a map of vertical and horizontal balance values.

The calibration method and information processing apparatus according to the present application will be described below with reference to the accompanying drawings. Note that this example does not limit the disclosed technology. Each of the embodiments can be combined as appropriate within a range that does not conflict with the processing contents.

[One aspect of terminology]
Hereinafter, the data signal may be referred to as a "DQ signal," and the data decision signal (data strobe signal) may be referred to as a "DQS signal." Furthermore, a voltage that is referred to as a threshold when determining the H level and L level of a DQ signal may be referred to as a "reference voltage." Further, the phase of the DQ signal and the DQS signal may be referred to as "timing", and the amount of delay in the phase of the DQ signal/DQS signal may be referred to as "DQ delay tap/DQS delay tap".

The "eye pattern" referred to below is created, by way of example only, by determining the success or failure of transmission of the DQ signal for each combination of the reference voltage of the DQ signal and the delay tap of the DQS signal. Below, as an example only, the reference voltage of the DQ signal is controlled in the range of Vref0 to Vref31, and the DQS signal is controlled in the range of -16 to 15 with the time length obtained by dividing the phase of one period of the DQS signal by 32 as a step size. An example will be given in which the delay tap of a signal is controlled. In this case, a total of 1024 combinations of reference voltages in the range of Vref0 to Vref31 and DQS delay taps in the range of -16 to 15 can be used as decision point candidates. An eye pattern is created by plotting a binary value, for example 0 or 1, representing the presence or absence of a transmission error in the DQ signal for each point corresponding to these 1024 combinations.

In the following, an "eye pattern" in which the presence or absence of a transmission error of a DQ signal is mapped will be exemplified, with the reference voltage as the vertical axis and the DQS delay tap as the horizontal axis, just as an example. When identifying the reference voltage range on the eye pattern that corresponds to the value of one DQS delay tap, the range is described as "code high" and the number of points included in the range is referred to as "code high". It may be written as "number of codes". Also, when identifying the range of DQS delay taps on the eye pattern corresponding to the value of one reference voltage, the range is referred to as the "tap width" and the number of points included in the range is referred to as the "tap width". It may be written as "Number of taps".

[One aspect of the background]
On a system board with a large-scale memory configuration, a plurality of memory modules are connected to one channel in order to improve the storage capacity per channel. FIG. 1 is a schematic diagram showing an example of the appearance of a system board. FIG. 1 shows, by way of example only, a system board 1a on which four memory channels and three memory slots A to Slot C are mounted. Memory modules M2, M1, and M0 of two ranks, Rank0 and Rank1, are inserted into these slots A to C. Thus, the CPU 10, via the memory controller 20, uses memory modules M2, M1, and M0 with a total of six ranks, three slots and two ranks per channel.

However, because a plurality of memory modules are connected to a transmission path, the number of branches, or so-called stubs, on the transmission path increases. FIG. 2 is a diagram illustrating an example of memory access topology. FIG. 2 shows reflected waves generated at each branch when memory module M0 of the three memory modules M0 to M2 is accessed. As shown in FIG. 2, in each branch, impedance mismatch occurs between the transmission line and the memory module, resulting in multiple reflections of the transmitted signal. The influence of such reflected waves causes the waveform shape of the DQ signal to be deformed, resulting in a waveform that makes it difficult to adjust the optimal values of the reference voltage and DQS delay tap to the decision point.

3 to 5 are diagrams showing examples of eye patterns. 3 to 5 show, by way of example only, matrices in which the vertical axis represents the reference voltage in the range of Vref0 to Vref31, and the horizontal axis represents the DQS delay tap in the range of -16 to 15. Furthermore, the results of reading the DQ signals from slots A to C shown in FIG. 1 to the memory controller 20 are plotted in the matrices shown in FIGS. 3 to 5. When the readout results are plotted in this way, as an example only, "1" is plotted at points where there is a DQ signal transmission error, while "0" is plotted at points where there is no DQ signal transmission error. is plotted. Note that FIG. 3 shows the results of reading from the memory block corresponding to Rank 0 on the memory module M2 inserted into slot A located at the far end of the CPU 10. Further, FIG. 4 shows the result of reading from the memory block corresponding to Rank 0 on the memory module M1 inserted into slot B. Further, FIG. 5 shows the results of reading from the memory block corresponding to Rank 0 on the memory module M0 inserted into the slot C located at the proximal end of the CPU 10.

As shown in FIGS. 3 to 5, as a result of plotting the readout results of the DQ signals, an area in which "0" points shown by hatching are connected appears as an eye pattern. According to the eye patterns shown in FIGS. 3 to 5, it is clear that the shapes of the eye patterns are different for each memory module M2, memory module M1, and memory module M0. Furthermore, although not shown here, the shape of the eye pattern may differ between ranks of the same memory module. From these facts, it can be seen that it is preferable to obtain an eye pattern for each slot and rank when calibrating between the processor and the memory.

An eye pattern common to each rank, which is created from eye patterns corresponding to each rank of Rank 0 of slot A, Rank 0 of slot B, and Rank 0 of slot C, is used for calibration.

FIG. 6 is a diagram showing an example of a common eye pattern. FIG. 6 also shows a matrix in which the vertical axis is the reference voltage in the range of Vref0 to Vref31 and the horizontal axis is the DQS delay tap in the range of -16 to 15. The matrix shown in FIG. 6 includes, for each point on the matrix, the sum of the readout result values shown in FIG. 3, the readout result values shown in FIG. 4, and the readout result values shown in FIG. values are plotted. In FIG. 6, an example is given in which memory blocks for a total of three ranks, Rank 0 of slot A, Rank 0 of slot B, and Rank 0 of slot C, are controlled by the memory controller 20.

For example, a point where the total value "0" is plotted means that no DQ signal transmission error is observed in all three memory blocks controlled by the memory controller 20. Further, at a point where the total value "1" is plotted, it means that a transmission error of the DQ signal was observed in any one of the three memory blocks controlled by the memory controller 20. Further, at points where the total value "2" is plotted, it means that a transmission error of the DQ signal was observed in two of the three memory blocks controlled by the memory controller 20. Furthermore, at points where the total value "3" is plotted, it means that a transmission error of the DQ signal was observed in all three memory blocks controlled by the memory controller 20.

In this way, the area where points with a total value of "0" are connected, shown by thin hatching in FIG. 6, is common to all memory blocks corresponding to three ranks: Rank 0 of slot A, Rank 0 of slot B, and Rank 0 of slot C. It appears as an eye pattern. Hereinafter, an eye pattern common to all memory blocks controlled by the memory controller 20 may be referred to as a "common eye pattern."

Here, if the number of samplings of the DQ signal used for calibration is large enough, it is possible to converge the range in which successful transmission of the DQ signal is observed on the matrix, so that it is possible to converge the range in which the successful transmission of the DQ signal is observed, making it possible to confirm the influence of noise on the transmission path. It is possible to create an eye pattern. For example, when the range in which successful transmission of the DQ signal is observed is converged, the area shown by dark hatching in FIG. 6 is obtained as a common eye pattern. When such a common eye pattern is used for calibration, the operation of the system can be stabilized no matter which point in the common eye pattern is set as a decision point.

However, when implementing the system, it is not always possible to obtain a sufficient number of samples of DQ signals used for calibration. For example, in order to avoid prolonging the time required from power-on to startup, short-time calibration may be required. In order to realize such implementation, the number of samplings of DQ signals may be reduced. If the number of samplings of the DQ signal is reduced, the common eye pattern shown in dark hatching in FIG. 6 may not necessarily be obtained during calibration, but the common eye pattern shown in light hatching in FIG. Sometimes you just can't get it.

In this way, when only the common eye pattern shown by thin hatching in FIG. 6 is obtained, the range in which successful transmission of the DQ signal is observed has not been converged. For this reason, when calibration is performed using the common eye pattern shown by light hatching in FIG. 6, it does not follow that any point within the common eye pattern may be set as a decision point. This is because, as the number of samplings of the DQ signal increases, there remains a possibility that the range in which the influence of noise on the transmission path is observed as a failure in transmission of the DQ signal will expand. As a result, in the example shown in Fig. 6, the range in which successful transmission of the DQ signal is observed may be reduced from the range shown by light hatching in Fig. 6 to the range shown by dark hatching in Fig. 6. This is because there is.

Therefore, from the aspect of suppressing the occurrence of transmission failure even if the range in which successful transmission of the DQ signal is observed is reduced due to the influence of noise in the transmission path, etc., the common eye pattern shown by thin hatching in Fig. 6 is used. It is preferable to set the decision point at the center of the

Examples of techniques that aim to set a decision point at the center of an eye pattern in this manner include Prior Art 1 and Prior Art 2 described below.

[Prior art 1]
For example, in Prior Art 1, the reference voltage with the maximum number of DQS delay taps on the common eye pattern and the center of the DQS delay taps in the range corresponding to the maximum tap width on the common eye pattern are set as decision points. do.

FIG. 7 is a flowchart showing the procedure of calibration processing according to Prior Art 1. As shown in FIG. 7, eye patterns for each rank are obtained by determining whether the DQ signal is transmitted successfully or unsuccessfully for each combination of the reference voltage of the DQ signal and the delay tap of the DQS signal (step S11).

8 to 10 are diagrams showing examples of eye patterns. FIGS. 8 to 10 show, by way of example only, a matrix in which the vertical axis is the reference voltage in the range of Vref0 to Vref31 and the horizontal axis is the DQS delay tap in the range of -16 to 15. FIG. 8 shows the result of reading from the memory block corresponding to Rank 0 on the memory module M2 inserted into slot A. Further, FIG. 9 shows the result of reading from the memory block corresponding to Rank 0 on the memory module M1 inserted into slot B. Further, FIG. 10 shows the result of reading from the memory block corresponding to Rank 1 on the memory module M1 inserted into slot B.

As shown in FIGS. 8 to 10, as a result of plotting the readout results of the DQ signals, an eye pattern appears as a region in which "0" points corresponding to successful transmission are connected, as indicated by hatching. According to the eye patterns shown in FIGS. 8 to 10, the shape of the eye pattern is different for each memory module M2 and memory module M1, and the shape of the eye pattern is also different for each rank of the same memory module M1. That is clear.

After executing step S11, an eye pattern common to all ranks (all slots and all ranks) is created by adding together the eye patterns created for each rank in step S11 for each same channel (step S12). FIG. 11 is a diagram showing an example of a common eye pattern. In the matrix shown in FIG. 11, the readout result values shown in FIG. 8, the readout result values shown in FIG. 9, and the readout result values shown in FIG. 10 are added for each point on the matrix. The combined total value is plotted. In FIG. 11, an example is given in which memory blocks for a total of three ranks, Rank 0 of slot A, Rank 0 of slot B, and Rank 1 of slot B, are controlled by the memory controller 20.

For example, a point where the total value "0" is plotted means that no DQ signal transmission error is observed in all three memory blocks controlled by the memory controller 20. Further, at a point where the total value "1" is plotted, it means that a transmission error of the DQ signal was observed in any one of the three memory blocks controlled by the memory controller 20. Further, at points where the total value "2" is plotted, it means that a transmission error of the DQ signal was observed in two of the three memory blocks controlled by the memory controller 20. Furthermore, at points where the total value "3" is plotted, it means that a transmission error of the DQ signal was observed in all three memory blocks controlled by the memory controller 20.

In this way, the area where points with a total value of "0" are connected, shown by hatching in FIG. 11, is common to all memory blocks corresponding to three ranks: Rank 0 of slot A, Rank 0 of slot B, and Rank 1 of slot B. Created as a common eye pattern.

After executing step S12, a reference voltage with the maximum number of DQS delay taps on the common eye pattern created in step S12 is identified (step S13).

FIG. 12 is a diagram illustrating an example of a method for setting decision points. In FIG. 12, the common eye pattern shown in FIG. 11 is shown, and the reference voltage corresponding to the maximum tap width on the common eye pattern is shown by a frame line. As shown by the frame line in FIG. 12, in the common eye pattern, the number of taps "23" corresponding to the range of DQS delay taps from -15 to 7 is the maximum tap width. Thus, in step S13, the reference voltage "Vref15" corresponding to the maximum tap width "23" on the common eye pattern is identified.

At this time, if there is not a plurality of maximum tap widths (No in step S14), the reference voltage identified in step S13 is set as the decision point (step S18). For example, in the example of the common eye pattern shown in FIG. 12, the maximum tap width is only one reference voltage "Vref15", so Vref15 is set as the reference voltage of the decision point.

On the other hand, if there are a plurality of maximum tap widths (Yes in step S14), the median value of the plurality of reference voltages corresponding to the plurality of maximum tap widths is calculated (step S15). At this time, if there is one median value (No in step S16), the median value of the plurality of reference voltages corresponding to the plurality of maximum tap widths is set as the decision point (step S18).

Here, if a plurality of median values exist (Step S16 Yes), the median value on the side with a larger tap width is selected from among the reference voltages adjacent above and below the reference voltage with the maximum tap width (Step S17). Then, the median value of the reference voltages selected in step S17 is set as a decision point (step S18).

FIG. 13 is a diagram showing another example of the common eye pattern. FIG. 13 shows another common eye pattern different from the common eye pattern shown in FIG. 11. In the example of the common eye pattern shown in FIG. 13, the number of taps is "9" for all four reference voltages Vref12 to Vref15, which is the maximum tap width. In this case, two reference voltages, Vref13 and Vref14, are calculated as the median value of the four reference voltages. In this case, as shown by the thin frame lines in FIG. 13, the number of taps of the common eye pattern in Vref11 adjacent to the lower side of Vref12 is "4", and the number of taps of the common eye pattern in Vref16 adjacent to the upper side of Vref15 is "4". 5" is compared. Comparing these two, the number of taps "5" in the Vref 16 adjacent to the upper side is larger than the number of taps "4" in the Vref 11 adjacent to the lower side. As a result, as shown by the thick frame line in FIG. 13, the upper one of Vref13 and Vref14 corresponding to the two median values is selected and set as the reference voltage of the decision point.

After executing step S18, the DQS delay tap that is the center of the range of DQS delay taps on the common eye pattern corresponding to the reference voltage set in step S18 is set as the timing of the decision point (step S19). For example, in the example of the common eye pattern shown in FIG. 12, with reference voltage "Vref15" corresponding to the maximum tap width of the common eye pattern, DQS delay taps in the range of -15 to 7 are included in the common eye pattern. . In this case, as shown in the black and white inverted display in Figure 12, the center DQS delay tap "-4" where the number of taps from the left end and the number of taps from the right end are both "11" is the timing of the decision point. Set.

[Prior art 2]
In prior art 2, the center of the reference voltage range corresponding to the DQS delay tap where the number of codes of the reference voltage is maximum on the common eye pattern is calculated as the first center point. Furthermore, in Prior Art 2, the center of the range of DQS delay taps corresponding to the reference voltage with the maximum number of DQS delay taps on the common eye pattern is calculated as the second center point. In addition, in Prior Art 2, the centers of the first center point and the second center point are set as decision points.

FIG. 14 is a flowchart showing the procedure of calibration processing according to Prior Art 2. As shown in FIG. 14, eye patterns for each rank are obtained by determining whether the DQ signal is transmitted successfully or unsuccessfully for each combination of the reference voltage of the DQ signal and the delay tap of the DQS signal (step S21).

After executing step S21, an eye pattern common to all ranks (all slots and all ranks) is created by adding together the eye patterns created for each rank in step S21 for each same channel (step S22).

Next, one unselected DQS delay tap is selected from the range of DQS delay taps for which the eye pattern was created in step S21, for example, from -16 to 15 (step SA23). Then, the chord height on the common eye pattern at the DQS delay tap selected in step SA23 is calculated (step SA24). Thereafter, the processes of step SA23 and step SA24 are repeatedly executed until all DQS delay taps are selected (No in step SA25).

If all the DQS delay taps are selected (step SA25 Yes), the DQS delay tap with the maximum code height on the common eye pattern is extracted from among the DQS delay taps (step SA26). Then, the point at which the reference voltage is centered at the code height on the common eye pattern corresponding to the DQS delay tap extracted at step SA26 is extracted as the first center point (step SA27).

FIG. 15 is a diagram illustrating an example of a method for extracting the first center point. In FIG. 15, a common eye pattern is shown, and the DQS delay tap corresponding to the maximum code height on the common eye pattern is shown with a frame line. As shown by the frame line in FIG. 15, in the common eye pattern, the maximum chord height is "17", which is the number of chords corresponding to the chord heights from Vref10 to Vref26, so the DQS delay tap "-2" is extracted. . At the DQS delay tap "-2" corresponding to the maximum code height of the common eye pattern, reference voltages in the range from Vref10 to Vref26 are included in the common eye pattern. In this case, as shown in black and white inverted display in FIG. 15, the center where the number of codes from the bottom and the number of codes from the top are both "8", that is, the DQS delay tap "-2" and the reference voltage " Point A of "Vref18" is extracted as the first central point.

Furthermore, one unselected reference voltage is selected from the range of reference voltages for which the eye pattern was created in step S21, for example, the range from Vref0 to Vref31 (step SB23). Then, the tap width on the common eye pattern at the reference voltage selected in step SB23 is calculated (step SB24). Thereafter, the processes of step SB23 and step SB24 are repeatedly executed until all reference voltages are selected (No in step SB25).

If all the reference voltages are selected (Step SB25 Yes), the reference voltage with the maximum tap width on the common eye pattern is extracted from among the reference voltages (Step SB26). Then, the point that is the center of the DQS delay tap with the tap width on the common eye pattern corresponding to the reference voltage extracted in step SB26 is extracted as the second center point (step SB27).

FIG. 16 is a diagram illustrating an example of a method for extracting the second center point. FIG. 16 shows a common eye pattern that is the same as the common eye pattern shown in FIG. 15, and also shows a reference voltage corresponding to the maximum tap width on the common eye pattern with a frame line. As shown by the frame line in FIG. 16, in the common eye pattern, the maximum tap width is "23", which is the number of taps corresponding to the tap widths from -15 to 7, so the reference voltage "Vref15" is extracted. For reference voltage "Vref15" corresponding to the maximum tap width of the common eye pattern, DQS delay taps in the range of -15 to 7 are included in the common eye pattern. In this case, as shown in black and white inverted display in FIG. 16, the center where the number of taps from the left and the number of taps from the right are both "11", that is, the DQS delay tap "-4" and the reference voltage "Vref15". ” point B is extracted as the second central point.

Then, the centers of the first center point and the second center point are set as decision points (step S28). FIG. 17 is a diagram illustrating an example of a method for setting decision points. FIG. 17 shows a common eye pattern that is the same as the common eye pattern shown in FIGS. 15 and 16. Furthermore, in FIG. 17, the first center point A and the second center point B are shown in black and white inverted display on the common eye pattern, and the centers of the first center point A and the second center point B are also shown. C is shown surrounded by a frame. As shown in FIG. 17, the first center point A of the DQS delay tap "-2" and the reference voltage "Vref18" and the second center point B of the DQS delay tap "-4" and the reference voltage "Vref15". The center point C is set as the decision point. That is, point C of the DQS delay tap "-3" and the reference voltage "Vref17" is set as the decision point.

[One aspect of the issue]
Both of the above-mentioned prior art 1 and the above-mentioned prior art 2 have limitations in appropriately setting decision points.

For example, in the above-mentioned prior art 1, the timing (center of the maximum tap width) at which setup and hold are equal is set as the decision point with respect to the reference voltage that is the maximum tap width of the DQS delay tap on the common eye pattern. Ru.

However, in the above-mentioned prior art 1, since the balance in the vertical direction (height direction) of the common eye pattern is ignored, there are cases where the decision point is set at a point that is vertically shifted from the center of the common eye pattern. Occur.

One of the reasons why such cases occur is related to the silhouette shape of the common eye pattern. In other words, the above-mentioned prior art 1 merely assumes that the silhouette shape of the common eye pattern is a circle or ellipse that is vertically and horizontally symmetrical. Difficult to set points appropriately.

FIG. 18 is a diagram illustrating an example of calibration failure in Prior Art 1. In FIG. 18, a common eye pattern having a distorted silhouette shape is shown, and the decision points set on the common eye pattern according to the above-mentioned prior art 1 are shown in black and white inverted display. As shown in FIG. 18 in black and white inverted display, in the above-mentioned prior art 1, decision points are set as follows. In other words, the decision point includes the reference voltage "Vref15" at which the maximum number of DQS delay taps on the common eye pattern is "23" and the DQS delay tap at the center of the range corresponding to the maximum tap width on the common eye pattern. A point of "-4" is set.

In this way, in the above-mentioned prior art 1, if the reference voltage that is the maximum tap width is located below the center of the common eye pattern, the reference voltage of the decision point is also set below the center of the common eye pattern. . For example, in the example shown in FIG. 18, the number of codes from the decision point to the lower boundary of the common eye pattern is smaller than the number of codes from the decision point to the upper boundary of the common eye pattern. As a result, the decision points set by the above-mentioned prior art 1 may not be able to suppress data transmission errors.

For example, FIG. 18 shows an example in which the common eye pattern shrinks from the range shown by light hatching in FIG. 18 to the range shown by dark hatching in FIG. 18 as the number of samplings of the DQ signal increases. has been done. That is, in the common eye pattern shown by dark hatching in FIG. 18, the number of codes is reduced by 6 codes on the top and bottom, and by 6 codes on the left and right, compared to the common eye pattern shown in FIG. 18 by light hatching. In this case, the decision point set by the above-mentioned prior art 1 is not included in the common eye pattern shown by dark hatching in FIG. 18 and is located outside the common eye pattern, which may cause a data transmission error. Gender arises.

In addition, in the above-mentioned prior art 2, the center between the first center point A, which is the center of the maximum code height on the common eye pattern, and the second center point B, which is the center of the maximum tap width on the common eye pattern. Point C, where , is set as a decision point.

However, in the above-mentioned prior art 2, as in the above-mentioned prior art 1, it is merely a premise that the silhouette shape of the common eye pattern is a circle or an ellipse that is vertically and horizontally symmetrical. Therefore, even in the above-mentioned prior art 2, it is difficult to appropriately set a decision point in a common eye pattern having a distorted silhouette shape.

FIG. 19 is a diagram illustrating an example of calibration failure in Prior Art 2. FIG. 19 shows a common eye pattern with a distorted silhouette shape. Further, in FIG. 19, the first center point A and the second center point B calculated by the above-mentioned prior art 2 on the common eye pattern are shown with thick frame lines, and the decision point C is shown with a black and white inversion. shown in the display.

As shown by the thin frame line in FIG. 19, at the DQS delay tap "-9" corresponding to the maximum code height of the common eye pattern, reference voltages in the range from Vref10 to Vref26 are included in the common eye pattern. In this case, as shown by the thick frame line in FIG. 19, the center where the number of codes from the bottom and the number of codes from the top are both "8", that is, the DQS delay tap "-9" and the reference voltage "Vref18". '' is extracted as the first central point A. Further, as shown by the thin frame line in FIG. 19, at the reference voltage "Vref15" corresponding to the maximum tap width of the common eye pattern, DQS delay taps in the range of -13 to 5 are included in the common eye pattern. In this case, as shown by the thick frame line in FIG. 19, the center where the number of taps from the left side and the number of taps from the right side are both "9", that is, the DQS delay tap "-4" and the reference voltage "Vref15". is extracted as the second center point B.

Then, as shown in black and white inverted display in FIG. 19, the first central point A of the DQS delay tap "-9" and the reference voltage "Vref18", '' is set as the decision point. That is, point C of the DQS delay tap "-7" and the reference voltage "Vref16" is set as the decision point.

In this way, in the above-mentioned prior art 2, when the silhouette shape of the common eye pattern is a distorted shape, the decision point is set at a position shifted from the center of the common eye pattern. For example, in the example shown in FIG. 19, the number of codes from the decision point to the lower boundary of the common eye pattern is smaller than the number of codes from the decision point to the upper boundary of the common eye pattern. Additionally, the number of codes from the decision point to the left border of the common eye pattern is less than the number of codes from the decision point to the right border of the common eye pattern. As a result, data transmission errors may not be suppressed even with the decision points set by the above-mentioned prior art 2.

For example, FIG. 19 shows an example in which the common eye pattern shrinks from the range shown by light hatching in FIG. 19 to the range shown by dark hatching in FIG. 19 as the number of samplings of the DQ signal increases. has been done. That is, in the common eye pattern shown by dark hatching in FIG. 19, the number of codes is reduced by 6 codes on the top and bottom, and by 6 codes on the left and right, compared to the common eye pattern shown by light hatching in FIG. In this case, the decision point set by the conventional technique 2 described above is not included in the common eye pattern shown by dark hatching in FIG. Gender arises.

[One aspect of problem-solving approach]
Therefore, in the calibration method according to this embodiment, among the maximum points where the minimum value of the margins up to the upper, lower, left, and right boundaries of the common eye pattern is maximum, the maximum point where the balance of the number of upper, lower, left, and right margins satisfies a predetermined standard is determined. Set to point. Furthermore, in the calibration method according to the present embodiment, if there is no maximum point that satisfies the criteria, the balance of the number of upper, lower, left, and right margins among the semi-maximum points whose minimum margin value is similar to the maximum value is the semi-maximum point that satisfies the predetermined criteria. Set a point as a decision point.

FIG. 20 is a flowchart showing the procedure of calibration processing according to the first embodiment. As shown in FIG. 20, in step S1, the maximum point at which the minimum value of the number of codes and the number of margins of the number of taps up to the upper, lower, left, and right boundaries of the common eye pattern is calculated. Subsequently, in step S2, the maximum point with the best balance between the number of upper, lower, left, and right margins is extracted from among the maximum points calculated in step S1.

Thereafter, in step S3, if the balance of the number of margins on the top, bottom, left, and right sides of the maximum point extracted in step S2 does not satisfy a predetermined standard, the minimum value of the number of margins is set to a predetermined value below the maximum point calculated in step S1, For example, a semi-maximum point smaller by "1" is calculated, and step S2 is re-executed.

Then, in step S4, if there are a plurality of maximum points or semi-maximum points confirmed to satisfy the criteria in step S3, two of the plurality of maximum points or plural semi-maximum points are used to balance the diagonal direction. The representative point with the best value is calculated.

Then, in step S5, if the minimum number of margins of the representative point calculated in step S4 is the same as the minimum number of margins calculated in step S1, the representative point calculated in step S4 is used as the decision point. set to points. Note that if the minimum value of the number of margins of the representative point calculated in step S4 is smaller than the minimum value of the number of margins calculated in step S1, at least one of the two points used in step S4 is changed and the step S4 is re-executed.

The calibration according to the above-mentioned prior art 1 and the above-mentioned prior art 2 will be compared with the calibration according to this embodiment using FIGS. 21 to 23.

FIG. 21 is a diagram illustrating an example of setting a decision point in Prior Art 1 and Example 1. FIG. 21 shows a common eye pattern that is the same as the common eye pattern shown in FIG. Further, on the common eye pattern shown in FIG. 21, the decision points set according to the above-mentioned prior art 1 are shown with dark hatching, and the decision points set according to the present embodiment are shown in reverse black and white. There is.

Comparing these two arrangements, it is found that the decision point set by the above-mentioned prior art 1 is located below the center of the common eye pattern, whereas the decision point set by this embodiment is located below the center of the common eye pattern. It is clear that it is located approximately at the center of .

FIG. 22 is a diagram illustrating an example of setting a decision point in Prior Art 2 and Example 1. FIG. 22 shows a common eye pattern that is the same as the common eye pattern shown in FIG. Furthermore, on the common eye pattern shown in FIG. 22, the decision points set by the above-mentioned prior art 2 are shown with dark hatching, and the decision points set by this embodiment are shown in reverse black and white. There is.

Comparing these two arrangements, it is found that the decision point set by the above-mentioned prior art 2 is located at the lower left side of the center of the common eye pattern, whereas the decision point set by this embodiment is located at the lower left side of the center of the common eye pattern. It is clear that it is located approximately at the center of .

FIG. 23 is a diagram illustrating an example of the number of margins on the top, bottom, left and right sides. FIG. 23 shows the number of margins up to the upper, lower, left, and right boundaries of the common eye pattern for each decision point according to the prior art 1 and the present embodiment shown in FIG. 21. As shown in FIGS. 21 and 23, in the decision point set by the above-mentioned prior art 1, the number of blank spaces on the top, bottom, left and right is as follows. That is, the number of codes to the upper border of the common eye pattern is "10", the number of codes to the lower border of the common eye pattern is "5", the number of taps to the left border of the common eye pattern is "11", and the number of taps to the left border of the common eye pattern is "11". The number of taps to the right border of the pattern is "11". On the other hand, in the decision point set according to this embodiment, the number of blank spaces on the top, bottom, left and right sides is as follows. That is, the number of codes to the upper border of the common eye pattern is "7", the number of codes to the lower border of the common eye pattern is "8", the number of taps to the left border of the common eye pattern is "10", and the number of taps to the left border of the common eye pattern is "10". The number of taps to the right border of the pattern is "11".

Here, the following is clear from a comparison of the number of vertical and horizontal margins according to Prior Art 1 and the number of vertical and horizontal margins according to this embodiment. For example, in Conventional Technology 1, the number of upper codes is "10" while the number of lower codes is "5", so it can be seen that there is only about half the margin below the decision point as above. . On the other hand, in this example, the number of upper codes is "7" while the number of lower codes is "8", so it can be seen that the number of codes is almost the same above and below the decision point. . From these facts, it is clear that the decision points set according to this embodiment have better balance in the number of upper and lower margins than the decision points set according to the prior art 1 described above. Furthermore, in the decision point according to the above-mentioned prior art 1, as shown by hatching in FIG. 23, the number of lower codes with the smallest margin among the numbers of upper, lower, left, and right margins is "5". On the other hand, in the decision point according to this embodiment, as shown by hatching in FIG. 23, the number of upper codes having the smallest margin among the numbers of upper, lower, left, and right margins is "7". From these facts, it is clear that in this example, compared to the above-mentioned prior art 1, it is possible to set a decision point that is more robust even in situations where the common eye pattern shrinks in any direction, up, down, left, or right. It is.

Further, FIG. 23 shows the number of margins up to the upper, lower, left, and right boundaries of the common eye pattern for each decision point according to the prior art 2 and the present embodiment shown in FIG. 22. As shown in FIGS. 22 and 23, in the decision point set by the above-mentioned prior art 2, the numbers of margins on the top, bottom, left and right are as follows. That is, the number of codes to the upper border of the common eye pattern is "9", the number of codes to the lower border of the common eye pattern is "6", the number of taps to the left border of the common eye pattern is "5", and the number of taps to the left border of the common eye pattern is "5". The number of taps to the right border of the pattern is "12". On the other hand, in the decision point set according to this embodiment, the number of blank spaces on the top, bottom, left and right sides is as follows. That is, the number of codes to the upper border of the common eye pattern is "7", the number of codes to the lower border of the common eye pattern is "8", the number of taps to the left border of the common eye pattern is "8", and the number of taps to the left border of the common eye pattern is "8". The number of taps to the right border of the pattern is "8".

Here, the following is clear from a comparison of the number of vertical and horizontal margins according to the second prior art and the number of vertical and horizontal margins according to the present embodiment. For example, in conventional technology 2, the number of upper codes is "9" and the number of lower codes is "6", so the vertical ratio of the upper and lower sides of the decision point is about 3:2. I understand that there is something. Furthermore, in Prior Art 2, the number of taps on the left side is "5" while the number of taps on the right side is "12", so it can be seen that there is a margin on the left side of the decision point that is less than half of the margin on the right side. On the other hand, in this example, the number of upper codes is "7" while the number of lower codes is "8", so it can be seen that the number of codes is almost the same above and below the decision point. . Furthermore, in this embodiment, the number of taps on the left side is "8" and the number of taps on the right side is also "8", so it can be seen that the number of taps on the left and right sides of the decision point is the same. From these facts, it is clear that the decision points set according to this embodiment are better balanced in the number of vertical and horizontal margins than the decision points set according to the conventional technique 2 described above. Furthermore, in the decision point according to the above-mentioned prior art 2, as shown by hatching in FIG. 23, the number of taps on the left side, which has the smallest margin among the numbers of upper, lower, left and right margins, is "5". On the other hand, in the decision point according to this embodiment, as shown by hatching in FIG. 23, the number of upper codes having the smallest margin among the numbers of upper, lower, left, and right margins is "7". From these facts, it is clear that in this example, compared to the above-mentioned prior art 2, it is possible to set a decision point that is more robust even in situations where the common eye pattern shrinks in any direction, up, down, left, or right. It is.

As described above, according to the calibration method according to the present embodiment, it is possible to set decision points more appropriately than in the above-described prior art 1 and the above-described prior art 2. Therefore, even if the silhouette shape of the common eye pattern is deformed into a distorted shape due to various factors such as the mounting status of memory modules and process variations in processors and memories, the occurrence of transmission errors can be suppressed. Therefore, it becomes possible to mount memory modules with different characteristics such as memory capacity, rank, vendor, etc. on the same memory channel.

[Configuration of information processing device 1]
FIG. 24 is a diagram illustrating a configuration example of the information processing device 1 according to the first embodiment. As shown in FIG. 24, the information processing device 1 includes a CPU 10, a memory controller 20, an I/O (Input/Output) circuit 30, transmission lines Ch1 to Chn, and memory modules M0 to Mn. Note that although the CPU 10 and the memory controller 20 are shown separately in FIG. 24 just as an example, the CPU 10 may include the memory controller 20 built-in.

The memory controller 20 is a controller that controls memory access to n memory modules M0 to Mn. The memory controller 20 is connected to n memory modules M0 to Mn via an I/O circuit 30 and transmission lines Ch1 to Chn. As an example of such memory modules M0 to Mn, a DIMM (Dual Inline Memory Module) equipped with a plurality of DRAM (Dynamic Random Access Memory) chips can be installed. Although FIG. 24 shows an example in which n memory modules M0 to Mn are connected to each of n transmission lines Ch1 to Chn, any number of transmission lines and memory modules may be used. Furthermore, although FIG. 24 shows a dual-rank memory module of Rank0 and Rank1 as an example, a single-rank or quad-rank memory module may be used.

For example, the memory controller 20 performs various processes such as generation of a DQ signal, generation of a DQS signal, and determination of success or failure in reading a DQ signal under control from a hardware processor such as the CPU 10. Here, reading of the DQ signal is executed for each rank of the DQ signal, the transmission lines Ch1 to Chm, and the memory modules M0 to Mn, and the result of reading the DQ signal is written to a register or the like (not shown).

Here, as an example only, FIG. 24 shows an example in which the CPU 10 executes a program stored in a ROM (Read Only Memory) not shown, such as firmware such as a calibration program that implements the above-described calibration method. ing. This is just an example, and of course the firmware may be executed by a processor other than the CPU 10, such as a service processor that functions as a remote management device.

By executing such firmware, the information processing device 1 functions as an acquisition unit 11, an extraction unit 12, a determination unit 13, and a setting unit 14, as shown in FIG.

The acquisition unit 11 acquires the transmission result of the DQ signal from the memory controller 20 for each combination of the reference voltage of the DQ signal and the delay tap of the DQS signal. In this way, by acquiring the DQ signal transmission results for each rank, eye patterns for each rank can be obtained. By adding up the eye patterns for each rank, a common eye pattern common to each rank is created.

The extraction unit 12 extracts the maximum point at which the minimum number of blank spaces up to the upper, lower, left, and right boundaries of the common eye pattern is maximum. Hereinafter, the minimum value among the four numbers of margins up to the upper, lower, left, and right boundaries of the common eye pattern may be referred to as a "minimum margin value." The determination unit 13 determines whether the balance of the number of margins above, below, left and right of the maximum point satisfies a predetermined criterion. At this time, if there is no maximum point that satisfies the predetermined criterion, the extraction unit 12 extracts a quasi-maximum point whose minimum margin value is similar to the maximum value. The setting unit 14 sets a maximum point or a semi-maximum point that satisfies a predetermined criterion as a decision point.

[Processing flow]
Next, a detailed process flow of the information processing device 1 according to this embodiment will be described. 25 and 26 are detailed flows (1) and (2) showing the procedure of the calibration process according to the first embodiment. This calibration process can be executed, by way of example only, as part of a POST (Power On Self-Test) executed when the information processing device 1 is powered on or reset.

As shown in FIG. 25, the acquisition unit 11 acquires eye patterns for each rank from the memory controller 20 (step S101). As an example, an example will be given in which memory blocks for a total of three ranks, Rank 0 of slot A, Rank 0 of slot B, and Rank 1 of slot B, are controlled by the memory controller 20.

In this case, the acquisition unit 11 can acquire the three eye patterns shown in FIGS. 8 to 10 from the memory controller 20. For example, FIG. 8 shows the result of reading from the memory block corresponding to Rank 0 on the memory module M2 inserted into slot A. Further, FIG. 9 shows the result of reading from the memory block corresponding to Rank 0 on the memory module M1 inserted into slot B. Further, FIG. 10 shows the result of reading from the memory block corresponding to Rank 1 on the memory module M1 inserted into slot B.

As shown in FIGS. 8 to 10, the readout results of the DQ signals are plotted in a matrix with the reference voltage in the range of Vref0 to Vref31 as the vertical axis and the DQS delay tap in the range of -16 to 15 as the horizontal axis. As a result, an area where "0" points corresponding to successful transmission are connected appears as an eye pattern, which is shown by hatching in FIGS. 8 to 10.

Returning to the explanation of FIG. 25, the acquisition unit 11 creates an eye pattern common to all ranks (all slots and all ranks) by adding together the eye patterns created for each rank in step S11 for each same channel. (Step S102).

For example, the read result values shown in FIG. 8, the read result values shown in FIG. 9, and the read result values shown in FIG. 10 are added for each point on the matrix. For example, a point where the total value "0" is plotted means that no DQ signal transmission error is observed in all three memory blocks controlled by the memory controller 20. Further, at a point where the total value "1" is plotted, it means that a transmission error of the DQ signal was observed in any one of the three memory blocks controlled by the memory controller 20. Further, at points where the total value "2" is plotted, it means that a transmission error of the DQ signal was observed in two of the three memory blocks controlled by the memory controller 20. Furthermore, at points where the total value "3" is plotted, it means that a transmission error of the DQ signal was observed in all three memory blocks controlled by the memory controller 20. In this way, the area where points with a total value of "0" are connected, shown by hatching in FIG. 11, is common to all memory blocks corresponding to three ranks: Rank 0 of slot A, Rank 0 of slot B, and Rank 1 of slot B. Created as a common eye pattern.

Then, the extraction unit 12 selects one point corresponding to the combination of the DQS delay tap and reference voltage (step S103). Next, the extraction unit 12 calculates the number of margins from the point selected in step S103 to the upper, lower, left, and right boundaries of the common eye pattern (step S104). Note that in step S103, an example was given in which all points on the matrix are selected, but the number of blank spaces at points outside the common eye pattern is set to "0" in all directions, and the selection is limited to points on the common eye pattern. It is okay to make a choice.

FIG. 27 is a diagram illustrating an example of a method for calculating the number of blank spaces. In FIG. 27, point X on the common eye pattern shown in FIG. 11 is shown in black and white inverted display. As shown in Figure 27, when point X located at DQS delay tap "-8" and reference voltage "Vref19" is selected, the number of margins in the four directions of the top, bottom, left, and right of point X can be calculated as follows. .

For example, when the upper code number of point X is calculated, points of "0" located above point X and corresponding to successful transmission are counted. In this case, five points from the point of DQS delay tap "-8" and reference voltage "Vref20" to the point of DQS delay tap "-8" and reference voltage "Vref24" are incremented. As a result, the number of upper codes of point X is determined to be "5".

Furthermore, when the number of codes below point X is calculated, points of "0" located below point X and corresponding to successful transmission are counted. In this case, nine points from the point of DQS delay tap "-8" and reference voltage "Vref18" to the point of DQS delay tap "-8" and reference voltage "Vref10" are incremented. As a result, the number of upper chords at point X is determined to be "9".

Furthermore, when the number of taps on the left side of point X is calculated, points of "0" located on the left side of point X and corresponding to successful transmission are counted. In this case, five points from the point of DQS delay tap "-9" and reference voltage "Vref19" to the point of DQS delay tap "-13" and reference voltage "Vref19" are incremented. As a result, the number of taps on the left side of point X is determined to be "5".

Furthermore, when the number of taps on the right side of point X is calculated, points of "0" located on the right side of point X and corresponding to successful transmission are counted. In this case, 14 points from the point of DQS delay tap "-7" and reference voltage "Vref19" to the point of DQS delay tap "8" and reference voltage "Vref19" are incremented. As a result, the number of taps on the right side of point X is determined to be "14".

Then, the processes of step S103 and step S104 described above are repeated until all points on the matrix corresponding to all combinations of DQS delay taps and reference voltages are selected (No in step S105).

As a result, the number of margins from each point on the matrix to the four-direction boundary of the common eye pattern (up, down, left, and right) is obtained as four maps: the number of upper codes, the number of lower codes, the number of left taps, and the number of right taps.

FIG. 28 is a diagram showing an example of a map of the number of upper codes. FIG. 29 is a diagram showing an example of a map of the number of lower codes. FIG. 30 is a diagram illustrating an example of a map of the number of taps on the left side. FIG. 31 is a diagram illustrating an example of a map of the number of taps on the right side. At each point of the four maps shown in FIGS. 28 to 31, the number of upper chords, the number of lower chords, the number of left taps, and the number of right taps calculated for each point on the matrix shown in FIG. 11 are plotted. Ru. Furthermore, in the example of point is mapped to the position of point X on the map. Further, the lower code number "9" calculated as explained using FIG. 27 is mapped to the position of point X on the lower code number map shown in FIG. Furthermore, the number of left taps "5" calculated as explained using FIG. 27 is mapped to the position of point X on the map of the number of left taps shown in FIG. Further, the number of right taps "14" calculated as explained using FIG. 27 is mapped to the position of point X on the map of the number of right taps shown in FIG. 31.

Returning to the explanation of FIG. 25, if all points on the matrix are selected (Step S105 Yes), the extraction unit 12 extracts the minimum value among the number of top, bottom, left and right margins for each point on the matrix (Step S106). .

For example, the following process is performed for each point on a matrix whose vertical axis is the reference voltage in the range of Vref0 to Vref31 and whose horizontal axis is the DQS delay tap in the range of -16 to 15. That is, the minimum value among the number of upper chords shown in FIG. 28, the number of lower chords shown in FIG. 29, the number of left taps shown in FIG. 30, and the number of right taps shown in FIG. 31 is the minimum margin value. is extracted as As a result, a map of the minimum margin value shown in FIG. 32 is obtained.

FIG. 32 is a diagram showing an example of a map of the minimum margin value. FIG. 32 shows a margin created from the map of the number of upper chords shown in FIG. 28, the map of the number of lower chords shown in FIG. 29, the map of the number of left taps shown in FIG. 30, and the map of the number of right taps shown in FIG. 31. A map of minimum values is shown. For example, in the case of point X indicated by a frame line in FIG. 32, the number of upper chords shown in FIG. The minimum value "5" among the left tap number "5" shown in FIG. 31 and the right tap number "14" shown in FIG. 31 is extracted as the minimum margin value.

Returning to the explanation of FIG. 25, the extraction unit 12 extracts the maximum point corresponding to the maximum value P from among the minimum margin values extracted for each point in step S106 (step S107). For example, in the example of the map of the minimum margin value shown in FIG. 32, the maximum value P is "7". Therefore, in step S107 above, the 16 points where the maximum value P of the minimum margin value is plotted, that is, the 16 points where the maximum value "7" is plotted in reverse black and white in FIG. 32 are extracted. Ru.

Subsequently, the determination unit 13 calculates the total value Q of the difference between the number of upper and lower chords and the difference between the number of left and right taps for each maximum point extracted in step S107 (step S108). Hereinafter, the difference between the number of upper and lower chords will be referred to as the "upper and lower balance value", and the difference between the number of left and right taps will be referred to as the "left and right balance value", as well as the upper and lower balance values and the left and right balance values. The total value is sometimes referred to as "up/down/left/right balance value." The "balance value" here refers to the degree of vertical symmetry, horizontal symmetry, or vertical and horizontal symmetry. For example, as the balance value approaches "0", symmetry approaches, and as the balance value increases, the degree of asymmetry increases. .

FIG. 33 is a diagram showing an example of a map of upper and lower balance values. In FIG. 33, the upper and lower balance values are plotted for each of the 16 maximum points extracted from the map of the minimum margin value shown in FIG. 32. Further, in FIG. 33, one maximum point p1 among the 16 maximum points is indicated by a frame line. Taking the maximum point p1 shown in FIG. 33 as an example, the vertical balance value of the point p1 is calculated from the difference between the number of upper chords and the number of lower chords of the point p1. For example, above point p1, there are six points from the DQS delay tap "-4" and reference voltage "Vref19" point to the DQS delay tap "-4" and reference voltage "Vref24" point. Therefore, the number of upper codes of point p1 is determined to be "6". On the other hand, below point p1, there are seven points from the point of DQS delay tap "-4" and reference voltage "Vref17" to the point of DQS delay tap "-4" and reference voltage "Vref11." Therefore, the number of lower chords of point p1 is determined to be "7". As a result, the upper and lower balance value of point p1 is determined to be "1" by calculating the absolute value |6-7| of the difference between the number of upper chords "6" and the number of lower chords "7" of point p1. .

FIG. 34 is a diagram showing an example of a map of left and right balance values. In FIG. 34, the left and right balance values are plotted for each of the 16 maximum points extracted from the map of the minimum margin values shown in FIG. 32. Further, in FIG. 34 as well, one maximum point p1 among the 16 maximum points is indicated by a frame line. Taking the maximum point p1 shown in FIG. 34 as an example, the left and right balance value of the point p1 is calculated from the difference between the number of taps on the left side and the number of taps on the right side of the point p1. For example, on the left side of point p1, there are eight points from the DQS delay tap "-5" and reference voltage "Vref18" point to the DQS delay tap "-12" and reference voltage "Vref18" point. Therefore, the number of taps on the left side of point p1 is determined to be "8". On the other hand, on the right side of point p1, there are 10 points from the DQS delay tap "-3" and reference voltage "Vref18" point to the DQS delay tap "6" and reference voltage "Vref18" point. Therefore, the number of taps on the right side of point p1 is determined to be "10". As a result, the left-right balance value of point p1 is determined to be "2" by calculating the absolute value |8-10| of the difference between the number of taps on the left side "8" and the number of taps on the right side "10" of point p1.

FIG. 35 is a diagram showing an example of a map of vertical and horizontal balance values. FIG. 35 shows vertical and horizontal balance values for each of the 16 maximum points extracted from the map of the minimum margin value shown in FIG. 32, for example, the vertical balance values shown in FIG. 33 and the vertical balance values shown in FIG. The total value Q of the left and right balance values is plotted. Further, in FIG. 35, one maximum point p2 among the 16 maximum points is shown in reverse black and white. Taking the maximum point p2 shown in FIG. 35 as an example, the vertical and horizontal balance values of the point p2 are calculated from the vertical and horizontal balance values of the point p2. That is, the vertical and horizontal balance values of point p2 are determined by calculating the sum of the vertical balance value of point p2 of "1" and the horizontal balance value of point p2 of "0", for example, "1+0". 1" is found.

Returning to the explanation of FIG. 25, the determination unit 13 extracts the maximum point that is the minimum value Qmin of the vertical and horizontal balance values Q calculated in step S108 from among the maximum points extracted in step S107 (step S109). . Then, the determination unit 13 determines whether the minimum value Qmin of the vertical and horizontal balance values Q is less than or equal to a predetermined threshold Th1, for example "2" (step S110).

Here, if the minimum value Qmin of the vertical and horizontal balance values Q is less than or equal to the above threshold Th1 (Step S110 Yes), the maximum point corresponding to the minimum value Qmin of the vertical and horizontal balance values Q has a good vertical and horizontal balance. It can be determined that In this case, the process moves to step S113 shown in FIG. 26.

For example, in the example of the map of vertical and horizontal balance values shown in FIG. 35, the vertical and horizontal balance value "1" at the maximum point p2 located at the DQS delay tap "-3" and the reference voltage "Vref18" is the minimum It becomes Qmin. The vertical and horizontal balance value "1" of this maximum point p2 is less than or equal to "2", which is an example of the threshold Th1. In this case, the process moves from the aspect of using the maximum point p2 to the setting of the decision point to the process of step S113 shown in FIG. Therefore, in this embodiment, as in the above-mentioned prior art 1, a situation where a point with poor vertical balance, that is, a DQS delay tap "-4" and a reference voltage "Vref15" is used for setting a decision point, is avoided. It can be suppressed.

On the other hand, if the minimum value Qmin of the vertical and horizontal balance values Q exceeds the above threshold Th1 (step S110 No), it is determined that the maximum point corresponding to the minimum value Qmin of the vertical and horizontal balance values Q is poor in the vertical and horizontal balance. can. In this case, the process does not immediately proceed to step S113. That is, the determination unit 13 further determines whether the minimum margin value of the point at which the determination in step S110 was made is the maximum value P (step S111).

At this time, if the minimum margin value of the point for which the determination in step S110 was made is the maximum value P (step S111 Yes), the extraction unit 12 extracts the maximum value P among the minimum margin values extracted for each point in step S106. A semi-maximum point having a semi-maximum value (P-1) corresponding to is extracted (step S112). Note that if the minimum margin value of the point determined in step S110 is not the maximum value P (step S111 No), the process moves to step S113 shown in FIG. 26.

In this way, the reason why the maximum point corresponding to the minimum value Qmin of the vertical and horizontal balance values Q is not immediately used to set the decision point is because the maximum point corresponding to the maximum value P of the minimum margin value does not necessarily provide the best balance between the vertical and horizontal directions. This is because there are cases where this is not the case. Even so, if the minimum margin value is allowed to be subtracted from the maximum value P without limit, even if the vertical and horizontal balance is improved, the margin from the boundary of the common eye pattern will be Becomes shorter.

For this reason, in this embodiment, the decision point candidates are narrowed down to semi-maximum points corresponding to semi-maximum values that are similar to the maximum value P of the minimum margin values. In the following, an example will be given just as an example in which only the value (P-1) next to the maximum value P is allowed as a quasi-maximum value for the maximum value P of the minimum margin value, but any value that is similar to the maximum value P may be used. It is also possible to allow a deviation from the quasi-maximum value (P-1) to the quasi-maximum value (P-α).

FIG. 36 is a diagram showing another example of a common eye pattern. FIG. 36 shows a common eye pattern that is different from the common eye pattern shown in FIG. In the matrix shown in FIG. 36, the total value of the read results of four ranks of memory blocks (not shown) is plotted for each point on the matrix. Using the common eye pattern shown in FIG. 36, the numbers of upper, lower, left, and right margins, such as the number of upper chords, the number of lower chords, the number of left taps, and the number of right taps, are calculated. For example, in the case of point Y located at the DQS delay tap "-8" and the reference voltage "Vref18" indicated by the frame line in FIG. 36, the number of blank spaces in the four directions (top, bottom, left and right) can be calculated as follows. .

For example, when the upper code number of point Y is calculated, points of "0" located above point Y and corresponding to successful transmission are counted. In this case, eight points from the point of DQS delay tap "-8" and reference voltage "Vref19" to the point of DQS delay tap "-8" and reference voltage "Vref26" are incremented. As a result, the number of upper chords at point Y is determined to be "8".

Furthermore, when the number of lower codes of point Y is calculated, points of "0" located below point Y and corresponding to successful transmission are counted. In this case, eight points from the point of DQS delay tap "-8" and reference voltage "Vref17" to the point of DQS delay tap "-8" and reference voltage "Vref10" are incremented. As a result, the number of upper chords at point Y is determined to be "8".

Further, when the number of taps on the left side of point Y is calculated, points of "0" located on the left side of point Y and corresponding to successful transmission are counted. In this case, eight points from the point of DQS delay tap "-9" and reference voltage "Vref18" to the point of DQS delay tap "-16" and reference voltage "Vref18" are incremented. As a result, the number of taps on the left side of point Y is determined to be "8".

Furthermore, when the number of taps on the right side of point Y is calculated, points of "0" located on the right side of point Y and corresponding to successful transmission are counted. In this case, 12 points from the point of DQS delay tap "-7" and reference voltage "Vref18" to the point of DQS delay tap "4" and reference voltage "Vref18" are incremented. As a result, the number of taps on the right side of point X is determined to be "12".

In addition to the point Y illustrated above, the number of margins from each point on the matrix to the four-direction boundary of the common eye pattern (top, bottom, left, and right) is calculated, resulting in the number of upper chords, the number of lower chords, and the number of left taps. and the number of taps on the right side. Thereafter, for each point on the matrix, the minimum value among the number of upper codes, the number of lower codes, the number of left taps, and the number of right taps is extracted as the minimum margin value. As a result, a map of the minimum margin value shown in FIG. 37 is obtained.

FIG. 37 is a diagram illustrating an example of a map of minimum margin values. For example, in the example of point Y indicated by the frame line in FIG. The value "8" is extracted as the minimum margin value. Here, in the example of the map of the minimum margin value shown in FIG. 37, the maximum value P is "8", and only point Y has the maximum value P. Therefore, after only point Y is extracted as the maximum point, the vertical balance value, the horizontal balance value, and the vertical and horizontal balance values are calculated. That is, since the upper and lower chord numbers of the maximum point Y are both "8", the upper and lower balance value of the maximum point Y is determined to be "0". Further, while the number of taps on the left side of the maximum point Y is "8", the number of codes on the right side of the maximum point Y is "12". Therefore, the left-right balance value of the maximum point Y can be found as "4" by calculating the absolute value |8-12| of the difference between the number of taps on the left side of point Y "8" and the number of taps on the right side "12" . Furthermore, the vertical and horizontal balance values of the maximum point Y are calculated by calculating the sum of the vertical balance value of the maximum point Y of "0" and the horizontal balance value of the maximum point Y of "4", for example, "0+4". So, we get "4".

Here, since only the point Y is extracted as the maximum point, the maximum point Y becomes the minimum value Qmin of the vertical and horizontal balance values Q in the common eye pattern shown in FIG. The vertical and horizontal balance value "4" of the maximum point Y exceeds the above-mentioned threshold Th1 "2". As a result, it is determined that the maximum point Y has poor vertical and horizontal balance.

Like the maximum point Y exemplified above, since it has the minimum value Qmin of the vertical and horizontal balance values Q among the maximum points with the maximum value P of the minimum margin value, it does not necessarily mean that it is It doesn't necessarily mean that the balance is good.

In this case, in accordance with the procedure of step S112 shown in FIG. 25, a quasi-maximum point that is a quasi-maximum value (P-1) that is similar to the maximum value P among the minimum margin values shown in FIG. 37 is extracted. For example, in the example of the map of the minimum margin value shown in FIG. 37, the quasi-maximum value (P-1) is "7". Therefore, in step S112 above, the 14 points at which the quasi-maximum value (P-1) of the minimum margin value are plotted, that is, the quasi-maximum value "7" indicated by the frame and underline in FIG. 37 are plotted. 14 points are extracted. The processes of step S108 and step S109 described above are also executed for these 14 semi-maximum points.

FIG. 38 is a diagram showing an example of a map of upper and lower balance values. In FIG. 38, the upper and lower balance values are plotted for each of the 14 semi-maximum points extracted from the map of the minimum margin value shown in FIG. 37. Furthermore, in FIG. 38, one semi-maximal point q1 among the 14 semi-maximal points is indicated by a frame line. Taking the quasi-maximum point q1 shown in FIG. 38 as an example, the vertical balance value of point q1 is calculated from the difference between the number of upper chords and the number of lower chords of point q1. For example, the number of upper chords of point q1 is "6", and the number of lower chords of point q1 is determined to be "7". Therefore, the upper and lower balance value of point q1 can be determined as "1" by calculating the absolute value |6-7| of the difference between the number of upper chords "6" and the number of lower chords "7" of point q1. .

FIG. 39 is a diagram showing an example of a map of left and right balance values. In FIG. 39, left and right balance values are plotted for each of the 14 semi-maximum points extracted from the map of the minimum margin value shown in FIG. 37. Further, in FIG. 39 as well, one semi-maximal point q1 among the 14 semi-maximal points is indicated by a frame line. Taking the quasi-maximum point q1 shown in FIG. 39 as an example, the left-right balance value of the point q1 is calculated from the difference between the number of taps on the left side and the number of taps on the right side of the point p1. For example, the number of taps on the left side of point q1 is "9", and the number of taps on the right side of point q1 is "9". Therefore, the left-right balance value of point q1 is determined to be "0" by calculating the absolute value |9-9| of the difference between the number of taps on the left side "9" and the number of taps on the right side "9" of point q1.

FIG. 40 is a diagram showing an example of a map of vertical and horizontal balance values. FIG. 40 shows vertical and horizontal balance values for each of the 14 semi-maximum points extracted from the map of the minimum margin value shown in FIG. 37, for example, the vertical balance values shown in FIG. The total value Q of the left and right balance values is plotted. Furthermore, in FIG. 40, two semi-maximum points q1 and q2 at which the vertical and horizontal balance values Q are the minimum values are indicated by frame lines. For example, taking the quasi-maximum point q1 shown in FIG. 40 as an example, the vertical and horizontal balance values of point q1 are calculated from the vertical and horizontal balance values of point q1. In other words, the vertical and horizontal balance values of point q1 are determined by calculating the sum of the vertical balance value of point q1 of "1" and the horizontal balance value of point q1 of "0", for example, "1+0". 1" is found. Further, for example, taking the quasi-maximum point q2 shown in FIG. 40 as an example, the vertical and horizontal balance values of the point q2 are calculated from the vertical and horizontal balance values of the point q2. In other words, the vertical and horizontal balance values of point q2 are determined by calculating the sum of the vertical balance value of point q2 of "1" and the horizontal balance value of point q2 of "0", for example, "1+0". 1" is found.

Here, in the example of the map of the vertical and horizontal balance values shown in FIG. 40, the vertical and horizontal balance values "1" at the semi-maximum point q1 and the quasi-maximum point q2 become the minimum value Qmin. The vertical and horizontal balance values "1" of these quasi-maximum points q1 and quasi-maximum points q2 are equal to or less than "2", which is an example of the threshold Th1. In this case, the quasi-maximum point q1 and the quasi-maximum point q2 are determined to have good vertical and horizontal balance.

Returning to the explanation of FIG. 26, if the minimum value Qmin of the upper, lower, left, and right balance values Q of the quasi-maximum point is less than or equal to the threshold Th1 (step S110 Yes), the process moves to step S113 shown in FIG. Moreover, even if the minimum value Qmin of the balance value Q of the upper, lower, left, and right sides of the quasi-maximum point is not equal to or less than the above-mentioned threshold Th1 (No in step S110), no further subtraction of the minimum margin value from the maximum value P is performed. That is, the process branches to No in step S111, and the process moves to step S113 shown in FIG. 26.

If there is one maximum point or quasi-maximum point that is the minimum value Qmin of the vertical and horizontal balance values Q (No in step S113), there are no other options. Therefore, the setting unit 14 sets the maximum point or semi-maximum point that is the minimum value Qmin of the vertical and horizontal balance values Q as the decision point (step S118), and ends the process.

For example, in the example of the map of vertical and horizontal balance values shown in FIG. 35, the maximum point that is the minimum value Qmin of the vertical and horizontal balance values "1" is one of the maximum points p2. In this case, the maximum point p2 is set as the decision point.

On the other hand, if there are multiple maximum points or semi-maximum points that are the minimum value Qmin of the vertical and horizontal balance values Q (step S113 Yes), the setting unit 14 executes the following process. That is, the setting unit 14 extracts the point Q1 where the DQS delay tap is the minimum and the point Q2 where the DQS delay tap is the maximum among the maximum points or semi-maximum points that are the minimum value Qmin of the vertical and horizontal balance values Q ( Step S114).

For example, in the example of the map of vertical and horizontal balance values shown in FIG. 40, the DQS delay tap at the semi-maximum point q1 is "-6", and the DQS delay tap at the semi-maximum point q2 is "-5". It is. Therefore, as a result of the DQS delay tap being smaller than the quasi-maximum point q2, the quasi-maximum point q1 that is the minimum is extracted as the point Q1. On the other hand, as a result of the DQS delay tap being larger than the semi-maximum point q1, the maximal semi-maximum point q2 is extracted as the point Q2.

Note that although an example is given here in which there is one point having the minimum or maximum DQS delay tap, it can also be assumed that there are multiple minimum or maximum DQS delay taps. For example, if there are multiple points having the minimum DQS delay tap, the point with the minimum reference voltage among the multiple points is extracted as point Q1. On the other hand, if there are multiple points having the maximum DQS delay tap, the point with the highest reference voltage among the multiple points is extracted as point Q2. In other words, among the points that have the minimum value Qmin of the vertical and horizontal balance values Q, the point located closest to the lower left is extracted as point Q1, and the point located closest to the upper right is extracted as point Q2. .

Returning to the explanation of FIG. 26, the setting unit 14 calculates the center point R corresponding to the center of the point Q1 and the point Q2 extracted in step S114 (step S115). At this time, from the aspect of giving priority to the point with a smaller DQS delay tap among two adjacent points as the center point R, the setting unit 14 sets the center R by rounding down the decimal point of the DQS delay tap and reference voltage. It can be calculated. Further, when the point Q1 and the point Q2 are adjacent to each other, the setting unit 14 can also select the point Q1 as the center point R, omitting the above calculation.

Then, the setting unit 14 sets the vertical and horizontal balance values of the center point R calculated in step S115 and the minimum value of the vertical and horizontal balance values Q of the maximum point or semi-maximum point that has proceeded to the Yes branch in step S110. Qmin (step S116). In addition, when passing through the branch of said step S111No, you may extract and compare the minimum value Qmin of the balance value Q of the upper, lower, left, and right among the maximum point and the semi-maximum point.

Here, if the upper, lower, left, and right balance values and the minimum value Qmin of the center point R are the same (step S116 Yes), the setting unit 14 sets the center point R calculated in step S115 as the decision point (step S118). , ends the process.

On the other hand, when the vertical and horizontal balance values of the center point R are less than the minimum value Qmin (step S116 No), the setting unit 14 sets the point where the DQS delay tap is the next smallest after point Q1, that is, the point where the DQS delay tap is the second smallest. The point is re-extracted as point Q1' (step S117).

Then, the process returns to step S115, and the center point R corresponding to the center of point Q1' and point Q2 re-extracted in step S117 is calculated again. Thereafter, the order of the DQS delay tap values used as the re-extraction standard is incremented until the balance value of the upper, lower, left, and right sides of the center point R calculated in step S115 becomes the same value as the minimum value Qmin (step S116 No). The processes of step S117 and step S115 described above are looped.

[One aspect of the effect]
As described above, the information processing device 1 according to the present embodiment is configured such that the balance of the number of upper, lower, left, and right margins meets a predetermined standard among the maximum points where the minimum value of margins to the upper, lower, left, and right boundaries of the common eye pattern is maximum. Set the maximum points that satisfy the decision point. Therefore, a point that is excellent in both the size of the margin from the boundary of the common eye pattern and the balance between the top, bottom, left, and right margins on the common eye pattern can be set as the decision point. Therefore, according to the information processing device 1 according to the present embodiment, it is possible to appropriately set decision points.

Further, in the case where there is no maximum point that satisfies the standard, the information processing device 1 according to the present embodiment is configured such that the balance of the number of vertical and horizontal margins satisfies the predetermined standard among the semi-maximum points whose minimum margin value is similar to the maximum value. Set the maximum point to the decision point. Therefore, according to the information processing device 1 according to the present embodiment, the size of the margin from the boundary of the common eye pattern is maintained at a quasi-maximum value, and the balance between the top, bottom, left, and right margins on the common eye pattern is improved. can be set as a decision point.

Regarding the embodiments including the above examples, the following additional notes are further disclosed.

(Additional Note 1) Obtaining the transmission result of the signal for each combination of a reference value used to determine the value of the signal and a delay value for memory access of the signal,
Among the combinations in which the transmission result is a transmission success, the difference between the combination in which the transmission result is a transmission success and the combination in which the transmission result is a transmission failure, the difference between the reference value and the delay value. Extract the maximum point where the minimum value of is the maximum value,
setting a maximum point among the maximum points where the balance between the difference in the reference value and the difference in the delay value satisfies a predetermined criterion as a decision point;
A calibration method in which processing is performed by a processor.

(Additional note 2) The extraction process extracts a semi-maximum point where the minimum value is a semi-maximum value similar to the maximum value, if there is no maximum point that satisfies the criterion,
The setting process is characterized in that, among the semi-maximum points, a semi-maximal point where the balance between the difference in the reference value and the difference in the delay value satisfies a predetermined criterion is set as a decision point. calibration method.

(Additional note 3) The processing to be set is performed until the maximum value when the total value of the difference between the differences on both sides of the reference value up to the boundary and the difference between the differences on both sides of the delay value up to the boundary is less than or equal to a predetermined threshold. The calibration method according to appendix 1 or 2, characterized in that the point is set as a decision point.

(Additional note 4) The acquisition process acquires the transmission result of the signal at each point for each rank of each memory module,
The calibration method according to appendix 1, wherein the extraction process extracts the maximum point using a common combination that corresponds to a combination in which the transmission result is a successful transmission in each rank.

(Additional Note 5) An acquisition unit that acquires the transmission result of the signal for each combination of a reference value used to determine the value of the signal and a delay value for memory access of the signal;
Among the combinations in which the transmission result is a transmission success, the difference between the combination in which the transmission result is a transmission success and the combination in which the transmission result is a transmission failure, the difference between the reference value and the delay value. an extraction unit that extracts the maximum point where the minimum value of is the maximum value;
a setting unit that sets a maximum point among the maximum points where the balance between the difference in the reference value and the difference in the delay value satisfies a predetermined criterion as a decision point;
An information processing device having:

(Supplementary Note 6) If there is no maximum point that satisfies the criterion, the extraction unit extracts a semi-maximal point whose minimum value is a semi-maximal value that is similar to the maximum value,
According to appendix 5, the setting unit sets a semi-maximum point among the semi-maximum points where a balance between the difference between the reference value and the delay value satisfies a predetermined criterion as a decision point. Information processing device.

(Additional Note 7) The setting unit is configured to set a maximum point at which the total value of the difference between the differences on both sides of the reference value up to the boundary and the difference between the differences on both sides of the delay value up to the boundary is less than or equal to a predetermined threshold. 7. The information processing device according to appendix 5 or 6, wherein the information processing device is configured to set a decision point as a decision point.

(Additional Note 8) The acquisition unit acquires the transmission result of the signal at each point for each rank of each memory module,
The information processing device according to appendix 5, wherein the extraction unit extracts the maximum points using a common combination that corresponds to a combination in which the transmission result is a transmission success in common for each rank.

(Additional Note 9) Obtaining the transmission result of the signal for each combination of a reference value used to determine the value of the signal and a delay value for memory access of the signal,
Among the combinations in which the transmission result is a transmission success, the difference between the combination in which the transmission result is a transmission success and the combination in which the transmission result is a transmission failure, the difference between the reference value and the delay value. Extract the maximum point where the minimum value of is the maximum value,
setting a maximum point among the maximum points where the balance between the difference in the reference value and the difference in the delay value satisfies a predetermined criterion as a decision point;
A calibration program whose processing is executed by the processor.

(Additional Note 10) The extraction process extracts a quasi-maximum point where the minimum value is a quasi-maximum value similar to the maximum value, if there is no maximum point that satisfies the criterion;
According to appendix 9, the setting process sets a semi-maximum point among the semi-maximum points where the balance between the difference in the reference value and the difference in the delay value satisfies a predetermined criterion as a decision point. calibration program.

(Additional Note 11) The processing to be set is performed at a maximum value when the total value of the difference between the differences on both sides of the reference value up to the boundary and the difference between the differences on both sides of the delay value up to the boundary is less than or equal to a predetermined threshold. The calibration program according to appendix 9 or 10, characterized in that the point is set as a decision point.

(Additional Note 12) The acquisition process acquires the transmission result of the signal at each point for each rank of each memory module,
9. The calibration program according to appendix 9, wherein the extraction process extracts the maximum points using a common combination that corresponds to a combination in which the transmission result is a successful transmission for each rank.

1 Information processing device 10 CPU
11 Acquisition unit 12 Extraction unit 13 Judgment unit 14 Setting unit 20 Memory controller 30 I/O circuit

Claims (5)

obtaining a transmission result of the signal for each combination of a reference value used to determine the value of the signal and a delay value for memory access of the signal;
In the matrix to which the transmission result is mapped , each of the combinations in which the transmission result is a transmission success is included in the range up to the boundary between the combination in which the transmission result is a transmission success and the combination in which the transmission result is a transmission failure. The number of combinations is determined in each of four directions, including two directions corresponding to the positive and negative directions of the reference value axis in the matrix and two directions corresponding to the positive and negative directions of the delay value axis perpendicular to the reference value axis. Calculate,
Among the combinations for which the transmission result is a successful transmission, extract the maximum combination for which the minimum value among the number of combinations calculated for each of the four directions is the maximum value;
out of the maximum combinations, the maximum combination in which the balance of the number of combinations in the four directions satisfies a predetermined criterion is set as a decision point for determining memory access timing of the signal and the reference value;
A calibration method in which processing is performed by a processor. In the extraction process, if there is no maximum combination that satisfies the criteria, extracting a semi-maximal combination in which the minimum value is a semi-maximum value similar to the maximum value,
The calibration method according to claim 1, wherein the setting process sets, as the decision point, a semi-maximum combination in which a balance of the number of combinations in the four directions satisfies a predetermined criterion among the semi-maximum combinations. . The processing to be set includes the difference between the number of combinations in two directions corresponding to the positive and negative directions of the axis of the reference value among the number of combinations in the four directions , and the difference between the number of combinations in two directions corresponding to the positive and negative directions of the axis of the delay value among the number of combinations in the four directions. 3. The calibration method according to claim 1, further comprising setting the maximum combination as the decision point for which the total value of the difference in the number of combinations in two directions corresponding to the direction is less than or equal to a predetermined threshold value. The acquiring process acquires the transmission result of the signal for each combination of the reference value and the delay value for each rank of a plurality of memory modules;
2. The extracting process extracts the maximum combination using a common combination corresponding to a combination in which the transmission result is a successful transmission in each rank of the plurality of memory modules. Calibration method as described. an acquisition unit that acquires a transmission result of the signal for each combination of a reference value used to determine the value of the signal and a delay value for memory access of the signal;
In the matrix to which the transmission result is mapped , each of the combinations in which the transmission result is a transmission success is included in the range up to the boundary between the combination in which the transmission result is a transmission success and the combination in which the transmission result is a transmission failure. The number of combinations is determined in each of four directions, including two directions corresponding to the positive and negative directions of the reference value axis in the matrix and two directions corresponding to the positive and negative directions of the delay value axis perpendicular to the reference value axis. A calculation unit that calculates;
an extraction unit that extracts a maximum combination in which the minimum value among the number of combinations calculated for each of the four directions is the maximum value among the combinations for which the transmission result is a successful transmission;
a setting unit that sets a maximum combination among the maximum combinations in which the balance of the number of combinations in the four directions satisfies a predetermined criterion as a decision point for determining memory access timing of the signal and the reference value;
An information processing device having:

Images