JP7383273B2 - Information processing device, information processing circuit, information processing system, and information processing method - Google Patents

Description

Article 30, Paragraph 2 of the Patent Act applies: https://ieeexplore. ieee. org/document/8412610/ Masaki Waga and Ichiro Hasuo published the article "Moore-Machine Filtering for Tim" on the Institute of Electrical and Electronics Engineers (IEEE) website "IEEE Xplore Digital Library" published at the above address. ed and Titled ``Untimed Pattern Matching'', the technology related to ``information processing devices, information processing systems, and information processing methods'' invented by Masaki Waga and Ichiro Hasuo was published on July 18, 2018.

The present invention relates to an information processing device that performs filtering for pattern matching, an information processing system including the information processing device, and an information processing method.

For example, Patent Document 1 discloses a time-series correlation extraction device that filters time-series data and can prevent processing from taking a large amount of time even when the number of transactions increases. is disclosed. When searching for a combination of records from a set of records consisting of a plurality of attributes, the time series correlation extraction device according to this conventional example uses a plurality of events each defining that a predetermined attribute in the record takes a specific value; a specification means for specifying a search pattern using an order relationship between the plurality of events defined based on the order of the attribute values, and searching for a combination of records corresponding to the specified search pattern from a set of records; The present invention includes a time series filter section having a search means for searching and an output means for outputting search results, and has a function of extracting time series correlation rules by a time series correlation engine section.

Japanese Patent Application Publication No. 2004-110327 International Publication No. 2004/038620 pamphlet International Publication No. 2012/057170 pamphlet

Eugene Asarin, Oded Maler, Dejan Nickovic, and Dogan Ulus, 2017, Combining the Temporal and Epistemic Dimensions for MTL Monitoring. A. Abate and G. Geeraerts (Eds.), 2017, Proc. FORMATS. LNCS, Vol. 10419. Springer . M. Krichen and S. Tripakis, 2009, Conformance testing for real-time systems, FMSD 34, 3 (2009), 238-304. Leena Salmela, Jorma Tarhio, and Jari Kytojoki, 2006, Multi-pattern string matching with q-grams, ACM Journal of Experimental Algorithmics 11 (2006). D. Ulus, T. Ferrere, E. Asarin, and O. Maler, 2014, Timed Pattern Matching, In Proc. FORMATS, (LNCS), A. Legay and M. Bozga (Eds.), Vol. 8711, Springer, 222-236. Masaki Waga, Ichiro Hasuo, and Kohei Suenaga, 2017, Efficient Online Timed Pattern Matching by Automata-Based Skipping, 224-243.

However, the disclosure also suggests that in the conventional time series correlation extraction device, a finite state machine such as a Moore machine is generated based on an automaton that describes matching conditions, and filtering is performed using the generated finite state machine. Therefore, there was a problem that the process could not be carried out efficiently.

An object of the present invention is to solve the above-mentioned problems, and to provide an information processing apparatus, an information processing system, and an information processing method that perform filtering for pattern matching, in which pattern matching is performed efficiently using filtering compared to the conventional example. An object of the present invention is to provide an information processing device, an information processing system, and an information processing method that can perform the following steps.

An information processing device according to an embodiment of the present invention generates a finite state machine based on predetermined matching conditions regarding input event sequence data, and uses the generated finite state machine to The present invention is characterized by comprising an information processing circuit that outputs sequence data that has been processed so as to substantially remove data that does not match matching conditions.

Therefore, according to the information processing device, information processing system, and information processing method according to the present invention, pattern matching can be performed efficiently using filtering, compared to the conventional example. In particular, compared to conventional real-time constrained pattern matching (without preprocessing by filtering) (e.g., Non-Patent Document 4), filtering allows efficient processing and significantly improves performance. You can improve. Furthermore, compared to conventional examples related to pattern matching using filtering (for example, Non-Patent Document 4), when there is no real-time constraint, a wider range of automata can be allowed as patterns, and when there is a real-time constraint, real-time Able to handle constraints.

FIG. 1 is a block diagram illustrating a configuration example of a physical information system (CPS) according to an embodiment. FIG. 3 is a conceptual diagram showing the relationship between pattern matching processing and filtering processing. 7 is a timing chart showing forward and backward movement processing in pattern matching used in the embodiment. FIG. 7 is a plan view showing an example of a position plot in pattern matching in a conventional document. FIG. 3B is a plan view showing identification of sections in the position plot of FIG. 3B. FIG. 3 is a conceptual diagram showing filtering padding processing in the embodiment. It is a conceptual diagram which shows the filtering process by Moore machine in embodiment. FIG. 2 is a diagram illustrating an example of a pattern that is a non-deterministic finite automaton (NFA) according to an embodiment. FIG. 3 is a diagram illustrating an example of a non-buffer portion of a Moore machine filter according to an embodiment. FIG. 3 is a diagram showing a run of a Moore machine filter for a predetermined character string. 3 is a block diagram illustrating an example of a processing circuit of a prefix information processing circuit according to an embodiment. FIG. 3 is a diagram showing an example of a Moore machine filter for data of an automobile torque sensor according to the first embodiment. FIG. 3 is a diagram showing an example of a Moore machine filter for data of an automobile gear sensor according to the first embodiment. FIG. 3 is a diagram showing an example of a Moore machine filter for data of an automobile accelerator sensor according to the first embodiment. 2 is a graph showing simulation results of a Moore machine filter on data from a torque sensor of an automobile according to Example 1, showing the length of a filtered string with real time versus the input string length with real time. 3 is a simulation result of a Moore machine filter for data of a gear sensor of an automobile according to Example 1, and is a graph showing the length of a filtered string with real time versus the input string length with real time. 3 is a simulation result of a Moore machine filter for data from an automobile accelerator sensor according to Example 1, and is a graph showing the length of a filtered string with real time versus the input string length with real time. 2 is a graph showing simulation results of a Moore machine filter on data from a torque sensor of an automobile according to Example 1, and showing an execution time with respect to an input character string length with real time. 3 is a simulation result of a Moore machine filter for data of a gear sensor of an automobile according to Example 1, and is a graph showing an execution time with respect to an input character string length with real time. 2 is a graph showing simulation results of a Moore machine filter on data from an automobile accelerator sensor according to Example 1, and showing execution time with respect to input character string length with real time. 2 is a graph illustrating a simulation result of a Moore machine filter for data of an automobile torque sensor according to Example 1, and shows a memory usage amount with respect to an input character string length with real time. 3 is a simulation result of a Moore machine filter for data of an automobile gear sensor according to Example 1, and is a graph showing a memory usage amount with respect to an input character string length with real time. 3 is a simulation result of a Moore machine filter for data of an automobile accelerator sensor according to Example 1, and is a graph showing memory usage with respect to input character string length with real time. It is a simulation result of a tool according to a comparative example for data of a torque sensor of a car, and is a graph showing an execution time with respect to an input character string length with real time. It is a simulation result of a tool according to a comparative example for data of a gear sensor of a car, and is a graph showing execution time with respect to input character string length with real time. It is a simulation result of a tool according to a comparative example with respect to data of an accelerator sensor of a car, and is a graph showing execution time with respect to input character string length with real time. FIG. 3 is a block diagram illustrating a configuration example of a prefix information processing circuit according to a second embodiment. FIG. 3 is a diagram illustrating a configuration example of a buffer section. It is a diagram showing an example of a state transition diagram of an automaton. FIG. 3 is a diagram showing an example of a state transition diagram of an automaton described using states with counters. 7 is a diagram illustrating an example of a state transition diagram of a Moore machine according to a second embodiment. FIG. FIG. 7 is a diagram illustrating an example of a state transition table of a Moore machine according to a second embodiment. 7 is a diagram illustrating an example of a state management table of a Moore machine according to a second embodiment. FIG. FIG. 3 is a diagram showing each functional block included in the prefix information processing circuit according to the second embodiment. 7 is a flowchart showing the flow of processing of the prefix information processing circuit according to the second embodiment. 3 is a flowchart showing the flow of processing at the time of state transition of the Moore machine. 7 is a flowchart showing the processing flow of the prefix information processing circuit when using a Moore machine with real-time constraints. 12 is a flowchart showing the flow of processing at the time of state transition of a Moore machine with real-time constraints. It is a flowchart which shows the determinization process of a real-time automaton. 12 is a flowchart showing an approximation process for approximating a real-time constrained automaton to a real-time automaton. FIG. 3 is a block diagram showing a configuration example of a vehicle control system having an automatic stop mechanism in the event of an abnormality according to a third embodiment. FIG. 7 is a block diagram showing a configuration example of a vehicle control system having a driving route optimization mechanism for a semi-connected car according to a fourth embodiment. FIG. 12 is a block diagram illustrating a configuration example of a communication system having a mechanism for monitoring attacks on a server device and blocking access according to a fifth embodiment.

Embodiments and examples according to the present invention will be described below with reference to the drawings. In addition, in each embodiment below, the same code|symbol is attached|subjected about the same component.

Embodiment.
Monitoring is the backbone of real-time, run-time verification techniques for embedded physical information systems. Mathematically, the monitoring problem is formulated as a pattern matching problem for patterned automata. The present inventors have been researching filtering as preprocessing for monitoring, motivated by embedded applications (particularly those where the capacity of the communication path between sensors and the processor that monitors them is limited). , we propose a method to construct a Moore machine that functions as a filter for a given pattern automaton.

The structure is automata-theoretic, and the inventors have found that the use of Moore machines is particularly suited for embedded applications. This is not only because sequential computation by Moore machines is relatively inexpensive, but also because Moore machines are compatible with hardware acceleration using dedicated circuits. We also demonstrate soundness (no missed matches). The present inventors conduct this study in the following situation setting. One is a setting without real-time constraints, in which the pattern is described by a non-deterministic finite automaton (NFA). The other is a setting with real-time constraints, in which the pattern is described as an automaton with real-time constraints. Although extending a no-time configuration to a timed configuration is technically complex, the following embodiments and examples demonstrate its practical benefits. In the embodiment, chapter numbers and section numbers are given for convenience of explanation.

1. Introduction 1.1 Monitoring and pattern matching with real-time constraints

Physical information systems (CPS) are becoming increasingly complex. This is due to the rapid development of digital control, which not only improves the efficiency of cars, such as fuel efficiency, but also realizes new functions such as autonomous driving. Therefore, a proper understanding of such systems remains an important and challenging task.

Due to the complexity of such physical information systems (CPS) and other reasons such as black-box parts provided by other suppliers, formal verification in the traditional sense is difficult to implement in real-world physical information systems (CPS). It is difficult to apply. For this reason, researchers and practitioners have turned their attention to so-called lightweight formal verification. Runtime formal verification is one such effort, in which the execution result sequence of a given system is checked against a given specification. Various algorithms for monitoring have been proposed for this purpose.

Mathematically speaking, one common formulation of the monitoring problem is the pattern matching problem (another common formulation is what we refer to as the pattern search problem. is easier than pattern matching, but yields less information). When the execution result string is given by the string w=a ₁ a ₂ ...a _n , the expected output is the restriction of the string w that satisfies the given pattern pat with the set of subscripts (i, j). A collection of things that represents

である。パターンｐａｔは文字列、文字列の集合、正規表現、あるいはオートマトンなどによって与えられる。また上の式（１）は、ｉ番目からｊ番目までの文字列がパターンｐａｔと一致することを意味する。

It is. The pattern pat is given by a string, a set of strings, a regular expression, an automaton, or the like. Furthermore, the above equation (1) means that the i-th to j-th character strings match the pattern pat.

(Example 1.1): Consider a regular expression given by the character string w1=abbbbbbaab and A1=a(a*)b. There are three matchings here, Match (w ₁ , A ₁ )={(1,2), (7,9), (8,9)}.

In physical information systems (CPS), an important issue is dealing with real-time constrained timed versions of pattern matching. In one common formulation, the execution result sequence is given by a timestamped string. This is a string of characters with a time record, for example, the string w ₂ = (a, 0.1) (b, 2.5) (a, 3.5) (b, 4.8 ). The pattern pat is given by a real-time constrained automaton (TA), and under this, in the time interval (t, t') representing the limit of the string w, the limit is given by the real-time constrained automaton (TA). set of things that are accepted by A

が計算される。時間なしの設定とは異なり、実時間制約付きオートマトン（ＴＡ）Ａではさまざまな実時間についての制約を表現することができ、物理情報システム（ＣＰＳ）の実行結果列のよりきめ細かい分析ができるようになる。

is calculated. Unlike the no-time setting, real-time constrained automaton (TA) A allows you to express various real-time constraints, allowing for more detailed analysis of the execution result sequence of a physical information system (CPS). Become.

(Example 1.2): String with timestamp w ₂ = (a, 0.1) (b, 2.5) (a, 3.5) (b, 4.8) and the pattern “b is a (The real-time constrained automaton (TA) corresponding to this pattern is essentially the same as the one in FIG. 9). Any match includes a second series of a and b. Note that the first series is too far apart. Such a matching is given, for example, by the character string w ₂ | _{(3, 5)} , and there are an uncountable infinite number of such matches. This matching set is symbolically expressed as {(t, t')|2.5≦t<3.5, 4.8<t'}.

Despite its obvious applications in various situations in the design and deployment of physical information systems (CPS), research on real-time constrained pattern matching has only recently begun (e.g., , 4, 6). Therefore, the practical application of pattern matching with real-time constraints in industry is extremely limited.

1.2 Remote Monitoring of Embedded Applications This embodiment proposes filtering for pattern matching with or without real-time constraints. This is preprocessing applied to the input string.

The motivation for this research comes from embedded applications. In embedded systems, which is an important aspect of physical information systems (CPS), the sensors and the processors (which perform the monitoring calculations) are typically located in separate physical locations. Furthermore, these communication channels often have limited capacity (see Figure 1).

FIG. 1 is a block diagram showing a configuration example of a physical information system (CPS) according to an embodiment.

In FIG. 1, a physical information system (CPS) includes a sensor device 1 and a monitor device 2, which are connected via a communication line 10 having a limited communication capacity, such as a CAN bus or a wireless network. Connected. Here, the sensor device 1 is configured to include a sensor 3 and a front end information processing circuit 4 having a slower processor, and the monitor device 2 includes a rear end information processing circuit 5 having a faster processor. and a display section 6.

An example of such a situation can be found, for example, in modern automobiles. There, a sensor device 1 located in the engine collects data and sends it to a monitoring device 2 with a remotely mounted processor, for example to avoid engine heat and vibrations. The sensor device 1 and the monitor device 2 are connected to each other via a communication line 10 such as a controller area network (CAN). This communication line 10 is under severe performance limitations to reduce costs. Another example can be found in Internet of Things (IoT) devices, such as home appliances and automobiles, connected to a communication line 10 such as a network. IoT devices constantly transmit their own status to a server device, and the server device installed in the cloud monitors the device. Note that the wireless communication line is limited, for example, by the capacity of the device's battery.

In this embodiment, the prefix information processing circuit 4 is an automaton (an automaton with or without real-time constraints) that describes predetermined matching conditions regarding input real-time time-stamped event sequence data. generate a Moore machine based on the generated Moore machine, filter the sequence data to substantially remove data that does not match the matching condition from the sequence data, and output sequence data as a result of the filtering. The serial digital data is transmitted to the post-information processing circuit 5 of the monitor device 2 via the communication line 10. In response, the post-information processing circuit 5 extracts sequence data matching the matching condition from the sequence data resulting from the filtering and outputs it to the display section 6.

1.3 Filtering for real-time constrained pattern matching In such remote monitoring situations, it is natural to try to reduce the amount of data sent from the sensor to the processor so as not to affect the monitoring results. . Since many sensors have built-in processors, they can be used for preprocessing. Assume here that the preprocessor (with built-in sensor, FIG. 1) is much slower than the processor that does the actual monitoring. In other words, preprocessing must be inexpensive in terms of computational complexity.

FIG. 2 conceptually represents the relationship between pattern matching processing and filtering processing performed in the physical information system (CPS) shown in FIG. 1. In FIG. 2, the filter unit (M _N,A ) 7 is a functional block included in the sensor device 1, and is a functional block realized by the pre-information processing circuit 4, for example. The pattern matching section 8 is a functional block provided in the monitor device 2, and is, for example, a functional block realized by the post-information processing circuit 5. In other words, as shown in FIG. 2, in the workflow proposed by the present inventors, the filter unit (M _N,A ) 7 is used to apply computationally inexpensive filtering to the input string. This reduces the load on the communication line 10 for transmitting data from the prefix information processing circuit 4 to the processor of the postfix information processing circuit 5, and further reduces the load on the processor.

1.4 Moore machine as a filter

This embodiment addresses two settings for monitoring:
(1) Setting without real-time constraints: The execution result string is a character string w∈Σ*, and the pattern is given by a non-deterministic finite automaton (NFA) A on Σ.
(2) Setting with real-time constraints: The execution result string is a character string with real-time constraints, and the pattern is given by a timed automaton (TA) with real-time constraints. The technical contribution of the present inventors is to provide a configuration of filters M _A,N realized as a Moore machine based on a pattern automaton A and a buffer size N (a natural number). A Moore machine is a well-known model of stateful computation, an automaton with an additional state-dependent output function. It works well sequentially and synchronously, reading one input character, moving to the next state, and outputting one character. This characteristic is particularly suitable for logic synthesis of digital circuits, and hardware acceleration using FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits) can be used.

The sequential operation of a Moore machine is in sharp contrast to the operation of pattern matching. In our settings, the pattern is given by the automaton A, so the matching length (for example, |w| _{[i, j]} ∈L(A) such that |w| _{[i, j]} |=j -i+1) is not fixed. Therefore, it is necessary to experiment with the input character string w by moving the matching window back and forth in different sizes and positions (see FIG. 3A). FIG. 3A is a timing chart showing forward and backward movement processing in pattern matching used in the embodiment.

This means that, as shown in FIG. 3A, the (sequential) filtering work is performed by the prefix information processing circuit 4 having a relatively slow preprocessor, and the postfix information processing circuit 5 having a relatively high speed main processor. This shows that there is a qualitative difference between the pattern matching task and the pattern matching task while moving. The configuration of the present inventors generates a Moore machine without real-time constraints as the filter M _A,N even in a setting with real-time constraints.

The output of the Moore machine filter M _A,N is the same as the input (real-time constrained) string except that some characters are masked with unused characters ⊥ means a character that cannot be included in the set of characters constituting the character string (input character string) input to the Moore machine filter M _A,N ). For example, under pattern A=aa*b, w=abbbbbaab is processed into ab⊥⊥⊥⊥aab. By representing the length of consecutive ⊥ in binary, the size of the data decreases exponentially. Furthermore, if you are interested only in the matching substring w| _{[i, j]} (that is, if you are not interested in the subscripts i, j), you can further collapse consecutive ⊥ into a single ⊥. Note that removing all ⊥ in the filtering stage may result in spurious matches in the pattern matching stage (see Figure 2).

The Moore machine filter M _A,N of the present inventors is composed of a pattern automaton A and a positive integer N representing the buffer size. Depending on the parameter N, the user can determine the cost of filtering (increasing N increases the number of states of the Moore machine filter M _A,N ) and the size of the filtered string (increasing N increases ⊥, which means that You can choose the balance between (the multiplied string becomes smaller). This flexibility makes the algorithm suitable for a variety of hardware configurations.

We implement this configuration and present experimental results for a real-time constrained setting (which is more difficult). Examples are chosen from the automotive sector. As a result, for a pattern (real-time constrained automaton (TA)) A that matches the actual problem and an input timestamped string w, the filtered string is 2 to 100 times larger than the original string w. See what can be shortened. Furthermore, it is experimentally confirmed that executing the Moore machine filter M _A,N is computationally light. Furthermore, by using the filter section 7 in FIG. 2, we can see that the real-time constrained pattern matching itself is accelerated by 1.2 to 2 times.

Regarding the theoretical analysis of this configuration, we prove the soundness, ie, all matches of the original input string are preserved by the filter. This soundness is proven both with and without real-time constraints. Note, however, that soundness is satisfied by trivial identity filters. Therefore, the benefit of filtering is not very obvious from the health perspective itself. In addition to experiments, we present some theoretical results on the performance of filtering in a setting without real-time constraints. This is something like this:

Completeness (meaning that all unnecessary strings are masked) and monotonicity (increasing N improves the filtering results) when the language L(A) is finite (multiple string matching settings) Since the configuration with real-time constraints has the same basic idea as the configuration without real-time constraints, these results also show the performance advantage of the configuration with real-time constraints.

The construction of our filter is automaton-theoretical and consists of two basic steps: (1) Prepare a buffer (of size N), and (2) make it deterministic. For the second step in a real-time constrained setting, a one-clock deterministic of the TA (e.g., (see Section 5.3 of Non-Patent Document 2).

1.5 Contributions The contributions of the present inventors (STFs (Special Technical Features) that are the features of the embodiments) are summarized as follows.
(1) Configuration of filters M _{A and N} for real-time unconstrained pattern matching for automaton A. The filter is given by a Moore machine and therefore operates simply, sequentially and synchronously. Furthermore, it is compatible with hardware acceleration using logic circuits. The parameter N allows the user to adjust the trade-off between computational cost and filtering effectiveness.
(2) Configuration of Moore machine filter M _A,N for pattern matching with real-time constraints. When an automaton A with real-time constraints as a pattern and a buffer size are given, a Moore machine filter M _A,N (without real-time constraints) is constructed. This configuration is more general as it is an extension of the one without real-time constraints, and utilizes a zone-based configuration of patterned real-time constrained automata. Considering practicality, the inventors believe that this real-time constrained configuration is the main contribution of this embodiment.
(3) Soundness (preservation of all matching) is proven in settings with and without real-time constraints.
(4) We further prove our theoretical results on the performance of our filter in a real-time constrained setting.
(5) Implementation of the configuration with real-time constraints and experiments demonstrating the benefits of our filter configuration.

1.6 Pattern Matching vs. Pattern Search Another mathematical formulation of monitoring (and thus another option for pattern matching) is what we call the pattern search problem. This asks whether the matching set (see section 1.2) is empty or not. Pattern search is attractive because it can be easily reduced to the problem of determining affiliation. Roughly speaking, given a pattern automaton A, we can first add a self-loop to the initial state to ignore the prefix of the input string, and then monitor whether the accept state becomes active. . Pattern searching is already well studied in the context of monitoring.

Pattern matching requires remembering subscripts (Figure 3A) and is computationally more expensive than pattern searching. However, it has strong implications for real-world monitoring applications (particularly in remote monitoring as in Example 1.3 below). Note that remote monitoring is often only quasi-online. This is because the logs may arrive at the monitor in sizable chunks intermittently. Therefore, it is essential to be able to extract which part of the received log is causing the warning.

The applicability of pattern matching to monitoring applications is well recognized in the community, and the literature has rapidly increased in recent years (for example, see Non-Patent Documents 4 and 5).

(Example 1.3) (Semi-online remote monitoring): As a specific example of remote monitoring (Figure 1), consider a semi-network connected car. It keeps driving logs in memory and sends them over the internet to a center when the vehicle stops within range of a known wireless network. Log analysis will be performed at the center. Driving logs are time-stamped strings containing information about the car's location, speed and acceleration. One such timestamped string w (taken from ROSBAGSTORE, rosbag.tier4.jp) looks like Figure 3B when the car's position is plotted.

FIG. 3B is a plan view showing an example of a position plot in pattern matching in the conventional literature, and FIG. 3C is a plan view showing identification of a section in the position plot of FIG. 3B.

Here, "the plot is discontinuous" means that data may be lost due to, for example, loss of a GPS signal. It is assumed that among these road sections, one is interested in those in which the accelerator pedal action exceeds a certain threshold for 10 seconds or more. Perform real-time constrained pattern matching on the character string w using an appropriate pattern automaton A. By mapping the identified time interval to a position plot, it is possible to identify the desired route section (see Figure 3C, hatched portions are generated by the tool MONAA).

(Configuration of Embodiment) Terms are defined in Chapter 2. In Section 3, we construct a Moore machine filter for pattern matching without real-time constraints. It also proves properties such as soundness. In Chapter 4, the same idea is used for filtering for a more complex problem, pattern matching with real-time constraints. Prove soundness here. In Section 5, the implementation and experimental results for the case with real-time constraints are presented. Related research is discussed in Chapter 6.

2. preparation

set

はΣ上の文字列の集合である。文字列ｗ＝ａ_１ａ_２…ａ_ｎ（ここで、ａ_ｉ∈Σ）の長さｎは｜ｗ｜と書かれる。

is a set of strings on Σ. The length n of the character string w=a ₁ a ₂ . . . a _n (here, a _i ∈Σ) is written as |w|.

For a non-deterministic finite automaton (NFA) A = (Σ, S, s ₀ , S _F , E) and a character string w∈Σ* on a common alphabet Σ, the run (RUN) of the automaton A on the character string w

は列

is a column

であって、任意のｉ∈［１，｜ｗ｜］について（ｓ_ｉ－１，ｗ_ｉ，ｓ_ｉ）∈Ｅが成り立つもののことである。ラン

, where (s _i-1 , w _i , s _i )∈E holds true for any i∈[1, |w|]. run

はｓ_｜ｗ｜∈Ｓ_Ｆが成り立つとき受理する（受理状態となる）という。

is said to be accepted (becomes in an accepting state) when s _|w| εS _F holds.

The power set of X is written as P(X). The disjunction of X and Y is X凵Y. For the alphabet Σ, the set Σ凵{⊥} extended with unused symbols ⊥ is written as Σ _⊥ .

The set {1, 2, ..., N} is used as the range of the counter. Since we take advantage of its algebraic structure (eg addition modulo N), it is written as Z/NZ.

The Moore machine is M=(Σ _in , Σ _out , Q, q ₀ , Δ, Λ). However, Σ _in and Σ _out are input and output alphabets, Q is a finite set of states, q ₀ ∈Q is the initial state, Δ: Q × Σ _in →Q is a transition function, Λ: Q → Σ _out is It is an output function. For Moore machine M and input string w=a ₁ a ₂ ...a _n ∈Σ* _in (where a _i ∈Σ _in ), run of Moore machine M on character string w

は列

is a column

であって、任意のｉ∈［１，｜ｗ｜］についてｑ_ｉ＝Δ（ｑ_ｉ－１，ａ_ｉ）を満足するものである。このとき、文字列ｗ上のムーアマシンＭの出力文字列ｗ'∈Σ＊_ｏｕｔは、ｗ'＝Λ（ｑ_０）Λ（ｑ_１）…Λ（ｑ_ｎ－１）∈Σ＊_ｏｕｔである。

and satisfies q _i =Δ(q _i−1 , a _i ) for any i∈[1, |w|]. At this time, the output string w'∈Σ* _out of the Moore machine M on the string w is w'=Λ(q ₀ )Λ(q ₁ )...Λ(q _n−1 )∈Σ* _out .

3. Moore machine filtering for pattern matching 1: No real-time constraints

3.1 Problem formulation (Definition 3.1) (pattern matching without real-time constraints): For a non-deterministic finite automaton (NFA) A on the alphabet Σ and a string a ₁ a ₂ ...a _n ∈Σ*, the pattern Matching problems are matching sets

を問うものである。ただし、ｗ｜_{［ｉ，ｊ］}＝ａ_ｉａ_ｉ＋１…ａ_ｊである。

The question is: However, w| _{[i, j]} = a _i a _i+1 ...a _j .

Our goal is the workflow shown in FIG. 2. Let us define the input/output type of the filter section 7 using the following general definition.

(Definition 3.2) (Moore machine for pattern matching without real-time constraints): Let the automaton A be a non-deterministic finite automaton (NFA) on the alphabet Σ, and let N be a positive integer. A filter with a buffer size N of the automaton A is a Moore machine filter M=(Σ _in , Σ _out , Q, q ₀ , Δ, Λ) that satisfies the following.

(1) Σ _in = Σ _out = Σ _⊥
(2) Let w=a ₁ ...a _n ∈Σ* be an arbitrary character string, and consider a character string w⊥ ^N with ⊥ added to the end. The output string of Moore machine M for this string w⊥ ^N must be of the form ⊥ ^N w'. However, the character string w'=b ₁ . . . b _n , and the character b _i is either a mask ⊥ or a character a _i for any i. The character a _i at position i is said to have passed when b _i =a _i holds. Otherwise (that is, if b _i =⊥), the character a _i is said to be masked.

A Moore machine filter M is said to be sound when it maintains all matching intervals. this is,

となる任意のｋ∈［１，ｎ］についてｂ_ｋ＝ａ_ｋが成立するという意味である。

This means that b _k =a _k holds for any k∈[1, n].

FIG. 4 is a conceptual diagram showing filtering padding processing in the embodiment.

Let's explain the buffer size N and addition of input/output strings with ^⊥N . Addition means that filtering is performed with a delay of N steps in the method illustrated in FIG. This delay is due to the way our Moore machine operates. This is because this Moore machine reads the input string from left to right, stores N characters in a FIFO buffer in the form encoded in the state space Q, and when extracting characters from the FIFO buffer, uses them as the output string. Output. That is why there is a delay of N steps.

FIG. 5 is a conceptual diagram showing filtering processing by the Moore machine in the embodiment.

In FIG. 5, first of all, the buffer is filled with ⊥ (step S0 in FIG. 5), which is why the prefix ⊥ ^N appears in the output string ⊥ ^N w'. The addition ^⊥N at the end of the input character string ^w⊥N is necessary to retrieve the contents of the buffer (step S(n+1) to step S(n+N)). During the processing in FIG. 5, some of the characters in the character string w=a ₁ . . . a _N are masked (b _i =⊥), but this is not explicitly shown in FIG. 5 .

3.2 Configuration of Moore machine filter M _{A, N}

(Definition 3.3) (Moore machine filter M _A,N for pattern matching (without real-time constraints)): Let Σ be an alphabet, let N be a positive integer, and A = (Σ, S, s ₀ , S _F , E) is a non-deterministic finite automaton (NFA). Moore machine filter M _A,N = (Σ _⊥ , Σ _⊥ , Q, q ₀ , Δ, Λ) is defined as follows.

Here, the state space Q is

とする。ここで、Ｚ／ＮＺはモジュロＮでの足し算を備えたＮ元集合である。

shall be. Here, Z/NZ is an N-element set with modulo N addition.

The initial state is

である。

It is.

Transition Δ: Q×Σ _⊥ →Q is defined as follows. For any a∈Σ _⊥ ,

however,

であり、

and

である。

It is.

here,

である。

It is.

Finally, the output function Λ:Q→ _Σ⊥ is defined as follows.

Describe intuition. The configuration of the Moore machine filter M _A,N is a combination of the following three blocks: a determinization processing unit (CPU 20 in FIG. 15, which will be described in detail later), a counter (included in 22b in FIG. 15), This is a buffer of size N (22a in FIG. 15).

(Deterministic) Pattern A is a non-deterministic finite automaton (NFA), but what we want is a deterministic Moore machine. This determinization is a component of the state space Q

に冪集合による構成Ｐが現れる理由を説明している。例えば、この部品の元｛（ｓ_１，ｎ_１），…，（ｓ_ｋ，ｎ_ｋ）｝は「非決定的有限オートマトン（ＮＦＡ）Ａにおいて、状態ｓ_１，…，ｓ_ｋはアクティブである」ということを意味している。式（４）を見ると、これは普通の決定化をしていることがわかる。例外は式（４）で（ｓ_０，０）を追加していることである。これは、入力文字列のどこからでもマッチングを始められるようにするためである。

This explains the reason why a configuration P based on a power set appears in . For example, the element {(s ₁ , n ₁ ), ..., (s _k , n _k )} of this part is "In a nondeterministic finite automaton (NFA) A, states s ₁ , ..., s _k are active." It means that. Looking at equation (4), it can be seen that this is a normal determinization. The exception is that (s ₀ , 0) is added in equation (4). This is so that matching can start anywhere in the input string.

(Counter) Furthermore, the active state in which the automaton A moves around has a counter (inside 22b in FIG. 15) that indicates how many steps it has moved from the initial state. This is the part Z/NZ of state space Q. The maximum value of these counters is the same as the buffer size N. When the maximum value is reached, the counter starts from 1. Looking at equation (4), it can be seen that the active state counter increases by one modulo N. Note that, for example, the maximum value of the counter may be 2×N, and the increment value may be set to 2 instead of 1, and the increment value is not limited to 1, but may be a predetermined natural number such as 2 or 3. .

(Buffer) A FIFO buffer of size N (22a in Figure 15) is the second component in state space Q.

が現れる理由を説明している。Ｎ個のセルそれぞれがΣ_⊥の文字とラベル（ｐａｓｓ又はｍａｓｋ）を保持している。式（３）と式（５）を見ると、バッファの基本的な動作は一番左の要素を取り出し、読んだ文字を右に追加することだと分かる。

This explains why it appears. Each of the N cells holds a character _Σ⊥ and a label (pass or mask). Looking at equations (3) and (5), we can see that the basic operation of the buffer is to take out the leftmost element and add the read character to the right.

It is the buffer label (pass or mask) that determines whether a certain character is masked. The prescribed label is mask (in the third case of equation (5)), and if it remains unchanged for N steps, the corresponding character in the output is masked with ⊥ (in the second case of equation (6)). The label can change from mask to pass for two different reasons (the first two cases in equation (5)).

1. The second case in equation (5) is when multiple characters up to the end of the buffer match against pattern A, leading to the acceptance state s∈S _F of pattern A. At this time, these multiple characters are marked with "pass" to clearly indicate that they must be passed to pattern matching (Figure 2). The number of characters passed ψ(S') is calculated using the counter n associated with the active state sεS _F.
2. Conditions for the first case of equation (5)

は、あるアクティブな状態ｓのカウンタが最大値Ｎに達したという意味である。この場合、Ａのこのアクティブ状態ｓが最終的に受理状態に到達するのかどうかがはっきりしない。安全側に倒すために、Ｎ個の文字全てをマスクせずにパターンマッチングに引き渡す。実時間制約なしの設定では、フィルタリングの完全性が失われるかもしれない箇所はここだけである。

means that the counter of a certain active state s has reached the maximum value N. In this case, it is not clear whether this active state s of A will eventually reach the accepting state. To be on the safe side, pass all N characters to pattern matching without masking them. In a setting without real-time constraints, this is the only place where filtering integrity may be lost.

In summary, Definition 3.3 constitutes a Moore machine that operates in the manner illustrated in FIG. The state space of a Moore machine is a combination of: a determinism of the pattern NFA A, a counter that counts the number of steps from the initial state, and N labeled with a pass or a mark. This is a FIFO (First-In First-Out) buffer that stores characters.

(Proposition 3.4): Moore machine M _A,N is a filter of A with buffer size N in the sense of Definition 3.2.

In our implementation, the filter is defined in the state space as described in Definition 3.2.

を持つようなムーアマシンそのままとしては実現していない。代わりに、状態空間Ｑを「バッファ部分」

A Moore machine like this has not been realized as it is. Instead, the state space Q is a "buffer part"

と「非バッファ部分」

and "unbuffered part"

に分割して、前半のバッファ部分を必要になり次第生成している。より正確に述べると、非バッファ部分ははじめに、決定的有限オートマトン（ＤＦＡ）として一度に構成され、このＤＦＡはサイズＮの配列として実現されたバッファ部分をどのように制御するかを支配している。実例を例３．６に示す。

The first half of the buffer is generated as needed. More precisely, the non-buffered part is initially constructed at once as a deterministic finite automaton (DFA), which governs how to control the buffered part, which is realized as an array of size N. . An illustration is shown in Example 3.6.

(Proposition 3.5): Let A = (Σ, S, s ₀ , S _F , E) be a non-deterministic finite automaton (NFA). For the induced Moore machine filter M _A,N , the size of the non-buffered part P(S×(Z/NZ)) of its state space is suppressed to O(2N·|S|).

Therefore, the memory usage of the non-buffered portion including transitions is O(2 ^{N · |S|} · |Σ|). The memory usage of the buffer portion is O(N·log|Σ|). In summary, the amount of spatial complexity when executing the inventors' Moore machine filter M _A,N is O(2 ^N·|S| ·|Σ|).

The spatial complexity is exponential in N, which comes from the power set construction for the non-buffered part P(S×(Z/NZ)). However, experimentally, memory consumption does not necessarily increase exponentially with N. This is because not all states of P(S×(Z/NZ)) are reachable (see RQ2 in Chapter 5).

FIG. 6A is a diagram illustrating an example of a pattern that is a non-deterministic finite automaton (NFA) according to the embodiment, and FIG. 6B is a diagram illustrating an example of a non-buffer portion of the Moore machine filter according to the embodiment. Further, FIG. 7A is a diagram showing a run of a Moore machine filter for a predetermined character string.

(Example 3.6): Consider pattern aa*b. This is illustrated in non-deterministic finite automaton (NFA) A ₀ in Figure 6A. The Moore machine filter M _A0,2 of Definition 3.3 is shown in FIG. 6B, where the buffer states are omitted. A run with the string w=abbbaab is shown in FIG. 7A. The output string is ⊥⊥ab⊥⊥aab, which indicates that the filtering result is ab⊥⊥aab.

FIG. 7A shows a run of M _A0,2 for the string w=abbbaab. The table in FIG. 7A represents the state of the buffer, and character data is added to the buffer from the right. "Symbols a, arrow, and b from the top" indicate that the input character is a and b is the output.

3.3 Properties of the Moore machine filter M _A,N In the rest of this section, we will define A as a pattern NFA (non-deterministic finite automaton) A = (Σ, S, S ₀ , E, S _F ), N as a positive integer, and M _{A , N} = (Σ _⊥ , Σ _⊥ , Q, q ₀ , Δ, Λ) are the Moore machine filters of Definition 3.3. Let w=a ₁ a ₂ . . . a _n be a character string on Σ, and ⊥ ^N w' be an output character string of the Moore machine filter M _A,N for the input character string w⊥ ^N. Let the character string w'=b ₁ b ₂ . . . _bn . However, b _i ∈Σ _⊥ .

(Theorem 3.7) (Soundness): Moore machine filter M _A,N is sound in the sense of Definition 3.2. There is an upper bound on the length of matching, and if the buffer size N is greater than or equal to the upper bound, then completeness is established. This is essentially the same as multiple string matching.

(Theorem 3.8) (Completeness): Assume max{|w|||wεL(A)}≦N<∞. At this time, it is possible to construct a non-deterministic finite automaton (NFA) A' where L(A)=L(A') and whose Moore machine filter M _A',N is complete. The second half means the following: If the subscript k satisfies a _k = b _k , then there is an interval [i, j] such that k∈[i, j] and w| _{[i, j]} ∈L(A). exists.

The intuition of monotonicity is that if the buffer size N' is increased, the Moore machine filter _MA,N' will mask more characters, but the state space will also increase. The exact argument is more complicated: the larger buffer size N'' must be a multiple of the smaller one.

(Theorem 3.9) (Monotonicity): For any positive real number N', let M _{A, N'} be the Moore machine filter of Definition 3.3, and ⊥ ^N' w'^(N') be the input string w⊥ Let it be the output character string of the Moore machine filter M _AN' for ^N' . Let w'^(N') = b ₁ ^(N') b ₂ ^(N') ...b _n ^(N') . However, b _i ^(N') ∈Σ _⊥ . For any positive real number n, N' and any subscript k of w, if b _k ^(N') = ⊥, then b _k ^(nN') = ⊥.

As stated in Proposition 3.5, the state space of the Moore machine filter is exponentially larger than the state space of A. This is due to the power set construction required for deterministic bifurcation. By sacrificing execution time, a non-deterministic finite automaton (NFA) can also be made deterministic on demand, which typically requires less memory space.

4. Moore Machine Filtering for Pattern Matching 2: With Real-Time Constraints We propose a Moore machine filter configuration for pattern matching with real-time constraints, which is the main contribution of the present inventors. The basic idea is the same as the setting without real-time constraints (Chapter 3), but since automata with real-time constraints (Timed Automata; TA) generally cannot be determinized, determinization becomes a technical issue. Here, the present inventors use one-clock determinization (for example, see Section 5.3 of Non-Patent Document 2). That configuration overestimates reachability, so filtering can be kept sane. Moreover, the local nature of the resulting TA (it has only one clock variable that is reset on every transition) allows us to create a filter that is a finite-state Moore machine without real-time constraints.

4.1 Problem formulation (Definition 4.1) (character string with time stamp): Let Σ be an alphabet. A time-stamped string on the alphabet Σ is a string w of the pair (a _i , τ _i )∈Σ×R _{> 0} , such that τ _i <τ for any i∈[1, |w|−1] This satisfies _i+1 .

をタイムスタンプ付き文字列とする。アルファベットΣ上のタイムスタンプ付き文字列の集合をＴ（Σ）と書く。

Let be a timestamped string. The set of time-stamped character strings on the alphabet Σ is written as T(Σ).

The substrings (a _i , τ _i ), (a _i+1 , τ _i+1 ), ..., (a _j , τ _j ) are written as w(i, j). For t∈R _≧0 , the string w is shifted by t (shifting only time t).

と定める。ただし、

It is determined that however,

である。タイムスタンプ付き文字列

It is. timestamped string

と

and

について、これらの吸収連結とは、

Regarding these absorption consolidations,

であり（ただし

(but

と

and

はどちらも普通の連結）、これらの非吸収連結とは

are both ordinary concatenations), and these non-absorbing concatenations are

である。吸収連結ｗ○ｗ'はτ_｜ｗ｜＜τ'_１のときにのみ定義されることに注意する。

It is. Note that the absorbing connection w○w' is defined only when τ _|w| <τ' ₁ .

String with timestamp on alphabet Σ

と、時刻ｔ，ｔ'∈Ｒ_＞０で、時刻ｔ＜ｔ'を満足するものについて、タイムスタンプ付き文字列区間ｗ｜_{（ｔ，ｔ'）}は、拡張アルファベットΣ凵｛＄｝上のタイムスタンプ付き文字列（ｗ（ｉ，ｊ）－ｔ）○（＄，ｔ'－ｔ）で定義される。ここで、パラメータｉ，ｊはτ_ｉ－１≦ｔ＜τ_ｉとτ_ｊ＜ｔ'≦τ_ｊ＋１となるように選ばれている。ここで、タイムスタンプ付き文字列ｗ（ｉ，ｊ）－ｔはｗ（ｉ，ｊ）の（－ｔ）シフトであり、未使用の記号＄は終端文字とよばれる。

, and for time t, t'∈R _{> 0} and time t <t', the timestamped string interval w | _{(t, t')} is the time on the extended alphabet Σ凵{$} It is defined as a stamped character string (w(i,j)-t)○($,t'-t). Here, parameters i and j are selected such that τ _i-1 ≦t<τ _i and τ _j <t'≦τ _j+1 . Here, the timestamped character string w(i,j)-t is a (-t) shift of w(i,j), and the unused symbol $ is called a terminal character.

(Definition 4.2) (Real-time constrained automaton): C represents a finite set of clock variables, and Φ(C) is an inequality

の複数の連言の集合を表わしている。

represents a set of multiple conjunctions.

Here, x∈C, c∈Z _≧0 ,

である。実時間制約付きオートマトンＡ＝（Σ，Ｓ，ｓ_０，Ｓ_Ｆ，Ｃ，Ｅ）は組であって、Σはアルファベット、Ｓは状態の有限集合、ｓ_０∈Ｓは初期状態、Ｓ_Ｆ⊂Ｓは受理状態の集合、Ｅ⊂Ｓ×Ｓ×Σ×Ｐ（Ｃ）×Φ（Ｃ）は遷移の集合である。遷移の複数の構成要素（ｓ，ｓ'，ａ，λ，δ）∈Ｅは、ソース、ターゲット、アクション、リセット変数、遷移のガードをそれぞれ表わしている。

It is. A real-time constrained automaton A = (Σ, S, s ₀ , S _F , C, E) is a set, where Σ is an alphabet, S is a finite set of states, s ₀ ∈S is an initial state, and S _F ⊂ S is a set of acceptance states, and E⊂S×S×Σ×P(C)×Φ(C) is a set of transitions. The plurality of components (s, s', a, λ, δ) ∈ E of the transition represent the source, target, action, reset variable, and guard of the transition, respectively.

A clock value ν is defined as a function ν:C→R _≧0 . The t shift ν+t of the clock value ν is defined as (ν+t)(x)=ν(x)+t. Here, t∈R _≧0 . Real-time constrained automaton A = (Σ, S, s ₀ , S _F , C, E) and a string with a timestamp

について、ｗ上のＡのランとは組（ｓ_ｉ，ｖ_ｉ）∈Ｓ×（Ｒ_≧０）^Ｃの列ｒであって、次の条件を満足するものである。

, a run of A on w is a sequence r of the set (s _i , v _i )∈S×(R _≧0 ) ^C that satisfies the following condition.

(Initial condition) s ₀ is an initial state, and ν ₀ (x)=0 for any x∈C.

(Continuity condition) Transition such that ν _i−1 +τ _i −τ _i−1 |=δ and ν _i (x)=0 (x∈λ is arbitrary) for any i∈[1, |w|] (s _i-1 , s _i , a _i , λ, δ)∈E exists and ν _i (x)=ν _i-1 (x)+τ _i −τ _i-1 (not x∈λ).

A run that satisfies only the continuity condition is called a pass. run

はｓの最後の要素ｓ_{｜ｓ｜－１}がＳ_Ｆに属するとき受理するという。言語Ｌ（Ａ）はタイムスタンプ付き文字列の集合｛ｗ｜ｗ上のＡの受理するランが存在する｝と定義される。

is said to be accepted when the last element s _|s|-1 of s belongs to _SF . The language L(A) is defined as a set of time-stamped character strings {w|There exists a run accepted by A on w}.

We now state our goal problem. Algorithms for solving this problem have been actively researched (for example, see Non-Patent Documents 4 and 5), and the contribution of this embodiment is the filtering Moore machine as a preprocessor for these algorithms.

(Definition 4.3) (Pattern matching with real-time constraints): Let A be an automaton with real-time constraints, w be a character string with a timestamp, and both are on a common alphabet Σ. The real-time constrained pattern matching problem is to find all intervals ( _{t, t') such that the interval w| (t, t')} is accepted by the real-time constrained automaton (TA) A. In other words, the matching set

を求めるものである。

This is what we seek.

4.2 1-clock determinism of TA Of the three main blocks that were used in the filter configuration without real-time constraints (Definition 3.3), the counter and buffer remain unchanged in this configuration with real-time constraints. You can bring it. For determinization, we use the idea of overestimation in Definition 4.5. This is based on (for example, see Section 5.3 of Non-Patent Document 2).

Let's start with the auxiliary symbols.

(Definition 4.4) (Restriction ν| _C , Connection ν凵ν'): ν:C'→R _≧0 is the clock value. The restriction of ν to C⊂C' is written as ν| _C :C→R _≧0 . This is (v| _C )(x)=ν(x) for any x∈C.

Let ν:C→R _≧0 and ν′:C′→R _≧0 be clock values. These connections ν凵ν′:C凵C′→R _≧0 are defined as clock values on the non-commutative C凵C′ as follows.

A function that maps x _i to r _i (for any i∈{1,...,n}) is

と書かれる。

is written.

(Definition 4.5) (1-clock determinism): Let A = (Σ, S, s ₀ , S _F , C, E) be a timed automaton (TA), and y be an unused clock. be a variable (in other words, yεC is not true). A real-time constrained automaton (TA) A' = (Σ, S', s ₀ ', S _F ', {y}, E') is called 1-clock determinism of automaton A when the following conditions hold. .

(1) Any element of a new, finite state space S'

は対（ｓ_ｉ，Ｚ_ｉ）の有限集合

is a finite set of pairs (s _i , Z _i )

である。ここで、ｓ_ｉ∈ＳはＡの状態であり、Ｚ_ｉは

It is. Here, s _i ∈S is the state of A, and Z _i is

の部分集合でゾーンとよばれる特殊な多角形により与えられるものである。

is a subset of , which is given by a special polygon called a zone.

(2) Any transition of automaton A'

について、ガードδはクロック変数ｙについての複数の区間の有限和集合である。さらに、それは遷移ＥがオートマトンＡで有効かどうかを反映している。正確には、任意のｕ，ｕ'∈Ｒ_≧０でδを満たすものについて、

, guard δ is a finite union of intervals for clock variable y. Furthermore, it reflects whether transition E is valid in automaton A. More precisely, for any u, u'∈R _≧0 that satisfies δ,

が成立している。ただし、集合

has been established. However, gathering

は

teeth

で定義される。

Defined by

(3) Any transition of automaton A' resets only one clock variable y. That is, all transitions

について、λ＝｛ｙ｝である。

For λ={y}.

(4) Any transition of automaton A'

はＡの遷移を模倣する。より正確には、

imitates the transition of A. More precisely,

と

and

とする。ｓ'∈Ｓとν'：Ｃ→Ｒ_≧０（ここで、τは経過時間）が存在して、

shall be. There exists s'∈S and ν': C→R _≧0 (where τ is the elapsed time),

がオートマトンＡの（長さ１の）パスであると仮定する。このとき、ゾーン

Suppose that is a (length 1) path of automaton A. At this time, the zone

であって、
１）

And,
1)

２）付値

2) Bid price

（これはクロック集合Ｃ凵｛ｙ｝上のものである）はゾーンＺ'に属する。

(which is on the clock set C{y}) belongs to zone Z'.

(5) Automaton A' is deterministic: any state

、任意のクロック付値

, any clock value

、ａ∈Σ、経過時間を表わすτ∈Ｒ_≧０について、

, a∈Σ, for τ∈R _≧0 representing the elapsed time,

からの長さ１のａ，τでラベル付けされたパスは一意である。つまり、もし

A path labeled with length a, τ of length 1 from is unique. That is, if

と

and

が両方ともオートマトンＡ'のパスならば、

If both are paths of automaton A', then

かつν'＝ν"となる。（条件３のために

and ν'=ν". (Due to condition 3,

となっていることに注意する。）

Please note that. )

(6) The initial state _s0 ' of the automaton A' is

で与えられる。ここで０は全てのクロック変数を０に写す付値である。

is given by Here, 0 is an assignment that maps all clock variables to 0.

(7) State S belongs to S' _F if s∈S _F

が存在するとき、かつそのときに限る。

exists, and only then.

(Proposition 4.6): Let A=(Σ, S, s ₀ , S _F , C, E) be a real-time constrained automaton (TA). Let automaton A'=(Σ, S', s ₀ ', S _F ', {y}, E') be a one-clock determinization of automaton A. At this time, automaton A' satisfies the following properties.

(Simulation) Let w∈T(Σ) be a character string with a timestamp, and assume that there is a run on the character string w such that automaton A reaches state s∈S. In this case, the following is satisfied

が存在する：（１）あるゾーンＺについて

exists: (1) For a certain zone Z

となる、（２）オートマトンＡ'で状態Ｓへの文字列ｗ上のランが存在する。

(2) There is a run on the string w to the state S in the automaton A'.

(Language inclusion) In particular, L(A)⊂L(A').

Note that Definition 4.5 gives properties, not configurations. For the same real-time constrained automaton (TA) A, there are multiple 1-clock determinizations with different sizes and precisions. In the implementation by the present inventors, for example, a specific configuration proposed in Section 5.3.4 of Non-Patent Document 2 is used.

4.3 Configuration of our Moore machine filter M _A,N (Definition 4.7) (Moore machine filter M _A,N for pattern matching with real-time constraints): A=(Σ,S,s ₀ , S _F , C, E) is a real-time constrained automaton (TA), and N∈Z _>0 . The configuration of the Moore machine filter _MA,N is performed according to the following steps.

The first step is to extend the original real-time constrained automaton (TA) A with a counter. in particular,

を次のように定義する。

is defined as follows.

、そして

,and

In the second step, we take a one-clock determinization (Definition 4.5) of the automaton A ^N-ctr .

がその結果であるとする。

Suppose that is the result.

Finally, in the third step, the Moore machine filter M _A,N is defined as shown in the following equation.

However, Δ and Λ are defined as follows.

、ただし、状態Ｓ'はオートマトンＡ^{Ｎ－ｃｔｒ－ｄ}での状態Ｓの、文字ａと経過時間τのもとでの一意な後続であり（定義４．５）、

, where state S' is a unique successor of state S in automaton A ^N-ctr-d under letter a and elapsed time τ (Definition 4.5),

は次式のように定義される。

is defined as the following equation.

here,

である。

It is.

と定義する。

It is defined as

FIG. 7B is a block diagram showing an example of a processing circuit of the prefix information processing circuit according to the embodiment. In FIG. 7B, the processing circuit includes a filter section 11 and a masking application section 12.

Note that the resulting Moore machine takes a timestamped string as input. This makes the input alphabet infinite (that is, Σ _⊥ ×R _≧0 ). This is not a big problem in implementation. This is because the state space remains finite. Furthermore, the output alphabet of the Moore machine filter M _A,N (filter unit 11 in FIG. 7B) is a binary set {pass, mask}, and the automaton of the Moore machine filter outputs only mask information. Although it is true that a finite state Moore machine cannot buffer multiple characters with real-time constraints, it is possible to copy the original timestamped character string and apply appropriate masking later using the masking application unit 12. It can be applied (see FIG. 7B).

(Theorem 4.8) (Soundness): Let the automaton A be the pattern TA A = (Σ, S, s ₀ , S _F , C, E), let N be a positive integer, and define M _{A, N} as 4.7 Let it be a Moore machine filter. w = (a ₁ , τ ₁ ) (a ₂ , τ ₂ )... Let (a _n , τ _n ) be a character string with a timestamp on Σ, and mask ^N w' be the input character string w (⊥, τ _n ) Let it be the output character string of the Moore machine filter M _A,N ^for N (here, it is assumed that the input and output character strings are mask ^N and (⊥, τ _n ) ^N added as shown in FIG. 4). Let the character string w'=b ₁ b ₂ . . . _bn . Here, b _k ∈{pass, mask}.

For any subscript pair (i, j) of a string w that satisfies w(i, j)−τ _i−1 ∈L(A) and for a subscript k∈[i, j] of a string w , b _k =pass.

5. Example 1 (implementation and experiment)
The present inventors implemented a Moore machine filter configuration for pattern matching with real-time constraints (Example 1). Our implementation collapses consecutive ⊥s into two ⊥s and keeps the timestamps of the first and last ⊥s. The buffer portion of the state space Q is generated as soon as it is needed ({pass, mask} ^N in Definition 4.7), as stated in Proposition 3.5. The present inventors conducted an experiment to answer the following research question (RQ).

RQ1: Does our Moore machine filter mask many events?
RQ2: Does our Moore machine filter work online?
That is, does it operate in linear time and constant space for the length of the input timestamped string?
RQ3: Does our Moore machine accelerate the overall task of real-time constrained pattern matching?
RQ4: Is the filter of the present inventors highly accurate?
That is, do many of the unmasked events contribute to the actual matching?
RQ5: Is the response of the inventors' filter fast?
In other words, won't there be a big delay?

The filter configuration was implemented using C++ language and compiled using clang-900.0.39.2. The tool's input consists of a pattern TA A, a buffer size N, and a timestamped string w, and outputs a filtered string. The experiment was conducted using Mac OS 10.13.4 on the RAM of a personal computer (MacBook Pro Early 2013 with 2.6 GHz Intel Core i5 processor and 8GB 1600MHz DDR). The benchmark problems used are shown in Figures 8 to 10. These are all taken from the automotive scenario.

FIG. 8 is a diagram showing an example of a Moore machine filter for data of an automobile torque sensor according to the first embodiment.

In FIG. 8, a set W of input character strings (length is 242,808 to 4,873,207) is generated by random input to create an automobile engine model sldemo_enginenewc. Generated from slx. This pattern describes that high occurs four or more times within one second. For a buffer size N=10, the size of the Moore machine filter M _A,10 (multiplied by the number of reachable states in the non-buffered part of SN-ctr-d) was 16.

FIG. 9 is a diagram showing an example of a Moore machine filter for data of an automobile gear sensor according to the first embodiment.

In FIG. 9, a set W of input strings (lengths from 306 to 1,011,426) was generated from a model of an automatic transmission. This pattern, taken from φAT5 of the model, represents the event of too frequent gear shifts (from 1st to 2nd gear). When the buffer size N=10, the size of the Moore machine filter _MA,10 was measured using the same method as in FIG. 8, and was found to be 3.

FIG. 10 is a diagram showing an example of a Moore machine filter for data from an automobile accelerator sensor according to the first embodiment.

In FIG. 10, a set W of input character strings (lengths from 708 to 1,739,535) was generated using the same model as the gear. The pattern is the same as φAT8: gears shift from 1st to 4th, RPM is higher, but speed is lower (in other words, the event v≧100 does not occur). When the size of the Moore machine filter M _A,10 was measured using the same method as in FIG. 8 for the buffer size N=10, it was 71.

To measure execution time and memory usage, we used GNU time and took the average of 20 executions. In each experiment, we measured the entire workflow. RQ2 measures time and memory usage including filter configuration, and RQ3 measures time and memory usage for filter configuration, filtering, interprocess communication, and pattern matching. In the RQ3 experiment, we used MONAA, a state-of-the-art tool for real-time constrained pattern matching.

RQ1: Filtering rate

FIG. 11A is a simulation result of a Moore machine filter for data from a torque sensor of an automobile according to Example 1, and is a graph showing the length of a filtered string with real time versus the input string length with real time. FIG. 11B is a graph showing simulation results of a Moore machine filter for data of a gear sensor of a car according to Example 1, and shows the length of a filtered string with real time versus the input string length with real time. FIG. 11C is a graph showing simulation results of a Moore machine filter on data from an automobile accelerator sensor according to Example 1, and shows the length of a filtered string with real time versus the input string length with real time. That is, FIGS. 11A to 11C show filtered timestamped string lengths for each real-time constrained automaton A, buffer size N, and timestamped string w∈W.

As is clear from FIGS. 11A to 11C, it can be seen that the larger the buffer size N becomes, the shorter the filtered character string becomes. This agrees with the theoretical consideration in Theorem 3.9 (although the result was set without real-time constraints). Peak performance appears to be achieved with a relatively small buffer size N, such as N=10. When the buffer size N=10, the lengths of the original time-stamped character strings for torque, gear, and accelerator are approximately 1/3, 1/2, and 1/100, respectively. For accelerator, our filter filters many characters. This is because the size of the alphabet and the size of the pattern real-time constrained automaton are relatively large. This dramatic data reduction shows that our filtering approach is practical in embedded scenarios (see Figure 1).

RQ2: Speed and memory usage

FIG. 12A is a graph showing simulation results of a Moore machine filter on data from an automobile torque sensor according to the first embodiment, and showing execution time versus input character string length with real time. FIG. 12B is a graph showing simulation results of a Moore machine filter for data of a gear sensor of a car according to Example 1, and showing execution time with respect to input character string length with real time. FIG. 12C is a graph showing simulation results of a Moore machine filter on data from an automobile accelerator sensor according to Example 1, and showing execution time versus input character string length with real time.

FIG. 13A is a graph showing a simulation result of a Moore machine filter on data from a torque sensor of an automobile according to the first embodiment, and shows the amount of memory used with respect to the input character string length with real time. FIG. 13B is a graph showing the simulation results of the Moore machine filter for the data of the automobile gear sensor according to the first embodiment, and shows the amount of memory used with respect to the length of the input character string with real time. FIG. 13C is a graph showing the simulation results of the Moore machine filter for the data of the automobile accelerator sensor according to the first embodiment, and shows the amount of memory used with respect to the input character string length with real time.

That is, FIGS. 12 and 13 show the execution time and memory usage of the inventors' Moore machine filter for each pattern real-time constrained automaton A, buffer size N, and timestamped string w∈W. ing.

In FIG. 12, it can be seen that the execution time is linear with respect to the input string. In FIG. 13, it can be seen that the memory usage is approximately constant with respect to the length of the input string. These two results suggest that our filtering technique can be used online.

The time required to construct a Moore machine filter is considered to be negligible. See now the execution time for a short input string in FIG.

Regarding the influence of varying the buffer size N, it can be seen that the execution time is relatively large for a small buffer size N. This is believed to be because fewer characters are masked and more characters are output, which worsens the cost of the input/output device (I/O). Regarding memory usage, the increase was modest for large buffer sizes N, contrary to the worst-case result in Proposition 3.5 (exponential with N). This is because not all states of the power set configuration can be reached.

RQ3: Acceleration of pattern matching with real-time constraints

FIG. 14A is a simulation result of a tool according to a comparative example for data from a torque sensor of a car, and is a graph showing execution time versus input character string length with real time. FIG. 14B is a graph showing the simulation results of the tool according to the comparative example for the data of the gear sensor of the automobile, and shows the execution time with respect to the input character string length with real time. FIG. 14C is a graph showing the simulation result of the tool according to the comparative example for the data of the accelerator sensor of the automobile, and shows the execution time with respect to the input character string length with real time.

That is, FIG. 14 shows the execution time of the workflow of FIG. 2. Here, the filter is given by the inventors' algorithm, and pattern matching is performed with the latest tool MONAA. More specifically, the standard output of the Moore machine filter is connected to the standard input of MONAA via a Unix pipeline. By doing so, the filter and MONAA are executed in parallel on different cores.

We have found that filtering improves the overall performance of real-time constrained pattern matching if the buffer size N is large enough (eg, N=10). Torque and gearing are now 1.2 times faster, and accelerator speeds are roughly twice as fast. This acceleration suggests that our filtering approach may be beneficial independent of the configuration assumptions shown in FIG. When logs are huge and monitoring takes hours or even days, running it in parallel with filters may save time.

RQ4: Accuracy

For the three examples torque, gear, and acceleration, and buffer size N=10, the proportions of unmasked events that contributed to the actual matching were 0.34%, 99%, and 92%, respectively. Therefore, it can be seen that accuracy varies dramatically depending on the pattern. Note that even for the less accurate example (torque), our filter does indeed reduce the log size by roughly a factor of 3 (FIGS. 11A-11C).

Most of the inaccuracy in this real-time constrained setting is due to the looseness of the one-clock determinism (Definition 4.5). For example, a torque real-time constrained automaton (TA) (FIG. 8) requires four consecutive high occurrences within 1 second using the same clock x. The best overestimation with this one-clock determinism (all clocks must be reset on every transition) is the requirement that high appear in each of four consecutive intervals of length 1 or less. This is much looser than the original requirement and explains the relatively low accuracy in the torque example.

RQ5: Reactivity

We calculated the average delay (execution time)/|w|×N by our filter for three examples: torque, gear, acceleration and buffer size N=10. The results were 2.2 microseconds, 3.1 microseconds, and 0.91 microseconds, respectively. Although these delays are highly dependent on the computing power of the processor, we conclude that filters with small delays operate sufficiently fast.

6. Related Research The efficiency of pattern matching has been actively researched in the fields of databases and networks. In these areas, the hardware configuration problem (speed difference between L1/L2 cache and main memory) is similar to the embedded monitor problem that we have previously discussed.

Research in these application areas has treated string(s) of characters as patterns. The main sources of inspiration here have been classical algorithms such as Boyer-Moore, Commentz-Walter, and Aho-Corasick. Many algorithms for patterns given by regular expressions or automata instead of strings rely on these string matching techniques.

In databases and networks, pattern matching for regular expressions has mainly been performed using application-specific heuristics that take machine configuration into account.

Prefiltering before actual pattern matching has been considered in the above studies (see, for example, Non-Patent Document 3). The main difference between these studies and ours is that their filter explicitly includes indexes of matching candidates, ie, potential matches. To this end, the second step of the workflow (pattern matching as we call it) is called inspection in their embodiment. In contrast, our filter only masks the input string. This is because the inventors' objective (with an eye toward embedded applications) is not only to speed up matching, but also to reduce the amount of data sent from the sensor to the pattern matching device. This selection made it possible to use a Moore machine, and furthermore, it became easy to implement with an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

Monitoring of real-time temporal logic and pattern matching with real-time constraints (see, for example, Non-Patent Document 4) is a relatively new topic. Although this type of research has mainly been studied in the context of physical information systems, there is also ample promise for applications in databases and networks. In real-time constrained pattern matching, specifications can be written using real-time constrained automata (used in this study), real-time constrained regular expressions, or temporal logic formulas with distance. Algorithms for real-time constrained pattern matching of specifications in these formulations have been actively researched, for example, in Non-Patent Document 1. In addition, real-time constrained pattern matching is accelerated by combining shift table techniques such as Boyer-Moore and Franek-Jennings-Smith with real-time constrained automata (for example, see Non-Patent Document 5). .

7. Conclusion In response to the increasing demand for monitoring in embedded applications in recent years, the present inventors proposed a filtering Moore machine configuration for pattern matching (with and without real-time constraints). Its configuration is based on automaton theory, and the filter is implemented as a Moore machine.

FIG. 15 is a block diagram showing a configuration example of the prefix information processing circuit 4 according to the second embodiment. In FIG. 15, the pre-information processing circuit 4 is a processor circuit having the function of a Moore machine filter, and includes a CPU 20, a ROM 21, a RAM 22, an operation section 23, a display section 24, an input interface 25, and an output interface. 26 are connected to each other via a bus 27.

In FIG. 15, a CPU 20 is a processor that controls and executes Moore machine filter processing. The ROM 21 stores programs and data necessary for operating the pre-information processing circuit 4. The RAM 22 is a memory area used when executing Moore machine filter processing (filtering processing), and is provided with a buffer section 22a, which is, for example, a FIFO memory, and a non-buffer section 22b. Note that the buffer section 22a is sometimes called the "buffer 22a", and the non-buffer section 22b is sometimes called the "non-buffer 22b". Further, various programs (generation program 22p1, main program 22p2, subprogram 22p3) executed by the CPU 20 are loaded into the RAM 22 from the ROM 21. Details of these programs will be described later. The input interface 25 receives input sequence data, converts it into a predetermined data format, and then outputs it to the CPU 20 or the like. The output interface 26 converts the sequence data resulting from the processing of the Moore machine filter by the CPU 20 into a predetermined data format, and then outputs the data to an external circuit or line. The operation unit 23 includes, for example, a keyboard and a mouse, and is used for executing, stopping, and inputting necessary data.

The operation unit 23 is also used to input conditions for a pattern to be searched (referred to as matching conditions) from the input sequence data to the prefix information processing circuit 4. The matching condition is preferably input in the form of a character string or regular expression. Alternatively, it may be provided to the prefix information processing circuit 4 as an automaton. In yet another embodiment, the matching conditions may be input together with the sequence data via the input interface 25 (eg, from an external device). The display unit 24 is, for example, a liquid crystal display, and displays input sequence data, output sequence data, etc.

FIG. 16 shows an example of the configuration of the buffer section 22a. The buffer section 22a is one of the components of a finite state machine (specifically, a Moore machine) that operates in the pre-information processing circuit 4. Although the details will be described later, the Moore machine that operates in the pre-information processing circuit 4 defines the state space by dividing it into a buffered part and a non-buffered part, like the Moore machine explained in Section 3.2 of this specification. . The buffer section 22a corresponds to a buffer portion of the state space.

The buffer section 22a is a FIFO buffer having N memory blocks (22a-1, 22a-2, . . . 22a-N). Each memory block (22a-1, 22a-2, . . . 22a-N) has a data area for storing one unit of input sequence data and a flag area. In FIG. 16, row 221a represents a data area, and row 221b represents a flag area. Each data area is a storage area with the same size (or larger size) as data for one unit of sequence data. For example, if the sequence data is a character string, each character making up the character string is a 1-byte character, and the sequence data is input character by character (1 byte byte) to the prefix information processing circuit 4, the size of the data area is 1 byte is sufficient.

Each flag area is, for example, a 1-bit storage area in which 0 (mask) or 1 (pass) is stored. Hereinafter, the data (0 or 1) stored in the flag area will be referred to as a "flag." Further, the value 0 stored in the flag area is written as "mask", and the value 1 stored in the flag area is written as "pass".

In the prefix information processing circuit 4 according to the second embodiment, when inputting sequence data to the buffer section 22a, the data is stored in the rightmost memory block (22a-1). Before data is stored in the memory block (22a-1), the data (and flag) of the leftmost memory block (22a-N) is output from the buffer section 22a, and the remaining memory blocks (22a-1, 22a-2, . . . 22a-(N-1)) are respectively moved to the adjacent memory block on the left (22a-2, 22a-3, . In the following description, the rightmost memory block (22a-1) will be referred to as the "head of the buffer section 22a", and the leftmost memory block (22a-N) will be referred to as the "end of the buffer section 22a".

Note that although an example has been described here in which each memory block (22a-1, 22a-2, . . . 22a-N) has a data area and a flag area, the data area may not be provided. For example, in a Moore machine that follows the definition explained in Section 4.3 of this specification, no data (input sequence data) is stored in the buffer part of the state space, as described in Section 4.3. Only flags are stored. Therefore, for example, if the Moore machine operating in the prefix information processing circuit 4 is a Moore machine that follows the definition described in Section 4.3 of this specification, no data area is required in the buffer section 22a.

Next, an example of a Moore machine that operates with the prefix information processing circuit 4 according to the second embodiment will be described. Here, we will mainly describe a case where the prefix information processing circuit 4 receives a character string without a time stamp as input sequence data and generates a Moore machine that filters the received character string. In this case, the Moore machine operating in the prefix information processing circuit 4 is similar to that described in Section 3.2 of this specification.

The Moore machine operated by the pre-information processing circuit 4 is generated based on matching conditions of input sequence data. Therefore, before explaining the Moore machine, an example of matching conditions will be explained. In the following explanation, an example will be described in which the matching condition is expressed as "a(a*)b" (when expressed using a regular expression).

The regular expression "a(a*)b" is equivalent to the automaton A=(Σ, S, s ₀ , S _F , E) that operates according to the state transition diagram shown in FIG. Note that the meanings of each symbol in the automaton A=(Σ, S, s ₀ , S _F , E) are as follows. Σ represents the input character set, S represents the set of states, s ₀ represents the initial state (also an element of S), and S _F represents the final state (also called the acceptance state) (a subset of S). ), E is a set of transitions.

In the example described here, automaton A has three states {s ₀ , s ₁ , s ₂ }, where s ₀ is the initial state and s ₂ is the final state (acceptance state). Further, Σ is composed of letters a and b. In FIG. 17, each state {s ₀ , s ₁ , s ₂ } is represented by a circle, and a double circle represents an acceptance state. Furthermore, the letters (a, b) attached above the arrows (edges) connecting each state mean inputs to the automaton A. For example, in _FIG . 17, the letter "a" is written above the arrow connecting state s ₀ and state s ₁ . Automaton A transitions to state _s1 .

The pre-information processing circuit 4 generates a Moore machine according to the definition described in Section 3.2 of this specification. The Moore machine generated here is expressed as M _A,N = (Σ _⊥ , Σ _⊥ , Q, q ₀ , Δ, Λ). Note that the meanings of each symbol in M _A,N = (Σ _⊥ , Σ _⊥ , Q, q ₀ , Δ, Λ) are as follows. The first Σ _⊥ represents the input character set, and the second Σ _⊥ represents the output character set. As mentioned earlier, Σ is the input character set of automaton A, and Σ _⊥ is the character set in which the character ⊥ is added to the input character set of automaton A (however, the character ⊥ is the input character set of automaton A ⊥ is a character that is not included in the set Σ (referred to herein as a "block character"). Q represents the state space of the Moore machine, q ₀ represents the initial state, Δ represents the transition function, and Λ represents the output function. Furthermore, the subscript A of M _A,N means the automaton that is the source of the Moore machine (that is, the automaton A accepted by the pre-information processing circuit 4), and N is the buffer size (the buffer explained using FIG. 16). 22a).

When generating a Moore machine, the pre-information processing circuit 4 first defines an extended state based on each state that the automaton A can take. In Example 2, we create a new set of states that automaton A can take (temporarily denoted as s _k ) and the number of transitions required for automaton A to transition from the initial state (s ₀ ) to state s _k . Define it as an (extended) state. If the number of transitions required to transition from the initial state (s ₀ ) to state s _k is c, this new state is expressed as (s _k , c). In the second embodiment, this new state is sometimes called a "state with a counter", and the number of transitions required to transit from the initial state (s ₀ ) to the state s _k is called a "counter". Sometimes. However, in Example 2, the counter is an integer greater than or equal to 0, but the upper limit is an integer with the buffer size N, and the counter is precisely the value obtained by calculating the following equation (7) (i.e. The counter belongs to the coset class with respect to modulo N).

((Number of transitions - 1) mod N) + 1 ... (7)
Therefore, to be exact, the number of transitions and the value of the counter may not match, but in the second embodiment, c in (s _k , c) may be called the counter of state s _k , or may be called the number of transitions. There is also.

Counters and states with counters will be explained using a state transition diagram (FIG. 18) of an automaton described using states with counters. In the following description, unless otherwise specified, a case where the buffer size (N) is 2 will be described.

In the automaton A of FIG. 17, the number of transitions required to transition from the initial state _s0 to the state _s1 is one, so the counter for the state _s1 is 1 based on the above equation (7). Therefore, the prefix information processing circuit 4 defines (s ₁ , 1) as a state with a counter.

In addition, as can be seen from FIG. 17, in automaton A, if the character "a" is input as sequence data when the state is s ₁ , the state transitions to s ₁ again (this is, for example, when the state is s ₀ ). This is the case when the letter "a" is entered twice in a row). In this case, the result of two transitions means a transition to state _s1 , so the number of transitions is 2 and the value of the counter is also 2. Therefore, the prefix information processing circuit 4 defines (s ₁ , 2) as a state with a counter.

Furthermore, in automaton A, if the character "a" is input three times in a row when the state is _s0 , the state transitions to _s1 again. In this case, the number of transitions is three, but since the buffer size is 2, the value of the counter is 1 [((3-1) mod 2)+1=1] based on the above equation (7). Therefore, there are two new states (states with a counter) that are generated by adding a counter to the state s ₁ that the automaton A can take: (s ₁ , 1) and (s ₁ , 2).

Similarly, there are two new states, (s ₂ , 1) and (s ₂ , 2), which are generated by adding a counter to the state s ₂ that the automaton A can take. Therefore, when the buffer size N is 2, the prefix information processing circuit 4 has five states with counters (s ₀ , 0), (s ₁ , 1), (s _1,2 ), ( _s2,1 ), and ( _s2,2 ). After defining the state with a counter, the prefix information processing circuit 4 defines an automaton using the state with a counter, as shown in FIG. 18 (the automaton using the state with a counter defined here is expressed as A') do).

The automaton A' shown in FIG. 18 differs from the automaton A shown in FIG. 17 in that each state is a state with a counter, but in principle, the state transition rules of the automaton A' shown in FIG. This is the same as automaton A shown in FIG. That is, the prefix information processing circuit 4 defines the automaton A' based on the automaton A shown in FIG. For example, in the automaton A shown in FIG. 17, if the character "b" is input while in the state s ₁ ((s ₁ , 1) or (s ₁ , 2)), the state changes to s ₂ ((s ₂ , 2) or (s ₂ , 1)). Therefore, when the prefix information processing circuit 4 defines the automaton A', if the character "b" is input in the state (s ₁ , 1) or (s ₁ , 2), the state becomes (s ₂ , 2). Or, define the automaton A' to transition to (s ₂ , 1).

Next, the prefix information processing circuit 4 defines (generates) a Moore machine based on the automaton A' shown in FIG. First, we will explain the definition of possible states (state space) of a Moore machine and how to define a transition function. In the Moore machine generation process performed by the prefix information processing circuit 4, a process similar to a known subset configuration method (also referred to as a power set configuration method) is performed. Since the subset configuration method is a well-known method as disclosed in, for example, Japanese Patent Application Laid-open No. 2009-58989, a detailed explanation will be omitted. Here, only the processing related to the generation of the Moore machine executed by the prefix information processing circuit 4 will be described.

The subset construction method is a process used to convert a non-deterministic finite automaton (NFA) into a deterministic finite automaton (DFA) (referred to as determinization). Therefore, the Moore machine generated by the prefix information processing circuit 4 is a DFA. As is well known, determinization involves identifying all the states to which a non-deterministic finite automaton (NFA) transitions when an input character x is given to a certain state (or a set of states), The set of specified states is made into a state of a deterministic finite automaton. The prefix information processing circuit 4 also performs a process similar to this determinization.

However, in the determinization performed by the prefix information processing circuit 4, the prefix information processing circuit 4 generates the initial state (s ₀ , 0) added to the previously mentioned "set of specified states". It is defined as the state of Moore machine M _A,N . Furthermore, the input character set _Σ⊥ is used instead of the input character set Σ of the automaton A'. Hereinafter, the generation process of Moore machines _{MA, N} by the prefix information processing circuit 4 will be explained with reference to FIGS. 18 and 19.

If the input character a is given while the automaton A' in FIG. 18 is in the initial state (s ₀ , 0), it transitions to the state with a counter (s ₁ , 1) and does not transition to any other state. Therefore, the prefix information processing circuit 4 converts the set of transition destination states (when input character a is given) from the initial state (s ₀ , 0) to {(s ₁ , 1), (s ₀ , 0) } (In other words, the specified transition destination state (s ₁ , 1) plus (s ₀ , 0) becomes the set of transition destination states). Below, this set of states will be expressed as q ₁ '. Further, the initial state (s ₀ , 0) is expressed as q ₀ ′ (that is, q ₀ ′ is the initial state of the Moore machine M _A,N ). In addition, the prefix information processing circuit 4 similarly generates a set of states to which the automaton A′ in the initial state (s ₀ , 0) transitions when input character b is given, and the initial state (s ₀ , 0). Specify the set of states to which the automaton A' in is transitioned when the input character ⊥ is given. Referring to FIG. 18, there are no transition destination states corresponding to these cases. If the transition destination state does not exist, this is equivalent to the above-mentioned "set of specified states" being an empty set. In this case, the prefix information processing circuit 4 determines the state set {(s ₀ , 0)} (that is, q ₀ ′) formed by adding the initial state (s ₀ , 0) to the empty set as the transition destination. do. Therefore, the prefix information processing circuit 4 converts the set of transition destination states (when input character b is given and when input character ⊥ is given) from the initial state (s ₀ , 0) to {(s ₀ , 0)} (=q ₀ ').

Subsequently, the prefix information processing circuit 4 identifies a set of transition destination states from the state set q ₁ ′ (={(s ₁ , 1), (s ₀ , 0)}). As can be seen from the state transition diagram in FIG. 18, when the input character a is given to the automaton A' in the state (s ₁ , 1), the transition destination state is (s ₁ , 2), and the state (s ₀ , 0 ) is given the input character a to the automaton A', the transition destination state is (s ₁ , 1). Therefore, the prefix information processing circuit 4 generates a set {(s ₁ , 1), (s ₁ , 2) formed by adding the state (s ₀ , 0) to the states (s ₁ , 1) and (s ₁ , 2). , (s ₀ , 0)} is determined to be a set of transition destination states when input character a is given to state set q ₁ ′. Below, this set of states {(s ₁ , 1), (s ₁ , 2), (s ₀ , 0)} will be expressed as q _{2 ′} . Similarly, the prefix information processing circuit 4. The set of transition destination states when the input character b is given to the state set q ₁ ' (this is q ₃ ' shown in FIG. 19. The elements of q ₃ ' are {(s ₂ , 2) , (s ₀ , 0)}), and the set of transition destination states (which becomes q ₀ ') when the input character ⊥ is given.

The prefix information processing circuit 4 determines each state and state transition of the Moore machines _{MA, N} by repeating these processes. FIG. 19 is a diagram illustrating the determined states and state transitions of Moore machines M _{A, N.} The prefix information processing circuit 4 then stores each determined state and state transition in the RAM 22. Examples of states and state transitions of Moore machines MA _{and N} stored in the RAM 22 are shown in FIGS. 20 and 21. FIG. 20 shows a state transition table (equivalent to the state transition diagram in FIG. 19) of the Moore machine M _A,N generated by the prefix information processing circuit 4 based on the automaton A' in FIG. is the state management table of Moore machine _MA,N .

As shown in FIG. 21, the state management table has columns of "state", "subset", and "current". The column "state" stores a list of possible states of Moore machines M _{A, N.} Each row of the column "Subset" stores elements included in the states of the Moore machines M _A,N (specifically, one or more states (states with counters) of the automaton A'). The column "Current" is an area for storing the current state of the Moore machine. Details will be described later, but the state corresponding to the row in which "1" is stored in the column "Current" is the state of the Moore machine. This is the current state.

The state transition table in FIG. 20 represents state transition rules (transition functions) of Moore machines MA _,N . The state transition table has a plurality of rows, and each row (denoted as δ ₀ to δ ₁₁ ) represents a transition specification of the Moore machine M _A,N . As shown in FIG. 20, each row of the state transition table has columns for "pre-transition state", "post-transition state", and "input". For example, for the top row of the state transition table (the row that describes the specifications of transition δ ₀ ), "q ₀ '" and "q ₁ '" and "a" are stored. This means that when the state before transition is q ₀ ', the state after transition becomes q ₁ ' when input character string "a" is given.

The state transition table and state management table of Moore machines _{MA, N} are stored in the non-buffer 22b of the RAM 22. Note that the state transition table and state management table generated by the prefix information processing circuit 4 may include information other than the information described here. Furthermore, the state transition table and state management table shown in FIGS. 20 and 21 are just examples, and the prefix information processing circuit 4 does not necessarily have to create information in the format shown in FIGS. 20 and 21. isn't it. The pre-information processing circuit 4 stores information necessary for the operation (state transition) of the Moore machines M _{A, N in} a storage area (RAM 22, etc.) in a format different from the format shown in FIGS. 20 and 21. Good too.

The operation of the Moore machine M _A,N requires the definition of a state, a transition function, and an output function, and the details of the output function will be described later. Furthermore, when the Moore machines M _{A, N} according to the second embodiment operate, the contents of the buffer 22a are also manipulated, which will also be described later.

Next, each functional block included in the prefix information processing circuit 4 will be explained. FIG. 22 is a diagram showing each functional block included in the prefix information processing circuit 4. As shown in FIG. As shown in FIG. 22, the prefix information processing circuit 4 includes processing modules (functional blocks): a generation module 22m1, a filter module 22m2, and a Moore machine module 22m3. These functional blocks are realized by the CPU 20 executing each program included in the prefix information processing circuit 4. Specifically, the generation module 22m1 is a functional block realized by the CPU 20 executing the generation program 22p1. The filter module 22m2 is a functional block realized by the CPU 20 executing the main program 22p2. The Moore machine module 22m3 is a functional block realized by the CPU 20 executing the subprogram 22p3.

The filter module 22m2 and the Moore machine module 22m3 are functional blocks that execute data processing (filtering processing), and the generation module 22m1 is a functional block that generates the Moore machine module 22m3 (subprogram 22p3). The generation module 22m1 generates the Moore machine module 22m3 by receiving instructions from the filter module 22m2. The Moore machine module 22m3 operates as the finite state machine (Moore machine) described above based on instructions from the filter module 22m2. Specifically, it receives sequence data (character string) one unit at a time (one character at a time) from the filter module 22m2, and changes the state and outputs information accordingly. Details of the processing of the generation module 22m1, filter module 22m2, and Moore machine module 22m3 will be described below.

Next, the flow of filtering processing performed by the prefix information processing circuit 4 will be explained. In the following, an example will be described in which the prefix information processing circuit 4 receives a sequence (character string) of 1-byte characters to which no timestamp is attached, one byte at a time, as sequence data.

23 and 24 are flowcharts of data processing processing (filtering processing) executed by the prefix information processing circuit 4. The flowchart in FIG. 23 shows the overall flow of filtering processing. FIG. 24 is a flowchart detailing a part (step S103) of the flowchart of FIG. 23.

First, the overall flow of filtering processing will be explained with reference to FIG. The filtering process is performed, for example, when the prefix information processing circuit 4 receives a process start instruction from the user via the operation unit 23, or when the prefix information processing circuit 4 receives a process start from an external device via the input interface 25. Executed when an instruction is received. When the filtering process is started, the filter module 22m2 receives matching conditions via the operation unit 23 or input interface 25, and generates a Moore machine from the received matching conditions (Step S101 in FIG. 23). Note that in step S101, the filter module 22m2 causes the generation module 22m1 to generate the Moore machine module 22m3. The generation module 22m1 defines the state of the Moore machine and the transition function as described above (in other words, the generation module 22m1 defines not only the program code executed by the CPU 20 but also the state management table described above). information (necessary for the operation of the Moore machine).

The definition of the state of the Moore machine and the definition of the transition function are as explained above using FIGS. 17 to 21. The generation module 22m1 generates a state management table as shown in FIG. 21 as a state definition result, and stores it in the non-buffer 22b (immediately after the state management table is generated, the Moore machine (Moore machine module 22m3) is in the initial state. Therefore, among the elements of the column "Current", the generation module 22m1 has a "Current" value of 1 in the row corresponding to the initial state (q ₀ ') (the top row in FIG. 21), and the other For the row, a state management table is generated in which the value of "Current" is set to 0). The generation module 22m1 generates a state transition table as shown in FIG. 20 as a result of the definition of the transition function, and stores it in the non-buffer 22b. The generation module 22m1 also creates a buffer 22a. Specifically, the generation module 22m1 secures an area having N memory blocks as shown in FIG. 16 on the RAM 22, and initializes the data area and flag area of these N memory blocks (all The flag "mask", that is, 0, is stored in the flag area of the memory block, and the block character ⊥ is stored in the data area of all memory blocks). Further, the definition of the output function will be described later.

Note that the filter module 22m2 does not necessarily need to receive the matching condition in step S101. For example, a Moore machine (Moore machine module 22m3) generated based on predetermined matching conditions may be installed in the prefix information processing circuit 4 in advance. In that case, when the filter module 22m2 executes the filtering process, it is preferable to execute this pre-installed Moore machine. If the Moore machine is installed in advance, the prefix information processing circuit 4 does not need to execute step S101, and the prefix information processing circuit 4 does not need to include the generation module 22m1.

Subsequently, in step S102, the filter module 22m2 receives sequence data via the input interface 25. Each time step S102 is executed once, the prefix information processing circuit 4 receives data for one unit of sequence data (here, a 1-byte character).

Next, the filter module 22m2 calls the Moore machine module 22m3, passes the data (1-byte character) received in step S102 to the Moore machine module 22m3, and causes the Moore machine module 22m3 to perform processing using the Moore machines M _{A, N} (step S103). Details of the process in step S103 will be described later, but once step S103 is executed, the Moore machine module 22m3 outputs the data stored in the memory block at the end of the buffer 22a. The filter module 22m2 outputs the data output from the Moore machine module 22m3 to an external device via the output interface 26.

Next, the filter module 22m2 determines whether input of sequence data has been completed (whether reception has been completed up to the terminal character of the character string) (step S104). For example, the input interface 25 notifies whether input of sequence data has been completed. However, the filter module 22m2 may detect whether input of sequence data has been completed using a method other than this. If it is determined that input of sequence data is not completed (step S104: NO), the filtering process returns to step S102. If it is determined that input of sequence data has been completed (step S104: YES), the filter module 22m2 performs the process of passing the block character ⊥ to the Moore machine module 22m3 N times (step S105). As mentioned earlier, N is the buffer size. Therefore, when the buffer size (N) is 2, step S103 is substantially performed twice in step S105. After step S105, the filtering process ends.

As mentioned earlier, when step S103 is executed, the data (1-byte character) passed to the Moore machine module 22m3 is input to (the data area of) the memory block of the buffer 22a, and The data stored in the last memory block is output. Therefore, when step S105 is executed, all data stored in the N memory blocks of the buffer 22a are output. That is, step S105 is performed in order to output all the data that was stored (remaining) in the memory block of the buffer 22a before the execution of step S105.

Next, details of the process performed in step S103 will be explained using FIG. 24. The process in FIG. 24 is executed by the Moore machine module 22m3. The Moore machine module 22m3 changes the state of the Moore machine (Moore machine module 22m3) and updates the contents of the buffer 22a every time it receives data from the filter module 22m2. In the following description, the buffer size N is assumed to be 2 (the number of memory blocks that the buffer 22a has is 2).

When the Moore machine module 22m3 receives data (1-byte character) from the filter module 22m2, it retrieves the data stored in the data area of the memory block (22a-N) at the end of the buffer 22a, and also retrieves the data stored in the data area of the memory block (22a-N) at the end of the buffer 22a. It is determined whether the flag stored in the flag area of the memory block (22a-N) is mask (step S201). If the flag of the memory block (22a-N) is not mask, that is, if the flag is pass (step S201: NO), the Moore machine module 22m3 transfers the data stored in the data area of the memory block (22a-N). is output (without modification) to the filter module 22m2 (step S202). The filter module 22m2 that has received the data from the Moore machine module 22m3 outputs the data to the outside via the output interface 26. Conversely, if the flag of the memory block (22a-N) is mask (step S201: YES), the Moore machine module 22m3 changes the retrieved data to the block character ⊥, and stores the changed data (block character ⊥) is output to the filter module 22m2 (step S203). The filter module 22m2 outputs the block character ⊥ received from the Moore machine module 22m3 to the outside via the output interface 26.

In step S204, the Moore machine module 22m3 stores the data received from the filter module 22m2 in the data area at the beginning of the buffer 22a. As mentioned above, before the data is stored at the beginning of the buffer 22a, the data in each memory block (22a-1, 22a-2, ... 22a-(N-1)) of the buffer 22a is and flags are respectively moved to the adjacent memory blocks on the left (22a-2, 22a-3, . . . 22a-N). In other words, the buffer 22a operates as a FIFO.

Next, the Moore machine module 22m3 executes the state transition of the Moore machine (Moore machine module 22m3) using the state transition table and state management table stored in the non-buffer 22b (step S205). An example in which the state transition table shown in FIG. 20 and the state management table shown in FIG. 21 are stored in the non-buffer 22b will be described below.

In the state management table of FIG. 21, the column "Current" records the current state of the Moore machine module 22m3. Each element of the column "Current" stores a value of either 0 or 1. The state corresponding to the row in which the value of the column "Current" is "1" is the current state. In FIG. 21, for the row whose column "state" is q ₁ ', the value of the column "Current" is "1", so the state management table of FIG. 21 shows that the current state is q ₁ '. .

After identifying the current state of the Moore machine module 22m3 in the manner described above, the Moore machine module 22m3 next uses the state transition table of FIG. 20 and the data received from the filter module 22m2 (hereinafter referred to as "input The transition destination state is determined based on the characters (referred to as "characters"). If the current state is q ₁ ' as shown in the state management table of FIG. 21 and the input character is "b", by referring to the state transition table of FIG. 20, the state after the transition will be q ₃ It turns out that ' Therefore, the Moore machine module 22m3 changes the current state to _q3 ' by rewriting the column "Current" in the state management table of FIG. Specifically, the Moore machine module 22m3 changes the value of the column "Current" in the row whose "state" is q ₁ ' to "0", and changes the value of the column "Current" in the row whose "state" is q ₃ ' to "0". Change to "1".

In step S206, the Moore machine module 22m3 changes the flag area of the first memory block (22a-1 in FIG. 16) of the buffer 22a to "mask".

In step S207, the Moore machine module 22m3 enters one or more states (hereinafter referred to as a "state subset") of the automaton A (or automaton A') included in the current state of the Moore machine module 22m3. , it is determined whether there is a state in which the value of the counter is equal to N (buffer size). The "state subset" is an element (state with one or more counters of the automaton A') stored in the column "subset" of the state management table in FIG. For example, a case will be described in which the current state of the Moore machine module 22m3 (state after execution of step S205) is q ₃ '. For _{the row} in which the column “state” of the state management table in _FIG . The state subset of the state q ₃ ' of the module 22m3 is {(s ₀ , 0), (s ₂ , 2)}. Among the states (counter-equipped states) included in this state subset, the counter value of state (s ₂ , 2) is 2 (that is, equal to the buffer size N). In such a case (step S207: YES), the Moore machine module 22m3 changes the flag areas of all memory blocks of the buffer 22a to "pass" (step S208). Conversely, if there is no state whose counter value is N in the state subset (step S207: NO), step S208 is not executed. For example, if the current state of the Moore machine module 22m3 is q ₁ ', the state subset of the state q ₁ ' is {(s ₀ , 0), (s ₁ , 1)}, so the counter value is N. A certain state does not exist. In such a case, step S208 is not executed.

In step S209, the Moore machine module 22m3 determines that the state subset of the current state of the Moore machine module 22m3 has the acceptance state of the automaton (automaton A in this embodiment) that is the source of the Moore machine module 22m3 as an element. (In other words, the state subset includes the acceptance state (in the examples of FIGS. 20 and 21, s ₂ ((s ₂ , 1) or (s ₂ , 2)) is the acceptance state). ). If the state subset of the current state of the Moore machine module 22m3 has an acceptance state (of the automaton that is the source of the Moore machine module 22m3) as an element (step S209: YES), the process proceeds to step S210. If the acceptance state is not included in the state subset (step S209: NO), the Moore machine module 22m3 ends the processing of the Moore machine module 22m3 without executing step S210.

In step S210, the Moore machine module 22m3 identifies all the counter values corresponding to the acceptance states included in the state subset, and calculates the maximum value of these counter values (hereinafter, this maximum value will be referred to as M). demand. Then, the Moore machine module 22m3 changes the flag area of the first M memory blocks among all the memory blocks of the buffer 22a to "pass". For example, if the current state of the Moore machine module 22m3 (the state after executing step S205) is q ₄ ′, the state subset of q ₄ ′ includes states (s ₂ , 1), (s ₂ , 2) is included. Therefore, the maximum value M of the counter value corresponding to the acceptance state is determined to be 2. In this case, the Moore machine module 22m3 changes the flag area of the first two memory blocks of all the memory blocks of the buffer 22a to "pass".

After step S210, the Moore machine module 22m3 ends the process, and the filter module 22m2 restarts the process immediately after step S103.

In the flowchart of FIG. 24, steps S201 to S203 are the operations of the output function of the Moore machine M _A,N . In steps S201 to S203, the operation shown in equation (6) in section 3.2 described above is performed. In equation (6), a ₁ and l ₁ respectively represent the contents of the data area and the contents of the flag area of the memory blocks 22a-N at the end of the buffer section 22a. According to equation (6), if l ₁ is "pass" (if the determination in step S201 of FIG. 24 is NO), a ₁ is output (step S202 of FIG. 24). Conversely, if _l1 is "mask" (YES in step S201 of FIG. 24), block characters are output (step S203 of FIG. 24).

Furthermore, in the flowchart of FIG. 24, by executing steps S206 to S210, processing corresponding to equation (5) in section 3.2 described above is performed.

As explained above, by executing the subprogram 22p3 in FIG. 24 (or it may be referred to as the Moore machine module 22m3 in FIG. 22), the operation (state transition) of the Moore machine is realized, and the buffer section The data in the contents of 22a is rewritten. At the same time, it is possible to output data that is masked (replaced with block characters) of data that clearly does not meet the matching conditions among the input sequence data.

Note that an example has been described above in which the prefix information processing circuit 4 receives a character string (sequence data) to which no time stamp is attached, and filters the received character string. In other words, the Moore machine (Moore machine module 22m3) operating in the prefix information processing circuit 4 was the same as that described in Section 3.2 of this specification. However, the Moore machine that operates in the prefix information processing circuit 4 is not limited to this. For example, a Moore machine according to the definition explained in Section 4.3 of this specification can also operate in the pre-information processing circuit 4. Specifically, when performing pattern matching on a character string (sequence data) to which a timestamp has been added, the prefix information processing circuit 4 uses a Moore machine (hereinafter referred to as This is called a ``Moore machine with real-time constraints'') to perform pattern matching.

The filtering process using the Moore machine with real-time constraints is generally similar to the filtering process described above. Below, we will mainly explain the differences between the filtering process using a Moore machine with real-time constraints and the filtering process described above, and will omit explanations that are common to both.

As explained in Section 4.3 of this specification, in a Moore machine with real-time constraints, only flags are stored in the buffer portion of the state space. Therefore, when the prefix information processing circuit 4 operates a Moore machine with real-time constraints, the prefix information processing circuit defines a buffer 22a that does not have a data area (row 221a is removed from the buffer 22a shown in FIG. 16). buffer is defined).

Furthermore, when the Moore machine with real-time constraints operates, data is not stored in the buffer 22a, so processing that is slightly different from the processing of the Moore machine module 22m3 described above is executed. The flow of processing when the prefix information processing circuit 4 operates a Moore machine with real-time constraints will be explained using the flowcharts shown in FIGS. 25 and 26.

First, the processing flow of a Moore machine with real-time constraints (hereinafter sometimes simply referred to as a "Moore machine") will be described using FIG. 26. Since many of the processes in FIG. 26 are the same as those in FIG. 24, the following will mainly explain the differences from FIG. 24 among the steps in FIG. 26.

As shown in FIG. 26, the real-time constrained Moore machine executes step S2020 instead of steps S201 to S203 in FIG. In other words, when the Moore machine receives data (1-byte character) from the filter module 22m2, it does not perform the processing shown in FIG. The flag stored in the flag area of the memory block (22a-N) is output (step S2020). The processing after step S205 is the same as the processing in FIG. 24, so the explanation will be omitted.

Since the Moore machine with real-time constraints does not have a data area in the buffer 22a, unlike the process shown in FIG. 24, it does not convert the data contained in the data area or output the data. The filter module 22m2 of the pre-information processing circuit 4 performs data conversion and output.

The processing of the filter module 22m2 when filtering processing by a Moore machine with real-time constraints is executed will be described using FIG. 25. First, the filter module 22m2 causes the generation module 22m1 to generate a Moore machine (step S1010). This process is similar to step S101 in FIG. 23, but differs from step S101 in FIG. 23 in that the generated Moore machine is a Moore machine with real-time constraints. Further, in step S1010, the filter module 22m2 secures a storage area on the RAM 22 for temporarily storing data received via the input interface 25. The storage area secured by the filter module 22m2 is a FIFO buffer, and this FIFO buffer has (N+1) memory blocks, each memory block containing data for one character (data received via the input interface 25). ) can be stored.

Subsequently, the filter module 22m2 receives sequence data via the input interface 25 (step S1020). Step S1020 is the same process as step S102 in FIG. However, in step S1020, the filter module 22m2 also performs a process of storing the received sequence data in the FIFO buffer secured in step S1010.

Next, the filter module 22m2 passes the data (1-byte character) received in step S1020 to the Moore machine (Moore machine with real-time constraints). In response, the real-time constrained Moore machine executes the process shown in FIG. 26 (step S1030). As mentioned earlier, when the Moore machine with real-time constraints executes the process shown in FIG. 26, it outputs the flag (pass or mask) stored in the flag area of the memory block (22a-N) at the end of the buffer 22a. do.

Next, the filter module 22m2 determines whether the processes of steps S1020 and S1030 have been executed N times. As mentioned earlier, N is the buffer size. If the processes in steps S1020 and S1030 have not been executed N times yet (step S1040: NO), the process returns to step S1020. If the processes in steps S1020 and S1030 have been executed N times (step S1040: YES), the filter module 22m2 executes the processes in and after step S1050.

In step S1050, the filter module 22m2 receives sequence data via the input interface 25. This is the same process as step S1020. In step S1050, the filter module 22m2 passes the data (1-byte character) received in step S1050 to the Moore machine. In other words, step S1050 is the same process as step S1030.

As described above, by executing step S1060, the Moore machine outputs a flag (pass or mask). In step S1070, the filter module 22m2 determines whether the output of the Moore machine is pass. If the output of the Moore machine is pass (step S1070: YES), the filter module 22m2 outputs one character worth of data stored at the end of the FIFO buffer to an external device via the output interface 26 (step S1080). . In step S1080, the data stored at the end of the FIFO buffer having (N+1) elements (memory blocks) is output, so for example, if step S1050 is the (N+1)th data reception process, step S1080 The data received the first time is output. On the other hand, if the output of the Moore machine is mask in step S1070 (step S1070: NO), the filter module 22m2 outputs the block character ⊥ to an external device via the output interface 26 (step S1090).

Next, the filter module 22m2 determines whether input of sequence data has been completed (whether reception has been completed up to the terminal character of the character string) (step S1100). The process in step S1100 is similar to step S104 in FIG. 23. If it is determined that input of sequence data is not completed (step S1100: NO), the process returns to step S1050. If it is determined that input of sequence data has been completed (step S1100: YES), step S1100 is performed next.

In step S1110, the filter module 22m2 passes the block character ⊥ to the Moore machine. As a result, a flag is output from the buffer 22a of the Moore machine. Subsequently, in step S1120, the processes of steps S1070 to S1090 are performed based on the state of the flag (pass or mask) output from the Moore machine in step S1100.

Next, the filter module 22m2 determines whether the processes of steps S1110 and S1120 have been performed N times (step S1130), and if the processes of steps S1110 and S1120 have been performed N times (step S1130: YES), the filter module 22m2 executes the processes. finish. If the processes in steps S1110 and S1120 have not been performed N times yet (step S1130: NO), the filter module 22m2 executes step S1110 again.

The processing in steps S1110 to S1130 is performed for the same purpose as step S105 in FIG. 23. In other words, immediately before step S1110 is executed, N (unoutput) flags remain in the memory block of the buffer 22a, so the filter module 22m2 executes steps S1110 to S1130 N times to The flag remaining in the memory block of the buffer 22a is output, and based on the output flag, the filter module 22m2 determines data to be output to an external device.

As explained above, the prefix information processing circuit 4 according to the second embodiment can output data that has been processed to remove data that clearly does not match the matching condition from among the input sequence data. can. However, in the prefix information processing circuit 4 according to the second embodiment, although a certain data string (for example, a character string) in the input sequence data does not actually match the matching condition, the data string (character string) matches the matching condition. If it is uncertain whether there is a match or not, the data string is output without being removed (without any processing).

This case may occur, for example, when the determination in step S207 in FIG. 24 is YES. An example will be explained using FIGS. 17 to 21 and 24. For example, a Moore machine generated based on the automaton A shown in FIG. 17 (having five states q ₀ ' to q ₄ ' shown in FIG. Assume a Moore machine with a buffer size of 2 and a buffer size of 2. When the current state of such a Moore machine is q ₂ ', the state subset of state q ₂ ' is {(s ₀ , 0), (s ₁ , 1), (s ₁ , 2)}. In this case, as can be seen from FIG. 24 (particularly steps S207 and S208), the data stored in the buffer 22a at this point is output as is (without being converted into block characters). This is because the flag areas of all memory blocks of the buffer 22a are changed to "pass" in step S208. However, since the state subset at this time does not include the acceptance state (s ₂ ) as an element, the data string stored in the buffer 22a is based on the matching condition described as automaton A shown in FIG. However, it is not certain whether the entire matching condition is met. In such a case, the prefix information processing circuit 4 according to the second embodiment outputs the data stored in the buffer 22a as is (without being converted into block characters), so there is a possibility that the matching condition will be met. No data will be deleted.

Furthermore, in the above example, the prefix information processing circuit 4 converts data that clearly does not match the matching condition to block characters ⊥ in order to remove data that clearly does not match the matching condition. The method for removing data that clearly does not match is not limited to this. For example, as a result of the prefix information processing circuit 4 converting data that clearly does not match the matching condition out of the input sequence data into block characters ⊥, the block characters ⊥ occur consecutively multiple times in the converted data string. For example, if the prefix information processing circuit 4 contains a character string that appears in good. Specifically, after the prefix information processing circuit 4 converts the character string "abbbbbbb" into "ab⊥⊥⊥⊥⊥" by performing the processing described above (FIGS. 23 and 24), " ab⊥⊥⊥⊥⊥" may be converted to "ab⊥5" and output to an external device (in other words, "⊥5" represents 5 consecutive block characters ⊥) . By performing such conversion, the data size is substantially compressed, so it is possible to reduce the amount of data output to an external device.

FIG. 27 is a flowchart showing the determinization process of the real-time automaton when configuring the prefix information processing circuit 4 according to the second embodiment.

In steps S61 to S63 in FIG. 27, the definition of the state s ₀ ^d to the state space S ₀ in the automaton, the initialization of the current state space S _curr ^d and the state space S ^d , and the initialization of the output function Λ _r ^d are performed. Perform processing. In steps S64 to S75, when the current state space S _curr ^d is not empty, processes in steps S67 to S74 are executed. Furthermore, in steps S65 to S72, the processes of steps S67 to S69 are executed for each state s ^d εS _curr ^d . Furthermore, in steps S66 to S71, the processes of steps S67 to S69 are executed for each character a∈Σ. Furthermore, in steps S68 to S70, the process of step S69 is executed for each interval I'∈J (J is the sparsest division of the set of intervals, as shown in step S67). In step S76, the state space S _F ^d of the filtering result is defined as a subset of the state space S ^d , and the intersection with the state space S _F of the filtering result is non-empty, and the determination process is ended. do.

As explained above, non-deterministic real-time time can be converted into a deterministic automaton by executing the determinization process shown in FIG. 27.

FIG. 28 is a flowchart showing an approximation process for approximating a real-time constrained automaton to a real-time automaton when configuring the prefix information processing circuit 4 according to the second embodiment. Note that the superscript of the parameter rt represents the real-time time parameter.

In steps S81 and S82 in FIG. 28, the state s ₀ ^rt in the automaton is defined and the state spaces S ^rt and S ^rt _curr are initialized. In steps S83 to S99, when the current state space S ^rt _curr is not empty, processes in steps S84 to S98 are executed. Furthermore, in steps S85 to S96, the processes of steps S87 to S94 are executed for each (s, Z)∈S ^rt _curr . Furthermore, in steps S86 to S95, the processes of steps S87 to S94 are executed for each (s; a; δ, λ, s')∈Σ. Note that up(Z) in step S87 represents the passage of time. Further, reset (Z', λ) in step S89 represents initialization of the clock variable included in λ. Further, S ^rt _next in step S94 and the like represents the next state space to be added next to the real-time state space S ^rt . Furthermore, the zone of the DBM in step S90 is a zone defined by a known Difference Bound Matrix. In step S100, the state space S ^rt _F of the filtering result is set to {(s, Z)εS ^rt |sεS _F }, thereby terminating the approximation process.

As explained above, by executing the approximation process shown in FIG. 28, a real-time constrained automaton can be approximated to a real-time automaton.

Automatic stop mechanism in case of abnormality.
FIG. 29 is a block diagram showing a configuration example of a vehicle control system having an automatic stop mechanism in the event of an abnormality according to the third embodiment.

In FIG. 29, the vehicle control system is configured such that sensor devices 1A and 1B are connected to a vehicle controller 30 via communication lines 10a and 10b, respectively.

In the sensor device 1A, the vehicle speed detected by the vehicle speed sensor 3a and the angular velocity detected by the acceleration sensor 3b are input to the front information processing circuit 4a. The prefix information processing circuit 4a has the same configuration as the prefix information processing circuit 4 according to the second embodiment. Further, the front information processing circuit 4a processes the input sequence data of vehicle speed and acceleration with real time so as to remove data that is easily found not to match the above matching condition, and processes the processed sequence data with real time. The data is transmitted to the post-information processing circuit 5 via the communication line 10a.

In the sensor device 1B, the slope detected by the slope sensor 3c, the mass detected by the mass sensor 3d, and the input data (emergency stop instruction data) input to the input data section 3e to the actuator are subjected to preliminary information processing. It is input to circuit 4b. The prefix information processing circuit 4b also has the same configuration as the prefix information processing circuit 4 according to the second embodiment. The pre-information processing circuit 4b processes the input slope, mass, and sequence data with real time of the input data so as to remove data that is easily found not to match the above matching condition, and processes the real time data after processing. The attached sequence data is transmitted to the trailing information processing circuit 5 via the communication line 10b.

In the automobile controller 30, the rear end information processing circuit 5 receives the sequence data processed by the front end information processing circuit 4a and the sequence data processed by the front end information processing circuit 4b. Then, the postfix information processing circuit 5 extracts sequence data that matches the above-mentioned matching conditions (the matching conditions used by the prefix information processing circuit 4a and the prefix information processing circuit 4b) from these sequence data. Then, the extracted sequence data is output to the failure detection section 31. The failure detection unit 31 determines whether or not a predetermined failure condition is matched based on the input sequence data, and when the failure condition is matched, outputs information to that effect to the vehicle driving control unit 32. , performs predetermined control processing such as, for example, stopping the car in an emergency.

As described above, the prefix information processing circuit 4b does not process (do not remove) data that matches a part of the matching condition but is not necessarily sure whether it matches the entire matching condition. Therefore, in the data extraction process performed by the postfix information processing circuit 5, data matching the above-mentioned matching conditions is extracted from the processed sequence data received from the prefix information processing circuit 4a and the prefix information processing circuit 4b. Processing to extract all is performed. Specifically, for example, the prefix information processing circuit 4a or the prefix information processing circuit 4b may output a character string (sequence data) in which some characters (characters that clearly do not match the matching conditions) have been rewritten to block characters ⊥. When transmitting to the position information processing circuit 5, the position information processing circuit 5 not only removes block characters from the character string, but also identifies character strings that match the matching condition among the character strings that have not been replaced with block characters ⊥. It also performs processing to determine whether it is included and extract character strings that match the matching conditions.

Note that the processing load for the trailing information processing circuit 5 to extract a character string (sequence data) that matches the matching condition is carried out by the front end information processing circuit 4a and the front end information processing circuit 4b as shown in FIG. When the prefix information processing circuit 4a and the prefix information processing circuit 4b are provided in the system, it is lower than when the prefix information processing circuit 4a and the prefix information processing circuit 4b are not provided. Data (character strings) that clearly do not match the matching conditions are removed (converted to block characters) by the prefix information processing circuit 4a and the prefix information processing circuit 4b, so that they are searched by the postfix information processing circuit 5. This is because the amount of data is significantly reduced.

As explained above, according to the third embodiment, failures can be detected by monitoring log data (vehicle speed, acceleration, slope, mass, etc.) of a running vehicle using the vehicle control system, and emergency If it is necessary to stop, an appropriate input is given to the vehicle driving control section 32 to perform an emergency stop. In particular, by attaching the front information processing circuits 4a and 4b to the sensor devices 1A and 1B, respectively, the amount of data transferred through the communication lines 10a and 10b can be reduced and more data can be handled.

Optimization of travel routes for semi-connected cars.
FIG. 30 is a block diagram showing a configuration example of a vehicle control system having a travel route optimization mechanism for a semi-connected car according to the fourth embodiment. The vehicle control system is configured by connecting a vehicle 40 to a server device 50 via a network including communication lines 10c and 10d. Here, the semi-connected car is one in which the control unit of the car 40 does not constantly connect to the server device 50, but controls the driving of the car 40 by connecting as needed.

In the automobile 40, the accelerator data detected by the accelerator sensor 3f and the accelerator pedal data detected by the brake pedal sensor 3g are input to the drive torque estimation section 33. The driving torque estimating section 33 estimates the driving torque using a known method based on the input accelerator data and accelerator pedal data, and outputs the estimated driving torque to the estimated vehicle speed calculating section 34 . Further, the gradient detected by the gradient sensor 3c and the mass detected by the mass sensor 3d are input to the estimated vehicle speed calculation section 34. The estimated vehicle speed calculation section 34 calculates an estimated vehicle speed using a known method based on the three input data and outputs it to the deviation amount calculation section 35. By comparing the calculated estimated vehicle speed with the vehicle speed detected by the vehicle speed sensor 3a, the deviation amount calculation unit 35 calculates a deviation amount that can estimate the road condition based on the deviation of the vehicle speed, and sends the calculated deviation amount to the front information processing circuit 4c. Output. The prefix information processing circuit 4c has the same configuration as the prefix information processing circuit 4 according to the second embodiment. Further, the prefix information processing circuit 4c processes the input sequence data with real time of the deviation amount so as to remove data that is easily found not to match the above matching condition, and processes the processed sequence data with real time. is transmitted to the postfix information processing circuit 5 of the server device 50 via the communication line 10c.

In the server device 50, the rear information processing circuit 5 receives the sequence data processed by the front information processing circuit 4c, extracts sequence data that matches the above matching condition, and uses the extracted sequence data to identify abnormal roads. It is output to the state detection section 51. The abnormal operating state detection unit 51 determines whether the input sequence data matches a predetermined "abnormal road condition" condition (for example, if the amount of deviation is equal to or greater than a predetermined threshold, the road condition is determined to be abnormal). If the condition is matched, information to that effect is output to the driving plan control section 52. The driving plan control unit 52 detects unfavorable road conditions based on the input information, optimizes the driving plan according to the road conditions, and transmits data of the optimized driving plan via the communication line 10d. By outputting to the driving control unit 36 of the automobile 40, the driving of the automobile 40 is optimized.

As described above, according to the fourth embodiment, the driving log (accelerator data, brake pedal data, gradient, mass, vehicle speed, and predetermined calculation data based on the accelerator data, brake pedal data, and predetermined calculation data based on the accelerator data) of the semi-connected car that is running is sent to the server device 50 as appropriate. It is transmitted via the communication line 10c. Here, by monitoring the data by the abnormal road condition detection unit 51, unfavorable road conditions are detected, and the driving plan is optimized according to the road conditions. Here, by providing the front end information processing circuit 4c in the automobile 40 which is a semi-connected car, and providing the rear end information processing circuit 5 in the server device 50, the amount of data transfer can be reduced. It can operate properly even under various environmental conditions.

Monitoring attacks on server equipment and blocking access.
FIG. 31 is a block diagram showing a configuration example of a communication system having a mechanism for monitoring attacks on a server device and blocking access according to the fifth embodiment. The communication system is configured by connecting a server device 60 and a router device 70 via a network including a communication line 10e.

In the server device 60 , an access log collection unit 61 collects logs (access source information, time, etc.) regarding external accesses to the server device 60 , and outputs the sequence data to the prefix information processing circuit 62 . The prefix information processing circuit 62 has the same configuration as the prefix information processing circuit 4 according to the second embodiment. The prefix information processing circuit 62 processes the input sequence data with real time so as to remove data that is easily found not to match the matching condition, and converts the processed sequence data with real time into postfix information. It is transmitted to the processing circuit 63. The postscript information processing circuit 63 receives input sequence data with real time, extracts sequence data that matches the above matching condition, and outputs the extracted sequence data to the attack detection section 64. The attack detection unit 64 refers to predetermined threshold data based on the input sequence data to detect an aggressive access to the server device 60, and transmits the detected access information to the router device via the communication line 10e. 70's access control unit 71. In response to this, the access control unit 71 performs control to block access to the server device 60 based on the input detected access information.

As explained above, according to the fifth embodiment, communication logs from the outside are monitored in the server device 60 such as the WWW using a real-time condition extracting device including the prefix information processing circuit 62 and the postfix information processing circuit 63. By doing this, it detects attacks from the outside and blocks access from the attacker by providing appropriate input to the router. By using the real-time data filter section of the real-time condition extracting device, the CPU time required for data processing can be reduced and monitoring can be performed without impairing the original operation of the server device 60.

In the above embodiments and examples, the prefix information processing circuit 4 generates a Moore machine based on an automaton that describes predetermined matching conditions regarding input event sequence data, and uses the generated Moore machine. Then, filtering is performed to substantially remove data that does not match the matching condition from the sequence data, and sequence data as a result of filtering is output. However, the present invention is not limited to this, and the model generated for filtering is not limited to the Moore machine, but may be any other finite state machine such as a Mealy machine.

Features of this embodiment and differences from Patent Documents 2 and 3.

(1) Patent document 2
In Patent Document 2, a program description (1) that defines multiple devices using a programming language that can describe parallel operations is input, the input program description is converted into an intermediate representation (S2), and real-time constraints are set. Based on the generated parameters, an intermediate representation based on a hardware description language (S3) and a circuit description are synthesized (S4). Intermediate expressions are concurrent control flow flags, timed automata with concurrent parameters, etc. Parametric model checking is performed for parameter generation. The program description uses the run method to define the device and the barrier synchronization to define the device's clock synchronization. This makes it possible to design a bus system that meets real-time constraints.

Patent Document 2 specifically describes a verification process for design automation in order to efficiently design a bus system to satisfy real-time constraints when designing a circuit using a language that can describe parallel operations such as JAVA (registered trademark). Modeling is performed as preprocessing. One step is to convert a concurrent control flow graph (C-CFG) to a concurrent parameterized timed automaton (C-TNFA), and then to a parameterized timed automaton (TNFA). When converting from C-CFG to C-TNFA, processing is performed to delete state transitions that do not meet the assumptions in the subsequent verification process, and when converting from C-TNFA to TNFA, parallel execution of operations that do not require bus ownership is performed. A process is performed to set an upper limit on the transition time and delete states that do not satisfy the upper limit.

Patent Document 2 discloses mask processing based on post-processing in pre-processing, but does not disclose specific methods of the present invention such as determinization and buffer optimization based on time constraints in an automaton.

(2) Patent document 3
The method of Patent Document 3 is a method of converting a software source code into a test code using a computer, and includes the steps of inputting the software source code and inputting a plurality of different conversion rules. inputting non-functional rules that are constraints regarding process performance; and converting the source code into non-functional inspection code written in the input language of a verification tool using the plurality of different conversion rules and the non-functional rules. and converting into.

In Patent Document 3, in particular, when converting the behavior of software into an input language (inspection code) as a pre-processing of software inspection, the software is converted into a timed automaton in which each component (function) of the software is given a processing time depending on the execution environment. , discloses a technology that eliminates the repetitive part when there is a specific defect only during repeated execution, reduces the number of states, and makes it possible to detect other defects, thereby avoiding state explosion that increases calculation time. ing.

However, although Patent Document 3 discloses mask processing in preprocessing, it does not disclose specific methods of the present invention such as determinization based on time constraints in an automaton and buffer optimization.

As described above in detail, according to the information processing apparatus and method according to the present invention, processing can be performed more efficiently than the time series correlation extraction apparatus according to the conventional example.

1, 1A, 1B Sensor device 2 Monitor device 3 Sensor 3a Vehicle speed sensor 3b Acceleration sensor 3c Gradient sensor 3d Mass sensor 3e Input data section to actuator 3f Accelerator sensor 3g Brake pedal sensor 4, 4a, 4b, 4c Front information processing circuit 5 Post-information processing circuit 6 Display section 7 Filter section 8 Pattern matching section 10, 10a to 10e Communication line 11 Filter section 12 Masking application section 20 CPU
21 ROM
22 RAM
22a Buffer section 22b Non-buffer section 23 Operation section 24 Display section 25 Input interface 26 Output interface 27 Bus 30 Vehicle controller 31 Failure detection section 32 Vehicle operation control section 33 Drive torque estimation section 34 Estimated vehicle speed calculation section 35 Deviation amount calculation section 36 Traveling Control unit 40 Car 50 Server device 51 Abnormal road condition detection unit 52 Driving plan control unit 60 Server device 61 Access log collection unit 62 Prefix information processing circuit 63 Postfix information processing circuit 64 Attack detection unit 70 Router device 71 Access control unit

Claims (8)

A finite state machine is generated based on a predetermined matching condition regarding input sequence data of events, and using the generated finite state machine, sequence data in which events that do not match the matching condition among the sequence data are masked. Equipped with an information processing circuit that outputs
The sequence data is real-time time-stamped event sequence data,
The matching condition is described as a real-time constrained automaton,
The finite state machine has a FIFO buffer having N memory blocks, and information describing state transition rules of the finite state machine, and each of the N memory blocks matches the matching condition. an area for storing a flag representing either a first state indicating that the matching condition is not met or a second state indicating that the matching condition is not met;
Information processing device. The sequence data is a time-stamped character string in which a time stamp is attached to each unit of data of the sequence data, and the characters constituting the character string are elements in a predetermined character set,
Each time the finite state machine receives input of one unit of the sequence data,
outputting a flag stored in a memory block at the end of the buffer;
Transitioning the state of the finite state machine based on the received data and the rule;
storing a second state in a memory block at the head of the buffer as an initial value of a flag corresponding to the received data;
Each of the states that the finite state machine can take is a set of a state s that the automaton can take and a set (s, n) of a counter n corresponding to the number of transitions required to reach the state s from the initial state {( s ₁ , n ₁ ), (s ₂ , n ₂ ), ... (s _k , n _k )} (k is an integer of 1 or more),
The information processing circuit includes:
(1) If there is a set whose counter value is N in the set of sets included in the state after the state transition of the finite state machine, N memories in the buffer change all flags of the block to the first state,
(2) If an acceptance state is included in the states s ₁ , s ₂ , ... s _k included in the state of the finite state machine, the maximum value M of the counter associated with the acceptance state and changing the flags of M memory blocks from the beginning of the buffer to the first state;
When the flag output by the finite state machine is in the first state, outputting one unit of data corresponding to the flag output by the finite state machine to the outside;
When the flag output by the finite state machine is in the second state, one unit of data corresponding to the flag output by the finite state machine is converted into characters not included in the character set and output to the outside. ,
The information processing device according to claim 1 . When characters not included in the character set are consecutive, the finite state machine outputs a binary representation of the number of consecutive characters or one character.
Information processing device according to claim 2. An information processing system comprising a first information processing device and a second information processing device connected to the first information processing device via a predetermined communication line or network,
The first information processing device generates a finite state machine based on a predetermined matching condition regarding the input sequence data of events, and uses the generated finite state machine to process data of the sequence data that meets the matching condition. Equipped with an information processing circuit that outputs sequence data with unmatched events masked,
The second information processing device extracts data matching the matching condition from the masked sequence data output by the first information processing device, and outputs the extracted data. Equipped with a circuit,
The sequence data is real-time time-stamped event sequence data,
The matching condition is described as a real-time constrained automaton,
The finite state machine has a FIFO buffer having N memory blocks, and information describing state transition rules of the finite state machine, and each of the N memory blocks matches the matching condition. an area for storing a flag representing either a first state indicating that the matching condition is not met or a second state indicating that the matching condition is not met;
Information processing system. The sequence data is a time-stamped character string in which a time stamp is attached to each unit of data of the sequence data, and the characters constituting the character string are elements in a predetermined character set,
Each time the finite state machine receives input of one unit of the sequence data,
outputting a flag stored in a memory block at the end of the buffer;
Transitioning the state of the finite state machine based on the received data and the rule;
storing a second state in a memory block at the head of the buffer as an initial value of a flag corresponding to the received data;
Each of the states that the finite state machine can take is a set of a state s that the automaton can take and a set (s, n) of a counter n corresponding to the number of transitions required to reach the state s from the initial state {( s ₁ , n ₁ ), (s ₂ , n ₂ ), ... (s _k , n _k )} (k is an integer of 1 or more),
The information processing circuit included in the first information processing device includes:
(1) If there is a set whose counter value is N in the set of sets included in the state after the state transition of the finite state machine, N memories in the buffer change all flags of the block to the first state,
(2) If an acceptance state is included in the states s ₁ , s ₂ , ... s _k included in the state of the finite state machine, the maximum value M of the counter associated with the acceptance state and changing the flags of M memory blocks from the beginning of the buffer to the first state;
If the flag output by the finite state machine is in a first state, transmitting one unit of data corresponding to the flag output by the finite state machine to the second information processing device;
When the flag output by the finite state machine is in the second state, one unit of data corresponding to the flag output by the finite state machine is converted into a character that is not included in the character set, and the second state is converted. Send to information processing device,
The information processing system according to claim 4 . When characters not included in the character set are consecutive, the finite state machine transmits a binary representation of the number of consecutive characters or one character to the second information processing device.
Information processing system according to claim 5. Accepts input of matching conditions to search for a predetermined pattern included in sequence data consisting of multiple symbols,
generating, based on the received matching condition, a finite state machine configured to generate information for masking events that do not match the matching condition in the sequence data ;
The sequence data is real-time time-stamped event sequence data,
The matching condition is described as a real-time constrained automaton,
The finite state machine has a FIFO buffer having N memory blocks, and information describing state transition rules of the finite state machine, and each of the N memory blocks matches the matching condition. an area for storing a flag representing either a first state indicating that the matching condition is not met or a second state indicating that the matching condition is not met;
Information processing circuit. An information processing method using an information processing device that performs predetermined processing on input event sequence data, the method comprising:
The information processing circuit included in the information processing device includes:
receiving an automaton describing predetermined matching conditions regarding sequence data;
generating a finite state machine based on the automaton;
a step of accepting input of the sequence data;
Processing the sequence data using the finite state machine so as to mask events that do not match the matching condition in the sequence data;
outputting the masked sequence data;
Run
The sequence data is real-time time-stamped event sequence data,
The matching condition is described as a real-time constrained automaton,
The finite state machine has a FIFO buffer having N memory blocks, and information describing state transition rules of the finite state machine, and each of the N memory blocks matches the matching condition. an area for storing a flag representing either a first state indicating that the matching condition is not met or a second state indicating that the matching condition is not met;
Information processing method.

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