JP7379005B2 - Imaging element, imaging device, and control method - Google Patents

Description

The present invention relates to an image sensor, an image sensor having the image sensor, and a method for controlling the image sensor.

Patent Document 1 discloses an image sensor in which an AD conversion circuit that performs analog-to-digital (hereinafter referred to as AD) conversion of a signal output from a pixel is arranged for each pixel. That is, a differential input circuit that outputs a signal when the voltage of the input signal is higher than the reference signal, and a faster transition speed when the comparison signal representing the comparison result between the input signal voltage and the reference signal voltage is inverted. A positive feedback circuit.

The current source of the differential input circuit is a transistor. Even if the current value supplied to the circuit is set to a small value, the output transition time is shortened by operating the positive feedback circuit.

International Publication No. 2016/136448

In the technique disclosed in Patent Document 1 in which the comparator is driven with a relatively small current value, noise is likely to occur because slight changes in current cause variations in the inversion timing of comparison signals for each pixel. Therefore, although global shutter drive that suppresses the power consumption of comparators that operate simultaneously in parallel has been achieved, there is a possibility that an appropriate image (for example, an image with less noise) cannot be obtained according to the drive control of the image sensor. There is.

In view of the above circumstances, an object of the present invention is to provide an imaging device, an imaging device, and a control method that can appropriately acquire images according to drive control of the imaging device.

In order to achieve the above object, an image sensor of the present invention has a plurality of pixels each including a pixel circuit that outputs a pixel signal corresponding to the amount of incident light, and an AD conversion circuit that converts the pixel signal from AD to AD. Control that controls to switch a drive current value for driving each of the plurality of AD conversion circuits based on the number of the AD conversion circuits that are two-dimensionally arranged and operate in parallel. It is characterized by comprising a part.

According to the present invention, an image can be appropriately acquired according to drive control of an image sensor.

FIG. 1 is a schematic diagram showing a semiconductor substrate structure of an image sensor according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the functional configuration of a unit pixel according to the first embodiment of the present invention. FIG. 3 is an equivalent circuit diagram of a pixel circuit, a differential input circuit, and a positive feedback circuit of a pixel according to the first embodiment of the present invention. 3 is a timing chart showing the operation of the AD conversion circuit according to the first embodiment of the present invention. 1 is a configuration diagram of a control section, a differential input circuit, and a positive feedback circuit according to a first embodiment of the present invention. FIG. FIG. 3 is a schematic diagram showing an operation in a global shutter drive mode according to the first embodiment of the present invention. FIG. 3 is a schematic diagram showing the operation in column parallel drive mode according to the first embodiment of the present invention. FIG. 3 is a schematic diagram showing the operation of the thinning GS drive mode according to the first embodiment of the present invention. FIG. 3 is a schematic diagram showing the operation of the region parallel drive mode according to the first embodiment of the present invention. FIG. 3 is a schematic diagram showing the operation of the AF drive mode according to the first embodiment of the present invention. FIG. 2 is a block diagram showing the overall configuration of an imaging device according to a second embodiment of the present invention. FIG. 7 is an explanatory diagram of a drive control method in an imaging device according to a second embodiment of the present invention.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Each embodiment described below is only an example of a configuration that can realize the present invention. Each of the following embodiments can be modified or changed as appropriate depending on the configuration of the device to which the present invention is applied and various conditions. Therefore, the scope of the present invention is not limited by the configurations described in each embodiment below. For example, a configuration in which a plurality of configurations described in the embodiments are combined can be adopted as long as there is no mutual contradiction.

In the following description, the High level and Low level of the digital signal pulse may be expressed as "High" and "Low", respectively.

<First embodiment>
The configuration and driving method of an image sensor 100 according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 10.

FIG. 1 is a schematic diagram showing a semiconductor substrate structure of an image sensor 100 according to a first embodiment of the present invention. As shown in FIG. 1, the image sensor 100 is formed by laminating a first substrate 110 and a second substrate 120 that receive light that has passed through an optical system (not shown).

The first substrate 110 has a plurality of pixel regions 111 arranged in a matrix (two-dimensionally), each including a photoelectric conversion section. The second substrate 120 has a plurality of pixel regions 121 each including an AD conversion section and arranged in a matrix like the first substrate 110, and also has a control section 122.

One pixel region 111 of the first substrate 110 corresponds to one pixel region 121 of the second substrate 120, and they are connected to each other via a connecting portion. The circuits in the pixel area 111 and the circuits in the pixel area 121 that correspond to each other work together to function as one unit pixel of the image sensor 100.

The circuits in the pixel regions 111 and 121 of the different substrates 110 and 120 are connected in units of pixels by, for example, a known connection method (microbump connection, direct bonding connection structure, etc.). Note that the image sensor 100 is not limited to the two-layer laminated structure as described above, and may be configured with a single substrate with a non-laminated structure, or may have a laminated structure of three or more layers, for example.

FIG. 2 is a block diagram showing the functional configuration of the unit pixel 200 according to the first embodiment of the present invention. As shown in FIG. 2, one pixel 200 includes a pixel circuit 210 and an AD conversion circuit 201. AD conversion circuit 201 includes a differential input circuit 220, a positive feedback circuit 230, and a latch circuit 240. As described above, one pixel 200 is configured by combining one pixel region 111 and one pixel region 121.

The pixel circuit 210 is a circuit including a photoelectric conversion section, and outputs a pixel signal having a voltage corresponding to the amount of incident light to the AD conversion circuit 201 (differential input circuit 220).

The AD conversion circuit 201 is a slope comparison type AD conversion circuit.

The differential input circuit 220 compares the pixel signal input from the pixel circuit 210 with a reference signal Ref whose voltage changes proportionally over time, and generates a comparison signal indicating the magnitude relationship between the pixel signal and the reference signal Ref. is output to the latch circuit 240 via the positive feedback circuit 230.

The positive feedback circuit 230 increases the transition speed when the comparison signal output from the differential input circuit 220 is inverted.

The latch circuit 240 can hold the time code when the comparison signal is inverted. The time code is a digital signal that increases by one count according to a predetermined time period. The time code is generated by a counter circuit (not shown) and input to the latch circuit 240 of each pixel 200. The counter circuit described above starts counting up the time code at the time when the voltage of the reference signal Ref starts to change proportionally.

Depending on the voltage of the pixel signal output from the pixel circuit 210, the inversion timing of the comparison signal output from the positive feedback circuit 230 changes. Since the time code corresponding to the inversion timing of the comparison signal is held in the latch circuit 240, as a result, the voltage of the pixel signal, which is an analog signal, is converted into the time code, which is a digital signal.

The digital signal held in the latch circuit 240 is output to the outside of the pixel 200 (image sensor 100) after being subjected to signal processing and output data format conversion. The above signal processing is, for example, correlated double sampling processing, gain processing, and signal rearrangement processing in a DFE (Digital Front End) or the like. The correlated double sampling process is a process that generates a difference value between a potential including pixel reset noise (N signal level) and a potential corresponding to the number of electrons transferred from the N signal level (N+S signal level).

FIG. 3 is an equivalent circuit diagram of the pixel circuit 210, differential input circuit 220, and positive feedback circuit 230 in one pixel 200 according to the first embodiment of the present invention.

The pixel circuit 210 includes a photodiode 211, a transfer transistor, a floating diffusion 213, a reset transistor 214, and a drain transistor 215. Hereinafter, "photodiode" may be abbreviated as PD, and "floating diffusion" may be abbreviated as FD.

The PD 211 is a photoelectric conversion unit that receives light that has passed through the optical system and accumulates electrons generated according to the amount of incident light.

The transfer transistor 212 is a transfer unit that transfers the electrons accumulated in the PD 211 to the FD 213 by being driven by the signal pulse Tx.

The FD 213 is a charge-voltage converter that holds electrons transferred from the PD 211 and converts them into voltage. Further, the FD 213 also functions as an input node of the differential input circuit 220. In the differential input circuit 220, the voltage of the FD 213 and the reference signal Ref are compared.

The reset transistor 214 is a reset unit that discharges electrons from the FD 213 and resets it to a reference voltage by being driven by a signal pulse Res.

The discharge transistor 215 is a discharge section that discharges the electrons accumulated in the PD 211 to the power supply AVDD by being driven by the signal pulse Ofg.

The differential input circuit 220 includes P-type MOS transistors (hereinafter referred to as PMOS) 221, 222, and 225, and N-type MOS transistors (hereinafter referred to as NMOS) 223, 224, 226, 227, and 228. PMOS221 and 222 constitute a current mirror circuit. NMOS 223 and 224 constitute a differential pair. NMOS 228 functions as a constant current source. The NMOS 226 controls the constant current supply to the differential pair for each row, and the NMOS 227 controls the constant current supply to the differential pair for each column. PMOS 225 outputs a comparison signal.

Of the NMOS 223 and 224 that are a differential pair, the gate of the NMOS 224 is connected to the FD 213, and a reference signal Ref is input to the gate of the NMOS 223. The source of the NMOS 228 is connected to a predetermined voltage (GND). The drain of NMOS 223 is connected to the gates of PMOS 221 and 222 constituting the current mirror circuit and the drain of PMOS 221, and the drain of NMOS 224 is connected to the drain of PMOS 222 and the gate of PMOS 225. The sources of PMOS221, 222 and PMOS225 are connected to power supply AVDD. The NMOSs 226 and 227 are inserted in series between the NMOSs 223 and 224, which are a differential pair, and the NMOS 228, which is a current source, and have a configuration in which constant current supply can be controlled. The gates of the NMOSs 226 and 227 are each connected to the control section 122, and constant current supply to the differential input circuit 220 is controlled by a control signal pulse input from the control section 122. Further, the NMOS 228 as a current source can control the Icm current value by a bias voltage input from the control unit 122. In particular, the image sensor 100 according to this embodiment has two or more modes in which the differential input circuit 220 operates at different Icm current values (drive current values). Details of the control executed by the control unit 122 will be described later.

Positive feedback circuit 230 includes PMOS 231, NMOS 232 to 235, and PMOS 236. A node Vin serving as an input node of the positive feedback circuit 230 is connected to the drain of the PMOS 225. PMOS 231 and NMOS 232 constitute an inverter circuit. The comparison signal output from the differential input circuit 220 can be output from the node Vout, which is the drain of each of the PMOS 231 and the NMOS 232, to the latch circuit 240 at a faster transition speed when inverted.

The NMOS 233 is driven by the signal pulse Ini to reset the voltage of the node Vin to Low at the start of the AD conversion operation. Similarly, the PMOS 236 is driven by the signal pulse Ini to control power supply to the node Vin in the AD conversion operation.

The gate of NMOS 234 is connected to node Vout via NMOS 235. Therefore, when the voltage at the node Vin exceeds the threshold voltage of the inverter circuit (PMOS 231 and NMOS 232) and the voltage at the node Vout becomes Low, the NMOS 234 becomes conductive. At this time, since the low level signal pulse Ini is applied to the PMOS 236, the PMOS 236 is also conductive. Therefore, the positive feedback circuit 230 rapidly charges the node Vin via the PMOS 236 and the NMOS 234, thereby raising its potential to the power supply AVDD at once. As a result, the transition speed when the comparison signal output from the differential input circuit 220 is inverted becomes faster.

However, since the gate of the NMOS 235 is connected to the control section 122, the conduction of the NMOS 235 is controlled by the control signal pulse received from the control section 122. Therefore, to speed up the inversion of the comparison signal described above, the control unit 122 switches between the operating state and the non-operating state. In particular, in the image sensor 100 of this embodiment, when the differential input circuit operates with a relatively small Icm current value, the positive feedback operation is controlled to be effective; Control is performed so that the positive feedback operation is disabled when the input circuit operates.

FIG. 4 is a timing chart illustrating the operation of the AD conversion circuit 201 described above. In the following description, it is assumed that the control signals output from the control unit 122 to the differential input circuit 220 are each High, and that the differential input circuit 220 is supplied with a predetermined Icm current value. Further, it is assumed that the NMOS 235 of the positive feedback circuit 230 is controlled to be in an on (conducting) state.

At time t401, when the signal pulse Res changes from High to Low, the reset transistor 214 becomes off (non-conductive). As a result, the FD 213 that has been reset with the reference voltage AVDD is fixed to a potential (N signal level) that includes reset noise after the reset is released.

At time t402, when the signal pulse Ini changes from High to Low, the reset state of the node Vin is released and the node Vin transitions to a standby state for performing AD conversion of the N signal level. At the same time (t402), the voltage of the reference signal Ref starts to change proportionally over time, and the comparison between the N signal level of the pixel 200 and the voltage of the reference signal Ref starts. During the period in which the voltage of the reference signal Ref is higher than the N signal level of the pixel 200, the PMOS 225 is turned off, so the voltage at the node Vin remains Low after the reset is released, and the voltage output from the node Vout remains High. be.

At time t403, when the voltage of the reference signal Ref falls below the N signal level, the output current of the current source NMOS 228 stops flowing through the NMOS 223, and the gate potentials of the PMOSs 221 and 222 rise, so that the channel resistance of the PMOS 222 increases. Since the current flowing into the PMOS 222 via the NMOS 224 causes a voltage drop and lowers the gate potential of the PMOS 225, the comparison signal output by the PMOS 225 (ie, the voltage at the node Vin) is inverted from Low to High. The positive feedback circuit 230 further outputs an inverted output of the voltage at the node Vin to the latch circuit 240 as Vout via an inverter circuit. The latch circuit 240 holds the time code of the inversion timing when Vout changes from High to Low as the N signal level of the pixel 200. As described above, if the NMOS 235 is controlled to be on, the positive feedback circuit 230 is driven and a positive feedback operation is performed, so that the transition of the comparison signal from High to Low is accelerated. On the other hand, if a sufficiently large current is set as the Icm current value, the positive feedback operation is disabled by controlling the NMOS 235 to an off state.

At time t404, the voltage of the reference signal Ref stops changing, and AD conversion of the N signal level of the pixel 200 is completed.

At time t405, when the signal pulse Ini changes from Low to High, in the positive feedback circuit 230, the NMOS 233 becomes conductive and the PMOS 236 turns off, so that the node Vin is reset to Low (GND). As a result, the comparison signal Vout also transitions from Low to High.

When the signal pulse Tx changes to High from time t406 to time t407, the transfer transistor 212 is turned on, so that the electrons accumulated in the PD 211 are transferred to the FD 213. In response, the potential of the FD 213 decreases from the N signal level to the potential (N+S signal level) corresponding to the number of transferred electrons.

The period from time t408 to time t411 is an AD conversion period of the N+S signal level, and is controlled in the same manner as the period from time t402 to time t405, which is the AD conversion period of the N signal level described above. More details are as follows.

At time t408, when the signal pulse Ini changes from High to Low, the reset state of the node Vin is released and a comparison between the N+S signal level of the pixel 200 and the voltage of the reference signal Ref starts.

At time t409, when the voltage of the reference signal Ref falls below the N+S signal level, the potential of the gate of the PMOS 225 decreases as described above, and the comparison signal output by the PMOS 225 (that is, the voltage of the node Vin) is inverted from Low to High. do. The positive feedback circuit 230 further outputs an inverted output of the voltage at the node Vin to the latch circuit 240 as Vout via an inverter circuit. The latch circuit 240 holds the time code of the inversion timing when Vout changes from High to Low as the N+S signal level of the pixel. At this time, as described above, the positive feedback circuit 230 is driven, so that the comparison signal changes from High to Low at high speed.

At time t410, the voltage of the reference signal Ref stops changing, and AD conversion of the N+S signal level of the pixel 200 ends.

At time t411, when the signal pulse Ini changes from Low to High, in the positive feedback circuit 230, the NMOS 233 becomes conductive and the PMOS 236 turns off, so that the node Vin is reset to Low (GND). As a result, the comparison signal Vout also transitions from Low to High.

At time t412, when the signal pulse Res changes from Low to High, the reset transistor 214 turns on, so the FD 213 is reset to the reference potential AVDD.

FIG. 5 is a configuration diagram of the control section 122, the differential input circuit 220, and the positive feedback circuit 230 according to the first embodiment of the present invention. In FIG. 5, for simplicity of illustration, a portion of the differential input circuit 220 and positive feedback circuit 230 of the pixel 200 is omitted. Although the pixels 200 arranged in 3 rows and 2 columns are shown in FIG. 5, more pixels 200 are actually arranged. Generally speaking, a control signal generated by the control section 122 is input to the differential input circuit 220 and the positive feedback circuit 230.

The control section 122 includes a row selection section 510, a column selection section 520, a current setting section 530, a constant current source 531, an NMOS 532, and a positive feedback operation setting section 540.

The row selection section 510 controls the supply of a constant current of the Icm current value to the differential input circuit 220 on a row-by-row basis according to the drive mode set by the drive mode setting section 1170. That is, the row selection unit 510 executes on/off control of the NMOS 226 in each row via the signal lines 301A, 301B, 301C, . In the rows where the NMOS 226 is in the on state, a constant current is supplied and the differential input circuit 220 operates, while in the rows where the NMOS 226 is in the off state, the supply of constant current is stopped and the differential input circuit 220 does not operate.

Similarly, the column selection section 520 controls the supply of a constant current of the Icm current value to the differential input circuit 220 on a column-by-column basis according to the drive mode set by the drive mode setting section 1170. That is, the row selection unit 510 executes on/off control of the NMOS 227 in each column via the signal lines 302a, 302b, . In the column where the NMOS 227 is in the on state, a constant current is supplied and the differential input circuit 220 operates, while in the column where the NMOS 227 is in the off state, the supply of constant current is stopped and the differential input circuit 220 does not operate.

Therefore, in the image sensor 100 according to the present embodiment, only the differential input circuit 220 of the pixel 200 corresponding to the row and column selected and controlled to be turned on by the row selection section 510 and the column selection section 520 operates. Selection of the differential input circuit 220 according to the drive mode will be described later in the explanation from FIG. 6 onwards.

The current setting unit 530 cooperates with the constant current source 531 and the NMOS 532 to control the Icm current value of the constant current supplied to the differential input circuit 220 over all pixels 200. Since the NMOS 532 constitutes a current mirror circuit together with the NMOS 228 which is a constant current source of the differential input circuit 220 of each pixel 200, a current having the same current value as the current supplied by the constant current source 531 and flowing through the NMOS 532 is applied to each differential input circuit 220. It is supplied to input circuit 220.

Therefore, the current setting unit 530 switches the Icm current value of the constant current supplied to the differential input circuit 220 to all pixels 200 uniformly by setting the current value of the constant current source 531 according to the drive mode. The current value switched by the current setting unit 530 and supplied to the differential input circuit 220 is a value according to the drive mode, and may be a relatively small value of about 0.1 μA or a relatively large value of about 5 μA, for example. It can take a value. That is, the drive current value input to the differential input circuit 220 of the AD conversion circuit 201 takes a value selected from one of a plurality of candidate current values. Control of the drive current value to the differential input circuit 220 according to the drive mode will be described later in the explanation from FIG. 6 onwards.

The positive feedback operation setting section 540 controls the positive feedback circuit 230 to enable/disable the positive feedback operation. When the current setting unit 530 is operated with a relatively small current value, the positive feedback operation is uniformly enabled for all pixels 200 in order to compensate for the speed at which the comparison signal is inverted. On the other hand, when the current setting unit 530 is operated with a relatively large current value, the positive feedback operation is uniformly disabled for all pixels 200.

A control method by the control unit 122 for each drive mode will be described with reference to FIGS. 6 to 10. Typical drive modes are listed below as global shutter drive mode, column parallel drive mode, thinned out global shutter drive mode (hereinafter referred to as thinned out GS drive mode), area parallel drive mode, and autofocus drive mode (hereinafter referred to as AF drive mode). exemplify.

FIG. 6 is a schematic diagram showing how the image sensor 100 operates in the global shutter drive mode. The global shutter drive mode is a mode in which all pixels 200 are driven simultaneously to accumulate and read out signal charges. The global shutter drive mode is suitable for photographing a moving object because the exposure time is the same for each pixel 200 within the imaging plane. In the global shutter drive mode, all pixels 200 operate uniformly, and power corresponding to the drive current of differential input circuit 220 is consumed in all pixels 200, resulting in large power consumption. Therefore, in the global shutter drive mode, the Icm current value is set to 0.1 μA, the NMOS 226 and NMOS 227 of all pixels 200 are set to the on state, positive feedback operation is enabled, and the image sensor 100 is driven.

FIG. 7 is a schematic diagram showing how the image sensor 100 operates in column parallel drive mode. The column parallel drive mode is a mode in which the pixels 200 are sequentially driven row by row to accumulate and read signal charges. The number of pixels 200 driven simultaneously, that is, the number of differential input circuits 220, is equal to the number of columns of pixels 200. Therefore, since the power consumption is lower than in the global shutter drive mode, the Icm current value is set to a relatively large value of 5 μA, the positive feedback operation is disabled, and the image sensor 100 is driven. In the column parallel drive mode, variations in the timing at which the comparison signals from the differential input circuit 220 are inverted are reduced, so noise can be suppressed compared to the global shutter drive mode.

FIGS. 7A and 7B show how the pixels 200 are sequentially scanned row by row. First, as shown in FIG. 7A, the row selection unit 510 selects the first row of the pixel array to turn on the NMOS 226 in the first row, and also turns on the NMOS 226 in the other rows. Set to off state. The column selection unit 520 sets the NMOSs 227 in all columns to the on state by selecting all columns in the pixel array. As a result, a constant current having a current value of Icm is supplied to the differential input circuit 220 of the pixel 200 indicated by diagonal lines in FIG. 7A, and the pixel 200 is driven as described above with reference to FIG. Processing then switches to the next line.

Next, as shown in FIG. 7B, the row selection unit 510 selects the second row of the pixel array to turn on the NMOS 226 in the second row, and turns on the NMOS 226 in the other rows. Set to off state. The column selection unit 520 maintains the NMOS 227 in all columns of the pixel array in an on state. Thereafter, the pixels 200 are similarly driven row by row.

As described above, the row selection unit 510 reads out signals from all pixels 200 in column parallel manner by sequentially and repeatedly selecting each row of the pixel array. Note that the row selection unit 510 may sequentially select and scan multiple rows of pixels 200 instead of reading out the pixels 200 row by row as described above.

Other drive modes will be described below with reference to FIGS. 8 to 10. In the following drive mode, similarly to the column parallel drive mode in FIG. 7, the Icm current value is set to a relatively large value of 5 μA, the positive feedback operation is disabled, and the image sensor 100 is driven. On the other hand, in the following drive mode, the method of selecting pixels 200 by the row selection section 510 and the column selection section 520 is different from the column parallel drive mode of FIG.

FIG. 8 is a schematic diagram showing how the image sensor 100 operates in the thinned-out GS drive mode. In the thinning GS drive mode, the row selection section 510 selects pixels 200 in one row every two rows, and the column selection section 520 selects pixels 200 in one column every two columns, so that four pixels (two rows In this mode, one pixel per two columns is driven at a time to accumulate and read out signal charges. Like the global shutter drive mode, the thinned-out GS drive mode is suitable for photographing a moving object because the exposure time is the same for each pixel 200 within the imaging plane. Furthermore, in the thinned-out GS drive mode, imaging is performed by some of the pixels 200, so it is suitable for cases where high-resolution pixel signals are not required. Note that the thinning rate is not limited to 1/4 (1 pixel for every 4 pixels), and other thinning rate (for example, 1/9 (1 pixel for every 9 pixels)) may be adopted.

FIG. 9 is a schematic diagram showing how the image sensor 100 operates in the region parallel drive mode. In the region parallel drive mode, pixels 200 at the same relative position within a pixel group 901 including a plurality of pixels 200 configured by dividing a pixel array into regions are driven in parallel to accumulate and read out signal charges. mode. In the example of FIG. 9, a region of 3 horizontal pixels x 2 vertical pixels (6 pixels) indicated by a rectangular dotted line constitutes one pixel group 901. A plurality of pixel groups 901 are arranged in a matrix. Note that the number of pixels 200 in the row direction and column direction in the pixel group 901 is not limited to this example, and any number of pixels may be adopted. The column parallel drive mode in FIG. 7 can be considered to be an area parallel drive mode in which all pixels in the horizontal direction (row direction) x one pixel in the vertical direction (column direction) are set as one pixel group.

FIGS. 9A and 9B show how pixels 200 within a pixel group 901 (within a region) are sequentially selected. First, as shown in FIG. 9A, the pixel 200 at the first relative position (upper left) in each pixel group 901 is selected. More specifically, the row selection unit 510 selects a row corresponding to the first row of the pixel group 901 (first row, third row, fifth row, etc.) to turn on the NMOS 226 of the corresponding row. At the same time, the NMOSs 226 in other rows are set to the off state. The column selection unit 520 selects a column corresponding to the first column (first column, fourth column, seventh column, etc.) in the pixel group 901 and sets the NMOS 227 of the corresponding column to the on state. , sets the NMOS 227 in other columns to the off state. As a result, a constant current having a current value of Icm is supplied to the differential input circuit 220 of the pixel 200 indicated by diagonal lines in FIG. 9A, and the pixel 200 is driven as described above with reference to FIG. Processing then switches to the next pixel 200.

Next, as shown in FIG. 9(b), the pixel 200 at the second relative position (upper center) within each pixel group 901 is selected. More specifically, the row selection unit 510 maintains the ON state of the NMOS 226 in the rows corresponding to the first row of the pixel group 901 (first row, third row, fifth row, . . . ). The column selection unit 520 selects a column corresponding to the second column of the pixel group 901 (second column, fifth column, eighth column, etc.) and sets the NMOS 227 of the corresponding column to the on state, NMOS 227 in other columns is set to off state.

As described above, the row selection unit 510 and the column selection unit 520 sequentially and repeatedly select the pixels 200 in the pixel group 901 for each relative position, thereby reading out signals from all pixels 200 in a region-parallel manner.

FIG. 10 is a schematic diagram showing how the image sensor 100 operates in the AF drive mode. The AF drive mode is a mode in which the pixels 200 are sequentially driven row by row at a specific period to accumulate and read signal charges. The method of driving the image sensor 100 as described above is also referred to as "line thinning readout". In particular, the AF drive mode of this example is a drive method that reads out only the signals of the pixels 200 in a specific row used in so-called imaging plane phase difference AF, and is different from the column parallel drive mode that simply reads out each row sequentially. . Image plane phase-difference AF uses photodiodes to receive each of the light beams that have passed through different exit pupils of the photographic lens, and detects the relative shift of the signals output according to the amount of received light, thereby focusing the photographic lens. This is a focusing method that directly determines the direction and amount of deviation. Imaging plane phase difference AF can perform focus detection faster than contrast AF and the like. There are two methods for acquiring signals of light fluxes that have passed through different exit pupils of a photographic lens: one is to divide the PD of a pixel with one microlens into two, and the other is to divide the PD of a pixel into two parts so that it receives only the light flux from a specific exit pupil area. There is a method of forming a light-shielding curtain on the surface. The AF drive mode of this example can be applied to any of the above methods.

FIGS. 10A and 10B show how pixels 200 in rows from which phase difference signals can be obtained are sequentially selected. First, as shown in FIG. 10A, the row selection unit 510 selects the third row from which a phase difference signal can be obtained, thereby setting the NMOS 226 in the third row to the on state, and The row NMOS 226 is set to the off state. The column selection unit 520 sets the NMOSs 227 in all columns to the on state by selecting all columns in the pixel array. As a result, a constant current having a current value of Icm is supplied to the differential input circuit 220 of the pixel 200 indicated by diagonal lines in FIG. 10A, and the pixel 200 is driven as described above with reference to FIG. Processing then switches to the next line.

Next, as shown in FIG. 10(b), the row selection unit 510 selects the sixth row from which the phase difference signal can be obtained, thereby setting the NMOS 226 in the sixth row to the on state, and setting the NMOS 226 in the sixth row to the on state. The row NMOS 226 is set to the off state. The column selection unit 520 maintains the NMOS 227 in all columns of the pixel array in an on state.

As described above, the row selection unit 510 reads out signals used in the imaging plane phase difference AF by sequentially and repeatedly selecting specific rows of the pixel array necessary for the AF operation. In the AF operation, there are cases in which it is sufficient to acquire a signal for the imaging plane phase difference AF only at an arbitrary distance measurement point selected by the user or in a specific area selected by subject detection. In the AF drive mode, the signals necessary for the AF operation can be read out at high speed without reading out unnecessary signals from the pixels 200 in the above cases, so the AF speed can be increased.

Among the drive modes described above, in the global shutter drive mode shown in FIG. 6, all pixels 200 operate uniformly. Therefore, the Icm current value is set to a relatively small 0.1 μA, the NMOS 226 and NMOS 227 of all pixels 200 are set to the on state, and the positive feedback operation is enabled to drive the image sensor 100. On the other hand, in other drive modes shown in FIGS. 7 to 10, the number of pixels 200 that are simultaneously driven in parallel is relatively small, so the Icm current value is set to a relatively large value of 5 μA, and positive feedback operation is performed. The image sensor 100 is driven in the disabled state. Control in other drive modes reduces variations in the timing at which the comparison signal from the differential input circuit 220 is inverted, so noise can be suppressed compared to the global shutter drive mode. In the above configuration, the Icm current value is switched between 0.1 μA and 5 μA for driving, but the Icm current value is not limited to the above set value. The Icm current value (relatively large value and relatively small value) can be arbitrarily changed depending on various factors such as the number of pixels 200 driven simultaneously, the current supply capacity of the power supply IC, and the purpose of use. .

According to the above configuration, the Icm current value for driving each of the AD conversion circuits 201 is set according to the drive mode of the image sensor 100. can be obtained. More specifically, according to the above configuration, an image having appropriate image quality depending on the drive mode can be obtained.

<Second embodiment>
An imaging device 1100 according to a second embodiment of the present invention will be described below with reference to FIGS. 11 and 12. In each of the embodiments illustrated below, the reference numerals referred to in the above description will be used for elements whose operations and functions are equivalent to those of the first embodiment, and the description of each will be omitted as appropriate.

FIG. 11 is a block diagram showing the overall configuration of an imaging device 1100 according to the second embodiment of the present invention. The imaging device 1100 includes the imaging element 100 according to the first embodiment, an optical system 1110, a signal processing section 1120, a storage section 1130, a display section 1140, a recording section 1150, an input interface 1160, a drive mode setting section 1170, and a mechanical shutter 1180. has.

The optical system 1110 is an imaging lens including optical elements such as a focus lens, a zoom lens, and an aperture.

As described above, the image sensor 100 converts an analog signal obtained by photoelectrically converting a subject image formed by the optical system 1110 into a digital signal and outputs the digital signal.

The signal processing unit 1120 performs image processing such as correction of defective pixels, noise reduction, color conversion, white balance correction, and gamma correction, resolution conversion processing, and image compression processing on the image signal output from the image sensor 100. It functions as an image processing unit.

The storage unit 1130 is a memory for arithmetic processing used by the signal processing unit 1120, and can function as a buffer memory when continuous shooting is performed in the imaging apparatus 1100.

The display unit 1140 is a display that displays information such as the image signal (image data) output from the signal processing unit 1120.

The recording unit 1150 is a recording medium that records information such as an image signal (image data) output from the signal processing unit 1120, and is, for example, a memory card or a hard disk.

Input interface 1160 electrically receives input from operating members such as buttons, switches, and electronic dials. In this embodiment, in particular, an operation by the user to select a shooting mode is accepted.

The drive mode setting unit 1170 selects a drive mode to be applied to the image sensor 100 according to the shooting mode input from the input interface 1160, and sends a signal (drive mode information) indicating the drive mode to be applied to the control unit 122. and output to the signal processing section 1120. As described in the first embodiment, in the image sensor 100 according to the embodiment of the present invention, the control unit 122 controls the operation of the pixel 200 based on drive mode information. Further, the signal processing unit 1120 selects and executes a processing method (image processing method) for the image signal from the image sensor 100 based on the drive mode information. Details will be described later with reference to FIG.

The mechanical shutter 1180 is a shutter mechanism that mechanically controls an exposure state in which the light flux from the optical system 1110 is made to enter the image sensor 100 and a light shielding state in which the light flux is blocked. The duration of the exposure state can be set in various ways. In the shooting mode for still images that do not need to be read out at a high frame rate, such as moving images, the exposure time of the image sensor 100 is controlled by the mechanical shutter 1180, and after the image sensor 100 is in a light-shielded state, the pixel signals are sequentially AD converted. It can be read out.

FIG. 12 is an explanatory diagram of a drive control method in the imaging device 1100 according to the second embodiment of the present invention. FIG. 12 shows the correspondence between the user-selectable shooting modes, the drive mode, the Icm current value, the operation of the differential input circuit 220, and the signal processing method (that is, the correspondence between the shooting modes and control parameters). It shows. Examples of shooting modes include a high-resolution video mode, a high frame rate (HFR) video mode, and a still image mode.

When the shooting mode input from the input interface 1160 is the high-resolution video mode, the drive mode setting unit 1170 controls the control unit 122 and the signal processing unit 1120 to drive the image sensor 100 in the global shutter drive mode of FIG. control. By selecting the global shutter drive mode, a high-resolution image is obtained and the occurrence of rolling distortion in a moving subject is suppressed. The control unit 122 uniformly sets the Icm current value to 0.1 μA for all pixels 200 and sets the positive feedback circuit 230 to operate, thereby increasing the transition speed at which the comparison signal is inverted.

In the video mode, the signal processing unit 1120 needs to convert the plurality of acquired images into a video format. For example, a full HD video requires processing to bin the image resolution to 1920x1080, and a 4K video requires processing to bin the image resolution to 3840x2160. In addition, in the video mode, the signal processing unit 1120 performs compression processing to reduce the size of a video file having continuous still image frames. In the above compression processing, for example, averaging processing of similar data within the same frame (in the spatial direction), processing of replacing data differences between multiple frames (in the temporal direction), etc. are executed. As a result of the above processing, noise is less noticeable in the high-resolution moving image mode than in still images, so even if the global shutter drive mode of FIG. 6, which has relatively large noise, is used, the influence of noise on moving images is small.

When the shooting mode input from the input interface 1160 is the HFR video mode, the drive mode setting unit 1170 controls the control unit 122 and the signal processing unit 1120 to drive the image sensor 100 in the thinned-out GS drive mode in FIG. do. By selecting the thinning GS drive mode, the resolution of the moving image is 1/4 compared to the global shutter drive mode, but it is possible to read out signals at a high frame rate, and it also prevents rolling distortion from occurring in moving subjects. is suppressed. In the thinned-out GS drive mode, the number of pixels 200 that are simultaneously driven in parallel is smaller than in the global shutter drive mode, so the control unit 122 sets the Icm current value of the pixels 200 to be driven to 5 μA, and also Set it so that it doesn't work. As a result, noise generation is suppressed in the HFR video mode compared to the global shutter drive mode.

When the shooting mode input from the input interface 1160 is the still image mode, the drive mode setting unit 1170 controls the control unit 122 and the signal processing unit 1120 to drive the image sensor 100 in the column parallel drive mode of FIG. do. This is because in still image mode, there is no need to read out image signals at a high frame rate like moving images. Similarly to the HFR video mode, the control unit 122 sets the Icm current value of the pixel 200 to be driven to 5 μA, and also sets the positive feedback circuit 230 not to operate. As a result, noise generation is suppressed in the still image mode compared to the global shutter drive mode.

Note that the above control parameters are just examples and can be set arbitrarily. That is, the image sensor 100 according to the present embodiment can be arbitrarily set according to the performance to be prioritized in the image capturing apparatus 1100. For example, in the HFR video mode, if priority should be given to reducing power consumption, when driving the image sensor 100 in the low resolution thinning GS drive mode, the Icm current value is set to 0.1 μA, and the positive feedback circuit 230 may be operated.

According to the above configuration, the drive mode setting unit 1170 of the imaging device 1100 selects the drive mode of the image sensor 100 according to the imaging mode of the imaging device 1100, so that the imaging Driving of the element 100 is controlled. For example, depending on the photography mode, photography using the global shutter drive mode and photography using the low noise drive mode (for example, thinned-out GS drive mode) are switched. As a result, it is possible to obtain images (moving images and still images) with appropriate image quality depending on the purpose of photography.

<Other embodiments>
Although preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and changes can be made within the scope of the gist thereof.

100 Image sensor 122 Control unit
200 pixels (unit pixel)
201 AD conversion circuit 210 Pixel circuit 220 Differential input circuit 230 Positive feedback circuit 901 Pixel group 1100 Imaging device 1170 Drive mode setting section

Claims (8)

a pixel circuit that outputs a pixel signal corresponding to the amount of incident light;
An image sensor in which a plurality of pixels are two-dimensionally arranged, each including an AD conversion circuit that AD converts the pixel signal,
An image pickup device comprising: a control unit that controls to switch a drive current value for driving each of the plurality of AD conversion circuits based on the number of the AD conversion circuits that operate in parallel . Each of the plurality of AD conversion circuits,
comprising a positive feedback circuit that speeds up the transition speed when a comparison signal indicating a result of comparing the voltage of the pixel signal and the voltage of the reference signal is inverted;
The control unit includes:
2. The image sensor according to claim 1, wherein the drive current value for driving the AD conversion circuit is switched, and a positive feedback operation by the positive feedback circuit is switched between a valid state and a disabled state. The control unit, for each of the plurality of AD conversion circuits,
controlling the positive feedback operation to be in a valid state when the drive current value of the AD conversion circuit is switched to a first current value;
According to claim 2, the positive feedback operation is controlled to be in an invalid state when the drive current value of the AD conversion circuit is switched to a second current value higher than the first current value. The image sensor described. The control unit includes:
The image sensor according to any one of claims 1 to 3 , wherein a plurality of the AD conversion circuits are sequentially selected and the selected AD conversion circuits are operated in parallel . The plurality of pixels each including the AD conversion circuit are arranged in a matrix,
The control unit includes:
5. The image sensor according to claim 4 , wherein the plurality of AD conversion circuits are sequentially selected row by row, and the AD conversion circuits in the selected rows are operated in parallel . The plurality of pixels each including the AD conversion circuit are divided into a plurality of pixel groups,
The control unit includes:
5. The plurality of AD conversion circuits are sequentially selected for each relative position within the pixel group, and the AD conversion circuits located at the selected relative positions are operated in parallel. Image sensor. An image sensor according to any one of claims 1 to 6 ,
An imaging device comprising: a drive mode setting unit that selects a drive mode to be applied to the image sensor according to a shooting mode,
The control unit of the image sensor includes:
An imaging device, characterized in that the operation of the plurality of pixels is controlled according to the drive mode selected by the drive mode setting section. a pixel circuit that outputs a pixel signal corresponding to the amount of incident light;
A method for controlling an image sensor in which a plurality of pixels are two-dimensionally arranged, each including an AD conversion circuit that AD converts the pixel signal,
A control method comprising controlling to switch a drive current value for driving each of the plurality of AD conversion circuits based on the number of the AD conversion circuits operating in parallel .

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