JP7368696B2 - light emitting device - Google Patents

Description

The present invention relates to a light emitting device.

2. Description of the Related Art Light-emitting devices using semiconductor light-emitting elements such as light-emitting diodes are widely used because they are small and provide high luminous efficiency. Mounting methods for semiconductor light emitting devices can be roughly divided into two types: face-up type, in which the surface on which pad electrodes are provided on the semiconductor light emitting device is positioned on the side opposite to the mounting board when mounted on a mounting board; There are two types: a face-down type (flip-chip type), which is placed on the opposite side.

In the face-up mounting method, a semiconductor light emitting element is mounted on a lead or the like, and the semiconductor light emitting element and the lead are connected using a bonding wire or the like. Therefore, when mounted on a mounting board and viewed in plan from a direction perpendicular to the surface of the board, a part of the bonding wire needs to be located outside the semiconductor light emitting element.

On the other hand, in the face-down mounting method, when the pad electrodes provided on the surface of the semiconductor light emitting device and the wiring provided on the mounting board are viewed from a plane perpendicular to the surface of the mounting board, the semiconductor light emitting device is It is possible to electrically connect by connecting means such as bumps or metal pillars located within the size range. According to semiconductor light emitting devices mounted in a face-down type, CSP (Chip Size Package) is used, which reduces the size of the light emitting device (particularly the size when viewed from above in a direction perpendicular to the mounting board) to a level close to the size of the semiconductor light emitting device. or Chip Scale Package).

When mounting a semiconductor light emitting device face-down on a mounting board, a reflow method using solder or the like may be used. At this time, if excessive solder reaches the semiconductor light emitting device, it may affect the reliability of the semiconductor light emitting device.

Patent Document 1 discloses a structure in which the side surface of a metal pillar connected to a pad electrode of a light emitting element is covered with a resin.

Japanese Patent Application Publication No. 2011-187679

Exemplary embodiments of the present disclosure provide a light emitting device having a structure that can suppress adhesive members such as melted solder from creeping up to semiconductor light emitting elements when mounted face-down.

A light emitting device according to an exemplary embodiment of the present disclosure includes a semiconductor stacked structure including an active layer, a p-side semiconductor layer and an n-side semiconductor layer disposed with the active layer in between, and a semiconductor stacked structure including a top surface of the semiconductor stacked structure. a p-electrode structure arranged and electrically connected to the p-side semiconductor layer; an n-electrode structure electrically connected to the n-side semiconductor layer; a mounting board; the p-electrode structure and the n-electrode structure. a bonding member located between an upper surface and the mounting board, at least one of the p-electrode structure and the n-electrode structure includes a first conductive layer electrically connected to the semiconductor laminated structure; a first metal layer disposed on the upper surface of the conductive layer; and a second conductive layer disposed on the upper surface of the first metal layer, and the wettability of the first metal layer with respect to the bonding member is determined by the second conductive layer. The side surface of the first metal layer is smaller than the wettability of the conductive layer with respect to the bonding member, and is exposed from the first conductive layer and the second conductive layer.

According to the exemplary embodiments of the present disclosure, a light emitting device can be obtained that has a structure that can suppress adhesive members such as solder melted during mounting from creeping up to the semiconductor light emitting element.

FIG. 1 is a cross-sectional view showing a first embodiment of a light emitting device of the present disclosure. FIG. 2A is a cross-sectional view of a light emitting element used in the light emitting device of the first embodiment. FIG. 2B is a plan view of a light emitting element used in the light emitting device of the first embodiment. FIG. 2C is a plan view of the semiconductor structure of the light emitting device shown in FIG. 2A. FIG. 2D is a plan view for explaining the structure of the light reflecting electrode of the light emitting element shown in FIG. 2A. FIG. 2E is a plan view for explaining the structure of the first insulating layer of the light emitting device shown in FIG. 2A. FIG. 2F is a plan view for explaining the structure of the second insulating layer of the light emitting element shown in FIG. 2A. FIG. 2G is a plan view for explaining the structure of the n-side electrode and the p-side electrode of the light emitting element shown in FIG. 2A. FIG. 3 is a flowchart showing the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4A is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4B is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4C is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4D is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4E is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4F is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4G is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4H is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4I is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4J is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4K is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 4L is a process cross-sectional view in the first embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 5A is a cross-sectional view showing a second embodiment of the light emitting device of the present disclosure. FIG. 5B is a cross-sectional view of a light emitting element used in the light emitting device of the second embodiment. FIG. 5C is a plan view of a light emitting element used in the light emitting device of the second embodiment. FIG. 5D is a cross-sectional view of another type of light emitting element used in the light emitting device of the second embodiment. FIG. 5E is a process cross-sectional view in the second embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 5F is a process cross-sectional view in the second embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 5G is a process cross-sectional view in the second embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 5H is a process cross-sectional view in the second embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 6A is a cross-sectional view showing a third embodiment of the light emitting device of the present disclosure. FIG. 6B is a cross-sectional view of a light emitting element used in the light emitting device of the third embodiment. FIG. 7 is a flowchart showing a third embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 8A is a process cross-sectional view in a third embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 8B is a process cross-sectional view in the third embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 9A is a cross-sectional view showing a fourth embodiment of the light emitting device of the present disclosure. FIG. 9B is a cross-sectional view of a light emitting element used in the light emitting device of the third embodiment. FIG. 10 is a flowchart showing a third embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 11A is a process cross-sectional view in a third embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 11B is a process cross-sectional view in the third embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 11C is a process cross-sectional view in the third embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 11D is a process cross-sectional view in the third embodiment of the method for manufacturing a light emitting device of the present disclosure. FIG. 11E is a process cross-sectional view in the third embodiment of the method for manufacturing a light emitting device of the present disclosure.

Embodiments of a light emitting device and a method for manufacturing the same according to the present invention will be described below. Note that the drawings referred to in the following description schematically illustrate the present invention, so the scale, spacing, positional relationship, etc. of each member may be exaggerated, or illustrations of some members may be omitted. There are cases. Furthermore, the scale and spacing of each member may not match between the perspective view, plan view, and cross-sectional view. In addition, in the following description, the same names and symbols basically indicate the same or homogeneous members, and detailed descriptions will be omitted as appropriate.

Further, in the light emitting device according to each embodiment of the present invention, "top", "bottom", "left", "right", etc. are interchanged depending on the situation. In this specification, "upper", "lower", etc. indicate relative positions between constituent elements in the drawings referred to for explanation, and do not indicate absolute positions unless otherwise specified. Not what I intended.

(First embodiment)
1. Structure of Light-Emitting Device 201 A first embodiment of the light-emitting device of the present disclosure will be described. FIG. 1 is a cross-sectional view of a light-emitting device 201 illustrating an example of a first embodiment of the light-emitting device of the present disclosure. The light emitting device 201 includes a light emitting element 101, a bonding member 140, and a mounting board 150, and the light emitting element 101 is mounted on the mounting board 150 by the bonding member 140. The light emitting element 101 has a light extraction surface 101a from which light is emitted, and an electrode surface 101b located on the opposite side of the light extraction surface 101a, and the electrode surface 101b faces the mounting board 150.

FIG. 2A is a cross-sectional view of the light emitting element 101. In this embodiment, the light emitting element 101 includes a substrate 10, a semiconductor stacked structure 20, an n-electrode structure 40, and a p-electrode structure 50. The light emitting element 101 further includes a light reflecting electrode 31, a first insulating layer 32, and a second insulating layer 33. In a semiconductor device, a semiconductor structure is generally formed on a substrate, and various electrodes are formed on the semiconductor structure. For this reason, the structure is often explained with the substrate placed at the bottom of the drawing. In this specification, the "upper" and "lower" structures of the light emitting element 101 will be described with the substrate 10 disposed on the lower side as shown in FIG. 2A. However, "upper", "lower", "right", and "left" only mean relative positional relationships in the light emitting element 101 shown in FIG. 2A.

In the light emitting element 101, the substrate 10 is located on the light extraction surface 101a side, and the n-electrode structure 40 and the p-electrode structure 50 are located on the electrode surface 101b side. FIG. 2B is a plan view (top view) of the light emitting element 101 viewed from the top side. The light emitting element 101 has a substantially square shape in plan view. FIG. 2A shows a cross section taken along line 2A-2A in FIG. 2B. In the plan view shown below, for ease of understanding, each component is shown with the same hatching as the cross-sectional hatching shown in FIG. 2A.

Each component of the light emitting element 101 will be described in detail below.

[Substrate 10]
The substrate 10 is a substrate for epitaxially growing the semiconductor stacked structure 20, and supports the semiconductor stacked structure 20. The substrate 10 is transparent to the wavelength of light emitted by the semiconductor stacked structure 20 . As the substrate 10, for example, when the semiconductor stacked structure 20 is made of a nitride semiconductor, a sapphire substrate can be used. The substrate 10 may be removed after the semiconductor stacked structure 20 is formed. Further, the substrate 10 may function only to support the semiconductor stacked structure 20. In this case, the semiconductor stacked structure 20 is formed on another support substrate, and the semiconductor stacked structure 20 is peeled off from the other support substrate and bonded to the substrate 10.

[Semiconductor stacked structure 20]
The semiconductor stacked structure 20 is supported on the substrate 10 and includes an n-side semiconductor layer 21, an active layer 22, and a p-side semiconductor layer 23. In the semiconductor stacked structure 20, the active layer 22 is sandwiched between an n-side semiconductor layer 21 and a p-side semiconductor layer 23. In the semiconductor stacked structure 20, an n-side semiconductor layer 21, an active layer 22, and a p-side semiconductor layer 23 are formed in this order from the substrate 10 side, and the n-side semiconductor layer 21 is in contact with the substrate 10.

FIG. 2C is a plan view (top view) of the semiconductor stacked structure 20 seen from the top side. The semiconductor stacked structure 20 has an upper surface 20a and a lower surface 20b, and the upper surface 20a has a stepped portion 20r and a plurality of holes 20h, as shown in FIG. 2C. The step portion 20r is located along the outer periphery of the upper surface 20a, and the p-side semiconductor layer 23 and the active layer 22 are not provided in the step portion 20r, and the n-side semiconductor layer 21 is exposed at the bottom surface. .

The plurality of holes 20h are distributed and arranged on the upper surface 20a. For example, in the example shown in FIG. 2C, the semiconductor stacked structure 20 has 12 holes 20h arranged in 4 rows and 3 columns. Each hole 20h is a non-through hole, and the p-side semiconductor layer 23 and the active layer 22 are not provided in the hole 20h. The n-side semiconductor layer 21 is exposed at the bottom of the hole 20h. A part of the n-electrode structure 40 is arranged in the step part 20r and the hole 20h, as described later, and the n-electrode structure 40 and the n-side semiconductor layer 21 are electrically connected at the bottom of the step part 20r and the bottom of the hole 20h. connected to.

The semiconductor stacked structure 20 is made of, for example, a nitride semiconductor such as In _x Al _Y Ga _1-X-Y N (0≦X, 0≦Y, X+Y<1). The n-side semiconductor layer 21, the active layer 22, and the p-side semiconductor layer 23 may each have a single layer structure, or a stacked structure or superlattice structure including a plurality of semiconductor layers having different compositions and/or film thicknesses. etc. may be provided. In particular, it is preferable that the active layer 22 has a single quantum well or multiple quantum well structure in which thin films that produce quantum effects are laminated. Further, the semiconductor stacked structure 20 may include other layers such as a buffer layer in addition to the n-side semiconductor layer 21, the active layer 22, and the p-side semiconductor layer 23.

[Light reflective electrode 31]
The light reflecting electrode 31 is provided on the upper surface of the p-side semiconductor layer 23. FIG. 2D is a plan view for explaining the structure of the light reflecting electrode 31. Of the light emitted from the active layer 22, the light reflecting electrode 31 reflects the light directed toward the electrode surface 101b and directs it toward the light extraction surface 101a. Further, the light reflecting electrode 31 also functions as a member that uniformly diffuses a current supplied from a p-electrode structure 50, which will be described later, to the p-side semiconductor layer 23. The light reflecting electrode 31 is arranged to cover substantially the entire lower surface of the p-side semiconductor layer 23 that constitutes the upper surface 20 a of the semiconductor stacked structure 20 . The light reflecting electrode 31 is not arranged in the area where the stepped portion 20r and the hole 20h are provided. Further, the light reflecting electrode 31 has a hole 31h located at a location corresponding to the hole 20h and larger than the hole 20h.

The light reflective electrode 31 can be formed of a metal material having good conductivity and good light reflectivity. For example, as the light-reflecting electrode 31, a film formed of a metal material having good reflectivity in the visible light region can be used. Specifically, for the light reflecting electrode 31, a metal film made of Ag or Al, or a metal film made of an alloy containing these metals as main components can be suitably used. The light reflecting electrode 31 may include one or more of these metal films.

[First insulating layer 32, second insulating layer 33]
The first insulating layer 32 is a barrier layer for preventing migration of the metal material forming the light reflecting electrode 31. In particular, when Ag or an alloy containing Ag as a main component, which tends to cause migration, is used as the light-reflecting electrode 31, it is preferable to provide the first insulating layer 32. The first insulating layer 32 preferably covers a portion of the light reflective electrode 31 that is not in contact with the semiconductor stacked structure 20 . Specifically, it is preferable to cover a portion of the lower surface and side surfaces of the light-reflecting electrode 31. FIG. 2E is a plan view for explaining the structure of the first insulating layer 32. The first insulating layer 32 has a first through hole 32h provided corresponding to a region of the semiconductor stacked structure 20 where the hole 20h is provided. The first insulating layer 32 has a plurality of second through holes 32g that expose a portion of the light reflective electrode 31.

As the first insulating layer 32, a film made of an insulating material having barrier properties can be used. For example, a film made of metal oxide, metal nitride, etc. can be used as the first insulating layer 32. Specifically, a film made of at least one kind of oxide or nitride selected from the group consisting of Si, Ti, Zr, Nb, Ta, and Al can be suitably used as the first insulating layer 32. The first insulating layer 32 may include one or more films of these insulating materials.

The second insulating layer 33 is provided to cover the first insulating layer 32 and the side surfaces of the semiconductor stacked structure 20 exposed from the first insulating layer 32 . The second insulating layer 33 suppresses electrical contact between the semiconductor stacked structure 20, the n-electrode structure 40, and the p-electrode structure 50 in areas other than necessary areas.

FIG. 2F is a plan view for explaining the structure of the second insulating layer 33. A third through hole 33h is arranged in the second insulating layer 33 at the bottom surface of the hole 20h, which also covers the inner surface of the hole 20h of the semiconductor stacked structure 20. In the third through hole 33h, the n-side semiconductor layer 21 of the semiconductor stacked structure 20 is exposed. The second insulating layer 33 is further provided with a plurality of fourth through holes 33g, and the fourth through holes 33g communicate with the second through holes 32g of the first insulating layer 32. The light reflecting electrode 31 is exposed within the fourth through hole 33g.

The second insulating layer 33 is formed of an insulating material. For example, a film made of metal oxide, metal nitride, etc. can be used as the second insulating layer 33. Specifically, a film made of at least one kind of oxide or nitride selected from the group consisting of Si, Ti, Zr, Nb, Ta, and Al can be suitably used as the second insulating layer 33. The second insulating layer 33 may include one or more films of these materials. Further, the second insulating layer 33 may be a DBR (Distributed Bragg Reflector) film in which two or more kinds of transparent dielectrics having different refractive indexes are laminated.

[N-electrode structure 40, p-electrode structure 50]
An n-electrode structure 40 and a p-electrode structure 50 are arranged on the second insulating layer 33. The n-electrode structure 40 is connected to the n-side semiconductor layer 21 of the semiconductor stacked structure 20 through the third through-hole 33h, and the p-electrode structure 50 is connected to the light-reflecting electrode through the fourth through-hole 33g and the second through-hole 32g. 31. Since the light reflecting electrode 31 is connected to the p-side semiconductor layer 23, the p-electrode structure 50 is electrically connected to the p-side semiconductor layer 23. The n-electrode structure 40 and the p-electrode structure 50 provide an electrode structure that can be flip-chip bonded to the mounting board 150 and a path for supplying power from the mounting board 150 to the semiconductor laminated structure 20.

The n-electrode structure 40 includes an n-side electrode 41, a first conductive layer 42, a first metal layer 43, and a second conductive layer 44. Similarly, p-electrode structure 50 includes a p-side electrode 51, a first conductive layer 52, a first metal layer 53, and a second conductive layer 54. Each layer included in these n-electrode structure 40 and p-electrode structure 50 has conductivity. A seed layer for forming the first conductive layer 42 by a plating method or the like is provided between the n-side electrode 41 and the first conductive layer 42 and between the p-side electrode 51 and the first conductive layer 52. It's okay.

FIG. 2F is a plan view for explaining the structure of the n-side electrode 41 and the p-side electrode 51. The n-side electrode 41 is arranged on the n-side semiconductor layer 21 exposed at the stepped portion 20r of the semiconductor stacked structure 20, on a part of the n-side semiconductor layer 21 and the second insulating layer 33 exposed in the third through hole 33h. . Further, the p-side electrode 51 is arranged on the light reflecting electrode 31 and the other part of the second insulating layer 33 exposed in the fourth through hole 33g. Since the n-side electrode 41 and the p-side electrode 51 are located at the same height on the second insulating layer 33, the n-side electrode 41 and the p-side electrode 51 are placed on the second insulating layer 33 so as not to be in electrical contact with each other. A gap 34 is provided between the side electrode 51 and the side electrode 51 . The gap 34 can be, for example, 10 μm or more and 30 μm or less. The n-side electrode 41 is directly connected to the n-side semiconductor layer 21. Therefore, in order to form a current path in the entire n-side semiconductor layer 21 as much as possible, the n-side Electrode 41 and n-side semiconductor layer 21 are connected. On the other hand, the p-side electrode 51 is electrically connected to the p-electrode structure 50 via the light-reflecting electrode 31 that diffuses the current path. By employing such a structure, it becomes possible to diffuse current throughout the semiconductor stacked structure 20 and cause the light emitting element 101 to emit light efficiently.

In the n-electrode structure 40, the first conductive layer 42 is disposed on the n-side electrode 41 and is electrically connected to the n-side semiconductor layer 21 of the semiconductor stacked structure 20 via the n-side electrode 41. The first metal layer 43 is placed on the top surface of the first conductive layer 42 . The second conductive layer 44 is arranged on the upper surface of the first metal layer 43.

As shown in FIG. 2A, in this embodiment, the first conductive layer 42, the first metal layer 43, and the second conductive layer 44 have approximately the same planar shape and are stacked on each other. The side surface 43s of the first metal layer 43 is not covered with the first conductive layer 42 and the second conductive layer 44 over the entire circumference and is exposed from the first conductive layer 42 and the second conductive layer 44.

Similarly, in the p-electrode structure 50, the first conductive layer 52 is disposed on the p-side electrode 51, and connects to the p-side semiconductor layer 23 of the semiconductor stacked structure 20 via the p-side electrode 51 and the light-reflecting electrode 31. electrically connected. The first metal layer 53 is arranged on the upper surface of the first conductive layer 52. The second conductive layer 54 is arranged on the upper surface of the first metal layer 53.

As shown in FIG. 2A, in this embodiment, the first conductive layer 52, the first metal layer 53, and the second conductive layer 54 have approximately the same planar shape and are stacked on each other. The side surface 53s of the first metal layer 53 is not covered with the first conductive layer 52 and the second conductive layer 54 over the entire circumference and is exposed from the first conductive layer 52 and the second conductive layer 54.

A film of a metal material can be used for the n-side electrode 41 and the p-side electrode 51, for example, a film of metal such as Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, etc. Alternatively, films of alloys containing these metals as main components can be suitably used. When using an alloy film, an alloy containing a non-metallic element such as Si as a constituent element can also be used, such as an AlSiCu alloy (ASC). The n-side electrode 41 and the p-side electrode 51 may include one or more films of these metals or alloys.

For the first conductive layers 42, 52 and the second conductive layers 44, 54, metal films such as Cu, Au, Ni, etc. can be suitably used. The first conductive layers 42, 52 and the second conductive layers 44, 54 may include one or more films of these metals. In particular, the first conductive layers 42, 52 and the second conductive layers 44, 54 preferably contain Cu from the viewpoint of good electrical conductivity and thermal conductivity. When the second conductive layers 44 and 54 include a plurality of films, at least the mounting surface is It is preferable to form the uppermost layer with an Au film. When the second conductive layers 44 and 54 include a plurality of films and the lower layer is made of a metal other than Au, such as Cu, the upper layer is made of Ni/Au or Ni in order to improve the adhesion with Au. It may also have a laminated structure such as /Pd/Au.

Furthermore, in order to further improve the adhesion at the interfaces between the first metal layers 43, 53 and the first conductive layers 42, 52, and at the interfaces between the first metal layers 43, 53 and the second conductive layers 44, 54, A film of a metal with good adhesion, such as Ni or Ti, may be used as the top layer of the first metal layers 43, 53 and the bottom layer of the first metal layers 43, 53.

The first metal layers 43 and 53 are made of a material whose wettability with respect to the bonding member 140 is smaller than that of the second conductive layers 44 and 54 with respect to the bonding member 140. Specifically, the first metal layers 43 and 53 are made of a film containing at least one member selected from the group consisting of Ti, Cr, Ni, W, and Mo. These metals have lower wettability with respect to the bonding member 140 described later than the above-mentioned metal materials whose main components are Cu, Au, and Ni. The wettability of the bonding member 140 is evaluated by the contact angle of the bonding member 140 placed on the surface of the member to be evaluated in a state where the bonding member 140 is melted and movable as a liquid. The higher the contact angle, the lower the wettability. However, it is not always necessary to obtain the contact angle value. For example, in the case where the molten bonding member 140 is placed on the surfaces of the first metal layers 43, 53 and the second conductive layer 44, if it can be determined in which layer the contact angle is larger, the above-mentioned wettability characteristics can be determined. It can be determined whether the first metal layers 43, 53 can have the same. As the metal material used for the first metal layers 43, 53 and the second conductive layers 44, 54, for example, when forming the first metal layers 43, 53 by a plating method, the first metal layers 43, 53 are Ni can be used, and the second conductive layers 44 and 54 can be made of Au. Further, when forming the first metal layers 43, 53 by sputtering, the first metal layers 43, 53 can be made of W, and the second conductive layers 44, 54 can be made of Cu. Further, the first conductive layers 42, 52 and the second conductive layers 44, 54 are preferably formed of the same metal material from the viewpoint of process simplification.

In the n-electrode structure 40 and the p-electrode structure 50, the thickness of the n-side electrode 41 and the p-side electrode 51 is, for example, about 500 nm to 2 μm. Further, the thickness of the first conductive layers 42, 52 and the second conductive layers 44, 54 is, for example, about 5 μm to 25 μm. As will be described later, the first metal layers 43 and 53 utilize their wettability to the bonding member 140 to prevent the bonding member 140 from creeping up onto the light emitting element 101 . In order to obtain this effect, the first metal layers 43 and 53 preferably have a thickness of 100 nm or more. If the thickness is less than 100 nm, there is a possibility that the bonding member 140 may reach the first conductive layers 42, 52 beyond the first metal layers 43, 53 if an excessive amount of the bonding member 140 is placed. . From the viewpoint of obtaining the above-mentioned effects, there is no upper limit to the thickness of the first metal layers 43, 53. However, some of the metal materials for the first metal layers 43 and 53 described above have relatively high electrical resistance. Further, there are metal materials that have limitations in manufacturing methods, making it difficult to form the thick first metal layers 43 and 53, or requiring a long time to form, which poses problems in terms of manufacturing costs. Considering these points, it is preferable that the thickness of the first metal layers 43, 53 is 5 μm or less. Further, the thickness of the first metal layers 43 and 53 is more preferably about 1 μm or more and 5 μm or less.

[Joining member 140]
The bonding member 140 is a bonding member that can bond the light emitting element 101 to the mounting board 150 by a reflow method or the like. Specifically, the bonding member 140 includes at least one selected from the group consisting of AuSn, AgSn, and CuSn.

[Mounting board 150]
The mounting board 150 supports the light emitting element 101 and supplies power to the light emitting element 101. As shown in FIG. 1, the mounting board 150 includes a base 151 and a conductive pattern 152 disposed on the top surface of the base 151. The base 151 may be made of an insulating material or a conductive material. For example, the mounting board 150 may be a printed or flexible board in which conductor wiring is printed on the upper surface of a base 151 made of insulating resin. More specifically, a glass epoxy substrate whose surface is provided with a conductive pattern made of copper foil or the like, or a metal substrate bonded with an insulating resin can be suitably used. Alternatively, a substrate may be used in which conductive wiring is provided on a metal material such as aluminum or copper through an insulating material. A substrate made of a metal material such as aluminum or copper has high heat dissipation properties. Further, the mounting board 150 may be a resin package having a recessed portion for housing the light emitting element 101. In this case, the mounting board 150 is composed of an insulating resin and a conductive lead electrode.

A bonding member 140 is located between the conductive pattern 152 of the mounting substrate 150 and the upper surfaces of the n-electrode structure 40 and the p-electrode structure 50, and the light emitting element 101 is bonded to the mounting substrate 150.

2. Method for manufacturing light emitting device 201 Next, a method for manufacturing light emitting device 201 will be described. FIG. 3 is a flowchart showing an example of a method for manufacturing the light emitting device 201, and FIGS. 4A to 4L are process cross-sectional views showing an example of the method for manufacturing the light emitting device 201. In the following manufacturing methods, unless otherwise mentioned, thin film forming techniques and photolithography techniques using CVD equipment, vacuum evaporation equipment, sputtering equipment, exposure equipment, development equipment, etc., commonly used in the manufacturing of semiconductor devices. Each step can be performed using, for example.

(1) Formation of semiconductor stack structure (S1)
First, a semiconductor stacked structure is formed on a substrate. As shown in FIG. 4A, an n-side semiconductor layer 21, an active layer 22, and a p-side semiconductor layer 23 are sequentially epitaxially grown on the upper surface of a substrate 10 made of sapphire or the like to form a semiconductor stacked structure 20 supported by the substrate 10.

Next, as shown in FIG. 4B, a light reflective electrode 31 and a first insulating layer 32 are formed on the semiconductor stacked structure 20. The first insulating layer 32 is formed to cover the top and side surfaces of the light reflective electrode 31 .

Next, as shown in FIG. 4C, a hole 20h and a stepped portion 20r are formed in the semiconductor stacked structure 20. The holes 20h and the stepped portions 20r are formed, for example, by forming a mask on the first insulating layer 32, which has openings that define the holes 20h and the stepped portions 20r, and using the mask to form the first insulating layer 32 and the semiconductor stacked structure 20. Formed by etching. Then remove the mask. Further, as shown in FIG. 4D, a second insulating layer 33 is formed to cover the first insulating layer 32 and the side surfaces of the semiconductor stacked structure 20. Thereafter, a mask having openings that define the third through hole 33h and the fourth through hole 33g is formed on the second insulating layer 33, and the second insulating layer 33 is etched using the mask. A hole 33h and a fourth through hole 33g are formed. At the position of the fourth through hole 33g, the first insulating layer 32 is also etched to form a second through hole 32g communicating with the fourth through hole 33g, and the light reflecting electrode 31 is exposed at the bottom of the fourth through hole 33g. let

(2) Formation of n-electrode structure 40 and p-electrode structure 50 As shown in FIG. 4E, an n-side electrode 41 and a p-side electrode 51 are formed on the semiconductor stacked structure 20. The n-side electrode 41 and the p-side electrode 51 are formed, for example, by forming a film of a metal material constituting the electrode so as to cover the entire second insulating layer 33, and then patterning the film using a mask.

(2-1) Step of forming a first photoresist layer (S2)
As shown in FIG. 4F, a first photoresist layer 61 having a first opening 61n located above the n-side electrode 41 and a second opening 61p located above the p-side electrode 51 is formed. The first photoresist layer 61 is supported by the semiconductor stacked structure 20 via the second insulating layer 33, the light reflective electrode 31, and the first insulating layer 32.

(2-2) Step of forming a first conductive layer (S3)
As shown in FIG. 4G, first conductive layers 42 and 52 are formed in the first opening 61n and second opening 61p of the first photoresist layer 61 by plating. Specifically, the n-side electrode 41 and the p-side electrode 51 are immersed in an electrolytic plating solution, and electrolytic plating is performed using the n-side electrode 41 and the p-side electrode 51 as cathodes. As a result, the first conductive layers 42 and 52 are formed on the n-side electrode 41 and the p-side electrode 51 exposed in the first opening 61n and the second opening 61p, respectively.

(2-3) Step of forming the first metal layer (S4)
As shown in FIG. 4H, first metal layers 43 and 53 are formed on the first conductive layers 42 and 52 located within the first opening 61n and second opening 61p of the first photoresist layer 61. The first metal layers 43 and 53 can be suitably formed by, for example, a plating method.

(2-4) Step of forming a second conductive layer (S5)
As shown in FIG. 4I, second conductive layers 44 and 54 are formed on the first metal layers 43 and 53 located in the first opening 61n and second opening 61p of the first photoresist layer 61 by a plating method. Specifically, the first metal layers 43 and 53 are immersed in an electrolytic plating solution, and electrolytic plating is performed using the first metal layers 43 and 53 as a cathode. As a result, second conductive layers 44 and 54 are formed on first metal layers 43 and 53 exposed in first opening 61n and second opening 61p.

(2-5) Step of removing the first photoresist layer (S6)
As shown in FIG. 4J, the first photoresist layer 61 is removed. As a result, as shown in FIG. 2A, an n-electrode structure 40 including an n-side electrode 41, a first conductive layer 42, a first metal layer 43, and a second conductive layer 44, a p-side electrode 51, a first conductive layer 52, etc. , a light emitting device 101 having a p-electrode structure 50 including a first metal layer 53 and a second conductive layer 54 is completed.

3. Step of mounting the light emitting element 101 (S7)
As shown in FIG. 4K, a mounting board 150 is prepared, and a bonding member paste 141 is placed on the conductive pattern 152 of the mounting board 150 by a printing method or the like. Thereafter, the light emitting element 101 is aligned with the mounting board 150 so that the upper surface of the n electrode structure 40 and the upper surface of the p electrode structure 50 face the mounting board 150, and the upper surface of the n electrode structure 40 and the p electrode The top surface of structure 50 is brought into contact with paste 141.

As shown in FIG. 4L, the mounting board 150 on which the light emitting elements 101 are aligned is introduced into a reflow oven, and the mounting board 150 is heated. As a result, the bonding member 140 such as Au-Sn in the paste 141 is melted. Further, volatile components in the paste 141 evaporate. At this time, a portion of the melted bonding member 140 creeps up onto the top surface and side surfaces of the second conductive layer 44 of the n-electrode structure 40 and creeps up onto the top surface and side surfaces of the second conductive layer 54 of the p-electrode structure 50. However, the wettability of the first metal layers 43 and 53 to the bonding member 140 is smaller than the wettability of the second conductive layer to the bonding member 140. Therefore, even if the molten bonding member 140 reaches the side surfaces of the first metal layers 43, 53 from the side surfaces of the second conductive layers 44, 54, it is difficult for the molten bonding member 140 to creep up further due to poor wettability. suppressed. As a result, the bonding member 140 melted on the light emitting element 101 during mounting on the mounting board 150 is prevented from creeping up, shorting the electrode structure formed on the light emitting element 101, or having an undesirable effect on the semiconductor stacked structure 20. be done.

After the melted bonding member 140 is uniformly arranged between the top surface of the n-electrode structure 40 and the top surface of the p-electrode structure 50 and the conductive pattern 152, the mounting board 150 is taken out of the reflow oven and the mounting board 150 is cooled. do. This completes the light emitting device 201. Here, if there is a difference in thermal expansion coefficient between the mounting board 150 and the light emitting element 101, thermal stress is generated in the members constituting the light emitting element 101 during the cooling process described above. By adopting a softer material than the bonding member 140 for the first conductive layers 42, 52 and the second conductive layers 44, 54, the thermal stress generated in each member is alleviated, which mainly has an adverse effect on the semiconductor stacked structure 20. can be suppressed from occurring. In such a case, the first metal layers 43 and 53 prevent the bonding member 140 from creeping up onto the semiconductor stacked structure 20, so that at least the side surfaces of the first conductive layers 42 and 52 are covered with the bonding member 140. things are suppressed. As a result, since the first conductive layers 42 and 52 that are not covered by the bonding member 140 exist between the mounting board 150 and the semiconductor laminated structure 20, the thermal stress relaxation function of the first conductive layers 42 and 52 is reduced. can be maintained. As a result, it is possible to effectively suppress the adverse effects that occur on the semiconductor stacked structure 20 due to thermal stress during mounting.

As described above, according to the present embodiment, the wettability of the first metal layers 43 and 53 to the bonding member 140 is smaller than the wettability of the second conductive layers 44 and 54 to the bonding member 140, so that the light emitting element 101 is not mounted. When mounting on the substrate 150, it is possible to suppress the melted joining member 140 from creeping up the side surfaces of the n-electrode structure 40 and the p-electrode structure 50. In addition, since the first metal layers 43 and 53 can be formed using thin film formation technology, the manufacturing process for forming the n-electrode structure 40 and the p-electrode structure 50 may not be significantly changed or a time-consuming process may be required. process is not required. Therefore, it is possible to avoid a significant increase in manufacturing costs and lead time.

(Second embodiment)
A second embodiment of the light emitting device of the present disclosure will be described. FIG. 5A is a cross-sectional view of a light-emitting device 202 illustrating an example of the second embodiment of the light-emitting device of the present disclosure. The light emitting device 202 includes a light emitting element 102, a bonding member 140, and a mounting board 150, and the light emitting element 102 is mounted on the mounting board 150 by the bonding member 140. 5B and 5C are a cross-sectional view and a plan view of the light emitting element.

The light-emitting element 102 includes an n-electrode structure 40 and a p-electrode structure 50 that have shapes different from those of the light-emitting element 101 of the first embodiment.

As shown in FIGS. 5B and 5C, in the n-electrode structure 40, the upper surface 43a of the first metal layer 43 is larger than the lower surface 44b of the second conductive layer 44, and a portion of the upper surface 43a of the first metal layer 43 is , is exposed from the second conductive layer 44 at the peripheral edge of the upper surface 43a of the first metal layer 43.

Similarly, in the p-electrode structure 50, the upper surface 53a of the first metal layer 53 is larger than the lower surface 54b of the second conductive layer 54, and a part of the upper surface 53a of the first metal layer 53 is It is exposed from the second conductive layer 54 at the peripheral edge of the upper surface 53a.

Since the n-electrode structure 40 and the p-electrode structure 50 have such a structure, not only the side surfaces but also a part of the top surface of the first metal layers 43 and 53 are exposed. Therefore, the path for the molten bonding member 140 to creep up is longer than in the first embodiment, making it difficult for the molten bonding member 140 to creep up the sides of the n-electrode structure 40 and the p-electrode structure 50. There is. In addition, since the exposed portions of the first metal layers 43 and 53 with low wettability to the bonding member 140 are longer during the path where the molten bonding member 140 creeps up, the melted bonding member 140 is more reliably exposed. It is possible to suppress the joining member 140 from climbing up the side surfaces of the n-electrode structure 40 and the p-electrode structure 50.

The light emitting device 202 may include a light emitting element 102' shown in FIG. 5D. In the light emitting element 102', the lower surface 43b of the first metal layer 43 is larger than the upper surface 42a of the first conductive layer 42, and a portion of the lower surface 43b of the first metal layer 43 is It is exposed from the first conductive layer 42 at the peripheral edge. Further, the lower surface 53b of the first metal layer 53 is larger than the upper surface 52a of the first conductive layer 52, and a portion of the lower surface 53b of the first metal layer 53 is located at the peripheral edge of the lower surface 53b of the first metal layer 53. 1 is exposed from the conductive layer 52.

Also in the light emitting device 202 including the light emitting element 102', the first metal layers 43 and 53 have a part of the bottom surface exposed in addition to the side surfaces. Therefore, the path for the molten bonding member 140 to creep up is longer than in the first embodiment, making it difficult for the molten bonding member 140 to creep up the sides of the n-electrode structure 40 and the p-electrode structure 50. There is. In addition, since the exposed portions of the first metal layers 43 and 53 with low wettability to the bonding member 140 are longer during the path where the molten bonding member 140 creeps up, the melted bonding member 140 is more reliably exposed. It is possible to suppress the joining member 140 from climbing up the side surfaces of the n-electrode structure 40 and the p-electrode structure 50.

The light emitting elements 102, 102' can be manufactured by the same manufacturing method as the light emitting element 101 of the first embodiment except for the steps described below. When manufacturing the light emitting device 102, the first metal layers 43 and 53 are formed in the first opening 61n and the second opening 61p of the first photoresist layer 61, as shown in FIG. 4H. The first metal layers 43 and 53 are formed by, for example, a plating method. Then, in the second conductive layer forming step (S5) shown in FIG. 3, as shown in FIG. A second photoresist layer 62 is formed. The third opening 62n and the fourth opening 62p are smaller than the first opening 61n and the second opening 61p of the first photoresist layer 61, respectively, and are located within the first opening 61n and the second opening 61p, respectively, in plan view. ing. Then, the second conductive layers 44 and 54 are formed in the third and fourth openings, and then the first photoresist layer 61 and the second photoresist layer 62 are removed.

Further, when manufacturing the light emitting device 102', as shown in FIG. 4G, first conductive layers 42 and 52 having a thickness thinner than the first photoresist layer 61 are formed by a plating method. Thereafter, as shown in FIG. 5F, a metal layer 71 is continuously formed on the upper surfaces of the first conductive layers 42 and 52 and the upper surface and side surfaces of the first photoresist layer 61. The first metal layers 43 and 53 are formed by, for example, a sputtering method. Next, as shown in FIG. 5G, a second photoresist layer 62 having a third opening 62n and a fourth opening 62p is formed on the metal layer 71. The third opening 62n and the fourth opening 62p are larger than the first opening 61n and the second opening 61p of the first photoresist layer 61, respectively, and are located in a region including the first opening 61n and the second opening 61p, respectively, in a plan view. positioned. Then, as shown in FIG. 5H, the second conductive layers 44 and 54 are formed on the metal layer 71 located in the third opening 62n and the fourth opening 62p, and then the first photoresist layer 61 and the second The resist layer 62 may be removed.

(Third embodiment)
A third embodiment of the light emitting device of the present disclosure will be described. FIG. 6A is a cross-sectional view of a light-emitting device 203 illustrating an example of the third embodiment of the light-emitting device of the present disclosure. The light emitting device 203 includes a light emitting element 103, a bonding member 140, and a mounting board 150, and the light emitting element 103 is mounted on the mounting board 150 by the bonding member 140. FIG. 6B is a cross-sectional view of the light emitting element 103. The light emitting element 103 differs from the light emitting element 102 of the second embodiment in that the n-electrode structure 40 includes a second metal layer 45 and a third conductive layer 46. Furthermore, the p-electrode structure 50 differs from the light emitting element 102 of the second embodiment in that it includes a second metal layer 55 and a third conductive layer 56.

In the n-electrode structure 40, the second metal layer 45 is placed on the top surface 44a of the second conductive layer 44, and the third conductive layer 46 is placed on the top surface 45a of the second metal layer 45. The lower surface 45b of the second metal layer 45 is larger than the upper surface 44a of the second conductive layer 44, and a portion of the lower surface 45b of the second metal layer 45 has a second It is exposed from the conductive layer 44. Further, the side surface of the second metal layer 45 is exposed from the second conductive layer 44 and the third conductive layer 46.

Similarly, in the p-electrode structure 50, the second metal layer 55 is placed on the top surface 54a of the second conductive layer 54, and the third conductive layer 56 is placed on the top surface 55a of the second metal layer 55. The lower surface 55b of the second metal layer 55 is larger than the upper surface 44a of the second conductive layer 54, and a portion of the lower surface 55b of the second metal layer 55 has a second It is exposed from the conductive layer 44. Further, the side surface of the second metal layer 55 is exposed from the second conductive layer 54 and the third conductive layer 56.

The second metal layers 45, 55 are made of the same material as the first metal layers 43, 53, and the third conductive layers 46, 56 are made of the same material as the first conductive layers 42, 52. . Therefore, the wettability of the second metal layers 45 and 55 with respect to the bonding member 140 is lower than that of the third conductive layers 46 and 56. The thickness of the second metal layers 45, 55 can be the same as that of the first metal layers 43, 53, and is, for example, about 100 nm or more and 5 μm or less.

According to the light emitting device 203, in addition to the first metal layers 43 and 53, the side surfaces and part of the bottom surface of the second metal layers 45 and 55 are exposed. Therefore, the path for the molten bonding member 140 to creep up is longer than in the second embodiment, making it even more difficult for the molten bonding member 140 to creep up the sides of the n-electrode structure 40 and the p-electrode structure 50. ing. In addition, during the path where the molten bonding member 140 creeps up, the exposed portions of the first metal layers 43, 53 and the second metal layers 45, 55, which have low wettability with respect to the bonding member 140, are long. , it is possible to more reliably suppress the melted joining member 140 from creeping up the side surfaces of the n-electrode structure 40 and the p-electrode structure 50.

The light emitting device 203 can be manufactured by adding a step of forming the second metal layers 45, 55 and the third conductive layers 46, 56 to the method of manufacturing the light emitting element 102 of the second embodiment.

FIG. 7 is a flowchart showing the manufacturing process of the light emitting element 103, and FIGS. 8A and 8B are process cross-sectional views showing a part of the manufacturing process of the light emitting element 103.

First, steps similar to those for manufacturing the light emitting elements 101 and 102 of the first and second embodiments are performed to form up to the second conductive layers 44 and 54, as shown in FIG. 8A (S1 to S6). As described in the second embodiment, the second photoresist layer 62 is smaller than the first opening 61n and the second opening 61p, and is located inside the first opening 61n and the second opening 61p in plan view. It has a third opening 62n and a fourth opening 62p. The second conductive layers 44, 54 are formed within the third opening 62n and the fourth opening 62p. After that, perform the following steps.

(3-1) Step of forming a third photoresist layer (S31)
As shown in FIG. 8B, a third photoresist layer 63 is formed on the second photoresist layer 62. The third photoresist layer 63 has a fifth opening 63n and a sixth opening 63p that are larger than the third opening 62n and the fourth opening 62p, respectively, and are located in a region including the third opening 62n and the fourth opening 62p in plan view. has.

(3-2) Step of forming a second metal layer (S32)
As shown in FIG. 8B, second metal layers 45, 55 are formed on the second conductive layers 44, 54 and the second photoresist layer 62 within the fifth opening 63n and sixth opening 63p of the third photoresist layer 63. Formed by plating method.

(3-3) Step of forming a third conductive layer (S33)
Third conductive layers 46 and 56 are formed on the second metal layers 45 and 55 in the fifth opening 63n and sixth opening 63p of the third photoresist layer 63 by a plating method.

(3-4) Step of removing the first photoresist layer 61, the second photoresist layer 62, and the third photoresist layer 63 (S34)
The first photoresist layer 61, the second photoresist layer 62, and the third photoresist layer 63 are removed. As a result, the first metal layers 43, 53 and the second metal layers 45, 55 are patterned. As shown in FIG. 6B described above, the n-electrode structure includes the n-side electrode 41, the first conductive layer 42, the first metal layer 43, the second conductive layer 44, the second metal layer 45, and the third conductive layer 46. 40, and a light emitting element 103 having a p-electrode structure 50 including a p-side electrode 51, a first conductive layer 52, a first metal layer 53, a second conductive layer 54, a second metal layer 55, and a third conductive layer 56. is completed.

Thereafter, similarly to the first embodiment, the light emitting device 203 is completed by mounting the light emitting element 103 on the mounting board 150.

(Fourth embodiment)
A fourth embodiment of the light emitting device of the present disclosure will be described. FIG. 9A is a cross-sectional view of a light-emitting device 204 illustrating an example of the fourth embodiment of the light-emitting device of the present disclosure. The light emitting device 204 includes a light emitting element 104, a bonding member 140, and a mounting board 150, and the light emitting element 104 is mounted on the mounting board 150 by the bonding member 140. FIG. 9B is a cross-sectional view of the light emitting element 104. The light-emitting element 104 includes an n-electrode structure 40' and a p-electrode structure 50' that are different from the light-emitting element 101.

Specifically, as shown in FIG. 9B, in the n-electrode structure 40', the second conductive layer 44' is disposed on the upper surface 42a of the first conductive layer 42, and is smaller than the upper surface 42a of the first conductive layer 42. It has a lower surface 44b'. Further, the first metal layer 43' is disposed at the peripheral edge of the upper surface 42a of the first conductive layer 42 in an exposed region where the second conductive layer 44' is not disposed. The side and top surfaces of the first metal layer 43' are exposed from the first conductive layer 42 and the second conductive layer 44'.

Similarly, in the p-electrode structure 50', the second conductive layer 54' is disposed on the upper surface 52a of the first conductive layer 52 and has a lower surface 54b' that is smaller than the upper surface 52a of the first conductive layer 52. Further, the first metal layer 53' is disposed at the peripheral edge of the upper surface 52a of the first conductive layer 52 in an exposed region where the second conductive layer 54' is not disposed. The side and top surfaces of the first metal layer 53' are exposed from the first conductive layer 52 and the second conductive layer 54'.

According to the light emitting device 204, the side and top surfaces of the first metal layers 43' and 53' are exposed in the n-electrode structure 40' and the p-electrode structure 50' of the light-emitting element 104, as in the second embodiment. . Therefore, the exposed portions of the first metal layers 43 and 53, which have low wettability with respect to the bonding member 140, prevent the melted bonding member 140 from creeping up the side surfaces of the n-electrode structure 40 and the p-electrode structure 50. Can be suppressed.

In addition, in the n-electrode structure 40' and the p-electrode structure 50', the second conductive layers 44', 54' are formed without intervening the first conductive layers 42, 52 and the first metal layers 43', 53'. are in direct contact. Therefore, the second conductive layers 44', 54' improve the adhesion between the first metal layers 43', 53' and the first conductive layers 42, 52 or the second conductive layers 44', 54'. Regardless of quality, the second conductive layers 44', 54' are prevented from peeling off from the n-electrode structure 40' and the p-electrode structure 50'. Furthermore, even if the first metal layers 43', 53' have high resistance, a low-resistance n-electrode structure 40' and p-electrode structure 50' can be realized. An insulating film may be formed on a portion of the upper surface of the first metal layers 43', 53'. For this insulating film, a film made of the same insulating material as the first insulating layer 32 described above can be used. Such an insulating film has relatively lower wettability with respect to the bonding member 140 than the first metal layers 43' and 53'. Therefore, compared to the case where only the first metal layers 43' and 53' are provided, it is possible to further suppress the joining member 140 from creeping up the side surfaces of the n-electrode structure 40 and the p-electrode structure 50.

The light emitting device 204 can be manufactured, for example, by the following steps.

FIG. 10 is a flowchart showing the manufacturing process of the light emitting element 104, and FIGS. 11A to 11E are process cross-sectional views showing a part of the manufacturing process of the light emitting element 104.

First, steps similar to those for manufacturing the light emitting element 101 of the first embodiment are performed to form up to the first metal layers 43 and 53, as shown in FIGS. 11A and 11B (S1 to S4). After that, perform the following steps. Note that in the step of forming the first metal layers 43, 53 shown in FIG. 11B, the first metal layers 43, 53 are continuously formed on the upper surfaces of the first conductive layers 42, 52 and the first photoresist layer 61 by sputtering. It can also be formed by

(4-1) Step of forming a second photoresist layer (S41)
As shown in FIG. 11C, a third opening on the first metal layers 43, 53 is smaller than the first opening 61n and the second opening 61p, respectively, and is located within the first opening 61n and the second opening 61p in plan view. A second photoresist layer 62 having a fourth opening 62n and a fourth opening 62p is formed.

(4-2) Step of exposing the first conductive layer (S42)
Using the second photoresist layer 62 as a mask, the first metal layers 43 and 53 are etched to form a third opening 62n and a fourth opening 62p within the first opening 61n and the second opening 61p, as shown in FIG. 11D. The first conductive layers 42, 52 are exposed with corresponding dimensions. For example, a dry etching method can be used for etching the first metal layers 43 and 53. As a result, a portion of the first metal layers 43, 53 is etched, and first metal layers 43', 53' having an annular shape in plan view are formed.

(4-3) Step of forming a second conductive layer (S43)
As shown in FIG. 11E, second conductive layers 44', 54' are formed by plating on the first conductive layers 42, 52 in the third opening 62n and fourth opening 62p. Specifically, the entire substrate 10 is immersed in an electrolytic plating solution, and electrolytic plating is performed using the n-side electrode 41 and the p-side electrode 51 as cathodes. Thereby, second conductive layers 44', 54' connected to the first conductive layers 42, 52 are formed in the third opening 62n and the fourth opening 62p.

(4-4) Step of removing the first photoresist layer and the second photoresist layer (S44)
First photoresist layer 61 and second photoresist layer 62 are removed. As a result, the first metal layers 43 and 53 are patterned as shown in FIG. 9B. An n-electrode structure 40 including an n-side electrode 41, a first conductive layer 42, a first metal layer 43', and a second conductive layer 44'; a p-side electrode 51; a first conductive layer 52; and a first metal layer 53. A light emitting device 104 having a p-electrode structure 50 including ' and a second conductive layer 54' is completed.

Thereafter, similarly to the first embodiment, the light emitting device 204 is completed by mounting the light emitting element 104 on the mounting board 150.

(other forms)
The light emitting device of the present disclosure is not limited to the above embodiments, and various modifications are possible. For example, the number of light emitting elements mounted on the mounting board is not limited to one, and the light emitting device may include a plurality of light emitting elements mounted on the mounting board. Further, as described above, the mounting board is not limited to a plate shape, but may be the bottom of a resin package including leads. Furthermore, in the above embodiments, both the n-electrode structure and the p-electrode structure included the first metal layer, but in the light-emitting device, either one of the n-electrode structure and the p-electrode structure includes the first metal layer. If so, the above effects can be obtained in the electrode structure including the first metal layer.

For reference, the summary of the method for manufacturing the light emitting device of the present disclosure is summarized below.

[Item 1]
forming, on a substrate, a semiconductor stacked structure including an active layer, and a p-type semiconductor layer and an n-type semiconductor layer disposed with the active layer in between;
forming a first photoresist layer supported by the semiconductor stacked structure and having first and second openings corresponding to an n-electrode structure and a p-electrode structure;
forming a first conductive layer in the first and second openings of the first photoresist layer by plating;
forming a first metal layer on the first conductive layer in the first and second openings by plating or sputtering;
forming a second conductive layer on the first metal layer in the first and second openings by a plating method;
forming the first electrode structure and the second electrode structure supported by the semiconductor structure and exposing side surfaces of the first metal layer by removing the first photoresist layer;
including;
The method for manufacturing a semiconductor device, wherein the first metal layer has lower wettability with respect to the bonding member than the second conductive layer.

[Item 2]
forming, on a substrate, a semiconductor stacked structure including an active layer, and a p-type semiconductor layer and an n-type semiconductor layer disposed with the active layer in between;
forming a first photoresist layer supported by the semiconductor stack structure and having first and second openings corresponding to a first electrode structure and a second electrode structure;
forming a first conductive layer in the first and second openings of the first photoresist layer by plating;
forming a first metal layer on the first conductive layer in the first and second openings by plating or sputtering;
A second photoresist layer having third and fourth openings each smaller than the first opening and the second opening and located inside the first opening and the second opening in plan view. forming on a photoresist layer and the first metal layer;
forming a second conductive layer on the first metal layer in the third and fourth openings by a plating method;
By removing the first photoresist layer and the second photoresist layer, the first photoresist layer is supported by the semiconductor structure and the outer edge of the side surface of the first metal layer and the top surface of the first metal layer are exposed. forming a first electrode structure and the second electrode structure;
including;
The method for manufacturing a semiconductor device, wherein the first metal layer has lower wettability with respect to the bonding member than the second conductive layer.

[Item 3]
forming, on a substrate, a semiconductor stacked structure including an active layer, and a p-type semiconductor layer and an n-type semiconductor layer disposed with the active layer in between;
forming a first photoresist layer supported by the semiconductor stack structure and having first and second openings corresponding to a first electrode structure and a second electrode structure;
forming a first conductive layer having substantially the same thickness as the first photoresist layer in the first and second openings of the first photoresist layer by plating;
a second photoresist layer having third and fourth openings each larger than the first opening and the second opening and including the first opening and the second opening in plan view; a step of forming on top;
forming a first metal layer on the first photoresist layer and the first conductive layer in the third and fourth openings by plating or sputtering;
forming a second conductive layer on the first metal layer in the third and fourth openings by a plating method;
By removing the first photoresist layer and the second photoresist layer, the first photoresist layer is supported by the semiconductor structure and the outer edge of the side surface of the first metal layer and the bottom surface of the first metal layer are exposed. forming a first electrode structure and the second electrode structure;
including;
The method for manufacturing a semiconductor device, wherein the first metal layer has lower wettability with respect to the bonding member than the second conductive layer.

[Item 4]
forming, on a substrate, a semiconductor stacked structure including an active layer, and a p-type semiconductor layer and an n-type semiconductor layer disposed with the active layer in between;
forming a first photoresist layer supported by the semiconductor stack structure and having first and second openings corresponding to a first electrode structure and a second electrode structure;
forming a first conductive layer in the first and second openings of the first photoresist layer by plating;
forming a first metal layer on the first conductive layer in the first and second openings by plating or sputtering;
A second photoresist layer having third and fourth openings each smaller than the first opening and the second opening and located inside the first opening and the second opening in plan view. forming on a photoresist layer and the first metal layer;
forming a second conductive layer having the same thickness as the second photoresist layer on the first metal layer in the third and fourth openings by plating;
A third photoresist layer having fifth and sixth openings each larger than the third opening and the fourth opening and including the third opening and the fourth opening in plan view, is formed in the second photoresist layer. a step of forming on top;
forming a second metal layer on the second photoresist layer and the first metal layer by plating or sputtering;
forming a third conductive layer on the second metal layer in the fifth and sixth openings by a plating method;
By removing the first photoresist layer, the second photoresist layer, and the third photoresist layer, a side surface of the first metal layer, a top surface of the first metal layer, and a side surface of the first metal layer, which is supported by the semiconductor structure, are removed. forming the first electrode structure and the second electrode structure in which an outer edge of the second metal layer, a side surface of the second metal layer, and an outer edge of the bottom surface of the second metal layer are exposed;
including;
Manufacturing a semiconductor device, wherein the first metal layer has a lower wettability with respect to the bonding member than the second conductive layer, and the wettability of the second metal layer with respect to the bonding member is lower than the third conductive layer. Method.

[Item 5]
forming, on a substrate, a semiconductor stacked structure including an active layer, and a p-type semiconductor layer and an n-type semiconductor layer disposed with the active layer in between;
forming a first photoresist layer supported by the semiconductor stack structure and having first and second openings corresponding to a first electrode structure and a second electrode structure;
forming a first conductive layer in the first and second openings of the first photoresist layer by plating;
forming a first metal layer on the first conductive layer in the first and second openings by plating or sputtering;
A second photoresist layer having third and fourth openings each smaller than the first opening and the second opening and located inside the first opening and the second opening in plan view. forming on a photoresist layer and the first metal layer;
etching the first metal layer using the second photoresist layer as a mask to expose the first conductive layer in the first opening and the second opening;
forming a second conductive layer on the first conductive layer in the third and fourth openings by a plating method;
By removing the first photoresist layer and the second photoresist layer, the first metal layer is supported on the semiconductor structure and the first metal layer is removed from the exposed portion of the top surface of the first conductive layer and the second conductive layer. forming the first electrode structure and the second electrode structure covering a portion of the side surfaces of the layers and exposing the side surfaces and top surface of the first metal layer;
including;
The method for manufacturing a semiconductor device, wherein the first metal layer has lower wettability with respect to the bonding member than the second conductive layer.

Embodiments of the present disclosure are useful for various illumination light sources, vehicle-mounted light sources, display light sources, and the like.

10 Substrate 20 Semiconductor stacked structure 20a, 42a, 43a, 44a, 52a, 53a, 54a, 55a Top surface 20b, 42b, 43b, 44b, 52b, 53b, 54b, 55b Bottom surface 20h Hole 20r Step portion 21 N-side semiconductor layer 22 Active Layer 23 P-side semiconductor layer 31 Light reflective electrode 32 First insulating layer 32h First through hole 32g Second through hole 33 Second insulating layer 33h Third through hole 33g Fourth through hole 34 Gap 40, 40' N electrode structure 41 N-side electrodes 42, 52 First conductive layer 43, 43' 53, 53' First metal layer 43s, 44s, 53s Side surface 44, 44', 54, 54' Second conductive layer 45, 45', 55, 55' Second metal layer 46, 56 Third conductive layer 50, 50' p-electrode structure 51 p-side electrode 61 first photoresist layer 61n first opening 61p second opening 62 second photoresist layer 62n third opening 62p fourth opening 63 Third photoresist layer 63n Fifth opening 63p Sixth openings 101 to 104 Light emitting element 101a Light extraction surface 101b Electrode surface 140 Bonding member 141 Paste 150 Mounting board 151 Base 152 Conductive patterns 201 to 204 Light emitting device

Claims (10)

a semiconductor stacked structure including an active layer, a p-side semiconductor layer and an n-side semiconductor layer disposed with the active layer in between;
a p-electrode structure disposed on the upper surface of the semiconductor stacked structure and electrically connected to the p-side semiconductor layer; and an n-electrode structure electrically connected to the n-side semiconductor layer;
a mounting board to which the upper surfaces of the p-electrode structure and the n-electrode structure are joined by a joining member;
At least one of the p-electrode structure and the n-electrode structure,
a first conductive layer electrically connected to the semiconductor stacked structure;
a second conductive layer disposed on the upper surface of the first conductive layer and having a lower surface smaller than the upper surface of the first conductive layer;
a first metal layer disposed at the periphery of the upper surface of the first conductive layer;
Equipped with
The wettability of the first metal layer to the bonding member is smaller than the wettability of the second conductive layer to the bonding member,
In the light emitting device, a side surface and a top surface of the first metal layer are exposed from the first conductive layer and the second conductive layer. a semiconductor stacked structure including an active layer, a p-side semiconductor layer and an n-side semiconductor layer disposed with the active layer in between;
a p-electrode structure disposed on the upper surface of the semiconductor stacked structure and electrically connected to the p-side semiconductor layer; and an n-electrode structure electrically connected to the n-side semiconductor layer;
A mounting board,
a joining member located between the upper surfaces of the p-electrode structure and the n-electrode structure and the mounting board;
Equipped with
At least one of the p-electrode structure and the n-electrode structure,
a first conductive layer electrically connected to the semiconductor stacked structure;
a first metal layer disposed on the top surface of the first conductive layer;
a second conductive layer disposed on the top surface of the first metal layer;
a second metal layer disposed on the top surface of the second conductive layer;
a third conductive layer disposed on the top surface of the second metal layer;
including;
The wettability of the first metal layer to the bonding member is smaller than the wettability of the second conductive layer to the bonding member,
A side surface of the first metal layer is exposed from the first conductive layer and the second conductive layer,
The wettability of the second metal layer with respect to the bonding member is lower than that of the third conductive layer, and a side surface of the second metal layer is exposed from the second conductive layer and the third conductive layer,
The top surface of the first metal layer is larger than the bottom surface of the second conductive layer, and the top surface of the first metal layer is exposed from the second conductive layer at a peripheral edge of the top surface of the first metal layer. Ori,
The lower surface of the second metal layer is larger than the upper surface of the second conductive layer, and a portion of the lower surface of the second metal layer is exposed from the second conductive layer at a peripheral edge of the lower surface of the second metal layer. A light-emitting device. The light emitting device according to claim 1 or 2 , wherein the first conductive layer has a thickness of 5 μm or more and 25 μm or less. The light emitting device according to any one of claims 1 to 3 , wherein the first conductive layer and the second conductive layer contain Cu or Au. 5. The light emitting device according to claim 1, wherein the first metal layer contains at least one selected from the group consisting of Ti, Cr, Ni, W, and Mo. The light emitting device according to any one of claims 1 to 5, wherein the first metal layer has a thickness of 100 nm or more and 5 μm or less. The light emitting device according to claim 2 , wherein the third conductive layer contains Cu or Au. The light emitting device according to claim 2, wherein the second metal layer contains at least one selected from the group consisting of Ti, Cr, Ni, W, and Mo. The light emitting device according to claim 2 , wherein the second metal layer has a thickness of 100 nm or more and 5 μm or less. The light emitting device according to any one of claims 1 to 9 , wherein the bonding member includes at least one selected from the group consisting of AuSn, AgSn, and CuSn.

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