JP7368505B2 - System and method for integrating stacked integrated circuit die elements and batteries - Google Patents

Description

The present disclosure relates to batteries for computing systems.

Volatile memory requires power to maintain stored data. If power is interrupted, for example if system power is turned off, data will be lost. When power is restored, the system must reload all data back into volatile memory. Reloading data requires time and processing power, thereby increasing system latency.

US Patent No. 6,627,985 U.S. Patent Application Publication No. 16/777,554

Various embodiments of the present disclosure provide systems and methods that include integrated circuit die substrates. Volatile memory is electrically coupled to the integrated circuit die substrate. A first integrated circuit die element is electrically coupled to the integrated circuit die substrate, includes a first field programmable gate array (FPGA), and is disposed proximate the volatile memory. . The charger is operable to receive power from a mains power source having an on state and an off state, with the mains power supply providing power in the on state and not providing power in the off state. A battery module is disposed over the top portion of the first integrated circuit die element and is operable to receive power from the charger and to provide power to the volatile memory at least when the main power is in an off state. is operable to supply

In some embodiments, the systems and methods further include a second integrated circuit die element stacked with and electrically coupled to the volatile memory.

In some embodiments, the volatile memory comprises a portion of the first integrated circuit die element.

In some embodiments, the second integrated circuit die element comprises a microprocessor.

In some embodiments, the second integrated circuit die element comprises a second FPGA and a corresponding reconfigurable dual function memory array.

In some embodiments, the systems and methods include a third integrated circuit die element stacked with and electrically coupled to the second integrated circuit die element; The integrated circuit die elements include either a microprocessor, additional volatile memory, a second FPGA, or a reconfigurable dual-function memory array.

In some embodiments, the systems and methods include a temperature sensor operable to monitor and sense a temperature of at least a portion of the system, and the control logic and microcontroller unit is coupled to the temperature sensor and detects the sensed temperature. is operable to disable one or more connected circuits based on the power source, thereby allowing the volatile memory to continue receiving power from the battery module when the main power is in an off state. Preventing power leakage from volatile memory during

Various embodiments of the present disclosure provide systems and methods that include integrated circuit die substrates. Volatile memory is electrically coupled to the integrated circuit die substrate. A first integrated circuit die element is electrically coupled to the integrated circuit die substrate and positioned proximate the volatile memory. The charger is operable to receive power from a mains power source having an on state and an off state, with the mains power supply providing power in the on state and not providing power in the off state. The battery module is disposed on the integrated circuit die substrate and is operable to receive power from the charger and is operable to power the volatile memory at least when the main power is in an off state. be.

In some embodiments, the systems and methods include a second integrated circuit die element stacked with and electrically coupled to the volatile memory.

In some embodiments, the volatile memory comprises a portion of the first integrated circuit die element.

In some embodiments, the second integrated circuit die element comprises a microprocessor.

In some embodiments, the second integrated circuit die element comprises a second FPGA and a corresponding reconfigurable dual function memory array.

In some embodiments, the systems and methods include a third integrated circuit die element stacked with and electrically coupled to the second integrated circuit die element; The integrated circuit die elements include either a microprocessor, additional volatile memory, a second FPGA, or a reconfigurable dual-function memory array.

In some embodiments, the systems and methods include a temperature sensor operable to monitor and sense a temperature of at least a portion of the system, and the control logic and microcontroller unit is coupled to the temperature sensor and detects the sensed temperature. is operable to disable one or more connected circuits based on the power source, thereby allowing the volatile memory to continue receiving power from the battery module when the main power is in an off state. Preventing power leakage from volatile memory during

Various embodiments of the present disclosure provide systems and methods configured for a volatile memory to receive power from a main power source having an on state and an off state, wherein the main power source is providing power in the on state. In an off state, unpowered, the volatile memory is electrically coupled to the integrated circuit die substrate. a first integrated circuit die element disposed on a top portion of a first integrated circuit die element, the first integrated circuit die element receiving power from a mains power source by a charger and having a first FPGA electrically coupled to the integrated circuit die element; Circuit die elements are placed in close proximity to the volatile memory. The battery receives power from the charger. Volatile memory receives power from the charger. The control logic and microcontroller unit detects that the power output of the main power supply indicates that the main power supply is in an off state. In response to detecting that the power output indicates that the main power supply is in an off state, disabling a first connection circuit between the main power supply and the volatile memory, thereby causing the volatile memory to Preventing power leakage from volatile memory while allowing it to continue receiving power from the memory.

In some embodiments, the volatile memory is electrically connected to and stacked with the second integrated circuit die element.

In some embodiments, the volatile memory comprises a portion of the first integrated circuit die element.

In some embodiments, the second integrated circuit die element comprises a microprocessor.

In some embodiments, the second integrated circuit die element comprises a second FPGA and a corresponding reconfigurable dual function memory array.

In some embodiments, the second integrated circuit die element is electrically coupled to and stacked with the third integrated circuit die element, and the third integrated circuit die element comprises: It includes either a microprocessor, additional volatile memory, a second FPGA, or a reconfigurable dual function memory array.

These and other features of the systems, methods, and non-transitory computer-readable media disclosed herein, as well as the manner of operation and function of associated elements in the structure, combinations of parts, and economics of manufacture, are described herein. These and other features will also become more apparent upon consideration of the following description and appended claims, with reference to the accompanying drawings, all of which form a part of this specification, and like reference numerals refer to the various Specify the corresponding part in the diagram. However, it is to be clearly understood that the drawings are for illustration and explanation only and are not intended to define limitations of the invention.

1 is a block diagram of a processing system including an integrated battery for powering volatile memory of a die stack package, according to some embodiments. FIG. 1 is a block diagram of a processing system including a die stack package and an integrated battery, according to some embodiments. FIG. 1 is a block diagram of a processing system including a die stack package and an integrated battery, according to some embodiments. FIG. 1 is a block diagram of a processing system including a reconfigurable dual-function cell array, according to some embodiments. FIG. FIG. 2 is a block diagram of a matrix of reconfigurable dual-function cell arrays, according to some embodiments. 2 is a flow diagram of a method of operating a processing system that includes a temperature sensor, a die stack package, and an integrated battery, according to some embodiments. 2 is a flowchart of a method of providing power to volatile memory in a die stack package using an integrated battery, according to some embodiments.

In various embodiments, a computing system that integrates a battery with a die stack package that includes volatile memory may improve performance of the computing system. For example, if a computing system's main power goes out (e.g., due to planned maintenance or during an unexpected power outage), integrated batteries may ensure that volatile memory does not lose data. . When main power is restored, the computing system can avoid reloading memory and/or reloading FPGA configuration information. Therefore, recovery time for the computing system may be shorter (eg, 100 times faster) and may use less energy than recovery with loss of volatile memory data. Integrated batteries may also regulate power levels to die stack packages, isolate noisy power components, and provide improved signal quality.

In some embodiments, the computing system also includes a temperature sensor. A temperature sensor may sense the temperature of a computing system and/or a portion of a computing system (eg, an integrated battery, a die stack package, volatile memory, etc.). If the temperature exceeds the threshold temperature, the computing system may perform one or more activities to protect against damage to system components. For example, the computing system may disable the battery, shut down the die stack package, etc. Once the temperature returns to normal operating levels, the computing system may be allowed to recover.

FIG. 1 is a block diagram of a processing system 100 that includes an integrated battery 106 configured to provide power to volatile memory 104 of die stack package 102, according to some embodiments. In the example of FIG. 1, processing system 100 includes a die stack package 102 with volatile memory 104, a mains power supply 105, an integrated battery (or simply "battery") 106, a charger 108, temperature sensor circuitry 112, control logic and micro It includes a controller unit 114 and connection circuits 116 and 118.

Die stack package 102 includes a stack of integrated circuit die elements and volatile memory 104 . Die stack package 102 may include a stack of one or more microprocessors, FPGAs, and/or volatile memory 104. Die stack package 102 may significantly accelerate data sharing between the microprocessor and the FPGA. Examples of die stack packages 102 are shown in FIGS. 2 and 3. An example of a die stacked package is described in US Pat. No. 6,627,985, although there is no support for an integrated battery. In some embodiments, die stack package 102 may include a reconfigurable dual-function cell array (eg, as shown in FIG. 5).

In some embodiments, the die stack package 102 includes three primary devices: a DRAM, an FPGA (logic unit) that allows the die stack package 102 to create a reconfigurable processor, and a microprocessor. (or master processor). Each primary element may be mounted on a die in die stack package 102. All three primary elements are volatile. Therefore, when processing system 100 is powered off, die stack package 102 data stored in memory 104 and FPGA configuration information are lost. In a system without integrated battery 106, when power is applied again, processing system 100 must reload all data back into memory 104 and reload FPGA configuration information. Reloading the memory and/or FPGA configuration (eg, from onboard serial flash memory) can take a long time, thereby increasing system latency.

Volatile memory 104 comprises memory that requires power to maintain stored data. Volatile memory 104 retains stored data while it is powered, but if power is interrupted, the stored data is lost. For example, volatile memory 104 may include DRAM, SRAM, and/or other volatile memory.

Main power supply 105 may function to provide power to processing system 100 . The main power supply 105 may convert the current from the source to the correct voltage, current, and frequency to power the load. Main power supply 105 may convert alternating current power to low voltage regulated direct current power for components of processing system 100. For example, main power supply 105 may be a power supply unit of a computer (eg, desktop computer, server). In some embodiments, main power source 105 may be a mobile device power source. For example, the main power source 105 may be a primary battery in a mobile device (eg, an iPhone).

In some embodiments, the main power source 105 may have an on state, an off state, and a low power state (eg, a sleep state). During the on state, the main power supply 105 is providing power; during the off state, the main power supply 105 is not providing power (or at least the volatile memory 104 is providing sufficient power to prevent loss of memory). power is not being supplied to volatile memory 104). The off-state may be triggered, for example, in response to an unexpected event (eg, power outage) or a planned event (eg, planned maintenance). During the sleep state, the main power supply 105 may be providing reduced power than during the on state and may direct that power to certain components that do not include volatile memory 104. Therefore, certain operations may be interrupted.

Battery 106 may function to power die stack package 102 . For example, battery 106 may provide at least enough voltage for volatile memory 104 to retain data stored therein and/or for FPGA to retain configuration information. In some embodiments, battery 106 may comprise a lithium cell battery. Battery 106 may be integrated with die stack package 102 for heterogeneous integration (eg, as shown in FIGS. 2 and 3). Battery 106 may be charged from power provided by charger 108 . Charger 108 may be charged by receiving power provided by main power source 105 .

In some embodiments, battery 106 may function as a backup power source (eg, a backup for main power source 105). For example, when main power supply 105 is in an off state, battery 106 may still provide sufficient power to die stack package 102 for volatile memory 104 to retain the data stored therein. Battery 106 may also maintain configuration data for the CMOS FPGA silicon of die stack package 102 when main power supply 105 is off.

In some embodiments, when the die stack package 102 is in a normal operating mode, the battery 106 may provide power to the die stack package 102 to maintain power distribution and/or to prevent glitches from the main power supply 105. may isolate power glitches originating from external components, including

In some embodiments, when the main power source 105 is in a sleep state (or low power mode), the connected device (e.g., an Internet-of-Things (IoT) device) is in a low power mode (sleep mode). It's fine. Connected equipment may have timing requirements to perform tasks when it wakes up. The battery 106 may provide sufficient power for the connected equipment to wake up and complete a given task for a given application, thereby meeting the timing requirements for performing the task.

In some embodiments, the battery 106 may be placed within close range of the power source of the die stack package 102. Lithium cell battery designs may provide fast charging, may be produced from cells of arbitrary shape (physical dimension design), and may provide battery safety protection. Current lithium ion battery manufacturers are able to produce arbitrarily shaped cells with small dimensions for die stack packages. For example, arbitrarily shaped cells can stack the battery on top of the die stack package (e.g., as shown in FIG. 3) and/or on the sides of the die stack package (e.g., as shown in FIG. 2). Do it like this.

Temperature sensor circuit 112 may function to monitor and/or sense (or detect) the temperature of processing system 100 and/or a portion of processing system 100. For example, a temperature sensor may detect the temperature of main power supply 105, battery 106, charger 108, die stack package 102, volatile memory 104, etc.

Control logic and microcontroller unit 114 functions to perform and/or trigger various activities (e.g., to control current/power and to reduce the temperature of die stack package 102 to operational levels). You may do so. For example, control logic and microcontroller unit 114 may perform actions based on the temperature detected by temperature sensor circuit 112. In some embodiments, control logic and microcontroller unit 114 may enable and/or disable components of processing system 100.

As shown, control logic and microcontroller unit 114 includes temperature detection circuit 130 and power detection circuit 132. Temperature detection circuit 130 may be operative to receive a sensed temperature value (eg, from a temperature sensor) and/or to determine whether the sensed temperature value exceeds a threshold temperature value. For example, a temperature threshold may correspond to a maximum safe temperature for normal system operation. Power detection circuit 132 may detect the state of main power supply 105 (eg, off state, on state, sleep state).

In some embodiments, control logic and microcontroller unit 114 may function to disable and/or enable connection circuits 116 and 118. Enabling connection circuitry 116 may enable die stack package 102 to receive power from main power source 105 . Disabling connection circuit 116 may prevent die stack package 102 from receiving power from main power supply 105 and/or may prevent power leakage from die stack package 102. Enabling connection circuitry 118 may enable die stack package 102 to receive power from battery 106 . Disabling connection circuitry 118 may prevent die stack package 102 from receiving power from battery 106 and/or may prevent power leakage from die stack package 102.

Normal Operating Mode In normal operating mode, control logic and microcontroller unit 114 enables connection circuits 116 and 118 and charger 168, according to some embodiments. Die stack package 102 receives power from main power supply 105 via electrical path P6. Die stack package 102 also receives power from battery 106 via electrical path P5.

Power Off Mode and Low Power Mode In the power off state and low power state (mode), power detection circuit 132 detects that main power supply 105 is off. Control logic and microcontroller unit 114 enables connection circuitry 118 to regulate power/current to die stack package 102 and temperature sensor circuitry 112. If temperature sensor circuit 112 detects a high temperature, in some embodiments control logic and microcontroller unit 114 disables charger 108 and reduces the current flowing through connection circuit 118 to die stack package 102. During low power mode, die stack package 102 requires low voltage levels that require only volatile memory data and FPGA configuration information to be maintained without changing (eg, abruptly changing) the data. The FPGA component may be an SRAM cell. In some embodiments, control logic and microcontroller unit 114 tristates the FPGA I/O pins of die stack package 102. The FPGA in die stack package 102 does not have to create any DC path that consumes battery power/current. FPGA power distribution allows the battery 106 regulator (connection circuitry 118) to power the die stack package 102 when the processing system 100 operates under a low power mode or when the main power supply 105 is off. become. In some embodiments, other components of processing system 100 do not consume battery power.

Safety Mode When the temperature detection circuit 130 detects a high temperature and the main power supply 105 is in a normal mode (eg, on state), the system may transition to a safety mode. In some embodiments, to enter the security mode, control logic and microcontroller unit 114 disables charger 108 and disables connection circuits 116 and 118. This allows processing system 100 and/or its components (eg, die stack package 102) to cool without performing any tasks. By shutting down die stack package 102, processing system 100 and the computing system as a whole may be protected from damage.

FIG. 2 is a block diagram of a processing system 200 that includes a die stack package 202 and an integrated battery 106, according to some embodiments. In the example of FIG. 2, battery 106 is placed directly on package substrate 204 of die stack package 202. In the example of FIG. Die stack package 202 may include die stack 206 comprised of integrated circuit die elements 207 . Although four integrated circuit die elements 207 are shown here, it will be appreciated that die stack 206 may include one or more integrated circuit die elements 207. Integrated circuit die elements 207 may include microprocessors, FPGAs, volatile memory, reconfigurable dual-function cell arrays, etc., and may be stacked in any configuration. For example, integrated circuit die elements 207 may be stacked immediately next to each other, such as on top of each other (eg, as shown in FIG. 3). An example of a laminate configuration is shown in US Pat. No. 6,627,985. An example of a dual function cell array is shown in US Patent Application Publication No. 16/777,554.

In the example of FIG. 2, battery 106 provides power to die stack 206 and/or one or more integrated circuit die elements 207 of die stack 206, at least when main power source 105 is turned off or in a low power state. supply. In the example of FIG. 2, charger 108 is placed on printed circuit board 201. In the example of FIG.

FIG. 3 is a block diagram of a processing system 300 that includes a die stack package 302 and an integrated battery 106, according to some embodiments. In the example of FIG. 3, die stack package 302 includes package substrate 304, die stack 306, and battery 106. Battery 106 is placed on top of FPGA chip package 307e in die stack 306. FPGA chip package 307e is placed on the side of integrated circuit die element 306e. Like other die stack packages described herein, die stack 306 may include one or more integrated circuit die elements 307. Integrated circuit die elements 307 may include microprocessors, FPGAs, volatile memory, reconfigurable dual-function cell arrays, etc., and may be stacked in any configuration. In some embodiments, battery 106 powers only the FPGA.

Although not shown, the system can have multiple batteries 106 that cooperate to power multiple volatile memories 104. The system can have multiple batteries 106, each supporting one or more different volatile memories 104. The battery may be located adjacent to or on top of the supported volatile memory 104.

FIG. 4A is a block diagram of a processing system 400 that includes a reconfigurable dual-function cell array 402, according to some embodiments. Processing system 400 further includes an FPGA device 404 and a storage memory device 406. In some embodiments, processing system 400 is implemented on a single integrated circuit die (eg, in die stack 206). In other embodiments, processing system 400 is implemented on multiple integrated circuit dies. For example, reconfigurable dual-function cell array 402, FPGA circuitry 404, and/or storage memory circuitry 406 may be implemented across multiple integrated circuit dies. Processing system 400 further includes control logic 408 that functions to configure various cells of reconfigurable dual-function cell array 402 as a memory array or logic array.

Reconfigurable dual-function cell array 402 includes one or more arrays of programmable cells that can be reconfigured to function as control memory cells for FPGA device 404 or as storage memory cells for memory device 406. For example, a single array or a matrix of arrays). As indicated above, programmable cells may be non-volatile memory cells or volatile memory cells. The storage memory cells may function as fast access memory cells (eg, cache) and the control memory cells may function as configuration data for configuring the FPGA. For example, the configuration data stored in the control memory cells can be used to configure the FPGA to configure the FPGA elements 404 to implement complex combinatorial functions and/or relatively simple logic gates (e.g., AND, XOR). Can be configured. In some embodiments, both logic cells and memory cells can be created on the same reconfigurable dual-function cell array 402.

Any number of such reconfigurable dual-function cell arrays 402 may be included within processing system 400. In some embodiments, processing system 400 configures the programmable cells of one reconfigurable dual-function cell array 402 to function as a memory array and the programmable cells of another reconfigurable dual-function cell array 402. The cells can be configured to function as a logical array. For example, if more memory is needed for a particular application, the processing system may reconfigure the logical array to function as a memory array. For example, if more logic is needed for a particular application, the processing system may reconfigure the memory array to function as a logical array. Memory and logic functionality may be increased or decreased as needed, so that the use of external memory may be avoided. This can improve system performance and/or consume less energy than conventional systems.

FPGA element 404 comprises circuitry configured to provide the functionality of an FPGA and/or a programmable logic device (PLD). FPGA element 404 includes I/O macro circuits 410-0 to 410-7. I/O macrocircuit 410 functions to provide complex combinatorial functions and/or relatively simple logic gates (eg, AND, XOR). Although eight I/O macro circuits 410 are shown here (eg, based on the number of rows/columns of reconfigurable dual function cell array 402), any number of such circuits may be present.

Control logic 408 functions to configure (eg, program) memory cells of reconfigurable dual-function cell array 402 as storage memory cells or control memory cells. Configuration may occur after manufacturing (eg, in the field). For example, different applications may have different storage memory and/or logic requirements. Control logic 408 may configure cells of reconfigurable dual-function cell array 402 automatically based on requirements or in response to user input. When requirements change, the cell may be reconfigured again. In some embodiments, individual cells of reconfigurable dual-function cell array 402 may have a default configuration as a storage memory cell or a control memory cell. In some embodiments, the default configuration may be a null configuration and may be reconfigured to storage memory cells or control memory cells.

Storage memory element 406 includes circuitry for memory operations, such as reading and/or writing. Storage memory element 406 includes Y-pass circuit 420 and sense amplifiers 430-0 through 430-7. Although eight sense amplifiers 430 are shown here (one sense amplifier per column of cells in reconfigurable dual-function cell array 402), any suitable number of sense amplifiers 430 (e.g., reconfigurable dual-function It will be appreciated that (based on the number of columns in cell array 402) may be used. Generally, sense amplifier 430 includes circuitry for reading data from reconfigurable dual-function cell array 402 (eg, from cells programmed as storage memory cells). Sense amplifier 430 senses low power signals from the bit lines of reconfigurable dual function cell array 402 representing data bits (e.g., 1 or 0) stored in storage memory cells to recognize small voltage swings. It functions to amplify to a possible logic level so that the data can be properly interpreted by logic outside of the reconfigurable dual function cell array 402.

In some embodiments, processing system 400 that includes a matrix of reconfigurable dual-function cell arrays may be implemented on a single integrated circuit die. A single integrated circuit die may be used independently of other integrated circuit dies and/or combined with other integrated circuit dies (e.g., microprocessor dies, memory dies, FPGA dies) in various configurations to further improve performance. May be laminated. For example, a laminate may include any combination of layers. Each layer may be a single die. One layer may include a processing system 400 and another layer may include a microprocessor die.

Storage Memory Mode In the storage memory mode of operation, control logic 408 sets a configuration value to a memory mode (e.g., “low”) to control at least some blocks (e.g., subarrays) of reconfigurable dual-function cell array 402. is configured as a storage memory. In some embodiments, the storage memory mode disables FPGA functionality (eg, output functionality of FPGA element 404). Bit line decoder/address buffer 440, word line decoder/address buffer 450, and/or Y-pass 420 address cell or row of cells. Data is transferred into and out of memory cells. Sense amplifier 430 connects to internal or external wiring channels.

FPGA Mode In the FPGA mode of operation, control logic 408 sets a configuration value to a logic mode (e.g., "high") to configure at least a portion of reconfigurable dual-function cell array 402 to achieve a logic function. do. In some embodiments, FPGA mode disables memory circuitry 406 and enables FPGA device 404. The address buffer may provide addresses to the reconfigurable dual function cell array 402 to implement logic functions. The output of reconfigurable dual function cell array 402 (eg, an AND-OR array) connects to I/O macrocircuit 410. I/O macro circuit 410 receives configuration data from the logic array. The configuration data configures the I/O macro circuit 410 to generate results based on the configuration data.

FIG. 4B is a block diagram of a matrix 450 of reconfigurable dual-function cell array 402, according to some embodiments. Matrix 450 includes a storage memory array and a logic array. As illustrated, some arrays may be programmed as storage memory arrays and some arrays may be programmed as logical arrays. When a design or application requires more storage memory cells, a logic memory array can be reconfigured (eg, programmed) from a logic memory array to a storage memory array. When a design or application requires more logic cells, the storage memory array can be reconfigured (eg, reprogrammed) from the storage memory array to a logic array. This approach can increase the effectiveness of memory array usage and reduce energy consumption.

In the example of FIG. 4B, matrix 450 includes a storage memory array 452 in region n,m of matrix 450 and a logic array in region n,1. Processing system 400 can reconfigure any of the arrays. For example, processing system 400 may reconfigure storage memory array 452 in regions n, m into a logical array.

FIG. 5 depicts a flowchart of a method 500 of providing power to volatile memory (eg, volatile memory 104) from an integrated battery (eg, battery 106), according to some embodiments. In this and other flowcharts and/or sequence diagrams, a flowchart illustrates, by way of example, a sequence of steps. It is to be understood that the steps may be rearranged or reordered to perform in parallel when applicable. Additionally, to avoid obscuring the invention and for clarity, we have removed certain steps that may have been included, and some steps that were included. can be removed, but may have been included for clarity of illustration.

At step 502, a main power supply (eg, main power supply 105) powers volatile memory (eg, volatile memory 104) of a die stack package (eg, die stack package 102, 202, or 302). For example, the volatile memory may be a memory die of a die stack (eg, die stack 206 or 306).

At step 504, the mains power supplies power to a charger (eg, charger 108). At step 506, the charger provides power to an integrated battery (eg, battery 106). At step 508, the integrated battery powers the volatile memory.

At step 510, a temperature sensor (eg, temperature sensor circuit 112) detects one or more temperatures of at least a portion of a processing system (processing system 100, processing system 200, or processing system 300). For example, a temperature sensor may sense the overall temperature of processing system 100 or one or more temperatures associated with a battery, charger, die stack package, mains power, etc.

At step 512, if the detected temperature exceeds the threshold temperature value, the control logic and microcontroller unit (e.g., control logic and microcontroller unit 114) detects whether the main power is on (step 514). ). For example, a temperature sensing circuit (e.g., temperature sensing circuit 130) may determine whether the sensed temperature exceeds a threshold, and a power sensing circuit (e.g., power sensing circuit 132) may determine whether the sensed temperature exceeds a threshold when the main power is off. You can detect whether it exists. If the main power is off, the control logic and microcontroller unit triggers a power off and safe low power mode (step 516). If power is on, the control logic and microcontroller unit triggers a security mode (step 518). In some embodiments, step 512 is not performed and only a single security mode exists.

In power off and safe low power modes, the control logic and microcontroller unit may perform one or more operations to reduce temperature to prevent damage to the system. For example, the control logic and microcontroller unit may override the charger. The control logic and microcontroller unit may reduce the current through connection circuit R2 (eg, connection circuit 118) to just enough power for the volatile memory to retain the memory contents. The control logic and microcontroller unit may interrupt all current through connection circuit R2 (eg, connection circuit 118). After the processing system has cooled sufficiently to resume normal operating mode, the method may re-enable the charger and return the connection to a fully operational state. In some embodiments, the system may perform a layered safety response, for example, may shut down the charger first. If cooling is not sufficient, the system may disconnect the battery. For example, the control logic and microcontroller unit may shut down and isolate the die stack by disabling the second connection circuit R1 (connection circuit 116).

In the security mode, the control logic and microcontroller unit may disable the battery, charger, and both connecting circuits R1 and R2. In some embodiments, the system may perform a hierarchical safety response, for example, first shutting off the power, shutting off the charger if insufficient, and shutting down the battery if insufficient. may be stopped. Alternatively, a layered safety response may first shut down the power source and charger, and if insufficient, shut down the battery. Although the contents of volatile memory are lost, this may help prevent damage to components of the processing system.

Method 500 may return to step 510. If the temperature still exceeds the threshold, the control logic and microcontroller unit may perform additional remedial measures. If the system has cooled sufficiently (eg, the temperature no longer exceeds the threshold temperature value), the control logic and microcontroller unit may return the processing system to a normal operating mode (eg, step 502).

FIG. 6 is a flowchart of a method 600 of providing power to volatile memory (eg, volatile memory in a die stack package) using an integrated battery, according to some embodiments.

At step 602, volatile memory (eg, volatile memory 104) receives power from a mains power source. The main power source may have an on state and an off state. The main power supply provides power in the on state and no power in the off state. Volatile memory may be electrically coupled to an integrated circuit die substrate (eg, substrate 204 or 304).

At step 604, a charger (e.g., charger 108) receives power from a mains power source and is electrically coupled to the integrated circuit die substrate on top of a first integrated circuit die element comprising a first FPGA. The first integrated circuit die element is disposed proximate the volatile memory.

At step 606, an integrated battery (eg, battery 106) receives power from a charger. At step 608, the volatile memory receives power from the charger. At step 610, the control logic and microcontroller unit (eg, control logic and microcontroller unit 114) detects that the power output of the main power supply indicates that the main power supply is in an off state.

At step 612, the control logic and microcontroller unit connects a first connection circuit between the main power supply and the volatile memory in response to detecting that the power output indicates that the main power supply is in an off state. disabling, thereby preventing power leakage from the volatile memory while allowing the volatile memory to continue receiving power from the battery (and retaining the contents of the volatile memory).

Throughout this specification, multiple instances may implement a component, act, or structure as a single instance. Although individual acts of one or more methods are illustrated and described as separate acts, one or more of the individual acts may be performed simultaneously, requiring the acts to be performed in the order illustrated. isn't it. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements are within the scope of the subject matter herein. It will be further appreciated that, as used herein, the term "or" may be interpreted in an inclusive or exclusive sense.

One or more inventions have been described above with reference to example embodiments. It will be apparent to those skilled in the art that various modifications may be made and other embodiments may be used without departing from the broader scope of the invention(s). Accordingly, these and other variations to the example embodiments are intended to be encompassed by one or more of the inventions.

Claims (17)

A system,
an integrated circuit die substrate;
a volatile memory electrically coupled to the integrated circuit die substrate;
a first integrated circuit die element comprising a first field programmable gate array (FPGA) electrically coupled to the integrated circuit die substrate;
A charger operable to receive power from a mains power supply having an on state and an off state, the mains power supply being operable to provide power and maintain the volatile memory when in the on state. a charger configured and configured not to provide power to maintain the volatile memory when in the off state;
a battery module operable to receive power from the charger and to power the volatile memory at least when the main power source is in the off state;
a temperature sensor operable to monitor a temperature of at least a portion of the system;
Based on the temperature , disabling one or more connection circuits connecting the volatile memory to the main power supply or connecting the volatile memory to the battery module, thereby removing the volatile memory from excessive temperatures. control logic and a microcontroller unit coupled to the temperature sensor, the system comprising: a control logic and microcontroller unit coupled to the temperature sensor; The system of claim 1 further comprising a second integrated circuit die element stacked with and electrically coupled to the volatile memory. 3. The system of claim 2, wherein the second integrated circuit die element comprises a microprocessor. 3. The system of claim 2, wherein the second integrated circuit die element comprises a second FPGA. 3. The system of claim 2, wherein the second integrated circuit die element comprises one of a microprocessor, additional volatile memory, a second FPGA, or a reconfigurable dual-function memory array. A system,
an integrated circuit die substrate;
a volatile memory electrically coupled to the integrated circuit die substrate;
a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first FPGA and located in close proximity to the volatile memory;
A charger operable to receive power from a mains power source having an on state and an off state, wherein the mains power source is providing power in the on state and not providing power in the off state. charger and
a first integrated circuit die element disposed on a top portion of the device and operable to receive power from the charger, at least when the main power source is in the off state, powering the volatile memory; a battery module operable to supply
a temperature sensor operable to monitor and sense a temperature of at least a portion of the system;
a control logic and microcontroller unit coupled to the temperature sensor;
the control logic and microcontroller unit is operable to disable one of the one or more connected circuits during a fault condition based on the sensed temperature;
The one or more connection circuits are configured to connect the volatile memory to the battery module while allowing the volatile memory to continue receiving power from the battery module when the main power source is in the off state during non-fault conditions. operable to prevent power leakage from volatile memory;
system. A system,
volatile memory,
A charger operable to receive power from a mains power supply having an on state and an off state, the mains power supply being operable to provide power and maintain the volatile memory when in the on state. a charger configured and configured not to provide power to maintain the volatile memory when in the off state;
a battery module operable to receive power from the charger and to power the volatile memory at least when the main power source is in the off state;
a temperature sensor operable to monitor a temperature of at least a portion of the system;
is operable to disable one or more connection circuits connecting the volatile memory to the main power source or connecting the volatile memory to the battery module based on the temperature, thereby; a control logic and microcontroller unit coupled to the temperature sensor to protect the volatile memory from excessive temperatures. 8. The system of claim 7, further comprising an integrated circuit die element stacked with and electrically coupled to the volatile memory. 9. The system of claim 8, wherein the integrated circuit die element comprises a microprocessor. 9. The system of claim 8, wherein the integrated circuit die element comprises an FPGA. 9. The system of claim 8, wherein the integrated circuit die element comprises any of a microprocessor, additional volatile memory, an FPGA, or a reconfigurable dual function memory array. A system,
an integrated circuit die substrate;
a volatile memory electrically coupled to the integrated circuit die substrate;
a first integrated circuit die element electrically coupled to an integrated circuit die substrate and disposed proximate the volatile memory;
A charger operable to receive power from a mains power source having an on state and an off state, wherein the mains power source is providing power in the on state and not providing power in the off state. charger and
disposed on the integrated circuit die substrate and operable to receive power from the charger and operable to power the volatile memory at least when the main power source is in the off state. battery module,
a temperature sensor operable to monitor and sense a temperature of at least a portion of the system;
a control logic and microcontroller unit coupled to the temperature sensor;
The control logic and microcontroller unit is configured to connect the volatile memory to the mains power supply or connect the volatile memory to the battery module during a fault condition based on the sensed temperature. is operable to disable one of the connecting circuits;
The one or more connection circuits are configured to connect the volatile memory to the battery module while allowing the volatile memory to continue receiving power from the battery module when the main power source is in the off state during non-fault conditions. operable to prevent power leakage from volatile memory;
system. A method performed by a system including a volatile memory, a charger, and a battery module, the method comprising:
receiving power by the volatile memory from a main power source having an on state and an off state, the main power supply supplying power to maintain the volatile memory when in the on state; configured to not provide power to maintain the volatile memory when in the off state, the volatile memory being coupled to an integrated circuit die substrate;
receiving power from the main power source by the charger;
receiving power from the charger by the battery module;
receiving power from the battery module by the volatile memory at least when the main power source is in the off state;
detecting the temperature of at least a portion of the system with a temperature sensor;
control logic and a microcontroller unit to disable a first connection circuit connecting the volatile memory to the main power supply or connecting the volatile memory to the battery module in response to the temperature, thereby , protecting the volatile memory from excessive temperatures. 14. The method of claim 13, wherein the volatile memory is stacked with integrated circuit die elements. 15. The method of claim 14, wherein the integrated circuit die element comprises a microprocessor. 15. The method of claim 14, wherein the integrated circuit die element comprises an FPGA. 15. The method of claim 14, wherein the integrated circuit die element comprises any of a microprocessor, additional volatile memory, an FPGA, or a reconfigurable dual function memory array.

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