JP7363255B2 - Information processing device, information processing method, and program - Google Patents

Description

The present invention relates to a cache used in an information processing device and the like, and particularly to an instruction cache for storing instructions.

The information processing device includes a processor as an entity that executes specific instructions. The execution of an instruction in a processor requires the instruction to be executed and the data used by the instruction. If instructions and data are not provided, the processor waits for instructions and data. In other words, the processor stops executing. In order to increase the execution efficiency of a processor, it is important to supply instructions and data to the processor so that the execution of the processor does not stop.

Data necessary for an instruction can be stored in a data cache in advance using a prefetch instruction or the like. However, the instructions include branch instructions and the like. The instruction executed after a branch instruction differs depending on whether a branch occurs or not. Therefore, it is difficult to prefetch instructions into the instruction cache.

Note that there is a branch predictor as a configuration for predicting whether or not a branch will be taken by a branch instruction. However, prediction based on a branch predictor is just a prediction. Therefore, actual processor operations do not necessarily branch as predicted by the branch predictor.

Therefore, techniques for realizing caching of instructions have been proposed (see, for example, Patent Documents 1 and 2).

Patent Document 1 discloses a technique for inserting an instruction for prefetching instructions into an instruction string generated by a compiler.

Patent Document 2 discloses a technique for moving a specific task to a core with a low cache miss rate.

Japanese Patent Application Publication No. 11-306028 Japanese Patent Application Publication No. 2014-130644

Among the instructions executed by a processor, there are instructions that are frequently executed. It is desirable that such frequently executed instructions are always placed in the instruction cache.

However, the technique described in Patent Document 1 does not distinguish between instructions when replacing instructions in the instruction cache.

Therefore, the technique described in Patent Document 1 has a problem in that frequently executed instructions are also evicted from the instruction cache like other instructions.

In the technique described in Patent Document 2, when a task including frequently executed instructions is used as a specific task, the frequently executed instructions can be placed in the cache of a core with a low cache miss rate.

However, the operation of each core is rarely fixed. In other words, the cache miss rate in each core is not fixed and constantly changes.

The technology described in Patent Document 2 requires an operation to move tasks between cores when the cache miss rate changes. This operation is different from instruction execution, and is an operation that reduces the execution efficiency of the processor.

In other words, the technique described in Patent Document 2 has a problem in that the execution efficiency of the processor decreases when the cache miss rate in each core changes.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an information processing device that reduces the number of replacements of predetermined instructions in an instruction cache.

An information processing device in one embodiment of the present invention includes:
a processor that executes instructions;
a first instruction storage means for storing instructions to be executed by the processor;
an execution module comprising: an address storage means for storing a range of addresses for storing instructions to be cached preferentially in the first instruction storage means;
a second instruction storage means for storing copies of instructions stored by the execution module as a cache of instructions executed by the processor;
Entry storage means for storing an entry containing an address of the instruction in the execution module as an address related to the instruction stored by the second instruction storage means;
an instruction cache comprising: a cache control means for determining an instruction to be replaced with a new instruction among instructions to be saved as a copy using an address to be saved by the entry and a range of addresses to be saved by the execution module;

An information processing device according to another embodiment of the present invention includes:
The above information processing device;
When generating an executable module,
an instruction specifying means for specifying an instruction to be preferentially stored in an instruction cache among instructions included in the execution module;
an instruction placement determining means for determining an address in the execution module to place a specified instruction in the execution module;
The method further includes a loader including an instruction embedding means for embedding the specified instruction at the determined address.

An information processing method in one form of the present invention includes:
a processor that executes instructions;
an execution module that stores instructions to be executed by the processor and a range of addresses for storing instructions to be cached preferentially;
In an information processing device including an instruction cache,
The instruction cache stores copies of instructions stored by execution modules as a cache for instructions executed by the processor.
saving an entry containing the address of the instruction in the execution module as an address associated with the saved instruction;
Using the address saved by the entry and the range of addresses saved by the execution module, an instruction to be replaced with a new instruction among the instructions saved as a copy is determined.

A program in one form of the present invention is
In an information processing device including a processor that executes instructions,
Stores the instructions that the processor executes,
Processing as an execution module that stores a range of addresses that store instructions to be cached with priority,
Stores a copy of the instructions stored by the execution module as a cache of instructions executed by the processor,
saving an entry containing the address of the instruction in the execution module as an address associated with the saved instruction;
Using the address stored by the entry and the range of addresses stored by the execution module, an instruction to be replaced with a new instruction is determined from among the instructions to be stored as a copy. Processing as an instruction cache is executed.

According to the present invention, it is possible to reduce the number of replacements of predetermined instructions in the instruction cache.

FIG. 1 is a block diagram showing an example of the configuration of an information processing apparatus according to the first embodiment. FIG. 2 is a diagram illustrating an example of the configuration of an instruction cache. FIG. 3 is a diagram showing an example of the structure of an entry. FIG. 4 is a diagram showing an example of the configuration of an entry compatible with 4-way. FIG. 5 is a diagram for explaining the operation of determining an instruction in the cache control unit. FIG. 6 is a flowchart illustrating an example of an operation of determining a replacement instruction in the cache control unit. FIG. 7 is a diagram showing an example of an area in an execution module. FIG. 8 is a block diagram showing an example of the configuration of an information processing device according to the second embodiment. FIG. 9 is a block diagram showing an example of the hardware configuration of the information processing device.

Next, embodiments of the present invention will be described with reference to the drawings.
Note that each drawing is for explaining an embodiment of the present invention. However, the present invention is not limited to the description in each drawing. Further, similar configurations in each drawing may be designated by the same numbers, and repeated description thereof may be omitted. In addition, in the drawings used in the following explanation, the configuration of portions that are not related to the explanation of the present invention may be omitted and may not be illustrated. Furthermore, the directions of the arrows in the drawings are for illustrative purposes only, and do not limit the direction of signals between blocks.

Note that the instruction used in the following explanation may be a single instruction, or may be an instruction sequence that is a combination of multiple instructions. For example, each embodiment may include a pipeline (also referred to as a way) for multiple instructions. However, in the following description, if there is no need to distinguish the structure of an instruction, it will simply be referred to as an "instruction."

Furthermore, in the following description, an instruction (predetermined instruction) whose replacement is to be reduced in the instruction cache, that is, an instruction that is preferentially cached in the instruction cache is referred to as a "priority instruction." Further, an instruction that is replaced with priority over a priority instruction in the instruction cache is called a "non-priority instruction."

Note that the priority command is arbitrary. For example, a priority instruction is an instruction that is executed more often than a predetermined frequency. Alternatively, priority instructions are instructions that are executed at predetermined intervals.

<First embodiment>
The first embodiment will be described below with reference to the drawings.

[Configuration description]
FIG. 1 is a block diagram showing an example of the configuration of an information processing device 10 according to the first embodiment.

Information processing device 10 includes an instruction cache 100, a loader 103, an execution module 120, and a processor 130.

The execution module 120 is generated on the memory (not shown) of the information processing device 10 and includes instructions to be executed by the processor 130. Execution module 120 may also include other information (eg, data used for execution).

Processor 130 executes instructions contained in execution module 120. At this time, the processor 130 uses the instruction cache 100 as a cache for instructions.

Note that the processor 130 may use another cache (for example, a data cache) in addition to the instruction cache 100.

The loader 103 generates an execution module 120.

The instruction cache 100 caches instructions to be executed by the processor 130 among the instructions of the execution module 120. That is, the instruction cache 100 stores copies of instructions included in the execution module 120 as an instruction cache.

The instruction cache 100 then operates to reduce replacement of priority instructions, as will be explained later.

Next, details of each configuration will be explained with reference to the drawings.

Note that the configuration and operation of the processor 130 are similar to those of a general processor, so a detailed explanation will be omitted.

(Execution module 120)
Execution module 120 includes an address storage section 101 and an instruction storage section 124.

The instruction storage unit 124 stores instructions to be executed by the processor 130. The instruction storage unit 124 shown in FIG. 1 includes a non-priority instruction storage unit 121 and a priority instruction storage unit 122 as an example of a configuration for storing instructions.

The non-priority instruction storage unit 121 stores non-priority instructions.

The priority instruction storage unit 122 stores priority instructions.

The address storage unit 101 stores the address range of the priority instruction storage unit 122.

Note that the address storage section 101 may store the address range of the non-priority instruction storage section 121. In this case, in the following description, the information processing device 10 uses the address range of the priority instruction as the address range of the instruction storage unit 124 excluding the address range stored in the address storage unit 101. It should work using .

In this way, the instruction storage unit 124 stores priority instructions and other instructions (non-priority instructions) in different address ranges.

FIG. 7 is a diagram showing an example of areas in the execution module 120.

The execution module 120 shown in FIG. 7 includes a lower limit address 700, an upper limit address 701, a non-priority instruction area 702, and a priority instruction area 703.

Note that the arrangement of regions and the like in FIG. 7 is an example. The arrangement of areas in the execution module 120 is not limited to that shown in FIG. 7. For example, the lower limit address 700 and the upper limit address 701 may be placed at the highest address.

The priority instruction area 703 is an area for storing priority instructions, that is, instructions that reduce replacement in the instruction cache 100.

The non-priority instruction area 702 is an area for storing other instructions (non-priority instructions).

The lower limit address 700 stores the lower limit address of the priority instruction area 703.

The upper limit address 701 stores the upper limit address of the priority instruction area 703.

The lower limit address 700 and the upper limit address 701 are examples of the address storage section 101.

The non-priority instruction area 702 and the priority instruction area 703 are examples of the instruction storage section 124.

Note that the instruction storage unit 124 may include a plurality of non-priority instruction areas 702 and a plurality of priority instruction areas 703.

Alternatively, the non-priority instruction area 702 and the priority instruction area 703 may be placed at separate addresses in the execution module 120 without being consecutive.

In this way, the execution module 120 may use a predetermined address range in the execution module 120 as the non-priority instruction area 702 and the priority instruction area 703.

Note that the instruction storage unit 124 may include other areas.

Further, the information indicating the range of addresses stored in the address storage unit 101 is not limited to the combination of upper and lower limits of addresses. For example, the address storage unit 101 may store the upper or lower limit of the address and the length or capacity of the range as the address range.

(Loader 103)
The loader 103 generates the execution module 120 according to a predetermined method. The method of generating the execution module 120 is similar to that of a general loader, so a detailed explanation will be omitted.

However, when generating the execution module 120, the loader 103 places priority instructions in a predetermined address range of the execution module 120.

Note that the method by which the loader 103 acquires the address range is arbitrary. For example, the loader 103 may acquire a predetermined address range from the user. Alternatively, the loader 103 may generate the address range according to predetermined rules. For example, the loader 103 may use a range of a predetermined ratio of the capacity of the execution module 120 as the address range.

The loader 103 stores the address range in the address storage unit 101 of the execution module 120.

The configuration related to priority instructions will be explained below.

The loader 103 includes an instruction specifying section 104, an instruction placement determining section 105, and an instruction embedding section 106.

The instruction specifying unit 104 specifies a priority instruction.

The method of specifying a priority instruction in the instruction specifying unit 104 is not limited. For example, the command designation unit 104 may acquire a designation regarding a priority command from a device (not shown) operated by a user. Alternatively, the command designation unit 104 may designate a priority command based on a predetermined rule, the configuration of the information processing device 10, or the content of execution in the execution module 120.

The instruction placement determining unit 105 determines an address at which an instruction included in the execution module 120 is placed. More specifically, for example, the instruction placement determining unit 105 determines the address of the priority instruction so that it is placed in the priority instruction storage unit 122 of the execution module 120. Furthermore, the instruction placement determining unit 105 determines addresses for non-priority instructions so that they are placed in the non-priority instruction storage unit 121 of the execution module 120. For example, the instruction placement determining unit 105 uses the lower limit address 700 and upper limit address 701 shown in FIG. 7 to determine the address where the instruction is placed.

The instruction embedding unit 106 embeds the instruction in the address of the execution module 120 determined by the instruction placement determining unit 105.

The loader 103 configured as described above embeds the priority instruction in the address range of the priority instruction storage section 122 in the execution module 120.

As a result of the above-described operation of the loader 103, the instruction cache 100 can determine whether the instruction is a priority instruction using the address of the instruction in the execution module 120, as will be explained later. Then, the instruction cache 100 can implement an operation such as leaving the priority instruction in the instruction cache 100 using the result of the determination.

(Instruction cache 100)
Instruction cache 100 includes a cache control section 102, an instruction storage section 111, and an entry storage section 112.

The cache control unit 102 controls each component in the instruction cache 100 to realize caching of instructions executed by the processor 130.

The instruction storage unit 111 is controlled by the cache control unit 102 and stores, as a cache, instructions to be executed by the processor 130 among the instructions included in the execution module 120.

Note that the instructions stored in the instruction cache 100 are the instructions stored in the execution module 120. Therefore, the instructions stored by the instruction cache 100 are also copies of the instructions stored by the execution module 120.

The entry storage unit 112 stores information (hereinafter referred to as “entry”) related to the address of the instruction (cached instruction) stored in the instruction storage unit 111. Entries will be explained later.

In the following description, it is assumed that the instruction cache 100 stores a plurality of instructions.

Note that the instruction cache 100 may store, as a cache, an instruction string (command array) including a plurality of instructions.

FIG. 2 is a diagram showing an example of the configuration of the instruction cache 100. Note that FIG. 2 is an example in which an instruction string (command array) is used as the instruction.

Instruction cache 100 shown in FIG. 2 includes a cache controller 200, an address array 201, and a data array 202.

The cache control unit 200 corresponds to the cache control unit 102 in FIG.

The address array 201 is an example of the entry storage unit 112 and stores information (entries) related to addresses of instructions stored in the instruction cache 100.

The data array 202 is an example of the instruction storage unit 111, and serves as a cache for storing instructions to be executed by the processor 130.

FIG. 3 is a diagram showing an example of the configuration of the entry 310.

Entry 310 includes address 300, Valid bit 301, and Priority bit 302.

Address 300 stores the address of the instruction corresponding to entry 310 (the address located in execution module 120). Note that the address 300 may store other addresses (eg, the address of the corresponding instruction in the data array 202).

Valid bit 301 is information indicating whether or not entry 310 is valid.

Entry 310 is valid if entry 310 is associated with an actual instruction. In this case, address 300 stores a valid address. Entry 310 being invalid means that entry 310 is not associated with an instruction.

For example, if Valid bit 301 is "1", entry 310 is valid. If Valid bit 301 is "0", entry 310 is not valid. Note that the Valid bit 301 is not limited to 1-bit information. For example, the Valid bit 301 may be 1 byte of information.

When the cache control unit 102 stores the instruction corresponding to the entry 310 in the instruction storage unit 111, the cache control unit 102 changes the Valid bit 301 to “valid (for example, “1”). Further, when the entry 310 is released, the cache control unit 102 changes the Valid bit 301 to "invalid (for example, "0")".

The Priority bit 302 is information indicating whether the instruction corresponding to the entry 310 is a priority instruction. The Priority bit 302 is also not limited to 1 bit, and may be 1 Byte of information, for example.

When caching an instruction, the cache control unit 102 uses the address in the instruction execution module 120 and the address storage unit 101 to determine whether the instruction is a priority instruction and sets the Priority bit 302. Set. When replacing an instruction, the cache control unit 102 uses the Priority bit 302 to determine whether the instruction corresponding to the entry 310 is a priority instruction.

However, the cache control unit 102 does not need to use the Priority bit 302 in determining whether an instruction is a priority instruction when replacing an instruction. For example, when replacing an instruction, the cache control unit 102 may determine the instruction to be replaced using the address in the execution module 120 of the instruction corresponding to the entry and the address storage unit 101. In this case, entry 310 may not include Priority bit 302.

Note that in FIG. 3, the Valid bit 301 is represented by "V", and the Priority bit 302 is represented by "P".

The address array 201 (that is, the entry storage unit 112) may store instructions corresponding to a plurality of ways.

FIG. 4 is a diagram showing an example of the configuration of an entry 414 that supports 4-way.

FIG. 4 shows a 4-way instruction as an example. However, the number of ways in this embodiment is not limited to four, and may be less than four, or may be five or more.

Entry 414 shown in FIG. 4 includes four entries that correspond to entry 310 shown in FIG.

The first entry is a way0 entry and includes an address 400, a Valid bit 401, and a Priority bit 402.

The second entry is a way 1 entry, and includes an address 403, a Valid bit 404, and a Priority bit 405.

The third entry is a way2 entry and includes an address 406, a Valid bit 407, and a Priority bit 408.

The fourth entry is a way3 entry and includes an address 409, a Valid bit 410, and a Priority bit 411.

Additionally, the entries 414 shown in FIG. 4 include non-priority entries 412 and priority entries 413.

The non-priority entry 412 stores information indicating an entry related to the non-priority instruction (for example, the value of the way of the entry related to the non-priority instruction).

The priority entry 413 stores information indicating an entry related to the priority instruction (for example, the value of a way related to the priority instruction).

Note that the entry 414 may include other information. Furthermore, the entry 414 may not include some of the above.

If the entry 414 includes a non-priority entry 412, the cache control unit 102 can use the non-priority entry 412 to determine whether there is an entry corresponding to the non-priority instruction. Note that the cache control unit 102 may determine an entry not included in the priority entry 413 as an entry corresponding to a non-priority instruction.

In this way, the cache control unit 102 may operate using either the non-priority entry 412 or the priority entry 413. Therefore, the entry 414 does not have to include either the non-priority entry 412 or the priority entry 413.

Note that an entry that is not included in either the non-priority entry 412 or the priority entry 413 is an empty entry. Therefore, the cache control unit 102 may use the non-priority entry 412 and the priority entry 413 to determine an empty entry. In this case, entry 414 may not include Valid bits 401, 404, 407, and 410.

Note that the cache control unit 102 may use the Priority bits 402, 405, 408, and 411 to set information in the non-priority entry 412 and the priority entry 413.

However, the cache control unit 102 may set the non-priority entry 412 and the priority entry 413 using the address in the execution module 120 of the instruction corresponding to each entry and the address storage unit 101. In this case, entry 414 may not include Priority bits 402, 405, 408, and 411.

FIG. 5 is a diagram for explaining the operation of determining an instruction in the cache control unit 102.

The operation of the cache control unit 102 shown in FIG. 5 is an example of the operation when using the execution module 120 shown in FIG. 7, more specifically, when using the lower limit address 500 and the upper limit address 501. .

Note that the cache control unit 102 may use the lower limit address 700 and upper limit address 701 stored by the execution module 120 as the lower limit address 500 and the upper limit address 501. Alternatively, the cache control unit 102 may store copies of the lower limit address 700 and the upper limit address 701 stored by the execution module 120 in the cache control unit 102.

First, the cache control unit 102 compares the address of the instruction (specifically, the address included in the entry corresponding to the instruction) with the lower limit address 500 and the upper limit address 501.

Note that the cache control unit 102 may include a comparator 503, and use the comparator 503 to compare addresses. Alternatively, the cache control unit 102 may compare the addresses as a software process.

If the address of the instruction is included in the range of the lower limit address 500 and the upper limit address 501, the cache control unit 102 determines that the instruction is a priority instruction (an instruction to be preferentially left in the instruction cache 100).

If the address of the instruction is not included in the range of the lower limit address 500 and the upper limit address 501, the cache control unit 102 determines that the instruction is a non-priority instruction (an instruction that is not preferentially left in the instruction cache 100).

FIG. 6 is a flow diagram illustrating an example of an operation in which the cache control unit 102 determines an instruction to be replaced. Instruction replacement occurs when the instruction to be executed by the processor 130 is not in the instruction cache 100 (in the case of a cache miss). Note that determination of a cache miss and the like are similar to those of a general cache, so a detailed explanation will be omitted.

When adding a new instruction such as a cache miss instruction to the cache, the cache control unit 102 performs the operations described below.

First, the cache control unit 102 determines whether there is an empty entry (unused entry) (step S801). For example, the cache control unit 102 may use the Valid bit 301 shown in FIG. 3 or the Valid bits 401, 404, 407, and 410 shown in FIG. 4 to determine an empty entry.

If there is an empty entry (Yes in step S801), the cache control unit 102 uses the empty entry as an entry for a new instruction (step S803). In other words, the cache control unit 102 caches new instructions using empty entries.

If there is no empty entry (No in step S801), the cache control unit 102 determines whether there is an entry corresponding to a non-priority instruction (step S805). For example, the cache control unit 102 may make the determination using the Priority bit 302 shown in FIG. 3 or the non-priority entry 412 shown in FIG. 4.

For example, if the non-priority entry 412 stores a way number, the cache control unit 102 determines that there is an entry corresponding to the non-priority instruction. If the non-priority entry 412 does not store a way number or stores a non-existent way number, the cache control unit 102 determines that there is no entry corresponding to the non-priority instruction.

If there is an entry corresponding to a non-priority instruction (Yes in step S805), the cache control unit 102 selects one of the entries and replaces the instruction corresponding to the selected entry with a new instruction ( Step S807). For example, the cache control unit 102 replaces the instruction corresponding to the entry with the way number stored in the non-priority entry 412 with the new instruction. Note that if there are multiple non-priority entries, the cache control unit 102 selects an entry according to a predetermined rule.

If there is no entry related to the non-priority instruction (No in step S805), the cache control unit 102 selects a replacement entry from the entries related to the priority instruction according to a predetermined rule. Then, the cache control unit 102 replaces the instruction related to the selected entry with the new instruction (step S809). For example, the cache control unit 102 selects one entry from the entries with the way number stored in the priority entry 413.

Note that the predetermined rule used for selecting entries is arbitrary. For example, the predetermined rule may be Least Recently Used (LRU) or Least Frequency Used (LFU).

In this way, if there is an empty entry, the information processing device 10 uses the empty entry as the entry for the new command. If there is no empty entry and there are entries corresponding to the priority instruction and entries corresponding to the non-priority instruction, the information processing device 10 responds to the non-priority instruction as a new instruction entry based on the above operation. Select an entry. Therefore, based on the above operation, the information processing device 10 can leave priority instructions in the instruction cache 100 more than non-priority instructions.

Based on such operations, the information processing device 10 reduces the number of replacements of predetermined instructions (for example, frequently used instructions) in the instruction cache 100.

[Explanation of effects]
Next, the effects of the information processing device 10 according to the first embodiment will be explained.

The information processing device 10 according to the first embodiment can obtain the effect of reducing replacement of a predetermined instruction (for example, a priority instruction) in the instruction cache 100.

The reason is as follows.

Information processing device 10 includes a processor 130, an instruction cache 100, and an execution module 120. Processor 130 executes instructions. The execution module 120 includes an instruction storage section 124 (first instruction storage section) and an address storage section 101. The instruction storage unit 124 stores instructions to be executed by the processor 130. The address storage unit 101 stores a range of addresses in which instructions to be cached preferentially are stored in the instruction storage unit 124 . The instruction cache 100 includes an instruction storage section 111 (second instruction storage section), an entry storage section 112, and a cache control section 102. The instruction storage unit 111 stores copies of instructions stored by the execution module 120 as a cache of instructions executed by the processor 130. The entry storage unit 112 stores an entry 310 that includes the address of the instruction in the execution module 120 as an address related to the instruction stored in the instruction storage unit 111. The cache control unit 102 uses the address stored in the entry 310 and the range of addresses stored in the execution module 120 to determine which instruction to be replaced with a new instruction among the instructions stored as copies.

As described above, the execution module 120 stores instructions to be preferentially stored in the cache in the address range stored in the address storage unit 101.

Therefore, the instruction cache 100 can use the address of the instruction in the execution module 120 to determine whether the instruction being cached is an instruction to be cached preferentially. Then, the instruction cache 100 uses the determination result to perform instruction replacement so as to leave instructions to be cached preferentially.

Therefore, the information processing device 10 configured in this manner can have the effect of reducing replacement of a predetermined instruction in the instruction cache 100 by using the configuration of the instruction cache 100 and the execution module 120.

Furthermore, the information processing device 10 includes a loader 103.

The loader 103 includes an instruction specifying section 104, an instruction placement determining section 105, and an instruction embedding section 106. When generating the execution module 120, the instruction specifying unit 104 specifies an instruction (priority instruction) to be preferentially stored in the instruction cache 100 among the instructions included in the execution module 120. The instruction placement determining unit 105 determines an address in the execution module 120 at which the designated instruction is placed in the execution module 120. The instruction embedding unit 106 embeds the specified instruction in the determined address.

The loader 103 configured in this manner can generate the execution module 120 so that the instruction cache 100 can realize the above operations.

In this way, the information processing device 10 according to the first embodiment reduces the number of replacements of predetermined instructions (for example, frequently executed instructions) in the instruction cache 100. In other words, the information processing device 10 according to the first embodiment can solve the problems in Patent Document 1.

Further, the information processing device 10 according to the first embodiment does not require movement between cores. Therefore, the information processing device 10 according to the first embodiment can solve the problems in the technique described in Patent Document 2, and can also have the effect of reducing the decrease in execution efficiency of the processor 130.

<Second embodiment>
Note that the instruction cache 100, loader 103, and execution module 120 do not need to be included in the same device. For example, the loader 103 may be provided in a device different from the information processing device 10.

Alternatively, after generating the execution module 120, the loader 103 may be deleted.

Next, a second embodiment will be described with reference to the drawings.

[Configuration description]
FIG. 8 is a block diagram showing an example of the configuration of the information processing device 11 according to the second embodiment.

Information processing device 11 includes a processor 130, an instruction cache 100, and an execution module 120.

Processor 130 executes instructions.

The execution module 120 is generated using a configuration similar to that of the loader 103 (not shown).

The execution module 120 includes an address storage section 101 and an instruction storage section 124 (first instruction storage section).

The instruction storage unit 124 stores instructions.

The address storage unit 101 stores a range of addresses in which priority instructions are stored among the instructions stored in the instruction storage unit 124.

Instruction cache 100 includes an instruction storage section 111, an entry storage section 112, and a cache control section 102.

The instruction storage unit 111 stores copies of instructions as a cache of instructions.

The entry storage unit 112 stores an entry 310 that includes the address of the instruction stored in the instruction storage unit 111.

The cache control unit 102 can use the address storage unit 101 to determine whether the instruction stored in the instruction storage unit 124 is a priority instruction.

Further, even when the instruction cache 100 replaces an instruction, the cache control unit 102 can use the address storage unit 101 and the entry storage unit 112 to select a non-priority instruction as the instruction to be replaced.

[Explanation of effects]
The information processing device 11 according to the second embodiment configured in this way can achieve the same effects as the information processing device 11 according to the first embodiment.

The reason is as follows.

Information processing device 11 includes a processor 130, an instruction cache 100, and an execution module 120. Processor 130 executes instructions. The execution module 120 includes an instruction storage section 124 (first instruction storage section) and an address storage section 101. The instruction storage unit 124 stores instructions to be executed by the processor 130. The address storage unit 101 stores a range of addresses in which instructions to be cached preferentially are stored in the instruction storage unit 124 . The instruction cache 100 includes an instruction storage section 111 (second instruction storage section), an entry storage section 112, and a cache control section 102. The instruction storage unit 111 stores copies of instructions stored by the execution module 120 as a cache of instructions executed by the processor 130. The entry storage unit 112 stores an entry 310 that includes the address of the instruction in the execution module 120 as an address related to the instruction stored in the instruction storage unit 111. The cache control unit 102 uses the address stored in the entry 310 and the range of addresses stored in the execution module 120 to determine which instruction to be replaced with a new instruction among the instructions stored as copies.

In this way, the configurations included in the instruction cache 100 and execution module 120 included in the information processing device 11 realize the same functions as the corresponding configurations in the first embodiment. Therefore, the information processing device 11 according to the second embodiment can achieve the same effects as the information processing device 10 according to the first embodiment.

Note that the information processing device 11 is also the minimum configuration in the first embodiment.

[Hardware configuration]
Next, the hardware configurations of the information processing devices 10 and 11 will be explained using the information processing device 10.

Each component of the information processing device 10 may be configured with a hardware circuit.

Alternatively, in the information processing device 10, each component may be configured using a plurality of devices connected via a network.

Alternatively, in the information processing device 10, the plurality of components may be configured by one piece of hardware.

Alternatively, the information processing device 10 may be realized as a computer device including a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). In addition to the above configuration, the information processing device 10 may be realized as a computer device that further includes an input and output connection circuit (IOC). In addition to the above configuration, the information processing device 10 may be realized as a computer device that further includes a network interface circuit (NIC).

FIG. 9 is a block diagram showing an example of the hardware configuration of the information processing device 10. As shown in FIG. Note that FIG. 9 shows an information processing device 600 as an example of hardware of the information processing device 10.

The information processing device 600 includes a CPU 610, a ROM 620, a RAM 630, an internal storage device 640, an IOC 650, and an NIC 680, and constitutes a computer device.

CPU 610 reads programs from ROM 620 and/or internal storage device 640. Then, the CPU 610 controls the RAM 630, internal storage device 640, IOC 650, and NIC 680 based on the read program. The computer including the CPU 610 controls these configurations and realizes the functions of the processor 130, instruction cache 100, loader 103, and execution module 120 shown in FIG.

CPU 610 is an example of processor 130.

The CPU 610 may use the RAM 630 or the internal storage device 640 as a temporary storage medium for programs when implementing each function.

Further, the CPU 610 may read a program included in a storage medium 690 that stores the program in a computer-readable manner using a storage medium reading device (not shown). Alternatively, the CPU 610 may receive a program from an external device (not shown) via the NIC 680, store it in the RAM 630 or the internal storage device 640, and operate based on the stored program.

Although not shown, the CPU 610 may include a built-in memory. In this case, the built-in memory may operate as the instruction cache 100.

The ROM 620 stores programs executed by the CPU 610 and fixed data. The ROM 620 is, for example, a P-ROM (Programmable-ROM) or a flash ROM.

The RAM 630 temporarily stores programs and data executed by the CPU 610. The RAM 630 is, for example, D-RAM (Dynamic-RAM).

Note that the RAM 630 may store the execution module 120.

Furthermore, RAM 630 may include multiple memories with different access performance. In this case, a memory with high access performance may operate as the instruction cache 100.

The internal storage device 640 stores data and programs that the information processing device 600 stores for a long time. Further, the internal storage device 640 may operate as a temporary storage device for the CPU 610. The internal storage device 640 is, for example, a hard disk device, a magneto-optical disk device, an SSD (Solid State Drive), or a disk array device.

Note that the internal storage device 640 may store the execution module 120.

The ROM 620 and the internal storage device 640 are non-transitory storage media. On the other hand, the RAM 630 is a volatile storage medium. The CPU 610 can operate based on programs stored in the ROM 620, internal storage device 640, or RAM 630. That is, the CPU 610 can operate using a nonvolatile storage medium or a volatile storage medium.

The IOC 650 mediates data between the CPU 610 and external devices. FIG. 9 shows an input device 660 and a display device 670 as an example of an external device. The IOC 650 is, for example, an IO interface card or a USB (Universal Serial Bus) card. Furthermore, the IOC 650 is not limited to a wired one such as a USB, but may also be a wireless one.

The input device 660 is a device that receives input instructions from the operator of the information processing device 600. Input device 660 is, for example, a keyboard, a mouse, or a touch panel.

The display device 670 is a device that displays information to the operator of the information processing device 600. Display device 670 is, for example, a liquid crystal display, an organic electroluminescent display, or electronic paper.

The NIC 680 relays data exchange with an external device (not shown) via the network. The NIC 680 is, for example, a LAN (Local Area Network) card. Furthermore, the NIC 680 is not limited to a wired one, and may be a wireless one.

The information processing device 600 configured in this manner can obtain the same effects as the information processing device 10.

The reason is that the CPU 610 of the information processing device 600 can implement the same functions as the information processing device 10 based on the program.

Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. The configuration and details of the present invention can be modified in various ways that can be understood by those skilled in the art within the scope of the present invention.

10 Information processing device 11 Information processing device 100 Instruction cache 101 Address storage unit 102 Cache control unit 103 Loader 104 Instruction specification unit 105 Instruction placement determination unit 106 Instruction embedding unit 111 Instruction storage unit 112 Entry storage unit 120 Execution module 121 Non-priority instruction storage Section 122 Priority instruction storage section 124 Instruction storage section 130 Processor 200 Cache control section 201 Address array 202 Data array 300 Address 301 Valid bit 302 Priority bit 310 Entry 400 Address 401 Valid bit 402 Priority bit 403 Address 404 V alid bit 405 Priority bit 406 Address 407 Valid bit 408 Priority bit 409 Address 410 Valid bit 411 Priority bit 412 Non-priority entry 413 Priority entry 414 Entry 500 Lower limit address 501 Upper limit address 503 Comparator 600 Information processing device 610 CPU
620 ROM
630 RAM
640 Internal storage device 650 IOC
660 Input device 670 Display device 680 NIC
690 Storage medium 700 Lower limit address 701 Upper limit address 702 Non-priority instruction area 703 Priority instruction area

Claims (8)

a processor that executes instructions;
generated in memory by the loader,
When generated,
a first instruction storage means for storing instructions to be executed by the processor;
an execution module generated to include, in the first instruction storage means, an address storage means for storing a range of addresses for storing instructions to be preferentially cached;
a second instruction storage means for storing copies of instructions stored by the execution module as a cache of instructions executed by the processor;
Entry storage means for storing an entry including an address of the instruction in the execution module as an address related to the instruction stored by the second instruction storage means;
an instruction cache comprising: a cache control means for determining an instruction to be replaced with a new instruction among instructions to be saved as a copy using an address to be saved by an entry and a range of addresses to be saved by the execution module; Information processing device. The cache control means,
If there is an entry unrelated to the instruction among the entries stored by the entry storage means, the entry unrelated to the instruction is determined as an entry of a new instruction;
Information processing according to claim 1, wherein if there is no entry unrelated to the instruction, an instruction related to an entry including an address that is not included in the range of addresses stored by the address storage means is determined to be an instruction to be replaced with a new instruction. Device. The entry is
Contains information indicating whether the entry is valid or not,
The information processing apparatus according to claim 2, wherein the cache control means determines whether an entry is related to an instruction using information as to whether the entry is valid or not. When the cache control means copies an instruction to the second instruction storage means, the instruction to be copied is given priority by using the address of the instruction in the execution module and the range of addresses stored in the address storage means. Determine whether the instruction is to be cached in
Save the judgment result in the entry,
The information processing apparatus according to any one of claims 1 to 3, wherein a replacement instruction is determined using a determination result stored in an entry. The address storage means,
The information processing apparatus according to any one of claims 1 to 4, wherein a lower limit address and an upper limit address of the address range are stored as the address range. further comprising the loader;
The loader is
When generating the execution module,
an instruction specifying means for specifying an instruction to be preferentially stored in the instruction cache among instructions included in the execution module;
In the execution module, an instruction placement determining unit that determines an address in the first instruction storage unit of the execution module where a designated instruction is to be placed, and stores the determined address in the address storage unit ;
an instruction embedding means for embedding a specified instruction in the determined address of the first instruction storage means;
including
The information processing device according to any one of claims 1 to 5 . a processor that executes instructions;
an execution module that is generated in a memory by a loader and that, when generated, stores instructions to be executed by the processor and a range of addresses that store instructions to be cached preferentially;
In an information processing device including an instruction cache,
the instruction cache stores copies of instructions stored by the execution module as a cache for instructions executed by the processor;
saving an entry containing an address of the instruction in the execution module as an address associated with the saved instruction;
An information processing method in which an instruction to be replaced with a new instruction among instructions to be saved as a copy is determined using an address saved by an entry and a range of addresses saved by the execution module. In an information processing device including a processor that executes instructions,
generated in memory by the loader,
When generated,
storing instructions to be executed by the processor;
Now saves a range of addresses for saving instructions to be cached preferentially
Processing to generate an executable module,
storing a copy of the instructions stored by the execution module as a cache of instructions executed by the processor;
saving an entry containing an address of the instruction in the execution module as an address associated with the saved instruction;
A program that executes processing as an instruction cache: determining an instruction to be replaced with a new instruction among instructions to be saved as a copy, using an address saved by an entry and a range of addresses saved by the execution module.

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