JP7338045B2 - Light Emitting Diode and Method of Forming Light Emitting Diode - Google Patents

Description

FIELD OF THE DISCLOSURE The present disclosure relates to III-nitride semiconductors. In particular, the present disclosure relates to light emitting diodes (LEDs) comprising III-nitride semiconductors.

Background A micro-LED array is generally defined as an array of LEDs having a size of 100×100 μm ² or less. Micro LED arrays are self-illuminating components within microdisplays/projectors suitable for use in a variety of devices such as smartwatches, headwear displays, heads-up displays, camcorders, viewfinders, multi-site excitation sources, and picoprojectors. .

One type of micro-LED array comprises a plurality of LEDs formed from group III-nitrides. III-nitride LEDs, for example, are inorganic semiconductor LEDs comprising GaN and its alloys with InN and AlN in the active light emitting region. III-nitride LEDs can be driven at significantly higher current densities and emit higher optical power densities than conventional large-area LEDs, such as organic light-emitting diodes (OLEDs), whose light-emitting layers are organic compounds. can. As a result, the higher luminance (brightness), defined as the amount of light emitted per unit area of the light source in a given direction, makes micro-LEDs suitable for applications requiring or benefiting from high brightness. make it suitable. For example, applications that benefit from high brightness may include displays or projectors in high brightness environments. In addition, III-nitride micro-LED arrays are known to have relatively high luminous efficiency, expressed in lumens per watt (lm/W), compared to other conventional large-area LEDs. The relatively high luminous efficiency of III-nitride micro-LED arrays reduces power usage compared to other light sources, making micro-LEDs particularly suitable for portable devices.

One method for forming micro-LEDs, particularly micro-LED arrays, from III-nitrides is selective area growth (SAG) as described in US Pat. No. 7,087,932. In the selective area growth technique, a mask is patterned on the buffer layer. The material in the mask is such that the growth conditions are such that the additional material does not grow directly on the mask, but only inside the openings that expose a portion of the surface of the underlying buffer layer.

Another notable feature of selective area growth of III-nitrides grown along the direction is also known as the c-plane (0001 ) facets are obtained around the perimeter of the c-plane semiconductor growth defined by the open areas of the patterned mask. Slanted facets are commonly found in wurtzite crystals.

, exhibiting a reduced polarization field compared to the c-plane (semipolar plane).
It is an object of the present invention to provide an improved method for forming LED precursors and improved LED precursors that address at least one of the problems associated with prior art methods and arrays, or at least commercial products thereof. to provide a useful alternative to

SUMMARY OF THE DISCLOSURE The inventors have recognized that the SAG method is highly dependent on the geometry of the layers/devices being fabricated. Therefore, performing the same SAG fabrication process on substrates with different mask geometries can result in undesirable local variations in doping profiles and layer compositions due to local variations in aperture size. Additionally, there may be variations in doping profiles and layer compositions across different substrates due to layout differences. That is, the doping profile/alloy composition of each layer of an LED device formed by SAG can depend on the geometry of the device. As a result, slight changes in the geometry of the device or array of devices may require the SAG process for each layer of the device to be recalibrated.

Additionally, the inventors have recognized that during the SAG process, material from the mask layer can be incorporated into the deposited structure. For example, elements in the masking layer can diffuse into the SAG-grown material during fabrication, resulting in undesirable doping of the grown LED structure. In particular, masking layers containing Si or O (eg, SiN _x , SiO ₂ ) can provide sources of Si or O dopants for III-nitride layers grown by SAG.

According to a first aspect of the present disclosure, a method of forming a light emitting diode precursor is provided. The method is
(a) forming a first semiconductor layer comprising a III-nitride on a substrate, the first semiconductor layer having a growth surface opposite the first semiconductor layer with respect to the substrate; forming a first semiconductor layer;
(b) selectively removing portions of the first semiconductor layer to form a mesa structure such that the growth surface of the first semiconductor layer comprises a mesa surface and a bulk semiconductor layer surface;
(c) forming a monolithic LED structure on the growth surface of the first semiconductor layer overlying the mesa surface and the bulk semiconductor surface, the monolithic LED structure comprising a plurality of layers, each layer comprising a Group III nitride; comprising a plurality of layers,
a second semiconductor layer;
forming a monolithic LED structure comprising: an active layer overlying a second semiconductor layer, the active layer being configured to generate light; and a p-type semiconductor layer overlying the active layer. wherein a potential barrier is provided between a first portion of the p-type semiconductor layer overlying the mesa surface and a second portion of the p-type semiconductor layer overlying the bulk semiconductor surface, the potential barrier comprising , surrounds a first portion of the p-type semiconductor layer overlying the mesa surface.

In the SAG method, a monolithic LED structure can be grown on exposed portions of the buffer layer. A monolithic LED structure is not grown on the portion of the buffer layer covered by the mask layer. In the method of the first aspect, a monolithic LED structure is overgrown on a substrate without the presence of a mask layer. Therefore, the method of manufacturing monolithic LED structures is a maskless overgrowth method. This forms a monolithic LED structure on the growth surface of the first semiconductor layer. Thus, the layers of the monolithic LED structure are formed on the growth surface overlying the mesa surface and the bulk semiconductor surface of the first semiconductor layer.

The mesa structure formed on the growth surface helps define the geometry of the monolithic LED structure. Thus, in contrast to known SAG methods, no masking layer is required to define openings for selective growth of LED structures. Rather, a monolithic LED structure is grown over the growth surface overlying the mesa structure. By covering the mesa structure, the monolithic LED structure formed can have slanted facets similar to monolithic LED structures grown by SAG methods known in the art.

Advantageously, the method of the first aspect allows monolithic LED structures to be formed on a growth surface without the presence of masking layers. Accordingly, the method of the first aspect reduces or eliminates problems associated with material recycling and mask layer contamination.

It will be appreciated that the method of the first aspect results in a monolithic LED structure having a substantially flat top surface surrounded by sloped sidewalls. Thus, a monolithic LED structure can have a substantially trapezoidal cross-section. Such a trapezoidal cross-section can enhance light extraction efficiency because the sloping sidewalls of the trapezoidal cross-section can direct a greater proportion of the light toward the emitting surface of the LED precursor.

Additionally, the method of the first aspect includes forming layers of the monolithic LED structure over the entire growth surface, including the mesa surface and the bulk semiconductor surface. The layers of the monolithic LED structure can be formed using manufacturing processes similar to SAG. However, in the method of the first aspect, the layers of the monolithic LED structure are formed over the entire growth surface (ie, no mask layers are present). Formation of the layers of a monolithic LED structure is therefore less sensitive to variations in the geometry of the formed LED precursor. As a result, the method of forming LED precursors can reduce or eliminate calibration processes performed to form layers of monolithic LED precursors each time the geometry of the device is changed.

In particular, in the method of the first aspect, the geometry of the LED precursor can be influenced by the geometry of the mesa structure formed. For example, when forming an LED precursor having a trapezoidal cross-section, the height and surface area of the mesa structure can be varied to control the desired height and surface area of the formed LED precursor. Therefore, the aspect ratio of the formed LED precursor can be adjusted using selective removal steps. Subsequent steps in which a monolithic LED structure is deposited over the mesa structure can be kept constant regardless of the aspect ratio of the LED precursor. In contrast, in the SAG process, changing the aspect ratio of the trapezoidal cross-section of the LED structure may require recalibrating one or more of the deposition steps.

It will be appreciated that unlike SAG technology, monolithic LED structures are grown over the entire growth surface, including the entire bulk semiconductor layer surface. A potential barrier is provided in the p-type layer of the monolithic LED structure to confine the charge carriers within the portion of the monolithic LED structure defined by the mesa structure. The p-type layer includes a first portion of the p-type semiconductor layer overlying the mesa surface to confine charge carriers flowing through the first portion of the p-type layer (i.e., confine the charge carriers within the mesa structure). It is provided between the second portion of the p-type semiconductor layer covering the bulk semiconductor surface.

Note that with the term "precursor" in LED precursors, the LED precursors being described do not necessarily include the LED's electrical contacts or associated circuitry that enable light emission. Of course, the method of forming the LED precursor of the first aspect does not exclude the addition of additional electrical contacts and associated circuitry. Accordingly, use of the term precursor in this disclosure is intended to include the final product (ie, LED, LED array, etc.).

In some embodiments, the first semiconductor layer may be an n-type doped semiconductor layer. That is, the first semiconductor layer may include an electron donor dopant.

In some embodiments, the second semiconductor layer may be an n-type doped semiconductor layer. In some embodiments in which the first semiconductor layer comprises an n-type doped semiconductor layer, the second semiconductor layer may contain a lower density of electron donors.

Alternatively, in some embodiments, the second semiconductor layer comprises undoped Group III-nitrides. By providing the second semiconductor layer as an undoped layer (i.e., containing no intentional doping) (or having a lower charge carrier density), the resistivity of the resulting monolithic LED structure is reduced to that of the LED structure. It can be increased in the sidewall region. Therefore, charge carriers can be more effectively confined within the mesa structure and through multiple layers provided on the mesa surface, thereby increasing the efficiency of the LED.

In some embodiments, the second semiconductor layer is formed on the growth surface to form a portion of the second semiconductor layer on the mesa surface of the first semiconductor layer and a bulk semiconductor surface of the first semiconductor layer. Provide sloped sidewalls extending between and a portion of the second semiconductor layer above. Thus, a second semiconductor layer is overgrown on the mesa structure of the first semiconductor layer to provide a III-nitride layer with a mesa surface and surrounded by sloped sidewalls on which the active layers of the LED can be formed. A semiconductor layer can be provided. Importantly, this structure can be formed without the presence of a mask layer.

In some embodiments, the active layer is configured to generate light of the first wavelength. For example, the active layer may be configured to generate light having a wavelength of at least 400 nm. Accordingly, the active layer is capable of producing visible light suitable for use in LED displays. In some embodiments, the active layer is capable of producing light having wavelengths of 700 nm or less. In some embodiments, the active layer may comprise multiple quantum wells (multi-quantum well layer).

According to embodiments of the present disclosure, a potential barrier within the p-type layer for confining charge carriers within the mesa structure can be provided in several ways.

In some embodiments, the p-type semiconductor layer comprises Al and the mesa surface is Al having a higher concentration than that of the first portion of the p-type semiconductor layer covering is incorporated into the sidewall portion of the p-type semiconductor layer.

In some embodiments, a portion of the p-type semiconductor layer surrounding the first portion of the p-type semiconductor layer overlying the mesa structure is selectively removed. For example, a portion of the p-type semiconductor layer may be selectively removed by etching. In some embodiments, the portion of the p-type semiconductor layer surrounding the mesa structure that is selectively removed may only partially penetrate the thickness of the p-type semiconductor layer. Thus, the remaining portion of the p-type semiconductor layer can include relatively thin sections with higher resistance, thereby providing potential barriers. In some embodiments, the portion of the p-type semiconductor layer surrounding the mesa structure that is selectively removed may extend at least through the thickness of the p-type semiconductor layer. Thus, the potential barriers formed may be defined by the resulting air gaps, or the air gaps may subsequently be filled with an insulating material.

According to a second aspect of the disclosure, a method of forming an LED array precursor is provided. The method is
(a) forming a first semiconductor layer comprising a III-nitride on a substrate, the first semiconductor layer having a growth surface opposite the first semiconductor layer with respect to the substrate; forming a first semiconductor layer;
(b) selectively removing portions of the first semiconductor layer to form a plurality of mesa structures such that the growth surface of the first semiconductor layer comprises a plurality of mesa surfaces and bulk semiconductor layer surfaces;
(c) forming a monolithic LED array structure on the growth surface of the first semiconductor layer overlying the mesa surface and the bulk semiconductor surface, the monolithic LED array structure comprising a plurality of layers, each layer III a group nitride, the plurality of layers comprising:
n-type semiconductor layer,
Forming a monolithic LED array structure comprising: an active layer overlying an n-type semiconductor layer, the active layer being configured to generate light; and a p-type semiconductor layer overlying the active layer. wherein a potential barrier is provided between a first portion of the p-type semiconductor layer overlying each mesa surface and a bulk portion of the p-type semiconductor layer overlying the bulk semiconductor surface, the potential barrier comprising: A p-type semiconductor layer covering the mesa surface surrounds each mesa portion.

A method according to the second aspect of the disclosure provides a method of forming a plurality of monolithic LED structures on a substrate, each monolithic structure formed being formed by the method of the first aspect of the disclosure. is similar to The method according to the second aspect can therefore include all the important features mentioned above with respect to the first aspect.

Array means that a plurality of LEDs are formed, the LEDs intentionally spaced throughout the monolithic structure, typically in a regular such as a hexagonally close-packed or square-packed array of LEDs. Form an array.

According to a third aspect of the disclosure, an LED precursor is provided. The LED precursor comprises a first semiconductor layer and a monolithic LED structure. The first semiconductor layer comprises a III-nitride, the first semiconductor layer having a mesa structure extending from a major surface of the first semiconductor layer to define a growth surface including a bulk semiconductor surface and a mesa surface. include. A monolithic LED structure is provided on the growth surface of the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the bulk semiconductor surface. The monolithic LED structure comprises a plurality of layers, each layer comprising a III-nitride, the plurality of layers comprising an n-type semiconductor layer, an active layer overlying the n-type semiconductor layer and configured to generate light; and a p-type semiconductor layer provided on the active layer. A potential barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface, the potential barrier being p surrounds the first portion of the semiconductor layer.

An LED precursor according to the third aspect provides an LED precursor that can be formed by the method of the first aspect. Thus, an LED precursor according to the third aspect can incorporate features corresponding to all of the important features of the first aspect described above.

In some embodiments, the height of the mesa structure (perpendicular to bulk semiconductor surface 26) is greater than or equal to the cross-sectional width of the mesa surface. That is, in at least one plane perpendicular to bulk semiconductor surface 26, the height of the mesa structure is greater than or equal to the cross-sectional width of the mesa surface. Therefore, the height of the mesa structure relative to the cross-sectional width of the mesa structure can provide an LED precursor with an optimized aspect ratio to enhance light extraction efficiency from the LED.

According to a fourth aspect of the present disclosure, an LED array precursor is provided. A light emitting diode array precursor comprises a first semiconductor layer and a monolithic LED array structure. The first semiconductor layer comprises a III-nitride, the first semiconductor layer including a plurality of mesa structures, each mesa structure first grown to define a growth surface including a bulk semiconductor surface and a plurality of mesa surfaces. It extends from the major surface of the first semiconductor layer. A monolithic LED array structure is provided on the growth surface of the first semiconductor layer such that the monolithic LED array structure covers each of the mesa surfaces and the bulk semiconductor surface. The monolithic LED array structure comprises a plurality of layers, each layer comprising a III-nitride, the plurality of layers comprising an n-type semiconductor layer, an active layer overlying the n-type semiconductor layer and configured to generate light. and a p-type semiconductor layer provided on the active layer. A potential barrier is provided between the mesa portion of the p-type semiconductor layer covering each of the mesa surfaces and the bulk portion of the p-type semiconductor layer covering the bulk semiconductor surface, the potential barrier being the p-type semiconductor covering the mesa surface. Surrounding each mesa portion of the layer.

An LED precursor array according to the fourth aspect provides an LED precursor array that can be formed by the method of the second aspect. Accordingly, an LED precursor array according to the fourth aspect may include a plurality of LEDs according to the third aspect. Accordingly, the LED precursor array can incorporate features corresponding to all of the important features of the first aspect described above.

BRIEF DESCRIPTION OF THE FIGURES The disclosure will now be described with reference to the following non-limiting drawings. Further advantages of the present disclosure will become apparent by reference to the detailed description when considered in conjunction with the drawings.

Fig. 3 shows an intermediate step of a method according to an embodiment of the present disclosure, in which a first semiconductor layer comprising a mesa structure is provided; FIG. 3B illustrates an intermediate step of a method according to an embodiment of the present disclosure, in which a first semiconductor layer with an overgrown second semiconductor layer is provided; FIG. 3B illustrates an intermediate step of a method according to an embodiment of the present disclosure, in which a monolithic LED structure is provided on a first semiconductor layer; Figure 4 shows an intermediate step of a method according to an embodiment of the present disclosure, in which a mask layer is provided over the intermediate structure of Figure 3; 1 is a diagram of an LED precursor according to one embodiment of the present disclosure; FIG. FIG. 3B illustrates an intermediate step of a method according to an embodiment of the present disclosure, in which a monolithic LED structure is provided on a first semiconductor layer; FIG. 4 is a diagram of an LED precursor according to another embodiment of the present disclosure; FIG. 8a shows an SEM image of the mesa structure of the first semiconductor layer. FIG. 8b shows an SEM image of the mesa structure of the first semiconductor layer. FIG. 8c shows an SEM image of an overgrown monolithic LED array structure. FIG. 8d shows an SEM image of an overgrown monolithic LED array structure. FIG. 10 shows an SEM image of an overgrown monolithic LED array structure with a hexagonal fill pattern; FIG. 3 is a cross-sectional SEM image of a first semiconductor layer including a plurality of mesa structures and an overgrown second semiconductor layer; FIG. 10 is a further cross-sectional SEM image of a first semiconductor layer comprising a plurality of mesa structures and an overgrown second semiconductor layer;

DETAILED DESCRIPTION According to one embodiment of the present disclosure, a method of forming an LED 1 is provided. Here, a method for forming an LED will be described with reference to FIGS. 1 to 4. FIG.

As shown in FIG. 1, a substrate 10 may be provided for forming LEDs thereon. The substrate may be any substrate 10 suitable for forming III-nitride electronic devices. For example, substrate 10 may be a sapphire substrate or a silicon substrate. The substrate can comprise one or more buffer layers configured to provide a substrate surface suitable for forming a III-nitride layer.

A first semiconductor layer 20 may be formed on the substrate surface. The first semiconductor layer 20 comprises group III-nitrides. In some embodiments, the first semiconductor layer may be n-type doped. In other embodiments, the semiconductor layer may not be intentionally doped.

For example, in the embodiment of FIG. 1, first semiconductor layer 20 comprises GaN. GaN may be n-type doped using a suitable dopant such as Si or Ge. The first semiconductor layer 20 may be deposited using any suitable process for manufacturing Group III-nitride thin films, such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). good. The first semiconductor layer 20 has a first surface, which is the surface of the first semiconductor layer 20 opposite the first semiconductor layer 20 with respect to the substrate 10 . The first surface is used to form at least a portion of the growth surface 22 on which the layers of the LED structure are deposited.

In some embodiments, the first semiconductor layer 20 may be formed on a substrate having (0001) crystal planes oriented parallel to the surface of the substrate.

The growth surface 22 of the first semiconductor layer 20 may then be shaped using a selective removal process. Accordingly, portions of first semiconductor layer 20 are selectively removed to form mesa structure 24 such that growth surface 22 of first semiconductor layer 20 comprises mesa surface 25 and bulk semiconductor layer surface 26 . .

For example, in FIG. 1, growth surface 22 can be shaped using an etching process. A mesa-defining mask layer (not shown) may be deposited on the first surface of the first semiconductor layer 20 in an etching process. The mesa-defining mask layer is configured to mask the portion of the first semiconductor layer 20 intended to form the mesa surface 25 of the growth surface. The unmasked portions of first semiconductor layer 20 can then be selectively removed using an etchant. The etchant may etch away portions of first semiconductor layer 20 to expose bulk semiconductor layer surface 26 of first semiconductor layer 20 . That is, the etchant does not have to etch through the thickness of the first semiconductor layer 20 to expose the substrate 10 underneath. The mesa-defining mask layer may then be removed from the first semiconductor layer. By following the process described above, the first semiconductor layer 20 can be shaped to provide a mesa structure 24 monolithically disposed on the bulk semiconductor layer surface 26, as shown, for example, in FIG.

In some embodiments, mesa surface portions of first semiconductor layer 20 may not be selectively removed. Therefore, the orientation of mesa surface 25 with respect to substrate 10 may remain unchanged after the selective removal step. Therefore, the mesa surface 25 can be parallel to the surface of the substrate. In some embodiments, the first semiconductor layer is etched such that bulk semiconductor surface 26 is also substantially parallel to substrate 10 . Accordingly, both the mesa surface 25 and the bulk semiconductor surface 26 of the first semiconductor layer 20 can be surfaces that are substantially parallel to each other. In some embodiments, mesa surface 25 and bulk semiconductor surface 26 may be oriented with the (0001) plane of the Group III-nitride forming first semiconductor layer 20 .

In FIG. 1, mesa structure 24 is shown having sidewalls substantially perpendicular to bulk semiconductor surface 26 and mesa surface 25 . In other embodiments, mesa structure 24 may be formed with sloped sidewalls. For example, different etchants can be used to control the shape of the sidewalls formed during the selective removal process.

A monolithic LED structure can then be formed on the growth surface 22 of the first semiconductor layer 20 . A monolithic LED structure covers the mesa surface 25 and the bulk semiconductor layer surface 26 . A monolithic LED structure comprises multiple layers, each layer comprising a group III-nitride. In some embodiments, the III-nitride comprises one or more of AlInGaN, AlGaN, InGaN and GaN.

A monolithic LED structure refers to providing an LED structure that is formed as a single piece. That is, a monolithic LED structure is formed as a single piece on the first semiconductor layer.

In one embodiment of the present disclosure, a second semiconductor layer 30 may be deposited over the first semiconductor layer 20, as shown in FIG. A second semiconductor layer 30 is formed on the first semiconductor layer 20 on the opposite side of the substrate 10 from the first semiconductor layer 20 . The second semiconductor layer 30 thus forms the first of the layers of the monolithic LED structure. For reference, FIG. 2 schematically shows the contour of the growth surface 22 of FIG. 1 as a dashed line.

Second semiconductor layer 30 may be formed on growth surface 22 by any suitable growth method for growing Group III-nitrides. In the embodiment of FIG. 2, second semiconductor layer 30 is monolithically formed over growth surface 22 (ie, an overgrowth method). Second semiconductor layer 30 may be formed as a continuous layer covering substantially the entire growth surface 22 . The second semiconductor layer 30 may be deposited using any suitable process for manufacturing Group III-nitride thin films, such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). good.

The second semiconductor layer 30 comprises group III-nitrides. In the embodiment of Figure 2, the second semiconductor layer 30 comprises GaN. The second semiconductor layer may be n-doped. GaN may be n-type doped using a suitable dopant such as Si or Ge. In the embodiment of FIG. 2, second semiconductor layer 30 is intentionally undoped. Accordingly, the second semiconductor layer 30 may be a (substantially) undoped layer. By substantially undoped, it is understood that the III-nitride layer does not contain significant amounts of dopant elements, although some impurities may be present as a result of the manufacturing process. Accordingly, a substantially undoped III-nitride may not be intentionally doped. By forming the second semiconductor layer 30 from an undoped semiconductor, charge carrier flow through the LED can be more effectively confined within the mesa structure 24 .

By growing the second semiconductor layer 30 on the first semiconductor layer 20 , the second semiconductor layer can have a crystal structure corresponding to the crystal structure of the first semiconductor layer 20 . For example, if the mesa surface 25 of the first semiconductor layer 20 is oriented with the (0001) plane of the III-nitride, the second semiconductor layer 30 can also be grown with a similar crystal orientation.

In the embodiment of FIG. 2, the second semiconductor layer 30 is formed on the growth surface 22 to include a first portion 34 of the second semiconductor layer on the mesa surface 25 of the first semiconductor layer and a first portion 34 of the second semiconductor layer on the mesa surface 25 of the first semiconductor layer. A sloped sidewall portion 33 is provided extending between a second portion 36 of the second semiconductor layer on the bulk semiconductor surface 26 of the second semiconductor layer. Thus, the second semiconductor layer 30 is overgrown on the mesa structure 24 of the first semiconductor layer 20 to provide a Group III-nitride with a second semiconductor layer mesa surface 35 and surrounded by sloped sidewall portions 33 . A semiconductor layer can be provided. Thus, the second semiconductor layer 30 can be overgrown on the mesa structure 24 to form a pillar with a regular trapezoidal cross-section perpendicular to the substrate, the mesa surface 35 of the second semiconductor layer being trapezoidal. forming a substantially flat upper surface of the cross-section; The mesa surface 35 of the second semiconductor layer can be oriented in a plane parallel to the substrate surface on which the layer is formed.

By "regular trapezoidal cross-section" is meant that the pillars are narrower at the top than at the base, have sloping straight sides, and have a substantially flat top surface. This may result in a truncated cone shape, or more likely a truncated pyramid shape with three or more sides, typically six sides. The description "regular trapezoidal cross-section" refers to the first portion 34 of the second semiconductor layer grown over the mesa structure 24 . A trapezoidal cross-section is a discontinuous portion of the second semiconductor layer that extends over a continuous planar portion of the second semiconductor layer.

The tapered sides of the trapezoidal cross-section of the post are referred to herein as sidewall portions 33 .
In some embodiments, the sidewall portion 33 of the pillar has a substantially constant angle (α) with respect to a plane parallel to the first semiconductor layer. That is, the angle between the side surface of the pillar and the plane parallel to the first semiconductor does not change significantly. For example, the angle α is 50°-70°, more preferably 58°-64°, most preferably about 62°.

Therefore, in some embodiments, the sidewall portion 33 of the pillar can be slanted with respect to the (0001) plane of the crystal structure of the first semiconductor layer 20 . The sloping sidewalls are generally wurtzite-type crystals, similar to structures produced by SAG.

, exhibiting a reduced polarization field compared to the c-plane (semipolar plane).
In some embodiments, the pillars of second semiconductor layer 30 are truncated hexagonal pyramids.

At this time, an active layer 40 may be formed on the second semiconductor layer 30, as shown in FIG. Active layer 40 is configured to generate light at a first wavelength as part of a monolithic LED structure.

In the embodiment of FIG. 2, active layer 40 may comprise one or more quantum well layers (not shown). Accordingly, active layer 40 may be a multiple quantum well layer. The quantum well layers in active layer 40 may comprise a III-nitride semiconductor, preferably a III-nitride alloy comprising In. For example, in the embodiment of FIG. 2, active layer 40 may comprise alternating layers of GaN and In _z Ga _1-z N, where 0<Z≦1. The thickness and In content of the quantum well layers can be controlled to control the wavelength of light produced by the active layer. Active layer 40 may be formed as a continuous layer covering a substantial portion (eg, all) of the exposed surface of second semiconductor layer 30 . Active layer 40 may be deposited using any suitable process for manufacturing Group III-nitride films, such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

Deposition of the active layer 40 on the second semiconductor layer 30 has a relatively high deposition rate on the first portion 35 of the second semiconductor layer on the mesa surface 25 and a significantly lower deposition on the sloped sidewalls. It can be done at speed. This effect arises from the different crystallographic orientations of the various surfaces, resulting in a thicker active layer 40 over mesa surface 25 than over sloped sidewalls 35 . This effect is described in more detail in GB 1811109.6.

Further layers of the monolithic LED structure can then be deposited on the active layer 40 on the opposite side of the active layer 40 to the second semiconductor layer 30 . FIG. 3 shows an example of multiple layers forming a monolithic LED structure formed on the growth surface 22 of the first semiconductor layer 20 . Each of the multiple layers of the monolithic LED structure may be formed as a continuous layer.

In the embodiment of FIG. 3, a second semiconductor layer 30 comprising undoped GaN is formed over the first semiconductor layer 20 . The first semiconductor layer of FIG. 3 comprises n-type doped GaN. The active layer 40 is provided on the second semiconductor layer 30 as described above.

In the embodiment of FIG. 3, an electron blocking layer 50 is provided on active layer 40 . The electron blocking layer 50 is provided on the side surface of the active layer 40 opposite to the side surface of the active layer 40 on which the second semiconductor layer 30 is provided. Electron blocking layer 50 comprises a III-nitride. Electron blocking layer 50 may be formed as a continuous layer covering a substantial portion (eg, all) of the exposed surface of active layer 40 . Electron blocking layer 50 is configured to reduce the flow of electrons from active layer 30 to p-type semiconductor layer 60 of the monolithic LED structure. For example, in the embodiment of FIG. 3, electron blocking layer 50 may comprise Al _x Ga _1-x N. Further details of suitable electron blocking layers 50 can be found at least in Schubert, E.; (2006). Light-Emitting Diodes. Cambridge: can be found at Cambridge University Press.

As shown in FIG. 3, a p-type semiconductor layer 60 is provided on the active layer 40 . The p-type semiconductor layer 60 is provided on the side surface of the electron block layer 50 on the side opposite to the side surface of the electron block layer 50 on which the active layer 40 is provided. The p-type semiconductor layer 60 comprises Group III nitrides. The p-type semiconductor layer is doped with a suitable electron acceptor, eg Mg. P-type semiconductor layer 60 may be formed as a continuous layer covering a substantial portion (eg, all) of the exposed surface of active layer 40 (or electron blocking layer 50 if present).

Accordingly, p-type semiconductor layer 60 may include a first portion 64 substantially aligned with mesa structure 24 . That is, the surfaces of the first portion 65 of the p-type semiconductor layer are provided in alignment above the mesa surface 25 (ie, the centers of the respective surfaces are aligned). P-type semiconductor layer 60 also includes a second portion that covers at least a portion of bulk semiconductor surface 26 remote from mesa surface 24 . Thus, a monolithic LED structure can generally be considered to have a first portion overlying mesa surface 25 and a second portion covering at least a portion of bulk semiconductor surface 26 remote from mesa surface 24 . .

In order to improve charge carrier confinement within the active layer above the mesa surface 25 of the LED, the method according to the present disclosure includes a first portion of the monolithic LED structure overlying the mesa surface 25 and a monolithic LED structure overlying the bulk semiconductor surface 26 . The potential barrier surrounds the first portion of the p-type semiconductor layer overlying the mesa surface 25 . That is, the method according to the present disclosure provides a potential barrier between the top contact surface of the regular trapezoidal shape and substantially planar surface and the layer formed over the bulk semiconductor surface 26 .

One method for forming such a potential barrier is shown schematically in FIGS. 3 and 4. FIG. The embodiments of FIGS. 4 and 5 show further processing steps after fabrication of the device shown in FIG.

In FIG. 4, a mask layer 70 is formed on the surface of p-type semiconductor layer 60 on the opposite side of p-type semiconductor layer 60 from electron blocking layer 50 .

The mask layer 70 may be selectively provided on the p-type semiconductor layer 60 . A mask layer 70 may be provided to define one or more openings. The openings can be configured to expose regions of p-type semiconductor layer 60 that are to be selectively removed. For example, the opening may define a third portion 61 of the p-type semiconductor layer surrounding the first portion 64 of the p-type semiconductor layer overlying the mesa structure. A third portion 61 of the p-type semiconductor layer may then be selectively removed, for example by etching, to provide a potential barrier. For example, in the embodiment of FIG. 4, the third portion 61 of the p-type semiconductor layer is the sloped sidewall portion of the p-type semiconductor layer 60 .

In the embodiments of FIGS. 4 and 5, an anisotropic etchant can be used to selectively remove the third portion 61 of the p-type semiconductor layer. Anisotropic etchants, such as KOH, preferentially etch sloped sidewall regions of III-nitrides at a faster rate than planes oriented parallel to the substrate (e.g., surfaces oriented with (0001) crystal planes). can be done. Thus, the mask layer 70 aligns and covers the surfaces of the first portion 65 of the p-type semiconductor layer and the third portion 61 of the p-type semiconductor layer corresponding to the sloped sidewall regions of the p-type semiconductor layer 60 . It may be provided to define an opening for exposure. The anisotropic etchant can then preferentially etch the p-type semiconductor layer 60 in the sloped sidewall regions at a significantly higher rate to remove the desired amount of material.

FIG. 5 shows a schematic representation of the LED precursor obtained after formation of the potential barrier by selective removal of the third portion 61 of the p-type semiconductor layer. As shown in FIG. 5, p-type semiconductor layer 60 is selectively removed through the thickness of the layer to expose the underlying layer (electron blocking layer 50 in the embodiment of FIG. 5). The selective removal step thus forms a channel within the monolithic LED structure surrounding the first portion 64 of the p-type semiconductor layer. As a result, in the p-type semiconductor layer 60 , a potential barrier is formed between the first portion 65 of the p-type semiconductor layer covering the mesa surface 25 and the second portion 66 of the p-type semiconductor layer covering the bulk semiconductor surface 26 . It is formed. A potential barrier is provided to increase the confinement of charge carriers within the mesa structure region of the active layer of the device during operation.

In other embodiments of methods according to the present disclosure, the depth of selectively removed channels can be varied. For example, in some embodiments, the channel may extend only partially through the thickness of the third portion 61 of the p-type semiconductor layer. By reducing the thickness of the third portion 61 of the p-type semiconductor layer in combination with the change in the deposition rate of the monolithic LED structure on the sidewall surface described above, the remaining portion of the third portion 61 of the p-type semiconductor layer The portion can present a large resistance between the first portion 65 and the second portion 66 of the p-type semiconductor layer, thereby effectively providing a potential barrier. In other embodiments, the channel may extend at least partially through the thickness of one or more of the other layers of the monolithic LED structure.

A further method for forming such a potential barrier is shown schematically in FIGS. 6 and 7. FIG.

FIG. 6 shows a structure comprising a first semiconductor layer 20 , a second semiconductor layer 30 and an active layer 40 . The structure of FIG. 6 can be formed by the method steps described above in connection with FIGS. 1-3.

Following formation of the structure of FIG. 6, a p-type semiconductor layer 60 is formed over the active layer 40, as shown in FIG. The p-type semiconductor layer 60 is formed on the opposite side of the active layer 40 with respect to the second semiconductor layer 30 . In some embodiments, an electron blocking layer 50 may be provided between the p-type semiconductor layer 60 and the active layer 40, as shown in FIG.

In the embodiment of FIG. 7, the p-type semiconductor layer 60 comprises an Al-containing Group III-nitride. The p-type semiconductor layer 60 is the first portion of the p-type semiconductor layer overlying the mesa surface 25 such that a potential barrier is provided between the sidewall portion 63 of the p-type semiconductor layer and the first portion 64 of the p-type semiconductor layer. A higher concentration of Al than the 1 portion 64 can be formed to be incorporated into the sidewall portion 63 of the p-type semiconductor layer. The difference in Al composition between the sidewall portion 63 and the first portion 64 of the p-type semiconductor layer is such that the change in bandgap between the first portion and the sidewall portion is greater than kT eV at room temperature (ie, about 0.0. 26 eV).

For example, the sidewall portion 63 of the p-type semiconductor layer may comprise p-type Al _x Ga _1-x N, where 2≦x≦50%, and the first portion 64 of the p-type semiconductor layer is p-type Al _y Ga _1-y N, where 1≦y≦15%.

As noted above, the sloping sidewalls of the second semiconductor layer 30 result in variations in the III-nitride deposition rate depending on whether the growth surface is a sloping sidewall or substantially parallel to the substrate. bring. Regarding the growth of the p-type semiconductor layer 60 , the difference in growth rate also affects the incorporation of Al into the p-type semiconductor layer 60 . Therefore, sloped sidewall portion 63 can be formed with a higher Al content than first portion 64 using the same deposition process. Therefore, the desired potential barriers for current confinement in the first portion 64 of the p-type semiconductor layer of the monolithic LED structure can be formed without additional patterning steps.

As noted above, an LED precursor can be provided having multiple layers.
The first semiconductor layer 20 may have a thickness between 100 nm and 8 μm, preferably between 3 μm and 5 μm. Portions of first semiconductor layer 20 may be selectively removed to define mesa structures having a height perpendicular to bulk semiconductor surface 26 of at least 100 nm, 200 nm, 300 nm, or 500 nm. The height of the mesa structure may be 5 μm or less. In some embodiments, the mesa structure may have a height of 1 μm to 3 μm.

The second semiconductor layer 30 may have a thickness of at least 5 nm on the mesa surface 24 of the first semiconductor layer 20 . The thickness of the second semiconductor layer 30 may be 4 μm or less.

The substantially planar first portion 34 of the active layer 30 may have a thickness of 30 nm to 150 nm, in some embodiments 40 nm to 60 nm.

The substantially planar first portion 44 of electron blocking layer 50 may have a thickness of 5 nm to 50 nm, in some embodiments 20 nm to 40 nm. For example, in the embodiment of FIG. 3, the electron blocking layer may have a thickness of 33 nm. Due to deposition rate variations, the thickness of electron blocking layer 50 in the sidewall regions of electron blocking layer 50 can have a thickness of at least 0.5 nm to about 25 nm, as described above. For example, in the embodiment of FIG. 3, electron blocking layer 50 may have a thickness of about 7 nm in the sidewall regions.

The substantially planar first portion 64 of the p-type semiconductor layer 60 may have a thickness of at least 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. The substantially planar first portion 64 of the p-type semiconductor layer 60 may have a thickness of 300 nm, 250 nm, or 200 nm or less. For example, in the embodiment of FIG. 3, substantially planar first portion 64 of p-type semiconductor layer 60 may have a thickness of approximately 100 nm.

In some embodiments, the height of the mesa structure (perpendicular to bulk semiconductor surface 26) is greater than or equal to the cross-sectional width of the mesa surface. That is, in at least one plane perpendicular to bulk semiconductor surface 26, the height of the mesa structure is greater than or equal to the cross-sectional width of the mesa surface. Therefore, the height of the mesa structure relative to the cross-sectional width of the mesa structure can provide an LED precursor with an optimized aspect ratio to enhance light extraction efficiency from the LED.

For example, in some embodiments, a mesa surface 25 having a surface area of 100 μm×100 μm or less can be provided. In particular, the mesa surface can have a surface area of 4 μm×4 μm or less. Accordingly, the height of the mesa structure may be at least 4 μm.

After formation of the LED precursor as described above, the LED precursor can undergo further processing steps to provide an LED. For example, in some embodiments, substrate 10 can be removed to expose light emitting surface 21 of first semiconductor layer 20 .

Preferably, light extraction features such as lenses (ie, dome-shaped surfaces) may also be provided on the light emitting surface. For example, lenses (or other dome-shaped structures) can be formed on the emitting surface 21 to increase the efficiency of light extraction from the LEDs. In some embodiments, a lens is aligned with each LED on emitting surface 21 . Each lens can cover a surface area of the emitting surface 21 corresponding to the surface area of the base of the monolithic LED structure (ie, the base of the trapezoidal shape). In some embodiments, a lens (dome-shaped surface) can be formed by the emitting surface 21 by selectively removing the first semiconductor layer 20 from the emitting surface 21 . By providing light extraction features on the emitting surface 21 of the LED, the light extraction efficiency of the LED can be increased.

According to one embodiment of the present disclosure, a light emitting diode precursor 1 is provided. The LED precursor comprises a first semiconductor layer 20 , a second semiconductor layer 30 , an active layer 40 and a p-type semiconductor layer 60 .

The first semiconductor layer 20 comprises group III-nitrides. As shown in FIG. 3, a first semiconductor layer 20 may be provided on the substrate 10 . Substrate 10 may comprise sapphire, silicon or SiC. Substrate 10 may comprise one or more buffer layers configured to provide a substrate surface suitable for formation of III-nitride layers. Of course, in some embodiments, the LED precursor 1 can be manufactured according to the method described above, after which the substrate 10 can be removed. In some embodiments, LED precursor 1 may be bonded to a backplane electronic substrate (not shown). The backplane electronic board can comprise electrical circuits and contacts configured to control and contact the LED precursors 1 . In some embodiments, the backplane electronic substrate may be bonded to the p-type semiconductor layer 60 .

5 and 7, first semiconductor layer 20 has a mesa structure extending from a major surface of first semiconductor layer 20 to define growth surface 22 including bulk semiconductor surface 26 and mesa surface 25 . 24. Major surface is understood to mean the surface of the first semiconductor layer 20 forming a substantial part of the total surface area of the first semiconductor layer 20 . For example, in FIGS. 5 and 7, the major surface forming the growth surface 22 is the surface of the first semiconductor layer 20 provided on the opposite side of the substrate 10 from the first semiconductor layer 20 .

Mesa structures 24 can be thought of as pillars extending from bulk semiconductor surface 26 of first semiconductor layer 20 . Mesa structure 24 is formed monolithically with bulk semiconductor surface 26 of first semiconductor layer 20, for example, as described in the methods above. The mesa structure 24 may be a pillar having an arbitrary cross-sectional shape (that is, a pillar shape when the first semiconductor layer 20 is viewed from above). For example, the mesa structure 24 may be a column with a regular polygonal cross section. In particular, mesa structure 24 may be an elliptical (or cylindrical), prismatic, or hexagonal prism. FIG. 8a shows an example of a plurality of mesa structures 24 of the first semiconductor layer 20, each mesa structure 24 being a cylinder.

In the embodiments shown in FIGS. 5 and 7, mesa structure 24 is shown having sidewalls substantially perpendicular to bulk semiconductor surface 26 and mesa surface 25 . In other embodiments, mesa structure 24 may be formed with sloped sidewalls.

As shown in FIGS. 5 and 7, a monolithic LED structure is provided on growth surface 22 of first semiconductor layer 20 such that the monolithic LED structure covers mesa surface 25 and bulk semiconductor surface 26 .

As mentioned above, a monolithic LED structure comprises multiple layers. Each layer is formed from a Group III nitride. The monolithic LED structure comprises a second semiconductor layer 30 , an active layer 40 and a p-type semiconductor layer 60 . In some embodiments, the monolithic LED structure can also include an electron blocking layer 50. FIG.

As described above, the second semiconductor layer 30 is provided on the growth surface 22 to provide a first portion 34 of the second semiconductor layer on the mesa surface 25 of the first semiconductor layer and a first portion 34 of the second semiconductor layer on the mesa surface 25 of the first semiconductor layer. A sloped sidewall 33 is provided extending between the second portion 36 of the second semiconductor layer on the bulk semiconductor surface 26 of layer 20 . Accordingly, the second semiconductor layer 30 is overgrown on the mesa structure 24 of the first semiconductor layer 20 to provide a III-nitride semiconductor layer having a first portion 34 and surrounded by sloped sidewalls 33 . be done. Thus, the second semiconductor layer 30 can be overgrown on the mesa structure 24 to form a pillar with a regular trapezoidal cross-section perpendicular to the substrate, the first portion 35 of the second semiconductor layer is substantially flat. The substantially planar surface of first portion 35 may lie in a plane parallel to the substrate surface on which each layer is formed.

Active layer 40, electron blocking layer 50 (if present), and p-type semiconductor layer 60 may be provided on second semiconductor layer 30 according to the methods described above to form a monolithic LED structure. Examples of such monolithic LED structures can also be seen in at least FIGS.

To improve charge carrier confinement within the active layer above the mesa surface 25 of the LED, the LED precursor according to the present disclosure comprises a first portion of the monolithic LED structure overlying the mesa surface 25 and a monolithic overlying bulk semiconductor surface 26 . A potential barrier is provided between the second portion of the LED structure and surrounds the first portion of the p-type semiconductor layer overlying the mesa surface 25 . That is, the method according to the present disclosure provides a potential barrier between a substantially planar surface of regular trapezoidal shape and a layer formed over bulk semiconductor surface 26 .

As shown in FIGS. 5 and 7, the monolithic LED structure is between a first portion 64 of p-type semiconductor layer covering the mesa surface and a second portion 66 of p-type semiconductor layer covering the bulk semiconductor surface. A potential barrier is formed to surround the first portion 64 of the p-type semiconductor layer overlying the mesa surface.

In the embodiment of FIG. 5, the potential barrier can be formed by selectively removing the third portion 61 of the p-type semiconductor layer surrounding the first portion 64 of the p-type semiconductor layer overlying the mesa surface. . As shown in FIG. 5, p-type semiconductor layer 60 is selectively removed through the thickness of the layer to expose the underlying layer (electron blocking layer 50 in the embodiment of FIG. 5).

In the embodiment of FIG. 7, the potential barrier may be formed by providing a p-type semiconductor layer 60 comprising an Al-containing III-nitride. The p-type semiconductor layer 60 is the first portion of the p-type semiconductor layer overlying the mesa surface 25 such that a potential barrier is provided between the sidewall portion 63 of the p-type semiconductor layer and the first portion 64 of the p-type semiconductor layer. A higher concentration of Al than the one portion 64 is provided to be incorporated into the sidewall portion 63 of the p-type semiconductor layer. The difference in Al composition between the sidewall portion 63 of the p-type semiconductor layer and the first portion 64 is such that the bandgap change is greater than kT eV (i.e., greater than about 0.26 eV) at room temperature. be able to.

For example, the sidewall portion of the p-type semiconductor layer may comprise p-type Al _x Ga _1-x N, where 2≦x≦50%, and the mesa surface portion 65 of the p-type semiconductor layer may comprise p-type Al _y Ga _1-y N, where 1≦y≦15%.

As noted above, the sloping sidewalls 33 of the second semiconductor layer 30 increase the Group III-nitride deposition rate, depending on whether the growth surface is a sloping sidewall or substantially parallel to the substrate. Bring change. Regarding the growth of the p-type semiconductor layer 60 , the difference in growth rate also affects the incorporation of Al into the p-type semiconductor layer 60 . Thus, the sloped sidewall portion 63 of the p-type semiconductor layer can be formed with a higher Al content than the first portion 65 of the p-type semiconductor layer using the same deposition process. Therefore, the desired potential barriers for current confinement in the first portion of the monolithic LED structure can be formed without additional patterning steps.
Accordingly, an LED precursor according to one embodiment of the present disclosure can be provided.

According to another embodiment of the present disclosure, a method of forming an LED array precursor can be provided.

According to this method, a first semiconductor layer 20 comprising III-nitride is formed on the substrate 10 . The first semiconductor layer has a growth surface 22 on the opposite side of the first semiconductor layer 20 with respect to the substrate 10 . Accordingly, first semiconductor layer 20 may be formed in substantially the same manner as described above for the embodiments of FIGS. 1-5 and 6-7.

Portions of the first semiconductor layer 20 are then selectively removed to form a plurality of mesa structures 24 such that the growth surface 22 of the first semiconductor layer 20 comprises a plurality of mesa surfaces 25 and a bulk semiconductor layer surface 26 . is formed. Accordingly, this step of the method is substantially the same as the corresponding step of the method of forming an LED precursor, except that multiple mesa structures 24 are formed.

The plurality of mesa structures 24 may be regularly spaced across the substrate growth surface 22 of the first semiconductor layer 20 . For example, the mesa structure may be provided in a hexagonal close-packed array or square-packed array of mesa structures 24 . FIG. 8a shows a scanning electron microscope (SEM) image of a first semiconductor layer comprising a plurality of mesa structures 24. FIG. A plurality of mesa structures 24 are provided as part of the first semiconductor layer 20, as shown in FIG. 8a. Each of the mesa structures 24 is a column of cylindrical shape (circular cross section). Figure 8b shows an enlarged view of one of the mesa structures 24 shown in Figure 8a.

A monolithic LED array structure is then formed on the growth surface of the first semiconductor layer 20 such that a first portion of the monolithic LED array structure overlies each mesa surface 25 and a second portion of the monolithic LED array structure. covers bulk semiconductor surface 26 . A monolithic LED array structure comprises multiple layers. Each layer is formed from a Group III nitride. The monolithic array structure includes a second semiconductor layer 30 , an active layer 40 provided on the second semiconductor layer 30 , and a p-type semiconductor layer 60 provided on the active layer 40 . In some embodiments, the monolithic LED structure may also include an electron blocking layer 50 provided between the active layer 40 and the second semiconductor layer 60 .

A monolithic LED array structure refers to providing an LED array structure formed as a single piece. That is, a monolithic LED array structure is formed as a single piece on the first semiconductor layer.

The layers of the monolithic LED array structure can be provided using substantially the same processes as described above for forming LED precursors. It will be appreciated that substantially the same process for forming the monolithic LED array structure/monolithic LED structure can be used regardless of the number or shape of LEDs being manufactured. Accordingly, the overgrowth method of the present disclosure provides a method of forming an LED array precursor in which a substantial portion of the manufacturing process is independent of the geometry of the LED array.

Figures 8c and 8d show SEM images of multiple mesa structures with an overgrown monolithic LED array structure. A monolithic LED array structure is formed on a plurality of mesa structures 24 similar to that shown in Figure 8a. In Figures 8a-8d, mesa structures 24 are formed in a square-filled array pattern. FIG. 9 shows an SEM image of a further array of mesa structures with an overgrown monolithic LED array structure. In FIG. 9, mesa structures 24 are arranged in a hexagonal close-packed array pattern to provide the array structure shown.

In some embodiments, second semiconductor layer 30 may comprise the same material as first semiconductor layer 20 . For example, the first semiconductor layer 20 and the second semiconductor layer 30 may comprise GaN n-doped with Si. Thus, the second semiconductor layer 30 may be monolithically formed over the growth surface 22 of the first semiconductor layer with substantially the same lattice constant. The resulting structure may have a substantially continuous crystalline structure at the interface between the first semiconductor layer 20 and the second semiconductor layer 30 . 10 and 11 show SEM images of first semiconductor layer 20 and second semiconductor layer 30 formed according to the method of the present disclosure. In the SEM images of FIGS. 10 and 11, the interface between the mesa structure 24 of the first semiconductor layer 20 and the second semiconductor layer 30 is not detected.

A potential barrier is provided between each first portion 64 of the p-type semiconductor layer overlying mesa surface 25 and a bulk portion 66 of the p-type semiconductor layer overlying bulk semiconductor surface 26 . A potential barrier surrounds each first portion 64 of the p-type semiconductor layer overlying each mesa surface 25 .

In order to improve charge carrier confinement within the active layer 40 over each mesa surface 25 of each LED, within each LED a first portion of the monolithic LED structure overlying the mesa surface 25 and a monolithic overlying bulk semiconductor surface 26 are formed. A potential barrier is formed between the second portion of the LED structure and surrounds the first portion of the p-type semiconductor layer overlying the mesa surface 25 . That is, the method according to the present disclosure provides a potential barrier between the top contact surface of the regular trapezoidal shape and substantially planar surface and the layer formed over the bulk semiconductor surface 26 .

The potential barriers of each monolithic LED structure of the LED array can be formed in several ways. For example, the potential barriers of each monolithic LED structure can be formed substantially as described above with reference to FIG. 5 or substantially as described above with reference to FIG.

For the embodiment of FIG. 5, the potential barriers may be formed by selectively removing the third portions 61 of the p-type semiconductor layer surrounding each first portion 64 of the p-type semiconductor layer overlying the mesa surface. can. As shown in FIG. 5, p-type semiconductor layer 60 is selectively removed through the thickness of the layer to expose the underlying layer (electron blocking layer 50 in the embodiment of FIG. 5).

For the embodiment of FIG. 7, the potential barrier may be formed by providing a p-type semiconductor layer 60 comprising an Al-containing III-nitride. The p-type semiconductor layer 60 is the first portion of the p-type semiconductor layer overlying the mesa surface 25 such that a potential barrier is provided between the sidewall portion 63 of the p-type semiconductor layer and the first portion 64 of the p-type semiconductor layer. A higher concentration of Al than the one portion 64 is provided to be incorporated into the sidewall portion 63 of the p-type semiconductor layer. The difference in Al composition between the sidewall portion 63 of the p-type semiconductor layer and the first portion 64 is such that the bandgap change is greater than kT eV (i.e., greater than about 0.26 eV) at room temperature. be able to.

Accordingly, an LED array precursor is provided.
The LED array precursor comprises a first semiconductor layer 20 , a second semiconductor layer 30 , an active layer 40 and a p-type semiconductor layer 60 .

The first semiconductor layer 20 comprises group III-nitrides. As shown in FIG. 3, a first semiconductor layer 20 may be provided on the substrate 10 . Substrate 10 may comprise sapphire, silicon or SiC. Substrate 10 may comprise one or more buffer layers configured to provide a substrate surface suitable for formation of III-nitride layers. Of course, in some embodiments, the LED array precursor can be fabricated according to the methods described above, after which the substrate 10 can be removed. In some embodiments, the LED array precursor may be bonded to a backplane electronic substrate. The backplane electronics board can include electrical circuitry and contacts configured to control and contact the LEDs of the LED array precursor. In some embodiments, the backplane electronic substrate may be bonded to the p-type semiconductor layer 60 . Accordingly, the first semiconductor layer may be provided substantially according to the methods outlined above.

5 and 7, the first semiconductor layer 20 extends from a major surface of the first semiconductor layer to define a growth surface 22 including a bulk semiconductor surface 26 and a mesa surface 25. It includes a plurality of mesa structures 24 for As mentioned above, an example of a first semiconductor layer comprising a plurality of mesa structures 24 is shown in FIG. 8a.

Similar to the embodiments shown in FIGS. 5 and 7, a monolithic LED array structure is provided on growth surface 22 of first semiconductor layer 20 such that the monolithic LED array structure overlies mesa surface 25 and bulk semiconductor surface 26 . be done. As mentioned above, an example of a monolithic LED array structure is shown in Figures 8c and 8d.

As mentioned above, a monolithic LED array structure comprises multiple layers. Each layer is formed from a Group III nitride. A monolithic LED array structure comprises a second semiconductor layer 30 , an active layer 40 and a p-type semiconductor layer 60 . In some embodiments, the monolithic LED array structure can also include an electron blocking layer 50. FIG. Each of the layers of the monolithic LED array structure may be formed as a continuous layer. Each of the layers of the monolithic LED array structure can thus be provided in a manner similar to the monolithic LED structure described above. Examples of such monolithic LED structures can also be seen in at least FIGS.

In order to improve charge carrier confinement within the active layer above each mesa surface 25 of the LED array precursor, each LED precursor of the array includes a first portion of each monolithic LED structure overlying the respective mesa surface 25 . A potential barrier is provided between the second portion of each monolithic LED structure overlying the bulk semiconductor surface 26 and surrounds the first portion of each p-type semiconductor layer overlying the respective mesa surface 25 . That is, the method according to the present disclosure provides a potential barrier between each substantially planar surface of the regular trapezoidal shape and the layer formed over bulk semiconductor surface 26 .

5 and 7, each monolithic LED array structure is between a first portion 64 of p-type semiconductor layer covering the mesa surface and a second portion 66 of p-type semiconductor layer covering the bulk semiconductor surface. is formed such that a potential barrier is provided at the top, the potential barrier surrounding the first portion 65 of the p-type semiconductor layer overlying the mesa surface.

Referring to FIG. 5 and the discussion above, the potential barrier is formed by selectively removing the third portion 61 of the p-type semiconductor layer surrounding the first portion 64 of the p-type semiconductor layer overlying the mesa surface. be able to. As shown in FIG. 5, the p-type semiconductor layer 60 can be selectively removed through the thickness of the layer to expose the underlying layer (electron blocking layer 50 in the embodiment of FIG. 5).

Referring to FIG. 7, the potential barrier may be formed by providing a p-type semiconductor layer 60 comprising an Al-containing III-nitride. The p-type semiconductor layer 60 is configured such that, for each LED precursor in the LED array precursor, a potential barrier is provided between the sidewall portion 63 of the p-type semiconductor layer and the first portion 65 of the p-type semiconductor layer. A higher concentration of Al is provided to be incorporated into the sidewall portions 63 of the p-type semiconductor layer 60 than in the first portion 64 of the p-type semiconductor layer covering the mesa surface 25 . The difference in Al composition between the sidewall portion 63 of the p-type semiconductor layer and the first portion 64 is such that the bandgap change is greater than kT eV (ie, greater than about 0.26 eV) at room temperature. can do.

For example, p-type semiconductor layer sidewall portions 63 may comprise p-type Al _x Ga _1-x N, where 2≦x≦50%, and p-type semiconductor layer mesa surface portions 65 may comprise p-type Al _y Ga _1-y N, where 1≦y≦15%.

As noted above, the sloping sidewalls of the second semiconductor layer 30 result in variations in the III-nitride deposition rate depending on whether the growth surface is a sloping sidewall or substantially parallel to the substrate. bring. Regarding the growth of the p-type semiconductor layer 60 , the difference in growth rate also affects the incorporation of Al into the p-type semiconductor layer 60 . Therefore, the sloped sidewall portion 63 can be formed with a higher Al content than the first portion 65 of the p-type semiconductor layer using the same deposition process. Therefore, the desired potential barriers for current confinement in the mesa surface portion of the monolithic LED structure can be formed without additional patterning steps.

Accordingly, an LED precursor according to one embodiment of the present disclosure can be provided.

Claims (18)

A method of forming a light emitting diode (LED) precursor comprising:
(a) forming a first semiconductor layer comprising a III-nitride on a substrate, said first semiconductor layer having a growth surface opposite said first semiconductor layer with respect to said substrate; forming a first semiconductor layer having
(b) selectively removing portions of the first semiconductor layer to form a mesa structure such that the growth surface of the first semiconductor layer comprises a mesa surface and a bulk semiconductor surface;
(c) forming a monolithic LED structure on the growth surface of the first semiconductor layer overlying the mesa surface and the bulk semiconductor surface, the monolithic LED structure comprising a plurality of layers; each layer comprising a III-nitride, the plurality of layers comprising:
a second semiconductor layer;
A monolithic LED structure comprising: an active layer overlying the second semiconductor layer, the active layer being configured to generate light; and a p-type semiconductor layer overlying the active layer. wherein a potential barrier is provided between a first portion of the p-type semiconductor layer overlying the mesa surface and a second portion of the p-type semiconductor layer overlying the bulk semiconductor surface. wherein the potential barrier surrounds the first portion of the p-type semiconductor layer overlying the mesa surface;
The method , wherein the second semiconductor layer comprises an undoped III-nitride . The second semiconductor layer is formed on the growth surface to include a first portion of the second semiconductor layer on the mesa surface of the first semiconductor layer and the first portion of the first semiconductor layer on the mesa surface. 2. The method of claim 1, further comprising providing sloped sidewall portions extending between a second portion of said second semiconductor layer over a bulk semiconductor surface. said p-type semiconductor layer comprising Al, and within sloped sidewall portions of said p-type semiconductor layer and between said first portion of said p-type semiconductor layer and said second portion of said p-type semiconductor layer; Al having a higher concentration than the first portion of the p-type semiconductor layer covering the mesa surface is incorporated into the sloped sidewall portion of the p-type semiconductor layer so as to form the potential barrier. 3. The method of claim 2 , wherein: The sloped sidewall portion of the p-type semiconductor layer comprises p-type Al _x Ga _1-x N with 2≦x≦50%, and the first portion of the p-type semiconductor layer comprises p-type Al. 4. The method of claim 3 , comprising _y Ga _1-y N, with 1≦y≦15%. 3. The method of claim 1 or 2, wherein a portion of said p-type semiconductor layer surrounding said first portion of said p-type semiconductor layer covering said mesa surface is selectively removed to expose said active layer underneath. Method. 6. The method of claim 5 , wherein a portion of said p-type semiconductor layer surrounding said first portion of said p-type semiconductor layer overlying said mesa surface is selectively removed using an anisotropic etchant. selectively removing portions of the first semiconductor layer to form the mesa structure,
selectively forming a mesa-defining mask layer on the first surface;
selectively removing unmasked portions of a first semiconductor layer to expose the bulk semiconductor surface of the first semiconductor layer;
and removing the mesa - defining mask layer. 8. The method of any one of claims 1-7, wherein the first semiconductor layer comprises GaN and the first semiconductor layer is an n-type semiconductor. 9. The method of any one of claims 1-8, wherein the height of the mesa structure between the mesa surface and the bulk semiconductor surface is at least 200 nm. A method of forming an LED array precursor, comprising:
(a) forming a first semiconductor layer comprising a III-nitride on a substrate, said first semiconductor layer having a growth surface opposite said first semiconductor layer with respect to said substrate; forming a first semiconductor layer having
(b) selectively removing portions of the first semiconductor layer to form a plurality of mesa structures such that the growth surface of the first semiconductor layer comprises a plurality of mesa surfaces and bulk semiconductor surfaces; and,
(c) forming a monolithic LED array structure on the growth surface of the first semiconductor layer overlying the mesa surface and the bulk semiconductor surface, the monolithic LED array structure comprising a plurality of layers; each layer comprising a Group III nitride, the plurality of layers comprising:
a second semiconductor layer;
A monolithic LED array comprising: an active layer on the second semiconductor layer, the active layer being configured to generate light; and a p-type semiconductor layer on the active layer. forming a structure, wherein a potential barrier is provided between each mesa portion of the p-type semiconductor layer overlying each mesa surface and a bulk portion of the p-type semiconductor layer overlying the bulk semiconductor surface. , the potential barrier surrounds each mesa portion of the p-type semiconductor layer covering the mesa surface;
The method , wherein the second semiconductor layer comprises an undoped III-nitride . A light emitting diode (LED) precursor comprising:
A first semiconductor layer comprising a III-nitride, said first semiconductor layer extending from a major surface of said first semiconductor layer to define a growth surface including a bulk semiconductor surface and a mesa surface. a first semiconductor layer comprising an overlying mesa structure;
A monolithic LED structure provided on the growth surface of the first semiconductor layer overlying the mesa surface and the bulk semiconductor surface, the monolithic LED structure comprising a plurality of layers, each layer formed of comprises a III-nitride, the plurality of layers comprising:
a second semiconductor layer;
A monolithic LED structure comprising: an active layer overlying the second semiconductor layer, the active layer being configured to generate light; and a p-type semiconductor layer overlying the active layer. and a potential barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface; a potential barrier surrounds the first portion of the p-type semiconductor layer overlying the mesa surface;
A light emitting diode (LED) precursor , wherein the second semiconductor layer comprises an undoped III-nitride . The second semiconductor layer comprises a first portion of the second semiconductor layer on the mesa surface of the first semiconductor layer and a second portion on the bulk semiconductor surface of the first semiconductor layer. 12. The LED precursor of claim 11 , comprising sloped sidewall portions extending between the second portion of the semiconductor layer. the p-type semiconductor layer comprises Al;
The sloped sidewall portion of the p-type semiconductor layer is the sloped sidewall portion of the p-type semiconductor layer between the first portion of the p-type semiconductor layer and the second portion of the p-type semiconductor layer. 13. The LED precursor of claim 12 , comprising a higher concentration of Al than the first portion of the p-type semiconductor layer overlying the mesa surface such that a potential barrier is formed therein. A portion of the p-type semiconductor layer surrounding the first portion of the p-type semiconductor layer covering the mesa structure is selectively removed to expose the active layer underneath . An LED precursor according to any one of the preceding claims. The LED precursor according to any one of claims 11-14 , wherein the height of the mesa structure between the mesa surface and the bulk semiconductor surface is at least 200 nm. The LED precursor according to any one of claims 11 to 15 , wherein the mesa surface has a surface area of 100 µm x 100 µm or less. 17. The mesa structure according to any one of claims 11 to 16 , wherein the height of the mesa structure between the mesa surface and the bulk semiconductor layer surface is at least equal to the cross-sectional width of the mesa surface of the mesa structure. of LED precursors. A light emitting diode array precursor comprising:
A first semiconductor layer comprising a III-nitride, said first semiconductor layer comprising a plurality of mesa structures, each mesa structure defining a growth surface including a bulk semiconductor surface and a plurality of mesa surfaces. a first semiconductor layer extending from a main surface of the first semiconductor layer, and
a monolithic LED array structure provided on the growth surface of the first semiconductor layer overlying each of the mesa surfaces and the bulk semiconductor surface, the monolithic LED array structure comprising a plurality of layers; each layer comprising a III-nitride, the plurality of layers comprising:
a second semiconductor layer;
A monolithic LED array comprising: an active layer on the second semiconductor layer, the active layer being configured to generate light; and a p-type semiconductor layer on the active layer. wherein a potential barrier is provided between each mesa portion of the p-type semiconductor layer overlying each of the mesa surfaces and a bulk portion of the p-type semiconductor layer overlying the bulk semiconductor surface; a potential barrier surrounds each of the mesa portions of the p-type semiconductor layer overlying the mesa surface;
A light emitting diode array precursor , wherein the second semiconductor layer comprises an undoped III-nitride .

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