JP7324896B2 - Receiving device and data receiving method - Google Patents

Description

The present invention relates to a receiving device and a data receiving method.

In order to realize high-speed data communication, a data communication system in which three or more wires constitute one lane is under study. An example of such technology is MIPI C-PHY (Mobile Industry Processor Interface C-PHY).

A large data valid window is desirable to improve the reliability of data communication, and data communication systems are designed to extend the data valid window.

In one embodiment, the receiving device includes a plurality of differential receivers each outputting a single-ended signal corresponding to a potential difference between two different wires among the three or more wires, and output from each of the plurality of differential receivers. a plurality of delay compensating circuits configured to delay the single-ended signal that is output by the plurality of delay compensating circuits; and a plurality of latch circuits configured to respectively latch the plurality of compensated single-ended signals in synchronization with the recovered clock signal. The multiple differential receivers include a first differential receiver that outputs a first single-ended signal according to a potential difference between a first wire and a second wire of the three or more wires. The plurality of delay compensation circuits includes a first delay compensation circuit that generates a first compensated single-ended signal among the plurality of compensated single-ended signals by delaying the first single-ended signal. A delay time of the first delay compensation circuit used for receiving the first symbol is controlled according to the potential difference between the first wire and the second wire when receiving the second symbol transmitted before the first symbol.

In another embodiment, the receiving device includes a first differential receiver that outputs a first single-ended signal according to the potential difference between the first wire and the second wire, and a first differential receiver that outputs a first single-ended signal according to the potential difference between the second wire and the third wire. a second differential receiver that outputs two single-ended signals; a third differential receiver that outputs a third single-ended signal according to the potential difference between the third wire and the first wire; the second single-ended signal and the third single a first state determination circuit that generates a first state signal indicating the state of the potential difference between the first wire and the second wire according to the end signal.

In yet another embodiment, the receiving method includes outputting a first single-ended signal in response to a potential difference between the first wire and the second wire, and outputting a second single-ended signal in response to a potential difference between the second wire and the third wire. outputting a signal; outputting a third single-ended signal according to a potential difference between the second wire and the third wire; and delaying the first single-ended signal, the second single-ended signal and the third single-ended signal. to generate a first compensated single-ended signal, a second compensated single-ended signal, and a third compensated single-ended signal; and a first compensated single-ended signal, a second compensated single-ended signal, and a third generating a recovered clock signal according to the compensated single-ended signal; and generating a first compensated single-ended signal, a second compensated single-ended signal, and a third compensated single-ended signal in synchronization with the recovered clock signal. and latching to. The delay time given to the first single-ended signal in generating the first compensated single-ended signal in the reception of the first symbol is the first wire and the second wire in the reception of the second symbol transmitted before the first symbol. is controlled according to the potential difference between

1 is a block diagram showing the configuration of a data communication system in one embodiment; FIG. Fig. 4 is a timing diagram showing possible transitions in the potentials V _A , V B , V _C of wires A, _B , C; FIG. 5 is a timing diagram superimposing possible transitions of potentials V _A , V _B , V _C on wires A, B, C; FIG. 1 is a timing chart showing possible transitions in potential differences _{V A} −V _B , V _B −V _C , V _C −V _A ; It is a circuit diagram which shows the structure of the receiving apparatus in one Embodiment. States of potential differences V _A −V _B , V _B −V _C , V _C −V _A and zero crossings of potential differences _V A −V _B , V _B −V _C , V _C −V _A in reception of previous and current symbols 4 is a table showing the relationship with timing; 6 is a table showing the operation of the delay compensation circuit in the receiver shown in FIG. 5; 5 is a table showing the relationship between the state of each wire, the logic value of a single-ended signal output by a differential receiver, and the states of potential differences V _A -V _B , V _B -V _C , and V _C -V _A ; FIG. 11 is a circuit diagram showing the configuration of a receiving device in another embodiment; 10 is a table showing the operation of the delay compensation circuit in the receiver shown in FIG. 9; FIG. 11 is a circuit diagram showing the configuration of a receiving device according to still another embodiment; States of potential differences V _A −V _B , V _B −V _C , V _C −V _A and zero crossings of potential differences _V A −V _B , V _B −V _C , V _C −V _A in reception of previous and current symbols Fig. 3 is a table showing the relationship between timing and differential receiver delay; 12 is a table showing the operation of the delay compensation circuit in the receiver shown in FIG. 11;

In one embodiment, a data communication system comprises a transmitting device 1 and a receiving device 2, as shown in FIG. In this embodiment, the data communication system operates according to the MIPI C-PHY standard, but is not limited to this. A transmitter 1 is connected to a receiver 2 via a lane 3 . In one embodiment, transmitter 1 and receiver 2 may be integrated on separate semiconductor chips.

In this data communication system, Lane 3 includes three wires A, B, C. Each of the wires A, B, C is allowed to take on three potentials. These three potentials are hereinafter referred to as "H", "M", and "L", respectively. When data transmission is performed, in each UI (unit interval), one of wires A, B, and C is set to "H" level, the other one is set to "M" level, and the remaining one is set to "M" level. It is set to "L" level. Therefore, the total number of combinations of potentials on wires A, B, C is six. A symbol transmitted to each UI is represented by a combination of potentials on wires A, B, and C. FIG. In the following, the potentials of wires A, B, and C may be referred to as _VA , _VB , and _VC, respectively.

As shown in FIG. 2, when transmitting a symbol after transmitting the next symbol, the potentials V _A , V B , V C of the wires A, _B , _C are equal to the potential V A transition is made to a combination different from the combination of _A 1 , V _B , and V _C . FIG. 3 shows that when the potentials V A , V B , and V C of wires _A , _B , and _C are at “H”, “M”, and “L” levels, respectively, at the time of transmission of a certain symbol, the next symbol All possible combinations of transitions of the potentials V _A , V _B , V _C of the wires A, B, C during transmission of are superimposed.

In data communication according to the MIPI C-PHY standard, based on the potential difference V _A -V B between wires A and _B , the potential difference V B -V C between wires _B and _C , and the potential difference V C -V A between wires _C and _A The generated three single-ended signals are generated by three differential receivers, and data is received by latching the three single-ended signals. The three single-ended signals are latched in synchronization with the recovered clock signal recovered from the three single-ended signals.

Referring to FIG. 4 showing possible transitions of potential differences V _A −V _B , V _B −V _C , V _C −V _A , potential differences _{V A} −V _B , V _B −V _C , V _C −V _A Each can have four states: "strong 1", "weak 1", "weak 0", and "strong 0". Of these four states, "strong 1" and "weak 1" correspond to logic "1", and "weak 0" and "strong 0" correspond to logic "0".

“Strong 1” is a state in which potential differences V _A −V _B , V _B −V _C , and V _C −V _A are positive voltages with relatively large absolute values. For example, when the potential V _A is at the "H" level and the potential V _B is at the "L" level, the potential difference V _A -V _B is "strong 1".

“Weak 1” is a state in which potential differences V _A −V _B , V _B −V _C , and V _C −V _A are positive voltages with relatively small absolute values. For example, when the potentials V _A and V _B are at the “H” level and “M” level, respectively, and when the potentials V _A and V _B are at the “M” level and the “L” level, respectively, the potential difference V _A − _VB goes into the "weak 1" state.

“Weak 0” is a state in which potential differences V _A −V _B , V _B −V _C , and V _C −V _A are negative voltages with relatively small absolute values. For example, when the potentials V _A and V _B are at the “M” level and “H” level, respectively, and when the potentials V _A and V _B are at the “L” level and “M” level, respectively, the potential difference V _A − _VB goes to the "weak 0" state.

Finally, "strong 0" is the state where the potential differences V _A -V _B , V _B -V _C and V _C -V _A are negative voltages with relatively large absolute values. For example, when the potentials V _A and V _B are at the "L" level and "H" level, respectively, the potential difference V _A -V _B is in a "strong 0" state.

In the following, the two states "weak 0" and "weak 1" in which the absolute value of the potential difference is relatively small are collectively referred to as the state "weak", and the two states "strong0" in which the absolute value of the voltage is relatively large. and "strong 1" may be collectively referred to as the state "strong".

At each transmission of the symbol, the potential differences V _A −V _B , V _B −V _C , V _C −V _A transition among “strong 1”, “weak 1”, “weak 0”, “strong 0”. . Zero crossings occur in the differences V _A −V _B , V _B −V _C and V _C −V _A when the logic value transitions between “1” and “0”. The timing at which zero cross occurs is called zero cross timing. The reproduced clock signals described above are generated in synchronization with the zero cross timings of the differences V _A -V _B , V _B -V _C and V _C -V _A .

In communication according to the MIPI C-PHY standard, the zero cross timings of the potential differences V _A −V _B , V _B −V _C , and V _C −V _A are, in principle, distributed into three types. The zero-crossing timing is earliest at transitions from "weak 1" to "strong 0" and from "weak 0" to "strong 1". This zero cross timing is hereinafter referred to as "Fast". The transition from "strong 1" to "weak 0" and the transition from "weak 1" to "strong 0" have the slowest zero cross timing. This zero cross timing is hereinafter referred to as "Slow". Transitions between "weak 0" and "weak 1" and transitions between "strong 0" and "strong 1" have intermediate zero-crossing timings. This zero cross timing is hereinafter referred to as "Mid".

In a configuration in which a recovered clock signal is recovered from three single-ended signals corresponding to potential differences _{V A} −V _B , V _B −V _C , and V _C −V _A , when the zero-crossing timing is dispersed, clock pulses of the recovered clock signal are generated. Timing is also distributed. This can reduce the data valid window. As will be described in detail below, the receiving device 2 of this embodiment is configured to suppress the reduction of the data valid window due to the dispersion of the zero-crossing timings.

5, the receiving device 2 includes input terminals 11 ₁ to 11 ₃ , differential receivers 12 ₁ to 12 ₃ , delay compensation circuits 13 ₁ to 13 ₃ , hold delay circuits 14 ₁ to 14 ₃ , latches 15 ₁ to 15 ₃ , and a clock recovery circuit 16 .

Input terminals 11 ₁ to 11 ₃ are connected to wires A, B, and C, respectively, and receive signals transmitted on wires A, B, and C from transmitter 1 .

Differential receivers 12 ₁ to 12 ₃ generate single-ended signals S _AB , S _{BC , and S BC corresponding to potential differences V A −V B , V B −V C} , and V _C −V _{A ,} respectively. to generate Specifically, differential receiver 12 ₁ has a first input to which wire A is connected and a second input to which wire B is connected, and has a logic value corresponding to the potential difference V _A -V _B . It outputs a single-ended signal _SAB . Similarly, differential receiver ₁₂₂ has a first input to which wire B is connected and a second input to which wire C is connected, and has a single input having a logic value corresponding to the potential difference V _B −V _C . It outputs an end signal _SBC . A differential receiver ₁₂₃ , having a first input connected to wire C and a second input connected to wire A, provides a single-ended signal S having a logic value corresponding to the potential difference V _C −V _A Output _CA. The single-ended signal S _A-B takes the logic value "1" when the potential difference V _A -V B of wires A, _B is "strong 1" or "weak 1", and "strong 0" or "weak 0". ", it takes the logical value "0". The same applies to the single-ended signals S _BC and S _C-A .

The delay compensation circuits 13 ₁ to 13 ₃ are configured to apply delays to the single-ended signals S _AB , S _BC , S _BC to compensate for the zero-crossing timing dispersion described above. In this embodiment, the delay compensation circuit _13-1 includes a delay circuit _21-1 , a selector _24-1 , and an XOR circuit _25-1 . The delay circuit ₂₁₁ is configured to delay the single-ended signal S _AB by a delay time D _A . The selector _24-1 has an input D0 connected to the output of the differential receiver _12-1 and an input D1 connected to the output of the delay circuit _21-1 . The selector _24-1 selects either the single _{-ended signal S AB} received from the differential receiver _12-1 or the output signal of the delay circuit _21-1 according to the output signal of the XOR circuit _25-1 , and selects the selected signal. to output

The delay compensation circuits 13 ₂ and 13 ₃ are similarly configured. _The delay compensation circuit _13-2 includes _a delay circuit _21-2 , a selector _24-2 , and _an XOR circuit _{25-2 .} and The delay time of the delay circuits 21 ₂ and 21 ₃ is _DA . Details of the operation of the delay compensation circuits 13 ₁ to 13 ₃ will be described later. The single-ended signals output from the delay compensation circuits 13 ₁ to 13 ₃ are hereinafter referred to as post-compensation single-ended signals Comp (AB), Comp (BC), and Comp (CA), respectively. .

The hold delay circuits 14 ₁ to 14 ₃ provide delays that can ensure the hold times of the latches 15 ₁ to 15 ₃ , respectively, to the compensated single-ended signals Comp (AB), Comp (BC), and Comp ( CA). The single-ended signals output from hold delay circuits 14 ₁ - 14 ₃ are the logic values of the symbols preceding the symbols transmitted by the signals currently input to differential receivers 12 ₁ - 12 ₃ from wires A, B, and C. These values are denoted as pre-symbol single-ended signals Prev(AB), Prev(BC), and Prev(CA), respectively.

The latches 15 ₁ to 15 ₃ synchronize the preceding symbol single-ended signals Prev (AB), Prev (BC), and Prev (CA) with the recovered clock signal RCLK supplied from the clock recovery circuit 16, respectively. , and outputs latched data signals Data (AB), Data (BC), and Data (CA) having latched logic values.

The clock recovery circuit 16 receives the compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) output from the delay compensation circuits 13 ₁ to 13 ₃ and recovers the clock. , to generate the recovered clock signal RCLK. The generated recovered clock signal RCLK is supplied to latches 15 ₁ to 15 ₃ . In one embodiment, the clock recovery circuit 16 is synchronized with the earliest timing among the timings at which the compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) are inverted. It may be configured to output a clock pulse of the recovered clock signal RCLK.

In order to compensate for the zero-cross timing dispersion, in this embodiment, the delay times of the delay compensation circuits 13 ₁ to 13 ₃ used in receiving each symbol are equal to the potential difference in receiving the symbol transmitted immediately before each symbol. It is controlled according to V _A -V _B , V _B -V _C and V _C -V _A . More specifically, the delay time of the delay compensation circuit ₁₃₁ used in receiving a certain symbol is such that the potential difference V _A −V _B in receiving the previously transmitted symbol is either “weak” or “strong”. is controlled depending on whether Similarly, the delay time of the delay compensation circuit ₁₃₂ used in receiving a certain symbol determines whether the potential difference V _B −V _C in receiving the previously transmitted symbol is “weak” or “strong”. The delay time of the delay compensating circuit ₁₃₃ used in receiving a certain symbol is controlled depending on whether the potential difference V _C −V _A in receiving the previously transmitted symbol is either “weak” or “strong”. is controlled depending on whether Such control is based on considerations as described below.

As can be seen from the table shown in FIG. 6, the zero-crossing timings of potential differences _{V A} −V _B , V _B −V _C , and V _C −V _A are determined by the potential differences V _A −V _B , Each of V _B -V _C and V _C -V _A depends on whether it is "weak" or "strong". Regarding the potential difference V _A −V _B , when the potential difference V _A −V _B in the reception of the previous symbol and the current symbol is both “weak” and when both are “strong”, the potential difference V _A −V The zero cross timing of _B is "Mid". When the potential difference V _A -V _B in receiving the previous symbol is "strong" and the potential difference V _A -V _B in receiving the current symbol is "weak", the zero cross timing of the potential difference V _A -V _B is "Slow". is. Further, when the potential difference V _A -V _B in receiving the previous symbol is "weak" and the potential difference V _A -V _B in receiving the current symbol is "strong", the zero cross timing of the potential difference V _A -V _B is " Fast”. The same applies to potential differences V _B -V _C and V _C -V _A .

_In this _{embodiment ,} the _{delay compensation} circuit _{13 1} A delay time of ~13 ₃ is controlled.

Specifically, as shown in FIG. 7, when the potential difference V _A −V _B in the reception of the previous symbol is “weak”, the delay compensation circuit 13 ₁ delays the single-ended signal S _AB by the delay time D _A. The resulting signal is output as a compensated single-ended signal Comp(AB). Such an operation is realized by the selector _24-1 of the delay compensation circuit _13-1 selecting the output signal of the delay circuit _21-1 . On the other hand, when the potential difference V _A −V _B in the reception of the previous symbol is “strong”, the delay compensation circuit 13 ₁ directly converts the single-ended signal S _AB received from the differential receiver 12 ₁ into the post-compensation single-ended signal Comp. Output as (AB).

According to such an operation, it is possible to generate the compensated single-ended signal Comp(AB) while compensating for the zero-cross timing dispersion of the potential difference V _A -V _B . For example, when the time difference between the timing "Fast" and the timing "Mid" and the time difference between the timing "Mid" and the timing "Slow" are the same, the delay time _DA of the delay circuit ₂₁₁ is the time difference , it is possible to generate the compensated single-ended signal Comp(A−B) in which the potential difference V _A −V _B has two effective zero-crossing timings, “Mid” and “Slow”. . Even if the time difference between the timing "Fast" and the timing "Mid" and the time difference between the timing "Mid" and the timing "Slow" are not the same, by properly setting the delay time _DA , for example, the timing Compensate for the variance of the zero-crossing timing of the potential difference _VA - _VB by setting it to the average of the time difference between "Fast" and timing "Mid" and the time difference between timing "Mid" and timing "Slow". can be done.

The delay times of the delay compensation circuits 13 ₂ and 13 ₃ are similarly controlled. When the potential difference V _B -V _C in the reception of the previous symbol is "weak", the delay compensating circuit ₁₃₂ delays the single-ended signal S _B-C by the delay time D _A to generate the compensated single-ended signal. Output as Comp(BC). On the other hand, when the potential difference V _B -V _C in the reception of the previous symbol is "strong", the delay compensation circuit 13 ₂ directly converts the single-ended signal S _BC received from the differential receiver 12 ₂ into the post-compensation single-ended signal Comp. Output as (BC). Further, when the potential difference V _C -V _A in the reception of the previous symbol is "weak", the delay compensation circuit ₁₃₃ delays the single-ended signal S _C-A by the delay time D _A to compensate for the signal obtained by delaying the single-ended signal S C -A. Output as an end signal Comp(CA). On the other hand, when the potential difference V _C -V _A in the reception of the previous symbol is "strong", the delay compensation circuit 13 ₃ directly converts the single-ended signal S _C-A received from the differential receiver 12 ₃ into the post-compensation single-ended signal Comp. Output as (CA). According to such an operation, the compensated single-ended signals Comp(BC) and Comp(CA) can be generated while compensating for the dispersion of the zero-cross timing.

In this embodiment, whether the potential differences V _A −V _B , V _B −V _C , and V _C −V _A in reception of the previous symbol are “weak” or “strong” is determined by the potential differences V _A −V _B , Instead of directly detecting V _B −V _C and V _C −V _A , it is calculated by logical operation of pre-symbol single-ended signals Prev(A−B), Prev(BC), Prev(CA). be. Determination of the states of potential differences V _A −V _B , V _B −V _C , and V _C −V _A by logical operations will be described below.

Referring to FIG. 8, the possible states of wires A, B, C are: There are six. These states are described as states #1 to #6, respectively. For example, state #1 means that wires A, B and C are at potentials "H", "M" and "L" respectively.

Whether the potential difference V _A -V _B is "weak" or "strong" in receiving a symbol depends on the single-ended signal S _BC output from the differential receivers 12 ₂ and 12 ₃ in receiving the symbol. , SC _-A . If the potential difference V _A -V _B is "weak", then either wire A or B will take the potential "M". This is the logical value of the single-ended signal S B _-C corresponding to the potential difference V _B -V _C on wires B and C, and the single-ended signal S C-A corresponding to the potential difference V _C -V _A on wires _{C and A.} means that one of the logical values of is "1" and the other is "0". For example, if wire A takes potential "M", wires A, B, and C are in either state #3 or #4. In state #3, the single-ended signals S _BC and S _C-A are respectively "1" and "0", and in state #4 the single-ended signals S _BC and S _C-A are They are "0" and "1", respectively. Therefore, if the exclusive OR of the logical values of the single-ended signals S _BC and S _C-A is "1", it can be determined that the potential difference V _A -V _B is "weak".

Similarly, whether the potential difference V _B −V _C is “weak” or “strong” depends on the single-ended signals S _{C−A and S C−A} output from the differential receivers 12 ₃ and 12 ₁ upon reception of the symbol. It can be determined from the logical value of _AB . If the exclusive OR of the logical values of the single _{-ended signals S CA} and S _AB is "1", it can be determined that the potential difference V _B -V _C is "weak".

Furthermore, whether the potential difference V _C -V _A is "weak" or "strong" depends on the single-ended signals S _AB and S _B output from the differential receivers 12 ₁ and 12 ₂ upon reception of the symbol. It can be determined from the logical value of _-C . If the exclusive OR of the logical values of the single _{-ended signals S AB} and S _BC is "1", it can be determined that the potential difference V _C -V _A is "weak".

As can be understood from the above discussion, whether the potential differences V _A −V _B , V _B −V _C , and V _C −V _A in reception of the previous symbol are “weak” or “strong” depends on whether the previous symbol It can be determined by logical operation of single-ended signals Prev(AB), Prev(BC), Prev(CA). The delay compensation circuits 13 ₁ , 13 ₂ , 13 ₃ shown in FIG. It is configured to determine whether _A -V _B , V _B -V _C , and V _C -V _A are "weak" or "strong" and control the respective delay times.

Specifically, the delay time of the delay compensation circuit ₁₃₁ is controlled according to the previous symbol single-ended signals Prev(AB) and Prev(BC). The XOR circuit 25 ₁ of the delay compensation circuit 13 ₁ is a state discrimination circuit that generates the previous symbol state signal Weak_P (AB) based on the previous symbol single-ended signals Prev (AB) and Prev (BC). Operate. The previous symbol state signal Weak_P(AB) indicates the state of the potential difference V _A -V _B , specifically whether the potential difference V _A -V _B is "weak" or "strong". The previous symbol state signal Weak_P (AB) has a logic value of the exclusive OR of the previous symbol single-ended signals Prev (BC) and Prev (CA), and the potential difference in the reception of the previous symbol is If V _A -V _B is "weak", it takes a logic "1".

When the previous symbol state signal Weak_P(AB) is "1", the selector _{24_1} selects the input D1 and outputs the output signal of the delay circuit _{21_1} as the compensated single-ended signal Comp(AB). do. On the other hand, when the previous symbol state signal Weak_P (A−B) is “0”, the selector 24 ₁ selects the input D 1 to convert the single-ended signal S _AB received from the differential receiver 12 ₁ into a compensated single signal. Output as an end signal Comp (AB). As a result, the operation of inserting a delay of delay time D _A into the single-ended signal S _AB when the potential difference V _A -V _B of the previous symbol is "weak" as shown in FIG. 7 is realized.

Similarly, the delay time of the delay compensation circuit ₁₃₂ is controlled according to the previous symbol single-ended signals Prev(CA) and Prev(AB). The XOR circuit 25 ₂ of the delay compensation circuit 13 ₂ is a state discrimination circuit that generates the previous symbol state signal Weak_P (BC) based on the previous symbol single-ended signals Prev (CA) and Prev (AB). Operate. The previous symbol state signal Weak_P (BC) has a logical value of the exclusive OR of the previous symbol single-ended signals Prev (CA) and Prev (AB). If V _B -V _C is "weak", it takes a logic value of "1". The selector _{24_2} outputs the output signal of the delay circuit _{21_2} as the post-compensation single-ended signal Comp(BC) when the previous symbol state signal Weak_P(BC) is "1", and when it is "0". In some cases, the single-ended signal _SBC received from the differential receiver ₁₂₂ is output as the compensated single-ended signal Comp(BC). This implements an operation of inserting a delay of delay time D _A into the single-ended signal S _BC when the potential difference V _B -V _C of the previous symbol is "weak".

Furthermore, the delay time of the delay compensation circuit ₁₃₃ is controlled according to the previous symbol single-ended signals Prev(AB) and Prev(BC). The XOR circuit _25-3 of the delay compensation circuit _13-3 is a state discrimination circuit that generates the previous symbol state signal Weak_P (CA) based on the previous symbol single-ended signals Prev (AB) and Prev (BC). Operate. The previous symbol state signal Weak_P (CA) has a logic value of the exclusive OR of the previous symbol single-ended signals Prev (AB) and Prev (BC), and the potential difference in the reception of the previous symbol is If V _C -V _A is "weak", it takes the value of logic "1". The selector _{24_3} outputs the output signal of the delay circuit _{21_3} as the post-compensation single-ended signal Comp(CA) when the previous symbol state signal Weak_P(CA) is "1", and when it is "0". In some cases, the single-ended signal SC _-A received from the differential receiver ₁₂₃ is output as a compensated single-ended signal Comp(CA). This implements an operation of inserting a delay of delay time D _A into the single-ended signal S _C-A when the potential difference V _C -V _A of the previous symbol is "weak".

The compensated single-ended signals Comp(A−B), Comp(BC), and Comp(CA) output from the delay compensation circuits 13 ₁ , 13 ₂ , and 13 ₃ operating in this way are the clock recovery circuit 16 , and used to generate the recovered clock signal RCLK. The timing at which the clock pulse of the recovered clock signal RCLK is output when each symbol is received is one of the timings at which the compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) are inverted. Synchronized with the earliest timing. Through such an operation, the recovered clock signal RCLK in which the dispersion of the zero cross timings of the potential differences V _A −V _B , V _B −V _C , and V _C −V _A is compensated is generated and supplied to the latches 15 ₁ to 15 ₃ . be.

As described above, in the present embodiment, it is detected whether the potential differences V _A −V _B , V _B −V _C , and V _C −V _A are “weak” or “strong”. The delay times of the delay compensation circuits 13 ₁ , 13 ₂ and 13 ₃ are controlled according to the result. As a result, compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) in which zero-cross timing dispersion is compensated are generated. By generating the recovered clock signal RCLK from the compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) thus generated, the receiver 2 of the present embodiment can effectively extend the data valid window.

In one embodiment shown in FIG. 9, the receiving device 2 has the states of the potential differences V _A −V _B , V _B −V _C , V _C −V _A on reception of the previous symbols, as well as the potential differences V _A on reception of the current symbol. -V _B , V _B -V _C and V _C -V _A are configured to control the delay times of the delay compensation circuits 13 ₁ , 13 ₂ and 13 ₃ according to the states. Specifically, in this embodiment, the receiving device 2 additionally includes delay circuits 17 ₁ , 17 ₂ , 17 ₃ and the configurations of the delay compensation circuits 13 ₁ , 13 ₂ , 13 ₃ are changed. Other configurations are the same as those of the receiver 2 shown in FIG.

Delay circuits 17 ₁ , 17 ₂ and 17 ₃ delay single-ended signals S _AB , S _BC and S _C-A output from differential receivers 12 ₁ , 12 ₂ and 12 ₃ respectively. Delayed single-ended signals Dly (AB), Dly (BC) and Dly (CA) are generated and supplied to delay compensation circuits 13 ₁ , 13 ₂ and 13 ₃ . Delay circuits 17 ₁ , 17 ₂ , 17 ₃ provide delay times of delay compensating circuits 13 ₁ , 13 ₂ , 13 ₃ according to potential differences V _A −V _B , V _B −V _C , V _C −V _A of the current symbol. is provided to ensure time to control the In the following, the single-ended signals S _{AB , S BC} , and S _C- A output from the differential receivers 12 ₁ , 12 ₂ , and 12 ₃ are the potential differences V _A −V _B and _V of the current symbol, respectively. Single-ended signals _{S AB} , S BC output from differential receivers 12 ₁ , 12 ₂ , 12 ₃ to clarify that they have logic values of B −V _C , _{V C −V A} . , SC _-A are sometimes referred to as current-symbol single-ended signals Crt(AB), Crt(BC), and Crt(CA), respectively.

In this embodiment, the delay compensation circuits 13 ₁ , 13 ₂ , 13 ₃ , in addition to the previous symbol single-ended signals Prev(AB), Prev(BC), Prev(CA), the current symbol single-ended Each delay time is controlled according to the signals Crt(AB), Crt(BC) and Crt(CA).

Specifically, in this embodiment, the delay compensation circuit _13-1 includes delay circuits _21-1 and _22-1 , a selector _24-1 , and XOR circuits _25-1 and _26-1 . The delay circuits 21 ₁ and 22 ₁ have delay times D _A and D _B respectively. The delay circuit _21-1 is connected to the output of the delay circuit _17-1 , and the delay circuit _22-1 is connected to the output of the delay circuit _21-1 . Selector ₂₄₁ has three inputs D0, D1 and D2. The input D0 of the selector _24-1 is connected to the output of the delay circuit _17-1 , the input D1 is connected to the output of the delay circuit _21-1 , and the input D2 is connected to the output of the delay circuit _22-1 . The delay compensating circuit 13 ₁ configured in this manner gives a delay time of 0, D _A , or D _A +D _B to the delayed single-ended signal Dly(A−B) output from the delay circuit 17 ₁ . be able to.

The XOR circuit ₂₅₁ operates as a state discrimination circuit that generates a previous symbol state signal Weak_P (AB) based on the previous symbol single-ended signals Prev (BC) and Prev (CA). ₁ operates as a state determination circuit that generates a current symbol state signal Weak_A (AB) based on the current symbol single-ended signals Crt(BC) and Crt(CA). The previous symbol state signal Weak_P(AB) is generated to have a logic value of the exclusive OR of the previous symbol single-ended signals Prev(BC) and Prev(CA). As can be seen from the discussion above, the previous symbol state signal Weak_P(AB) will be set to "1" when the potential difference AB is "weak" in the reception of the previous symbol. . Similarly, the current symbol state signal Weak_C(AB) is generated to have the logic value of the exclusive OR of the current symbol single-ended signals Crt(BC) and Crt(CA). The current symbol state signal Weak_C(AB) will be set to "1" when the potential difference AB is "weak" in the reception of the current symbol.

Selector 24 ₁ selects any one of inputs D0, D1 and D2 according to previous symbol state signal Weak_P (AB) and current symbol state signal Weak_C (AB) output from XOR circuits 25 ₁ and 26 ₁ respectively. is selected, and the single-ended signal input to the selected input is output as the compensated single-ended signal Comp(AB).

The delay compensation circuit ₁₃₂ is similarly configured and operates similarly. The delay compensation circuit 13 ₂ includes delay circuits 21 ₂ and 22 ₂ , a selector 24 ₂ and XOR circuits 25 ₂ and 26 ₂ . The delay circuits 21 ₂ and 22 ₂ have delay times D _A and D _B respectively. The XOR circuit ₂₅₂ generates a previous symbol state signal Weak_P (BC) having a logic value of the exclusive OR of the previous symbol single-ended signals Prev (CA) and Prev (AB). The XOR circuit ₂₆₂ generates a current symbol state signal Weak_A(BC) having a logic value of the exclusive OR of the current symbol single-ended signals Crt(CA) and Crt(AB). The selector ₂₄₂ selects one of the inputs D0, D1, and D2 according to the previous symbol state signal Weak_P (BC) and the current symbol state signal Weak_A (BC), and selects the single signal input to the selected input. The end signal is output as a compensated single-ended signal Comp(BC).

Furthermore, the delay compensation circuit ₁₃₂ is similarly configured and operates similarly. The delay compensation circuit 13 ₃ includes delay circuits 21 ₃ and 22 ₃ , a selector 24 ₃ , and XOR circuits 25 ₃ and 26 ₃ . The delay circuits 21 ₃ and 22 ₃ have delay times D _A and D _B respectively. The XOR circuit ₂₅₃ generates a previous symbol state signal Weak_P(CA) having a logic value of exclusive OR of the previous symbol single-ended signals Prev(AB) and Prev(BC). The XOR circuit ₂₆₃ generates a current symbol state signal Weak_A (CA) having a logic value of the exclusive OR of the current symbol single-ended signals Crt(AB) and Crt(BC). The selector ₂₄₃ selects one of the inputs D0, D1, and D2 according to the previous symbol state signal Weak_P (CA) and the current symbol state signal Weak_A (CA), and selects the single signal input to the selected input. The end signal is output as a compensated single-ended signal Comp(CA).

As shown in FIG. 10, in this embodiment, the delay times of the delay compensation circuits 13 ₁ , 13 ₂ and 13 ₃ are equal to the potential differences V _A −V _B , V _B −V _C and V _C −V in the reception of the previous symbol. _A plus the potential differences V _A −V _B , V _B −V _C , V _C −V _A at the reception of the current symbol. First, control of the delay time of the delay compensation circuit ₁₃₁ will be described below.

The delay time of the delay compensation circuit 13 ₁ is determined by whether the potential difference V _A −V _B in receiving the previous symbol and the potential difference V _A −V _B in receiving the current symbol are “weak” or “strong”, respectively. controlled according to When the potential difference V _A -V _B in receiving the previous symbol and the potential difference V _A -V _B in receiving the current symbol are both "weak", the delay time of the delay compensation circuit 13 ₁ is set to D _A . Specifically, the previous symbol state signal Weak_P (AB) and the current symbol state signal Weak_C (AB) output from the XOR circuits 25 ₁ and 26 ₁ are both set to "1". In this case, the selector ₂₄₁ selects the input D1 and outputs the single-ended signal input to the input D1 as the compensated single-ended signal Comp(AB). As a result, the delay time given to the delayed single-ended signal Dly (AB) by the delay compensation circuit ₁₃₁ is controlled to _DA .

The delay time of the delay compensation circuit _13-1 is also set to D _A when the potential difference V _A -V _B in the reception of the previous symbol and the potential difference V _A -V _B in the reception of the current symbol are both "strong". Specifically, the previous symbol state signal Weak_P (AB) and the current symbol state signal Weak_C (AB) output from the XOR circuits 25 ₁ and 26 ₁ are both set to "0". In this case, the selector ₂₄₁ selects the input D1 and outputs the single-ended signal input to the input D1 as the compensated single-ended signal Comp(AB). As a result, the delay time given to the delayed single-ended signal Dly (AB) by the delay compensation circuit ₁₃₁ is controlled to _DA .

When the potential difference V _A -V _B in receiving the previous symbol is "strong" and the potential difference V _A -V _B in receiving the current symbol is "weak", the delay time of the delay compensation circuit _13-1 is set to 0. be. Specifically, the previous symbol state signal Weak_P (AB) and the current symbol state signal Weak_C (AB) are set to "0" and "1", respectively. In this case, the selector ₂₄₁ selects the input D0 and outputs the single-ended signal input to the input D0 as the compensated single-ended signal Comp(AB). As a result, the delay time given to the delayed single-ended signal Dly(AB) by the delay compensation circuit ₁₃₁ is controlled to zero.

When the potential difference V _A -V _B in receiving the previous symbol is "weak" and the potential difference V _A -V _B in receiving the current symbol is "strong", the delay time of the delay compensation circuit _13-1 is D _A +D _B is set. Specifically, the previous symbol state signal Weak_P(AB) and the current symbol state signal Weak_C(AB) are set to "1" and "0", respectively. In this case, the selector ₂₄₁ selects the input D2 and outputs the single-ended signal input to the input D2 as the compensated single-ended signal Comp(AB). As a result, the delay time given to the delayed single-ended signal Dly (A−B) by the delay compensation circuit 13 ₁ is controlled to D _A +D _B .

According to such an operation, the post-compensation single-ended signal Comp(AB) can be generated while further compensating for the dispersion of the zero-cross timings of the potential difference V _A -V _B . For example, when the time difference between the timing "Fast" and the timing "Mid" and the time difference between the timing "Mid" and the timing "Slow" are the same, the delay times D _A of the delay circuits 21 ₁ and 22 ₁ , Generating a compensated single-ended signal Comp(A−B) such that the effective zero-crossing timing of the potential difference V _A −V _B is one type of “Slow” by matching D _B with the time difference. can be done. Even if the time difference between the timing "Fast" and the timing "Mid" and the time difference between the timing "Mid" and the timing "Slow" are not the same, by appropriately setting the delay times D _A and D _B , For example, by setting the average of the time difference between the timing "Fast" and the timing "Mid" and the time difference between the timing "Mid" and the timing "Slow", the variance of the zero cross timing of the potential difference V _A -V _B is can be compensated.

The delay time of the delay compensating circuit ₁₃₂ is similarly controlled. The delay compensation circuit ₁₃₂ is controlled depending on whether the potential difference V _B -V _C in the reception of the previous symbol and the potential difference V _B -V _C in the reception of the current symbol are "weak" or "strong", respectively. be done.

Specifically, when the potential difference V _B −V _C in the reception of the previous symbol and the potential difference V _B −V _C in the reception of the current symbol are both “weak” or both are “strong”, the selector 24 ₂ selects the input D1 and outputs the single-ended signal input to the input D1 as the compensated single-ended signal Comp(BC). As a result, the delay time given to delayed single-ended signal Dly (BC) by delay compensation circuit ₁₃₂ is controlled to delay time _DA .

If the potential difference V _B -V _C on reception of the previous symbol is "strong" and the potential difference V _B -V _C on reception of the current symbol is "weak", the selector ₂₄₂ selects input D0, input D0 , is output as a single-ended signal Comp (BC) after compensation. As a result, the delay time applied to delayed single-ended signal Dly (BC) by delay compensation circuit ₁₃₂ is controlled to zero.

Further, when the potential difference V _B -V _C in receiving the previous symbol is "weak" and the potential difference V _B -V _C in receiving the current symbol is "strong", the selector ₂₄₂ selects the input D2, A single-ended signal input to the input D2 is output as a post-compensation single-ended signal Comp(AB). As a result, the delay time given to the delayed single-ended signal Dly (B−C) by the delay compensation circuit ₁₃₂ is controlled to D _A +D _B .

Furthermore, the delay time of the delay compensation circuit ₁₃₃ is similarly controlled. The delay compensation circuit ₁₃₃ is controlled depending on whether the potential difference V _C -V _A in receiving the previous symbol and the potential difference V _C -V _A in receiving the current symbol are "weak" or "strong", respectively. be done.

If the potential difference V _C -V _A in receiving the previous symbol and the potential difference V _C -V _A in receiving the current symbol are both "weak" or both are "strong", the selector ₂₄₃ inputs D1 is selected, and the single-ended signal input to input D1 is output as the post-compensation single-ended signal Comp(CA). As a result, the delay time given to the delayed single-ended signal Dly(CA) by the delay compensation circuit ₁₃₃ is controlled to _DA .

If the potential difference V _C -V _A on reception of the previous symbol is "strong" and the potential difference V _C -V _A on reception of the current symbol is "weak", the selector ₂₄₃ selects input D0, input D0 , is output as a compensated single-ended signal Comp(CA). As a result, the delay time given to the delayed single-ended signal Dly(CA) by the delay compensation circuit ₁₃₃ is controlled to zero.

Further, when the potential difference V _C -V _A in receiving the previous symbol is "weak" and the potential difference V _C -V _A in receiving the current symbol is "strong", the selector ₂₄₃ selects the input D2, A single-ended signal input to the input D2 is output as a post-compensation single-ended signal Comp(CA). As a result, the delay time given to the delayed single-ended signal Dly(CA) by the delay compensating circuit ₁₃₃ is controlled to D _A +D _B .

The compensated single-ended signals Comp(A−B), Comp(BC), and Comp(CA) output from the delay compensation circuits 13 ₁ , 13 ₂ , and 13 ₃ operating in this way are the clock recovery circuit 16 supplied to The clock recovery circuit 16 generates a recovered clock signal RCLK from the compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) output from the delay compensation circuits 13 ₁ to 13 ₃ . do. Through such an operation, the recovered clock signal RCLK in which the dispersion of the zero cross timings of the potential differences V _A −V _B , V _B −V _C , and V _C −V _A is compensated is generated and supplied to the latches 15 ₁ to 15 ₃ . be.

As described above, in this embodiment, the potential differences V _A −V _B , V _B −V _C , and V _C −V _A in the reception of the current symbol in addition to the previous symbol are “weak” and “strong”. , and the delay times of the delay compensation circuits 13 ₁ , 13 ₂ and 13 ₃ are controlled according to the detection result. As a result, the compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) in which the zero-cross timing dispersion is further compensated are generated. By generating the recovered clock signal RCLK from the compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) thus generated, the receiver 2 of the present embodiment can effectively extend the data valid window.

In the embodiment shown in FIG. 11, the configurations of the delay compensation circuits 13 ₁ , 13 ₂ and 13 ₃ are changed. Other parts of the receiving device 2 in FIG. 11 are configured in the same manner as the receiving device 2 shown in FIG.

Specifically, the delay compensation circuit _13-1 additionally comprises a delay circuit _23-1 connected to the output of the delay circuit _22-1 and having a delay time _DC . The selector ₂₄₁ has four inputs D0-D3. The input D0 of the selector _24-1 is connected to the output of the delay circuit _17-1 , the input D1 is connected to the output of the delay circuit _21-1 , the input D2 is connected to the output of the delay circuit _22-1 , and the input D3 is connected to the delay circuit _23-1. connected to the output of The delay compensating circuit 13 ₁ configured in this manner applies 0, D _A , D A +D _B , and _{D A} +D _B +D _C to the delayed single-ended signal Dly(A−B) output from the delay circuit 17 ₁ . Any delay time can be provided.

The delay compensation circuits 13 ₂ and 13 ₃ are similarly configured. The delay compensating circuit _13-2 additionally comprises a delay circuit _23-2 having a delay time _Dc , and the delay compensating circuit _13-3 additionally comprises a delay circuit _23-3 having a delay time _Dc . Each of the selectors 24 ₂ and 24 ₃ has four inputs D0-D3. Input D0 of selector _24-2 is connected to the output of delay circuit _17-2 , input D1 is connected to the output of delay circuit _21-2 , input D2 is connected to the output of delay circuit _22-2 , and input D3 is connected to delay circuit _23-2. connected to the output of The input D0 of the selector _24-3 is connected to the output of the delay circuit _17-3 , the input D1 is connected to the output of the delay circuit _21-3 , the input D2 is connected to the output of the delay circuit _22-3 , and the input D3 is connected to the delay circuit _23-3. connected to the output of The delay compensation _circuits 13 ₂ and 13 ₃ configured as described above apply 0, _{D A} , D _A +D _B , or D _A +D _B +D _C .

Such a configuration of the delay compensation circuits 13 ₁ , 13 ₂ , 13 ₃ compensates for zero-cross timing dispersion, and at the same time, the differential receivers 12 ₁ to 12 ₃ depend on the potential differences of the input signals of the differential receivers 12 1 to 12 ₃ . ₁₂₃ delay variations can be compensated for. As shown in FIG. 12, the delay of the differential receivers 12 ₁ to 12 ₃ depends on whether the potential differences _{V A} −V _B , V _B −V _C , and V _C −V _A are “weak” or “strong”. Varies depending on By compensating for variations in the delay of the differential receivers 12 ₁ to 12 ₃ , the data valid window can be further expanded.

In one embodiment, the delay of the differential receivers 12 ₁ to 12 ₃ in receiving the current symbol is such that the potential differences V _A −V _B , V _B −V _C , V _C −V _A in receiving the current symbol are “weak”. Larger in some cases, smaller in "strong" cases. In addition, the delays of the differential receivers 12 ₁ to 12 ₃ are also affected by the potential differences V _A −V _B , V _B −V _C and V _C −V _A in the reception of previous symbols, although they are less affected by the current symbol. obtain. In this embodiment, the delays of the differential receivers 12 ₁ to 12 ₃ are large when the potential differences V _A −V _B , V _B −V _C and V _C −V _A in the reception of the previous symbols are “weak”. , is “strong”.

Taken _together , _in this embodiment, _{the delays} of the differential receivers _{12 1} to 12 ₃ are _: largest in This delay is described as "Large". Also, the potential differences V _A −V _B , V _B −V _C , and V _C −V _A in the reception of both the current symbol and the previous symbol are the smallest when they are “strong”. This delay is described as "Small". Further, the potential differences V _A −V _B , V _B −V _C and V _C −V _A in the reception of the current symbol are “strong”, and the potential differences _V A −V _B , V _B −V _C in the reception of the previous symbol are “strong”. When V _C -V _A is "weak", the delay of differential receivers 12 ₁ -12 ₃ is medium. This delay is described as "Mid". According to the operation of the receiving device 2 of this embodiment described below, such variations in delay of the differential receivers 12 ₁ to 12 ₃ can be compensated.

As shown in FIG. 13, in this embodiment, similarly to the operation shown in FIG. 10, the delay times of the delay compensation circuits 13 ₁ , 13 ₂ and 13 ₃ are equal to the potential differences V _A −V _B and V It is controlled according to _B - V _C , V _C - V _A and the potential differences V _A - V _B , V _B - V _C , V _C - V _A at the reception of the current symbol. However, the control of the delay times of the delay compensation circuits 13 ₁ , 13 ₂ and 13 ₃ in this embodiment differs from the operation shown in FIG. In this embodiment, the delay times of the delay compensation circuits 13 ₁ , 13 ₂ , 13 ₃ are selected from 0, _DA , _DA + _DB , and _DA + _DB + _DC . First, control of the delay time of the delay compensation circuit ₁₃₁ will be described below.

When the potential difference V _A -V _B in receiving the previous symbol is "strong" and the potential difference V _A -V _B in receiving the current symbol is "weak", the zero crossing timing of the potential difference V _A -V _B is the slowest." Slow”, and the delay of the differential receiver ₁₂₁ becomes “Large”, which is the longest. Therefore, the delay time of the delay compensation circuit ₁₃₁ is set to 0, which is the smallest. Specifically, the previous symbol state signal Weak_P (AB) output from the XOR circuit ₂₅₁ is set to "0", and the current symbol state signal Weak_C (AB) output from the XOR circuit ₂₆₁ is set to "0". 1”. The selector ₂₄₁ selects the input D0 and outputs the single-ended signal input to the input D0 as the compensated single-ended signal Comp(AB). As a result, the delay time given to the delayed single-ended signal Dly(AB) by the delay compensation circuit ₁₃₁ is controlled to zero.

When the potential difference V _A -V _B in the reception of the previous symbol and the current symbol are both "weak", the zero crossing timing of the potential difference V _A -V _B becomes "Mid" and the delay of the differential receiver 12 ₁ is Become “Large”. Therefore, the delay time of the delay compensation circuit _13-1 is set to the second smallest _DA . Specifically, the previous symbol state signal Weak_P (AB) and the current symbol state signal Weak_C (AB) output from the XOR circuits 25 ₁ and 26 ₁ are both set to "1". The selector ₂₄₁ selects the input D1 and outputs the single-ended signal input to the input D1 as the compensated single-ended signal Comp(AB). As a result, the delay time given to the delayed single-ended signal Dly (AB) by the delay compensation circuit ₁₃₁ is controlled to _DA .

When the potential difference V _A -V _B in the reception of the previous symbol and the current symbol are both "strong", the zero cross timing of the potential difference V _A -V _B is "Mid" and the delay of the differential receiver 12 ₁ is It becomes the smallest “Small”. Therefore, the delay time of the delay compensation circuit 13 ₁ is set to D _A +D _B which is the second largest. Specifically, the previous symbol state signal Weak_P (AB) and the current symbol state signal Weak_C (AB) output from the XOR circuits 25 ₁ and 26 ₁ are both set to "0". The selector ₂₄₁ selects the input D2 and outputs the single-ended signal input to the input D2 as the compensated single-ended signal Comp(AB). As a result, the delay time given to the delayed single-ended signal Dly (A−B) by the delay compensation circuit 13 ₁ is controlled to D _A +D _B .

When the potential difference V _A -V _B in receiving the previous symbol is "weak" and the potential difference V _A -V _B in receiving the current symbol is "strong", the zero crossing timing of the potential difference V _A -V _B is the earliest."Fast" and the delay of the differential receiver ₁₂₁ becomes "Mid". In this case, in this embodiment, the maximum delay time of the delay compensation circuit _13-1 is set to D _A +D _B +D _C . Specifically, the previous symbol state signal Weak_P (AB) output from the XOR circuit ₂₅₁ is set to "1", and the current symbol state signal Weak_C (AB) output from the XOR circuit ₂₆₁ is set to "1". The selector ₂₄₁ , which is set to 0″, selects the input D3 and outputs the single-ended signal input to the input D3 as the compensated single-ended signal Comp(AB). As a result, the delay time given to the delayed single-ended signal Dly (AB) by the delay compensation circuit 13 ₁ is controlled to D _A +D _B +D _C .

According to such operation, by appropriately setting the delay times D _A , D _B , and D _C of the delay circuits 21 ₁ , 22 ₁ , and 23 ₁ , the dispersion of the zero cross timing of the potential difference V _A −V _B is compensated. Furthermore, it is possible to generate the compensated single-ended signal Comp(AB) while compensating for the dispersion of the delay time of the differential receiver ₁₂₁ .

The delay time of the delay compensating circuit ₁₃₂ is similarly controlled. If the potential difference V _B -V _C at reception of the previous symbol is "strong" and the potential difference V _B -V _C at reception of the current symbol is "weak", the selector 24 ₂ of the delay compensation circuit 13 ₂ outputs the input D0 is selected, and the single-ended signal input to the input D0 is output as the post-compensation single-ended signal Comp(BC). As a result, the delay time applied to delayed single-ended signal Dly (BC) by delay compensation circuit ₁₃₂ is controlled to zero.

If the potential difference V _B −V _C in the reception of the previous symbol and the current symbol are both “weak”, the selector ₂₄₂ selects the input D1 and converts the single-ended signal input to the input D1 to the compensated single-ended Output as a signal Comp (AB). As a result, the delay time given to delayed single-ended signal Dly (BC) by delay compensation circuit ₁₃₂ is controlled to _DA .

If the potential difference V _B −V _C at the reception of the previous symbol and the current symbol are both “strong”, selector ₂₄₂ selects input D2 and converts the single-ended signal input to input D2 to the compensated single-ended Output as a signal Comp (BC). As a result, the delay time given to the delayed single-ended signal Dly (B−C) by the delay compensation circuit ₁₃₂ is controlled to D _A +D _B .

If the potential difference V _B -V _C on reception of the previous symbol is "weak" and the potential difference V _B -V _C on reception of the current symbol is "strong", selector ₂₄₂ selects input D3, , is output as a single-ended signal Comp (BC) after compensation. As a result, the delay time given to the delayed single-ended signal Dly (BC) by the delay compensation circuit ₁₃₂ is controlled to D _A +D _B +D _C .

Furthermore, the delay time of the delay compensation circuit ₁₃₃ is similarly controlled. If the potential difference V _C −V _A upon reception of the previous symbol is “strong” and the potential difference V _C −V _A upon reception of the current symbol is “weak”, the selector 24 ₃ of the delay compensation circuit 13 ₃ outputs the input D0 to output the single-ended signal input to the input D0 as the compensated single-ended signal Comp(CA). As a result, the delay time given to the delayed single-ended signal Dly(CA) by the delay compensation circuit ₁₃₃ is controlled to zero.

If the potential difference V _C -V _A in the reception of the previous symbol and the current symbol are both "weak", the selector ₂₄₃ selects the input D1 and converts the single-ended signal input to the input D1 to the compensated single-ended Output as signal Comp(CA). As a result, the delay time given to the delayed single-ended signal Dly(CA) by the delay compensation circuit ₁₃₃ is controlled to _DA .

If the potential difference V _C -V _A in the reception of the previous symbol and the current symbol are both "strong", the selector ₂₄₃ selects the input D2 and converts the single-ended signal input to the input D2 to the compensated single-ended Output as signal Comp(CA). As a result, the delay time given to the delayed single-ended signal Dly(CA) by the delay compensating circuit ₁₃₃ is controlled to D _A +D _B .

If the potential difference V _C -V _A on reception of the previous symbol is "weak" and the potential difference V _C -V _A on reception of the current symbol is "strong", selector ₂₄₃ selects input D3, , is output as a compensated single-ended signal Comp(CA). As a result, the delay time given to the delayed single-ended signal Dly(CA) by the delay compensation circuit ₁₃₃ is controlled to D _A +D _B +D _C .

The compensated single-ended signals Comp(A−B), Comp(BC), and Comp(CA) output from the delay compensation circuits 13 ₁ , 13 ₂ , and 13 ₃ operating in this way are the clock recovery circuit 16 supplied to The clock recovery circuit 16 generates a recovered clock signal RCLK from the compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) output from the delay compensation circuits 13 ₁ to 13 ₃ . do.

As described above, in this embodiment, the potential differences V _A −V _B , V _B −V _C , and V _C −V _A in the reception of the current symbol in addition to the previous symbol are “weak” and “strong”. and the delay times of the delay compensation circuits 13 ₁ , 13 ₂ , 13 ₃ are changed from 0, D _A , D _A +D _B , D _A +D _B +D _C according to the detection result. selected. By such operation, _the dispersion of the zero-cross timing is compensated, and the compensated single- _ended signals Comp(A− _B ) and Comp(BC ), Comp(CA) is generated. By generating the recovered clock signal RCLK from the compensated single-ended signals Comp(AB), Comp(BC), and Comp(CA) thus generated, the receiver 2 of the present embodiment can effectively extend the data valid window.

In this embodiment, the delay times provided by the delay compensation circuits 13 ₁ , 13 ₂ and 13 ₃ can be changed according to the characteristics of the differential receivers 12 ₁ -12 ₃ . For example, if the differential receivers 12 ₁ to 12 ₃ are configured such that the smaller the absolute values of the potential differences V _A −V _B , V _B −V _C , and V _C −V _A , the smaller the delay. The correspondence between the potential differences V _A −V _B , V _B −V _C , V _C −V _A in the reception of the symbol and the current symbol and the delay times provided by the delay compensation circuits 13 ₁ , 13 ₂ , 13 ₃ are shown in FIG. 13 may be modified. The delay times provided by the delay compensation circuits 13 ₁ , 13 ₂ , 13 ₃ can be changed by changing the truth table that defines the operation of the selectors 24 ₁ -24 ₃ .

Although various embodiments of the present disclosure have been specifically described above, the techniques described in the present disclosure may be implemented with various modifications. For example, the above describes a data communication system conforming to the MIPI C-PHY standard, in which data communication takes place over three wires A, B, C, each of which can assume three potentials, The techniques disclosed in the above embodiments can also be used in data communication systems in which data communication takes place over four or more wires and in which each wire can have four or more voltage levels. can be

1: transmitter 2: receiver 3: lanes A, B, C: wires 11 ₁ to 11 ₃ : input terminals 12 ₁ to 12 ₃ : differential receivers 13 ₁ to 13 ₃ : delay compensation circuits 14 ₁ to 14 ₃ : Hold delay circuits 15 ₁ to 15 ₃ : Latches 16 : Clock recovery circuits 17 ₁ to 17 ₃ : Delay circuits 21 ₁ to 21 ₃ : Delay circuits 22 ₁ to 22 ₃ : Delay circuits 23 ₁ to 23 ₃ : Delay circuits 24 ₁ to 24 ₃ : selectors 25 ₁ to 25 ₃ : XOR circuits 26 ₁ to 26 ₃ : XOR circuits

Claims (9)

a first differential receiver configured to output a first single-ended signal based on the potential difference between the first wire and the second wire;
a second differential receiver connected to the second wire and the third wire and configured to output a second single-ended signal;
a third differential receiver connected to the third wire and the first wire and configured to output a third single-ended signal;
a first delay compensation circuit configured to generate a first compensated single-ended signal by delaying the first single-ended signal;
a clock recovery circuit configured to generate a recovered clock signal based at least in part on the first compensated single-ended signal;
a first latch circuit configured to latch the first compensated single-ended signal in synchronization with the reproduced clock signal;
with
The delay time of the first delay compensation circuit used for receiving the first symbol is equal to the second single-ended signal, the third single-ended signal, and the reception of the second symbol transmitted before the first symbol. based at least in part on the potential difference between the first wire and the second wire at. The delay time of the first delay compensation circuit used for receiving the first symbol determines whether the potential difference between the first wire and the second wire in receiving the second symbol is in the first state or the second state. based at least in part on a
The receiving device according to claim 1, wherein the absolute value of the potential difference between the first wire and the second wire in the second state is smaller than the absolute value of the potential difference between the first wire and the second wire in the first state. . a first differential receiver configured to output a first single-ended signal based on a potential difference between a first wire and a second wire of the three or more wires;
a first delay compensation circuit configured to generate a first compensated single-ended signal by delaying the first single-ended signal;
a clock recovery circuit configured to generate a recovered clock signal based at least in part on the first compensated single-ended signal;
a first latch circuit configured to latch the first compensated single-ended signal in synchronization with the reproduced clock signal;
with
The delay time of the first delay compensation circuit used for receiving the first symbol is at least part of the potential difference between the first wire and the second wire in receiving the second symbol transmitted before the first symbol. based on
A signal generated according to the MIPI C-PHY standard is supplied to the first wire and the second wire
receiving device. a first differential receiver configured to output a first single-ended signal based on the potential difference between the first wire and the second wire;
a second differential receiver configured to output a second single-ended signal based on the potential difference between the second wire and the third wire;
a third differential receiver configured to output a third single-ended signal based on the potential difference between the third wire and the first wire;
a first delay compensation circuit configured to generate a first compensated single-ended signal by delaying the first single-ended signal;
a second delay compensation circuit configured to generate a second compensated single-ended signal by delaying the second single-ended signal;
a third delay compensation circuit configured to generate a third compensated single-ended signal by delaying the third single-ended signal;
with
The delay time of the first delay compensation circuit used for receiving the first symbol is at least part of the potential difference between the first wire and the second wire in receiving the second symbol transmitted before the first symbol. based on
a delay time of the second delay compensation circuit used for receiving the first symbol is based at least in part on a potential difference between the second wire and the third wire in receiving the second symbol;
the delay time of the third delay compensation circuit used in receiving the first symbol is based at least in part on the potential difference between the third wire and the first wire in receiving the second symbol;
receiving device. a first hold delay circuit configured to generate a first pre-symbol single-ended signal by delaying the first compensated single-ended signal;
a second hold delay circuit configured to generate a second pre-symbol single-ended signal by delaying the second compensated single-ended signal;
a third hold delay circuit configured to generate a third pre-symbol single-ended signal by delaying the third compensated single-ended signal;
with
5. The receiving apparatus according to claim 4 , wherein the delay time of said first delay compensation circuit is based at least partially on said second previous symbol single-ended signal and said third previous symbol single-ended signal. the delay time of the second delay compensation circuit is based at least in part on a potential difference between the second wire and the third wire upon reception of the first symbol;
5. The receiver of claim 4 , wherein the delay time of said third delay compensation circuit is at least partially based on the potential difference between said third wire and said first wire. 3. The delay time of said first delay compensation circuit used for receiving said first symbol is further based on the potential difference between said first wire and said second wire in receiving said first symbol. 5. The receiving device according to any one of 4 . The delay time of the first delay compensation circuit used for receiving the first symbol is determined by the potential difference between the first wire and the second wire when receiving the first symbol and the first wire when receiving the second symbol. and based at least in part on whether the potential difference of the second wire is in a first state or a second state;
8. The receiving device according to claim 7 , wherein the absolute value of the potential difference between the first wire and the second wire in the second state is smaller than the absolute value of the potential difference between the first wire and the second wire in the first state. . outputting a first single-ended signal based on a potential difference between the first wire and the second wire;
outputting a second single-ended signal based on the potential difference between the second wire and the third wire;
outputting a third single-ended signal based on a potential difference between the third wire and the first wire;
generating a first compensated single-ended signal by delaying the first single-ended signal;
generating a recovered clock signal based on the first compensated single-ended signal;
latching the first compensated single-ended signal in synchronization with the recovered clock signal;
including
Generating the first compensated single-ended signal comprises: delay time applied to the first single-ended signal when generating the first compensated single-ended signal in receiving a first symbol; controlling based on a single-ended signal, said third single-ended signal, and a potential difference between said first wire and said second wire upon reception of a second symbol transmitted before said first symbol. Data reception method.

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