JP7315684B2 - 量子アルゴリズムの検証、および量子アルゴリズムの実行時間の推定 - Google Patents
量子アルゴリズムの検証、および量子アルゴリズムの実行時間の推定 Download PDFInfo
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- JP7315684B2 JP7315684B2 JP2021543345A JP2021543345A JP7315684B2 JP 7315684 B2 JP7315684 B2 JP 7315684B2 JP 2021543345 A JP2021543345 A JP 2021543345A JP 2021543345 A JP2021543345 A JP 2021543345A JP 7315684 B2 JP7315684 B2 JP 7315684B2
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N10/60—Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
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- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N10/70—Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation
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- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3604—Software analysis for verifying properties of programs
- G06F11/3612—Software analysis for verifying properties of programs by runtime analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/81—Threshold
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Description
から3つのキュービットを用いて形成される複合ゲートについての複合ゲート・エラー率を生成する。AxyおよびBxyは、第1の校正演算および第2の校正演算それぞれの間に、キュービットxおよびyから形成される量子ゲートについてのプリミティブ・ゲート・エラー率である。
Claims (10)
- 量子アルゴリズムを受信することと、
前記量子アルゴリズムをシミュレートすることであって、前記量子アルゴリズムが量子ゲートの第1のセットを形成する、前記シミュレートすることと、
前記量子ゲートの第1のセットのパラメータの第1のセットを分析することと、
前記量子ゲートの第1のセットを実行するキュービットのセットのパラメータの第2のセットを分析することと、
前記パラメータの第1のセットまたは前記パラメータの第2のセットのうちの少なくとも1つが合格基準を満たすと判断することに応答して、前記量子アルゴリズムを量子ゲートの第2のセットに変換することと、
を含む、方法。 - 前記量子アルゴリズムを記憶された量子アルゴリズムと比較して、前記量子アルゴリズムの実行時間を推定することをさらに含む、請求項1に記載の方法。
- 前記パラメータの第1のセットまたは前記パラメータの第2のセットのうちの少なくとも1つが合格基準を満たすと判断することに応答して、検証済み量子アルゴリズムを実行する量子プロセッサのための量子アルゴリズムのキュー内の場所に対応する検証チケットを作成することをさらに含む、請求項1に記載の方法。
- ユーザによってサブミットされた量子アルゴリズムのセットの総実行時間が実行時間閾値を超えることに応答して、前記検証チケットを無効にすることをさらに含む、請求項3に記載の方法。
- 前記パラメータの第1のセットまたは前記パラメータの第2のセットのうちの少なくとも1つのパラメータが合格基準を満たさないと判断することに応答して、満たさなかった前記少なくとも1つのパラメータをユーザに通知することをさらに含む、請求項1に記載の方法。
- 前記量子ゲートの第2のセットを用いて前記量子アルゴリズムを実行することをさらに含む、請求項1に記載の方法。
- 前記合格基準が、量子ゲートのエラー率閾値である、請求項1に記載の方法。
- 前記合格基準が、キュービットのコヒーレンス時間閾値である、請求項1に記載の方法。
- 請求項1ないし8のいずれかに記載の方法の全てのステップを実行するように適合される手段を含む、システム。
- コンピュータ・プログラムであって、前記コンピュータ・プログラムがコンピュータ・システム上で実行されるときに、請求項1ないし8のいずれかに記載の方法の全てのステップを実行する命令を含む、コンピュータ・プログラム。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US16/297,604 | 2019-03-09 | ||
US16/297,604 US11580433B2 (en) | 2019-03-09 | 2019-03-09 | Validating and estimating runtime for quantum algorithms |
PCT/EP2020/055256 WO2020182489A1 (en) | 2019-03-09 | 2020-02-28 | Validating and estimating runtime for quantum algorithms |
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JP2022522101A JP2022522101A (ja) | 2022-04-14 |
JPWO2020182489A5 JPWO2020182489A5 (ja) | 2022-07-21 |
JP7315684B2 true JP7315684B2 (ja) | 2023-07-26 |
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US (2) | US11580433B2 (ja) |
EP (1) | EP3938971A1 (ja) |
JP (1) | JP7315684B2 (ja) |
KR (1) | KR20210119533A (ja) |
CN (1) | CN113614752A (ja) |
AU (1) | AU2020233909B2 (ja) |
WO (1) | WO2020182489A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US11474867B2 (en) * | 2019-07-11 | 2022-10-18 | Microsoft Technology Licensing, Llc | Measurement sequence determination for quantum computing device |
US11853731B2 (en) * | 2020-03-24 | 2023-12-26 | IonQ, Inc. | Pulse generation |
CN114757225B (zh) * | 2022-03-31 | 2023-05-30 | 北京百度网讯科技有限公司 | 信号采样质量的确定方法、装置、设备及存储介质 |
CN117744819A (zh) * | 2022-09-14 | 2024-03-22 | 本源量子计算科技(合肥)股份有限公司 | 评测量子设备性能的方法、装置、存储介质及电子装置 |
CN115934346B (zh) * | 2022-12-28 | 2023-10-20 | 北京大学 | 算子的自动检测方法、装置、电子设备及介质 |
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US20170228483A1 (en) | 2015-11-06 | 2017-08-10 | Rigetti & Co., Inc. | Analyzing quantum information processing circuits |
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EP3593298A4 (en) | 2017-03-10 | 2021-01-20 | Rigetti & Co., Inc. | PERFORMING A CALIBRATION PROCESS IN A QUANTUM DATA PROCESSING SYSTEM |
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EP3642765A4 (en) | 2017-06-19 | 2021-04-07 | Rigetti & Co., Inc. | DISTRIBUTED QUANTUM COMPUTER SYSTEM |
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- 2020-02-28 WO PCT/EP2020/055256 patent/WO2020182489A1/en active Application Filing
- 2020-02-28 CN CN202080019974.8A patent/CN113614752A/zh active Pending
- 2020-02-28 EP EP20709146.3A patent/EP3938971A1/en active Pending
- 2020-02-28 KR KR1020217028759A patent/KR20210119533A/ko active Search and Examination
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US20030169041A1 (en) | 2001-12-22 | 2003-09-11 | D-Wave Systems, Inc. | Quantum computing integrated development environment |
JP2018503796A (ja) | 2014-09-24 | 2018-02-08 | クオンタム ヴァリー インベストメント ファンド リミテッド パートナーシップ | 量子制御のための制御シーケンスの生成 |
US20170228483A1 (en) | 2015-11-06 | 2017-08-10 | Rigetti & Co., Inc. | Analyzing quantum information processing circuits |
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Publication number | Publication date |
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JP2022522101A (ja) | 2022-04-14 |
US11580433B2 (en) | 2023-02-14 |
AU2020233909A1 (en) | 2021-09-30 |
WO2020182489A1 (en) | 2020-09-17 |
US20230409938A1 (en) | 2023-12-21 |
AU2020233909B2 (en) | 2023-04-13 |
KR20210119533A (ko) | 2021-10-05 |
US20200285986A1 (en) | 2020-09-10 |
CN113614752A (zh) | 2021-11-05 |
EP3938971A1 (en) | 2022-01-19 |
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