JP7308655B2 - Display device and electronic device - Google Patents

Description

One embodiment of the present invention relates to a display device, an operating method thereof, and an electronic device. One embodiment of the present invention relates to a method for manufacturing a display device. One embodiment of the present invention relates to a transistor and a method for manufacturing the transistor.

Note that one embodiment of the present invention is not limited to the above technical field. Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input/output devices, and driving methods thereof. , or methods for producing them, can be mentioned as an example. A semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

As a semiconductor material applicable to transistors, an oxide semiconductor using a metal oxide has attracted attention. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is the proportion of gallium. A semiconductor device is disclosed in which the field-effect mobility (sometimes simply referred to as mobility or μFE) is increased by making it larger than .

A metal oxide that can be used for a semiconductor layer can be formed by a sputtering method or the like; therefore, it can be used for a semiconductor layer of a transistor included in a large-sized display device. In addition, since it is possible to modify a part of production equipment for transistors using polycrystalline silicon or amorphous silicon and use it, equipment investment can be suppressed. In addition, since a transistor using a metal oxide has higher field-effect mobility than a transistor using amorphous silicon, a highly functional display device provided with a driver circuit can be realized.

Wearable display devices and stationary display devices are becoming popular as display devices for augmented reality (AR) or virtual reality (VR). Wearable display devices include, for example, head-mounted displays (HMDs) and glasses-type display devices. Stationary display devices include, for example, a head-up display (HUD: Head-Up Display).

Further, an electronic viewfinder is used as a viewfinder for confirming an image to be captured before capturing, which is provided in a digital camera or the like, which is an electronic device having an image capturing device. A display section is provided in the electronic viewfinder, and an image obtained by the imaging element can be displayed as an image on the display section. For example, Patent Literature 2 discloses an electronic viewfinder capable of obtaining good visibility from the center of the image to the periphery of the image.

JP 2014-7399 A JP 2012-42569 A

In a display device such as a head-mounted display (HMD) where the distance between the display surface and the user is short, the user can easily see the pixels, and the graininess is strongly felt, so the immersive feeling and presence of AR and VR are lost. It may fade. Further, the electronic viewfinder is provided with an eyepiece like the optical viewfinder, and an image displayed on the display of the electronic viewfinder is viewed by bringing the user's eye closer to the eyepiece. Therefore, the distance between the display section of the electronic viewfinder and the user is reduced. This makes it easier for the user to visually recognize the pixels provided in the display unit, and the user may feel a strong graininess. For the reasons described above, HMDs and electronic viewfinders are desired to have display devices with fine pixels so that the pixels are not visible to the user. For example, the pixel density is preferably 1000 ppi or more, preferably 5000 ppi or more, more preferably 10000 ppi. Further, for example, in a display device especially provided in an electronic viewfinder, it is preferable that an image with a resolution of 4K (number of pixels: 3840×2160), 5K (number of pixels: 5120×2880) or higher can be displayed.

An object of one embodiment of the present invention is to provide a display device with a large number of pixels. Alternatively, an object of one embodiment of the present invention is to provide a high-definition display device. Alternatively, an object of one embodiment of the present invention is to provide a display device capable of displaying a high-resolution image. Another object of one embodiment of the present invention is to provide a display device capable of displaying high-quality images. Another object of one embodiment of the present invention is to provide a display device that can display an image with a high degree of presence. Another object of one embodiment of the present invention is to provide a display device capable of displaying a high-brightness image. Alternatively, an object of one embodiment of the present invention is to provide a display device with a high dynamic range. Another object of one embodiment of the present invention is to provide a display device with a narrow frame. Alternatively, an object of one embodiment of the present invention is to provide a small display device. Alternatively, an object of one embodiment of the present invention is to provide a display device that operates at high speed. Alternatively, an object of one embodiment of the present invention is to provide a display device with low power consumption. Alternatively, an object of one embodiment of the present invention is to provide an inexpensive display device. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable display device. Another object of one embodiment of the present invention is to provide a display device with a high degree of layout freedom. Alternatively, an object of one embodiment of the present invention is to provide a novel display device. Another object of one embodiment of the present invention is to provide a novel method of operating a display device. Alternatively, an object of one embodiment of the present invention is to provide a novel electronic device.

The description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from descriptions in the specification, drawings, claims, and the like.

One embodiment of the present invention is a display device in which a first layer and a second layer are stacked, and the first layer includes an interface circuit, a buffer element, and a source driver circuit. The second layer has a display portion, the display portion has pixels arranged in a matrix, the buffer element has a region overlapping with the pixels, and the source driver circuit has a region overlapping with the pixels. A display device having an overlapping region, wherein the interface circuit is electrically connected to the input terminal of the buffer element and the output terminal of the buffer element is electrically connected to the source driver circuit.

Alternatively, in the above aspect, the source driver circuit may have a buffer circuit, and the output terminal of the buffer element may be electrically connected to the input terminal of the buffer circuit.

Alternatively, in the above aspect, the buffer element has a first transistor, a second transistor, and a third transistor, and the source driver circuit has one of the source or drain of the first transistor and the one of the source and drain of the second transistor, the other of the source and drain of the second transistor is electrically connected to one of the source and drain of the third transistor, and the The gate may be electrically connected with the interface circuit.

Alternatively, in the above aspect, the first layer may have a gate driver circuit, the gate driver circuit may have a region that overlaps with the pixels, and the gate driver circuit may have a region that overlaps with the source driver circuit.

Alternatively, in the above aspect, the buffer element may be provided in a region where the gate driver circuit and the source driver circuit overlap.

Alternatively, in the above aspect, the pixel has a transistor including a metal oxide in a channel formation region, and the metal oxide includes an element M (M is Al, Ga, Y, or Sn) and Zn. may

Alternatively, one embodiment of the present invention includes an interface circuit, a first buffer element, a second buffer element, a third buffer element, a first source driver circuit, a second source driver circuit, is provided, the interface circuit is electrically connected to the input terminal of the first buffer element and the input terminal of the second buffer element, and the output terminal of the first buffer element is connected to the first source driver circuit The output terminal of the second buffer element is electrically connected to the input terminal of the third buffer element, and the output terminal of the third buffer element is electrically connected to the second source driver circuit. is a display device connected to the

Alternatively, in the above aspect, the display device has a first gate driver circuit and a second gate driver circuit, and the first gate driver circuit has a region overlapping with the first source driver circuit. , the second gate driver circuit may have a region that overlaps with the second source driver circuit.

Alternatively, in the above aspect, the first and second buffer elements are provided in a region where the first gate driver circuit and the first source driver circuit overlap, and the third buffer element is provided in the second gate driver circuit. The driver circuit and the second source driver circuit may be provided in an overlapping region.

Alternatively, one embodiment of the present invention is a display device in which a first layer and a second layer are stacked, and the first layer includes an interface circuit and a first buffer element. , a second buffer element, a third buffer element, a first source driver circuit, and a second source driver circuit are provided, and the second layer includes a first display section and a second a display portion, in which first pixels are arranged in a matrix in the first display portion; second pixels are arranged in a matrix in the second display portion; and a first buffer is provided. The element has an area that overlaps the first pixel, the second buffer element has an area that overlaps the first pixel, and the first source driver circuit has an area that overlaps the first pixel. , the third buffer element has a region that overlaps the second pixel, the second source driver circuit has a region that overlaps the second pixel, and the interface circuit has an input terminal of the first buffer device. , and the input terminal of the second buffer element, the output terminal of the first buffer element is electrically connected to the first source driver circuit, and the output terminal of the second buffer element is The display device is electrically connected to the input terminal of the third buffer element, and the output terminal of the third buffer element is electrically connected to the second source driver circuit.

Alternatively, in the above aspect, the first layer has a first gate driver circuit and a second gate driver circuit, and the first gate driver circuit has a region overlapping with the first pixel. , the second gate driver circuit has a region that overlaps the second pixel, the first gate driver circuit has a region that overlaps the first source driver circuit, the second gate driver circuit has a region that overlaps the first It may have a region that overlaps two source driver circuits.

Alternatively, in the above aspect, the first and second buffer elements are provided in a region where the first gate driver circuit and the first source driver circuit overlap, and the third buffer element is provided in the second gate driver circuit. The driver circuit and the second source driver circuit may be provided in an overlapping region.

Alternatively, in the above aspect, the first and second pixels have a transistor having a metal oxide in a channel formation region, and the metal oxide includes an element M (M is Al, Ga, Y, or Sn), Zn and

Alternatively, in the above aspect, the first source driver circuit has a first buffer circuit, the second source driver circuit has a second buffer circuit, and the output terminal of the first buffer element is It may be electrically connected to the input terminal of the first buffer circuit, and the output terminal of the third buffer element may be electrically connected to the input terminal of the second buffer circuit.

Alternatively, in the above aspect, the first buffer element has a first transistor, a second transistor, and a third transistor, and the first source driver circuit is the source of the first transistor or One of the drain and one of the source or drain of the second transistor is electrically connected, and the other of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor. , the gate of the second transistor is electrically connected to the interface circuit, the second buffer element has a fourth transistor, a fifth transistor, and a sixth transistor; One of the source and drain of the transistor is electrically connected to one of the source and drain of the fifth transistor, and the other of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor. the gate of the fifth transistor is electrically connected to the interface circuit; and the third buffer element has a seventh transistor, an eighth transistor, and a ninth transistor. , the second source driver circuit is electrically connected to one of the source or drain of the seventh transistor and one of the source or drain of the eighth transistor, the gate of the seventh transistor being connected to the fourth transistor; The other of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the ninth transistor, and the gate of the eighth transistor is connected to the gate of the fourth transistor may be electrically connected to either the source or the drain of the .

An electronic device including a display device of one embodiment of the present invention and a lens is also one embodiment of the present invention.

According to one embodiment of the present invention, a display device with a large number of pixels can be provided. Alternatively, according to one embodiment of the present invention, a high-definition display device can be provided. Alternatively, one embodiment of the present invention can provide a display device capable of displaying a high-resolution image. Alternatively, according to one embodiment of the present invention, a display device capable of displaying high-quality images can be provided. Alternatively, according to one embodiment of the present invention, a display device capable of displaying an image with a high degree of presence can be provided. Alternatively, according to one embodiment of the present invention, a display device capable of displaying a high-brightness image can be provided. Alternatively, according to one embodiment of the present invention, a display device with a high dynamic range can be provided. Alternatively, according to one embodiment of the present invention, a display device with a narrow frame can be provided. Alternatively, according to one embodiment of the present invention, a small display device can be provided. Alternatively, according to one embodiment of the present invention, a display device that operates at high speed can be provided. Alternatively, according to one embodiment of the present invention, a display device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, an inexpensive display device can be provided. Alternatively, one embodiment of the present invention can provide a highly reliable display device. Alternatively, according to one embodiment of the present invention, a display device with a high degree of layout freedom can be provided. Alternatively, one embodiment of the present invention can provide a novel display device. Alternatively, according to one embodiment of the present invention, a novel method for operating a display device can be provided. Alternatively, one embodiment of the present invention can provide a novel electronic device.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from descriptions in the specification, drawings, claims, and the like.

FIG. 1 is a block diagram showing a configuration example of a display device. FIG. 2 is a block diagram showing a configuration example of a display device. FIG. 3 is a block diagram showing a configuration example of a display device. FIG. 4 is a circuit diagram showing a configuration example of a display device. FIG. 5 is a circuit diagram showing a configuration example of a display device. FIG. 6 is a circuit diagram showing a configuration example of a display device. FIG. 7 is a timing chart showing an example of the operation method of the display device. FIG. 8 is a timing chart showing an example of the operation method of the display device. FIG. 9 is a timing chart showing an example of the operation method of the display device. FIG. 10 is a circuit diagram showing a configuration example of a display device. FIG. 11 is a timing chart showing an example of the operation method of the display device. FIG. 12 is a timing chart showing an example of the operation method of the display device. FIG. 13 is a timing chart showing an example of the operation method of the display device. FIG. 14 is a block diagram showing a configuration example of a source driver circuit. FIG. 15 is a block diagram showing a configuration example of a display device. FIG. 16 is a block diagram showing a configuration example of a shift register. FIG. 17A is a block diagram showing a configuration example of a shift register. FIG. 17B is a circuit diagram showing a configuration example of a shift register. FIG. 18 is a schematic diagram showing the arrangement of gate driver circuits and source driver circuits. FIG. 19 is a top view showing a configuration example of a gate driver circuit and a source driver circuit. FIG. 20 is a top view showing a configuration example of a gate driver circuit, a source driver circuit, and a buffer circuit. FIG. 21 is a block diagram showing a configuration example of a display device. FIG. 22 is a block diagram showing a configuration example of a display device. FIG. 23 is a block diagram showing a configuration example of a display device. FIGS. 24A to 24E are diagrams showing configuration examples of pixels. 25A to 25C are circuit diagrams showing configuration examples of pixels. 26A, 26C, and 26D are circuit diagrams showing configuration examples of pixels. FIG. 26B is a timing chart showing an example of a pixel operating method. 27A to 27D are circuit diagrams showing configuration examples of pixels. FIG. 28 is a block diagram showing a configuration example of a display device. FIG. 29 is a diagram for explaining an operation example of the display device. FIG. 30 is a cross-sectional view showing a configuration example of a display device. FIG. 31 is a cross-sectional view showing a configuration example of a display device. FIG. 32 is a cross-sectional view showing a configuration example of a display device. FIG. 33 is a cross-sectional view showing a configuration example of a display device. FIG. 34 is a cross-sectional view showing a configuration example of a display device. FIG. 35 is a cross-sectional view showing a configuration example of a display device. 36A to 36E are diagrams showing structural examples of light-emitting elements. FIG. 37A is a top view showing a structural example of a transistor. 37B and 37C are cross-sectional views showing structural examples of transistors. FIG. 38A is a top view showing a structural example of a transistor. 38B and 38C are cross-sectional views showing structural examples of transistors. FIG. 39A is a top view showing a structural example of a transistor. 39B and 39C are cross-sectional views showing structural examples of transistors. FIG. 40 is a block diagram showing a configuration example of a display device. FIG. 41 is a circuit diagram showing a configuration example of a shift register. FIG. 42 is a circuit diagram showing a configuration example of a pixel. FIG. 43 is a timing chart showing an example of a pixel operating method. 44A to 44E are perspective views illustrating examples of electronic devices. 45A to 45G are perspective views illustrating examples of electronic devices. 46A and 46B are cross-sectional TEM photographs of the transistor according to the example. FIG. 47A is a diagram showing measurement results of the Id-Vg characteristics according to the example. FIG. 47B is a diagram showing measurement results of Ig-Vg characteristics according to the example. FIG. 48 is a diagram showing measurement results of the Id-Vg characteristics according to the example. FIG. 49A is a diagram showing measurement results of the Id-Vg characteristics according to the example. FIG. 49B is a diagram showing measurement results of the Id-Vd characteristics according to the example. FIG. 50 is a diagram showing measurement results of the Id-Vd characteristics according to the example. FIGS. 51A and 51B are diagrams showing measurement results of the Id-Vg characteristics according to the example. FIG. 52 shows the time course of the output potential of the gate driver circuit according to the example. FIG. 53 shows measurement results of the gate driver circuit according to the example using an oscilloscope. FIG. 54 is a display result of an image by the display device according to the example. FIG. 55A is a photograph showing the appearance of a display device according to Example. FIG. 55B is a display result of an image by the display device according to Example. FIG. 56A is a photograph showing the appearance of a display device according to Example. FIG. 56B is a display result of an image by the display device according to Example. FIG. 57 shows simulation results according to the example. FIG. 58 is a display result of an image by the display device according to the example. FIGS. 59A and 59B are the display results of images by the display device according to the example. FIG. 60 is a graph showing the luminance of light emitted from a pixel included in the display device according to the example for each gradation.

Hereinafter, embodiments will be described with reference to the drawings. However, those skilled in the art will readily appreciate that the embodiments can be embodied in many different forms and that various changes in form and detail can be made therein without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

Also, in the figures described herein, the size of each feature, layer thickness, or region may be exaggerated for clarity.

Also, the ordinal numbers "first", "second", and "third" used in this specification are added to avoid confusion of constituent elements, and are not numerically limited.

In this specification, terms such as "above" and "below" are used for convenience in order to describe the positional relationship between configurations with reference to the drawings. In addition, the positional relationship between the configurations changes appropriately according to the direction in which each configuration is drawn. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately rephrased according to the situation.

In this specification and the like, the functions of a source and a drain of a transistor may be interchanged when the polarity of the transistor or the direction of current changes in circuit operation. Therefore, the terms "source" and "drain" can be used interchangeably.

In this specification and the like, "electrically connected" includes the case of being connected via "something that has some electrical effect". Here, "something that has some kind of electrical action" is not particularly limited as long as it enables transmission and reception of electrical signals between connection objects. For example, "something that has some electrical action" includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, buffer circuits, and other elements and circuits that have various functions. In addition, an inverter may also be included in "things having some kind of electrical action".

In this specification and the like, the terms “film” and “layer” can be used interchangeably. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

In this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is in an off state (also referred to as a non-conducting state or a cutoff state). Unless otherwise specified, an off state means a state in which the voltage _Vgs between the gate and the source is lower than the threshold voltage _Vth in an n-channel transistor (higher than _Vth in a p-channel transistor). Say.

Also, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes, values, or the like shown in the drawings. For example, in an actual manufacturing process, a layer, a resist mask, or the like may be unintentionally reduced due to processing such as etching, but this may not be reflected in the drawings for easy understanding. In addition, in the drawings, the same reference numerals may be used in common for the same parts or parts having similar functions, materials, etc. between different drawings, and repeated description thereof may be omitted. Also, when referring to similar functions, materials, etc., the hatch patterns may be the same and no particular reference numerals may be attached.

In this specification and the like, a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor including an oxide or an oxide semiconductor.

(Embodiment 1)
In this embodiment, a display device which is one embodiment of the present invention will be described.

One embodiment of the present invention relates to a display device in which a first layer and a second layer are stacked. A first layer has an interface circuit, a gate driver circuit, and a source driver circuit, and a second layer has a display portion. The gate driver circuit and the source driver circuit are provided so as to have a region overlapping with the display portion. Accordingly, the frame of the display device of one embodiment of the present invention can be narrowed and the size thereof can be reduced. Note that the interface circuit has a function of receiving image data from the outside of the display device and supplying the image data as an image signal to the source driver circuit. Also, the interface circuit can be provided, for example, on the outer periphery of the display device.

Also, the gate driver circuit and the source driver circuit are not clearly separated and have overlapping regions. Accordingly, the frame of the display device can be further narrowed and the size thereof can be reduced as compared with the case where the overlapping region is not provided.

Here, when the gate driver circuit and the source driver circuit do not overlap with the display portion, the gate driver circuit and the source driver circuit are provided, for example, in the outer peripheral portion of the display portion. In this case, it is difficult to provide more display portions than 2 rows and 2 columns from the viewpoint of installation locations of the gate driver circuit and the source driver circuit. On the other hand, in the display device of one embodiment of the present invention, the gate driver circuit and the source driver circuit can be provided in a layer different from the layer in which the display portion is provided so as to have a region overlapping with the display portion. Therefore, more display portions than two rows and two columns can be provided.

As described above, the gate driver circuit and the source driver circuit are provided so as to overlap with the display portion; A larger number of display units can be provided than a display device with an undesired configuration. By providing many display portions, the number of pixels provided in one display portion can be reduced. Therefore, the display device of one embodiment of the present invention can operate at high speed, for example. Therefore, the definition of the display device of one embodiment of the present invention can be higher than that of a display device in which the gate driver circuit and the source driver circuit do not overlap with the display portion. For example, the pixel density of the display device of one embodiment of the present invention can be 1000 ppi or more, 5000 ppi or more, or 10000 ppi. Further, the resolution of an image that can be displayed by the display device of one embodiment of the present invention is higher than the resolution of an image that can be displayed by a display device in which the gate driver circuit and the source driver circuit do not overlap with the display portion. can be done.

Here, when the gate driver circuit and the source driver circuit are provided so as to overlap with the display portion, and the interface circuit is provided in the outer peripheral portion of the display device of one embodiment of the present invention, wiring from the interface circuit to the source driver circuit can be achieved. Distance may be longer. Therefore, when the image data received by the interface circuit is supplied to the source driver circuit as an image signal, the image signal is attenuated, and the source driver circuit may not be able to recognize the image signal correctly. For example, if the image signal is a digital signal, the source driver circuit may not be able to correctly recognize whether the bit of the signal is "0" or "1". Further, due to attenuation of the image signal, it may take a long time to supply the image signal from the interface circuit to the source driver circuit.

Therefore, in the display device of one embodiment of the present invention, a buffer circuit is provided between the interface circuit and the source driver circuit. Specifically, a buffer circuit is provided such that an input terminal of the buffer circuit is electrically connected to the interface circuit and an output terminal of the buffer circuit is electrically connected to the source driver circuit. Accordingly, the source driver circuit can correctly recognize the image signal, so that the reliability of the display device of one embodiment of the present invention can be improved. Further, the operation speed of the display device of one embodiment of the present invention can be increased. Note that the buffer circuit can be provided in the first layer so as to have a region overlapping with the display portion.

A buffer circuit may also be provided in the source driver circuit. For example, the output terminal of the buffer circuit (first buffer circuit) provided between the interface circuit and the source driver circuit is the input terminal of the buffer circuit (second buffer circuit) provided in the source driver circuit. can be electrically connected to Thus, even if the image signal output from the first buffer circuit is attenuated before being input to the source driver circuit, the image signal input to the source driver circuit can be correctly processed. Therefore, the reliability of the display device of one embodiment of the present invention can be improved. Further, the operation speed of the display device of one embodiment of the present invention can be increased.

<Configuration Example 1 of Display Device>
FIG. 1 is a block diagram showing a configuration example of a display device 10 which is a display device of one embodiment of the present invention. The display device 10 has a layer 20 and a layer 30 stacked above the layer 20 . Layer 20 is provided with gate driver circuits 21 , source driver circuits 22 , buffer circuits 25 and interface circuits 50 . Note that the interface circuit 50 can be provided, for example, in the outer peripheral portion of the display device 10 .

A display portion 33 is provided on the layer 30 and pixels 34 are arranged in a matrix in the display portion 33 . An interlayer insulating layer may be provided between layers 20 and 30 . Note that the layer 20 may be laminated on the layer 30 . Interface circuitry 50 may also be provided on layer 30 . In this case, the layer 20 may be configured without the interface circuit 50 .

The interface circuit 50 is electrically connected to the input terminal of the buffer circuit 25 . An output terminal of the buffer circuit 25 is electrically connected to the source driver circuit 22 .

Pixels 34 in the same row are electrically connected to the gate driver circuit 21 via wiring 31 , and pixels 34 in the same column are electrically connected to the source driver circuit 22 via wiring 32 . The wiring 31 functions as a scanning line, and the wiring 32 functions as a data line.

Note that FIG. 1 shows a configuration in which the pixels 34 in one row are electrically connected by one wiring 31 and the pixels 34 in one column are electrically connected by one wiring 32. One aspect of the present invention is not limited to this. For example, one row of pixels 34 may be electrically connected by two or more wirings 31 , or one column of pixels 34 may be electrically connected by two or more wirings 32 . That is, for example, one pixel 34 may be electrically connected to two or more scanning lines, or may be electrically connected to two or more data lines. Further, for example, one wiring 31 may be electrically connected to pixels 34 in two or more rows, or one wiring 32 may be electrically connected to pixels 34 in two or more columns. . That is, for example, one wiring 31 may be shared by two or more rows of pixels 34 , and one wiring 32 may be shared by two or more columns of pixels 34 .

The gate driver circuit 21 has a function of generating a signal for controlling the operation of the pixel 34 and supplying the signal to the pixel 34 via the wiring 31 . The interface circuit 50 has a function of receiving image data from outside the display device 10 and outputting the image data as an image signal. The interface circuit 50 has, for example, a serial-parallel conversion circuit. Accordingly, when the image data received by the display device 10 is serial image data, the image data can be parallel-converted. Therefore, the interface circuit 50 can output the image data even if the load when the interface circuit 50 outputs the image data is large.

The image signal output from the interface circuit 50 is input to the buffer circuit 25 . The buffer circuit 25 can be a unity gain buffer, for example, and has a function of outputting an input signal and a corresponding signal. For example, when the signal input to the buffer circuit 25 is a digital signal, the buffer circuit 25 has a function of outputting a signal of bits corresponding to the signal. For example, when the bit of the signal input to the buffer circuit 25 is "0", the buffer circuit 25 can output a signal of "0" and the bit of the signal input to the buffer circuit 25 is "1". ", the buffer circuit 25 can output a signal of "1". When the bit of the signal input to the buffer circuit 25 is "0", the buffer circuit 25 outputs a signal of "1", and the bit of the signal input to the buffer circuit 25 is "1". buffer circuit 25 may output a signal of "0". That is, the buffer circuit 25 may be either a non-inverting buffer circuit or an inverting buffer circuit.

The source driver circuit 22 has a function of supplying a signal corresponding to the image signal output from the buffer circuit 25 to the pixel 34 via the wiring 32 . For example, the source driver circuit 22 has a digital-to-analog conversion circuit (hereinafter referred to as a DA conversion circuit), converts a digital image signal into an analog signal by the DA conversion circuit, and supplies the analog signal to the pixels 34. can be done.

The display unit 33 has a function of displaying an image corresponding to the signal supplied to the pixels 34 by the source driver circuit 22 . Specifically, an image is displayed on the display unit 33 by emitting light of luminance corresponding to the signal from the pixel 34 .

In FIG. 1, the positional relationship between the layer 20 and the layer 30 is indicated by a dashed-dotted line and an outline circle, and the outline circle of the layer 20 and the outline circle of the layer 30, which are connected by the dashed-dotted line, overlap each other. ing. Note that the same notation is used in other drawings as well.

In the display device 10 , the gate driver circuit 21 and the source driver circuit 22 are provided so as to have a region overlapping the display section 33 . For example, the gate driver circuit 21 and the source driver circuit 22 have regions that overlap the pixels 34 . By stacking the gate driver circuit 21, the source driver circuit 22, and the display portion 33 so as to have regions that overlap each other, the display device 10 can have a narrow frame and can be miniaturized. can.

On the other hand, if the gate driver circuit 21 and the source driver circuit 22 are provided so as to have a region overlapping with the display section 33, and the interface circuit 50 is provided in the outer peripheral portion of the display device 10, wiring from the interface circuit 50 to the source driver circuit 22 Distance may be longer. Therefore, when the image data received by the interface circuit 50 is supplied to the source driver circuit 22 as an image signal, the image signal is attenuated and the source driver circuit 22 may not recognize the image signal correctly. For example, when the image signal is a digital signal, the source driver circuit 22 may not correctly recognize whether the bit of the signal is "0" or "1". Further, it may take a long time to supply the image signal from the interface circuit 50 to the source driver circuit 22 due to attenuation of the image signal.

Therefore, in the display device 10 , the buffer circuit 25 is provided between the interface circuit 50 and the source driver circuit 22 . Specifically, for example, the buffer circuit 25 is provided such that the input terminal is electrically connected to the interface circuit 50 and the output terminal is electrically connected to the source driver circuit 22 as described above. Since the buffer circuit 25 can be a unity gain buffer as described above, even if the image signal output from the interface circuit 50 is attenuated, the attenuation is restored before the image signal is input to the source driver circuit 22. can be made As a result, the source driver circuit 22 can correctly recognize the image signal, so the reliability of the display device 10 can be improved. Also, the operation of the display device 10 can be speeded up. Note that the buffer circuit 25 can be provided in the layer 20 so as to have a region overlapping with the display section 33, as shown in FIG.

The gate driver circuits 21 and the source driver circuits 22 are not clearly separated and may have overlapping areas. This area is referred to as area 23 . By having the region 23, the area occupied by the gate driver circuit 21 and the source driver circuit 22 can be reduced. Therefore, even if the area of the display section 33 is small, the gate driver circuit 21 and the source driver circuit 22 can be provided without protruding from the display section 33 . Alternatively, the areas of the gate driver circuit 21 and the source driver circuit 22 that do not overlap with the display section 33 can be reduced. As described above, the frame can be made narrower than when the region 23 is not provided, and the size can be reduced.

FIG. 1 shows a configuration example in which one gate driver circuit 21, one source driver circuit 22, one buffer circuit 25, and one interface circuit 50 are provided in the layer 20, and one display section 33 is provided in the layer 30. FIG. However, a plurality of display portions 33 may be provided on the layer 30 . In other words, the display section provided on the layer 30 may be divided. FIG. 2 is a modification of the configuration shown in FIG. 1, and shows a configuration example of the display device 10 in which the layer 30 is provided with the display units 33 of 3 rows and 3 columns. The layer 30 may be provided with the display units 33 of 2 rows and 2 columns, or may be provided with the display units 33 of 4 rows and 4 columns or more. Further, the number of rows and the number of columns of the display portions 33 provided on the layer 30 may be different. In the display device 10 having the configuration shown in FIG. 2, for example, one image can be displayed using all the display units 33 .

In this specification and the like, for example, 1st row 1st column, 2nd row 1st column, 3rd row 1st column, 1st row 2nd column, 2nd row 2nd column, 3rd row 2nd column, 1st row 3rd column, 2 [1,1], [2,1], [3,1], [1,2], [2,2], [3, 2], [1,3], [2,3], and [3,3]. Further, various circuits corresponding to the display section 33, for example, various circuits having an area overlapping with the display section 33 are distinguished by the same notation. For example, the source driver circuit 22 having a region overlapping the display section 33[1,1] is described as a source driver circuit 22[1,1] to distinguish it from the other source driver circuits 22. FIG.

Although FIG. 2 omits the wiring 31 and the wiring 32 for clarity of illustration, the wiring 31 and the wiring 32 are actually provided in the display device 10 having the configuration shown in FIG. there is Also, although the input/output relationship of signals among the interface circuit 50, the buffer circuit 25, and the source driver circuit 22 is omitted, the aforementioned signals are actually input/output. It should be noted that in other drawings, some of the constituent elements and the like may be omitted as in FIG.

The display device 10 can be provided with the same number of gate driver circuits 21 , source driver circuits 22 , and buffer circuits 25 as the display section 33 , for example. In this case, the gate driver circuit 21 can be provided so as to have a region overlapping with the display portion 33 provided with the pixels 34 to which the gate driver circuit 21 supplies signals. Further, the source driver circuit 22 can be provided so as to have a region overlapping with the display portion 33 provided with the pixels 34 to which the source driver circuit 22 supplies signals.

Further, the display device 10 can be provided with an interface circuit 50 for each column of the display section 33 as shown in FIG. 2, for example. In the display device 10 having the configuration shown in FIG. 2, since the three-column display section 33 is provided on the layer 30, three interface circuits 50 are provided. Further, the layer 20 can be provided with an interface circuit 50 for each row of the display section 33, for example. Alternatively, layer 20 may be provided with only one interface circuit 50 . Alternatively, layer 20 may be provided with interface circuits 50 for each row and column. In this case, if the display device 10 is provided with the display section 33 of 3 rows and 3 columns, six interface circuits 50 can be provided.

In this specification and the like, for example, the interface circuits 50 corresponding to the first, second, and third columns of the display units 33 are distinguished by notations [1], [2], and [3], respectively.

A plurality of display portions 33 are provided, and a gate driver circuit 21, a source driver circuit 22, a buffer circuit 25, and an interface circuit 50 are provided accordingly, thereby reducing the number of pixels 34 provided in one display portion 33. can be done. The plurality of gate driver circuits 21 can be operated in parallel, and the plurality of source driver circuits 22 can be operated in parallel. to the pixel 34 can be shortened. Therefore, the length of one frame period can be shortened, and the operation speed of the display device 10 can be increased. Therefore, the number of pixels 34 included in the display device 10 can be increased, and the definition of the display device 10 can be improved. Further, the resolution of an image that can be displayed by the display device 10 can be made higher than the resolution of an image that can be displayed by a display device having a configuration in which the gate driver circuit and the source driver circuit do not overlap the display section. Furthermore, since the clock frequency can be reduced, the power consumption of the display device 10 can be reduced.

Here, when the gate driver circuit and the source driver circuit do not overlap with the display portion, the gate driver circuit and the source driver circuit are provided, for example, in the outer peripheral portion of the display portion. In this case, it is difficult to provide more display portions than 2 rows and 2 columns from the viewpoint of installation locations of the gate driver circuit and the source driver circuit. On the other hand, in the display device 10, the gate driver circuit and the source driver circuit can be provided in a layer different from the layer in which the display portion is provided so as to have a region overlapping with the display portion. More than two rows and two columns of displays can be provided as shown.

As described above, by providing the gate driver circuit 21 and the source driver circuit 22 so as to have a region overlapping with the display section 33, the display device 10 has a configuration in which the gate driver circuit and the source driver circuit do not overlap with the display section. More display units 33 can be provided than the display device of . By providing many display portions, the number of pixels provided in one display portion can be reduced. Thereby, the display device 10 can be operated at high speed, for example. Therefore, the definition of the display device 10 can be made higher than that of a display device in which the gate driver circuit and the source driver circuit do not overlap the display section. For example, the pixel density of the display device 10 can be 1000 ppi or more, can be 5000 ppi or more, and can be 10000 ppi. Therefore, the display device 10 can display a high-quality image with little graininess, and can display an image with a high presence. Therefore, the display device 10 can be suitably used particularly for devices in which the display surface is close to the user, particularly portable electronic devices, wearable electronic devices (wearable devices), electronic book terminals, and the like. Moreover, it can be suitably used for VR equipment, AR equipment, and the like. Furthermore, it can be suitably used for a viewfinder such as an electronic viewfinder provided in a digital camera or the like, which is an electronic device having an imaging device.

Further, the resolution of an image that can be displayed by the display device 10 can be made higher than the resolution of an image that can be displayed by a display device having a configuration in which the gate driver circuit and the source driver circuit do not overlap the display section. For example, when the display device 10 is used as a viewfinder, the display device 10 is capable of displaying 4K, 5K, or higher resolution images.

FIG. 3 is a diagram showing electrical connections among the interface circuit 50, the buffer circuit 25, and the source driver circuit 22 in the display device 10 configured as shown in FIG.

The interface circuit 50[1] is electrically connected to the input terminal of the buffer circuit 25[1,1]. The output terminal of the buffer circuit 25[1,1] is electrically connected to the input terminals of the source driver circuit 22[1,1] and the buffer circuit 25[2,1]. The output terminal of the buffer circuit 25[2,1] is electrically connected to the input terminals of the source driver circuit 22[2,1] and the buffer circuit 25[3,1]. The output terminal of the buffer circuit 25[3,1] is electrically connected to the source driver circuit 22[3,1].

The interface circuit 50[2] is electrically connected to the input terminals of the buffer circuit 25[1,2]. Output terminals of the buffer circuit 25[1,2] are electrically connected to input terminals of the source driver circuit 22[1,2] and the buffer circuit 25[2,2]. The output terminal of the buffer circuit 25[2,2] is electrically connected to the input terminals of the source driver circuit 22[2,2] and the buffer circuit 25[3,2]. The output terminal of the buffer circuit 25[3,2] is electrically connected to the source driver circuit 22[3,2].

The interface circuit 50[3] is electrically connected to the input terminals of the buffer circuit 25[1,3]. Output terminals of the buffer circuit 25[1,3] are electrically connected to input terminals of the source driver circuit 22[1,3] and the buffer circuit 25[2,3]. Output terminals of the buffer circuit 25[2,3] are electrically connected to input terminals of the source driver circuit 22[2,3] and the buffer circuit 25[3,3]. The output terminal of the buffer circuit 25[3,3] is electrically connected to the source driver circuit 22[3,3].

As described above, the interface circuit 50 is provided, for example, on the outer periphery of the display device 10 . Therefore, for example, as shown in FIGS. 2 and 3, when the interface circuit 50 is provided for each column of the display section 33, the wiring distance from the interface circuit 50 to the source driver circuit 22 in the second row is 1.5 mm from the interface circuit 50. It is longer than the wiring distance to the source driver circuit 22 of the row. For example, the wiring distance from the interface circuit 50[1] to the source driver circuit 22[2,1] is longer than the wiring distance from the interface circuit 50[1] to the source driver circuit 22[1,1]. Therefore, for example, when the image data received by the interface circuit 50[1] is supplied as an image signal to the source driver circuit 22[2,1], the image signal is input to the buffer circuit 25[2,1]. image signal may be attenuated. As a result, even if the image signal is passed through the buffer circuit 25[2,1], the source driver circuit 22[2,1] may not be able to recognize the image signal correctly. Further, due to attenuation of the image signal, it may take a long time to supply the image signal from the interface circuit 50[1] to the source driver circuit 22[2,1].

Therefore, it is preferable to pass the image signal output from the interface circuit 50 through the buffer circuit 25 in the first row and then through the buffer circuit 25 in the second row. This can prevent the image signal from attenuating before it is input to the buffer circuit 25 on the second row. For example, by passing the image signal output from the interface circuit 50[1] through the buffer circuit 25[1,1] and then through the buffer circuit 25[2,1], the image signal is transferred to the buffer circuit 25[2,1]. 1] can be suppressed. As a result, for example, the source driver circuit 22[2,1] can correctly recognize the image signal, so the reliability of the display device 10 can be improved. Also, the operation of the display device 10 can be speeded up.

Also, the wiring distance from the interface circuit 50 to the source driver circuit 22 in the third row is longer than the wiring distance from the interface circuit 50 to the source driver circuit 22 in the second row. For example, the wiring distance from the interface circuit 50[1] to the source driver circuit 22[3,1] is longer than the wiring distance from the interface circuit 50[1] to the source driver circuit 22[2,1]. Therefore, for example, when the image data received by the interface circuit 50[1] is supplied as an image signal to the source driver circuit 22[3,1], the image signal is input to the buffer circuit 25[3,1]. image signal may be attenuated.

Therefore, it is preferable to pass the image signal output from the interface circuit 50 through the buffer circuit 25 on the first row and the buffer circuit 25 on the second row before passing it through the buffer circuit 25 on the third row. This can prevent the image signal from attenuating before it is input to the buffer circuit 25 on the third row. For example, by passing the image signal output from the interface circuit 50[1] through the buffer circuit 25[1,1] and the buffer circuit 25[2,1] and then through the buffer circuit 25[3,1] , the attenuation of the image signal before it is input to the buffer circuit 25[3,1] can be suppressed. As a result, for example, the source driver circuit 22[3,1] can correctly recognize the image signal, so the reliability of the display device 10 can be improved. Also, the operation of the display device 10 can be speeded up.

By configuring the display device 10 as described above, image signals supplied to the source driver circuit 22 having a long wiring distance from the interface circuit 50 can pass through many buffer circuits 25 . As a result, even the source driver circuit 22 with a long wiring distance from the interface circuit 50 can correctly recognize the image signal, so that the reliability of the display device 10 can be improved. Also, the operation of the display device 10 can be speeded up.

<Configuration Example 1 of Buffer Circuit>
FIG. 4 is a circuit diagram showing a specific configuration example of the buffer circuit 25[1,1], the buffer circuit 25[2,1], and the buffer circuit 25[3,1]. Note that FIG. 4 shows an interface circuit 50[1], a source driver circuit 22[1,1], a source driver circuit 22[2,1], and a source circuit 50[1] in order to show an electrical connection relationship with the buffer circuit 25. A driver circuit 22[3,1] is also shown. That is, it can be said that it is a diagram showing a specific configuration example of part of the display device 10 configured as shown in FIG.

Buffer circuit 25[1,1] has buffer element 28a[1,1], buffer element 28b[1,1], and buffer element 28c[1,1]. The buffer circuit 25[2,1] has a buffer element 28b[2,1] and a buffer element 28c[2,1]. The buffer circuit 25[3,1] has a buffer element 28c[3,1].

Buffer element 28a[1,1] has transistor 81a[1,1] and transistor 82a[1,1]. Buffer element 28b[1,1] includes transistor 81b[1,1] and transistor 82b[1,1]. Buffer element 28c[1,1] includes transistor 81c[1,1] and transistor 82c[1,1]. Buffer element 28b[2,1] includes transistor 81b[2,1] and transistor 82b[2,1]. Buffer element 28c[2,1] includes transistor 81c[2,1] and transistor 82c[2,1]. Buffer element 28c[3,1] includes transistor 81c[3,1] and transistor 82c[3,1].

One of the source and drain of the transistor 81a[1,1] and one of the source and drain of the transistor 82a[1,1] are electrically connected to the source driver circuit 22[1,1] through a wiring 29a. ing. The other of the source and the drain of the transistor 81a[1,1] and the gate of the transistor 81a[1,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82a[1,1] is electrically connected to the wiring 92. FIG. A gate of the transistor 82a[1,1] is electrically connected to the wiring 27a.

One of the source and drain of the transistor 81b[1,1] and one of the source and drain of the transistor 82b[1,1] are electrically connected to the gate of the transistor 82b[2,1]. The other of the source and the drain of the transistor 81b[1,1] and the gate of the transistor 81b[1,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82b[1,1] is electrically connected to the wiring 92 . A gate of the transistor 82b[1,1] is electrically connected to the interface circuit 50[1] through the wiring 27b.

One of the source and drain of the transistor 81c[1,1] and one of the source and drain of the transistor 82c[1,1] are electrically connected to the gate of the transistor 82c[2,1]. The other of the source and the drain of the transistor 81c[1,1] and the gate of the transistor 81c[1,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82c[1,1] is electrically connected to the wiring 92 . A gate of the transistor 82c[1,1] is electrically connected to the wiring 27c.

One of the source and drain of the transistor 81b[2,1] and one of the source and drain of the transistor 82b[2,1] are electrically connected to the source driver circuit 22[2,1] through a wiring 29b. ing. The other of the source and the drain of the transistor 81b[2,1] and the gate of the transistor 81b[2,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82b[2,1] is electrically connected to the wiring 92 .

One of the source and drain of the transistor 81c[2,1] and one of the source and drain of the transistor 82c[2,1] are electrically connected to the gate of the transistor 82c[3,1]. The other of the source and the drain of the transistor 81c[2,1] and the gate of the transistor 81c[2,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82c[2,1] is electrically connected to the wiring 92 .

One of the source and drain of the transistor 81c[3,1] and one of the source and drain of the transistor 82c[3,1] are electrically connected to the source driver circuit 22[3,1] through a wiring 29c. ing. The other of the source and the drain of the transistor 81c[3,1] and the gate of the transistor 81c[3,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82c[3,1] is electrically connected to the wiring 92 .

Here, the wiring 91 and the wiring 92 function as power supply lines, for example, and can supply a constant potential. For example, the wiring 91 can be supplied with a high potential and the wiring 92 can be supplied with a low potential.

Note that in FIG. 4, the transistors 81 and 82 included in the buffer element 28 are n-channel transistors. Transistor 82 can be a p-channel transistor.

In this specification and the like, the term "buffer element 28" indicates any of the buffer element 28a, the buffer element 28b, the buffer element 28c, and the like. Further, the term "transistor 81" refers to any of the transistors 81a, 81b, 81c, etc., and the term "transistor 82" refers to any of the transistors 82a, 82b, 82c, etc. show. It should be noted that the same description may be made for other elements and the like.

In the buffer element 28 having the configuration shown in FIG. 4, the gate of the transistor 82 can be used as an input terminal of the buffer circuit 25, and one of the source and drain of the transistor 81 and one of the source and drain of the transistor 82 can be used as the input terminal of the buffer circuit 25. can be used as an output terminal for

In the case where the buffer element 28 has the configuration shown in FIG. 4, when a high potential signal is input to the buffer element 28, the buffer element 28 outputs a low potential signal. Also, when a low-potential signal is input to the buffer element 28, the buffer element 28 outputs a high-potential signal. That is, the buffer element 28 having the configuration shown in FIG. 4 is an inverting buffer. Therefore, the bit of the image signal output from the interface circuit 50 and the bit of the signal input to the source driver circuit 22 may differ. Therefore, in order to make the bits of the image signal output from the interface circuit 50 the same as the bits of the signal input to the source driver circuit 22, for example, an inverter circuit is provided between the interface circuit 50 and the buffer circuit 25. can be provided.

In FIG. 4, the inverter circuit 26a is provided between the interface circuit 50[1] and the buffer element 28a[1,1], and the inverter circuit 26a is provided between the interface circuit 50[1] and the buffer element 28c[1,1]. 26c is provided. Specifically, the input terminal of the inverter circuit 26a is electrically connected to the interface circuit 50[1], and the output terminal of the inverter circuit 26a is electrically connected to the wiring 27a. An input terminal of the inverter circuit 26c is electrically connected to the interface circuit 50[1], and an output terminal of the inverter circuit 26c is electrically connected to the wiring 27c. The configuration of the inverter circuits 26a and 26c can be the same as that of the buffer element 28 when the buffer element 28 is an inverting buffer.

As shown in FIG. 4, the image signal input to the source driver circuit 22[1,1] passes through one buffer element 28 after being output from the interface circuit 50[1]. Therefore, by providing the inverter circuit 26a, the bits of the signal input to the source driver circuit 22[1,1] can be the same as the bits of the image signal output from the interface circuit 50[1]. . An image signal input to the source driver circuit 22[3,1] passes through three buffer elements 28 after being output from the interface circuit 50[1]. Therefore, by providing the inverter circuit 26c, the bits of the signal input to the source driver circuit 22[3,1] can be the same as the bits of the image signal output from the interface circuit 50[1]. . The image signal input to the source driver circuit 22[2,1] passes through two buffer elements 28 after being output from the interface circuit 50[1]. Therefore, even if an inverter circuit is not provided between the interface circuit 50[1] and the buffer element 28b[1,1], the bits of the signal input to the source driver circuit 22[2,1] can be It can be the same as the bit of the image signal output from the interface circuit 50[1].

Note that the inverter circuit 26a and the inverter circuit 26c do not have to be provided between the interface circuit 50[1] and the buffer circuit 25[1,1]. For example, the inverter circuit 26a may be provided between the buffer element 28a[1,1] and the source driver circuit 22[1,1]. Further, the inverter circuit 26c may be provided between the buffer element 28c[1,1] and the buffer element 28c[2,1], or may be provided between the buffer element 28c[2,1] and the buffer element 28c[3,1]. ], or between the buffer element 28c[3,1] and the source driver circuit 22[3,1].

The buffer circuit 25[1,2] and the buffer circuit 25[1,3] illustrated in FIG. 3 can have the same configuration as the buffer circuit 25[1,1]. Further, the buffer circuit 25[2,2] and the buffer circuit 25[2,3] can have the same configuration as the buffer circuit 25[2,1]. Furthermore, the buffer circuit 25[3,2] and the buffer circuit 25[3,3] can have the same configuration as the buffer circuit 25[3,1]. In this case, for example, an inverter circuit 26a and an inverter circuit 26c can be provided between the interface circuit 50[2] and the buffer circuit 25[1,2]. Further, for example, an inverter circuit 26a and an inverter circuit 26c can be provided between the interface circuit 50[3] and the buffer circuit 25[1,3].

<Configuration Example 2 of Buffer Circuit>
FIG. 5 is a circuit diagram showing a specific configuration example of the buffer circuit 25[1,1], the buffer circuit 25[2,1], and the buffer circuit 25[3,1], and the configuration shown in FIG. It is a modification of the example. The configuration shown in FIG. 5 differs from the configuration shown in FIG. 4 in that the buffer element 28 has transistors 93 and 94 in addition to the transistors 81 and 82 .

Specifically, buffer element 28a[1,1] has transistor 93a[1,1] and transistor 94a[1,1]. Buffer element 28b[1,1] has transistor 93b[1,1] and transistor 94b[1,1]. Buffer element 28c[1,1] has transistor 93c[1,1] and transistor 94c[1,1]. Buffer element 28b[2,1] includes transistor 93b[2,1] and transistor 94b[2,1]. Buffer element 28c[2,1] includes transistor 93c[2,1] and transistor 94c[2,1]. Buffer element 28c[3,1] includes transistor 93c[3,1] and transistor 94c[3,1].

One of the source and drain of the transistor 81a[1,1] and one of the source and drain of the transistor 82a[1,1] are electrically connected to the gate of the transistor 93a[1,1]. The other of the source and the drain of the transistor 81a[1,1] and the gate of the transistor 81a[1,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82a[1,1] is electrically connected to the wiring 92. FIG. One of the source and drain of the transistor 93a[1,1] and one of the source and drain of the transistor 94a[1,1] are electrically connected to the source driver circuit 22[1,1] through a wiring 29a. ing. The other of the source and the drain of the transistor 93a[1,1] is electrically connected to the wiring 95 . The other of the source and the drain of the transistor 94a[1,1] is electrically connected to the wiring 96. FIG. A gate of the transistor 82a[1,1] and a gate of the transistor 94a[1,1] are electrically connected to the wiring 27a.

One of the source and drain of the transistor 81b[1,1] and one of the source and drain of the transistor 82b[1,1] are electrically connected to the gate of the transistor 93b[1,1]. The other of the source and the drain of the transistor 81b[1,1] and the gate of the transistor 81b[1,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82b[1,1] is electrically connected to the wiring 92 . One of the source or drain of transistor 93b[1,1] and one of the source or drain of transistor 94b[1,1] is connected to the gate of transistor 82b[2,1] and the gate of transistor 94b[2,1]. is electrically connected to The other of the source and the drain of the transistor 93b[1,1] is electrically connected to the wiring 95 . The other of the source and the drain of the transistor 94b[1,1] is electrically connected to the wiring 96 . A gate of the transistor 82b[1,1] and a gate of the transistor 94b[1,1] are electrically connected to the wiring 27b.

One of the source and drain of the transistor 81c[1,1] and one of the source and drain of the transistor 82c[1,1] are electrically connected to the gate of the transistor 93c[1,1]. The other of the source and the drain of the transistor 81c[1,1] and the gate of the transistor 81c[1,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82c[1,1] is electrically connected to the wiring 92 . One of the source or drain of transistor 93c[1,1] and one of the source or drain of transistor 94c[1,1] is connected to the gate of transistor 82c[2,1] and the gate of transistor 94c[2,1]. is electrically connected to The other of the source and the drain of the transistor 93c[1,1] is electrically connected to the wiring 95 . The other of the source and the drain of the transistor 94c[1,1] is electrically connected to the wiring 96 . A gate of the transistor 82c[1,1] and a gate of the transistor 94c[1,1] are electrically connected to the wiring 27c.

One of the source and drain of the transistor 81b[2,1] and one of the source and drain of the transistor 82b[2,1] are electrically connected to the gate of the transistor 93b[2,1]. The other of the source and the drain of the transistor 81b[2,1] and the gate of the transistor 81b[2,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82b[2,1] is electrically connected to the wiring 92 . One of the source and drain of the transistor 93b[2,1] and one of the source and drain of the transistor 94b[2,1] are electrically connected to the source driver circuit 22[2,1] through a wiring 29b. ing. The other of the source and the drain of the transistor 93b[2,1] is electrically connected to the wiring 95 . The other of the source and the drain of the transistor 94b[2,1] is electrically connected to the wiring 96. FIG.

One of the source and drain of the transistor 81c[2,1] and one of the source and drain of the transistor 82c[2,1] are electrically connected to the gate of the transistor 93c[2,1]. The other of the source and the drain of the transistor 81c[2,1] and the gate of the transistor 81c[2,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82c[2,1] is electrically connected to the wiring 92 . One of the source or drain of transistor 93c[2,1] and one of the source or drain of transistor 94c[2,1] is connected to the gate of transistor 82c[3,1] and the gate of transistor 94c[3,1]. is electrically connected to The other of the source and the drain of the transistor 93 c [2, 1] is electrically connected to the wiring 95 . The other of the source and the drain of the transistor 94 c[2,1] is electrically connected to the wiring 96 .

One of the source and drain of the transistor 81c[3,1] and one of the source and drain of the transistor 82c[3,1] are electrically connected to the gate of the transistor 93c[3,1]. The other of the source and the drain of the transistor 81c[3,1] and the gate of the transistor 81c[3,1] are electrically connected to the wiring 91 . The other of the source and the drain of the transistor 82c[3,1] is electrically connected to the wiring 92 . One of the source and drain of the transistor 93c[3,1] and one of the source and drain of the transistor 94c[3,1] are electrically connected to the source driver circuit 22[3,1] through a wiring 29c. ing. The other of the source and the drain of the transistor 93c[3,1] is electrically connected to the wiring 95 . The other of the source and the drain of the transistor 94c[3,1] is electrically connected to the wiring 96 .

Here, the wirings 95 and 96, like the wirings 91 and 92, function as power supply lines, for example, and can supply a constant potential. For example, the wiring 95 can be supplied with a high potential and the wiring 96 can be supplied with a low potential. Further, the potential supplied to the wiring 91 can be higher than the potential supplied to the wiring 95 .

Note that although the transistors 93 and 94 are n-channel transistors in FIGS. 5A and 5B, the transistors 93 and 94 can be changed to p-channel transistors by supplying a low potential to the wiring 95 and a high potential to the wiring 96, for example. type transistor.

In the buffer element 28 having the structure shown in FIG. 5, the gate of the transistor 82 and the gate of the transistor 94 can be used as input terminals of the buffer circuit 25, and one of the source and drain of the transistor 93 and the source or drain of the transistor 94 can be used. can be used as the output terminal of the buffer circuit 25 .

By configuring buffer circuit 25 as shown in FIG. 5, attenuation of the potential of the signal output from buffer circuit 25 due to the threshold voltage of transistor 81 or the like can be suppressed. As a result, for example, the source driver circuit 22 can correctly recognize the signal, so the reliability of the display device 10 can be improved. Also, the operation of the display device 10 can be speeded up.

<Configuration Example 3 of Buffer Circuit>
FIG. 6 is a circuit diagram showing a configuration example of buffer circuit 25[1,1], buffer circuit 25[2,1], and buffer circuit 25[3,1], which is different from the configuration shown in FIG. As in FIG. 4, FIG. 6 shows an interface circuit 50[1], a source driver circuit 22[1,1], and a source driver circuit 22[2] in order to show an electrical connection relationship with the buffer circuit 25. , 1], and the source driver circuit 22[3,1] are also shown. That is, it can be said that it is a diagram showing a specific configuration example of part of the display device 10 configured as shown in FIG.

4, buffer circuit 25[1,1] has buffer element 28a[1,1], buffer element 28b[1,1], and buffer element 28c[1,1]. Also, the buffer circuit 25[2,1] has a buffer element 28b[2,1] and a buffer element 28c[2,1]. Further, the buffer circuit 25[3,1] has a buffer element 28c[3,1].

The buffer element 28a[1,1] shown in FIG. 6 has a transistor 84a[1,1], a transistor 85a[1,1], and a transistor 86a[1,1]. Buffer element 28b[1,1] includes transistor 84b[1,1], transistor 85b[1,1], and transistor 86b[1,1]. Buffer element 28c[1,1] includes transistor 84c[1,1], transistor 85c[1,1], and transistor 86c[1,1]. Buffer element 28b[2,1] includes transistor 84b[2,1], transistor 85b[2,1], and transistor 86b[2,1]. Buffer element 28c[2,1] includes transistor 84c[2,1], transistor 85c[2,1], and transistor 86c[2,1]. Buffer element 28c[3,1] includes transistor 84c[3,1], transistor 85c[3,1], and transistor 86c[3,1].

One of the source and drain of the transistor 84a[1,1] and one of the source and drain of the transistor 85a[1,1] are electrically connected to the source driver circuit 22[1,1] through a wiring 29a. ing. The other of the source and the drain of the transistor 84a[1,1] is electrically connected to the wiring 91. FIG. A gate of the transistor 84a[1,1] is electrically connected to the wiring 87a. The other of the source and drain of the transistor 85a[1,1] is electrically connected to one of the source and drain of the transistor 86a[1,1]. A gate of the transistor 85a[1,1] is electrically connected to the wiring 27a. The other of the source and the drain of the transistor 86a[1,1] is electrically connected to the wiring 92. FIG. A gate of the transistor 86a[1,1] is electrically connected to the wiring 88a[1,1].

One of the source and the drain of the transistor 84b[1,1] and one of the source and the drain of the transistor 85b[1,1] are electrically connected to the wiring 83b[1,1]. The other of the source and the drain of the transistor 84b[1,1] is electrically connected to the wiring 91 . A gate of the transistor 84b[1,1] is electrically connected to the wiring 87b. The other of the source or drain of the transistor 85b[1,1] is electrically connected to one of the source or drain of the transistor 86b[1,1]. A gate of the transistor 85b[1,1] is electrically connected to the interface circuit 50[1] through the wiring 27b. The other of the source and the drain of the transistor 86b[1,1] is electrically connected to the wiring 92 . A gate of the transistor 86b[1,1] is electrically connected to the wiring 88b[1,1].

One of the source and drain of the transistor 84c[1,1] and one of the source and drain of the transistor 85c[1,1] are electrically connected to the wiring 83c[1,1]. The other of the source and the drain of the transistor 84 c [1, 1] is electrically connected to the wiring 91 . A gate of the transistor 84c[1,1] is electrically connected to the wiring 87c. The other of the source and drain of the transistor 85c[1,1] is electrically connected to one of the source and drain of the transistor 86c[1,1]. A gate of the transistor 85c[1,1] is electrically connected to the wiring 27c. The other of the source and the drain of the transistor 86c[1,1] is electrically connected to the wiring 92 . A gate of the transistor 86c[1,1] is electrically connected to the wiring 88c[1,1].

One of the source and drain of the transistor 84b[2,1] and one of the source and drain of the transistor 85b[2,1] are electrically connected to the source driver circuit 22[2,1] through a wiring 29b. ing. The other of the source and the drain of the transistor 84b[2,1] is electrically connected to the wiring 91 . A gate of the transistor 84b[2,1] is electrically connected to the wiring 87b. The other of the source or drain of the transistor 85b[2,1] is electrically connected to one of the source or drain of the transistor 86b[2,1]. A gate of the transistor 85b[2,1] is electrically connected to the wiring 83b[1,1]. The other of the source and the drain of the transistor 86b[2,1] is electrically connected to the wiring 92 . A gate of the transistor 86b[2,1] is electrically connected to the wiring 88b[2,1].

One of the source and the drain of the transistor 84c[2,1] and one of the source and the drain of the transistor 85c[2,1] are electrically connected to the wiring 83c[2,1]. The other of the source and the drain of the transistor 84 c[2,1] is electrically connected to the wiring 91 . A gate of the transistor 84c[2,1] is electrically connected to the wiring 87c. The other of the source and drain of the transistor 85c[2,1] is electrically connected to one of the source and drain of the transistor 86c[2,1]. A gate of the transistor 85c[2,1] is electrically connected to the wiring 83c[1,1]. The other of the source and the drain of the transistor 86 c[2,1] is electrically connected to the wiring 92 . A gate of the transistor 86c[2,1] is electrically connected to the wiring 88c[2,1].

One of the source and drain of the transistor 84c[3,1] and one of the source and drain of the transistor 85c[3,1] are electrically connected to the source driver circuit 22[3,1] through a wiring 29c. ing. The other of the source and the drain of the transistor 84c[3,1] is electrically connected to the wiring 91 . A gate of the transistor 84c[3,1] is electrically connected to the wiring 87c. The other of the source or drain of the transistor 85c[3,1] is electrically connected to one of the source or drain of the transistor 86c[3,1]. A gate of the transistor 85c[3,1] is electrically connected to the wiring 83c[2,1]. The other of the source and the drain of the transistor 86c[3,1] is electrically connected to the wiring 92 . A gate of the transistor 86c[3,1] is electrically connected to the wiring 88c[3,1].

As described above, the wiring 91 can be supplied with a high potential and the wiring 92 can be supplied with a low potential.

Note that although the transistors 84 to 86 included in the buffer element 28 are n-channel transistors in FIGS. 6A and 6B, the transistors 84 to 86 may be p-channel transistors, for example, by appropriately switching the high potential and the low potential. can be done.

Also, the wiring 87 and the wiring 88 can be electrically connected to the gate driver circuit 21 shown in FIG. 2, for example. In this case, the gate driver circuit 21 can have a function of generating a signal for controlling the operation of the buffer circuit 25 and supplying the signal to the buffer circuit 25 via the wiring 87 or wiring 88 .

In the buffer element 28 having the configuration shown in FIG. 6, the gate of the transistor 85 can be used as an input terminal of the buffer circuit 25, and one of the source and drain of the transistor 84 and one of the source and drain of the transistor 85 can be used as the input terminal of the buffer circuit 25. can be used as an output terminal for

[An example of the operation method of the buffer element]
Next, an example of a method of operating the buffer element 28 having the configuration shown in FIG. 6 will be described. FIG. 7 is a timing chart showing an example of how the buffer element 28a[1,1] operates. FIG. 8 is a timing chart showing an example of how the buffer elements 28b[1,1] and 28b[2,1] operate. Further, FIG. 9 is a timing chart showing an example of how the buffer element 28c[1,1], the buffer element 28c[2,1], and the buffer element 28c[3,1] operate. 7 to 9, "H" indicates a high potential and "L" indicates a low potential. In addition, the same notation may be used in other drawings and the like.

An example of how buffer element 28a[1,1] operates will now be described with reference to FIG. First, at time T01, the potential of the wiring 87a is set to a high potential, and the potential of the wiring 88a[1,1] is set to a low potential. As a result, the transistor 84a[1,1] is turned on and the transistor 86a[1,1] is turned off. Thereby, the potential of the wiring 29a is reset.

After that, the potential of the wiring 27a becomes a potential corresponding to the potential of the image signal output from the interface circuit 50[1]. As a result, a signal corresponding to the image signal is input to the buffer element 28a[1,1] through the wiring 27a. Here, it is assumed that the potential of the wiring 27a is high. As a result, the transistor 85a[1,1] becomes conductive.

At time T02, the potential of the wiring 87a is set to a low potential, and the potential of the wiring 88a[1,1] is set to a high potential. As a result, the transistor 84a[1,1] is rendered non-conductive and the transistor 86a[1,1] is rendered conductive. As a result, the transistor 85a[1,1] and the transistor 86a[1,1] are turned on, and the potential of the wiring 29a becomes low, which is the potential of the wiring 92. FIG. Therefore, a low-potential signal is supplied to the source driver circuit 22[1,1].

Here, the signal input to the buffer element 28a[1,1] through the wiring 27a is a high-potential signal. On the other hand, the interface circuit 50[1] is electrically connected to the input terminal of the inverter circuit 26a, and the output terminal of the inverter circuit 26b is electrically connected to the wiring 27a. From the above, it can be said that the interface circuit 50[1] outputs a low-potential image signal. Therefore, it can be said that both the image signal output from the interface circuit 50[1] and the signal input to the source driver circuit 22[1,1] are low potential signals.

At time T03, the potential of the wiring 87a is set to a high potential, and the potential of the wiring 88a[1,1] is set to a low potential. As a result, the transistor 84a[1,1] is turned on and the transistor 86a[1,1] is turned off. Thereby, the potential of the wiring 29a is reset.

After that, the potential of the wiring 27a becomes a potential corresponding to the potential of the image signal output from the interface circuit 50[1]. As a result, a signal corresponding to the image signal is input to the buffer element 28a[1,1] through the wiring 27a. Here, it is assumed that the potential of the wiring 27a is low. As a result, the transistor 85a[1,1] is rendered non-conductive.

At time T04, the potential of the wiring 87a is set to a low potential, and the potential of the wiring 88a[1,1] is set to a high potential. As a result, the transistor 84a[1,1] is rendered non-conductive and the transistor 86a[1,1] is rendered conductive. However, since the transistor 85a[1,1] remains non-conductive, the potential of the wiring 29a is kept high. Therefore, a high-potential signal is supplied to the source driver circuit 22[1,1].

Here, since the signal input to the buffer element 28a[1,1] via the wiring 27a is a low-potential signal, it can be said that the interface circuit 50[1] outputs a high-potential image signal. . From the above, it can be said that both the image signal output from the interface circuit 50[1] and the signal input to the source driver circuit 22[1,1] are high-potential signals.

At time T05, the potential of the wiring 87a is set to a high potential, and the potential of the wiring 88a[1,1] is set to a low potential. As a result, the transistor 84a[1,1] is turned on and the transistor 86a[1,1] is turned off. Thereby, the potential of the wiring 29a is reset.

As described above, the resetting of the potential of the wiring 29a and the supply of the signal corresponding to the image signal output from the interface circuit 50[1] to the source driver circuit 22[1,1] are alternately repeated. The above is an example of the operation method of the buffer element 28a[1,1].

An example of how buffer element 28b[1,1] and buffer element 28b[2,1] operate will now be described with reference to FIG. First, at time T11, the potential of the wiring 87b is set to a high potential, and the potentials of the wirings 88a[1,1] and 88b[2,1] are set to a low potential. Accordingly, the transistors 84b[1,1] and 84b[2,1] are turned on, and the transistors 86b[1,1] and 86b[2,1] are turned off. Therefore, the potential of the wiring 83b[1,1] and the potential of the wiring 29b are high, which is the potential of the wiring 91 . Accordingly, the potential of the wiring 83b[1,1] and the potential of the wiring 29b are reset. Note that since the potential of the wiring 83b[1,1] is high, the transistor 85b[2,1] is turned on.

After that, the potential of the wiring 27b becomes a potential corresponding to the potential of the image signal output from the interface circuit 50[1]. As a result, a signal corresponding to the image signal is input to the buffer element 28b[1,1] via the wiring 27b. Here, it is assumed that the potential of the wiring 27b is high. As a result, the transistor 85b[1,1] becomes conductive.

At time T12, the potential of the wiring 87b is set to a low potential, and the potential of the wiring 88b[1,1] is set to a high potential. As a result, the transistors 84b[1,1] and 84b[2,1] are rendered non-conductive, and the transistor 86b[1,1] is rendered conductive. As a result, the transistor 85b[1,1] and the transistor 86b[1,1] are turned on, and the potential of the wiring 83b[1,1] becomes low, which is the potential of the wiring 92 . Therefore, the transistor 85b[2,1] becomes non-conductive.

At time T13, the potential of the wiring 88b[2,1] is set to a high potential. This renders transistor 86b[2,1] conductive. However, since the transistor 85b[2,1] remains non-conductive, the potential of the wiring 29b is kept high. Therefore, a high-potential signal is supplied to the source driver circuit 22[2,1].

Here, since the signal input to the buffer element 28b[1,1] through the wiring 27b is a high-potential signal, the image signal output from the interface circuit 50[1] and the source driver circuit 22[2] , 1] can be said to be high-potential signals.

At time T14, the potential of the wiring 87b is set to a high potential, and the potentials of the wirings 88b[1,1] and 88b[2,1] are set to a low potential. Accordingly, the transistors 84b[1,1] and 84b[2,1] are turned on, and the transistors 86b[1,1] and 86b[2,1] are turned off. Therefore, the potential of the wiring 83b[1,1] and the potential of the wiring 29b are high, which is the potential of the wiring 91 . Accordingly, the potential of the wiring 83b[1,1] and the potential of the wiring 29b are reset. Note that since the potential of the wiring 83b[1,1] is high, the transistor 85b[2,1] is turned on.

After that, the potential of the wiring 27b becomes a potential corresponding to the potential of the image signal output from the interface circuit 50[1]. As a result, a signal corresponding to the image signal is input to the buffer element 28b[1,1] via the wiring 27b. Here, it is assumed that the potential of the wiring 27b is low. As a result, the transistor 85b[1,1] is rendered non-conductive.

At time T15, the potential of the wiring 87b is set to a low potential, and the potential of the wiring 88b[1,1] is set to a high potential. As a result, the transistors 84b[1,1] and 84b[2,1] are rendered non-conductive, and the transistor 86b[1,1] is rendered conductive. However, since the transistor 85b[1,1] remains off, the potential of the wiring 83b[1,1] is kept high. Therefore, transistor 85b[2,1] remains conductive.

At time T16, the potential of the wiring 88b[2,1] is set to a high potential. This renders transistor 86b[2,1] conductive. As a result, the transistor 85b[2,1] and the transistor 86b[2,1] are turned on, and the potential of the wiring 29b becomes low, which is the potential of the wiring 92 . Therefore, a low-potential signal is supplied to the source driver circuit 22[2,1].

Here, since the signal input to the buffer element 28b[1,1] through the wiring 27b is a low-potential signal, the image signal output by the interface circuit 50[1] and the source driver circuit 22[2] , 1] can be said to be low potential signals.

At time T17, the potential of the wiring 87b is set to a high potential, and the potentials of the wirings 88b[1,1] and 88b[2,1] are set to a low potential. Accordingly, the transistors 84b[1,1] and 84b[2,1] are turned on, and the transistors 86b[1,1] and 86b[2,1] are turned off. Therefore, the potential of the wiring 83b[1,1] and the potential of the wiring 29b are high, which is the potential of the wiring 91 . Accordingly, the potential of the wiring 83b[1,1] and the potential of the wiring 29b are reset. Note that since the potential of the wiring 83b[1,1] is high, the transistor 85b[2,1] is turned on.

As described above, the potential of the wiring 83b[1,1] and the potential of the wiring 29b are reset, and the signal corresponding to the image signal output from the interface circuit 50[1] is sent to the source driver circuit 22[2,1]. and the supply of , are alternately repeated. The above is an example of the operation method of the buffer element 28b[1,1] and the buffer element 28b[2,1].

An example of how buffer element 28c[1,1], buffer element 28c[2,1], and buffer element 28c[3,1] operate will now be described with reference to FIG. First, at time T21, the potential of the wiring 87c is set to a high potential, and the potentials of the wirings 88c[1,1], 88c[2,1], and 88c[3,1] are set to a low potential. . As a result, the transistors 84c[1,1], 84c[2,1], and 84c[3,1] become conductive, and the transistors 86c[1,1], 86c[2,1], and the transistors 86c[1,1] 86c[3,1] becomes non-conducting. Therefore, the potential of the wiring 83c[1,1], the potential of the wiring 83c[2,1], and the potential of the wiring 29c are high, which is the potential of the wiring 91 . Accordingly, the potential of the wiring 83c[1,1], the potential of the wiring 83c[2,1], and the potential of the wiring 29c are reset. Note that since the potential of the wiring 83c[1,1] is high, the transistor 85c[2,1] is turned on. Further, since the potential of the wiring 83c[2,1] is high, the transistor 85c[3,1] is turned on.

After that, the potential of the wiring 27c becomes a potential corresponding to the potential of the image signal output from the interface circuit 50[1]. As a result, a signal corresponding to the image signal is input to the buffer element 28c[1,1] via the wiring 27c. Here, it is assumed that the potential of the wiring 27c is high. As a result, the transistor 85c[1,1] becomes conductive.

At time T22, the potential of the wiring 87c is set low and the potential of the wiring 88c[1,1] is set high. As a result, transistors 84c[1,1], 84c[2,1], and 84c[3,1] are rendered non-conductive, and transistor 86c[1,1] is rendered conductive. As a result, the transistor 85c[1,1] and the transistor 86c[1,1] are turned on, and the potential of the wiring 83c[1,1] becomes low, which is the potential of the wiring 92 . Therefore, the transistor 85c[2,1] becomes non-conductive.

At time T23, the potential of the wiring 88c[2,1] is set to a high potential. This renders transistor 86c[2,1] conductive. However, since the transistor 85c[2,1] remains off, the potential of the wiring 83c[2,1] is kept high. Therefore, transistor 85c[3,1] remains conductive.

At time T24, the potential of the wiring 88c[3,1] is set to a high potential. This renders transistor 86c[3,1] conductive. As a result, the transistor 85c[3,1] and the transistor 86c[3,1] are turned on, and the potential of the wiring 29c becomes low, which is the potential of the wiring 92 . Therefore, a low-potential signal is supplied to the source driver circuit 22[3,1].

Here, the signal input to the buffer element 28c[1,1] through the wiring 27c is a high-potential signal. On the other hand, the interface circuit 50[1] is electrically connected to the input terminal of the inverter circuit 26c, and the output terminal of the inverter circuit 26c is electrically connected to the wiring 27c. From the above, it can be said that the interface circuit 50[1] outputs a low-potential image signal. Therefore, it can be said that both the image signal output from the interface circuit 50[1] and the signal input to the source driver circuit 22[3,1] are low potential signals.

At time T25, the potential of the wiring 87c is set to a high potential, and the potentials of the wirings 88c[1,1], 88c[2,1], and 88c[3,1] are set to a low potential. As a result, the transistors 84c[1,1], 84c[2,1], and 84c[3,1] become conductive, and the transistors 86c[1,1], 86c[2,1], and the transistors 86c[1,1] 86c[3,1] becomes non-conducting. Therefore, the potential of the wiring 83c[1,1], the potential of the wiring 83c[2,1], and the potential of the wiring 29c are high, which is the potential of the wiring 91 . Accordingly, the potential of the wiring 83c[1,1], the potential of the wiring 83c[2,1], and the potential of the wiring 29c are reset. Note that since the potential of the wiring 83c[1,1] is high, the transistor 85c[2,1] is turned on. Further, since the potential of the wiring 83c[2,1] is high, the transistor 85c[3,1] is turned on.

After that, the potential of the wiring 27c becomes a potential corresponding to the potential of the image signal output from the interface circuit 50[1]. As a result, a signal corresponding to the image signal is input to the buffer element 28c[1,1] via the wiring 27c. Here, it is assumed that the potential of the wiring 27c is low. This renders the transistor 85c[1,1] non-conductive.

At time T26, the potential of the wiring 87c is set low and the potential of the wiring 88c[1,1] is set high. As a result, transistors 84c[1,1], 84c[2,1], and 84c[3,1] are rendered non-conductive, and transistor 86c[1,1] is rendered conductive. However, since the transistor 85c[1,1] remains off, the potential of the wiring 83c[1,1] is kept high. Therefore, transistor 85c[2,1] remains conductive.

At time T27, the potential of the wiring 88c[2,1] is set to a high potential. This renders transistor 86c[2,1] conductive. As a result, the transistor 85c[2,1] and the transistor 86c[2,1] are brought into conduction, and the potential of the wiring 83c[2,1] becomes low, which is the potential of the wiring 92 . Therefore, the transistor 85c[3,1] becomes non-conductive.

At time T28, the potential of the wiring 88c[3,1] is set to a high potential. This renders transistor 86c[3,1] conductive. However, since the transistor 85c[3,1] remains non-conductive, the potential of the wiring 29c is kept high. Therefore, a high-potential signal is supplied to the source driver circuit 22[3,1].

Here, since the signal input to the buffer element 28c[1,1] via the wiring 27c is a low-potential signal, it can be said that the interface circuit 50[1] outputs a high-potential image signal. . From the above, it can be said that both the image signal output from the interface circuit 50[1] and the signal input to the source driver circuit 22[3,1] are high-potential signals.

At time T29, the potential of the wiring 87c is set high, and the potentials of the wirings 88c[1,1], 88c[2,1], and 88c[3,1] are set low. As a result, the transistors 84c[1,1], 84c[2,1], and 84c[3,1] become conductive, and the transistors 86c[1,1], 86c[2,1], and the transistors 86c[1,1] 86c[3,1] becomes non-conducting. Therefore, the potential of the wiring 83c[1,1], the potential of the wiring 83c[2,1], and the potential of the wiring 29c are high, which is the potential of the wiring 91 . Accordingly, the potential of the wiring 83c[1,1], the potential of the wiring 83c[2,1], and the potential of the wiring 29c are reset. Note that since the potential of the wiring 83c[1,1] is high, the transistor 85c[2,1] is turned on. Further, since the potential of the wiring 83c[2,1] is high, the transistor 85c[3,1] is turned on.

As described above, the potential of the wiring 83c[1,1], the potential of the wiring 83c[2,1], and the potential of the wiring 29c are reset, and the signal corresponding to the image signal output from the interface circuit 50[1] is reset. The supply to the source driver circuit 22[3,1] is alternately repeated. The above is an example of the operation method of the buffer element 28c[1,1], the buffer element 28c[2,1], and the buffer element 28c[3,1].

Note that the operation shown in FIG. 7, the operation shown in FIG. 8, and the operation shown in FIG. 9 can be performed in parallel.

Even if the polarities of the transistors 84 to 86 are the same in the buffer element 28 having the structure shown in FIG. can be done. Thereby, it is possible to suppress current from flowing from the wiring 91 to the wiring 92 . In other words, the flow of current through the transistor provided between the wiring 91 and the wiring 92 can be suppressed. Thereby, the power consumption of the display device 10 can be reduced.

Here, OS transistors can be applied to the transistors 84 and 85 . The metal oxide can have a bandgap of 2 eV or more, or 2.5 eV or more. Therefore, the OS transistor has extremely low leakage current (off current) in a non-conducting state. Therefore, by using OS transistors as the transistors 84 and 85, the potentials of the wirings 29 and 83 can be held for a long time.

As a metal oxide, In-M-Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or the like) may be used. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. Alternatively, indium oxide, zinc oxide, In—Ga oxide, In—Zn oxide, Ga—Zn oxide, or gallium oxide may be used as the metal oxide.

Note that as the transistors 84 to 86, transistors other than the OS transistor, such as a transistor including Si in a channel formation region (hereinafter referred to as a Si transistor), may be used. Here, the Si transistor includes a transistor containing amorphous silicon, a transistor containing crystalline silicon (typically, low-temperature polysilicon), a transistor containing monocrystalline silicon, and the like.

<Configuration Example 4 of Buffer Circuit>
FIG. 10 is a circuit diagram showing a specific configuration example of the buffer circuit 25[1,1], the buffer circuit 25[2,1], and the buffer circuit 25[3,1], and the configuration shown in FIG. It is a modification of the example. The configuration shown in FIG. 10 differs from the configuration shown in FIG. 6 in that a delay circuit 89 is provided.

As shown in FIG. 10, the wiring 88b[1,1] is electrically connected to the input terminal of the delay circuit 89b[1,1] as well as the gate of the transistor 86b[1,1]. The output terminal of the delay circuit 89b[1,1] is electrically connected to the gate of the transistor 86b[2,1] through the wiring 88b[2,1].

The wiring 88c[1,1] is electrically connected to the gate of the transistor 86c[1,1] and also to the input terminal of the delay circuit 89c[1,1]. The output terminal of the delay circuit 89c[1,1] is electrically connected to the gate of the transistor 86c[2,1] through the wiring 88c[2,1].

Further, the wiring 88c[2,1] is electrically connected to the input terminal of the delay circuit 89c[2,1] in addition to the gate of the transistor 86c[2,1]. The output terminal of the delay circuit 89c[2,1] is electrically connected to the gate of the transistor 86c[3,1] through the wiring 88c[3,1].

The delay circuit 89 has a function of delaying an input signal by a certain period and outputting the delayed signal. For example, it has a function of outputting an input signal after one clock period has elapsed. For example, it has a function of outputting an input signal after a lapse of 0.5 clock period.

In the case shown in FIG. 6, the potential of the wiring 88b[1,1] and the potential of the wiring 88b[2,1] are individually controlled. Further, the potential of the wiring 88c[1,1], the potential of the wiring 88c[2,1], and the potential of the wiring 88c[3,1] are individually controlled. On the other hand, in the case shown in FIG. 10, the potential of the wiring 88b[2,1] is automatically controlled by controlling the potential of the wiring 88b[1,1]. Further, by controlling the potential of the wiring 88c[1,1], the potentials of the wirings 88c[2,1] and 88c[3,1] are automatically controlled. As described above, the operation of the display device 10 can be easily controlled.

[An example of the operation method of the buffer element]
Next, an example of the operation method of the buffer element 28 in the case shown in FIG. 10 will be described. FIG. 11 is a timing chart showing an example of how the buffer element 28a[1,1] operates. FIG. 12 is a timing chart showing an example of how the buffer elements 28b[1,1] and 28b[2,1] operate. Further, FIG. 13 is a timing chart showing an example of how the buffer element 28c[1,1], the buffer element 28c[2,1], and the buffer element 28c[3,1] operate.

The operation method of buffer element 28a[1,1] in the case shown in FIG. 10 can be the same as the operation method of buffer element 28a[1,1] in the case shown in FIG. Therefore, the operation method shown in FIG. 11 is the same as the operation method shown in FIG.

When the buffer elements 28b[1,1] and 28b[2,1] operate, as shown in FIG. 12, the wiring 88b[1,1] is at a high potential at time T12, and the wiring 88b [1,1] becomes the low potential. Further, the potential of the wiring 88b[2,1] becomes high at time T13, and the potential of the wiring 88b[2,1] becomes low at time T14.

After that, the potential of the wiring 88b[1,1] becomes high at time T15, and the potential of the wiring 88b[1,1] becomes low at time T16. Further, the potential of the wiring 88b[2,1] becomes high at time T16, and the potential of the wiring 88b[2,1] becomes low at time T17.

That is, after the potential of the wiring 88b[1,1] becomes high, the potential of the wiring 88b[2,1] becomes high with a delay. Further, after the potential of the wiring 88b[1,1] becomes low, the potential of the wiring 88b[2,1] becomes low with a delay. Therefore, it can be said that the signal input to the wiring 88b[1,1] is input to the wiring 88b[2,1] with a delay. Note that in the operation method shown in FIG. 12, the time when the potential of the wiring 88b[1,1] becomes low and the time when the potential of the wiring 88b[2,1] becomes high are the same. They do not have to be identical. Although the period in which the potential of the wiring 88b[1,1] is high does not overlap with the period in which the potential of the wiring 88b[2,1] is high, there is a period in which they overlap. You may

When the display device 10 having the structure shown in FIG. 10 operates, as shown in FIG. 12, the length of the period during which the potential of the wiring 88b[1,1] is high is equal to the length of the period during which the potential of is high, for example. On the other hand, in the operation illustrated in FIG. 8, the length of the period during which the potential of the wiring 88b[1,1] is high is equal to the length of the period during which the potential of the wiring 88b[2,1] is high. can be longer than Note that even when the display device 10 having the configuration shown in FIG. 6 operates, the buffer element 28b[1,1] and the buffer element 28b[2,1] may be operated by the method shown in FIG.

When the buffer element 28c[1,1], the buffer element 28c[2,1], and the buffer element 28c[3,1] operate, the wiring 88c[1,1] is turned off at time T22 as shown in FIG. The potential becomes high, and the wiring 88c[1, 1] becomes low potential at time T23. Further, the potential of the wiring 88c[2,1] becomes high at time T23, and the potential of the wiring 88c[2,1] becomes low at time T24. Further, the potential of the wiring 88c[3,1] becomes high at time T24, and the potential of the wiring 88c[3,1] becomes low at time T25.

After that, the potential of the wiring 88c[1,1] becomes high at time T26, and the potential of the wiring 88c[1,1] becomes low at time T27. Further, the potential of the wiring 88c[2,1] becomes high at time T27, and the potential of the wiring 88c[2,1] becomes low at time T28. Further, the potential of the wiring 88c[3,1] becomes high at time T28, and the potential of the wiring 88c[3,1] becomes low at time T29.

That is, after the potential of the wiring 88c[1,1] becomes high, the potential of the wiring 88c[2,1] becomes high with a delay, and the potential of the wiring 88c[3,1] becomes high with a delay. becomes. After the potential of the wiring 88c[1,1] becomes low, the potential of the wiring 88c[2,1] becomes low with a delay, and the potential of the wiring 88c[3,1] becomes low with a delay. becomes. Therefore, it can be said that the signal input to the wiring 88c[1,1] is input to the wiring 88c[2,1] with a delay, and is further input to the wiring 88c[3,1] with a delay.

Note that in the operation method illustrated in FIG. 13, the time when the potential of the wiring 88c[1,1] becomes low is the same as the time when the potential of the wiring 88c[2,1] becomes high. They do not have to be identical. In the operation method shown in FIG. 13, the time when the potential of the wiring 88c[2,1] becomes low and the time when the potential of the wiring 88c[3,1] becomes high are the same. They do not have to be identical. In addition, in the operation method illustrated in FIG. 13, the period in which the potential of the wiring 88c[1,1] is high overlaps with the period in which the potential of the wiring 88c[2,1] is high. not, but may have overlapping periods. Although the period in which the potential of the wiring 88c[2,1] is high does not overlap with the period in which the potential of the wiring 88c[3,1] is high, there is a period in which they overlap. You may Further, a period in which the potential of the wiring 88c[1,1] is high and a period in which the potential of the wiring 88c[3,1] is high may overlap.

When the display device 10 having the configuration shown in FIG. 10 operates, as shown in FIG. For example, the length of the period during which the potential is maintained is equal to the length of the period during which the wiring 88c[3,1] is maintained at the high potential. On the other hand, in the operation illustrated in FIG. 9, the period during which the wiring 88c[1,1] is at a high potential is set longer than the period during which the wiring 88c[2,1] is at a high potential. can be done. In addition, the period during which the wiring 88c[2,1] is at a high potential can be longer than the period during which the wiring 88c[3,1] is at a high potential. Note that even when the display device 10 having the configuration shown in FIG. You may operate by the method shown.

<Configuration example of source driver circuit>
FIG. 14 is a block diagram showing a configuration example of the source driver circuit 22. As shown in FIG. Note that FIG. 14 also shows a buffer circuit 25 electrically connected to the source driver circuit 22 .

The source driver circuit 22 has a buffer circuit 43 , a shift register circuit 44 , a latch circuit 45 , a DA conversion circuit 46 and an amplifier circuit 47 . In FIG. 14, one source driver circuit 22 includes one buffer circuit 43, one shift register circuit 44, one latch circuit 45, one DA conversion circuit 46, and one amplifier circuit 47. A plurality of each of the above circuits can be provided. For example, one source driver circuit 22 includes a number of buffer circuits 43, shift register circuits 44, latch circuits 45, DA converters corresponding to the number of columns of pixels 34 provided in the display section 33 shown in FIG. A circuit 46 and an amplifier circuit 47 may be provided. For example, one source driver circuit 22 can be provided with the same number of circuits as the number of columns of pixels 34 provided in the display section 33 shown in FIG.

14, one source driver circuit 22 includes n buffer circuits 43, shift register circuits 44, latch circuits 45, DA conversion circuits 46, and amplifier circuits 47 (n is an integer of 2 or more). is shown. Here, the n buffer circuits 43, the shift register circuits 44, the latch circuits 45, the DA conversion circuits 46, and the amplifier circuits 47 are distinguished by notations [1] to [n], respectively.

The output terminal of buffer circuit 25 is electrically connected to the input terminal of buffer circuit 43 . The output terminal of the buffer circuit 43 and the shift register circuit 44 are electrically connected to the latch circuit 45 . The latch circuit 45 is electrically connected to the DA conversion circuit 46 . The DA conversion circuit 46 is electrically connected to the input terminal of the amplifier circuit 47 . An output terminal of the amplifier circuit 47 is electrically connected to the wiring 32 . Note that the wiring 32 electrically connected to the output terminal of the amplifier circuit 47[1] is denoted as wiring 32[1], and the wiring 32 electrically connected to the output terminal of the amplifier circuit 47[n]. is written as wiring 32[n].

The buffer circuit 43 can be a unity gain buffer, for example, and can have the same configuration as the buffer circuit 25 . That is, the buffer circuit 43 can be configured to have the buffer element 28 configured as shown in FIGS. 4 to 6 or 10, for example. The buffer circuit 43 can be configured to have one or two buffer elements 28, for example.

If the buffer circuit 43 is not provided in the source driver circuit 22, the signal output from the buffer circuit 25 is attenuated before being input to the source driver circuit 22, and the source driver circuit 22 may not recognize the signal correctly. For example, the signal output from the buffer circuit 25 may attenuate before being input to the latch circuit 45, and the source driver circuit 22 may not be able to recognize the signal correctly. Further, due to signal attenuation, it may take a long time for the source driver circuit 22 to process the signal. In particular, when the wiring distance between the buffer circuit 25 and the source driver circuit 22 is long, specifically, when the wiring distance between the buffer circuit 25 and the latch circuit 45 is long, for example, these problems become noticeable. There is

Therefore, by providing the buffer circuit 43 in the source driver circuit 22, even if the signal output from the buffer circuit 25 is attenuated, the attenuation can be recovered by the buffer circuit 43. FIG. As a result, the shift register circuit 44, the latch circuit 45, the DA conversion circuit 46, and the like included in the source driver circuit 22 can correctly recognize the signal input to the source driver circuit 22, and the reliability of the display device 10 is improved. can increase In addition, since the shift register circuit 44, the latch circuit 45, the DA conversion circuit 46, and the like included in the source driver circuit 22 can process the signal input to the source driver circuit 22 at high speed, the operation of the display device 10 can be improved. It can be faster.

Furthermore, since the wiring distance between the buffer circuit 25 and the source driver circuit 22 can be increased, the flexibility of arrangement of the buffer circuit 25 can be increased. Therefore, the flexibility of the layout of the display device 10 can be increased.

The shift register circuit 44 has a function of generating signals for controlling the operation of the latch circuit 45 . The latch circuit 45 has a function of holding or outputting the signal output by the buffer circuit 43 . Whether to hold or output the signal in the latch circuit 45 is selected based on the signal supplied from the shift register circuit 44 .

The DA conversion circuit 46 has a function of converting the digital image signal output by the latch circuit 45 into an analog image signal.

The amplifier circuit 47 has a function of amplifying the image signal output from the DA conversion circuit 46 and outputting it to the wiring 32 functioning as a data line. By providing the amplifier circuit 47, the image signal can be stably supplied to the pixel 34. FIG. A voltage follower circuit or the like having an operational amplifier or the like can be applied as the amplifier circuit 47 . Note that when a circuit having a differential input circuit is used as the amplifier circuit, it is preferable that the offset voltage of the differential input circuit is 0 V as much as possible.

<Configuration Example 2 of Display Device>
FIG. 15 is a block diagram showing a configuration example of the display device 10, which is a modification of the configuration shown in FIG. In the display device 10 configured as shown in FIG. 15, two gate driver circuits 21 (gate driver circuit 21a and gate driver circuit 21b) are provided for one display unit 33, and two source driver circuits 22 (source driver circuit 21b) are provided. A driver circuit 22a and a source driver circuit 22b) are provided. Three or more gate driver circuits 21 may be provided for one display unit 33, four gate driver circuits 21 may be provided, or five or more gate driver circuits 21 may be provided. Further, three or more source driver circuits 22 may be provided for one display section 33, four or more may be provided, or five or more may be provided.

Here, even if two or more source driver circuits 22 are provided for one display section 33, the number of buffer circuits 25 may be one for one display section 33. can. Two or more buffer circuits 25 may be provided. For example, although the buffer circuit 25 is provided in the vicinity of the source driver circuit 22a in FIG. 15, the buffer circuit 25 may also be provided in the vicinity of the source driver circuit 22b.

In the display device 10 having the configuration shown in FIG. 15, the odd-numbered pixels 34 are electrically connected to the gate driver circuit 21a through the wiring 31a, and the even-numbered pixels 34 are connected to the gate driver circuit 21a through the wiring 31b. It is electrically connected to the circuit 21b. The wiring 31 a and the wiring 31 b function as scanning lines like the wiring 31 .

In addition, in the display device 10 having the configuration shown in FIG. 15, the odd-numbered pixels 34 are electrically connected to the source driver circuit 22a via the wiring 32a, and the even-numbered pixels 34 are electrically connected to the source driver circuit 22a via the wiring 32b. It is electrically connected to the source driver circuit 22b. The wiring 32a and the wiring 32b, like the wiring 32, function as data lines.

The gate driver circuit 21a has a function of generating a signal for controlling the operation of the odd-numbered pixels 34 and supplying the signal to the odd-numbered pixels 34 via the wiring 31a. The gate driver circuit 21b has a function of generating a signal for controlling the operation of the even-numbered pixels 34 and supplying the signal to the even-numbered pixels 34 via the wiring 31b.

The source driver circuit 22a has a function of supplying a signal corresponding to the image signal output from the buffer circuit 25 to the odd-numbered pixels 34 via the wiring 32a. The source driver circuit 22b has a function of supplying a signal corresponding to the image signal output from the buffer circuit 25 to the even-numbered pixels 34 via the wiring 32b.

The gate driver circuits 21 a and 21 b and the source driver circuits 22 a and 22 b have regions overlapping the display section 33 . For example, the gate driver circuits 21 a and 21 b and the source driver circuits 22 a and 22 b have regions that overlap the pixels 34 .

The gate driver circuit 21a and the source driver circuit 22a may have a region 23a that is not clearly separated and is an overlapping region. The gate driver circuit 21b and the source driver circuit 22a may have a region 23b that is not clearly separated and is an overlapping region. The gate driver circuit 21a and the source driver circuit 22b may have a region 23c that is not clearly separated and is an overlapping region. The gate driver circuit 21b and the source driver circuit 22b may have a region 23d that is not clearly separated and is an overlapping region.

In the display device 10 having the configuration shown in FIG. 15, the gate driver circuit 21a is operated to write the image signals to all the pixels 34 of the odd-numbered rows, and then the gate driver circuit 21b is operated to write the image signals to all the pixels 34 of the even-numbered rows. 34 can be written with an image signal. In other words, the display device 10 configured as shown in FIG. 15 can be operated in an interlaced manner. By operating in the interlace mode, the operation speed of the display device 10 can be increased and the frame frequency can be increased. In addition, the number of pixels 34 to which image signals are written in one frame period can be reduced to half that in the case of operating the display device 10 by the progressive method. Therefore, when the display device 10 is operated by the interlace method, the clock frequency can be made smaller than when it is operated by the progressive method, so that the power consumption of the display device 10 can be reduced.

By providing a plurality of gate driver circuits 21 and source driver circuits 22 as shown in FIG. 15, the density of elements such as transistors constituting the gate driver circuits 21 and source driver circuits 22 can be reduced. Thereby, the degree of freedom of the layout of the display device 10 can be increased.

<Configuration example of gate driver circuit>
FIG. 16 is a block diagram showing a configuration example of the gate driver circuit 21. As shown in FIG. The gate driver circuit 21 has a shift register circuit SR composed of a plurality of set/reset flip-flops. The shift register circuit SR is electrically connected to a wiring 31 functioning as a scanning line and has a function of outputting a signal to the wiring 31 .

The signal RES is a reset signal, and by setting the signal RES to a high potential, for example, all the outputs of the shift register circuit SR can be set to a low potential. A signal SP is a start pulse signal, and by inputting this signal to the gate driver circuit 21, the shift operation by the shift register circuit SR can be started. The signal PWC is a pulse width control signal and has a function of controlling the pulse width of the signal output to the wiring 31 by the shift register circuit SR. Signal CLK[1], signal CLK[2], signal CLK[3], and signal CLK[4] are clock signals. One shift register SR has signals CLK[1] to CLK[4]. , for example, two signals can be input.

Note that the configuration shown in FIG. 16 can also be applied to the shift register circuit 44 and the like included in the source driver circuit 22 by using other wiring instead of the wiring 31 electrically connected to the shift register circuit SR. .

FIG. 17A is a diagram showing signals input to the shift register circuit SR and signals output from the shift register circuit SR. Here, FIG. 17A shows the case where the signal CLK[1] and the signal CLK[3] are input as clock signals.

A signal FO is an output signal, for example, a signal output to the wiring 31 . The signal SROUT is a shift signal, and can be the signal LIN input to the next-stage shift register circuit SR. Among the signals shown in FIG. 17A, the signal RES, the signal PWC, the signal CLK[1], the signal CLK[3], and the signal LIN are signals input to the shift register circuit SR. and a signal SROUT is a signal output from the shift register circuit SR.

FIG. 17B is a circuit diagram showing a configuration example of a shift register circuit SR whose input/output signals are the signals shown in FIG. 17A. The shift register circuit SR includes transistors 51 to 63 and capacitors 64 to 66 .

One of the source and drain of the transistor 51 is electrically connected to one of the source and drain of the transistor 52 , one of the source and drain of the transistor 56 , and one of the source and drain of the transistor 59 . The gate of the transistor 52 is one of the source and drain of the transistor 53, one of the source and drain of the transistor 54, one of the source and drain of the transistor 55, the gate of the transistor 58, the gate of the transistor 61, and one of the capacitor 64. It is electrically connected with the electrode. The other of the source and drain of the transistor 56 is electrically connected to the gate of the transistor 57 and one electrode of the capacitor 65 . The other of the source and drain of the transistor 59 is electrically connected to the gate of the transistor 60 and one electrode of the capacitor 66 . One of the source and the drain of the transistor 60 is electrically connected to one of the source and the drain of the transistor 61 , the gate of the transistor 62 , and the other electrode of the capacitor 66 .

A signal LIN is input to the gate of the transistor 51 and the gate of the transistor 55 . A signal CLK[3] is input to the gate of the transistor 53 . A signal RES is input to the gate of the transistor 54 . A signal CLK[1] is input to one of the source and drain of the transistor 57 . A signal PWC is input to the other of the source and drain of the transistor 60 .

One of the source and the drain of the transistor 62 and one of the source and the drain of the transistor 63 are electrically connected to the wiring 31, and the signal FO is output from the wiring 31 as described above. A signal SROUT is output from the other of the source or drain of the transistor 57 , one of the source or drain of the transistor 58 , and the other electrode of the capacitor 65 .

The other of the source or the drain of the transistor 51, the other of the source or the drain of the transistor 53, the other of the source or the drain of the transistor 54, the gate of the transistor 56, the gate of the transistor 59, and the other of the source or the drain of the transistor 62 has a potential. VDD is supplied. the other of the source or drain of the transistor 52, the other of the source or drain of the transistor 55, the other of the source or drain of the transistor 58, the other of the source or drain of the transistor 61, the other of the source or drain of the transistor 63, and the capacitor 64 A potential VSS is supplied to the other electrode.

In this specification and the like, the potential VDD can be, for example, a high potential, and the potential VSS can be, for example, a low potential.

The transistor 63 is a bias transistor and functions as a constant current source. A potential Vbias, which is a bias potential, can be supplied to the gate of the transistor 63 .

A source follower circuit 67 is configured by the transistor 62 and the transistor 63 . By providing the source follower circuit 67 in the shift register circuit SR, even if signal attenuation or the like occurs due to wiring resistance, parasitic capacitance, or the like inside the shift register circuit SR, the potential of the signal FO is reduced due to this. can be suppressed. Thereby, the operation of the display device 10 can be speeded up. The source follower circuit 67 may be a circuit other than the source follower circuit as long as it has a buffer function.

<Configuration example of area 23>
FIG. 18 is a diagram showing a configuration example of the region 23 where the gate driver circuit 21 and the source driver circuit 22 overlap. As shown in FIG. 18, in the region 23, a region having elements forming the gate driver circuit 21 and a region having elements forming the source driver circuit 22 are provided with a certain regularity. FIG. 18 shows a transistor 71 as an element forming the gate driver circuit 21 and a transistor 72 as an element forming the source driver circuit 22 .

In FIG. 18, regions having elements forming the gate driver circuit 21 are provided in the first and third rows, and regions having elements forming the source driver circuit 22 are provided in the second and fourth rows. is shown. In the region 23, dummy elements are provided between the regions having the elements forming the gate driver circuit 21. FIG. Dummy elements are provided between the regions having the elements forming the source driver circuit 22 . FIG. 18 shows a configuration example of the region 23 when dummy transistors 73 are provided as dummy elements on the four sides of the transistor 71 and on the four sides of the transistor 72 . Here, the area where the dummy elements are provided is assumed to be area 74 .

By providing a dummy element such as the dummy transistor 73 in the region 23, the dummy element absorbs the impurity and can suppress diffusion of the impurity to the transistor 71, the transistor 72, and the like. Accordingly, the reliability of the transistors 71 and 72 and the like can be improved, so that the reliability of the display device 10 can be improved. Note that although the transistors 71 and 72 and the dummy transistors 73 are arranged in a matrix in FIG. 18, they may not be arranged in a matrix.

FIG. 19 is a top view showing a configuration example of a region 70 that is part of the region 23. As shown in FIG. As shown in FIGS. 18 and 19, the region 70 is provided with one transistor 71, one transistor 72, and two dummy transistors 73. FIG. As shown in FIG. 19, the transistor 71 has a channel formation region 110, a source region 111, and a drain region 112. As shown in FIG. Further, a gate electrode 113 is provided so as to have a region overlapping with the channel formation region 110 .

Note that constituent elements such as a gate insulator are omitted in FIG. 19 and the like. Also, in FIG. 19 and the like, the channel formation region, the source region, and the drain region are not clearly separated.

An opening 114 is provided in the source region 111 , and the source region 111 is electrically connected to a wiring 115 through the opening 114 . An opening 116 is provided in the drain region 112 , and the drain region 112 is electrically connected to a wiring 117 through the opening 116 .

An opening 118 is provided in the gate electrode 113 , and the gate electrode 113 is electrically connected to the wiring 121 through the opening 118 . An opening 119 is provided in the wiring 115 , and the wiring 115 is electrically connected to the wiring 122 through the opening 119 . An opening 120 is provided in the wiring 117 , and the wiring 117 is electrically connected to the wiring 123 through the opening 120 . That is, the source region 111 is electrically connected to the wiring 122 through the wiring 115 , and the drain region 112 is electrically connected to the wiring 123 through the wiring 117 .

The transistor 72 has a channel formation region 130 , a source region 131 and a drain region 132 . Further, a gate electrode 133 is provided so as to have a region overlapping with the channel formation region 130 .

An opening 134 is provided in the source region 131 , and the source region 131 is electrically connected to a wiring 135 through the opening 134 . An opening 136 is provided in the drain region 132 , and the drain region 132 is electrically connected to a wiring 137 through the opening 136 .

An opening 138 is provided in the gate electrode 133 , and the gate electrode 133 is electrically connected to the wiring 141 through the opening 138 . An opening 139 is provided in the wiring 135 , and the wiring 135 is electrically connected to the wiring 142 through the opening 139 . An opening 140 is provided in the wiring 137 , and the wiring 137 is electrically connected to the wiring 143 through the opening 140 . That is, the source region 131 is electrically connected to the wiring 142 through the wiring 135 and the drain region 132 is electrically connected to the wiring 143 through the wiring 137 .

Note that the channel formation region 110 and the channel formation region 130 can be provided in the same layer. Further, the source region 111 and the drain region 112 and the source region 131 and the drain region 132 can be provided in the same layer. Further, the gate electrode 113 and the gate electrode 133 can be provided in the same layer. Further, the wirings 115 and 117 and the wirings 135 and 137 can be provided in the same layer. That is, the transistor 71 and the transistor 72 can be provided in the same layer. Accordingly, compared to the case where the transistor 71 and the transistor 72 are provided in different layers, the manufacturing process of the display device 10 can be simplified, and the cost of the display device 10 can be reduced.

Wirings 121 to 123 electrically connected to the transistor 71 included in the gate driver circuit 21 are provided in the same layer. Wirings 141 to 143 electrically connected to the transistor 72 included in the source driver circuit 22 are provided in the same layer. Further, the wirings 121 to 123 are provided in layers different from those of the wirings 141 to 143 . As described above, it is possible to suppress an electrical short circuit between the transistor 71 that is an element forming the gate driver circuit 21 and the transistor 72 that is an element forming the source driver circuit 22 . Therefore, even if the gate driver circuit 21 and the source driver circuit 22 are not clearly separated and have overlapping regions, malfunction of the gate driver circuit 21 and the source driver circuit 22 can be suppressed. Thereby, the reliability of the display device 10 can be improved.

In this specification and the like, "the same layer as A" means, for example, a layer formed in the same step as A and having the same material.

19 shows a structure in which the wirings 141 to 143 are provided above the wirings 121 to 123, the wirings 141 to 143 may be provided below the wirings 121 to 123. FIG.

19 illustrates a structure in which the wirings 121 to 123 extend in the horizontal direction and the wirings 141 to 143 extend in the vertical direction; however, one embodiment of the present invention is not limited to this. For example, the wirings 121 to 123 may be extended in the vertical direction, and the wirings 141 to 143 may be extended in the horizontal direction. Alternatively, both the wirings 121 to 123 and the wirings 141 to 143 may extend in the horizontal direction or in the vertical direction.

The dummy transistor 73 has a semiconductor 151 and a conductor 152 . The conductor 152 has a region that overlaps with the semiconductor 151 . The semiconductor 151 can be formed in the same layer as the channel formation regions of the transistors 71 and 72 . Further, the conductor 152 can be formed in the same layer as the gate electrodes of the transistors 71 and 72 . Note that the dummy transistor 73 may be configured without either the semiconductor 151 or the conductor 152 .

The semiconductor 151 and the conductor 152 can have a structure in which they are not electrically connected to other wirings or the like. A constant potential may be supplied to the semiconductor 151 and/or the conductor 152 . For example, ground potential may be supplied.

A buffer circuit 25 may be provided in the region 23 in addition to the gate driver circuit 21 and the source driver circuit 22 . For example, elements forming the buffer circuit 25 may be provided between regions having elements forming the gate driver circuit 21 . Also, an element forming the buffer circuit 25 may be provided between regions having elements forming the source driver circuit 22 . That is, the buffer circuit 25 may be provided in the region 74. FIG. For example, the buffer circuit 25 can be provided in the region 74 by replacing part or all of the dummy elements such as the dummy transistor 73 shown in FIG. For example, the buffer circuit 25[1,1] can be provided in the area 23[1,1], which is the area where the gate driver circuit 21[1,1] and the source driver circuit 22[1,1] overlap. .

FIG. 20 is a top view showing a configuration example of the region 70. Instead of the dummy transistor 73 shown in FIG. 19, transistors 81 and 82 included in the buffer circuit 25 having the configuration shown in FIG.

The transistor 81 has a channel formation region 160 , a source region 161 and a drain region 162 . Further, a gate electrode 163 is provided so as to have a region overlapping with the channel formation region 160 .

An opening 164 is provided in the source region 161 , and the source region 161 is electrically connected to a wiring 165 through the opening 164 . An opening 166 is provided in the drain region 162 , and the drain region 162 is electrically connected to a wiring 167 through the opening 166 .

An opening 168 is provided in the gate electrode 163 , and the gate electrode 163 is electrically connected to the wiring 171 through the opening 168 . An opening 170 is provided in the wiring 167 , and the wiring 167 is electrically connected to the wiring 171 through the opening 170 . That is, the gate electrode 163 and the drain region 162 are electrically connected through the wiring 171 and the wiring 167 .

An opening 169 is provided in the wiring 165 and the wiring 165 is electrically connected to the wiring 172 through the opening 169 . That is, the source region 161 is electrically connected to the wiring 172 through the wiring 165 .

The transistor 82 has a channel forming region 180 , a source region 181 and a drain region 182 . Further, a gate electrode 183 is provided so as to have a region overlapping with the channel formation region 180 .

An opening 184 is provided in the source region 181 , and the source region 181 is electrically connected to a wiring 185 through the opening 184 . An opening 186 is provided in the drain region 182 , and the drain region 182 is electrically connected to a wiring 187 through the opening 186 .

An opening 188 is provided in the gate electrode 183 , and the gate electrode 183 is electrically connected to the wiring 191 through the opening 188 . An opening 189 is provided in the wiring 185 , and the wiring 185 is electrically connected to the wiring 192 through the opening 189 . That is, the source region 181 is electrically connected to the wiring 192 through the wiring 185 .

An opening 190 is provided in the wiring 187 and the wiring 187 is electrically connected to the wiring 172 through the opening 190 . That is, the source region 161 of the transistor 81 and the drain region 182 of the transistor 82 are electrically connected through the wirings 165 , 172 , and 187 .

Note that the channel formation regions 160 and 180 can be provided in the same layer as the channel formation region 110 or the channel formation region 130 . In addition, the source region 161 and the drain region 162 and the source region 181 and the drain region 182 can be provided in the same layer as the source region 111 or the drain region 112 or the source region 131 or the drain region 132 .

Further, the gate electrode 163 and the gate electrode 183 can be provided in the same layer as the gate electrode 113 or the gate electrode 133 . Further, the wirings 165 and 167 and the wirings 185 and 187 can be provided in the same layer as the wiring 115 or 117 or the wiring 135 or 137 . That is, the transistors 71, 72, 81, and 82 can all be provided in the same layer. As a result, the manufacturing process of the display device 10 can be simplified, and the display device 10 can be made inexpensive.

A wiring 171, a wiring 172, a wiring 191, and a wiring 192 electrically connected to the transistor 81 and/or the transistor 82 included in the buffer circuit 25 can be provided in the same layer. FIG. 20 shows the case where the wirings 171 , 172 , 191 , and 192 are provided in the same layer as the wirings 121 to 123 . Note that the wirings 171 , 172 , 191 , and 192 may be provided in the same layer as the wirings 141 to 143 . Alternatively, the wirings 171 , 172 , 191 , and 192 may be provided in a layer different from that of the wirings 121 to 123 and the wirings 141 to 143 .

In addition, although the wiring 171, the wiring 172, the wiring 191, and the wiring 192 extend in the horizontal direction in FIG. 20, they do not necessarily extend in the horizontal direction.

By providing the elements constituting the buffer circuit 25 in the region 23 where the gate driver circuit 21 and the source driver circuit 22 overlap, the wiring distance between the buffer circuit 25 and the source driver circuit 22 can be shortened. can. Accordingly, it is possible to prevent the signal output from the buffer circuit 25 from attenuating before being input to the buffer circuit 43 . Therefore, the signal output from the buffer circuit 25 can be correctly recognized by the buffer circuit 43 and the like, and the reliability of the display device 10 can be improved.

Buffer element 28 shown in FIGS. 5, 6, and 10 may be provided in region 23. FIG. 5, 6, and 10 is provided in region 23 by replacing part or all of dummy transistor 73 with transistor 93, transistor 94, transistor 84, transistor 85, or transistor 86, for example. be able to.

<Configuration Example 3 of Display Device>
FIG. 21 is a block diagram showing a configuration example of the display device 10, which is a modification of the configuration shown in FIG. In the display device 10 configured as shown in FIG. 21, the source driver circuit 22 is connected to both ends of the wiring 32 . By connecting multiple points of the wiring 32 to the source driver circuit 22, it is possible to suppress signal delay and the like caused by wiring resistance, parasitic capacitance, and the like. Thereby, the operation of the display device 10 can be speeded up.

In addition to the one end and the other end of the wiring 32 , other portions of the wiring 32 may be connected to the source driver circuit 22 . For example, the central portion of the wiring 32 may be connected to the source driver circuit 22 . By increasing the number of connection points between the wiring 32 and the source driver circuit 22, signal delay and the like can be further suppressed, and the operation speed of the display device 10 can be further increased. For example, one end of the wiring 32 and the central portion of the wiring 32 may be connected to the source driver circuit 22 , and the other end of the wiring 32 may not be connected to the source driver circuit 22 .

Also, when one source driver circuit 22 is connected to a plurality of wirings 32, the area occupied by the source driver circuit 22 increases as shown in FIG. Even in this case, the source driver circuit 22 is laminated so as to have a region overlapping with the display portion 33, and the gate driver circuit 21 and the source driver circuit 22 are not clearly separated and have an overlapping region. Therefore, it is possible to prevent the display device 10 from increasing in size. Note that in FIG. 21, the entire gate driver circuit 21 overlaps with the source driver circuit 22 without being clearly separated. Alternatively, only a part of the gate driver circuit 21 may overlap with the source driver circuit 22 .

A plurality of wirings 31 may be connected to one gate driver circuit 21 . This also suppresses signal delay and the like, and speeds up the operation of the display device 10 . With such a configuration, the area occupied by the source driver circuit 22 becomes large as in the case of the source driver circuit 22 shown in FIG. However, since the gate driver circuit 21 is laminated so as to have an area overlapping with the display section 33, and the gate driver circuit 21 and the source driver circuit 22 are not clearly separated and have an overlapping area, An increase in size of the display device 10 can be suppressed.

FIG. 22 is a block diagram showing a configuration example of the display device 10, which is a modification of the configuration shown in FIG. In the display device 10 configured as shown in FIG. 22, the gate driver circuits 21 are provided in the same number as the columns of the display section 33 . In the display device 10 configured as shown in FIG. 22, since the display section 33 of three columns is provided, three gate driver circuits 21 are provided. Also, three rows of display portions 33 are provided, and the display portions 33 of three rows and one column share one gate driver circuit 21 .

FIG. 23 is a block diagram showing a configuration example of the display device 10, which is a modification of the configuration shown in FIG. In the display device 10 configured as shown in FIG. 23, one gate driver circuit 21 is provided. In the display device 10 configured as shown in FIG. 23, the display units 33 of 3 rows and 3 columns share one gate driver circuit 21 . In the display device 10 having the configuration shown in FIG. 23, the gate driver circuit 21 can be configured so as not to overlap the display section 33 .

Also, although not shown, the number of source driver circuits 22 may not be the same as that of the display section 33 , and may be more or less than the display section 33 .

<Example of pixel configuration>
FIGS. 24A to 24E are diagrams illustrating colors exhibited by the pixels 34 provided in the display device 10. FIG. As shown in FIG. 7A, a pixel 34 exhibiting red (R), a pixel 34 exhibiting green (G), and a pixel 34 exhibiting blue (B) can be provided in the display device of one embodiment of the present invention. can. Alternatively, as shown in FIG. 24B, the display device 10 may include a pixel 34 exhibiting cyan (C), a pixel 34 exhibiting magenta (M), and a pixel 34 exhibiting yellow (Y). .

Alternatively, as shown in FIG. 24C, a pixel 34 exhibiting red (R), a pixel 34 exhibiting green (G), a pixel 34 exhibiting blue (B), and a pixel 34 exhibiting white (W) are displayed. It may be provided in the device 10 . Alternatively, as shown in FIG. 24D, a pixel 34 exhibiting red (R), a pixel 34 exhibiting green (G), a pixel 34 exhibiting blue (B), and a pixel 34 exhibiting yellow (Y) are displayed. It may be provided in the device 10 . Alternatively, as shown in FIG. 24E, a pixel 34 exhibiting cyan (C), a pixel 34 exhibiting magenta (M), a pixel 34 exhibiting yellow (Y), and a pixel 34 exhibiting white (W) are displayed. It may be provided in the device 10 .

As shown in FIGS. 24C and 24E, by providing the display device 10 with the pixels 34 exhibiting white color, the brightness of the displayed image can be increased. In addition, as shown in FIG. 24D and the like, by increasing the number of types of colors exhibited by the pixels 34, the reproducibility of intermediate colors can be improved, so that the display quality can be improved.

25A and 25B are circuit diagrams showing configuration examples of the pixel 34. FIG. A pixel 34 having the structure shown in FIG. In addition to the wiring 31 and the wiring 32 , the wiring 35 and the like are electrically connected to the pixel 34 .

The potential of one electrode of the liquid crystal element 570 is appropriately set according to the specifications of the pixel 34 . The alignment state of the liquid crystal element 570 is set by an image signal written to the pixel 34 . Note that a common potential (common potential) may be supplied to one electrode of the liquid crystal element 570 included in each of the plurality of pixels 34 . Alternatively, different potentials may be supplied to one electrodes of the liquid crystal elements 570 of the pixels 34 in each row.

25B includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel 34 having the structure illustrated in FIG. As the light emitting element 572, for example, an EL element using electroluminescence can be applied. An EL element has a layer containing a light-emitting compound (hereinafter also referred to as an EL layer) between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting substance contained in the EL layer emits light.

Further, EL elements are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

In the organic EL element, when a voltage is applied, electrons are injected from one electrode and holes are injected from the other electrode into the EL layer. Then, recombination of these carriers (electrons and holes) causes the light-emitting organic compound to form an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

In addition to the light-emitting compound, the EL layer includes a substance with a high hole-injection property, a substance with a high hole-transport property, a hole-blocking material, a substance with a high electron-transport property, a substance with a high electron-injection property, or a bipolar compound. a substance having high electron-transport properties and high hole-transport properties, or the like.

The EL layer can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements according to the element structure. A dispersion-type inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. A thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and the light-emitting mechanism is localized light emission utilizing inner-shell electronic transition of metal ions.

At least one of the pair of electrodes of the light-emitting element should be transparent in order to emit light. Then, a transistor and a light emitting element are formed on a substrate, and a top emission structure in which light is emitted from the opposite side of the substrate, a bottom emission structure in which light is emitted from the substrate side, or a bottom emission structure. There is a light emitting device with a dual emission structure in which light is emitted from both sides, and any light emitting device with an emission structure can be applied.

Note that an element similar to the light emitting element 572 can be used for the light emitting element other than the light emitting element 572 as well.

One of the source and drain of the transistor 552 is electrically connected to the wiring 32 . The other of the source and drain of the transistor 552 is electrically connected to one electrode of the capacitor 562 and the gate of the transistor 554 . The other electrode of the capacitor 562 is electrically connected to the wiring 35a. A gate of the transistor 552 is electrically connected to the wiring 31 . One of the source and the drain of the transistor 554 is electrically connected to the wiring 35a. The other of the source and drain of the transistor 554 is electrically connected to one electrode of the light emitting element 572 . The other electrode of the light emitting element 572 is electrically connected to the wiring 35b. A low potential, for example, is supplied to the wiring 35a, and a high potential, for example, is supplied to the wiring 35b.

In the pixel 34 having the structure shown in FIG. 25B, the current flowing through the light-emitting element 572 is controlled according to the potential supplied to the gate of the transistor 554, so that the luminance of light emitted from the light-emitting element 572 is controlled. .

FIG. 25C shows a configuration different from the pixel 34 having the configuration shown in FIG. 25B. In the pixel 34 having the structure shown in FIG. 25C, one of the source and drain of the transistor 552 is electrically connected to the wiring 32 . The other of the source and drain of the transistor 552 is electrically connected to one electrode of the capacitor 562 and the gate of the transistor 554 . A gate of the transistor 552 is electrically connected to the wiring 31 . One of the source and the drain of the transistor 554 is electrically connected to the wiring 35a. The other of the source and drain of the transistor 554 is electrically connected to the other electrode of the capacitor 562 and one electrode of the light emitting element 572 . The other electrode of the light emitting element 572 is electrically connected to the wiring 35b. A high potential, for example, is supplied to the wiring 35a, and a low potential, for example, is supplied to the wiring 35b.

FIG. 26A shows a configuration example of the pixel 34, which is different from the pixel 34 having the configuration shown in FIGS. 25A to 25C in having a memory. A pixel 34 having a structure illustrated in FIG. 26A includes a transistor 511 , a transistor 513 , a capacitor 515 , and a circuit 401 . In addition, the pixel 34 is electrically connected to the wirings 31_1 and 31_2 as the wiring 31 functioning as a scan line, and is electrically connected to the wiring 32_1 and the wiring 32_2 as the wiring 32 functioning as the data line. there is

One of the source and the drain of the transistor 511 is electrically connected to the wiring 32_1. The other of the source and drain of the transistor 511 is electrically connected to one electrode of the capacitor 515 . A gate of the transistor 511 is electrically connected to the wiring 31_1. One of the source and the drain of the transistor 513 is electrically connected to the wiring 32_2. The other of the source and drain of the transistor 513 is electrically connected to the other electrode of the capacitor 515 and the circuit 401 . A gate of the transistor 513 is electrically connected to the wiring 31_2.

Circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, and typically light emitting elements such as organic light emitting elements and LED elements, liquid crystal elements, MEMS (Micro Electro Mechanical Systems) elements, and the like can be applied.

In this specification and the like, a voltage supplied to a display element such as a light-emitting element or a liquid crystal element means a potential applied to one electrode of the display element and a potential applied to the other electrode of the display element. , indicates the difference between

A node connecting the transistor 511 and the capacitor 515 is N1, and a node connecting the transistor 513 and the circuit 401 is N2.

By turning off the transistor 511, the pixel 34 can hold the potential of the node N1. By turning off the transistor 513, the potential of the node N2 can be held. Further, by turning off the transistor 513 and writing a predetermined potential to the node N1 through the transistor 511, capacitive coupling through the capacitor 515 changes the potential of the node N2 according to the change in the potential of the node N1. can be made

Here, OS transistors can be applied to the transistors 511 and 513 . The metal oxide can have a bandgap of 2 eV or more, or 2.5 eV or more. Therefore, the OS transistor has extremely low leakage current (off current) in a non-conducting state. Therefore, by using OS transistors as the transistors 511 and 513, the potentials of the nodes N1 and N2 can be held for a long time.

[One example of pixel operation method]
Next, an example of an operation method of the pixel 34 having the configuration shown in FIG. 26A will be described with reference to FIG. 26B. FIG. 26(B) is a timing chart relating to the operation of the pixel 34 having the configuration shown in FIG. 26(A). For ease of explanation, the effects of various resistances such as wiring resistance, parasitic capacitances of transistors and wirings, threshold voltages of transistors, and the like are not considered.

In the operation shown in FIG. 26B, one frame period is divided into a period T1 and a period T2. A period T1 is a period in which a potential is written to the node N2, and a period T2 is a period in which a potential is written to the node N1.

In the period T1, a potential for turning on the transistor is supplied to both the wiring 31_1 and the wiring 31_2. A potential _Vref which is a fixed potential is supplied to the wiring 32_1, and a potential _Vw is supplied to the wiring 32_2.

A potential V _ref is supplied from the wiring 32_1 through the transistor 511 to the node N1. Further, the potential _Vw is supplied from the wiring 32_2 through the transistor 513 to the node N2. Therefore, the capacitor 515 holds the potential difference V _w −V _ref .

Subsequently, in the period T2, a potential for turning on the transistor 511 is supplied to the wiring 31_1, and a potential for turning off the transistor 513 is supplied to the wiring 31_2. A potential V _data is supplied to the wiring 32_1, and a predetermined constant potential is supplied to the wiring 32_2. Note that the potential of the wiring 32_2 may be floating.

A potential V _data is supplied to the node N1 through the transistor 511 . At this time, due to capacitive coupling by the capacitor 515, the potential of the node N2 changes by the potential dV according to the potential _Vdata . That is, a potential obtained by adding the potential _Vw and the potential dV is input to the circuit 401 . Although dV is shown to be a positive value in FIG. 26B, it may be a negative value. That is, the potential V _data may be lower than the potential V _ref .

Here, the potential dV is roughly determined by the capacitance value of the capacitor 515 and the capacitance value of the circuit 401 . When the capacitance value of the capacitor 515 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is close to the potential difference V _data -V _ref .

In this way, the pixel 34 can generate a potential supplied to the circuit 401 including a display element by combining two types of data signals. be able to. Here, one of the two types of data signals can be the aforementioned image signal, and the other of the two types of data signals can be, for example, a correction signal. For example, after supplying the potential _Vw corresponding to the correction signal to the node N2 in the period T1, and then supplying the potential _Vdata corresponding to the image signal to the node N1 in the period T2, the image displayed on the display unit 33 is , the image signal may be corrected by a correction signal. Note that not only the image signal but also the correction signal and the like can be generated by the source driver circuit 22 included in the display device 10 .

In addition, the pixel 34 can generate a potential that exceeds the maximum potential that can be supplied to the wirings 32_1 and 32_2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Moreover, when a liquid crystal element is used, overdrive driving or the like can be performed. Accordingly, light with luminance higher than the luminance corresponding to the maximum potential that can be supplied to the wiring 32_1 or the wiring 32_2 can be emitted from the pixel 34 .

[Configuration example of circuit 401]
26C and 26D show a configuration example of the pixel 34 including a specific configuration example of the circuit 401. FIG. A circuit 401 provided in the pixel 34 having the structure shown in FIG. 26C includes a liquid crystal element 570 and a capacitor 517 .

One electrode of liquid crystal element 570 is electrically connected to node N2. The other electrode of the liquid crystal element 570 is electrically connected to the wiring 533 . One electrode of the capacitor 517 is electrically connected to the node N2. The other electrode of the capacitor 517 is electrically connected to the wiring 531 . The wiring 531 and the wiring 533 can be common wiring for, for example, all the pixels 34 provided in the display device 10 . In this case, potentials supplied to the wirings 531 and 533 are a common potential.

The capacitor 517 functions as a storage capacitor. Note that the capacitor 517 may be omitted.

The pixel 34 having the structure shown in FIG. 26C can supply one electrode of the liquid crystal element 570 with a potential higher than the potential that can be generated by the source driver circuit 22 or the like. Therefore, a high voltage can be supplied to the liquid crystal element 570 without requiring the source driver circuit 22 to have a high withstand voltage, and the display device 10 can be made inexpensive. Alternatively, while suppressing an increase in power consumption of the display device 10, high-speed display can be realized by overdrive driving, or a liquid crystal material with a high driving voltage can be applied. Further, by supplying a correction signal to the wiring 32_1 or the wiring 32_2, the image signal can be corrected according to the operating temperature, the deterioration state of the liquid crystal element 570, and the like.

A circuit 401 provided in the pixel 34 having the structure shown in FIG.

One of the source and drain of the transistor 521 is electrically connected to the wiring 537 . The other of the source and drain of the transistor 521 is electrically connected to one electrode of the light emitting element 572 . A gate of transistor 521 is electrically connected to node N2. One electrode of the capacitor 517 is electrically connected to the node N2. The other electrode of the capacitor 517 is electrically connected to the wiring 535 . The other electrode of the light emitting element 572 is electrically connected to the wiring 539 .

The wiring 535 can be a common wiring for, for example, all the pixels 34 provided in the display device 10 . In this case, the potential supplied to the wiring 535 is a common potential. A constant potential can be supplied to the wirings 537 and 539 . For example, the wiring 537 can be supplied with a high potential, and the wiring 539 can be supplied with a low potential, for example.

The transistor 521 has a function of controlling current supplied to the light emitting element 572 . The capacitor 517 functions as a storage capacitor. Capacitive element 517 may be omitted.

Note that although FIG. 26D shows a structure in which the anode side of the light-emitting element 572 is electrically connected to the transistor 521, the transistor 521 may be electrically connected to the cathode side. In this case, the value of the potential supplied to the wiring 537 and the value of the potential supplied to the wiring 537 can be changed as appropriate.

The pixel 34 having the structure shown in FIG. 26D can supply one electrode of the light emitting element 572 with a potential higher than the potential that can be generated by the source driver circuit 22 or the like. Therefore, a high potential can be supplied to the gate of the transistor 521 without requiring the source driver circuit 22 to have a high withstand voltage, and the display device 10 can be inexpensive. By supplying a high potential to the gate of the transistor 521, a large current can flow through the light-emitting element 572; therefore, HDR display or the like can be realized in the pixel 34 having the structure illustrated in FIG. Further, by supplying a correction signal to the wiring 32_1 or the wiring 32_2, variations in electrical characteristics of the transistor 521 and the light-emitting element 572 can be corrected.

Further, by supplying a high potential to the gate of the transistor 521, a high voltage can be supplied to the light emitting element 572. Specifically, for example, the potential of the wiring 537 can be increased. Therefore, when the light-emitting element 572 is an organic EL element, the light-emitting element can have a tandem structure, which will be described later. Thereby, the current efficiency and the external quantum efficiency of the light emitting element 572 can be improved. Therefore, a high-brightness image can be displayed on the display device 10 . Moreover, the power consumption of the display device 10 can be reduced.

Note that the circuits are not limited to the circuits illustrated in FIGS. For example, by adding one transistor and one capacitor to the structures shown in FIGS. 26C and 26D, the number of nodes capable of holding a potential can be increased to three. That is, the pixel 34 can be provided with one more node capable of holding a potential in addition to the nodes N1 and N2. Thereby, the potential of the node N2 can be made higher. Therefore, when the pixel 34 has the structure shown in FIG. 26C, a higher voltage can be supplied to the liquid crystal element 570 . Further, when the pixel 34 has the structure shown in FIG. 26D, a larger current can flow through the light emitting element 572.

27A to 27D are diagrams showing configuration examples of the circuit 401 in the case where the light-emitting element 572 is used as a display element. A circuit 401 having the structure shown in FIG. 27A includes a capacitor 517, a transistor 521, and a light-emitting element 572, similarly to the circuit 401 having the structure shown in FIG.

In the circuit 401 having the structure shown in FIG. 27A, the gate of the transistor 521 and one electrode of the capacitor 517 are electrically connected to the node N2. One of the source and drain of the transistor 521 is electrically connected to the wiring 537 . The other of the source and drain of the transistor 521 is electrically connected to the other electrode of the capacitor 517 . The other electrode of the capacitor 517 is electrically connected to one electrode of the light emitting element 572 . The other electrode of the light emitting element 572 is electrically connected to the wiring 539 .

A circuit 401 having the structure shown in FIG. 27B also includes a capacitor 517, a transistor 521, and a light-emitting element 572, similarly to the circuit 401 having the structure shown in FIG.

In the circuit 401 having the structure shown in FIG. 27B, the gate of the transistor 521 and one electrode of the capacitor 517 are electrically connected to the node N2. One electrode of the light emitting element 572 is electrically connected to the wiring 537 . The other electrode of the light emitting element 572 is electrically connected to one of the source and drain of the transistor 521 . The other of the source and drain of the transistor 521 is electrically connected to the other electrode of the capacitor 517 . The other electrode of the capacitor 517 is electrically connected to the wiring 539 .

FIG. 27C shows a configuration example of the circuit 401 in which a transistor 525 is added to the circuit 401 shown in FIG. 27A. One of the source and drain of the transistor 525 is electrically connected to the other of the source and drain of the transistor 521 and the other electrode of the capacitor 517 . The other of the source and drain of the transistor 525 is electrically connected to one electrode of the light emitting element 572 . A gate of the transistor 525 is electrically connected to the wiring 541 . A wiring 541 functions as a scan line that controls conduction of the transistor 525 .

In the pixel 34 having the circuit 401 having the configuration shown in FIG. 27C, even if the potential of the node N2 is higher than or equal to the threshold voltage of the transistor 521, current flows through the light-emitting element 572 unless the transistor 525 is turned on. do not have. Therefore, malfunction of the display device 10 can be suppressed.

FIG. 27D shows a configuration example of the circuit 401 in which a transistor 527 is added to the circuit 401 shown in FIG. 27C. One of the source and drain of the transistor 527 is electrically connected to the other of the source and drain of the transistor 521 . The other of the source and drain of the transistor 527 is electrically connected to the wiring 543 . A gate of the transistor 527 is electrically connected to the wiring 545 . A wiring 545 functions as a scan line that controls conduction of the transistor 527 .

The wiring 543 can be electrically connected to a source of a specific potential such as a reference potential. By supplying a specific potential from the wiring 543 to the other of the source and the drain of the transistor 521, writing of an image signal to the pixel 34 can be stabilized.

In addition, the wiring 543 can be electrically connected to the circuit 520 . The circuit 520 can have one or more of a source of the specific potential, a function of obtaining electrical characteristics of the transistor 521, and a function of generating a correction signal.

<Configuration Example 4 of Display Device>
FIG. 28 is a block diagram showing a configuration example of the display device 10 when the pixels 34 have the configurations shown in FIGS. 26(A), (C), and (D). The display device 10 having the configuration shown in FIG. 28 is provided with a demultiplexer circuit 24 in addition to the components of the display device 10 shown in FIG. A demultiplexer circuit 24 may be provided, for example, in layer 20, as shown in FIG. The number of demultiplexer circuits 24 can be the same as the number of columns of pixels 34 provided in the display section 33, for example.

The gate driver circuit 21 is electrically connected to the pixel 34 through the wiring 31_1. The gate driver circuit 21 is electrically connected to the pixel 34 through the wiring 31_2. The wiring 31_1 and the wiring 31_2 function as scan lines.

The source driver circuit 22 is electrically connected to the input terminals of the demultiplexer circuit 24 . A first output terminal of the demultiplexer circuit 24 is electrically connected to the pixel 34 via the wiring 32_1. A second output terminal of the demultiplexer circuit 24 is electrically connected to the pixel 34 via the wiring 32_2. The wiring 32_1 and the wiring 32_2 function as data lines.

Note that the source driver circuit 22 and the demultiplexer circuit 24 may be collectively called a source driver circuit. That is, the demultiplexer circuit 24 may be included in the source driver circuit 22 .

In the display device 10 configured as shown in FIG. 28, the source driver circuit 22 has a function of generating the image signal S1 and the image signal S2. The demultiplexer circuit 24 has a function of supplying the image signal S1 to the pixel 34 via the wiring 32_1, and a function of supplying the image signal S2 to the pixel 34 via the wiring 32_2. Here, if the display device 10 having _{the configuration} shown in FIG. 28 is operated by the method shown in FIG. It can be a potential corresponding to S2.

As shown in FIG. 26B, by supplying the potential _Vw to the node N2 and then supplying the potential _Vdata to the node N1, the potential of the node N2 becomes " _Vw +dV". Here, as described above, the potential dV is a potential corresponding to the potential V _data . Therefore, the image signal S1 can be added to the image signal S2. That is, the image signal S1 can be superimposed on the image signal S2.

The magnitudes of the potential V _data corresponding to the image signal S1 and the potential V _w corresponding to the image signal S2 are limited according to the withstand voltage of the source driver circuit 22 and the like. Therefore, by superimposing the image signal S1 and the image signal S2, an image corresponding to the image signal having a potential higher than the potential that the source driver circuit 22 can output can be displayed on the display section 33 . Thereby, a high-brightness image can be displayed on the display unit 33 . In particular, when the pixel 34 has the light-emitting element 572 as a display element, a high-brightness image can be displayed on the display portion 33 because a large amount of current can flow through the light-emitting element 572 . In addition, the dynamic range, which is the range of brightness of an image that can be displayed by the display unit 33, can be expanded.

The image corresponding to the image signal S1 and the image corresponding to the image signal S2 may be the same or different. When the image corresponding to the image signal S1 and the image corresponding to the image signal S2 are the same, the display unit 33 displays the luminance of the image corresponding to the image signal S1 and the luminance of the image corresponding to the image signal S2. Images with higher brightness can be displayed.

FIG. 29 shows a case where an image P1 corresponding to the image signal S1 is an image containing only characters, and an image P2 corresponding to the image signal S2 is an image containing both pictures and characters. In this case, by superimposing the image P1 and the image P2, the brightness of the characters can be increased, for example, the characters can be emphasized. Further, as shown _in FIG. 26B, after the potential _Vw is written to the node N2, the potential of the node N2 changes according to the potential _Vdata . When rewriting, the potential V _data of the image signal S1 must be written again. On the other hand, when the potential V _data is rewritten, the potential V _w needs to be rewritten as long as the charge written to the node N2 at time T1 in FIG. 26B is held without leaking from the transistor 513 or the like. do not have. Therefore, in the case shown in FIG. 29, the luminance of characters can be adjusted by adjusting the value of the potential V _data .

Here, as described above, when the potential _Vw corresponding to the image signal S2 is rewritten, the potential _Vdata corresponding to the image signal S1 must be rewritten. On the other hand, when rewriting the potential V _data , there is no need to rewrite the potential V _w . Therefore, it is preferable that the image P2 be an image with a lower rewriting frequency than the image P1. Note that the image P1 is not limited to an image containing only characters, and the image P2 is not limited to an image containing a picture and characters.

<Example of cross-sectional configuration of display device>
FIG. 30 is a cross-sectional view showing a configuration example of the display device 10. As shown in FIG. The display device 10 has a substrate 701 and a substrate 705 , and the substrates 701 and 705 are attached to each other with a sealing material 712 .

As the substrate 701, a single crystal semiconductor substrate such as a single crystal silicon substrate can be used. Note that a semiconductor substrate other than a single crystal semiconductor substrate may be used as the substrate 701 .

A transistor 441 and a transistor 601 are provided over the substrate 701 . The transistor 441 can be a transistor provided in the interface circuit 50 . The transistor 601 can be a transistor provided in the gate driver circuit 21 , a transistor provided in the source driver circuit 22 , or a transistor provided in the buffer circuit 25 . That is, the transistor 441 and the transistor 601 can be provided in the layer 20 illustrated in FIG. 1 and the like.

The transistor 441 includes a conductor 443 functioning as a gate electrode, an insulator 445 functioning as a gate insulator, and part of the substrate 701, and includes a semiconductor region 447 including a channel formation region and a source region. Or it has a low resistance region 449a functioning as one of the drain regions and a low resistance region 449b functioning as the other of the source or drain regions. Transistor 441 may be either p-channel or n-channel.

A transistor 441 is electrically isolated from other transistors by an element isolation layer 403 . FIG. 30 shows the case where the element isolation layer 403 electrically isolates the transistor 441 from the transistor 601 . The element isolation layer 403 can be formed using a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

Here, in the transistor 441 shown in FIG. 30, the semiconductor region 447 has a convex shape. In addition, a conductor 443 is provided to cover the side and top surfaces of the semiconductor region 447 with the insulator 445 interposed therebetween. Note that FIG. 30 does not show how the conductor 443 covers the side surface of the semiconductor region 447 . A material that adjusts the work function can be used for the conductor 443 .

A transistor in which a semiconductor region has a convex shape, such as the transistor 441, can be called a fin transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the projection may be provided in contact with the upper portion of the projection. In addition, although FIG. 30 shows a structure in which part of the substrate 701 is processed to form a convex portion, a semiconductor having a convex shape may be formed by processing an SOI substrate.

Note that the structure of the transistor 441 illustrated in FIG. 30 is an example, and is not limited to that structure, and an appropriate structure may be employed depending on the circuit structure, the operation method of the circuit, or the like. For example, transistor 441 may be a planar transistor.

The transistor 601 can have a structure similar to that of the transistor 441 .

In addition to the element isolation layer 403 and the transistors 441 and 601 , the insulators 405 , 407 , 409 , and 411 are provided over the substrate 701 . A conductor 451 is embedded in the insulator 405 , the insulator 407 , the insulator 409 , and the insulator 411 . Here, the height of the top surface of the conductor 451 and the height of the top surface of the insulator 411 can be made approximately the same.

An insulator 413 and an insulator 415 are provided over the conductor 451 and the insulator 411 . A conductor 457 is embedded in the insulator 413 and the insulator 415 . The conductor 457 can be provided in the same layer as the wirings 121 to 123 illustrated in FIGS. Here, the height of the top surface of the conductor 457 and the height of the top surface of the insulator 415 can be made approximately the same.

An insulator 417 and an insulator 419 are provided over the conductor 457 and the insulator 415 . A conductor 459 is embedded in the insulator 417 and the insulator 419 . The conductor 459 can be provided in the same layer as the wirings 141 to 143 shown in FIGS. Here, the height of the top surface of the conductor 459 and the height of the top surface of the insulator 419 can be made approximately the same.

An insulator 421 and an insulator 214 are provided over the conductor 459 and the insulator 419 . A conductor 453 is embedded in the insulator 421 and the insulator 214 . Here, the height of the top surface of the conductor 453 and the height of the top surface of the insulator 214 can be made approximately the same.

An insulator 216 is provided over the conductor 453 and the insulator 214 . A conductor 455 is embedded in the insulator 216 . Here, the height of the top surface of the conductor 455 and the height of the top surface of the insulator 216 can be made approximately the same.

An insulator 222 , an insulator 224 , an insulator 254 , an insulator 244 , an insulator 280 , an insulator 274 , and an insulator 281 are provided over the conductor 455 and the insulator 216 . The conductor 305 is embedded in the insulator 222 , the insulator 224 , the insulator 254 , the insulator 244 , the insulator 280 , the insulator 274 , and the insulator 281 . Here, the height of the upper surface of the conductor 305 and the height of the upper surface of the insulator 281 can be made approximately the same.

An insulator 361 is provided over the conductor 305 and the insulator 281 . A conductor 317 and a conductor 337 are embedded in the insulator 361 . Here, the height of the top surface of the conductor 337 and the height of the top surface of the insulator 361 can be made approximately the same.

An insulator 363 is provided over the conductor 337 and the insulator 361 . A conductor 347 , a conductor 353 , a conductor 355 , and a conductor 357 are embedded in the insulator 363 . Here, the height of the top surfaces of the conductors 353, 355, and 357 and the height of the top surface of the insulator 363 can be approximately the same.

A connection electrode 760 is provided over the conductor 353 , the conductor 355 , the conductor 357 , and the insulator 363 . An anisotropic conductor 780 is provided to be electrically connected to the connection electrode 760 , and an FPC (Flexible Printed Circuit) 716 is provided to be electrically connected to the anisotropic conductor 780 . Various signals and the like are supplied to the display device 10 from the outside of the display device 10 by the FPC 716 .

As shown in FIG. 30, low-resistance region 449b, which functions as the other of the source and drain regions of transistor 441, includes conductors 451, 457, 459, 453, 455, and 455. 305 , conductor 317 , conductor 337 , conductor 347 , conductor 353 , conductor 355 , conductor 357 , connection electrode 760 , and anisotropic conductor 780 are electrically connected to FPC 716 . . Here, FIG. 30 shows three conductors, a conductor 353, a conductor 355, and a conductor 357, as conductors having a function of electrically connecting the connection electrode 760 and the conductor 347. The mode is not limited to this. The number of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347 may be one, two, or four or more. By providing a plurality of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347, contact resistance can be reduced.

A transistor 750 is provided over the insulator 214 . The transistor 750 can be a transistor provided in the pixel 34 . That is, the transistor 750 can be provided in the layer 30 illustrated in FIG. 1 and the like. An OS transistor can be used as the transistor 750 . An OS transistor has a feature of extremely low off-state current. Therefore, since the holding time of an image signal or the like can be lengthened, the frequency of refresh operations can be reduced. Therefore, power consumption of the display device 10 can be reduced.

The conductors 301 a and 301 b are embedded in the insulators 254 , 244 , 280 , 274 , and 281 . The conductor 301 a is electrically connected to one of the source and drain of the transistor 750 , and the conductor 301 b is electrically connected to the other of the source and drain of the transistor 750 . Here, the height of the top surfaces of the conductors 301a and 301b and the height of the top surface of the insulator 281 can be made approximately the same.

Note that an OS transistor or the like may be provided between the layer provided with the transistors 441 and 601 and the like and the layer provided with the transistor 750 and the like. Further, an OS transistor or the like may be provided in a layer above the layer in which the transistor 750 and the like are provided.

A conductor 311 , a conductor 313 , a conductor 331 , a capacitor 790 , a conductor 333 , and a conductor 335 are embedded in the insulator 361 . The conductors 311 and 313 are electrically connected to the transistor 750 and function as wirings. The conductors 333 and 335 are electrically connected to the capacitor 790 . Here, the height of the top surfaces of the conductors 331, 333, and 335 and the height of the top surface of the insulator 361 can be approximately the same.

A conductor 341 , a conductor 343 , and a conductor 351 are embedded in the insulator 363 . Here, the height of the top surface of the conductor 351 and the height of the top surface of the insulator 363 can be made approximately the same.

Insulator 405, insulator 407, insulator 409, insulator 411, insulator 413, insulator 415, insulator 417, insulator 419, insulator 421, insulator 214, insulator 280, insulator 274, insulator 281, the insulator 361, and the insulator 363 function as interlayer films and may function as planarization films that cover the uneven shapes below them. For example, the top surface of the insulator 363 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like in order to improve planarity.

As shown in FIG. 30, the capacitive element 790 has a lower electrode 321 and an upper electrode 325 . An insulator 323 is provided between the lower electrode 321 and the upper electrode 325 . That is, the capacitor 790 has a stacked structure in which the insulator 323 functioning as a dielectric is sandwiched between a pair of electrodes. Note that although FIG. 30 shows an example in which the capacitor 790 is provided over the insulator 281 , the capacitor 790 may be provided over an insulator different from the insulator 281 .

FIG. 30 shows an example in which the conductor 301a, the conductor 301b, and the conductor 305 are formed in the same layer. Further, an example in which the conductor 311, the conductor 313, the conductor 317, and the lower electrode 321 are formed in the same layer is shown. Further, an example in which the conductor 331, the conductor 333, the conductor 335, and the conductor 337 are formed in the same layer is shown. Further, an example in which the conductor 341, the conductor 343, and the conductor 347 are formed in the same layer is shown. Furthermore, an example in which the conductor 351, the conductor 353, the conductor 355, and the conductor 357 are formed in the same layer is shown. By forming a plurality of conductors in the same layer in this way, the manufacturing process of the display device 10 can be simplified, so that the display device 10 can be made inexpensive. Note that they may be formed in different layers and may have different types of materials.

The display device 10 shown in FIG. 30 has a liquid crystal element 570 . The liquid crystal element 570 has a conductor 772, a conductor 774, and a liquid crystal layer 776 therebetween. A conductor 774 is provided on the substrate 705 side and functions as a common electrode. In addition, the conductor 772 is electrically connected to the other of the source and the drain of the transistor 750 through the conductors 351, 341, 331, 313, and 301b. A conductor 772 is formed over the insulator 363 and functions as a pixel electrode.

A material that transmits visible light or a material that reflects visible light can be used for the conductor 772 . As a light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like is preferably used. As the reflective material, for example, a material containing aluminum, silver, or the like may be used.

If a reflective material is used for the conductor 772, the display device 10 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductor 772 and a light-transmitting material is also used for the substrate 701 and the like, the display device 10 becomes a transmissive liquid crystal display device. When the display device 10 is a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, when the display device 10 is a transmissive liquid crystal display device, a pair of polarizing plates are provided so as to sandwich the liquid crystal element.

Moreover, although not shown in FIG. 30, an alignment film may be provided in contact with the liquid crystal layer 776 . Further, optical members (optical substrates) such as a polarizing member, a retardation member, and an antireflection member, and a light source such as a backlight and a sidelight can be appropriately provided.

A structure 778 is provided between the insulator 363 and the conductor 774 . A structural body 778 is a columnar spacer and has a function of controlling the distance (cell gap) between the substrate 701 and the substrate 705 . Note that a spherical spacer may be used as the structure 778 .

A light shielding layer 738, a colored layer 736, and an insulator 734 in contact with these layers are provided on the substrate 705 side. The light blocking layer 738 has a function of blocking light emitted from adjacent regions. Alternatively, the light shielding layer 738 has a function of blocking external light from reaching the transistor 750 and the like. Note that the colored layer 736 is provided so as to have a region overlapping with the liquid crystal element 570 .

The liquid crystal layer 776 includes thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), and ferroelectric liquid crystal. , an antiferroelectric liquid crystal, or the like can be used. In the case of adopting the horizontal electric field method, a liquid crystal exhibiting a blue phase without using an alignment film may be used.

Further, modes of the liquid crystal element include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, and ASM (Axially Symmetrically aligned Micro-cell) mode. mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, guest host mode, and the like can be used.

Alternatively, the liquid crystal layer 776 can be a scattering liquid crystal using a polymer dispersed liquid crystal, a polymer network liquid crystal, or the like. At this time, a structure in which black-and-white display is performed without providing the coloring layer 736 or a structure in which color display is performed using the coloring layer 736 may be employed.

Further, as a method for driving the liquid crystal element, a time-division display method (also referred to as a field sequential driving method) in which color display is performed based on a sequential additive color mixing method may be applied. In that case, a structure in which the colored layer 736 is not provided can be employed. When the time-division display method is used, it is not necessary to provide sub-pixels for each color of R (red), G (green), and B (blue). There are advantages such as being able to increase the degree.

Although the display device 10 having the structure illustrated in FIG. 30 uses a liquid crystal element as a display element, one embodiment of the present invention is not limited thereto. FIG. 31 is a modification of the display device 10 shown in FIG. 30, and differs from the display device 10 shown in FIG. 30 in that light-emitting elements are used as display elements.

The display device 10 shown in FIG. 31 has a light emitting element 572 . The light-emitting element 572 has a conductor 772 , an EL layer 786 , and a conductor 788 . The EL layer 786 has an organic compound or an inorganic compound such as quantum dots.

Materials that can be used for the organic compound include fluorescent materials, phosphorescent materials, and the like. Materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell quantum dot materials, core-type quantum dot materials, and the like.

An insulator 730 is provided over the insulator 363 in the display device 10 illustrated in FIG. Here, the insulator 730 can be configured to cover part of the conductor 772 . The light-emitting element 572 includes a light-transmitting conductor 788 and is a top-emission light-emitting element. Note that the light-emitting element 572 may have a bottom emission structure in which light is emitted to the conductor 772 side or a dual emission structure in which light is emitted to both the conductor 772 and the conductor 788 .

The light emitting element 572 can have a microcavity structure, which will be described in detail later. As a result, light of predetermined colors (for example, RGB) can be extracted without providing a colored layer, and the display device 10 can perform color display. Absorption of light by the colored layer can be suppressed by adopting a structure in which the colored layer is not provided. Thereby, the display device 10 can display a high-brightness image, and the power consumption of the display device 10 can be reduced. Note that even when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel row, that is, in the case where the EL layer 786 is formed by coloring separately, a structure in which a colored layer is not provided can be employed.

Note that the light-blocking layer 738 is provided so as to have a region overlapping with the insulator 730 . Also, the light shielding layer 738 is covered with an insulator 734 . A sealing layer 732 is filled between the light emitting element 572 and the insulator 734 .

In addition, structure 778 is provided between insulator 730 and EL layer 786 . Also, the structure 778 is provided between the insulator 730 and the insulator 734 .

FIG. 32 is a modification of the display device 10 shown in FIG. 31, and differs from the display device 10 shown in FIG. 31 in that a colored layer 736 is provided. By providing the colored layer 736, the color purity of light extracted from the light emitting element 572 can be increased. Thereby, a high-quality image can be displayed on the display device 10 . Further, for example, all the light-emitting elements 572 of the display device 10 can be light-emitting elements that emit white light. can do.

30 to 32 show a structure in which the transistor 441 and the transistor 601 are provided so that a channel formation region is formed inside the substrate 701, and an OS transistor is provided by stacking the transistor 441 and the transistor 601 over the transistor 441 and the transistor 601. FIG. However, one aspect of the present invention is not limited to this. 33 is a modified example of FIG. 30, FIG. 34 is a modified example of FIG. 31, and FIG. 35 is a modified example of FIG. 30 to 32 in that a transistor 750 is provided. That is, the display device 10 having the structure shown in FIGS. 33 to 35 is provided with stacked OS transistors.

An insulator 613 and an insulator 614 are provided over the substrate 701 , and the transistor 602 and the transistor 603 are provided over the insulator 614 . Note that a transistor or the like may be provided between the substrate 701 and the insulator 613 . For example, a transistor having structures similar to those of the transistor 441 and the transistor 601 illustrated in FIGS. 30 to 32 may be provided between the substrate 701 and the insulator 613 . An OS transistor or the like may be provided between the layer provided with the transistors 602 and 603 and the like and the layer provided with the transistor 750 and the like. Furthermore, an OS transistor or the like may be provided in a layer above the layer in which the transistor 750 and the like are provided.

Transistor 602 may be a transistor provided in interface circuit 50 . The transistor 603 can be a transistor provided in the gate driver circuit 21 , a transistor provided in the source driver circuit 22 , or a transistor provided in the buffer circuit 25 . That is, the transistors 602 and 603 can be provided in the layer 20 illustrated in FIG. 1 and the like.

The transistors 602 and 603 can be transistors with structures similar to that of the transistor 750 . Note that the transistors 602 and 603 may be OS transistors having structures different from that of the transistor 750 .

In addition to the transistor 602 and the transistor 603, the insulator 616, the insulator 622, the insulator 624, the insulator 654, the insulator 644, the insulator 680, the insulator 674, and the insulator 681 are provided over the insulator 614. . A conductor 461 is embedded in the insulator 654 , the insulator 644 , the insulator 680 , the insulator 674 , and the insulator 681 . Here, the height of the top surface of the conductor 461 and the height of the top surface of the insulator 681 can be made approximately the same.

An insulator 501 is provided over the conductor 461 and the insulator 681 . A conductor 463 is embedded in the insulator 501 . Here, the height of the top surface of the conductor 463 and the height of the top surface of the insulator 501 can be made approximately the same.

An insulator 503 is provided over the conductor 463 and the insulator 501 . A conductor 465 is embedded in the insulator 503 . Here, the height of the top surface of the conductor 465 and the height of the top surface of the insulator 503 can be made approximately the same.

An insulator 505 is provided over the conductor 465 and the insulator 503 . A conductor 467 is embedded in the insulator 505 . The conductor 467 can be provided in the same layer as the wirings 121 to 123 shown in FIGS. 19, 20, and the like. Here, the height of the top surface of the conductor 467 and the height of the top surface of the insulator 505 can be made approximately the same.

An insulator 507 is provided over the conductor 467 and the insulator 505 . A conductor 469 is embedded in the insulator 507 . Here, the height of the top surface of the conductor 469 and the height of the top surface of the insulator 507 can be made approximately the same.

An insulator 509 is provided over the conductor 469 and the insulator 507 . A conductor 471 is embedded in the insulator 509 . The conductor 471 can be provided in the same layer as the wirings 141 to 143 shown in FIGS. 19, 20, and the like. Here, the height of the top surface of the conductor 471 and the height of the top surface of the insulator 509 can be made approximately the same.

An insulator 421 and an insulator 214 are provided over the conductor 471 and the insulator 509 . A conductor 453 is embedded in the insulator 421 and the insulator 214 . Here, the height of the top surface of the conductor 453 and the height of the top surface of the insulator 214 can be made approximately the same.

33 to 35, one of the source and the drain of the transistor 602 is connected to the conductor 461, the conductor 463, the conductor 465, the conductor 467, the conductor 469, the conductor 471, the conductor 453, and the conductor. 455 , conductor 305 , conductor 317 , conductor 337 , conductor 347 , conductor 353 , conductor 355 , conductor 357 , connection electrode 760 , and anisotropic conductor 780 . It is connected.

The insulators 613, 614, 680, 674, 681, 501, 503, 505, 507, and 509 function as interlayer films. , may have a function as a planarizing film covering the uneven shape below each.

By using the structure shown in FIGS. 33 to 35 for the display device 10, all the transistors included in the display device 10 can be OS transistors while the frame size and size of the display device 10 are reduced. This eliminates the need to manufacture different types of transistors, so that the manufacturing cost of the display device 10 can be reduced, and the display device 10 can be made inexpensive.

<Configuration example of light-emitting element>
36A to 36E are diagrams showing structural examples of the light-emitting element 572. FIG. FIG. 36A shows a structure in which an EL layer 786 is sandwiched between conductors 772 and 788 (single structure). As described above, EL layer 786 includes a light-emitting material, for example, a light-emitting material that is an organic compound.

FIG. 36B shows a stacked structure of the EL layer 786. FIG. Here, in the light-emitting element 572 having the structure shown in FIG. 36B, the conductor 772 functions as an anode and the conductor 788 functions as a cathode.

The EL layer 786 has a structure in which a hole-injection layer 721 , a hole-transport layer 722 , a light-emitting layer 723 , an electron-transport layer 724 , and an electron-injection layer 725 are stacked in this order over the conductor 772 . Note that when the conductor 772 functions as a cathode and the conductor 788 functions as an anode, the stacking order is reversed.

The light-emitting layer 723 includes a light-emitting material or an appropriate combination of a plurality of materials, and can have a structure in which fluorescence or phosphorescence with a desired emission color can be obtained. Further, the light-emitting layer 723 may have a laminated structure with different emission colors. Note that in this case, different materials may be used for the light-emitting substances and other substances used in the stacked light-emitting layers.

In the light-emitting element 572, for example, the conductor 772 shown in FIG. Light emitted from the light-emitting layer 723 included in 786 can be resonated between both electrodes, and light emitted through the conductor 788 can be enhanced.

Note that when the conductor 772 of the light-emitting element 572 is a reflective electrode having a laminated structure of a reflective conductive material and a translucent conductive material (transparent conductive film), the film thickness of the transparent conductive film Optical adjustment can be performed by controlling Specifically, the distance between the electrodes of the conductor 772 and the conductor 788 is adjusted to about mλ/2 (where m is a natural number) with respect to the wavelength λ of light obtained from the light-emitting layer 723 . is preferred.

In order to amplify desired light (wavelength: λ) obtained from the light-emitting layer 723, an optical distance from the conductor 772 to a region (light-emitting region) of the light-emitting layer where desired light is obtained and It is preferable to adjust the optical distance to a region (light-emitting region) of the light-emitting layer 723 from which desired light is obtained and to be near (2m′+1)λ/4 (where m′ is a natural number). Note that the light-emitting region here means a recombination region of holes and electrons in the light-emitting layer 723 .

By performing such optical adjustment, the spectrum of specific monochromatic light obtained from the light-emitting layer 723 can be narrowed, and light emission with good color purity can be obtained.

However, in the above case, the optical distance between the conductors 772 and 788 can be strictly defined as the total thickness from the reflective area of the conductor 772 to the reflective area of the conductor 788 . However, since it is difficult to strictly determine the reflection areas of the conductors 772 and 788, the above effect can be sufficiently obtained by assuming arbitrary positions of the conductors 772 and 788 as reflection areas. It shall be possible. Strictly speaking, the optical distance between the conductor 772 and the light-emitting layer from which desired light is obtained is the optical distance between the reflection region of the conductor 772 and the light-emitting region of the light-emitting layer from which desired light is obtained. be able to. However, it is difficult to strictly determine the reflective region of the conductor 772 and the light-emitting region of the light-emitting layer from which desired light is obtained. By assuming that an arbitrary position of the light-emitting layer is the light-emitting region, it is assumed that the above effects can be sufficiently obtained.

Since the light-emitting element 572 shown in FIG. 36B has a microcavity structure, light of different wavelengths (monochromatic light) can be extracted from the same EL layer. Therefore, separate coloring (for example, RGB) for obtaining different emission colors is unnecessary. Therefore, it is easy to achieve high definition. A combination with a colored layer is also possible. Furthermore, since it is possible to increase the emission intensity of the specific wavelength in the front direction, it is possible to reduce power consumption.

Note that the light-emitting element 572 shown in FIG. 36B may not have a microcavity structure. In this case, the light-emitting layer 723 has a structure that emits white light, and by providing a colored layer, light of predetermined colors (eg, RGB) can be extracted. Further, when the EL layer 786 is formed, if different colors are applied to obtain different emission colors, light of a predetermined color can be extracted without providing a colored layer.

At least one of the conductor 772 and the conductor 788 can be a light-transmitting electrode (a transparent electrode, a semi-transmissive/semi-reflective electrode, or the like). When the light-transmitting electrode is a transparent electrode, the visible light transmittance of the transparent electrode is set to 40% or more. In the case of the semi-transmissive/semi-reflective electrode, the visible light reflectance of the semi-transmissive/semi-reflective electrode should be 20% or more and 80% or less, preferably 40% or more and 70% or less. Moreover, the resistivity of these electrodes is preferably 1×10 ⁻² Ωcm or less.

When the conductor 772 or the conductor 788 is a reflective electrode (reflective electrode), the visible light reflectance of the reflective electrode is 40% to 100%, preferably 70% to 100%. and Moreover, the resistivity of this electrode is preferably 1×10 ⁻² Ωcm or less.

The structure of the light-emitting element 572 may be the structure shown in FIG. In FIG. 36C, two EL layers (an EL layer 786a and an EL layer 786b) are provided between the conductor 772 and the conductor 788, and charge is generated between the EL layer 786a and the EL layer 786b. A light-emitting element 572 having a stacked structure (tandem structure) with a layer 792 is shown. When the light-emitting element 572 has a tandem structure, current efficiency and external quantum efficiency of the light-emitting element 572 can be increased. Therefore, a high-brightness image can be displayed on the display device 10 . Moreover, the power consumption of the display device 10 can be reduced. Here, the EL layers 786a and 786b can have a structure similar to that of the EL layer 786 shown in FIG.

The charge generation layer 792 injects electrons into one of the EL layer 786a and the EL layer 786b and injects holes into the other when a voltage is applied between the conductor 772 and the conductor 788. It has the function to Therefore, when a voltage is supplied so that the potential of the conductor 772 is higher than the potential of the conductor 788, electrons are injected from the charge generation layer 792 into the EL layer 786a and holes are injected from the charge generation layer 792 into the EL layer 786b. will be

From the viewpoint of light extraction efficiency, the charge generation layer 792 preferably transmits visible light (specifically, the charge generation layer 792 has a visible light transmittance of 40% or more). Also, the conductivity of charge generating layer 792 may be less than the conductivity of conductor 772 or the conductivity of conductor 788 .

The structure of the light-emitting element 572 may be the structure shown in FIG. In FIG. 36D, three EL layers (an EL layer 786a, an EL layer 786b, and an EL layer 786c) are provided between the conductor 772 and the conductor 788, and the EL layer 786a and the EL layer 786b are provided. A tandem structure light-emitting element 572 having a charge generation layer 792 between and between EL layers 786b and 786c is shown. Here, the EL layer 786a, the EL layer 786b, and the EL layer 786c can have a structure similar to that of the EL layer 786 shown in FIG. By configuring the light-emitting element 572 as shown in FIG. 36D, the current efficiency and the external quantum efficiency of the light-emitting element 572 can be further increased. Therefore, an image with higher brightness can be displayed on the display device 10 . Moreover, the power consumption of the display device 10 can be further reduced.

The structure of the light emitting element 572 may be the structure shown in FIG. In FIG. 36E, n EL layers (EL layers 786 ( 1 ) to 786 ( n )) are provided between the conductor 772 and the conductor 788 . shows a tandem-structured light-emitting element 572 having a charge generation layer 792 . Here, the EL layers 786(1) to 786(n) can have a structure similar to that of the EL layer 786 shown in FIG. Note that of the EL layers 786, an EL layer 786(1), an EL layer 786(m), and an EL layer 786(n) are shown in FIG. Here, m is an integer of 2 or more and less than n, and n is an integer of m or more. As the value of n increases, the current efficiency and external quantum efficiency of the light emitting element 572 can be increased. Therefore, a high-brightness image can be displayed on the display device 10 . Moreover, the power consumption of the display device 10 can be reduced.

<Constituent Material of Light Emitting Element>
Next, constituent materials that can be used for the light-emitting element 572 are described.

<<Conductor 772 and Conductor 788>>
For the conductors 772 and 788, the following materials can be used in combination as appropriate as long as they can function as an anode and a cathode. For example, metals, alloys, electrically conductive compounds, mixtures thereof, and the like can be used as appropriate. Specifically, In--Sn oxide (also referred to as ITO), In--Si--Sn oxide (also referred to as ITSO), In--Zn oxide, and In--W--Zn oxide are given. In addition, aluminum (Al), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), gallium (Ga), zinc (Zn ), indium (In), tin (Sn), molybdenum (Mo), tantalum (Ta), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), silver (Ag), yttrium (Y ), neodymium (Nd), and alloys containing appropriate combinations thereof can also be used. In addition, elements belonging to Group 1 or Group 2 of the periodic table of elements not exemplified above (e.g., lithium (Li), cesium (Cs), calcium (Ca), strontium (Sr)), europium (Eu), ytterbium A rare earth metal such as (Yb), an alloy containing an appropriate combination thereof, graphene, and the like can be used.

<<Hole Injection Layer 721 and Hole Transport Layer 722>>
The hole-injection layer 721 is a layer that injects holes from the conductor 772 or the charge generation layer 792, which is an anode, into the EL layer 786, and contains a material with a high hole-injection property. Here, the EL layer 786 includes an EL layer 786a, an EL layer 786b, an EL layer 786c, and EL layers 786(1) to 786(n).

Materials with high hole injection properties include transition metal oxides such as molybdenum oxide, vanadium oxide, ruthenium oxide, tungsten oxide, and manganese oxide. In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (abbreviation: CuPC), 4,4′-bis[N-(4-diphenylaminophenyl)-N-phenylamino]biphenyl ( Abbreviations: DPAB), N,N'-bis{4-[bis(3-methylphenyl)amino]phenyl}-N,N'-diphenyl-(1,1'-biphenyl)-4,4'-diamine ( An aromatic amine compound such as DNTPD) or a polymer such as poly(3,4-ethylenedioxythiophene)/poly(styrenesulfonic acid) (abbreviation: PEDOT/PSS) can be used.

A composite material containing a hole-transporting material and an acceptor material (electron-accepting material) can also be used as a material having a high hole-injecting property. In this case, electrons are extracted from the hole-transporting material by the acceptor material, holes are generated in the hole-injection layer 721 , and holes are injected into the light-emitting layer 723 via the hole-transporting layer 722 . The hole injection layer 721 may be formed of a single layer made of a composite material containing a hole-transporting material and an acceptor material (electron-accepting material). (electron-accepting material) may be laminated in separate layers.

The hole-transporting layer 722 is a layer that transports holes injected from the conductor 772 by the hole-injecting layer 721 to the light-emitting layer 723 . Note that the hole-transport layer 722 is a layer containing a hole-transport material. A hole-transporting material used for the hole-transporting layer 722 preferably has a HOMO level that is the same as or close to the HOMO level of the hole-injecting layer 721 .

As an acceptor material used for the hole-injection layer 721, oxides of metals belonging to groups 4 to 8 in the periodic table can be used. Specific examples include molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide. Among them, molybdenum oxide is particularly preferred because it is stable even in the atmosphere, has low hygroscopicity, and is easy to handle. In addition, organic acceptors such as quinodimethane derivatives, chloranil derivatives, and hexaazatriphenylene derivatives can be used. Specifically, 7,7,8,8-tetracyano-2,3,5,6-tetrafluoroquinodimethane (abbreviation: F ₄ -TCNQ), chloranil, 2,3,6,7,10,11 -Hexacyano-1,4,5,8,9,12-hexaazatriphenylene (abbreviation: HAT-CN) and the like can be used.

As a hole-transporting material used for the hole-injection layer 721 and the hole-transporting layer 722, a substance having a hole mobility of 10 ⁻⁶ cm ² /Vs or more is preferable. Note that any substance other than these can be used as long as it has a higher hole-transport property than electron-transport property.

As the hole-transporting material, π-electron-rich heteroaromatic compounds (eg, carbazole derivatives and indole derivatives) and aromatic amine compounds are preferred. Specific examples include 4,4′-bis[N-(1-naphthyl )-N-phenylamino]biphenyl (abbreviation: NPB or α-NPD), N,N′-bis(3-methylphenyl)-N,N′-diphenyl-[1,1′-biphenyl]-4,4 '-diamine (abbreviation: TPD), 4,4'-bis[N-(spiro-9,9'-bifluoren-2-yl)-N-phenylamino]biphenyl (abbreviation: BSPB), 4-phenyl-4 '-(9-phenylfluoren-9-yl)triphenylamine (abbreviation: BPAFLP), 4-phenyl-3'-(9-phenylfluoren-9-yl)triphenylamine (abbreviation: mBPAFLP), 4-phenyl -4'-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBA1BP), 3-[4-(9-phenanthryl)-phenyl]-9-phenyl-9H-carbazole (abbreviation: PCPPn), N-(4-biphenyl)-N-(9,9-dimethyl-9H-fluoren-2-yl)-9-phenyl-9H-carbazol-3-amine (abbreviation: PCBiF), N-(1 ,1′-biphenyl-4-yl)-N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]-9,9-dimethyl-9H-fluorene-2-amine (abbreviation: PCBBiF) , 4,4′-diphenyl-4″-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBBi1BP), 4-(1-naphthyl)-4′-(9-phenyl- 9H-carbazol-3-yl)triphenylamine (abbreviation: PCBANB), 4,4′-di(1-naphthyl)-4″-(9-phenyl-9H-carbazol-3-yl)triphenylamine ( Abbreviation: PCBNBB), 9,9-dimethyl-N-phenyl-N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]fluoren-2-amine (abbreviation: PCBAF), N-phenyl- N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]spiro-9,9′-bifluoren-2-amine (abbreviation: PCBASF), 4,4′,4″-tris(carbazole -9-yl)triphenylamine (abbreviation: TCTA), 4,4′,4″-tris(N,N-diphenylamino)triphenylamine (abbreviation: TDATA), 4,4′,4″- Compounds having an aromatic amine skeleton such as tris[N-(3-methylphenyl)-N-phenylamino]triphenylamine (abbreviation: MTDATA), 1,3-bis(N-carbazolyl)benzene (abbreviation: mCP) , 4,4′-di(N-carbazolyl)biphenyl (abbreviation: CBP), 3,6-bis(3,5-diphenylphenyl)-9-phenylcarbazole (abbreviation: CzTP), 3,3′-bis( 9-phenyl-9H-carbazole) (abbreviation: PCCP), 3-[N-(9-phenylcarbazol-3-yl)-N-phenylamino]-9-phenylcarbazole (abbreviation: PCzPCA1), 3,6- Bis[N-(9-phenylcarbazol-3-yl)-N-phenylamino]-9-phenylcarbazole (abbreviation: PCzPCA2), 3-[N-(1-naphthyl)-N-(9-phenylcarbazole- 3-yl)amino]-9-phenylcarbazole (abbreviation: PCzPCN1), 1,3,5-tris[4-(N-carbazolyl)phenyl]benzene (abbreviation: TCPB), 9-[4-(10-phenyl -9-anthracenyl)phenyl]-9H-carbazole (abbreviation: CzPA) and other compounds having a carbazole skeleton, 4,4′,4″-(benzene-1,3,5-triyl)tri(dibenzothiophene) ( Abbreviations: DBT3P-II), 2,8-diphenyl-4-[4-(9-phenyl-9H-fluoren-9-yl)phenyl]dibenzothiophene (abbreviations: DBTFLP-III), 4-[4-(9 -Phenyl-9H-fluoren-9-yl)phenyl]-6-phenyldibenzothiophene (abbreviation: DBTFLP-IV) and other compounds having a thiophene skeleton, 4,4′,4″-(benzene-1,3, 5-triyl)tri(dibenzofuran) (abbreviation: DBF3P-II), 4-{3-[3-(9-phenyl-9H-fluoren-9-yl)phenyl]phenyl}dibenzofuran (abbreviation: mmDBFFLBi-II), etc. and a compound having a furan skeleton.

Furthermore, poly(N-vinylcarbazole) (abbreviation: PVK), poly(4-vinyltriphenylamine) (abbreviation: PVTPA), poly[N-(4-{N'-[4-(4-diphenylamino) phenyl]phenyl-N'-phenylamino}phenyl)methacrylamide] (abbreviation: PTPDMA), poly[N,N'-bis(4-butylphenyl)-N,N'-bis(phenyl)benzidine] (abbreviation: Polymer compounds such as Poly-TPD) can also be used.

However, the hole-transporting material is not limited to the above, and one or a combination of various known materials can be used as the hole-transporting material for the hole-injection layer 721 and the hole-transporting layer 722. . Note that each of the hole transport layers 722 may be formed from a plurality of layers. That is, for example, a first hole transport layer and a second hole transport layer may be laminated.

<<light-emitting layer 723>>
The light-emitting layer 723 is a layer containing a light-emitting substance. Note that as the light-emitting substance, a substance that emits light of blue, purple, blue-violet, green, yellow-green, yellow, orange, red, or the like is used as appropriate. Here, as shown in FIGS. 36C, 36D, and 36E, when the light-emitting element 572 has a plurality of EL layers, different light-emitting substances are used for the light-emitting layers 723 provided in the respective EL layers. Therefore, it is possible to provide a configuration that exhibits different emission colors (for example, white emission obtained by combining emission colors that are complementary to each other). For example, when the light-emitting element 572 has the structure shown in FIG. 36C, a light-emitting substance used for the light-emitting layer 723 provided in the EL layer 786a, , the emission color of the EL layer 786a can be made different from the emission color of the EL layer 786b. Note that a laminated structure in which one light-emitting layer contains different light-emitting substances may be used.

In addition to the light-emitting substance (guest material), the light-emitting layer 723 may contain one or more organic compounds (host material, assist material). Also, one or both of a hole-transporting material and an electron-transporting material can be used as the one or more organic compounds.

A light-emitting substance that can be used for the light-emitting layer 723 is not particularly limited, and a light-emitting substance that converts singlet excitation energy into light emission in the visible light region or a light-emitting substance that converts triplet excitation energy into light emission in the visible light region is used. be able to. Examples of the light-emitting substance include the following.

Examples of light-emitting substances that convert singlet excitation energy into light emission include substances that emit fluorescence (fluorescent materials). quinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, naphthalene derivatives and the like. Pyrene derivatives are particularly preferred because they have a high emission quantum yield. Specific examples of pyrene derivatives include N,N'-bis(3-methylphenyl)-N,N'-bis[3-(9-phenyl-9H-fluoren-9-yl)phenyl]pyrene-1,6 -diamine (abbreviation: 1,6mMemFLPAPrn), N,N'-diphenyl-N,N'-bis[4-(9-phenyl-9H-fluoren-9-yl)phenyl]pyrene-1,6-diamine (abbreviation: : 1,6FLPAPrn), N,N'-bis(dibenzofuran-2-yl)-N,N'-diphenylpyrene-1,6-diamine (abbreviation: 1,6FrAPrn), N,N'-bis(dibenzothiophene -2-yl)-N,N'-diphenylpyrene-1,6-diamine (abbreviation: 1,6ThAPrn), N,N'-(pyrene-1,6-diyl)bis[(N-phenylbenzo[b ] naphtho[1,2-d]furan)-6-amine] (abbreviation: 1,6BnfAPrn), N,N′-(pyrene-1,6-diyl)bis[(N-phenylbenzo[b]naphtho[ 1,2-d]furan)-8-amine] (abbreviation: 1,6BnfAPrn-02), N,N′-(pyrene-1,6-diyl)bis[(6,N-diphenylbenzo[b]naphtho [1,2-d]furan)-8-amine] (abbreviation: 1,6BnfAPrn-03) and the like. Pyrene derivatives are also a group of compounds useful for achieving blue chromaticity in one embodiment of the present invention.

In addition, 5,6-bis[4-(10-phenyl-9-anthryl)phenyl]-2,2'-bipyridine (abbreviation: PAP2BPy), 5,6-bis[4'-(10-phenyl- 9-anthryl)biphenyl-4-yl]-2,2'-bipyridine (abbreviation: PAPP2BPy), N,N'-bis[4-(9H-carbazol-9-yl)phenyl]-N,N'-diphenyl Stilbene-4,4'-diamine (abbreviation: YGA2S), 4-(9H-carbazol-9-yl)-4'-(10-phenyl-9-anthryl)triphenylamine (abbreviation: YGAPA), 4-( 9H-carbazol-9-yl)-4′-(9,10-diphenyl-2-anthryl)triphenylamine (abbreviation: 2YGAPPA), N,9-diphenyl-N-[4-(10-phenyl-9- anthryl)phenyl]-9H-carbazol-3-amine (abbreviation: PCAPA), 4-(10-phenyl-9-anthryl)-4′-(9-phenyl-9H-carbazol-3-yl)triphenylamine ( abbreviation: PCBAPA), 4-[4-(10-phenyl-9-anthryl)phenyl]-4′-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBAPBA), perylene, 2 ,5,8,11-tetra(tert-butyl)perylene (abbreviation: TBP), N,N''-(2-tert-butylanthracene-9,10-diyldi-4,1-phenylene)bis[N, N',N'-triphenyl-1,4-phenylenediamine] (abbreviation: DPABPA), N,9-diphenyl-N-[4-(9,10-diphenyl-2-anthryl)phenyl]-9H-carbazole -3-amine (abbreviation: 2PCAPPA), N-[4-(9,10-diphenyl-2-anthryl)phenyl]-N,N',N'-triphenyl-1,4-phenylenediamine (abbreviation: 2DPAPPA) ) etc. can be used.

Examples of light-emitting substances that convert triplet excitation energy into light emission include substances that emit phosphorescence (phosphorescent materials) and thermally activated delayed fluorescence (TADF) materials that exhibit thermally activated delayed fluorescence. .

Phosphorescent materials include organic metal complexes, metal complexes (platinum complexes), rare earth metal complexes, and the like. Since these exhibit different emission colors (emission peaks) depending on the substance, they are appropriately selected and used as necessary.

Examples of phosphorescent materials that exhibit blue or green color and have an emission spectrum with a peak wavelength of 450 nm or more and 570 nm or less include the following substances.

For example, tris{2-[5-(2-methylphenyl)-4-(2,6-dimethylphenyl)-4H-1,2,4-triazol-3-yl-κN2]phenyl-κC}iridium (III ) (abbreviation: [Ir(mpptz-dmp) ₃ ]), tris(5-methyl-3,4-diphenyl-4H-1,2,4-triazolato)iridium (III) (abbreviation: [Ir(Mptz) ₃ ]), tris[4-(3-biphenyl)-5-isopropyl-3-phenyl-4H-1,2,4-triazolato]iridium (III) (abbreviation: [Ir(iPrptz-3b) ₃ ]), tris 4H-triazole skeletons such as [3-(5-biphenyl)-5-isopropyl-4-phenyl-4H-1,2,4-triazolato]iridium(III) (abbreviation: [Ir(iPr5btz) ₃ ]), tris[3-methyl-1-(2-methylphenyl)-5-phenyl-1H-1,2,4-triazolato]iridium(III) (abbreviation: [Ir(Mptz1-mp) ₃ ]), 1H-triazoles such as tris(1-methyl-5-phenyl-3-propyl-1H-1,2,4-triazolato)iridium(III) (abbreviation: [Ir(Prptz1-Me) ₃ ]) organometallic complex having a skeleton, fac-tris[1-(2,6-diisopropylphenyl)-2-phenyl-1H-imidazole]iridium (III) (abbreviation: [Ir(iPrpmi) ₃ ]), tris[3- (2,6-dimethylphenyl)-7-methylimidazo[1,2-f]phenanthridinato]iridium (III) (abbreviation: [Ir(dmpimpt-Me) ₃ ]) having an imidazole skeleton metal complex, bis[2-(4′,6′-difluorophenyl)pyridinato-N,C ^2′ ]iridium(III) tetrakis(1-pyrazolyl)borate (abbreviation: FIr6), bis[2-(4′, 6′-difluorophenyl)pyridinato-N,C ^2′ ]iridium (III) picolinate (abbreviation: FIrpic), bis[2-(3,5-bistrifluoromethylphenyl)pyridinato-N,C ^2′ ]iridium (III ) picolinate (abbreviation: [Ir(CF ₃ ppy) ₂ (pic)]), bis[2-(4′,6′-difluorophenyl)pyridinato-N,C ^2′ ]iridium (III) acetylacetonate (abbreviation : FIr(acac)), and organometallic complexes in which a phenylpyridine derivative having an electron withdrawing group is used as a ligand.

Examples of phosphorescent materials that exhibit green or yellow color and have an emission spectrum with a peak wavelength of 495 nm or more and 590 nm or less include the following substances.

For example, tris(4-methyl-6-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(mpm) ₃ ]), tris(4-t-butyl-6-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(tBuppm) ₃ ]), (acetylacetonato)bis(6-methyl-4-phenylpyrimidinato)iridium (III) (abbreviation: [Ir(mppm) ₂ (acac)]), ( acetylacetonato)bis(6-tert-butyl-4-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(tBuppm) ₂ (acac)]), (acetylacetonato)bis[6-(2- norbornyl)-4-phenylpyrimidinato]iridium (III) (abbreviation: [Ir(nbppm) ₂ (acac)]), (acetylacetonato)bis[5-methyl-6-(2-methylphenyl)-4 -phenylpyrimidinato]iridium(III) (abbreviation: [Ir(mpmpm) ₂ (acac)]), (acetylacetonato)bis{4,6-dimethyl-2-[6-(2,6-dimethylphenyl )-4-pyrimidinyl-κN]phenyl-κC}iridium (III) (abbreviation: [Ir(dmpm-dmp) ₂ (acac)]), (acetylacetonato)bis(4,6-diphenylpyrimidinato)iridium (III) Organometallic iridium complexes having a pyrimidine skeleton such as (abbreviation: [Ir(dppm) ₂ (acac)]), (acetylacetonato)bis(3,5-dimethyl-2-phenylpyrazinato)iridium (III) (abbreviation: [Ir(mppr-Me) ₂ (acac)]), (acetylacetonato)bis(5-isopropyl-3-methyl-2-phenylpyrazinato)iridium (III) (abbreviation: [ Organometallic iridium complexes having a pyrazine skeleton such as Ir(mppr-iPr) ₂ (acac)]), tris(2-phenylpyridinato-N,C ^2′ ) iridium (III) (abbreviation: [Ir(ppy ) ₃ ]), bis(2-phenylpyridinato-N,C ^2′ )iridium(III) acetylacetonate (abbreviation: [Ir(ppy) ₂ (acac)]), bis(benzo[h]quinolinato) iridium (III) acetylacetonate (abbreviation: [Ir(bzq) ₂ (acac)]), tris(benzo[h]quinolinato)iridium (III) (abbreviation: [Ir(bzq) ₃ ]), tris(2- phenylquinolinato-N,C ^2′ )iridium(III) (abbreviation: [Ir(pq) ₃ ]), bis(2-phenylquinolinato-N,C ^2′ )iridium(III) acetylacetonate (abbreviation: Organometallic iridium complexes having a pyridine skeleton such as [Ir(pq) ₂ (acac)]), bis(2,4-diphenyl-1,3-oxazolato-N,C ^2′ )iridium(III) acetylacetonate (abbreviation: [Ir(dpo) ₂ (acac)]), bis{2-[4′-(perfluorophenyl)phenyl]pyridinato-N,C ^2′ }iridium(III) acetylacetonate (abbreviation: [Ir (p-PF-ph) ₂ (acac)]), bis(2-phenylbenzothiazolato-N,C ^2′ ) iridium (III) acetylacetonate (abbreviation: [Ir(bt) ₂ (acac)] ) and rare earth metal complexes such as tris(acetylacetonato)(monophenanthroline)terbium(III) (abbreviation: [Tb(acac) ₃ (Phen)]).

Among the above-described organometallic iridium complexes having a pyridine skeleton (especially a phenylpyridine skeleton) or a pyrimidine skeleton, are a group of compounds useful for achieving green chromaticity in one embodiment of the present invention.

Examples of phosphorescent materials that exhibit yellow or red color and have an emission spectrum with a peak wavelength of 570 nm or more and 750 nm or less include the following substances.

For example, (diisobutyrylmethanato)bis[4,6-bis(3-methylphenyl)pyrimidinato]iridium (III) (abbreviation: [Ir (5mdppm) ₂ (dibm)]), bis[4,6-bis ( 3-methylphenyl)pyrimidinato](dipivaloylmethanato)iridium (III) (abbreviation: [Ir(5mdppm) ₂ (dpm)]), (dipivaloylmethanato)bis[4,6-di(naphthalene- 1-yl)pyrimidinato]iridium(III) (abbreviation: [Ir(d1npm) ₂ (dpm)]), an organometallic complex having a pyrimidine skeleton, (acetylacetonato)bis(2,3,5-triphenyl pyrazinato)iridium (III) (abbreviation: [Ir(tppr) ₂ (acac)]), bis(2,3,5-triphenylpyrazinato)(dipivaloylmethanato)iridium (III) (abbreviation: : [Ir(tppr) ₂ (dpm)]), bis{4,6-dimethyl-2-[3-(3,5-dimethylphenyl)-5-phenyl-2-pyrazinyl-κN]phenyl-κC} ( 2,6-dimethyl-3,5-heptanedionato-κ ² O,O′) iridium (III) (abbreviation: [Ir(dmdppr-P) ₂ (dibm)]), bis{4,6-dimethyl-2- [5-(4-cyano-2,6-dimethylphenyl)-3-(3,5-dimethylphenyl)-2-pyrazinyl-κN]phenyl-κC}(2,2,6,6-tetramethyl-3 ,5-heptanedionato-κ ² O,O′)iridium(III) (abbreviation: [Ir(dmdppr-dmCP) ₂ (dpm)]), (acetylacetonato)bis[2-methyl-3-phenylquinoxalinato —N,C ^2′ ]iridium (III) (abbreviation: [Ir(mpq) ₂ (acac)]), (acetylacetonato)bis(2,3-diphenylquinoxalinato-N,C ^2′ )iridium ( III) (abbreviation: [Ir(dpq) ₂ (acac)]), (acetylacetonato)bis[2,3-bis(4-fluorophenyl)quinoxalinato]iridium (III) (abbreviation: [Ir(Fdpq) ₂ (acac)]), an organometallic complex having a pyrazine skeleton such as tris(1-phenylisoquinolinato-N,C ^2′ ) iridium (III) (abbreviation: [Ir(piq) ₃ ]), bis( Organometallic complexes having a pyridine skeleton such as 1-phenylisoquinolinato-N,C ^2′ )iridium (III) acetylacetonate (abbreviation: [Ir(piq) ₂ (acac)]), 2,3,7 ,8,12,13,17,18-octaethyl-21H,23H-porphyrinplatinum(II) (abbreviation: [PtOEP]), platinum complexes such as tris(1,3-diphenyl-1,3-propanedionate ) (monophenanthroline) europium (III) (abbreviation: [Eu(DBM) ₃ (Phen)]), tris[1-(2-thenoyl)-3,3,3-trifluoroacetonato](monophenanthroline) europium Rare earth metal complexes such as (III) (abbreviation: [Eu(TTA) ₃ (Phen)]) can be mentioned.

Among the above-described organometallic iridium complexes having a pyrazine skeleton, they are a compound group useful for achieving red chromaticity in one embodiment of the present invention. In particular, organometallic iridium complexes having a cyano group, such as [Ir(dmdppr-dmCP) ₂ (dpm)], are highly stable and preferred.

Note that as the blue light-emitting substance, a substance having a photoluminescence peak wavelength of 430 nm to 470 nm, preferably 430 nm to 460 nm, may be used. As a green light-emitting substance, a substance having a photoluminescence peak wavelength of 500 nm to 540 nm, preferably 500 nm to 530 nm, may be used. As a red light-emitting substance, a substance having a photoluminescence peak wavelength of 610 nm to 680 nm, preferably 620 nm to 680 nm, may be used. Note that the photoluminescence measurement may be performed on either a solution or a thin film.

By using such a compound together with the microcavity effect, the chromaticity described above can be achieved more easily. At this time, the film thickness of the semi-transmissive/semi-reflective electrode (metal thin film portion) necessary to obtain the microcavity effect is preferably 20 nm or more and 40 nm or less. More preferably, it is larger than 25 nm and 40 nm or less. In addition, if the thickness exceeds 40 nm, the efficiency may decrease.

As the organic compound (host material, assist material) used for the light-emitting layer 723, one or a plurality of substances having an energy gap larger than that of the light-emitting substance (guest material) may be selected and used. The hole-transporting material described above and the electron-transporting material described later can also be used as a host material or an assist material, respectively.

When the light-emitting substance is a fluorescent material, an organic compound having a high singlet excited energy level and a low triplet excited energy level is preferably used as the host material. For example, it is preferable to use an anthracene derivative or a tetracene derivative. Specifically, 9-phenyl-3-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (abbreviation: PCzPA), 3-[4-(1-naphthyl)-phenyl]-9 -Phenyl-9H-carbazole (abbreviation: PCPN), 9-[4-(10-phenyl-9-anthracenyl)phenyl]-9H-carbazole (abbreviation: CzPA), 7-[4-(10-phenyl-9- anthryl)phenyl]-7H-dibenzo[c,g]carbazole (abbreviation: cgDBCzPA), 6-[3-(9,10-diphenyl-2-anthryl)phenyl]-benzo[b]naphtho[1,2-d ] Furan (abbreviation: 2mBnfPPA), 9-phenyl-10-{4-(9-phenyl-9H-fluoren-9-yl)biphenyl-4′-yl}anthracene (abbreviation: FLPPA), 5,12-diphenyltetracene , 5,12-bis(biphenyl-2-yl)tetracene and the like.

When the light-emitting substance is a phosphorescent material, an organic compound having triplet excitation energy higher than the triplet excitation energy (the energy difference between the ground state and the triplet excited state) of the light-emitting substance may be selected as the host material. In this case, in addition to zinc and aluminum-based metal complexes, oxadiazole derivatives, triazole derivatives, benzimidazole derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, pyrimidine derivatives, triazine derivatives, pyridine derivatives , bipyridine derivatives, phenanthroline derivatives, aromatic amines, carbazole derivatives and the like can be used.

Specifically, tris(8-quinolinolato)aluminum (III) (abbreviation: Alq), tris(4-methyl-8-quinolinolato)aluminum (III) (abbreviation: Almq ₃ ), bis(10-hydroxybenzo[h ] Quinolinato)beryllium (II) (abbreviation: BeBq ₂ ), bis(2-methyl-8-quinolinolato)(4-phenylphenolato)aluminum (III) (abbreviation: BAlq), bis(8-quinolinolato)zinc(II) ) (abbreviation: Znq), bis[2-(2-benzoxazolyl)phenolato]zinc (II) (abbreviation: ZnPBO), bis[2-(2-benzothiazolyl)phenolato]zinc (II) (abbreviation: ZnBTZ ), 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis[5-(p -tert-butylphenyl)-1,3,4-oxadiazol-2-yl]benzene (abbreviation: OXD-7), 3-(4-biphenylyl)-4-phenyl-5-(4-tert-butyl Phenyl)-1,2,4-triazole (abbreviation: TAZ), 2,2′,2″-(1,3,5-benzenetriyl)-tris(1-phenyl-1H-benzimidazole) (abbreviation: TAZ) : TPBI), bathophenanthroline (abbreviation: BPhen), bathocuproine (abbreviation: BCP), 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBphen), 9 Heterocyclic compounds such as -[4-(5-phenyl-1,3,4-oxadiazol-2-yl)phenyl]-9H-carbazole (abbreviation: CO11), aromatic amines such as NPB, TPD, and BSPB compound.

Condensed polycyclic aromatic compounds such as anthracene derivatives, phenanthrene derivatives, pyrene derivatives, chrysene derivatives, dibenzo[g,p]chrysene derivatives, and the like, specifically, 9,10-diphenylanthracene (abbreviation: DPAnth). , N,N-diphenyl-9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazol-3-amine (abbreviation: CzA1PA), 4-(10-phenyl-9-anthryl)triphenyl Amine (abbreviation: DPhPA), YGAPA, PCAPA, N,9-diphenyl-N-{4-[4-(10-phenyl-9-anthryl)phenyl]phenyl}-9H-carbazol-3-amine (abbreviation: PCAPBA) ), 9,10-diphenyl-2-[N-phenyl-N-(9-phenyl-9H-carbazol-3-yl)amino]anthracene (abbreviation: 2PCAPA), 6,12-dimethoxy-5,11-diphenyl chrysene, N,N,N',N',N'',N'',N''',N'''-octaphenyldibenzo[g,p]chrysene-2,7,10,15-tetramine ( Abbreviations: DBC1), 9-[4-(10-phenyl-9-anthracenyl)phenyl]-9H-carbazole (abbreviation: CzPA), 3,6-diphenyl-9-[4-(10-phenyl-9-anthryl) ) phenyl]-9H-carbazole (abbreviation: DPCzPA), 9,10-bis(3,5-diphenylphenyl)anthracene (abbreviation: DPPA), 9,10-di(2-naphthyl)anthracene (abbreviation: DNA), 2-tert-butyl-9,10-di(2-naphthyl)anthracene (abbreviation: t-BuDNA), 9,9′-bianthryl (abbreviation: BANT), 9,9′-(stilbene-3,3′- diyl)diphenanthrene (abbreviation: DPNS), 9,9′-(stilbene-4,4′-diyl)diphenanthrene (abbreviation: DPNS2), 1,3,5-tri(1-pyrenyl)benzene (abbreviation: TPB3) ) and the like can be used.

In the case where a plurality of organic compounds are used for the light-emitting layer 723, it is preferable to use a compound that forms an exciplex in combination with a light-emitting substance. In this case, various organic compounds can be used in combination as appropriate. transportable materials) are particularly preferred. Note that as specific examples of the hole-transporting material and the electron-transporting material, the materials described in this embodiment can be used.

A TADF material is a material that can up-convert (reverse intersystem crossing) a triplet excited state to a singlet excited state with a small amount of thermal energy, and efficiently exhibits light emission (fluorescence) from the singlet excited state. be. In addition, as a condition for efficiently obtaining thermally activated delayed fluorescence, the energy difference between the triplet excitation level and the singlet excitation level is 0 eV or more and 0.2 eV or less, preferably 0 eV or more and 0.1 eV or less. mentioned. In addition, delayed fluorescence in the TADF material refers to light emission having a spectrum similar to that of normal fluorescence and having a significantly long lifetime. Its lifetime is 10 ⁻⁶ seconds or more, preferably 10 ⁻³ seconds or more.

Examples of TADF materials include fullerenes and derivatives thereof, acridine derivatives such as proflavine, and eosin. Also included are metal-containing porphyrins containing magnesium (Mg), zinc (Zn), cadmium (Cd), tin (Sn), platinum (Pt), indium (In), or palladium (Pd). Examples of metal-containing porphyrins include protoporphyrin-tin fluoride complex (SnF ₂ (Proto IX)), mesoporphyrin-tin fluoride complex (SnF ₂ (Meso IX)), hematoporphyrin-tin fluoride complex (SnF ₂ (Hemato IX)), coproporphyrin tetramethyl ester-tin fluoride complex (SnF ₂ (Copro III-4Me)), octaethylporphyrin-tin fluoride complex (SnF ₂ (OEP)), ethioporphyrin-tin fluoride complex (SnF ₂ (Etio I)), octaethylporphyrin-platinum chloride complex (PtCl ₂ OEP), and the like.

In addition, 2-(biphenyl-4-yl)-4,6-bis(12-phenylindolo[2,3-a]carbazol-11-yl)-1,3,5-triazine (PIC-TRZ ), 2-{4-[3-(N-phenyl-9H-carbazol-3-yl)-9H-carbazol-9-yl]phenyl}-4,6-diphenyl-1,3,5-triazine (PCCzPTzn ), 2-[4-(10H-phenoxazin-10-yl)phenyl]-4,6-diphenyl-1,3,5-triazine (PXZ-TRZ), 3-[4-(5-phenyl-5 ,10-dihydrophenazin-10-yl)phenyl]-4,5-diphenyl-1,2,4-triazole (PPZ-3TPT), 3-(9,9-dimethyl-9H-acridin-10-yl)- 9H-xanthen-9-one (ACRXTN), bis[4-(9,9-dimethyl-9,10-dihydroacridine)phenyl]sulfone (DMAC-DPS), 10-phenyl-10H,10′H-spiro[ Heterocyclic compounds having π-electron-rich heteroaromatic rings and π-electron-deficient heteroaromatic rings such as acridine-9,9′-anthracene]-10′-one (ACRSA) can be used. In a substance in which a π-electron-rich heteroaromatic ring and a π-electron-deficient heteroaromatic ring are directly bonded, both the donor property of the π-electron-rich heteroaromatic ring and the acceptor property of the π-electron-deficient heteroaromatic ring are strengthened. , is particularly preferable because the energy difference between the singlet excited state and the triplet excited state is small.

In addition, when using a TADF material, it can also be used in combination with other organic compounds.

<<electron transport layer 724>>
The electron-transporting layer 724 is a layer that transports electrons injected from the conductor 788 by the electron-injecting layer 725 to the light-emitting layer 723 . Note that the electron-transporting layer 724 is a layer containing an electron-transporting material. An electron-transporting material used for the electron-transporting layer 724 is preferably a substance having an electron mobility of 1×10 ⁻⁶ cm ² /Vs or more. Note that any substance other than these substances can be used as long as it has a higher electron-transport property than hole-transport property.

Examples of electron-transporting materials include metal complexes having quinoline ligands, benzoquinoline ligands, oxazole ligands, or thiazole ligands, oxadiazole derivatives, triazole derivatives, phenanthroline derivatives, pyridine derivatives, bipyridine derivatives, and the like. is mentioned. In addition, a π-electron-deficient heteroaromatic compound such as a nitrogen-containing heteroaromatic compound can also be used.

Specifically, Alq ₃ , tris(4-methyl-8-quinolinolato)aluminum (abbreviation: Almq ₃ ), bis(10-hydroxybenzo[h]quinolinato)beryllium (abbreviation: BeBq ₂ ), BAlq, Zn (BOX ) ₂ , metal complexes such as bis[2-(2-hydroxyphenyl)benzothiazolato]zinc (abbreviation: Zn(BTZ) ₂ ), 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1 , 3,4-oxadiazole (abbreviation: PBD), 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazol-2-yl]benzene (abbreviation: OXD -7), 3-(4′-tert-butylphenyl)-4-phenyl-5-(4″-biphenyl)-1,2,4-triazole (abbreviation: TAZ), 3-(4-tert- Butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: Bphen), bathocuproine (abbreviation: BCP) , 4,4′-bis(5-methylbenzoxazol-2-yl)stilbene (abbreviation: BzOs) and other heteroaromatic compounds, 2-[3-(dibenzothiophen-4-yl)phenyl]dibenzo[f, h]quinoxaline (abbreviation: 2mDBTPDBq-II), 2-[3′-(dibenzothiophen-4-yl)biphenyl-3-yl]dibenzo[f,h]quinoxaline (abbreviation: 2mDBTBPDBq-II), 2-[4 -(3,6-diphenyl-9H-carbazol-9-yl)phenyl]dibenzo[f,h]quinoxaline (abbreviation: 2CzPDBq-III), 7-[3-(dibenzothiophen-4-yl)phenyl]dibenzo[ quinoxaline or dibenzoquinoxaline derivative such as f,h]quinoxaline (abbreviation: 7mDBTPDBq-II), 6-[3-(dibenzothiophen-4-yl)phenyl]dibenzo[f,h]quinoxaline (abbreviation: 6mDBTPDBq-II); can be used.

In addition, poly(2,5-pyridinediyl) (abbreviation: PPy), poly[(9,9-dihexylfluorene-2,7-diyl)-co-(pyridine-3,5-diyl)] (abbreviation: PF -Py), poly[(9,9-dioctylfluorene-2,7-diyl)-co-(2,2′-bipyridine-6,6′-diyl)] (abbreviation: PF-BPy) Molecular compounds can also be used.

In addition, the electron transport layer 724 may have a structure in which two or more layers made of the above substances are laminated as well as a single layer.

<<electron injection layer 725>>
The electron injection layer 725 is a layer containing a substance with high electron injection properties. Electron injection layer 725 may include alkali metals such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride ( _CaF2 ), lithium oxide ( _LiOx ), alkaline earth metals, or the like. can be used. Also, rare earth metal compounds such as erbium fluoride (ErF ₃ ) can be used. Electride may also be used for the electron injection layer 725 . Examples of the electride include a mixed oxide of calcium and aluminum to which electrons are added at a high concentration. Note that the above-described substances forming the electron-transporting layer 724 can also be used.

Alternatively, a composite material obtained by mixing an organic compound and an electron donor (donor) may be used for the electron injection layer 725 . Such a composite material has excellent electron injection properties and electron transport properties because electrons are generated in the organic compound by the electron donor. In this case, the organic compound is preferably a material that is excellent in transporting the generated electrons. ) can be used. As the electron donor, any substance can be used as long as it exhibits an electron donating property with respect to an organic compound. Specifically, alkali metals, alkaline earth metals, and rare earth metals are preferred, and examples include lithium, cesium, magnesium, calcium, erbium, and ytterbium. Further, alkali metal oxides and alkaline earth metal oxides are preferred, and examples thereof include lithium oxide, calcium oxide and barium oxide. Lewis bases such as magnesium oxide can also be used. An organic compound such as tetrathiafulvalene (abbreviation: TTF) can also be used.

<<charge generating layer 792>>
The charge generation layer 792 is formed in the EL layer 786 closer to the conductor 772 of the two EL layers 786 in contact with the charge generation layer 792 when a voltage is applied between the conductor 772 and the conductor 788 . It has a function of injecting electrons and injecting holes into the EL layer 786 on the side different from the conductor 788 . For example, in the light-emitting element 572 having the structure shown in FIG. 36C, the charge generation layer 792 has a function of injecting electrons into the EL layer 786a and holes into the EL layer 786b. Note that the charge generation layer 792 may have a structure in which an electron acceptor (acceptor) is added to a hole-transporting material or a structure in which an electron donor (donor) is added to an electron-transporting material. good. Also, both of these configurations may be stacked. Note that by forming the charge generation layer 792 using the above material, an increase in driving voltage of the display device 10 in the case where EL layers are stacked can be suppressed.

When the charge generation layer 792 has a structure in which an electron acceptor is added to a hole-transporting material, the electron acceptor is 7,7,8,8-tetracyano-2,3,5,6-tetrafluoro Examples include quinodimethane (abbreviation: F ₄ -TCNQ), chloranil and the like. In addition, oxides of metals belonging to groups 4 to 8 in the periodic table can be mentioned. Specific examples include vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, and rhenium oxide.

When the charge generation layer 792 has a structure in which an electron donor is added to an electron transporting material, the electron donor is an alkali metal, an alkaline earth metal, a rare earth metal, or elements of groups 2 and 13 in the periodic table. and oxides and carbonates thereof can be used. Specifically, it is preferable to use lithium (Li), cesium (Cs), magnesium (Mg), calcium (Ca), ytterbium (Yb), indium (In), lithium oxide, cesium carbonate, or the like. Alternatively, an organic compound such as tetrathianaphthacene may be used as an electron donor.

Note that the light-emitting element 572 can be manufactured by a vacuum process such as an evaporation method, or a solution process such as a spin coating method or an inkjet method. When vapor deposition is used, physical vapor deposition (PVD) such as sputtering, ion plating, ion beam vapor deposition, molecular beam vapor deposition, vacuum vapor deposition, or chemical vapor deposition (CVD) is used. be able to. In particular, regarding the functional layers (hole injection layer, hole transport layer, light emitting layer, electron transport layer, electron injection layer) and charge generation layer included in the EL layer of the light emitting element, vapor deposition (vacuum vapor deposition, etc.), coating method (dip coat method, die coat method, bar coat method, spin coat method, spray coat method, etc.), printing method (inkjet method, screen (stencil printing) method, offset (lithographic printing) method, flexographic (letterpress printing) method, gravure method, microcontact method, etc.).

Note that each functional layer (a hole-injection layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, and an electron-injection layer) and a charge-generation layer constituting the EL layer of the light-emitting element described in this embodiment are made of the above materials. However, other materials can be used in combination as long as they can satisfy the functions of each layer. Examples include polymer compounds (oligomers, dendrimers, polymers, etc.), middle-molecular-weight compounds (compounds in the intermediate region between low-molecular-weight and high-molecular-weight compounds: molecular weight 400 to 4000), inorganic compounds (quantum dot materials, etc.), and the like. can. As the quantum dot material, a colloidal quantum dot material, an alloy quantum dot material, a core-shell quantum dot material, a core quantum dot material, or the like can be used.

At least a part of the structural examples and the drawings corresponding to them in this embodiment can be combined with other structural examples, drawings, and the like as appropriate.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 2)
In this embodiment, a transistor that can be used for a display device that is one embodiment of the present invention will be described.

<Structure Example 1 of Transistor>
37A, 37B, and 37C are a top view and a cross-sectional view of a transistor 200A that can be used in a display device that is one embodiment of the present invention, and the periphery of the transistor 200A. The transistor 200A can be applied to the display device of one embodiment of the present invention.

FIG. 37A is a top view of the transistor 200A. 37B and 37C are cross-sectional views of the transistor 200A. Here, FIG. 37B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 37A, and is also a cross-sectional view in the channel length direction of the transistor 200A. FIG. 37C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 37A, and is also a cross-sectional view in the channel width direction of the transistor 200A. Note that in the top view of FIG. 37A, some elements are omitted for clarity of illustration.

As shown in FIGS. 37A, 37B, and 37C, the transistor 200A includes a metal oxide 230a placed over a substrate (not shown) and a metal oxide 230a placed over the metal oxide 230a. The conductors 242a and 242b are arranged over the metal oxide 230b and the conductor 242a and the conductor 242b spaced apart from each other over the metal oxide 230b and the conductor 242a and the conductor 242b. An insulator 280 with an opening formed therebetween, a conductor 260 arranged in the opening, a metal oxide 230b, a conductor 242a, and a conductor 242b, the insulator 280, and the conductor 260. It has an insulator 250 interposed therebetween, a metal oxide 230b, a conductor 242a, a conductor 242b, an insulator 280, and a metal oxide 230c interposed therebetween. Here, as shown in FIGS. 37B and 37C, the top surface of the conductor 260 is substantially aligned with the top surfaces of the insulator 250, the insulator 254, the metal oxide 230c, and the insulator 280. is preferred. Note that the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may be collectively referred to as the metal oxide 230 below. Also, the conductor 242a and the conductor 242b may be collectively referred to as a conductor 242 in some cases.

In the transistor 200A illustrated in FIGS. 37A, 37B, and 37C, side surfaces of the conductors 242a and 242b on the conductor 260 side are substantially vertical. Note that the transistor 200A shown in FIGS. 37A, 37B, and 37C is not limited to this, and the angle between the side surfaces and the bottom surfaces of the conductors 242a and 242b is 10° to 80°. Hereinafter, preferably, the angle may be 30° or more and 60° or less. Moreover, the opposing side surfaces of the conductor 242a and the conductor 242b may have a plurality of surfaces.

In addition, as shown in FIGS. 37A, 37B, and 37C, an insulator 224, a metal oxide 230a, a metal oxide 230b, a conductor 242a, a conductor 242b, and a metal oxide 230c, and an insulating material An insulator 254 is preferably disposed between the body 280 and the body 280 . Here, as shown in FIGS. 37B and 37C, the insulator 254 includes the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, and the metal oxide. It preferably contacts the sides of 230 a and metal oxide 230 b and the top of insulator 224 .

Note that in the transistor 200A, three layers of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c are stacked in a region where a channel is formed (hereinafter also referred to as a channel formation region) and its vicinity. , but the invention is not limited to this. For example, a two-layer structure of the metal oxide 230b and the metal oxide 230c, or a laminated structure of four or more layers may be provided. Further, in the transistor 200A, the conductor 260 has a two-layer structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a laminated structure of three or more layers. Moreover, each of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may have a laminated structure of two or more layers.

For example, if the metal oxide 230c has a stacked structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, the first metal oxide is the metal oxide 230b. Having a similar composition, the second metal oxide preferably has a similar composition to metal oxide 230a.

Here, the conductor 260 functions as a gate electrode of the transistor, and the conductors 242a and 242b function as source and drain electrodes, respectively. As described above, the conductor 260 is formed to be embedded in the opening of the insulator 280 and the region sandwiched between the conductors 242a and 242b. Here, the arrangement of the conductors 260 , 242 a and 242 b is selected in a self-aligned manner with respect to the opening of the insulator 280 . That is, in the transistor 200A, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, since the conductor 260 can be formed without providing a margin for alignment, the area occupied by the transistor 200A can be reduced. As a result, the display device can have high definition. In addition, the display device can have a narrow frame.

Further, as shown in FIGS. 37A, 37B, and 37C, the conductor 260 includes a conductor 260a provided inside the insulator 250 and a conductor 260a provided so as to be embedded inside the conductor 260a. It is preferable to have the conductors 260b and .

In addition, the transistor 200A includes an insulator 214 provided over a substrate (not shown), an insulator 216 provided over the insulator 214, and a conductor embedded in the insulator 216. 205 , insulator 222 disposed over insulator 216 and conductor 205 , and insulator 224 disposed over insulator 222 . A metal oxide 230 a is preferably disposed over the insulator 224 .

An insulator 274 and an insulator 281 functioning as an interlayer film are preferably provided over the transistor 200A. Here, the insulator 274 is preferably arranged in contact with top surfaces of the conductor 260 , the insulator 250 , the insulator 254 , the metal oxide 230 c , and the insulator 280 .

The insulators 222, 254, and 274 preferably have a function of suppressing at least one diffusion of hydrogen (eg, hydrogen atoms, hydrogen molecules, or the like). For example, insulators 222 , 254 , and 274 preferably have lower hydrogen permeability than insulators 224 , 250 , and 280 . The insulators 222 and 254 preferably have a function of suppressing at least one diffusion of oxygen (eg, oxygen atoms, oxygen molecules, or the like). For example, insulators 222 and 254 preferably have lower oxygen permeability than insulators 224 , 250 and 280 .

Here, insulator 224 , metal oxide 230 , and insulator 250 are separated by insulators 280 and 281 and insulators 254 and 274 . Therefore, impurities such as hydrogen contained in the insulators 280 and 281 and excess oxygen are added to the insulator 224, the metal oxide 230a, and the insulator 250 in the insulator 224, the metal oxide 230a, and the metal oxide. 230b and the insulator 250 can be suppressed.

Further, it is preferable that a conductor 240 (a conductor 240a and a conductor 240b) which is electrically connected to the transistor 200A and functions as a plug is provided. Note that insulators 241 (an insulator 241a and an insulator 241b) are provided in contact with side surfaces of the conductor 240 functioning as a plug. That is, the insulator 241 is provided in contact with the inner walls of the openings of the insulator 254 , the insulator 280 , the insulator 274 , and the insulator 281 . Alternatively, the first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241 and the second conductor of the conductor 240 may be provided inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made approximately the same. Note that although the structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown in the transistor 200A, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned in order of formation for distinction.

In the transistor 200A, the metal oxide 230 (the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c) including the channel formation region is added with a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). ) is preferably used. For example, as the metal oxide that serves as the channel formation region of the metal oxide 230, it is preferable to use one having a bandgap of 2 eV or more, preferably 2.5 eV or more, as described above.

Further, as shown in FIG. 37B, the thickness of the metal oxide 230b in a region that does not overlap with the conductor 242 is thinner than that in a region that overlaps with the conductor 242 in some cases. This is formed by removing a portion of the top surface of metal oxide 230b when forming conductors 242a and 242b. When a conductive film to be the conductor 242 is formed on the top surface of the metal oxide 230b, a region with low resistance may be formed near the interface with the conductive film. By removing the region with low resistance located between the conductors 242a and 242b on the top surface of the metal oxide 230b in this manner, formation of a channel in this region can be prevented.

According to one embodiment of the present invention, a high-definition display device including a small-sized transistor can be provided. Alternatively, a high-luminance display device including a transistor with high on-state current can be provided. Alternatively, a fast-operating display device can be provided with a fast-operating transistor. Alternatively, a highly reliable display device including a transistor with stable electrical characteristics can be provided. Alternatively, a display device including a transistor with low off-state current and low power consumption can be provided.

A detailed structure of the transistor 200A that can be used in the display device that is one embodiment of the present invention will be described.

The conductor 205 is arranged so as to have regions that overlap with the metal oxide 230 and the conductor 260 . Further, the conductor 205 is preferably embedded in the insulator 216 . Here, it is preferable to improve the flatness of the upper surface of the conductor 205 . For example, the average surface roughness (Ra) of the upper surface of the conductor 205 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Accordingly, planarity of the insulator 224 formed over the conductor 205 can be improved, and crystallinity of the metal oxides 230b and 230c can be improved.

Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. In some cases, the conductor 205 functions as a second gate (also referred to as a bottom gate) electrode. In that case, V _th of the transistor 200A can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 . In particular, by applying a negative potential to the conductor 205, _Vth of the transistor 200A can be made higher than 0 V, and off current can be reduced. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no potential is applied.

Further, the conductor 205 is preferably provided larger than the channel formation region in the metal oxide 230 . In particular, as shown in FIG. 37(C), the conductor 205 preferably extends even in a region outside the edge crossing the channel width direction of the metal oxide 230 . In other words, the conductor 205 and the conductor 260 preferably overlap with each other with an insulator interposed therebetween on the outside of the side surface of the metal oxide 230 in the channel width direction.

With the above structure, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode cause the channel formation region of the metal oxide 230 to be expanded. It can be surrounded electrically.

Further, as shown in FIG. 37C, the conductor 205 is extended to function as wiring. However, without being limited to this, a structure in which a conductor functioning as a wiring is provided under the conductor 205 may be employed.

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 205 . Although the conductor 205 is illustrated as a single layer, it may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive material.

In addition, it has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ etc.), copper atoms, etc. under the conductor 205 . A conductor having (the above-described impurities are difficult to permeate) may be used. Alternatively, it is preferable to use a conductor that has a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) (permeation of oxygen is difficult). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of either one or all of the impurities or oxygen.

By using a conductor having a function of suppressing diffusion of oxygen under the conductor 205, it is possible to suppress oxidation of the conductor 205 and a decrease in conductivity. As the conductor having a function of suppressing diffusion of oxygen, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example. Therefore, as the first conductor of the conductor 205, a single layer or a laminate of the above conductive materials may be used.

The insulator 214 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200A from the substrate side. Therefore, the insulator 214 has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ and the like), and copper atoms. (It is difficult for the above impurities to permeate.) It is preferable to use an insulating material. Alternatively, it is preferable to use an insulating material that has a function of suppressing at least one diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above-described oxygen is difficult to permeate).

For example, aluminum oxide, silicon nitride, or the like is preferably used as the insulator 214 . Accordingly, impurities such as water or hydrogen can be prevented from diffusing from the substrate side to the transistor 200A side with respect to the insulator 214 . Alternatively, diffusion of oxygen contained in the insulator 224 or the like to the substrate side of the insulator 214 can be suppressed.

Further, the insulators 216 , 280 , and 281 that function as interlayer films preferably have a lower dielectric constant than the insulator 214 . By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, the insulator 216, the insulator 280, and the insulator 281 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, and carbon and nitrogen are added. Silicon oxide, silicon oxide having holes, or the like may be used as appropriate.

The insulators 222 and 224 function as gate insulators.

Here, the insulator 224 in contact with the metal oxide 230 preferably releases oxygen by heating. In this specification, the oxygen released by heating is sometimes referred to as excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be used as appropriate for the insulator 224 . By providing an insulator containing oxygen in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be reduced and the reliability of the transistor 200A can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator 224 . The oxide that desorbs oxygen by heating means that the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 ¹⁸ atoms/cm ³ or more, preferably 1, in TDS (Thermal Desorption Spectroscopy) analysis. 0×10 ¹⁹ atoms/cm ³ or more, more preferably 2.0×10 ¹⁹ atoms/cm ³ or more, or 3.0×10 ²⁰ atoms/cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.

Further, as shown in FIG. 37C, the insulator 224 does not overlap with the insulator 254 and does not overlap with the metal oxide 230b, and the thickness of the region is thinner than that of the other regions. There is The thickness of the region of the insulator 224 which does not overlap with the insulator 254 and does not overlap with the metal oxide 230b is preferably a thickness with which oxygen can be diffused sufficiently.

Like the insulator 214 and the like, the insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200A from the substrate side. For example, insulator 222 preferably has a lower hydrogen permeability than insulator 224 . By surrounding the insulator 224, the metal oxide 230, the insulator 250, and the like with the insulator 222, the insulator 254, and the insulator 274, impurities such as water or hydrogen can be prevented from entering the transistor 200A from the outside. can be suppressed.

Further, the insulator 222 preferably has a function of suppressing diffusion of at least one of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less permeable). For example, insulator 222 preferably has a lower oxygen permeability than insulator 224 . The insulator 222 preferably has a function of suppressing diffusion of oxygen and impurities, so that diffusion of oxygen in the metal oxide 230 to the substrate side can be reduced. Further, the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 and the metal oxide 230 .

As the insulator 222, an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials, is preferably used. As the insulator containing oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 222 is formed using such a material, the insulator 222 prevents oxygen from being released from the metal oxide 230 and impurities such as hydrogen from entering the metal oxide 230 from the periphery of the transistor 200A. Acts as a restraining layer.

Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

The insulator 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr)TiO ₃ (BST). Insulators containing so-called high-k materials may be used in single or stacked layers. As transistors are miniaturized and highly integrated, thinning of gate insulators may cause problems such as leakage current. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

Note that the insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may be used. For example, an insulator similar to the insulator 224 may be provided under the insulator 222 .

Metal oxide 230 has metal oxide 230a, metal oxide 230b over metal oxide 230a, and metal oxide 230c over metal oxide 230b. Having the metal oxide 230a under the metal oxide 230b can suppress the diffusion of impurities from the structure formed below the metal oxide 230a to the metal oxide 230b. In addition, by having the metal oxide 230c on the metal oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed above the metal oxide 230c to the metal oxide 230b.

Note that the metal oxide 230 preferably has a layered structure with oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the metal oxide 230a, the atomic ratio of the element M among the constituent elements is higher than the atomic ratio of the element M among the constituent elements in the metal oxide used for the metal oxide 230b. Large is preferred. Moreover, in the metal oxide used for the metal oxide 230a, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the metal oxide 230b. Moreover, in the metal oxide used for the metal oxide 230b, the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the metal oxide 230a. In addition, the metal oxide 230c can be a metal oxide that can be used for the metal oxide 230a or the metal oxide 230b.

The metal oxide 230a, the metal oxide 230b, and the metal oxide 230c preferably have crystallinity, and in particular, CAAC-OS is preferably used. A crystalline oxide such as CAAC-OS has few impurities and defects (such as oxygen vacancies) and has a dense structure with high crystallinity. Therefore, extraction of oxygen from the metal oxide 230b by the source electrode or the drain electrode can be suppressed. As a result, the extraction of oxygen from the metal oxide 230b can be reduced even if heat treatment is performed, so the transistor 200A is stable against high temperatures (so-called thermal budget) in the manufacturing process.

In addition, it is preferable that the energy of the conduction band bottom of the metal oxide 230a and the metal oxide 230c be higher than the energy of the conduction band bottom of the metal oxide 230b. Also, in other words, the electron affinities of the metal oxides 230a and 230c are preferably smaller than the electron affinities of the metal oxide 230b. In this case, the metal oxide 230c is preferably a metal oxide that can be used for the metal oxide 230a. Specifically, in the metal oxide used for the metal oxide 230c, the atomic ratio of the element M among the constituent elements is higher than the atomic ratio of the element M among the constituent elements in the metal oxide used for the metal oxide 230b. , preferably large. Moreover, in the metal oxide used for the metal oxide 230c, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the metal oxide 230b. In addition, the atomic ratio of In to the element M in the metal oxide used for the metal oxide 230b is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the metal oxide 230c.

Here, the energy level at the bottom of the conduction band changes smoothly at the junction of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c. In other words, it can be said that the energy level at the bottom of the conduction band at the junction of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c continuously changes or continuously joins. In order to achieve this, it is preferable to lower the defect level density of the mixed layers formed at the interfaces between the metal oxides 230a and 230b and the interfaces between the metal oxides 230b and 230c.

Specifically, the metal oxide 230a and the metal oxide 230b, and the metal oxide 230b and the metal oxide 230c have a common element (main component) other than oxygen, so that the defect level density is low. Mixed layers can be formed. For example, when the metal oxide 230b is an In--Ga--Zn oxide (also referred to as IGZO), the metal oxide 230a and the metal oxide 230c are In--Ga--Zn oxide, Ga--Zn oxide, gallium oxide, or the like. may be used. Alternatively, the metal oxide 230c may have a laminated structure. For example, a stacked structure of In--Ga--Zn oxide and Ga--Zn oxide on the In--Ga--Zn oxide, or In--Ga--Zn oxide and on the In--Ga--Zn oxide can be used. In other words, a stacked structure of an In--Ga--Zn oxide and an oxide containing no In may be used as the metal oxide 230c.

Specifically, a metal oxide of In:Ga:Zn=1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] may be used as the metal oxide 230a. As the metal oxide 230b, a metal oxide of In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] may be used. In addition, as the metal oxide 230c, In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:1 [ atomic number ratio] or Ga:Zn=2:5 [atomic ratio]. Further, as a specific example of the case where the metal oxide 230c has a laminated structure, In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio]. Laminated structure, In: Ga: Zn = 4: 2: 3 [atomic ratio] and Ga: Zn = 2: 5 [atomic ratio], In: Ga: Zn = 4: 2: 3 [ atomic ratio] and a laminated structure with gallium oxide.

At this time, the main path of carriers becomes the metal oxide 230b. By configuring the metal oxide 230a and the metal oxide 230c as described above, the defect level density at the interface between the metal oxide 230a and the metal oxide 230b and at the interface between the metal oxide 230b and the metal oxide 230c can be reduced. can be lowered. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200A can obtain high on-current and high frequency characteristics. When the metal oxide 230c has a laminated structure, in addition to the effect of lowering the defect level density at the interface between the metal oxide 230b and the metal oxide 230c, the constituent elements of the metal oxide 230c are It is expected to suppress the diffusion to the insulator 250 side. More specifically, the metal oxide 230c has a stacked structure, and the oxide that does not contain In is positioned above the stacked structure, so that In that can diffuse toward the insulator 250 can be suppressed. Since the insulator 250 functions as a gate insulator, the characteristics of the transistor deteriorate when In is diffused. Therefore, by forming the metal oxide 230c into a stacked structure, a highly reliable display device can be provided.

A metal oxide that functions as an oxide semiconductor is preferably used as the metal oxide 230 . For example, it is preferable to use a metal oxide having a bandgap of 2 eV or more, preferably 2.5 eV or more, as the metal oxide that serves as the channel formation region of the metal oxide 230 . By using a metal oxide with a large bandgap in this manner, off-state current of a transistor can be reduced. By using such a transistor, a display device with low power consumption can be provided.

A conductor 242 (a conductor 242a and a conductor 242b) functioning as a source electrode and a drain electrode is provided over the metal oxide 230b. Conductors 242 include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the metal elements described above, or an alloy combining the metal elements described above. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, and the like are used. is preferred. Also, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even after absorbing oxygen.

By providing the conductor 242 so as to be in contact with the metal oxide 230, the oxygen concentration in the vicinity of the conductor 242 of the metal oxide 230 may be reduced. In addition, in the vicinity of the conductor 242 of the metal oxide 230, a metal compound layer containing the metal contained in the conductor 242 and the components of the metal oxide 230 may be formed. In such a case, the carrier density increases in the region of the metal oxide 230 near the conductor 242, and the region becomes a low resistance region.

Here, a region between the conductor 242a and the conductor 242b is formed so as to overlap with the opening of the insulator 280. As shown in FIG. Accordingly, the conductor 260 can be arranged in a self-aligned manner between the conductor 242a and the conductor 242b.

Insulator 250 functions as a gate insulator. The insulator 250 is preferably placed in contact with the top surface of the metal oxide 230c. For the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies is used. be able to. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

Like the insulator 224, the insulator 250 preferably has a reduced impurity concentration such as water or hydrogen. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

Alternatively, a metal oxide may be provided between the insulator 250 and the conductor 260 . The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260 . Accordingly, oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

The metal oxide may also function as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide is preferably a high-k material with a high dielectric constant. When the gate insulator has a stacked-layer structure of the insulator 250 and the metal oxide, the stacked-layer structure can be stable against heat and have a high relative dielectric constant. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical film thickness of the gate insulator. Also, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator can be reduced.

Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like can be used. can. In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulator containing oxides of one or both of aluminum and hafnium.

Although the conductor 260 is shown as having a two-layer structure in FIG. 37, it may have a single-layer structure or a laminated structure of three or more layers.

The conductor 260a has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ and the like), and copper atoms. It is preferable to use a conductor having a Alternatively, a conductive material having a function of suppressing at least one diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) is preferably used.

In addition, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress oxidation of the conductor 260b due to oxygen contained in the insulator 250 and a decrease in conductivity. As the conductive material having a function of suppressing diffusion of oxygen, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example.

Further, the conductor 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. In addition, since the conductor 260 also functions as a wiring, a conductor with high conductivity is preferably used. For example, a conductive material whose main component is tungsten, copper, or aluminum can be used. Further, the conductor 260b may have a layered structure, for example, a layered structure of titanium, titanium nitride, and any of the above conductive materials.

Further, as shown in FIGS. 37A and 37C, in a region of the metal oxide 230b that does not overlap with the conductor 242, in other words, in a channel formation region of the metal oxide 230, the side surface of the metal oxide 230 are arranged to be covered with the conductor 260 . This makes it easier for the electric field of the conductor 260 functioning as the first gate electrode to act on the side surfaces of the metal oxide 230 . Therefore, it is possible to increase the ON current of the transistor 200A and improve the frequency characteristics.

Like the insulator 214 and the like, the insulator 254 preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the transistor 200A from the insulator 280 side. For example, insulator 254 preferably has a lower hydrogen permeability than insulator 224 . Further, as shown in FIGS. 37B and 37C, the insulator 254 includes side surfaces of the metal oxide 230c, top and side surfaces of the conductor 242a, top and side surfaces of the conductor 242b, and the metal oxide 230a. and the side surface of the metal oxide 230 b and the top surface of the insulator 224 . With such a structure, hydrogen contained in the insulator 280 enters the metal oxide 230 from the top surface or the side surface of the conductor 242a, the conductor 242b, the metal oxide 230a, the metal oxide 230b, and the insulator 224. can be suppressed.

Further, the insulator 254 preferably has a function of suppressing diffusion of at least one of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less permeable). For example, insulator 254 preferably has a lower oxygen permeability than insulator 280 or insulator 224 .

The insulator 254 is preferably deposited using a sputtering method. By forming the insulator 254 by a sputtering method in an atmosphere containing oxygen, oxygen can be added to the vicinity of a region of the insulator 224 which is in contact with the insulator 254 . Accordingly, oxygen can be supplied from the region into the metal oxide 230 through the insulator 224 . Here, the insulator 254 has a function of suppressing upward diffusion of oxygen, so that diffusion of oxygen from the metal oxide 230 to the insulator 280 can be prevented. In addition, since the insulator 222 has a function of suppressing diffusion of oxygen downward, oxygen can be prevented from diffusing from the metal oxide 230 to the substrate side. In this manner, oxygen is supplied to the channel formation region of metal oxide 230 . Accordingly, oxygen vacancies in the metal oxide 230 can be reduced, and the normally-on state of the transistor can be suppressed.

As the insulator 254, for example, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. Note that as the insulator containing oxides of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.

The insulator 224, the insulator 250, and the metal oxide 230 are covered with the insulator 254 having a barrier property against hydrogen; and isolated from the insulator 250 . This can prevent impurities such as hydrogen from entering the transistor 200A from the outside, so that the transistor 200A can have good electrical characteristics and reliability.

The insulator 280 is provided over the insulator 224 , the metal oxide 230 , and the conductor 242 with the insulator 254 interposed therebetween. For example, the insulator 280 is formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or the like. It is preferable to have In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies is preferable because a region containing oxygen that is released by heating can be easily formed.

It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Also, the upper surface of the insulator 280 may be flattened.

Like the insulator 214 and the like, the insulator 274 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 280 from above. As the insulator 274, an insulator that can be used for the insulator 214, the insulator 254, or the like may be used, for example.

An insulator 281 functioning as an interlayer film is preferably provided over the insulator 274 . As with the insulator 224 and the like, the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

In addition, the conductors 240 a and 240 b are arranged in openings formed in the insulators 281 , 274 , 280 , and 254 . The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240 a and 240 b may be flush with the top surface of the insulator 281 .

Note that the insulator 241a is provided in contact with the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and the first conductor of the conductor 240a is formed in contact with the side surface of the insulator 241a. ing. A conductor 242a is positioned at least part of the bottom of the opening, and the conductor 240a is in contact with the conductor 242a. Similarly, the insulator 241b is provided in contact with the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and the first conductor of the conductor 240b is formed in contact with the side surface of the insulator 241b. It is A conductor 242b is positioned at least part of the bottom of the opening, and the conductor 240b is in contact with the conductor 242b.

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductors 240a and 240b. Further, the conductor 240a and the conductor 240b may have a laminated structure.

In the case where the conductor 240 has a stacked structure, the conductors in contact with the metal oxide 230a, the metal oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281 include the above-described conductors. It is preferable to use a conductor having a function of suppressing diffusion of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Further, the conductive material having a function of suppressing diffusion of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, oxygen added to the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b. Further, impurities such as water or hydrogen from a layer above the insulator 281 can be prevented from entering the metal oxide 230 through the conductors 240a and 240b.

As the insulators 241a and 241b, an insulator that can be used for the insulator 254 or the like may be used, for example. Since the insulators 241a and 241b are provided in contact with the insulator 254, impurities such as water or hydrogen from the insulator 280 or the like are prevented from entering the metal oxide 230 through the conductors 240a and 240b. can do. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

Further, although not illustrated, a conductor functioning as a wiring may be arranged in contact with the top surface of the conductor 240a and the top surface of the conductor 240b. A conductive material containing tungsten, copper, or aluminum as a main component is preferably used for the conductor functioning as the wiring. Further, the conductor may have a layered structure, for example, a layered structure of titanium, titanium nitride, and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator.

<Structure Example 2 of Transistor>
38A, 38B, and 38C are a top view and a cross-sectional view of a transistor 200B that can be used in a display device that is one embodiment of the present invention, and the periphery of the transistor 200B. Transistor 200B is a modification of transistor 200A.

FIG. 38A is a top view of the transistor 200B. 38B and 38C are cross-sectional views of the transistor 200B. Here, FIG. 38B is a cross-sectional view of the portion indicated by the dashed-dotted line B1-B2 in FIG. 38A, and is also a cross-sectional view in the channel length direction of the transistor 200B. FIG. 38C is a cross-sectional view of the portion indicated by the dashed-dotted line B3-B4 in FIG. 38A, and is also a cross-sectional view in the channel width direction of the transistor 200B. Note that in the top view of FIG. 38A, some elements are omitted for clarity of illustration.

In transistor 200B, conductors 242a and 242b have regions that overlap with metal oxide 230c, insulator 250, and conductor 260. FIG. Accordingly, the transistor 200B can have a high on-state current. Also, the transistor 200B can be a transistor that is easy to control.

A conductor 260 functioning as a gate electrode has a conductor 260a and a conductor 260b over the conductor 260a. For the conductor 260a, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) is preferably used.

Since the conductor 260a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 260b can be improved. In other words, with the presence of the conductor 260a, oxidation of the conductor 260b is suppressed, and a decrease in conductivity can be prevented.

Further, an insulator 254 is preferably provided so as to cover the top and side surfaces of the conductor 260, the side surfaces of the insulator 250, and the side surfaces of the metal oxide 230c. Note that an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used for the insulator 254 .

By providing the insulator 254, oxidation of the conductor 260 can be suppressed. In addition, with the insulator 254, impurities such as water and hydrogen contained in the insulator 280 can be prevented from diffusing into the transistor 200B.

<Structure Example 3 of Transistor>
39A, 39B, and 39C are a top view and a cross-sectional view of a transistor 200C that can be used in a display device that is one embodiment of the present invention, and the periphery of the transistor 200C. Transistor 200C is a modification of transistor 200A.

FIG. 39A is a top view of the transistor 200C. 39B and 39C are cross-sectional views of the transistor 200C. Here, FIG. 39B is a cross-sectional view of the portion indicated by the dashed-dotted line C1-C2 in FIG. 39A, and is also a cross-sectional view in the channel length direction of the transistor 200C. FIG. 39C is a cross-sectional view of the portion indicated by the dashed-dotted line C3-C4 in FIG. 39A, and is also a cross-sectional view in the channel width direction of the transistor 200C. Note that in the top view of FIG. 39A, some elements are omitted for clarity of illustration.

The transistor 200C has an insulator 250 over the metal oxide 230c and a metal oxide 252 over the insulator 250c. A conductor 260 is provided over the metal oxide 252 and an insulator 270 is provided over the conductor 260 . An insulator 271 is provided over the insulator 270 .

The metal oxide 252 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 252 that suppresses diffusion of oxygen between the insulator 250 and the conductor 260, diffusion of oxygen to the conductor 260 is suppressed. In other words, reduction in the amount of oxygen supplied to the metal oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen can be suppressed.

Note that the metal oxide 252 may function as part of the gate electrode. For example, an oxide semiconductor that can be used as the metal oxide 230 can be used as the metal oxide 252 . In that case, by forming the conductor 260 by a sputtering method, the electric resistance value of the metal oxide 252 can be lowered and the metal oxide 252 can be a conductor. This can be called an OC (Oxide Conductor) electrode.

Metal oxide 252 may also function as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide 252 is preferably a high-k material with a high dielectric constant. By using the laminated structure, a laminated structure that is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as a gate insulator.

Although the metal oxide 252 is shown as a single layer in the transistor 200C, it may have a stacked structure of two or more layers. For example, a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulator may be stacked.

When the metal oxide 252 functions as a gate electrode, the on-state current of the transistor 200C can be improved without weakening the influence of the electric field from the conductor 260 . Alternatively, when acting as a gate insulator, the physical thicknesses of insulator 250 and metal oxide 252 maintain a distance between conductor 260 and metal oxide 230 to keep conductor 260 and metal oxide 230 apart. Leakage current with the oxide 230 can be suppressed. Therefore, by providing the stacked structure of the insulator 250 and the metal oxide 252, the physical distance between the conductor 260 and the metal oxide 230 and the electric field intensity applied from the conductor 260 to the metal oxide 230 can be reduced. , can be easily adjusted.

Specifically, as the metal oxide 252, a low-resistance oxide semiconductor that can be used for the metal oxide 230 can be used. Alternatively, metal oxides containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulating layer containing oxides of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to be crystallized in heat treatment in a later step. Note that the metal oxide 252 is not an essential component. It may be appropriately designed depending on the required transistor characteristics.

For the insulator 270, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, aluminum oxide, hafnium oxide, or the like is preferably used. Accordingly, oxidation of the conductor 260 by oxygen from above the insulator 270 can be suppressed. In addition, impurities such as water or hydrogen from above the insulator 270 can be prevented from entering the metal oxide 230 through the conductor 260 and the insulator 250 .

Insulator 271 functions as a hard mask. By providing the insulator 271, when the conductor 260 is processed, the side surface of the conductor 260 is substantially vertical. Preferably, it can be 80 degrees or more and 95 degrees or less.

Note that the insulator 271 may also function as a barrier layer by using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 270 may not be provided.

Using the insulator 271 as a hard mask, the insulator 270, the conductor 260, the metal oxide 252, the insulator 250, and part of the metal oxide 230c are selectively removed so that their sides are substantially flush. and expose a portion of the metal oxide 230b surface.

Transistor 200C also has region 243a and region 243b on a portion of the exposed metal oxide 230b surface. One of region 243a or region 243b functions as a source region and the other of region 243a or region 243b functions as a drain region.

The regions 243a and 243b are formed by, for example, introducing an impurity element such as phosphorus or boron into the exposed surface of the metal oxide 230b by ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. It can be realized by In this embodiment and the like, "impurity element" refers to an element other than the main component element.

Further, a metal film is formed after part of the surface of the metal oxide 230b is exposed, and then heat treatment is performed to diffuse an element contained in the metal film into the metal oxide 230b, thereby forming the regions 243a and 243b. can also be formed.

A region of the metal oxide 230b into which the impurity element is introduced has a lower electrical resistivity. Therefore, the regions 243a and 243b are sometimes referred to as "impurity regions" or "low resistance regions".

By using the insulator 271 and/or the conductor 260 as a mask, the regions 243a and 243b can be formed in a self-aligned manner. Therefore, the region 243a and/or the region 243b does not overlap with the conductor 260, and parasitic capacitance can be reduced. Also, no offset region is formed between the channel forming region and the source/drain region (region 243a or region 243b). By forming the regions 243a and 243b in a self-aligned manner, it is possible to increase the ON current, reduce the threshold voltage, and improve the operating frequency.

The transistor 200C includes the insulator 271, the insulator 270, the conductor 260, the metal oxide 252, the insulator 250, and the insulator 272 on the side surface of the metal oxide 230c. The insulator 272 is preferably an insulator with a low dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, resin, or the like. Preferably. In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having vacancies for the insulator 272 because an excess oxygen region can be easily formed in the insulator 272 in a later step. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. Further, the insulator 272 preferably has a function of diffusing oxygen.

Note that an offset region may be provided between the channel formation region and the source/drain region in order to further reduce the off current. The offset region is a region having a high electric resistivity, and is a region where the above-described impurity element is not introduced. The formation of the offset region can be achieved by introducing the above-described impurity element after the insulator 272 is formed. In this case, the insulator 272 also functions as a mask like the insulator 271 and the like. Therefore, an impurity element is not introduced into a region of the metal oxide 230b overlapping with the insulator 272, and the electrical resistivity of the region can be kept high.

In addition, the transistor 200C has the insulator 272 and the insulator 254 over the metal oxide 230 . The insulator 254 is preferably deposited using a sputtering method. By using a sputtering method, an insulator containing few impurities such as water or hydrogen can be formed.

Note that an oxide film formed by sputtering may extract hydrogen from a structure to be formed. Therefore, the insulator 254 absorbs hydrogen and water from the metal oxide 230 and the insulator 272, so that the hydrogen concentrations in the metal oxide 230 and the insulator 272 can be reduced.

<Materials Constituting Transistors>
A constituent material that can be used for a transistor is described.

<<Substrate>>
As a substrate for forming the transistor 200, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. Examples of insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized zirconia substrates, etc.), resin substrates, and the like. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are a substrate including a metal nitride, a substrate including a metal oxide, and the like. Furthermore, there are a substrate in which an insulator substrate is provided with a conductor or a semiconductor, a substrate in which a semiconductor substrate is provided with a conductor or an insulator, a substrate in which a conductor substrate is provided with a semiconductor or an insulator, and the like. Alternatively, those substrates provided with elements may be used. Elements provided on the substrate include a capacitive element, a resistance element, a switch element, a light emitting element, a memory element, and the like.

<<insulator>>
As insulators, oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, metal oxynitrides, and the like having insulating properties are given.

For example, as transistors are miniaturized and highly integrated, thinning of gate insulators may cause problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material should be selected according to the function of the insulator.

Insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and silicon and hafnium. oxynitrides containing silicon, or nitrides containing silicon and hafnium.

Insulators with a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and air. There are silicon oxide with pores, resin, and the like.

A transistor including an oxide semiconductor is surrounded by an insulator (such as the insulator 214, the insulator 222, the insulator 254, and the insulator 274) which has a function of suppressing permeation of impurities such as hydrogen and oxygen. , the electrical characteristics of the transistor can be stabilized. Examples of insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. A single layer or stack of insulators including lanthanum, neodymium, hafnium, or tantalum may be used. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Alternatively, a metal oxide such as tantalum oxide, or a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.

An insulator that functions as a gate insulator preferably has a region containing oxygen that is released by heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be compensated.

<< Conductor >>
Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from among the above, an alloy containing the above-described metal elements as a component, or an alloy or the like in which the above-described metal elements are combined. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, and the like are used. is preferred. Also, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even after absorbing oxygen. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

Alternatively, a plurality of conductors formed using any of the above materials may be stacked and used. For example, a laminated structure in which the material containing the metal element described above and the conductive material containing oxygen are combined may be used. Alternatively, a laminated structure may be employed in which the material containing the metal element described above and the conductive material containing nitrogen are combined. Alternatively, a laminated structure may be employed in which the material containing the metal element described above, the conductive material containing oxygen, and the conductive material containing nitrogen are combined.

Note that in the case where a metal oxide is used for a channel formation region of a transistor, a conductor functioning as a gate electrode has a stacked-layer structure in which a material containing the above metal element and a conductive material containing oxygen are combined. is preferred. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

In particular, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as a conductor functioning as a gate electrode. Alternatively, a conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed can be captured in some cases. Alternatively, it may be possible to capture hydrogen that enters from the outer insulator or the like.

<<metal oxide>>

The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

Consider here the case where the metal oxide is an In--M--Zn oxide with indium, the element M and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above elements may be combined.

In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[Structure of Metal Oxide]
Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include, for example, CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductors), pseudo-amorphous oxide semiconductors (a-like (OS: amorphous-like oxide semiconductor), amorphous oxide semiconductor, and the like.

[impurities]
Here, the effect of each impurity in the metal oxide will be described.

Further, if the metal oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed to generate carriers. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region tends to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS (concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry)) is 1×10 ¹⁸ atoms. /cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons, which are carriers, are generated in some cases. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor using a metal oxide containing hydrogen tends to have normally-on characteristics.

Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm Less than ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ . By using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted.

A highly crystalline thin film is preferably used as a metal oxide used for a semiconductor of a transistor. By using the thin film, the stability or reliability of the transistor can be improved. The thin film includes, for example, a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, a high temperature or laser heating process is required to form a single crystal metal oxide thin film or a polycrystalline metal oxide thin film on a substrate. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.

At least a part of the structural examples and the drawings corresponding to them in this embodiment can be combined with other structural examples, drawings, and the like as appropriate.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 3)
In this embodiment mode, a display device including the transistor 200A shown in FIGS.

By using the transistor 200A as a transistor included in the display device, the transistor can be miniaturized. As a result, the definition of the display device can be increased. For example, the pixel density can be 2000 ppi or higher. Alternatively, the pixel density can be 5000 ppi or higher.

FIG. 40 is a block diagram illustrating a configuration example of a display device 800 which is a display device of one embodiment of the present invention. The display device 10 has a display portion 801 , a gate driver circuit 803 a , a gate driver circuit 803 b , and a source driver circuit 804 . Pixels 802 are provided in a matrix in the display portion 801 . The gate driver circuits 803a and 803b each have a shift register circuit SR.

The gate driver circuit 803a, the gate driver circuit 803b, and the source driver circuit 804 may be built-in type or external type. For example, the gate driver circuits 803a and 803b can be built-in, and the source driver circuit 804 can be external.

The pixels 802 in the same row are electrically connected to the gate driver circuit 803a or the gate driver circuit 803b through a wiring 805. FIG. Pixels 802 in the same column are electrically connected to a source driver circuit 804 through wirings 806 . The wiring 805 functions as a scanning line, and the wiring 806 functions as a data line.

Here, the gate driver circuit 803a can be electrically connected to, for example, the odd-numbered pixels 802, and the gate driver circuit 803b can be electrically connected to, for example, the even-numbered pixels 802. .

Note that although FIG. 40 illustrates a structure in which one pixel 802 is electrically connected to one wiring 805 and one wiring 806, one embodiment of the present invention is not limited to this. For example, one wiring may be electrically connected to two wirings 805 and two wirings 806 . Alternatively, for example, one wiring may be electrically connected to three or more wirings 805 and three or more wirings 806 .

The gate driver circuits 803 a and 803 b have functions of generating signals for controlling the operation of the pixels 802 and supplying the signals to the pixels 802 through wirings 805 .

By providing a plurality of gate driver circuits as shown in FIG. 40, the display device 800 can reduce the number (number of stages) of the shift register circuits SR provided in one gate driver circuit. Thereby, the degree of freedom of layout of the display device 800 can be increased as compared with the case where only one gate driver circuit is provided. Note that the display device 800 may be provided with two source driver circuits.

The source driver circuit 804 has a function of supplying image signals to the pixels 802 through wirings 806 . For example, the source driver circuit 804 has a DA conversion circuit, which can convert a digital image signal into an analog signal and supply the analog signal to the pixels 802 .

The gate driver circuits 803a and 803b can have the same configuration as the gate driver circuit 21 shown in FIG. Here, FIG. 41 shows a configuration example of the shift register circuit SR included in the gate driver circuits 803a and 803b.

A shift register circuit SR having a structure illustrated in FIG. 41 includes transistors 811 to 821 and capacitors 822 to 824 .

One of the source and drain of the transistor 811 is electrically connected to one of the source and drain of the transistor 812 , one of the source and drain of the transistor 816 , and one of the source and drain of the transistor 819 . The gate of the transistor 812 is one of the source and drain of the transistor 813, one of the source and drain of the transistor 814, one of the source and drain of the transistor 815, the gate of the transistor 818, the gate of the transistor 821, and one of the capacitor 822. It is electrically connected with the electrode. The other of the source and drain of the transistor 816 is electrically connected to the gate of the transistor 817 and one electrode of the capacitor 823 . The other of the source and drain of the transistor 819 is electrically connected to the gate of the transistor 820 and one of the source and drain of the capacitor 824 .

A signal LIN is input to the gates of the transistors 811 and 814 . A signal CLK2 is input to the gate of the transistor 813 . A signal RES is input to the gate of the transistor 815 . A signal CLK1 is input to the other of the source and drain of the transistor 817 . A signal PWC is input to one of the source and drain of the transistor 820 .

A signal SROUT is output from the other of the source or drain of the transistor 817 , one of the source or drain of the transistor 818 , and the other electrode of the capacitor 823 . A signal GOUT is output from the other of the source or drain of the transistor 820 , one of the source or drain of the transistor 821 , and the other electrode of the capacitor 824 .

The other of the source and the drain of the transistor 811, the other of the source and the drain of the transistor 813, the other of the source and the drain of the transistor 815, the gate of the transistor 816, and the gate of the transistor 819 are supplied with the potential VDD. The other of the source and the drain of the transistor 812, the other of the source and the drain of the transistor 814, the other of the source and the drain of the transistor 818, the other of the source and the drain of the transistor 821, and the other of the source and the drain of the capacitor 822 have For example, ground potential is supplied.

The signal RES is a reset signal, and by setting the signal RES to a high potential, for example, all the outputs of the shift register circuit SR can be set to a low potential. The signal PWC is a pulse width control signal and has a function of controlling the pulse width of the signal output to the wiring 805 by the shift register circuit SR. Signal CLK1 and signal CLK2 are clock signals.

A signal GOUT is an output signal that is output to the wiring 805 . The signal SROUT is a shift signal, and can be the signal LIN input to the next-stage shift register circuit SR.

The transistors 811 to 821 have gates and bottom gates. The gate of transistor 811 is electrically connected to the bottom gate of transistor 811, the gate of transistor 813 is electrically connected to the bottom gate of transistor 813, and the gate of transistor 815 is electrically connected to the bottom gate of transistor 815. , the gate of transistor 816 is electrically connected to the bottom gate of transistor 816, the gate of transistor 817 is electrically connected to the bottom gate of transistor 817, and the gate of transistor 819 is electrically connected to the bottom gate of transistor 819. and the gate of transistor 820 is electrically connected to the bottom gate of transistor 820 . Accordingly, the on-state currents of the transistors 811, 813, 815, 816, 817, 819, and 820 can be increased.

A signal VBG1 is input to the bottom gate of the transistor 812, the bottom gate of the transistor 818, and the bottom gate of the transistor 821. FIG. A signal VBG2 is input to the bottom gate of the transistor 814 . Accordingly, the potentials of the bottom gates of the transistors 812, 814, 818, and 821 can be controlled independently of the gate potentials. Therefore, the transistor 812, the transistor 814, the transistor 818, and the transistor 821 can have large on-state current and small off-state current.

The pixel 802 can have a structure similar to that of the pixel 34 shown in FIGS. Alternatively, the configuration shown in FIG. 42 can be used. It can be said that the pixel 802 having the configuration shown in FIG. 42 is a pixel having a memory, like the pixel 34 having the configuration shown in FIGS.

A pixel 802 having the configuration shown in FIG. 42 has a layer 830 and a layer 840 that are stacked on top of each other. Layer 840 may be provided below layer 830 . Note that layer 840 may be provided above layer 830 .

A display element 831 , a transistor 832 , a transistor 833 , and a capacitor 834 are provided in the layer 830 . A layer 840 is provided with a transistor 841 , a transistor 842 , and a capacitor 843 . In addition, the pixel 802 having the structure illustrated in FIG. 42 is electrically connected to wirings 805_1 and 805_2 as wirings 805 functioning as scan lines, and wirings 806_1 and 806_2 as wirings 806 functioning as data lines. are electrically connected.

The display element 831, like the light emitting element 572, can be, for example, an EL element, such as an organic EL element.

One of the source and drain of the transistor 832 is electrically connected to the gate of the transistor 833 . A gate of the transistor 833 is electrically connected to one electrode of the capacitor 834 . One of the source and drain of the transistor 833 is electrically connected to the other electrode of the capacitor 834 . The other electrode of the capacitor 834 is electrically connected to one electrode of the display element 831 .

A node to which one of the source and drain of the transistor 832, the gate of the transistor 833, and one electrode of the capacitor 834 are electrically connected is denoted by N11. A node to which one electrode of the display element 831, one of the source and the drain of the transistor 833, and the other electrode of the capacitor 834 are electrically connected is denoted by N12.

The other of the source and drain of the transistor 832 is electrically connected to the wiring 806_2. A gate of the transistor 832 is electrically connected to the wiring 805_2. The other of the source and drain of the transistor 833 is electrically connected to the wiring 835 . The other electrode of the display element 831 is electrically connected to a wiring 836 .

One of the source and drain of the transistor 841 is electrically connected to one electrode of the capacitor 843 . The other electrode of the capacitor 843 is electrically connected to the node N11 included in the layer 830. FIG. One of the source and drain of the transistor 842 is electrically connected to the node N12. Here, the node to which one of the source and drain of the transistor 841 is electrically connected is N13.

The other of the source and the drain of the transistor 841 is electrically connected to the wiring 806_1. A gate of the transistor 841 and a gate of the transistor 842 are electrically connected to the wiring 805_1. The other of the source and drain of the transistor 842 is electrically connected to a wiring 844 . Here, the wiring 844 has a function as a monitor line, and electric characteristics and the like of the display element 831 can be detected by detecting current flowing through the wiring 844 or the like.

By turning off the transistor 832, the pixel 802 can hold the potential of the node N11. By turning off the transistor 841, the potential of the node N13 can be held. Further, by turning off the transistor 832 and writing a predetermined potential to the node N13 through the transistor 841, capacitive coupling through the capacitor 843 causes the potential of the node N11 to change according to the change in the potential of the node N13. can be made

Transistors with low off-state current, such as OS transistors, are preferably used as the transistors 832 and 841 . Accordingly, the potentials of the nodes N11 and N13 can be held for a long time. In addition, OS transistors can be applied to all of the transistors 832 , 833 , 841 , and 842 .

The structure of the OS transistor can be the transistor 200A shown in FIGS. 37A, 37B, and 37C as described above. This allows the display device 800 to have high definition.

In the pixel 802 having the structure shown in FIG. 42, the circuit formed in the layer 830 has the same structure as the structure shown in FIG. 25C. In other words, the layer 830 is provided with elements, elements, and the like that form a minimum required circuit when the display device 800 performs display, and the other elements, elements, and the like are provided in the layer 840. be able to. By using such a stacked structure for the pixel 802, the display device 800 can have high definition even when the number of transistors, capacitors, and the like is increased compared to the structure shown in FIG. be able to.

42 and the transistor 200A shown in FIGS. 37A, 37B, and 37C is used as the transistor included in the display device 800, whereby the pixel 802 provided in the display portion 801 is obtained. pixel density of 2000 ppi or more. Alternatively, the pixel density of the pixels 802 can be 2500 ppi or higher.

FIG. 43 is a timing chart showing an example of the operation method of the pixel 802 having the configuration shown in FIG. 43, the wiring 31_1 is set to the wiring 805_1, the wiring 31_2 to the wiring 805_2, the wiring 32_1 to the wiring 806_1, the wiring 32_2 to the wiring 806_2, the node N1 to the node N13, and the node N2 to the node N11. 26(B).

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 4)
In this embodiment, an electronic device including a display device which is one embodiment of the present invention will be described.

FIG. 44A is a diagram showing the appearance of camera 8000 with finder 8100 attached. The camera 8000 is provided with an imaging device. Camera 8000 may be, for example, a digital camera. Note that in FIG. 44A, the camera 8000 and the viewfinder 8100 are separate electronic devices, and are configured to be detachable. good too.

A camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like. A detachable lens 8006 is attached to the camera 8000 .

Here, the camera 8000 is configured so that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.

The camera 8000 can take an image by pressing the shutter button 8004 . Further, the display portion 8002 has a function as a touch panel, and an image can be captured by touching the display portion 8002 .

A housing 8001 of the camera 8000 has a mount having electrodes, and can be connected to a finder 8100, a strobe device, and the like.

A viewfinder 8100 includes a housing 8101, a display portion 8102, buttons 8103, and the like. Viewfinder 8100 may be an electronic viewfinder.

The housing 8101 has mounts that engage mounts of the camera 8000 so that the viewfinder 8100 can be attached to the camera 8000 . Further, the mount has an electrode, and an image or the like received from the camera 8000 through the electrode can be displayed on the display portion 8102 .

A button 8103 has a function as a power button. A button 8103 can switch on/off of the display on the display portion 8102 .

The display device of one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100 . Since the display device of one embodiment of the present invention has extremely high definition, even if the distance between the display portion 8002 or the display portion 8102 and the user is short, the pixels are not visible to the user, which makes the display more realistic. A vivid image can be displayed on the display portion 8002 or the display portion 8102 . In particular, since an image displayed on a display unit 8102 provided in the viewfinder 8100 is visually recognized by bringing the user's eye closer to the eyepiece of the viewfinder 8100, the distance between the user and the display unit 8102 is large. becomes very close. Therefore, it is particularly preferable to apply the display device of one embodiment of the present invention to the display portion 8102 . Note that in the case where the display device of one embodiment of the present invention is applied to the display portion 8102, the resolution of an image that can be displayed on the display portion 8102 can be 4K, 5K, or higher.

Note that the resolution of the image that can be captured by the imaging device provided in the camera 8000 is preferably equal to or higher than the resolution of the image that can be displayed on the display portion 8002 or the display portion 8102 . For example, when an image with a resolution of 4K can be displayed on the display portion 8102, the camera 8000 is preferably provided with an imaging device capable of capturing an image of 4K or higher. Further, for example, when an image with a resolution of 5K can be displayed on the display portion 8102, the camera 8000 is preferably provided with an imaging device capable of capturing an image of 5K or higher.

FIG. 44B is a diagram showing the appearance of the head mounted display 8200. As shown in FIG.

The head mounted display 8200 has a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205 and the like. A battery 8206 is built in the mounting portion 8201 .

Cable 8205 supplies power from battery 8206 to body 8203 . A main body 8203 includes a wireless receiver or the like, and can display an image corresponding to received image data or the like on the display portion 8204 . In addition, by capturing the movement of the user's eyeballs and eyelids with a camera provided in the main body 8203 and calculating the coordinates of the user's line of sight based on the information, the user's line of sight can be used as an input means. can.

Also, the mounting portion 8201 may be provided with a plurality of electrodes at positions where the user touches. The main body 8203 may have a function of recognizing the line of sight of the user by detecting the current flowing through the electrodes as the user's eyeballs move. It may also have a function of monitoring the user's pulse by detecting the current flowing through the electrode. Moreover, the mounting unit 8201 may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc., and may have a function of displaying the biological information of the user on the display unit 8204 . Alternatively, the movement of the user's head or the like may be detected, and the image displayed on the display unit 8204 may be changed according to the movement.

The display device of one embodiment of the present invention can be applied to the display portion 8204 . Accordingly, the frame of the head-mounted display 8200 can be narrowed, a high-quality image can be displayed on the display portion 8204, and an image with high presence can be displayed. Also, the reliability of the head mounted display 8200 can be improved.

44(C), (D), and (E) are diagrams showing the appearance of the head mounted display 8300. FIG. A head mounted display 8300 includes a housing 8301 , a display portion 8302 , a band-shaped fixture 8304 , and a pair of lenses 8305 .

The user can see the display on the display portion 8302 through the lens 8305 . Note that it is preferable to arrange the display portion 8302 in a curved manner. By arranging the display portion 8302 in a curved manner, the user can feel a high presence. Note that although the structure in which one display portion 8302 is provided is exemplified in this embodiment mode, the present invention is not limited to this and, for example, a structure in which two display portions 8302 are provided may be employed. In this case, if one display unit is arranged for one eye of the user, it is possible to perform three-dimensional display using parallax.

Note that the display device of one embodiment of the present invention can be applied to the display portion 8302 . Since the display device of one embodiment of the present invention has extremely high definition, even when the display device is enlarged using the lens 8305 as shown in FIG. High image can be displayed.

Next, examples of electronic devices different from the electronic devices shown in FIGS. 44A to 44E are shown in FIGS.

The electronic device shown in FIGS. 45A to 45G includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, sensors 9007 (power , displacement, position, speed, acceleration, angular velocity, number of revolutions, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , odor, or infrared measurement), a microphone 9008, and the like.

Electronic devices illustrated in FIGS. 45A to 45G have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date, time, etc., and a function to control processing by various software (programs). , wireless communication function, function to connect to various computer networks using wireless communication function, function to transmit or receive various data using wireless communication function, read programs or data recorded on recording media It can have a function of displaying on a display portion, and the like. Note that the functions that the electronic devices illustrated in FIGS. 45A to 45G can have are not limited to these, and can have various functions. Further, although not shown in FIGS. 45A to 45G, the electronic device may have a structure including a plurality of display portions. In addition, a camera or the like is provided in the electronic device to take still images, to take moving images, to save the shot images in a recording medium (external or built into the camera), and to display the shot images on the display unit. and the like.

Details of the electronic devices shown in FIGS. 45A to 45G are described below.

FIG. 45A is a perspective view showing a television device 9100. FIG. The television apparatus 9100 can incorporate a display 9001 with a large screen, eg, 50 inches or more, or 100 inches or more.

The display device of one embodiment of the present invention can be applied to the display portion 9001 included in the television device 9100 . Accordingly, the frame of the television device 9100 can be narrowed, a high-quality image can be displayed on the display portion 9001, and an image with high presence can be displayed. Also, the reliability of the television device 9100 can be enhanced.

FIG. 45B is a perspective view showing a mobile information terminal 9101. FIG. The mobile information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, notebook, information browsing device, and the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. In addition, the mobile information terminal 9101 can display characters and images on its multiple surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001 . In addition, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display portion 9001 . Examples of the information 9051 include a display that notifies an incoming e-mail, SNS (social networking service), telephone call, etc., the title of the e-mail, SNS, etc., the name of the sender of the e-mail, SNS, etc., the date and time, and the time. , remaining battery power, strength of antenna reception, and the like. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at the position where the information 9051 is displayed.

The display device of one embodiment of the present invention can be applied to the display portion 9001 included in the portable information terminal 9101 . Accordingly, the size of the portable information terminal 9101 can be reduced, and a high-quality image can be displayed on the display portion 9001, so that an image with high presence can be displayed. In addition, reliability of the portable information terminal 9101 can be improved.

FIG. 45C is a perspective view showing a mobile information terminal 9102. FIG. The portable information terminal 9102 has a function of displaying information on three or more sides of the display portion 9001 . Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, the user of the mobile information terminal 9102 can confirm the display (here, information 9053) while the mobile information terminal 9102 is stored in the breast pocket of the clothes. Specifically, the telephone number, name, or the like of the caller of the incoming call is displayed at a position that can be observed from above the portable information terminal 9102 . The user can check the display and determine whether or not to receive the call without taking out the portable information terminal 9102 from the pocket.

The display device of one embodiment of the present invention can be applied to the display portion 9001 included in the portable information terminal 9102 . Accordingly, the size of the portable information terminal 9101 can be reduced, and a high-quality image can be displayed on the display portion 9001, so that an image with high presence can be displayed. In addition, reliability of the portable information terminal 9102 can be improved.

FIG. 45D is a perspective view showing a wristwatch-type portable information terminal 9200. FIG. The personal digital assistant 9200 can run various applications such as mobile phone, e-mail, text viewing and writing, music playback, Internet communication, computer games, and the like. Further, the display portion 9001 has a curved display surface, and display can be performed along the curved display surface. In addition, the mobile information terminal 9200 is capable of performing short-range wireless communication according to communication standards. For example, by intercommunicating with a headset capable of wireless communication, hands-free communication is also possible. In addition, the portable information terminal 9200 has a connection terminal 9006 and can directly exchange data with another information terminal through a connector. Also, charging can be performed through the connection terminal 9006 . Note that the charging operation may be performed by wireless power supply without using the connection terminal 9006 .

The display device of one embodiment of the present invention can be applied to the display portion 9001 included in the portable information terminal 9200 . As a result, the frame of the portable information terminal 9200 can be narrowed, a high-quality image can be displayed on the display portion 9001, and an image with high presence can be displayed. Moreover, the reliability of the portable information terminal 9200 can be improved.

45(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 45E is a perspective view of the portable information terminal 9201 in an unfolded state, and FIG. 45F is a state in which the portable information terminal 9201 is in the process of changing from one of the unfolded state and the folded state to the other. 45(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 has excellent portability in the folded state, and has excellent display visibility due to a seamless wide display area in the unfolded state. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055 . By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly transformed from the unfolded state to the folded state. For example, the mobile information terminal 9201 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

The display device of one embodiment of the present invention can be applied to the display portion 9001 included in the portable information terminal 9201 . Accordingly, the frame of the portable information terminal 9201 can be narrowed, and a high-definition image can be displayed on the display portion 9001, so that an image with high presence can be displayed. In addition, reliability of the portable information terminal 9201 can be improved.

At least a part of the structural examples and the drawings corresponding to them in this embodiment can be combined with other structural examples, drawings, and the like as appropriate.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

Example 1 In this example, results of manufacturing an OS transistor will be described.

In this example, a transistor having a structure similar to that of the transistor 200A shown in FIGS. 37A, 37B, and 37C was manufactured. The transistor had a channel width of 60 nm and a gate insulator thickness of 6 nm in terms of EOT (Equivalent Oxide Thickness). In addition, CAAC-IGZO was used as a semiconductor for forming a channel. CAAC-IGZO was used as a semiconductor for the transistor manufactured in this example. The transistor is a field-effect transistor using CAAC-IGZO as a semiconductor (also referred to as a “CAAC-IGZO transistor”).

46A and 46B show cross-sectional TEM photographs of the transistor manufactured in this example. FIG. 46A is a cross-sectional TEM photograph of the transistor in the channel length direction, and FIG. 46B is a cross-sectional TEM photograph of the transistor in the channel width direction. 46A and 46B show the gate electrode (TGE), gate insulator (TGI), source and drain electrodes (SDE), semiconductor (CAAC-IGZO), and back electrode of the transistor manufactured in this example. A gate insulator (BGI) is shown, as well as a back gate electrode (BGE). Since FIG. 46B is a cross-sectional TEM photograph in the channel width direction passing through the gate electrode and the back gate electrode, the SDE is not shown.

As shown in FIGS. 46A and 46B, it was confirmed that a CAAC-IGZO transistor could be manufactured.

Example 1 In this example, measurement results of electrical characteristics of an OS transistor will be described.

In this example, the drain current-gate voltage characteristics (Id-Vg characteristics) of the OS transistors having the configurations shown in FIGS. and drain current-drain voltage characteristics (Id-Vd characteristics) were measured. The lower measurement limit of the measuring instrument used to measure the current in this example is 1×10 ⁻¹² A.

47A, 47B, and 48 are graphs showing measurement results of electrical characteristics of an OS transistor having a channel length of 60 nm and a channel width of 60 nm. 47A and 48 are graphs showing the measurement results of the Id-Vg characteristics, and FIG. 47B is a graph showing the relationship between the gate current (Ig) and Vg. In the graph shown in FIG. 47A, the solid line indicates the Id-Vg characteristics when Vds is set to 1.2V, and the dotted line indicates the Id-Vg characteristics when Vds is set to 0.1V. The Id-Vg characteristics shown in FIG. 48 were measured with a drain voltage Vd of 4V.

49A, 49B, and 50 are graphs showing measurement results of electrical characteristics of an OS transistor having a channel length of 200 nm and a channel width of 60 nm. FIG. 49A is a graph showing measurement results of Id-Vg characteristics, and FIGS. 49B and 50 are graphs showing measurement results of Id-Vd characteristics. In the graph shown in FIG. 49A, the solid line indicates the Id-Vg characteristics when Vds is set to 1.2V, and the dotted line indicates the Id-Vg characteristics when Vds is set to 0.1V. Further, in the graph shown in FIG. 49B, the solid line indicates the Id-Vd characteristics when the gate potential is 1.7 V, the dashed line indicates the Id-Vd characteristics when the gate potential is 1.0 V, A dotted line indicates the Id-Vd characteristic when the gate potential is 0.8V. Further, the Id-Vd characteristics shown in FIG. 50 were measured with a gate voltage Vg of 3V.

FIGS. 51A and 51B show the Id-Vg characteristics of the OS transistor when two OS transistors having the configurations shown in FIGS. 37A, 37B, and 37C are laminated. It is a graph which shows a measurement result. FIG. 51A shows the Id-Vg characteristics of the OS transistors in the upper layer, and FIG. 51B shows the Id-Vg characteristics of the OS transistors in the lower layer. Here, the channel length and channel width of the OS transistor whose Id-Vg characteristics were measured were 360 nm and 360 nm, respectively. Also, the drain voltage Vd was set to 0.1V or 3.3V.

From FIGS. 47A, 48, 49A, 51A, and 51B, the off current of the OS transistors having the configurations shown in FIGS. , was confirmed to be below the lower measurement limit. Further, from FIG. 47B, it can be seen that if the potential supplied to the gate of the OS transistor having the structures shown in FIGS. was confirmed to be smaller. Further, from FIGS. 49B and 50, it is confirmed that the OS transistors having the structures shown in FIGS. rice field. Further, even when the electrode of the organic EL element is electrically connected to the drain of the OS transistor configured as shown in FIGS. It was confirmed that a current of sufficient magnitude can be passed through the

Example 1 In this example, a gate driver circuit provided in a display device was manufactured, and the results of evaluation by simulation and actual measurement will be described. In addition, a display device including the gate driver circuit is manufactured, and a result of displaying an image is described.

In this example, a gate driver circuit 803a and a gate driver circuit 803b included in the display device 800 were manufactured assuming the display device 800 having the structure shown in FIG. Table 1 shows specifications of the assumed display device 800 . The configurations of the gate driver circuit 803a and the gate driver circuit 803b are shown in FIGS. 16 and 41. FIG. Here, the transistors 811 to 821 are all OS transistors having the structures illustrated in FIGS. Note that the pixels are assumed to have the configuration shown in FIG.

FIG. 52 is a graph showing the passage of time in the output potentials of the gate driver circuits 803a and 803b. Specifically, the solid line graph in FIG. 52 indicates the potential output from the gate driver circuit 803a to the wiring 805 electrically connected to the pixels 802 in the first row. A dotted line graph in FIG. 52 indicates a potential output from the gate driver circuit 803b to the wiring 805 electrically connected to the pixel 802 in the second row.

From FIG. 52, it was confirmed that the fall time of the gate driver circuit is about 240 ns, and the settling time of about 5540 ns can be secured for the source driver circuit.

FIGS. 53A and 53B show measurement results of the gate driver circuit fabricated in this example using an oscilloscope. FIG. 53A shows changes over time in potentials input to the gate driver circuit, and FIG. 53B shows changes over time in potentials output from the gate driver circuit.

It was confirmed from FIGS. 53A and 53B that the fall time was 50 ns. Further, it was confirmed that the gate driver circuit manufactured in this example has a withstand voltage that does not cause an abnormality in operation.

FIG. 54 shows a display result when an image is displayed by the display device 800 having the gate driver circuits 803a and 803b which are the gate driver circuits manufactured in this embodiment. As shown in FIG. 54, it was confirmed that the display device having the gate driver circuit manufactured in this example can display images.

Example 1 In this example, the result of manufacturing a display device and displaying an image will be described.

In this example, a display device 800 having the configuration shown in FIG. 40 was manufactured. Table 2 shows the specifications of the manufactured display device 800 . Here, the pixel 802 included in the display device 800 has the structure shown in FIG. In addition, the transistors 552 and 554 included in the pixel 802 are OS transistors having the structures illustrated in FIGS. Further, the channel lengths of the transistor 552 and the transistor 554 are set to be greater than or equal to 60 nm and less than or equal to 200 nm.

FIGS. 55A and 56A are photographs showing the appearance of the display device 800 manufactured in this example. Here, the pixel 802 included in the display device 800 shown in FIG. 55A has the structure shown in FIG. 25C. A pixel 802 included in the display device 800 shown in FIG. 56A has the structure shown in FIG. 25B.

A “display area” shown in FIGS. 55A and 56A is the display unit 801 . The size of the display portion 801 is 6.14 mm×3.16 mm.

FIG. 55(B) is a photograph showing the "Display Area" shown in FIG. 55(A). FIG. 56(B) is a photograph showing the "Display Area" shown in FIG. 56(A). As shown in FIGS. 55B and 56B, it was confirmed that the display device 800 could display an image even when the pixel density was 5000 ppi or more.

Example 4 In this example, a display device having specifications different from those in Example 4 was manufactured, and the result of displaying an image will be described.

Table 3 shows the specifications of the display device for which the layout was performed in this example.

In this example, the layout of the display device 800 having the configuration shown in FIG. 40 was performed. A pixel 802 included in the display device 800 has a two-layer structure as shown in FIG. Also, although the circuit configuration is similar to that of FIG. 42, a layout of a display device 800 having a pixel 802 having a one-layer structure, ie, a configuration in which all display elements, transistors, and capacitor elements are provided in the same layer, was laid out. Here, the transistors 832, 833, 841, and 842 are all OS transistors having the structures illustrated in FIGS.

Table 4 shows the sizes of the pixels 802 included in the display device 800 that has been laid out. Also, Table 4 shows the pixel density of the display device 800 on which the layout is performed.

As shown in Table 4, when the pixel 802 has a two-layer structure as shown in FIG. 42, the area of the pixel 802 is reduced by about 70% compared to the one-layer structure, and the pixel density is about 1.7. Estimated to be double.

Also, the display device 800 on which the layout was performed was operated by the method shown in FIG. 43 by simulation. FIG. 57 shows the potential of the node N11 and the potential _Vdata when the potential _Vw is 0.0V, 0.5V, 1.0V, 1.5V, 2.0V, 2.5V, or 3.0V. It is a graph showing the relationship. Here, the potential _Vref is set to 0V, and the potential of the wiring 844 functioning as a monitor line is set to 0V. Further, it is assumed that the capacitance value of the capacitor 834 and the capacitance value of the capacitor 843 are equal.

From FIG. 57, the potential V _data is increased regardless of the potential V _w of 0.0 V, 0.5 V, 1.0 V, 1.5 V, 2.0 V, 2.5 V, and 3.0 V. It was confirmed that the potential of the node N11 was increased by doing so.

FIG. 58 shows a display result when an image is displayed by the display device 800 manufactured in this example. As shown in FIG. 58, it was confirmed that the display device 800 can display an image even when the pixel has a two-layer structure and the pixel density is 2000 ppi or more.

Moreover, in this example, the display device 800 was operated by the method shown in FIG. Here, the operation was performed under two conditions by changing the magnitude of the potential V _data . In Condition 1, the potential V _data was equal to the potential V _ref . That is, the potential of the wiring 806_1 in the period T2 is equal to the potential of the wiring 806_1 in the period T1. In Condition 2, the potential V _data was equal to the potential V _w . That is, the potential of the wiring 806_1 in the period T2 is made different from the potential of the wiring 806_1 in the period T1. Note that the potential _Vw under condition 1 and the potential _Vw under condition 2 were made equal.

59A shows an image display result when the display device 800 is operated under condition 1, and FIG. 59B shows an image display result when the display device 800 is operated under condition 2. be. It was confirmed that under condition 2, an image with higher brightness than under condition 1 could be displayed.

FIG. 60 is a graph showing the brightness of light emitted from the pixel 802 for each gradation when the display device 800 is operated by the method shown in FIG. The dotted line graph shows the case where the display device 800 is operated under the condition 1, and the solid line graph shows the case where the display device 800 is operated under the condition 2. FIG. Note that the display device 800 includes, as the pixel 802, a subpixel that emits red (R) light, a subpixel that emits green (G) light, and a subpixel that emits blue (B) light. , the gradation of light emitted from each sub-pixel was made equal. In other words, gray display was performed.

As shown in FIG. 60, it was confirmed that the pixel 802 can emit light with higher luminance under condition 2 than under condition 1 when the gradations are equal.

10 display device 20 layer 21 gate driver circuit 21a gate driver circuit 21b gate driver circuit 22 source driver circuit 22a source driver circuit 22b source driver circuit 23 region 23a region 23b region 23c region 23d region 24 demultiplexer circuit 25 buffer circuit 26a inverter circuit 26b Inverter circuit 26c Inverter circuit 27a Wiring 27b Wiring 27c Wiring 28 Buffer element 28a Buffer element 28b Buffer element 28c Buffer element 29 Wiring 29a Wiring 29b Wiring 29c Wiring 30 Layer 31 Wiring 31_1 Wiring 31_2 Wiring 31a Wiring 31b Wiring 32 Wiring 32_1 Wiring 32_2 Wiring 32a Wiring 32b Wiring 33 Display portion 34 Pixel 35 Wiring 35a Wiring 35b Wiring 43 Buffer circuit 44 Shift register circuit 45 Latch circuit 46 DA conversion circuit 47 Amplifier circuit 50 Interface circuit 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 Transistor 57 Transistor 58 Transistor 59 transistor 60 transistor 61 transistor 62 transistor 63 transistor 64 capacitor 65 capacitor 66 capacitor 67 source follower circuit 70 region 71 transistor 72 transistor 73 dummy transistor 74 region 81 transistor 81a transistor 81b transistor 81c transistor 82 transistor 82a transistor 82b transistor 82c transistor 83 Wiring 83b Wiring 83c Wiring 84 Transistor 84a Transistor 84b Transistor 84c Transistor 85 Transistor 85a Transistor 85b Transistor 85c Transistor 86 Transistor 86a Transistor 86b Transistor 86c Transistor 87 Wiring 87a Wiring 87b Wiring 87c Wiring 88 Wiring 88a Wiring 88b Wiring 88c Wiring 89 Delay circuit 89b Delay circuit 89c Delay circuit 91 Wiring 92 Wiring 93 Transistor 93a Transistor 93b Transistor 93c Transistor 94 Transistor 94a Transistor 94b Transistor 94c Transistor 95 Wiring 96 Wiring 110 Channel formation region 111 Source region 112 Drain region 113 Gate electrode 114 Opening 115 Wiring 116 Opening 117 Wiring 118 Opening 119 Opening 120 Opening 121 Wiring 122 Wiring 123 Wiring 130 Channel forming region 131 Source region 132 Drain region 133 Gate electrode 134 Opening 135 Wiring 136 Opening 137 Wiring 138 Opening 139 Opening 140 Opening 141 Wiring 142 Wiring 143 Wiring 151 Semiconductor 152 Conductor 160 Channel forming region 161 Source region 162 Drain region 163 Gate electrode 164 Opening 165 Wiring 166 Opening 167 Wiring 168 Opening 169 Opening 170 Opening 171 Wiring 172 Wiring 180 Channel forming region 181 Source region 182 Drain region 183 Gate electrode 184 Opening 185 Wiring 186 Opening 187 Wiring 188 Opening 189 Opening 190 Opening 191 Wiring 192 Wiring 200 Transistor 200A Transistor 200B Transistor 200C Transistor 205 Conductor 214 Insulator 216 Insulator 222 Insulator 224 Insulator 230 Metal oxide 230a Metal oxide 230b Metal oxide 230c Metal oxide 240 Conductor 240a Conductor 240b Conductor 241 Insulator 241a Insulator 241b Insulator 242 Conductor 242a Conductor 242b Conductor 243a Region 243b region 244 insulator 250 insulator 252 metal oxide 254 insulator 260 conductor 260a conductor 260b conductor 270 insulator 271 insulator 272 insulator 274 insulator 280 insulator 281 insulator 301a conductor 301b conductor 305 conductor Body 311 Conductor 313 Conductor 317 Conductor 321 Lower electrode 323 Insulator 325 Upper electrode 331 Conductor 333 Conductor 335 Conductor 337 Conductor 341 Conductor 343 Conductor 347 Conductor 351 Conductor 353 Conductor 355 Conductor 357 Conductor 361 Insulator 363 Insulator 401 Circuit 403 Element isolation layer 405 Insulator 407 Insulator 409 Insulator 411 Insulator 413 Insulator 415 Insulator 417 Insulator 419 Insulator 421 Insulator 441 Transistor 443 Conductor 445 Insulator 447 Semiconductor region 449a Low-resistance region 449b Low-resistance region 451 Conductor 453 Conductor 455 Conductor 457 Conductor 459 Conductor 461 Conductor 463 Conductor 465 Conductor 467 Conductor 469 Conductor 471 Conductor 501 Insulator 503 Insulator 505 insulator 507 insulator 509 insulator 511 transistor 513 transistor 515 capacitor 517 capacitor 520 circuit 521 transistor 525 transistor 527 transistor 531 wiring 533 wiring 535 wiring 537 wiring 539 wiring 541 wiring 543 wiring 545 wiring 550 transistor 552 transistor 554 transistor 560 capacitance Element 562 Capacitive element 570 Liquid crystal element 572 Light-emitting element 601 Transistor 602 Transistor 603 Transistor 613 Insulator 614 Insulator 616 Insulator 622 Insulator 624 Insulator 644 Insulator 654 Insulator 674 Insulator 680 Insulator 681 Insulator 701 Substrate 705 Substrate 712 sealing material 716 FPC
721 hole-injection layer 722 hole-transport layer 723 light-emitting layer 724 electron-transport layer 725 electron-injection layer 730 insulator 732 sealing layer 734 insulator 736 colored layer 738 light-shielding layer 750 transistor 760 connection electrode 772 conductor 774 conductor 776 liquid crystal Layer 778 Structure 780 Anisotropic Conductor 786 EL Layer 786a EL Layer 786b EL Layer 786c EL Layer 788 Conductor 790 Capacitor 792 Charge Generation Layer 800 Display Device 801 Display Portion 802 Pixel 803a Gate Driver Circuit 803b Gate Driver Circuit 804 Source Driver circuit 805 wiring 805_1 wiring 805_2 wiring 806 wiring 806_1 wiring 806_2 wiring 811 transistor 812 transistor 813 transistor 814 transistor 815 transistor 816 transistor 817 transistor 818 transistor 819 transistor 820 transistor 821 transistor 822 capacitor 823 capacitor 824 capacitor 830 layer 831 display element 832 transistor 833 transistor 834 capacitor 835 wiring 836 wiring 840 layer 841 transistor 842 transistor 843 capacitor 844 wiring 8000 camera 8001 housing 8002 display unit 8003 operation button 8004 shutter button 8006 lens 8100 viewfinder 8101 housing 8102 display unit 8103 button 8200 head Mount display 8201 Mounting unit 8202 Lens 8203 Main body 8204 Display unit 8205 Cable 8206 Battery 8300 Head mount display 8301 Housing 8302 Display unit 8304 Fixing tool 8305 Lens 9000 Housing 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 90 50 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television device 9101 Mobile information terminal 9102 Mobile information terminal 9200 Mobile information terminal 9201 Mobile information terminal

Claims (15)

A display device in which a first layer and a second layer are laminated,
The first layer is provided with an interface circuit, a buffer element, and a source driver circuit,
The second layer has a display section,
Pixels are arranged in a matrix in the display unit,
The buffer element has a region overlapping with the pixel,
The source driver circuit has a region overlapping with the pixel,
The source driver circuit has a buffer circuit,
an output terminal of the buffer element is electrically connected to an input terminal of the buffer circuit;
the interface circuit is electrically connected to an input terminal of the buffer element;
The display device, wherein the output terminal of the buffer element is electrically connected to the source driver circuit. In claim 1 ,
the buffer element has a first transistor, a second transistor, and a third transistor;
the source driver circuit is electrically connected to one of the source or drain of the first transistor and one of the source or drain of the second transistor;
the other of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor;
The display device, wherein the gate of the second transistor is electrically connected to the interface circuit. In claim 1 or 2 ,
the first layer having gate driver circuitry;
The gate driver circuit has a region overlapping with the pixel,
The display device, wherein the gate driver circuit has a region overlapping with the source driver circuit. In claim 3 ,
The display device, wherein the buffer element is provided in the region where the gate driver circuit and the source driver circuit overlap. In any one of claims 1 to 4 ,
the pixel has a transistor having a metal oxide in a channel formation region;
The display device, wherein the metal oxide includes an element M (M is Al, Ga, Y, or Sn) and Zn. an interface circuit, a first buffer element, a second buffer element, a third buffer element, a first source driver circuit, and a second source driver circuit;
the interface circuit is electrically connected to the input terminal of the first buffer element and the input terminal of the second buffer element;
an output terminal of the first buffer element is electrically connected to the first source driver circuit;
the output terminal of the second buffer element is electrically connected to the input terminal of the third buffer element;
The display device, wherein the output terminal of the third buffer element is electrically connected to the second source driver circuit. In claim 6 ,
The display device has a first gate driver circuit and a second gate driver circuit,
The first gate driver circuit has a region overlapping with the first source driver circuit,
The display device, wherein the second gate driver circuit has a region overlapping with the second source driver circuit. In claim 7 ,
the first buffer element and the second buffer element are provided in the region where the first gate driver circuit and the first source driver circuit overlap;
The display device, wherein the third buffer element is provided in the region where the second gate driver circuit and the second source driver circuit overlap. A display device in which a first layer and a second layer are laminated,
The first layer includes an interface circuit, a first buffer element, a second buffer element, a third buffer element, a first source driver circuit, and a second source driver circuit. be
The second layer has a first display section and a second display section,
In the first display section, first pixels are arranged in a matrix,
second pixels are arranged in a matrix in the second display unit,
the first buffer element has a region overlapping with the first pixel;
the second buffer element has a region overlapping with the first pixel;
the first source driver circuit has a region overlapping with the first pixel;
the third buffer element has a region overlapping with the second pixel;
the second source driver circuit has a region overlapping with the second pixel;
the interface circuit is electrically connected to the input terminal of the first buffer element and the input terminal of the second buffer element;
an output terminal of the first buffer element is electrically connected to the first source driver circuit;
the output terminal of the second buffer element is electrically connected to the input terminal of the third buffer element;
The display device, wherein the output terminal of the third buffer element is electrically connected to the second source driver circuit. In claim 9 ,
the first layer has a first gate driver circuit and a second gate driver circuit;
The first gate driver circuit has a region overlapping with the first pixel,
the second gate driver circuit has a region overlapping with the second pixel;
The first gate driver circuit has a region overlapping with the first source driver circuit,
The display device, wherein the second gate driver circuit has a region overlapping with the second source driver circuit. In claim 10 ,
the first buffer element and the second buffer element are provided in the region where the first gate driver circuit and the first source driver circuit overlap;
The display device, wherein the third buffer element is provided in the region where the second gate driver circuit and the second source driver circuit overlap. In any one of claims 9 to 11 ,
the first pixel and the second pixel each have a transistor having a metal oxide in a channel formation region;
The display device, wherein the metal oxide includes an element M (M is Al, Ga, Y, or Sn) and Zn. In any one of claims 6 to 12 ,
The first source driver circuit has a first buffer circuit,
The second source driver circuit has a second buffer circuit,
the output terminal of the first buffer element is electrically connected to the input terminal of the first buffer circuit;
The display device, wherein the output terminal of the third buffer element is electrically connected to the input terminal of the second buffer circuit. In any one of claims 6 to 13 ,
the first buffer element has a first transistor, a second transistor, and a third transistor;
the first source driver circuit is electrically connected to one of the source or drain of the first transistor and one of the source or drain of the second transistor;
the other of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor;
a gate of the second transistor electrically connected to the interface circuit;
the second buffer element has a fourth transistor, a fifth transistor, and a sixth transistor;
one of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the fifth transistor;
the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor;
a gate of the fifth transistor is electrically connected to the interface circuit;
the third buffer element has a seventh transistor, an eighth transistor, and a ninth transistor;
the second source driver circuit is electrically connected to one of the source or drain of the seventh transistor and one of the source or drain of the eighth transistor;
the gate of the seventh transistor is electrically connected to the gate of the fourth transistor;
the other of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the ninth transistor;
The display device, wherein the gate of the eighth transistor is electrically connected to one of the source and the drain of the fourth transistor. a display device according to any one of claims 1 to 14 ;
An electronic device having a lens.

Images