JP7304732B2 - monitoring device - Google Patents

Description

The invention disclosed herein relates to monitoring devices.

2. Description of the Related Art In recent years, monitoring devices (so-called monitoring ICs) that monitor various voltages, clock signals, and the like and detect abnormalities thereof have been used in various applications.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

WO2013/084277

However, the above-described conventional monitoring device has room for further improvement in improving its failure detection rate.

In recent years, in particular, in-vehicle ICs are required to comply with ISO26262 (an international standard for functional safety related to electrical and electronic components of automobiles). Reliability design is important.

An object of the invention disclosed in the present specification is to provide a monitoring device with a high failure detection rate in view of the above-described problems found by the inventors of the present application.

The monitoring device disclosed in this specification includes a monitoring unit that detects an abnormality in a monitored object, a self-diagnostic unit that diagnoses whether the monitoring unit is normal, and the monitoring unit that is operated by the self-diagnostic unit. and a sub-monitoring unit that substitutes for the monitoring unit and detects an abnormality in the monitoring object during the diagnosis (first configuration).

In addition, in the monitoring device having the first configuration, the sub-monitoring unit substitutes for the monitoring unit when the monitoring unit is diagnosed as not normal (the first 2 configuration).

Further, in the monitoring device having the first or second configuration, the sub-monitoring unit sequentially replaces the monitoring unit that is being diagnosed among the plurality of monitoring units provided for each of the plurality of monitoring targets ( 3rd configuration).

Further, in the monitoring device having any one of the first to third configurations, the self-diagnosis unit diagnoses whether or not the sub-monitoring unit is normal during operation of the monitoring unit (fourth configuration).

Further, the monitoring device having any one of the first to fourth configurations includes: an output signal generation section that receives an input signal from the monitoring section and generates an output signal; and a second self-diagnostic unit for diagnosing whether the output signal generating unit is normal by inputting to and determining the expected value of the output signal (fifth configuration). .

The monitoring device having the fifth configuration includes a transistor whose drain or collector is connected to a signal output terminal, and a multiplexer that outputs one of the output signal and the test output signal to the transistor in response to an output switching signal. , and an interface for receiving an external input of the output switching signal and the test output signal (sixth configuration).

Further, the monitoring apparatus disclosed in this specification includes a monitoring unit that detects anomalies in a monitored object, an output signal generation unit that receives an input signal from the monitoring unit and generates an output signal, and a test of a predetermined pattern. A configuration having a self-diagnosis unit that diagnoses whether the output signal generation unit is normal by inputting an input signal to the output signal generation unit and determining the expected value of the output signal (a seventh configuration).

Further, the monitoring device disclosed in this specification includes a monitoring unit that detects an abnormality in a monitored object, an output signal generation unit that receives an input signal from the monitoring unit and generates an output signal, and a drain or a collector. A transistor connected to a signal output terminal, a multiplexer for outputting one of the output signal and the test output signal to the transistor according to an output switching signal, and an interface for receiving an external input of the output switching signal and the test output signal. and (eighth configuration).

Further, the electronic equipment disclosed in this specification has a configuration (ninth configuration) having a monitoring device having any one of the first to eighth configurations.

Further, the vehicle disclosed in this specification has a configuration (tenth configuration) having the electronic device having the above ninth configuration.

According to the invention disclosed in this specification, it is possible to provide a monitoring device with a high failure detection rate.

Diagram showing the overall configuration of an electronic device Diagram showing the package appearance of the monitoring IC Diagram showing pin arrangement of monitoring IC The figure which shows 1st Embodiment of monitoring IC A diagram showing a configuration example of a test circuit A diagram showing an example of diagnostic operation in the first embodiment. The figure which shows 2nd Embodiment of monitoring IC A diagram showing an example of diagnostic operation in the second embodiment. The figure which shows 3rd Embodiment of monitoring IC Diagram showing an example of reset output operation A diagram showing an example of diagnostic operation in the third embodiment. The figure which shows 4th Embodiment of monitoring IC A diagram showing an example of diagnostic operation in the fourth embodiment. External view of vehicle

<Electronic equipment>
FIG. 1 is a diagram showing the overall configuration of an electronic device. The electronic device 1 of this configuration example has a monitoring IC 100 , a power management IC 200 , and a microcomputer 300 . The electronic device 1 also includes resistors R1 to R10 and R12 to R16 and capacitors C1 and C2 as discrete components externally attached to the semiconductor devices 100 to 300 described above.

The monitoring IC 100 is a semiconductor integrated circuit device that operates by receiving supply of the power supply voltage VDD (=output voltage VO1) from the power management IC 200. The monitoring IC 100 monitors various output voltages of the power management IC 200 and the output frequency of the microcomputer 300 and monitors them. anomaly detection. The monitor IC 100 has a plurality of external terminals (VDD pin, GND pin, CT pin, MISO pin, MOSI pin, SCLK pin, XSCS pin, WDIN pin, DIN1 ∼ DIN4 pins, PG1 to PG4 pins, XRSTIN pin, and XRSTOUT pin).

The power management IC 200 is a semiconductor integrated circuit device that operates by receiving the supply of the battery voltage VBAT, generates a plurality of output voltages VO1 to VO5, and supplies them to each part of the electronic device 1. FIG. It is also possible to use a plurality of single-output DC/DC converters or LDO [low drop-out] regulators instead of the multi-output power management IC 200 .

The microcomputer 300 is a semiconductor integrated circuit device that operates by receiving power supply voltage VDD (=output voltage VO1) from the power management IC 200, and controls overall operation of the electronic device 1 including the monitoring IC 100 and the power management IC 200. do.

The microcomputer 300 is reset by a reset output signal XRSTOUT input from the monitoring IC 100. FIG. More specifically, the microcomputer 300 is in a reset state (=disabled state) when the reset output signal XRSTOUT is at low level, and is in a reset release state (=enabled state) when the reset output signal XRSTOUT is at high level. ).

In addition, the microcomputer 300 determines whether the output voltage VOx of the power management IC 200 is normal according to the logic level of the power good signal PGx (where x=1, 2, 3, and 4; the same applies hereinafter) input from the monitoring IC 100. It has a function to determine whether or not More specifically, the microcomputer 300 determines that the output voltage VOx is normal when the power good signal PGx is at high level, and determines that the output voltage VOx is abnormal (when the power good signal PGx is at low level). For example, it is determined that there is an overvoltage abnormality or a low voltage abnormality).

The microcomputer 300 also has a function of outputting a watchdog input signal WDIN (=reset pulse signal of several tens of Hz) to the WDIN pin of the monitoring IC 100 .

The monitoring IC 100 and the microcomputer 300 each have a function of performing bidirectional communication via an SPI [serial peripheral interface] bus, with the microcomputer 300 as a master and the monitoring IC 100 as a slave. For example, the microcomputer 300 has a function of controlling the oscillation frequency of the oscillator and enabling control of the watchdog timer by register control of the monitoring IC 100 through SPI communication. The microcomputer 300 also has a function of determining whether the set value to which the microcomputer 300 has instructed to write matches the stored value read from the monitoring IC 100 for the watchdog enable register.

The resistors R1 and R2 are connected in series between the output terminal of the output voltage VO1 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO1. A connection node between the resistors R1 and R2 (=the output terminal of the voltage dividing circuit) is connected to the XRSTIN pin of the monitoring IC 100. FIG.

The resistors R3 and R4 are connected in series between the output terminal of the output voltage VO2 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO2. A connection node between the resistors R3 and R4 (=the output terminal of the voltage dividing circuit) is connected to the DIN1 pin of the monitoring IC 100. FIG.

The resistors R5 and R6 are connected in series between the output terminal of the output voltage VO3 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO3. A connection node between the resistors R5 and R6 (=the output end of the voltage dividing circuit) is connected to the DIN2 pin of the monitor IC100.

The resistors R7 and R8 are connected in series between the output terminal of the output voltage VO4 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO4. A connection node between the resistors R7 and R8 (=the output terminal of the voltage dividing circuit) is connected to the DIN3 pin of the monitor IC100.

The resistors R9 and R10 are connected in series between the output terminal of the output voltage VO5 and the ground terminal, and function as a voltage dividing circuit for the output voltage VO5. A connection node between the resistors R9 and R10 (=the output end of the voltage dividing circuit) is connected to the DIN4 pin of the monitor IC100.

The resistor R12 is connected between the XRSTOUT pin of the monitoring IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the reset output signal XRSTOUT from the monitoring IC 100 to the microcomputer 300 to the power supply voltage VDD.

The resistor R13 is connected between the PG1 pin of the monitoring IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the power good signal PG1 from the monitoring IC 100 to the microcomputer 300 to the power supply voltage VDD.

The resistor R14 is connected between the PG2 pin of the monitoring IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the power good signal PG2 from the monitoring IC 100 to the microcomputer 300 to the power supply voltage VDD.

The resistor R15 is connected between the PG3 pin of the monitoring IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the power good signal PG3 from the monitoring IC 100 to the microcomputer 300 to the power supply voltage VDD.

The resistor R16 is connected between the PG4 pin of the monitor IC 100 and the power supply terminal, and functions as a pull-up resistor for pulling up the power good signal PG4 from the monitor IC 100 to the microcomputer 300 to the power supply voltage VDD.

The capacitor C1 is connected between the VDD pin of the monitoring IC 100 and the ground terminal, and functions as smoothing means for the output voltage VO1 (=power supply voltage VDD).

Capacitor C2 is connected between the CT pin of monitor IC 100 and ground, and functions as a reset time setting element.

<Monitoring IC (package)>
FIG. 2 is a diagram showing the package appearance (top surface and bottom surface) of the monitoring IC 100. As shown in FIG. As shown in this figure, as a package of the monitoring IC 100, for example, a VQFN [very thin quad flat non-leaded] package may be adopted.

More specifically, the monitoring IC 100 has a resin sealing body 101 that is rectangular in plan view, and on the bottom surface of which does not protrude from the resin sealing body 101, a total of 20 lines, five on each side. External terminals 102 are exposed. With such a leadless VQFN package, it is possible to reduce the mounting area compared to packages with leads (such as QFP [quad flat package]).

The resin sealing body 101 is tapered from the side surface to the bottom surface so that the bottom surface is slightly smaller than the top surface. Also, the external terminals 102 are exposed from the bottom surface to the side surface of the resin sealing body 101 . With such a configuration, mounting work on a printed wiring board (not shown) can be carried out easily and reliably.

Also, on the bottom surface of the resin sealing body 101, the back surface of the island (=the back side of the chip mounting surface) on which the semiconductor chip (not shown) of the monitoring IC 100 is mounted is exposed as a heat radiation pad 103. FIG. With such a configuration, it is possible to improve the heat dissipation of the monitoring IC 100 .

At least one of the four corners of the heat radiation pad 103 is preferably provided with a notch 103a. With such a configuration, it is possible to improve the adhesion with the resin sealing body 101 and prevent the heat radiation pad 103 (=island) from coming off.

<Monitoring IC (pin arrangement)>
FIG. 3 is a diagram showing the pin arrangement of the monitor IC 100 (when a 20-pin VQFN is used). On the first side (bottom side of the figure) of the monitor IC 100, five external terminals (pins 1 to 5) are arranged in order from left to right in the figure. 1 pin is a power supply terminal (VDD pin). 2 pin is an unused terminal (NC [non-connection] pin). 3 pin is a ground terminal (GND pin). 4 pin is an unused terminal (NC pin). Pin 5 is a reset time setting terminal (CT pin).

Five external terminals (pins 6 to 10) are arranged in order from bottom to top in the figure on the second side (right side in the figure) of the monitoring IC 100 . 6 pin is an SPI data output terminal (MIMO pin). A 7 pin is an SPI data input terminal (MOSI pin). Pin 8 is an SPI clock terminal (SCLK pin). Pin 9 is an SPI chip select terminal (XSCS pin). Pin 10 is a watchdog input terminal (WDIN pin).

Five external terminals (pins 11 to 15) are arranged in order from right to left in the figure on the third side (upper side in the figure) of the monitoring IC 100 . Pin 11 is the first monitor input pin (DIN1 pin). A 12th pin is a first power good output terminal (PG1 pin). Pin 13 is the second monitor input pin (DIN2 pin). A 14th pin is a second power good output terminal (PG2 pin). Pin 15 is the third monitoring input pin (DIN3 pin).

Five external terminals (pins 16 to 20) are arranged in order from top to bottom in the figure on the fourth side (left side in the figure) of the monitoring IC 100 . A 16th pin is a third power good output terminal (PG3 pin). A 17th pin is a fourth monitoring input pin (DIN4 pin). The 18th pin is a fourth power good output terminal (PG4 pin). A 19th pin is a monitor input pin for reset (XRSTIN pin). A 20th pin is a reset output terminal (XRSTOUT pin).

<Monitoring IC (first embodiment)>
FIG. 4 is a diagram showing a first embodiment (basic configuration) of the monitoring IC 100. As shown in FIG. The monitoring IC 100 of this embodiment includes a reference voltage generation unit 111, a sub-reference voltage generation unit 112, a reference voltage detection unit 120, a UVLO [under voltage locked-out] unit 130, and threshold voltage generation units 140 to 149. , comparators 150 to 159, oscillators 161 and 162, a digital processing unit 170, N-channel MOS [metal oxide semiconductor] field effect transistors 180 to 184, and an SPI interface 190 are integrated.

The reference voltage generator 111 generates a predetermined reference voltage VREF from the power supply voltage VDD input to the VDD pin.

The sub-reference voltage generator 112 generates a predetermined sub-reference voltage VREF2 from the power supply voltage VDD.

The reference voltage detection unit 120 operates by receiving the supply of the power supply voltage VDD, detects whether the reference voltage VREF and the sub-reference voltage VREF2 rise normally, and generates the reference voltage detection signal VREF_DET. The reference voltage detection signal VREF_DET becomes low level when both the reference voltage VREF and the sub-reference voltage VREF2 rise normally, and becomes high level when at least one of them does not rise normally. A BIST [built-in self test] enable signal BIST_EN is input to the reference voltage detection unit 120 . That is, the reference voltage detection unit 120 corresponds to a monitoring unit (or one of a plurality of monitoring mechanisms included therein) that is subject to self-diagnosis when the monitoring IC 100 is activated.

The UVLO unit 130 detects a low voltage abnormality of the power supply voltage VDD and outputs a low voltage abnormality signal UVLO. The low voltage abnormality signal UVLO becomes high level when the power supply voltage VDD becomes higher than the low voltage abnormality release value UVLO_OFF, and becomes low level when the power supply voltage VDD becomes lower than the low voltage abnormality detection value UVLO_ON.

Threshold voltage generators 140 and 141 divide the reference voltage VREF to generate an upper threshold voltage Vth0H (eg, 0.88 V) and a lower threshold voltage Vth0L (eg, 0.72 V).

The threshold voltage generators 142 and 143 divide the reference voltage VREF to generate an upper threshold voltage Vth1H (eg, 0.88 V) and a lower threshold voltage Vth1L (eg, 0.72 V).

The threshold voltage generators 144 and 145 divide the reference voltage VREF to generate an upper threshold voltage Vth2H (eg, 0.88 V) and a lower threshold voltage Vth2L (eg, 0.72 V).

The threshold voltage generators 146 and 147 divide the reference voltage VREF to generate an upper threshold voltage Vth3H (eg, 0.88 V) and a lower threshold voltage Vth3L (eg, 0.72 V).

The threshold voltage generators 148 and 149 divide the reference voltage VREF to generate an upper threshold voltage Vth4H (eg, 0.88 V) and a lower threshold voltage Vth4L (eg, 0.72 V).

The comparator 150 receives the supply of the power supply voltage VDD and operates. The input voltage V0 input from the XRSTIN pin to the non-inverting input terminal (+) and the input voltage V0 from the threshold voltage generator 140 to the inverting input terminal (-) are input to the comparator 150. A comparison signal RSTOVD is generated by comparing with the upper threshold voltage Vth0H. The comparison signal RSTOVD becomes high level when V0>Vth0H, and becomes low level when V0<Vth0H.

The comparator 151 receives the supply of the power supply voltage VDD and operates, and receives the input voltage V0 input to the inverting input terminal (-) from the XRSTIN pin and the non-inverting input terminal (-) from the threshold voltage generator 141. A comparison signal RSTUVD is generated by comparing with the lower threshold voltage Vth0L. The comparison signal RSTUVD becomes low level when V0>Vth0L, and becomes high level when V0<Vth0L.

The comparator 152 receives the supply of the power supply voltage VDD and operates, and receives the input voltage V1 input from the DIN1 pin to the non-inverting input terminal (+) and the input voltage V1 from the threshold voltage generator 142 to the inverting input terminal (-). A comparison signal DIN1OVD is generated by comparing with the upper threshold voltage Vth1H. The comparison signal DIN1OVD becomes high level when V1>Vth1H, and becomes low level when V1<Vth1H.

The comparator 153 operates by receiving supply of the power supply voltage VDD, and receives the input voltage V1 input to the inverting input terminal (-) from the DIN1 pin and the non-inverting input terminal (-) from the threshold voltage generator 143. A comparison signal DIN1UVD is generated by comparing with the lower threshold voltage Vth1L. The comparison signal DIN1UVD becomes low level when V1>Vth1L, and becomes high level when V1<Vth1L.

The comparator 154 receives the supply of the power supply voltage VDD and operates, and receives the input voltage V2 input from the DIN2 pin to the non-inverting input terminal (+) and the input voltage V2 from the threshold voltage generator 144 to the inverting input terminal (-). A comparison signal DIN2OVD is generated by comparing with the upper threshold voltage Vth2H. The comparison signal DIN2OVD becomes high level when V2>Vth2H, and becomes low level when V2<Vth2H.

The comparator 155 receives supply of the power supply voltage VDD and operates, and receives the input voltage V2 input to the inverting input terminal (-) from the DIN2 pin and the non-inverting input terminal (-) from the threshold voltage generator 145. A comparison signal DIN2UVD is generated by comparing with the lower threshold voltage Vth2L. The comparison signal DIN2UVD becomes low level when V2>Vth2L, and becomes high level when V2<Vth2L.

The comparator 156 receives supply of the power supply voltage VDD and operates, and receives the input voltage V3 input to the non-inverting input terminal (+) from the DIN3 pin and the input voltage V3 to the inverting input terminal (-) from the threshold voltage generator 146. A comparison signal DIN3OVD is generated by comparing with the upper threshold voltage Vth3H. The comparison signal DIN3OVD becomes high level when V3>Vth3H, and becomes low level when V3<Vth3H.

The comparator 157 receives the supply of the power supply voltage VDD and operates, and receives the input voltage V3 input to the inverting input terminal (-) from the DIN3 pin and the non-inverting input terminal (-) from the threshold voltage generator 147. A comparison signal DIN3UVD is generated by comparing with the lower threshold voltage Vth3L. The comparison signal DIN3UVD becomes low level when V3>Vth3L, and becomes high level when V3<Vth3L.

The comparator 158 receives the supply of the power supply voltage VDD and operates, and receives the input voltage V4 input from the DIN4 pin to the non-inverting input terminal (+) and the input voltage V4 from the threshold voltage generator 148 to the inverting input terminal (-). A comparison signal DIN4OVD is generated by comparing with the upper threshold voltage Vth4H. The comparison signal DIN4OVD becomes high level when V4>Vth4H, and becomes low level when V4<Vth4H.

The comparator 159 operates by receiving the power supply voltage VDD, and receives the input voltage V4 input from the DIN4 pin to the inverting input terminal (-) and the input voltage V4 from the threshold voltage generator 149 to the non-inverting input terminal (-). A comparison signal DIN4UVD is generated by comparing with the lower threshold voltage Vth4L. The comparison signal DIN4UVD becomes low level when V4>Vth4L, and becomes high level when V4<Vth4L.

A BIST enable signal BIST_EN is input to each of the comparators 151 to 159 described above. That is, each of the comparators 151 to 159 corresponds to a monitoring section (or one of a plurality of monitoring mechanisms included therein) that is subject to self-diagnosis when the monitoring IC 100 is activated.

The oscillator 161 operates by receiving supply of the power supply voltage VDD and the reference voltage VREF, and generates a clock signal CLK1 having an oscillation frequency f1 (for example, f1=2.2 MHz) used in the digital processing section 170 .

The oscillator 162 operates with the supply of the power supply voltage VDD and the reference voltage VREF, and generates a clock signal CLK2 with an oscillation frequency f2 (for example, f2=500 kHz) used by the digital processing unit 170 (especially the watchdog timer 173). Note that the oscillation frequency f2 of the clock signal CLK2 can be arbitrarily adjusted by SPI communication.

Also, the oscillators 161 and 162 are reset by the low voltage fault signal UVLO. More specifically, the oscillators 161 and 162 are reset (=disabled) when the low voltage error signal UVLO is at low level, and are reset when the low voltage error signal UVLO is at high level. It will be in a released state (=enable state).

The digital processing unit 170 operates by being supplied with the power supply voltage VDD, and performs monitoring processing of various input signals and generation processing of various output signals. Also, the digital processing unit 170 is reset by the low voltage abnormality signal UVLO. More specifically, the digital processing unit 170 is in a reset state (=disabled state) when the low voltage abnormality signal UVLO is at low level, and is in a reset release state when the low voltage abnormality signal UVLO is at high level. (=enable state). The internal configuration and operation of the digital processing unit 170 will be described later.

The transistor 180 is connected between the XRSTOUT pin (=the output terminal of the reset output signal XRSTOUT) and the ground terminal, and is turned on/off according to the gate signal G0 input from the digital processing section 170 . The reset output signal XRSTOUT is at low level (=logic level at reset) when the transistor 181 is on, and at high level (=logic level at reset cancellation) when the transistor 181 is off.

The transistor 181 is connected between the PG1 pin (=the output terminal of the power good signal PG1) and the ground terminal, and is turned on/off according to the gate signal G1 input from the digital processing section 170 . The power good signal PG1 is low level (=abnormal logic level) when the transistor 181 is on, and is high level (=normal logic level) when the transistor 181 is off.

The transistor 182 is connected between the PG2 pin (=the output terminal of the power good signal PG2) and the ground terminal, and is turned on/off according to the gate signal G2 input from the digital processing section 170. FIG. The power good signal PG2 is low level (=abnormal logic level) when the transistor 182 is on, and is high level (=normal logic level) when the transistor 182 is off.

The transistor 183 is connected between the PG3 pin (=the output terminal of the power good signal PG3) and the ground terminal, and is turned on/off according to the gate signal G3 input from the digital processing section 170. FIG. The power good signal PG3 is low level (=abnormal logic level) when the transistor 183 is on, and is high level (=normal logic level) when the transistor 183 is off.

The transistor 184 is connected between the PG4 pin (=the output terminal of the power good signal PG4) and the ground terminal, and is turned on/off according to the gate signal G4 input from the digital processing section 170. FIG. The power good signal PG4 is low level (=abnormal logic level) when the transistor 184 is on, and is high level (=normal logic level) when the transistor 184 is off.

The SPI interface 190 is connected to the XSCS pin, the SCLK pin, the MOSI pin, and the MISO pin, and performs bidirectional communication between the monitor IC 100 (especially the digital processing unit 170) and the microcomputer 300 via the SPI bus. conduct.

<Digital processing unit>
Next, the internal configuration of the digital processing section 170 will be described with reference to FIG. The digital processing unit 170 of this configuration example includes a self-diagnosis unit 171, a clock detection unit 172, a watchdog timer 173, filters FLT0 to FLT4, counters CNT0 to CNT4, OR gates OR0 to OR4 and OR10 to OR14. and including.

The self-diagnostic unit 171 checks the reference voltage detection signal VREF_DET and the comparison signals (RSTOVD, RSTUVD, DINxOVD, and DINxUVD) when the monitoring IC 100 is activated, so that the reference voltage detection unit 120 and the comparators 150 to 159 are normal. A self-diagnostic operation (hereinafter abbreviated as BIST) is performed to determine whether the system is functioning correctly, and a BIST error signal BIST_ERROR is generated. Note that the BIST error signal BIST_ERROR becomes high level when an abnormality is detected in either the reference voltage detection unit 120 or the comparators 150 to 159 .

Self-diagnosis section 171 also generates a BIST enable signal BIST_EN and sends it to reference voltage detection section 120 and comparators 150 to 159, respectively. Note that the BIST enable signal BIST_EN becomes high level during execution of the BIST.

The clock detector 172 detects frequency anomalies of the clock signals CLK1 and CLK2 and generates a clock detection signal CLK_DET. The clock detection signal CLK_DET becomes high level when the frequency abnormality of the clock signal CLK1 or CLK2 is detected.

The watchdog timer 173 detects frequency anomalies (SLOW anomaly and FAST anomaly) of the microcomputer 300 and generates a watchdog detection signal WDT_DET. The watchdog detection signal WDT_DET becomes high level when the frequency abnormality of the microcomputer 30 is detected. Note that the WDIN pin is pulled down inside the monitoring IC 100 .

OR gate OR0 performs a logical sum operation of comparison signals RSTOVD and RSTUVD. Therefore, the output signal of the OR gate OR0 becomes high level when at least one of the comparison signals RSTOVD and RSTUVD is high level, and becomes low level when both the comparison signals RSTOVD and RSTUVD are low level.

OR gate OR1 performs a logical sum operation of comparison signals DIN1OVD and DIN1UVD. Therefore, the output signal of the OR gate OR1 becomes high level when at least one of the comparison signals DIN1OVD and DIN1UVD is high level, and becomes low level when both the comparison signals DIN1OVD and DIN1UVD are low level.

OR gate OR2 performs a logical sum operation of comparison signals DIN2OVD and DIN2UVD. Therefore, the output signal of the OR gate OR2 becomes high level when at least one of the comparison signals DIN2OVD and DIN2UVD is high level, and becomes low level when both the comparison signals DIN2OVD and DIN2UVD are low level.

OR gate OR3 performs a logical sum operation of comparison signals DIN3OVD and DIN3UVD. Therefore, the output signal of the OR gate OR3 becomes high level when at least one of the comparison signals DIN3OVD and DIN3UVD is high level, and becomes low level when both the comparison signals DIN3OVD and DIN3UVD are low level.

A logical sum gate OR4 performs a logical sum operation of the comparison signals DIN4OVD and DIN4UVD. Therefore, the output signal of the OR gate OR4 becomes high level when at least one of the comparison signals DIN4OVD and DIN4UVD is high level, and becomes low level when both the comparison signals DIN4OVD and DIN4UVD are low level.

Filters FLT0-FLT4 perform predetermined filtering processing on the output signals of OR gates OR0-OR4, respectively, and output the filtered signals to subsequent stages. However, the filters FLT0 to FLT4 are not essential components, and if there is no concern about noise, etc., the filters FLT0 to FLT4 may be omitted and the output signals of the OR gates OR0 to OR4 may be passed through to the subsequent stage. .

The counters CNT0 to CNT4 perform predetermined counter processing on the output signals of the filters FLT0 to FLT4, respectively, and output the results to subsequent stages. Note that the output signal of the counter CNT0 is output to the OR gate OR10 as the reset input detection signal RSTIN_DET. However, the counters CNT0 to CNT4 are not essential components, and if there is no concern about noise, etc., the counters CNT0 to CNT4 can be omitted and the output signals of the OR gates OR0 to OR4 (or the outputs of the filters FLT0 to FLT4) signal) may be passed through to the subsequent stage.

The OR gate OR10 outputs the reset output detection signal RSTOUT_DET by ORing the reference voltage detection signal VREF_DET, the reset input detection signal RSTIN_DET, the BIST error signal BIST_ERROR, the watchdog detection signal WDT_DET, and the clock detection signal CLK_DET. Generate. Therefore, the reset output detection signal RSTOUT_DET becomes high level when any one of the plurality of input signals is high level, and becomes low level when all of them are low level. Note that the reset output detection signal RSTOUT_DET is output to the gate of the transistor 180 as the aforementioned gate signal G0.

OR gates OR11 to OR14 generate power good detection signals PG1_DET to PG4_DET by ORing output signals of counters CNT1 to CNT4 and reference voltage detection signal VREF_DET, respectively. Therefore, when the reference voltage detection signal VREF_DET is at low level, the output signals of the counters CNT1 to CNT4 are directly output as the power good detection signals PG1_DET to PG4_DET. On the other hand, when the reference voltage detection signal VREF_DET is at high level, the power good detection signals PG1_DET to PG4_DET are all fixed at high level regardless of the output signals of the counters CNT1 to CNT4. The power good detection signals PG1_DET to PG4_DET are output to the gates of the transistors 181 to 184 as the aforementioned gate signals G1 to G4.

<Self-diagnosis function>
Next, the self-diagnosis function of the monitor IC 100 will be described in detail. FIG. 5 is a circuit diagram showing a configuration example of a test circuit introduced into a monitoring unit to be self-diagnosed. As shown in the figure, the monitor IC 100 incorporates a plurality of test circuits (T1, T2, T10 to T14) as means for implementing the BIST described above.

The test circuits T1 and T2 are attached to the reference voltage detector 120. FIG. More specifically, the reference voltage detection unit 120 includes divided voltage generation units 121 and 122 and comparators 123 and 124, and the test circuits T1 and T2 are connected to the divided voltage generation units 121 and 122, respectively. It is connected to the.

The divided voltage generator 121 generates divided voltages Vd1H and Vd1L (Vd1H>Vd1L) from the reference voltage VREF.

The divided voltage generator 122 generates divided voltages Vd2H and Vd2L (Vd2H>Vd2L) from the sub-reference voltage VREF2.

The comparator 123 compares the divided voltage Vd2H input to the non-inverting input terminal (+) and the divided voltage Vd1L input to the inverting input terminal (-) to generate a comparison signal VRDET1. The comparison signal VRDET1 becomes high level when Vd2H>Vd1L, and becomes low level when Vd2H<Vd1L.

The comparator 124 compares the divided voltage Vd1H input to the non-inverting input terminal (+) and the divided voltage Vd2L input to the inverting input terminal (-) to generate a comparison signal VRDET2. The comparison signal VRDET2 becomes high level when Vd1H>Vd2L, and becomes low level when Vd1H<Vd2L.

The test circuit T1 is connected to the middle point node A of the divided voltage generator 121 (=the middle node sandwiched between the output terminals of the divided voltages Vd1H and Vd1L). The voltage value of point node A is switched. Specifically, the test circuit T1 opens the midpoint node A when VRDET1SW=L, and shorts the midpoint node A to the ground when VRDET1SW=H.

The test circuit T2 is connected to the middle point node B of the divided voltage generator 122 (=the middle node sandwiched between the output terminals of the divided voltages Vd2H and Vd2L). Switch the voltage value of the point node B. Specifically, the test circuit T2 opens the midpoint node B when VRDET2SW=L, and shorts the midpoint node B to ground when VRDET2SW=H.

The test circuit T10 is connected to the input terminal of the input voltage V0, and switches the voltage value of the input voltage V0 in accordance with the control signals RSTSW1 to RSTSW4 (=binary signals that are alternatively set to high level). Specifically, test circuit T10 sets V0=XRSTIN when RSTSW1=H, sets V0=V0H (eg, 1.04 V) when RSTSW2=H, and sets V0= when RSTSW3=H. V0M (0.8V, for example), and V0=V0L (0.56V, for example) when RSTSW4=H. The three test input voltages (V0H, V0M, V0L) are preferably generated by dividing the reference voltage VREF.

The test circuit T11 is connected to the input terminal of the input voltage V1, and switches the voltage value of the input voltage V1 according to the control signals DIN1SW1 to DIN1SW4 (=binary signals that are alternatively set to high level). Specifically, the test circuit T11 sets V1=DIN1 when DIN1SW1=H, sets V1=V1H (eg, 1.04 V) when DIN1SW2=H, and sets V1= when DIN1SW3=H. V1M (0.8 V, for example), and V1=V1L (0.56 V, for example) when DIN1SW4=H. The three test input voltages (V1H, V1M, V1L) are preferably generated by dividing the reference voltage VREF.

The test circuit T12 is connected to the application terminal of the input voltage V2, and switches the voltage value of the input voltage V2 according to the control signals DIN2SW1 to DIN2SW4 (=binary signals that are alternatively set to high level). Specifically, the test circuit T12 sets V2=DIN2 when DIN2SW1=H, sets V2=V2H (eg, 1.04 V) when DIN2SW2=H, and sets V2= when DIN2SW3=H. V2M (0.8V, for example), and V2=V2L (0.56V, for example) when DIN2SW4=H. The three test input voltages (V2H, V2M, V2L) are preferably generated by dividing the reference voltage VREF.

The test circuit T13 is connected to the input terminal of the input voltage V3, and switches the voltage value of the input voltage V3 according to the control signals DIN3SW1 to DIN3SW4 (=binary signals that are alternatively set to high level). Specifically, the test circuit T13 sets V3=DIN3 when DIN3SW1=H, sets V3=V3H (eg, 1.04 V) when DIN3SW2=H, and sets V3= when DIN3SW3=H. V3M (for example, 0.8V) and V3=V3L (for example, 0.56V) when DIN3SW4=H. The three test input voltages (V3H, V3M, V3L) are preferably generated by dividing the reference voltage VREF.

The test circuit T14 is connected to the input terminal of the input voltage V4, and switches the voltage value of the input voltage V4 in accordance with the control signals DIN4SW1 to DIN4SW4 (=binary signals that are alternatively set to high level). Specifically, test circuit T14 sets V4=DIN4 when DIN4SW1=H, sets V4=V4H (eg, 1.04 V) when DIN4SW2=H, and sets V4= when DIN4SW3=H. V4M (for example, 0.8V) and V4=V4L (for example, 0.56V) when DIN4SW4=H. The three test input voltages (V4H, V4M, V4L) are preferably generated by dividing the reference voltage VREF.

<BIST>
FIG. 6 is a timing chart showing an example of BIST (focusing only on the DIN1 pin) in the first embodiment, in which the input voltage V1 and the comparison signals DIN1OVD and DIN1UVD are depicted in order from the top.

As indicated by the upward arrows in the figure, in the BIST of this embodiment, the expected value determination of both the comparison signals DIN1OVD and DIN1UVD is performed each time the voltage value of the input voltage V1 is switched. More specifically, during the input period of the test input voltage V1H, an expected value determination is made as to whether DIN1OVD=H and DIN1UVD=L. =L and DIN1UVD=H. Further, during the input period of the test input voltage V1M, an expected value determination is made as to whether or not DIN1OVD=DIN1UVD=L.

In this figure, the BIST of the monitoring mechanism (comparators 152 and 153) connected to the DIN1 pin is taken as an example, but other external terminals (DIN2 pin, DIN3 pin, DIN4 pin, or XRSTIN pin) are also connected. The BIST similar to the above is sequentially performed for the monitoring mechanism that has been selected.

That is, the self-diagnostic section 171 selects a monitoring mechanism to be diagnosed from among a plurality of monitoring mechanisms (for example, comparators 150 to 159) included in the monitoring section (=comparator for inputting test input voltage V*H or V*L). ), while comparing whether or not the output signal matches the expected value, and also for the monitoring mechanism other than the diagnosis object (=comparator to which the test input voltage V*M is input), each output signal matches the expected value.

In this way, according to the BIST method in which each comparator is targeted for diagnosis one by one and the outputs of all comparators are evaluated at all comparison timings, it is possible to improve the failure detection rate of the monitoring IC 100 .

It should be noted that the BIST described above is preferably performed in the monitoring IC 100 after the power management IC 200 has started the power supply, until a predetermined reset cancellation waiting time t1 (for example, 10 ms) elapses. If no abnormality is detected in the monitor IC 100, the monitor operation is promptly started, and the reset of the microcomputer 300 is released when the reset release waiting time t1 has passed. As a result, the operation of the microcomputer 300 is started.

Therefore, BIST can be performed without affecting the operation start timing of the microcomputer 300, so that the electronic device 1 can be started at the same timing as before. Focusing on the monitoring IC 100, it is possible to start the original monitoring operation after self-diagnosing whether it is normal or not, so it is possible to improve the failure detection rate.

Prior to the BIST described above, the digital processing unit 170 should perform a self-test such as a scan path to confirm that it operates normally.

By the way, the monitoring IC 100 of the present embodiment performs BIST only once at startup. Alternatively, it is desirable to perform BIST at any timing. Therefore, a second embodiment is proposed in which BIST can be performed even while the monitoring IC 100 is in operation.

<Monitoring IC (second embodiment)>
FIG. 7 is a diagram showing a second embodiment of the monitoring IC 100. As shown in FIG. The monitoring IC 100 of the present embodiment is based on the first embodiment described above, and is a means for performing BIST of the monitoring units (for example, the comparators 152 to 159) not only when the monitoring IC 100 is activated but also during operation. , a multiplexer MUX, comparators 15A and 15B and a test circuit T15. Further, the digital processing unit 170 additionally includes an OR gate OR5, a filter FLT5, and a counter CNT5. Note that the same reference numerals as those in FIG. 4 are given to the components that have already been described to omit redundant description, and the characteristic portions of the present embodiment will be mainly described below.

A multiplexer MUX selects one of the DIN1 to DIN4 pins and connects it to the input terminal of the test circuit T15.

The comparator 15A generates a comparison signal SP_OVD by comparing the input voltage VSP input to the non-inverting input terminal (+) and the upper threshold voltage VthxH input to the inverting input terminal (-). The comparison signal SP_OVD becomes high level when VSP>VthxH, and becomes low level when VSP<VthxH.

Note that the upper threshold voltage VthxH is varied in conjunction with the multiplexer MUX. Specifically, the upper threshold voltage VthxH is Vth1H when the DIN1 pin is selected, Vth2H when the DIN2 pin is selected, Vth3H when the DIN3 pin is selected, and Vth4H when the DIN4 pin is selected.

The comparator 15B generates a comparison signal SP_UVD by comparing the input voltage VSP input to the inverting input terminal (-) and the lower threshold voltage VthxL input to the non-inverting input terminal (+). The comparison signal SP_UVD becomes low level when VSP>VthxL, and becomes high level when VSP<VthxL.

Note that the lower threshold voltage VthxL is varied in conjunction with the multiplexer MUX. Specifically, the lower threshold voltage VthxL is Vth1L when the DIN1 pin is selected, Vth2L when the DIN2 pin is selected, Vth3L when the DIN3 pin is selected, and Vth4L when the DIN4 pin is selected.

The test circuit T15 is connected to the application end of the input voltage VSP (=the output end of the multiplexer MUX), and switches the voltage value of the input voltage VSP. Note that the configuration of the test circuit T15 is similar to that of the test circuits T11 to T14 (see FIG. 5), so detailed description thereof will be omitted.

A logical sum gate OR5 performs a logical sum operation of the comparison signals SP_OVD and SP_UVD. Therefore, the output signal of the OR gate OR5 becomes high level when at least one of the comparison signals SP_OVD and SP_UVD is high level, and becomes low level when both the comparison signals SP_OVD and SP_UVD are low level.

Filter FLT5 applies a predetermined filtering process to the output signal of OR gate OR5 and outputs the result to the subsequent stage. However, the filter FLT5 is not an essential component, and if there is no concern about noise or the like, the filter FLT5 may be omitted and the output signal of the OR gate OR5 passed through to the subsequent stage. This point is similar to the filters FLT1 to FLT4 already described.

The counter CNT5 performs predetermined counter processing on the output signal of the filter FLT5 and outputs the result to the subsequent stage. Output signals from the counters CNT1 to CNT4 are output to the self-diagnosis section 171 as error detection signals DIN1_ERR to DIN4_ERR. Similarly, the output signal of the counter CNT5 is output to the self-diagnosis section 171 as the error detection signal SP_ERR. However, the counter CNT5 is not an essential component, and if there is no concern about noise, etc., the counter CNT5 can be omitted and the output signal of the OR gate OR5 (or the output signal of the filter FLT5) passed through to the subsequent stage. good too. This point is similar to the counters CNT1 to CNT4 already described.

The components added in this embodiment function as sub-monitoring units that detect abnormalities in monitored objects by substituting for the monitoring units (for example, comparators 152 to 159) during diagnosis by the self-diagnostic unit 171. FIG. The operation of the sub-monitoring unit will be described in detail below.

FIG. 8 is a flowchart showing an example of diagnostic operation (analog BIST during operation of the monitoring IC 100) in the second embodiment. In step S1, while normal operation of the monitor IC 100 (=detection of abnormality of pins DIN1 to DIN4 using comparators 152 to 159) is performed, in step S2, the timing at which BIST of comparators 152 to 159 should be performed. has arrived. Here, if the determination is YES, the flow proceeds to step S3. On the other hand, if the determination is NO, the flow returns to step S1 and the normal operation of the monitor IC 100 is continued. It should be noted that the yes determination conditions in step S2 include elapse of an interval time, reception of a BIST request command, and the like.

If a YES determination is made in step S2, BIST of comparators 152 and 153 that monitor the DIN1 pin is performed in step S3. At this time, the multiplexer MUX selects the DIN1 pin among the DIN1 to DIN4 pins and connects it to the input end of the test circuit T15. The test circuit T15 passes through the output of the multiplexer MUX. The digital processing unit 170 treats the error detection signal SP_ERR as the error detection signal DIN1_ERR. Due to the series of operations described above, during the diagnosis of the comparators 152 and 153, the comparators 15A and 15B are used to continue detecting the abnormality of the DIN1 pin.

Next, in step S4, BIST of comparators 154 and 155 that monitor the DIN2 pin is performed. At this time, the multiplexer MUX selects the DIN2 pin among the DIN1 to DIN4 pins and connects it to the input terminal of the test circuit T15. The test circuit T15 passes through the output of the multiplexer MUX. The digital processing unit 170 treats the error detection signal SP_ERR as the error detection signal DIN2_ERR. Through the series of operations described above, during the diagnosis of the comparators 154 and 155, the comparators 15A and 15B are used to continue detecting the abnormality of the DIN2 pin.

Next, in step S5, BIST of the comparators 156 and 157 that monitor the DIN3 pin is performed. At this time, the multiplexer MUX selects the DIN3 pin among the DIN1 to DIN4 pins and connects it to the input terminal of the test circuit T15. The test circuit T15 passes through the output of the multiplexer MUX. The digital processing unit 170 treats the error detection signal SP_ERR as the error detection signal DIN3_ERR. Due to the series of operations described above, during the diagnosis of the comparators 156 and 157, the comparators 15A and 15B are used to continue detecting the abnormality of the DIN3 pin.

Next, in step S6, the BIST of comparators 158 and 159 that monitor the DIN4 pin is performed. At this time, the multiplexer MUX selects the DIN4 pin among the DIN1 to DIN4 pins and connects it to the input terminal of the test circuit T15. The test circuit T15 passes through the output of the multiplexer MUX. The digital processing unit 170 treats the error detection signal SP_ERR as the error detection signal DIN4_ERR. Due to the series of operations described above, during the diagnosis of the comparators 158 and 159, the comparators 15A and 15B are used to continue detecting the abnormality of the DIN4 pin.

In this way, the sub-monitoring units (comparators 15A and 15B) successively replace the monitoring units (comparators 151 to 159) provided for the DIN1 to DIN4 pins that are being diagnosed. With such a configuration, BIST of the comparators 151 to 159 can be performed periodically or at arbitrary timing without interrupting the abnormality detection operation of each of the DIN1 to DIN4 pins.

In the subsequent step S7, it is determined whether or not any abnormality (NG) has been detected in the BIST. Here, if the determination is YES, the flow proceeds to step S8, an abnormality is notified to the microcomputer 300 (=register storage of the BIST diagnosis result), and the sub-monitoring units (comparators 15A and 15B ) switches to an alternative action using

For example, when at least one of the comparators 152 and 153 that monitor the DIN1 pin is diagnosed to be abnormal, the comparators 152 and 153 are not used, and the comparators 15A and 15B are used to continue detecting the abnormality of the DIN1 pin. be done.

Basically, the same applies when any of the comparators 154 and 155 that monitor the DIN2 pin, the comparators 156 and 157 that monitor the DIN3 pin, and the comparators 158 and 159 that monitor the DIN4 pin are determined to be abnormal. Similarly, an alternative operation using comparators 15A and 15B is performed, with the use of the bad comparators being turned off.

On the other hand, if a negative determination is made in step S7, the flow returns to step S1 and the monitor IC 100 returns to normal operation. During the normal operation in step S1, the sub-monitoring units (comparators 15A and 15B) become redundant, so BIST using the test circuit T15 is performed to diagnose whether the sub-monitoring units are functioning normally. It is desirable to keep At this time, if any abnormality (NG) is detected in the sub-monitoring unit, the sub-monitoring unit cannot be substituted, so it is sufficient to always make a NO determination in step S2. Further, when a backup sub-monitoring unit is prepared, the use of the abnormal sub-monitoring unit may be stopped and the backup sub-monitoring unit may be used.

By the way, the monitoring IC 100 described so far has a function (=analog BIST function) for checking the accuracy of the reference voltage detection unit 120 and the comparators 150 to 159, but the accuracy of the digital processing unit 170 is checked. However, the factor of latent fault (LF [latent fault]) remains. Therefore, there is no guarantee that the monitoring IC 100 will operate correctly in the event of an accidental failure. Therefore, a third embodiment is proposed to solve the above problem.

<Monitoring IC (third embodiment)>
FIG. 9 is a diagram showing a third embodiment of the monitoring IC 100 (an example of circuit configuration focused on the XRSTIN monitoring system). The monitoring IC 100 of the present embodiment is based on the first embodiment (or the second embodiment) described above, and has an analog BIST function (= for example, a function to check the likelihood of the comparators 150 and 151), as well as a digital A BIST function (=a function for checking the certainty of the digital processing unit 170) is added.

Specifically, the digital processing unit 170 includes, in addition to the OR gates OR0 and OR10, the filter FLT0, and the counter CNT0, multiplexers MUX1 and MUX2, and a second self-diagnostic unit ( digital BIST section) 174 and an OR gate OR20.

The OR gates OR0 and OR10, the filter FLT0, and the counter CNT0 correspond to an output signal generator that receives the comparison signals RSTOVD and RSTUVD from the comparators 150 and 151 and generates the reset output detection signal RSTOUT_DET.

The multiplexer MUX1 selects either the comparison signal RSTOVD input from the comparator 150 or the digital BIST input signal DBIST_IN1 input from the second self-diagnosis section 174, and outputs it to the OR gate OR0. More specifically, the multiplexer MUX1 selects and outputs the comparison signal RSTOVD during normal operation, and selects and outputs the digital BIST input signal DBIST_IN1 during digital BIST operation.

The multiplexer MUX2 selects either the comparison signal RSTUVD input from the comparator 151 or the digital BIST input signal DBIST_IN2 input from the second self-diagnosis section 174, and outputs it to the OR gate OR0. More specifically, the multiplexer MUX2 selects and outputs the comparison signal RSTUVD during normal operation, and selects and outputs the digital BIST input signal DBIST_IN2 during digital BIST operation.

The second self-diagnosis section 174 performs digital BIST of the output signal generation section according to the digital BIST enable signal DBIST_EN input from the self-diagnosis section 171 .

More specifically, the second self-diagnosis section 174 inputs digital BIST input signals DBIST_IN1 and IN2 of a predetermined pattern to an output signal generation section (OR gate OR0), and generates a reset output detection signal RSTOUT_DET. By determining the expected value of (=digital BIST output signal DBIST_OUT), it is diagnosed whether the output signal generator is normal.

The second self-diagnosis section 174 also has a pattern table 174a and an expected value table 174b. The pattern table 174a stores patterns of the digital BIST input signals DBIST_IN1 and IN2 (=test input signals). The expected value table 174b stores expected values of the digital BIST output signal DBIST_OUT (=test output signal). Naturally, the patterns of the digital BIST input signals DBIST_IN1 and IN2 and the expected value of the digital BIST output signal DBIST_OUT are stored in association with each other.

In this figure, for convenience of illustration, attention is paid only to the XRSTIN monitoring system, but the same digital BIST function block (=multiplexer and second self-diagnostic unit ) has been introduced.

The self-diagnosis unit 171 receives not only the second self-diagnosis unit 174 of the XRSTIN monitoring system but also the digital BIST result signals DBIST_RST and DBIST_DINx (=is the output signal generation unit normal?) from the second self-diagnosis unit of the DINx monitoring system. diagnosis result indicating whether or not Then, the self-diagnosis section 171 generates a BIST error signal BIST_ERROR based on these digital BIST result signals DBIST_RST and DBIST_DINx.

The self-diagnostic section 171 also has a function of generating an analog BIST enable signal ABIST_EN (=corresponding to the BIST enable signal BIST_EN already described) and a digital BIST enable signal DBIST_EN.

The OR gate OR20 generates the gate signal G0 by ORing the reset output detection signal RSTOUT_DET, the analog BIST enable signal ABIST_EN, and the digital BIST enable signal DBIST_EN. Therefore, when at least one of the analog BIST enable signal ABIST_EN and the digital BIST enable signal DBIST_EN is at a high level (=logic level during BIST operation), the gate signal G0 can be generated regardless of the logic level of the reset output detection signal RSTOUT_DET. is held high, transistor 180 is turned on. That is, the reset output signal XRSTOUT is fixed at low level during the BIST operation before the completion of activation of the monitor IC 100 .

First, before explaining the digital BIST, the normal operation (=reset output operation) of the output signal generator will be briefly explained.

FIG. 10 is a timing chart showing an example of the reset output operation. From the top, the terminal voltage of the XRSTIN pin (=input voltage V0), the comparison signal RSTUVD, the count value of the counter CNT0, the reset input detection signal RSTIN_DET, and the A reset output signal XRSTOUT is depicted.

It is assumed that the lower threshold voltage Vth0L of the comparator 151 has hysteresis (UVD detection threshold and UVD cancellation threshold). All input signals to the OR gate OR10 are fixed at low level except for the reset input detection signal RSTIN_DET.

Before time t11, the input voltage V0 is higher than the UVD detection threshold, so the comparison signal RSTUVD becomes low level, and the reset input detection signal RSTIN_DET also becomes low level. As a result, the transistor 180 is turned off, so the reset output signal XRSTOUT is pulled up to high level (=logic level when reset is released).

At time t11, when the input voltage V0 becomes lower than the UVD detection threshold, the comparison signal RSTUVD rises to high level, and the reset input detection signal RSTIN_DET also rises to high level without delay. As a result, the transistor 180 is turned on, and the reset output signal XRSTOUT falls to low level (=logic level at reset).

At time t12, when the input voltage V0 becomes higher than the UVD cancellation threshold, the comparison signal RSTUVD falls to low level. At this time, the counting operation of the counter CNT0 is started, and the count value starts to be incremented. Note that the reset input detection signal RSTIN_DET is maintained at high level until the count value of the counter CNT0 reaches a predetermined value. As a result, the reset output signal XRSTOUT is maintained at low level even after the comparison signal RSTUVD has fallen to low level.

At time t13, when the count value of counter CNT0 reaches a predetermined value, reset input detection signal RSTIN_DET falls to low level. As a result, the transistor 180 is turned off, so the reset output signal XRSTOUT is pulled up to high level.

Thus, once the reset output signal XRSTOUT falls to low level, it is maintained at low level over the reset holding period Thold (=time t12 to t13, eg, 10 ms).

Next, the digital BIST performed by the second self-diagnosis section 174 will be described in detail.

FIG. 11 is a timing chart showing an example of diagnostic operation (digital BIST) in the third embodiment. The operating state of the self-diagnostic unit 174 (=operating state as a checker) and the reset output signal XRSTOUT are depicted.

At times t21 to t22, when the digital BIST enable signal DBIST_EN rises to high level, the digital BIST input signals DBIST_IN1 and IN2 of a predetermined pattern are input to the output signal generator (OR gate OR0). As for the patterns of the digital BIST input signals DBIST_IN1 and IN2, not only high-level/low-level combinations (four patterns) but also the pulse width, the number of pulses, or the pulse cycle can be arbitrarily set. .

After that, the output signal generator generates a digital BIST output signal DBIST_OUT corresponding to the digital BIST input signals DBIST_IN1 and IN2.

Then, the second self-diagnostic unit 174 performs expected value determination (=match/dismatch determination between the actual output value and the expected value) of the digital BIST output signal DBIST_OUT fed back from the output signal generation unit. A diagnosis is made as to whether or not the signal generator is normal.

At this time, if the actual output value and the expected value match, a diagnosis result indicating that the output signal generator is normal (for example, DBIST_RST=L) is obtained. XRSTOUT rises to high level (=logic level at reset release).

On the other hand, if the actual output value and the expected value do not match, a diagnostic result indicating that there is an internal failure in the output signal generator (for example, DBIST_RST=H) is obtained. is maintained at a low level (=logic level at reset).

In this way, if the digital BIST function is provided in addition to the analog BIST function, not only the certainty of the comparators 150 and 151 but also the certainty (validity of operation) of the digital processing unit 170 connected in the succeeding stage can be obtained. can also be checked, it is possible to contribute to improving the reliability of the monitoring IC 100 .

Note that the digital BIST may be performed, for example, when the monitoring IC 100 is activated. Also, the analog BIST and the digital BIST may be implemented serially or in parallel.

By the way, in the monitoring IC 100 of this embodiment, the accuracy of the open-drain output stage (I/O block) connected to the subsequent stage of the digital processing unit 170 is not checked, and the monitoring IC 100 is guaranteed to operate correctly in the event of an accidental failure. There is no Therefore, a fourth embodiment is proposed to solve the above problem.

<Monitoring IC (Fourth Embodiment)>
FIG. 12 is a diagram showing a fourth embodiment of the monitoring IC 100. As shown in FIG. The monitoring IC 100 of this embodiment is based on the above-described third embodiment, and has a multiplexer as a means for implementing an XRSTOUT pin fixation detection function (=a function of detecting fixation of the reset output signal XRSTOUT at a high level). It has a MUXO register 175 .

The multiplexer MUXO selects either the output signal of the OR gate OR20 or the inverted test output signal IOHL[0]B (=logically inverted signal of the test output signal IOHL[0]) according to the output switching signal IOHL[1]. is selected and output as the gate signal G0 of the transistor 180.

More specifically, the multiplexer MUXO sets the output signal of the OR gate OR20 to the gate signal G0 when IOHL[1]="0", and the inversion test when IOHL[1]="1". Assume that the output signal IOHL[0]B is the gate signal G0.

The register 175 stores setting values of the output switching signal IOHL[1] and the test output signal IOHL[0]. Note that output switching signal IOHL[1] and test output signal IOHL[0] can be arbitrarily set from microcomputer 300 via SPI interface 190 that receives respective external inputs.

FIG. 13 is a timing chart showing an example of the diagnostic operation (the operation of detecting sticking of the XRSTOUT pin by the microcomputer 300) in the fourth embodiment. The SPI communication state of the test output signal IOHL[0] is depicted.

First, the microcomputer 300 sets the output switching signal IOHL[1] to "1" through SPI communication. As a result, after time t31 when writing to the register 175 is completed, the output control of the XRSTOUT pin shifts from normal control to manual control. Note that the initial value of the test output signal IOHL[0] is "0". Therefore, immediately after the shift to manual control, the transistor 180 is turned on and the reset output signal XRSTOUT falls to the low level (initial state).

Next, the microcomputer 300 sets the test output signal IOHL[0] to "1" through SPI communication. As a result, after time t32 when writing to the register 175 is completed, the transistor 180 is turned off and the reset output signal XRSTOUT is pulled up to high level. Therefore, by monitoring the reset output signal XRSTOUT, the microcomputer 300 can diagnose whether the transistor 180 is normally turned off (=whether the reset signal XRSTOUT correctly rises to a high level).

Subsequently, the microcomputer 300 sets the test output signal IOHL[0] to "0" through SPI communication. As a result, after time t33 when writing to the register 175 is completed, the transistor 180 turns on and the reset output signal XRSTOUT falls to low level. Therefore, by monitoring the reset output signal XRSTOUT, the microcomputer 300 can diagnose whether the transistor 180 is normally turned on (=whether the reset signal XRSTOUT correctly falls to low level).

Finally, the microcomputer 300 sets the output switching signal IOHL[1] to "0" through SPI communication. As a result, after time t34 when writing to the register 175 is completed, the output control of the XRSTOUT pin shifts from manual control to normal control, and the series of diagnostic operations described above is completed.

As described above, the monitoring IC 100 of the present embodiment can detect sticking failures of the XRSTOUT pin by SPI control using the microcomputer 300, so that reliability can be improved.

As the transistor 180, instead of an open-drain N-channel MOSFET whose drain is connected to the XRSTOUT pin, an open-collector npn bipolar transistor whose collector is connected to the XRSTOUT pin may be used.

In addition, in this embodiment, only the XRSTOUT pin is focused, but if the sticking detection function similar to the above is introduced for other external terminals (PG1 to PG4 pins and MISO pin) having an open drain output stage. good.

<Application to vehicles>
FIG. 14 is an external view showing one configuration example of the vehicle X. As shown in FIG. The vehicle X of this configuration example is equipped with various electronic devices (in-vehicle devices) X11 to X18 that operate by being supplied with power from a battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, and other electronic devices built into vehicle X at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

Note that the monitoring IC 100 described above can be incorporated in any of the electronic devices X11 to X18.

<Other Modifications>
In the above-described embodiment, a monitoring IC mounted on an on-vehicle device was taken as an example, but the application target is not limited to this, and it is possible to apply it widely to electronic devices in general.

In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments. It is to be understood that a range and equivalents are meant to include all changes that fall within the range.

The invention disclosed in this specification can be used, for example, in general electronic devices that require functional safety (vehicle cameras, radars, infotainment, lamps, clusters, power trains, sensor fusion, etc.). is possible.

1 electronic device 100 monitoring IC (monitoring device)
REFERENCE SIGNS LIST 101 Resin sealing body 102 External terminal 103 Heat dissipation pad 103a Notch 111 Reference voltage generation unit 112 Sub-reference voltage generation unit 120 Reference voltage detection unit 121, 122 Divided voltage generation unit 123, 124 Comparator 130 UVLO unit 140 to 149 Threshold voltage Generation unit 150 to 159, 15A, 15B Comparator 161 Oscillator (for digital processing)
162 oscillator (for watchdog timer)
170 digital processing unit 171 self-diagnosis unit 172 clock detection unit 173 watchdog timer 174 second self-diagnosis unit 174a pattern table 174b expected value table 175 registers 180 to 184 N-channel MOS field effect transistor 190 SPI interface 200 power management IC ( power supply)
300 Microcomputer C1, C2 Capacitor CNT0 to CNT5 Counter FLT0 to FLT5 Filter MUX, MUX1, MUX2, MUXO Multiplexer OR0 to OR5, OR10 to OR14, OR20 OR gate R1 to R10, R12 to R16 Resistor T1, T2, T10 to T15 Test Circuit X Vehicle X11-X18 Electronic equipment

Claims (7)

a monitoring unit that detects anomalies in a monitoring target;
a self-diagnosis unit that diagnoses whether the monitoring unit is normal;
a sub-monitoring unit that substitutes for the monitoring unit during diagnosis of the monitoring unit by the self-diagnosing unit and detects an abnormality in the monitoring target;
has
The monitoring device, wherein the sub-monitoring unit sequentially replaces a monitoring unit that is being diagnosed among the plurality of monitoring units provided for each of a plurality of monitoring targets. 2. The monitoring apparatus according to claim 1, wherein said sub-monitoring unit replaces said monitoring unit and continues abnormality detection of said monitored object when said monitoring unit is diagnosed as not normal. 3. The monitoring device according to claim 1, wherein said self-diagnosis unit diagnoses whether said sub-monitoring unit is normal during operation of said monitoring unit. an output signal generation unit that receives an input signal from the monitoring unit and generates an output signal;
a second self-diagnosis unit for diagnosing whether the output signal generation unit is normal by inputting a test input signal of a predetermined pattern to the output signal generation unit and determining an expected value of the output signal;
A monitoring device according to any one of claims 1 to 3, further comprising: an open- drain or open- collector transistor ; and
a multiplexer that outputs one of the output signal and the test output signal to the transistor in response to an output switching signal;
an interface that accepts an external input of the output switching signal and the test output signal;
5. The monitoring device of claim 4, further comprising: An electronic device comprising the monitoring device according to any one of claims 1 to 5 . A vehicle comprising the electronic device according to claim 6 .

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