JP7298442B2 - Electronic control device, control method by main processor of electronic control device, and control program executed by main processor of electronic control device - Google Patents

Description

The present invention relates to an electronic control device, a control method by a main processor of the electronic control device, and a control program executed by the main processor of the electronic control device.

2. Description of the Related Art An image forming apparatus such as a multifunction printer called an MFP (MultiFunction Printer) is required to reduce power consumption in a standby state. For this reason, the image forming apparatus has, for example, a main CPU (Central Processing Unit) to which power supply is stopped during the energy saving mode, and a sub CPU to which power is always supplied including during the energy saving mode. . During the energy saving mode, power supply to engines such as printers and scanners is also stopped.

The main CPU executes overall control of the image forming apparatus including execution of printing operations and the like. The sub CPU controls the image forming apparatus in the energy saving mode, monitors the occurrence of a recovery factor from the energy saving mode, and, when detecting the occurrence of the recovery factor, recovers the engine earlier than the recovery of the main CPU. As a result, the operation after recovery from the energy saving mode is started earlier than in the case where the engine is recovered from the main CPU after the main CPU is recovered (Patent Document 1).

In general, an electronic control device such as an image forming device has an RTC (Real Time Clock) that needs to be updated periodically. Action needs to be taken. For example, in an electric control device that performs update processing for multiple types of modules with mutually different update intervals while the main CPU is starting and stopping repeatedly, a method for performing multiple types of update processing without causing an error. Also, no method has been proposed for suppressing an increase in the activation frequency.

The disclosed technique has been made in view of the above problems, and aims to perform multiple types of update processing during startup without causing an error by a main processor that repeatedly starts and stops. do.

In order to solve the above technical problem, an electronic control device according to one aspect of the present invention includes a main processor that repeatedly starts and stops, and an update timer that sets an update time that determines the next start timing of the main processor. and a sub-processor that always operates, wherein the main processor includes a main processor control unit that controls the start and stop of the main processor; an update factor storage unit that stores an update interval, an allowable delay time indicating a delay time allowed for the update interval, and a previous update time indicating the previous update time, corresponding to each of the update factors; an update time calculator for calculating the update time to be set in the update timer from the update interval, the allowable delay time and the previous update time stored in the update factor storage unit, and the current time; and the update time. and an update timer setting control unit that controls setting of the update time calculated by the calculation unit to the update timer.

It is possible to perform multiple types of update processing during activation by the main processor, which repeatedly starts and stops, without causing an error.

1 is a block diagram showing an example of an electronic control device according to a first embodiment of the invention; FIG. FIG. 2 is a functional block diagram showing an example of functions of main parts of the electronic control unit of FIG. 1; 2 is a sequence diagram showing an example of the operation of the electronic control device of FIG. 1; FIG. 2 is a timing chart showing an example of the operation of a main CPU of the electronic control unit of FIG. 1; FIG. FIG. 5 is a functional block diagram showing an example of functions of main parts of an electronic control device according to a second embodiment of the present invention; 6 is a timing chart showing an example of the operation of the main CPU of the electronic control unit of FIG. 5 in an energy saving effect priority mode; FIG. FIG. 7 is a timing chart showing the continuation of the operation of FIG. 6; 6 is a timing chart showing an example of the operation of the main CPU of the electronic control unit of FIG. 5 in an operation delay elimination priority mode; FIG. FIG. 9 is a timing chart showing the continuation of the operation of FIG. 8; FIG. 6 is a flow chart showing an example of the operation of the main CPU of the electronic control unit of FIG. 5; FIG. 5 is a timing chart showing an example (comparative example) of the operation of a main CPU of another electronic control device;

Hereinafter, embodiments will be described with reference to the drawings. In addition, in each drawing, the same code|symbol may be attached|subjected to the same component part, and the overlapping description may be abbreviate|omitted.

(First embodiment)
FIG. 1 is a block diagram showing an example of an electronic control device according to a first embodiment of the invention. An electronic control device 100 shown in FIG. 1 is, for example, an image forming device such as a multifunction machine. The electronic control device 100 may be an image forming device having a single function, such as a scanner, printer, or facsimile, or may be a projector, an electronic blackboard, or the like.

The electronic control unit 100 has an engine section 10, a main CPU 20, a sub CPU 30, a memory 40, a nonvolatile memory 50, an RTC (Real Time Clock) 60, and the like. The electronic control unit 100 includes, in addition to those shown in FIG. may have The engine section 10 has a printer unit, a fixing unit, a transport unit, and the like.

The main CPU 20 controls the overall operation of the electronic control unit 100 and executes scanner operation, printer operation, copy operation, and the like. Further, the main CPU 20 stores a snapshot of the operation program in the non-volatile memory 50 and stops the operations of the main CPU 20 and the memory 40 when shifting to the energy saving mode. For example, a snapshot is data in a state in which the boot program has been expanded in the memory 40 .

The main CPU 20 calculates the update time to be set in the update timer 32 mounted on the sub CPU 30, and notifies the sub CPU 30 of the calculated update time, thereby controlling the setting of the update time (set value) to the update timer 32. implement. The energy saving mode is hereinafter also referred to as the energy saving mode.

The sub CPU 30 controls the power supplied to the electronic control unit 100, and also controls transition to and return from the energy saving mode of the main CPU 20. FIG. For example, the energy saving mode is shifted to when an operation unit (not shown) is not operated for a predetermined time or longer. When shifting to the energy saving mode, sub CPU 30 stops supplying power to main CPU 20 and memory 40 after a snapshot of the operation program is stored in nonvolatile memory 50 by main CPU 20 . At this time, power supply to the nonvolatile memory 50 may also be stopped.

The main CPU 20 repeats starting and stopping, and the sub CPU 30 always operates. The main CPU 20 and the sub CPU 30 may be processors other than the CPU. The main CPU 20 is an example of a main processor, and the sub CPU 30 is an example of a sub processor.

Recovery from the energy-saving mode is performed when the update time set in the update timer 32 has elapsed, or upon occurrence of a recovery factor such as operation of an operation unit (not shown). When returning the main CPU 20 from the energy-saving mode, the sub CPU 30 supplies power to the main CPU 20 and the memory 40, causes the main CPU 20 to execute a process of expanding the snapshot from the nonvolatile memory 50 to the memory 40, and restarts the main CPU 20. start it up. By expanding the boot program from the non-volatile memory 50 to the memory 40 at the time of restarting, the startup time of the main CPU 20 can be shortened.

For example, the memory 40 is a main memory such as a DRAM (Dynamic Random Access Memory), and stores various programs executed by the main CPU 20 and data used by the various programs. For example, the non-volatile memory 50 is a flash memory, stores a program to be developed in the memory 40, and temporarily stores the snapshot. The RTC 60 operates by power received from a battery (not shown) and keeps time. For example, the RTC (hardware clock) requires periodic updating (correction) to maintain accuracy, such as matching it with the system clock.

FIG. 2 is a functional block diagram showing an example of functions of main parts of the electronic control unit 100 of FIG. It should be noted that FIG. 2 shows functional blocks related to the control of starting and stopping of the main CPU 20 by the main CPU 20 and the sub CPU 30 .

The main CPU 20 has a main CPU control section 21 , an update time calculation section 22 , an update factor table 23 and an update timer notification section 24 . The sub CPU 30 has a sub CPU control section 31 and an update timer 32 .

For example, the functions of the main CPU control section 21, the update time calculation section 22, and the update timer notification section 24 are realized by the main CPU 20 executing a control program. The update factor table 23 may be implemented using a rewritable storage unit such as a built-in RAM or a register built into the main CPU 20, or may be implemented using a rewritable non-volatile storage unit built into the main CPU 20. may be implemented. Note that the main CPU control unit 21, the update time calculation unit 22, and the update timer notification unit 24 may be realized by hardware.

For example, the functions of the sub CPU control unit 31 are realized by the sub CPU 30 executing a control program. The update timer 32 is implemented using an internal timer installed in the sub CPU 30, but may be implemented by a control program executed by the sub CPU 30. FIG.

The main CPU control unit 21 performs a pause process (stop process) of the main CPU 20 when shifting to the energy saving mode, and performs a startup process of the main CPU 20 when returning from the energy saving mode. The main CPU control unit 21 stores a snapshot of the operating program in the non-volatile memory 50 in the pause processing. In the activation process, the main CPU control unit 21 expands the snapshot from the nonvolatile memory 50 to the memory 40, activates the main CPU 20, and causes the update time calculation unit 22 to calculate the update time until the next update process is performed. . Here, the snapshot saved in the nonvolatile memory 50 may include information held by the update factor table 23 . The main CPU control section 21 is an example of a main processor control section that controls the start and stop of the main CPU 20 .

Based on an instruction from the main CPU control unit 21, the update time calculation unit 22 refers to the update factor table 23 and calculates the update time, which is the time until the next update process is performed. The update timer notification unit 24 notifies the sub CPU 30 of the update time calculated by the update time calculation unit 22 , thereby causing the sub CPU 30 to set the update time of the update timer 32 . Note that the update timer notification unit 24 may set the update time to the update timer 32 instead of notifying the sub CPU 30 of the update time. The update timer notification unit 24 is an example of an update timer setting control unit that controls setting of the update time calculated by the update time calculation unit 22 to the update timer 32 .

The update factor table 23 has an area for storing an update interval, an allowable delay time, and a previous update time for each of the modules Mod1 and Mod2 (update factors) that need to be updated at predetermined intervals. The update interval indicates the basic update interval of each module Mod1 and Mod2 until the next update process. The allowable delay time indicates the allowable delay time from the update interval.

Therefore, the shortest update interval of each module Mod1 and Mod2 is the update interval, and the maximum update interval of each module Mod1 and Mod2 is the sum of the update interval and the allowable delay time. The previous update time indicates the start time of the update process performed immediately before, and indicates the start time of the previous or current update process. For example, the previous update time is the same as the boot time of the main CPU 20 . The update interval, the allowable delay time, and the previous update time are not limited to being stored in the update factor table 23, but may be stored in a register or memory. The update factor table 23 is an example of an update factor storage unit.

The update factor table 23 shown in FIG. 2 indicates that the module Mod1 can extend the start time of the update process by up to 1 second after the update interval of 1 second has elapsed. Module Mod2 indicates that the start time of the update process can be further extended up to 0.4 seconds after the update interval of 2.4 seconds has elapsed. Hereinafter, the update process by the module Mod1 is also called the update process Mod1, and the update process by the module Mod2 is also called the update process Mod2.

The sub CPU control unit 31 sets the update time notified from the update timer notification unit 24 to the update timer 32 and activates the update timer 32 . Note that the sub CPU control unit 31 may control the power supplied to the electronic control unit 100 described above, the transition of the main CPU 20 to the energy saving mode, and the return of the main CPU 20 from the energy saving mode. For example, when the set update time has passed, the update timer 32 outputs information indicating the elapse of the update time to the functional unit in the sub CPU 30 that controls activation of the main CPU 20 . Information indicating the elapse of the update time may be notified by interrupt processing.

FIG. 3 is a sequence diagram showing an example of the operation of electronic control unit 100 of FIG. The sequence shown in FIG. 3 is started when the update time set in the update timer 32 has passed and the main CPU 20 is activated. The sequence shown in FIG. 3 is implemented by the main CPU 20 executing the control program. That is, the sequence shown in FIG. 3 shows an example of a control method by the main CPU 20, and shows an example of processing performed by a control program executed by the main CPU 20. FIG.

Note that, in parallel with the operation shown in FIG. 3, update processing of the update target module Mod (one or both of Mod1 and Mod2) is performed. After setting the update time to the update timer 32 and updating the module Mod to be updated, the operation of the main CPU 20 is stopped by the sub CPU control unit 31 .

The main CPU control unit 21 outputs an update time calculation request requesting calculation of the next update time of the module Mod to the update time calculation unit 22 (FIG. 3(a)).

Based on the update time calculation request, the update time calculator 22 refers to the update factor table 23 and acquires update factor information (update interval and allowable delay time for each module Mod1 and Mod2) (FIG. 3(b)). . In FIG. 3, dashed arrows indicate completion notifications and the like indicating processing responses. For example, the response based on the update time calculation request includes update factor information (update interval and allowable delay time) read from the update factor table 23 .

The update time calculator 22 uses the acquired update factor information to calculate the next update time (FIG. 3(c)). Note that the update time calculator 22 sets the current update time in the previous update time area of the update cause table 23 corresponding to the module (for example, Mod1) that performs the current update process. Then, the update time calculation unit 22 uses the previous update time set in the update factor table 23 as the reference time, and uses the update interval and the allowable delay time to calculate the next update time (that is, the next update time). Calculate

The update time calculation unit 22 notifies the update timer notification unit 24 of the calculated update time (FIG. 3(d)). Note that setting of the previous update time to the update factor table 23 may be performed after notification of the update time to the update timer notification unit 24 .

The update timer notification unit 24 notifies the sub-CPU control unit 31 of the notified update time, and causes the sub-CPU control unit 31 to set the update timer 32 (FIG. 3(e)). The update timer 32 starts timing the set update time. Note that the update timer 32 may be set directly from the update timer notification unit 24 . Then, when the update time set in the update timer 32 has elapsed, the sub-CPU control unit 31 controls activation of the stopped main CPU 20 .

FIG. 4 is a timing chart showing an example of the operation of the main CPU 20 of the electronic control unit 100 of FIG. 4 includes operations according to the control method executed by the main CPU 20 shown in FIG. 2, and includes operations according to the control program executed by the main CPU 20. FIG. That is, FIG. 4 shows an example of a control method by the main CPU 20, and shows an example of processing performed by a control program executed by the main CPU 20. As shown in FIG. In FIG. 4, the time is indicated only by the number of seconds in order to make the explanation easier to understand.

In the operation shown in FIG. 4, the main CPU 20 is activated at time 122.0 seconds in order to perform the update processes Mod1 and Mod2, and the main CPU 20 is stopped again after, for example, 0.2 seconds (FIG. 4(a)). . During 0.2 seconds, the update processes Mod1 and Mod2 are performed and the update timer 32 is reset. Based on the update time set in the update timer 32, the main CPU 20 is repeatedly started and stopped. Note that the main CPU 20 may have three or more modules that require update processing. In this case, a multi-row area is allocated to the update factor table 23 shown in FIG. 2 according to the number of modules.

The update time calculator 22 stores the current time=122.0 seconds in the previous update time corresponding to the modules Mod1 and Mod2 that perform update processing in the update factor table 23 (FIGS. 4B and 4C). ). Thus, the previous update time indicates not only the update time of the completed update processes Mod1 and Mod2, but also the update time of the unfinished update processes Mod1 and Mod2 (immediate previous update time). The update factor table 23 shown in FIG. 2 shows the state at this time.

The update time calculator 22 refers to the update interval, allowable delay time, and previous update time of the module Mod1 in the update factor table 23, and calculates the next settable updateable period from the previous update time=122.0 seconds. . For example, the update time calculation unit 22 updates the module Mod1 from the time (123.0 seconds) obtained by adding the update interval of the module Mod1 to the previous set time to the time (124.0 seconds) obtained by adding the allowable delay time. It is set as a possible period (FIG. 4(d)).

Similarly, the update time calculator 22 refers to the update interval, the allowable delay time, and the previous update time of the module Mod2, and calculates the next settable updateable period from the previous update time=122.0 seconds. For example, the update time calculation unit 22 updates the module Mod2 from the time (124.4 seconds) obtained by adding the update interval of the module Mod2 to the previous setting time to the time (124.8 seconds) obtained by adding the allowable delay time. It is set as a possible period (FIG. 4(e)).

Since the updatable periods of the update processes Mod1 and Mod2 do not overlap, the update time calculation unit 22 decides to perform the update process Mod1 with the closest updatable period at the next update time, and postpones the update process Mod2. to decide. Note that execution of the update process Mod1 at the next update time may be stored as a snapshot in the non-volatile memory 50 and referred to when the main CPU 20 is booted next time.

The update time calculator 22 determines to set the next update time to 1 second later, and notifies the module Mod1 of the update time, which is the time after the update time elapses. 32 is set to "1 second" (FIG. 4(f)). Thus, the update time calculator 22 can calculate the updateable period for each of the modules Mod1 and Mod2 by using the update interval, the allowable delay time, and the previous update time of the update factor table 23 . Then, the update time calculation unit 22 can calculate the module to be updated next (one or both of Mod1 and Mod2) and the update time based on the calculated updatable period.

After that, the main CPU 20 that has stopped operating is restarted at time=123.0 seconds (FIG. 4(g)). The update time calculator 22 stores the current time=123.0 seconds in the previous update time corresponding to the module Mod1 that performs the update process in the update factor table 23 (FIG. 4(h)). Then, based on the activation of the main CPU 20, the module Mod1 whose update time has been notified in advance performs the update process (FIG. 4(i)). Here, the previous update time of the module Mod1 is the previous update time (123.0 seconds), and the previous update time of the module Mod2 is literally the previous update time (122.0 seconds).

The update time calculator 22 calculates that the next updatable period of the module Mod1 that has undergone the update process is 1 second from 124.0 seconds to 125.0 seconds in the same manner as described above ((j) in FIG. 4). ). The update time calculator 22 calculates that the next settable updateable period for the postponed update process Mod2 is 0.4 seconds from 124.4 seconds to 124.8 seconds (Fig. 4 (k)).

The updatable period of the update process Mod2 is calculated by referring to the update interval, the allowable delay time, and the previous update time of the module Mod2 in the update factor table 23 in the same manner as in the update process described above. That is, the update time calculation unit 22 calculates the time (124.4 seconds) obtained by adding the update interval to the previous update time (122.0 seconds) of the module Mod2, and the time (124.8 seconds) obtained by adding the allowable delay time. is the renewal period.

Since the updatable periods of the update processes Mod1 and Mod2 overlap, the update time calculator 22 determines to start both the update processes Mod1 and Mod2 within the period in which the updatable periods overlap. In this example, the update time calculator 22 determines to start the next update processes Mod1 and Mod2 at time=124.4 seconds. Then, the update time calculator 22 notifies the modules Mod1 and Mod2 of the update time, and sets "1.4 seconds" to the update timer 32 via the update timer notification unit 24 ((l) in FIG. 4). In subsequent operations as well, based on the information of the modules Mod1 and Mod2 stored in the update factor table 23, the set value of the update timer 32 corresponding to the startup time of the main CPU 20 is set appropriately for each update process. is set to

As described above, in this embodiment, the main CPU 20 has the update factor table 23 that stores the update interval, the allowable delay time, and the previous update time for each of the modules Mod1 and Mod2. As a result, the update time calculator 22 can calculate the updatable period for each of the modules Mod1 and Mod2 by using the update interval, the allowable delay time, and the previous update time of the update factor table 23 . Then, the update time calculation unit 22 can calculate the module to be updated next (one or both of Mod1 and Mod2) and the update time based on the calculated updatable period.

As a result, a plurality of types of update processes Mod1 and Mod2 that the main CPU 20, which repeats starting and stopping, performs during start-up can be performed while the main CPU 20 is starting. In other words, the update processing of the modules Mod1 and Mod2 having at least one of the update interval and the allowable delay time different from each other can be performed without causing an error. On the other hand, if the updatable period of the module Mod1 or Mod2 is out of the activation period of the main CPU 20, the module Mod1 or Mod2 cannot be updated within the updatable period, causing a timeout error or the like.

(Second embodiment)
FIG. 5 is a functional block diagram showing an example of functions of main parts of an electronic control unit according to the second embodiment of the present invention. Elements similar to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted. The electronic control unit 100A shown in FIG. 5 has a main CPU 20A instead of the main CPU 20 shown in FIG. The configuration of the electronic control unit 100A excluding the main CPU 20A is the same as the configuration of the electronic control unit 100 shown in FIG. For example, the electronic control device 100A is an image forming device such as a multifunction machine, but may be an image forming device having a single function such as a scanner, printer, or facsimile, or may be a projector, an electronic blackboard, or the like.

The main CPU 20A has a main CPU control section 21, an update time calculation section 22A, an update factor table 23, an update timer notification section 24 and a mode register 25. The sub CPU 30 has a sub CPU control section 31 and an update timer 32 as in FIG.

In addition to the function of the update time calculation unit 22 shown in FIG. 2, the update time calculation unit 22A has a function of changing the calculation method of the update time set in the update timer 32 according to the value set in the mode register 25. have. The mode register 25 is set to "0" in the energy saving effect priority mode, and is set to "1" in the operation delay elimination priority mode. Note that the main CPU 20A may have three or more priority modes, and in this case, the mode register 25 holds a set value that allows identification of each priority mode.

For example, the setting of the priority mode by the mode register 25 is performed by the user using the electronic control unit 100A operating the selection screen displayed on the display device equipped with the touch panel function included in the electronic control unit 100A. As a result, the priority mode can be set according to the usage environment of the electronic control unit 100A desired by the user.

A display device equipped with a touch panel function is an example of an operation unit that can be operated by a user. The mode register 25 is an example of an operation mode storage unit that stores operation modes according to user's operation of the operation unit.

The energy saving effect priority mode is an operation mode that gives priority to the energy saving performance of the main CPU 20A and gives priority to reducing the power consumption of the main CPU 20A. In the energy saving effect priority mode, the update time calculator 22A effectively uses the allowable delay time set in the update factor table 23 to determine the next update time.

The operation delay elimination priority mode is an operation mode in which the update processing of the modules Mod1 and Mod2 is performed at an early timing, thereby eliminating the operation delay of the functional units using the modules Mod1 and Mod2 and eliminating the operation delay of the electronic control unit 100A. is. In the operation delay elimination priority mode, the update time calculator 22A suppresses the use of the allowable delay time set in the update factor table 23 and determines the next update time based on the update interval. As shown in FIGS. 6 to 9, the update frequency of the plurality of modules in the energy saving effect priority mode is set lower than the update frequency of the plurality of modules in the operation delay elimination priority mode.

6 and 7 are timing charts showing an example of the operation in the energy saving effect priority mode of the main CPU 20A of the electronic control unit 100A of FIG. FIG. 7 shows a continuation of FIG. 6 and 7 include operations by the control method by the main CPU 20A of the electronic control unit 100A, and include operations by the control program of the electronic control unit 100A executed by the main CPU 20A. That is, FIGS. 6 and 7 show an example of a control method by the main CPU 20A, and show an example of processing performed by a control program executed by the main CPU 20A. A detailed description of the same operations as in FIG. 4 will be omitted. The sequence of operations of the electronic control unit 100A is the same as in FIG.

In the operation shown in FIG. 6, as in FIG. 4, the main CPU 20A is activated at time 122 seconds in order to perform the update processes Mod1 and Mod2, and the main CPU 20A is stopped after 0.2 seconds (FIG. ).

The update time calculator 22A sets the current update time = 122.0 seconds in the previous update time area of the update factor table 23 corresponding to the modules Mod1 and Mod2 that are to be updated this time ((b) in FIG. 6). , (c)). The update time calculator 22A refers to the update factor table 23 and calculates the next updatable period of the update process Mod1 to be 1 second from 123.0 seconds to 124.0 seconds (FIG. 6(d)). Further, the update time calculator 22A calculates the next updatable period of the update process Mod2 to be 0.4 seconds from 124.4 seconds to 124.8 seconds (FIG. 6(e)).

Since the updatable periods of the update processes Mod1 and Mod2 do not overlap, the update time calculator 22A determines to perform the update process Mod1 with the closest updatable period at the next update time. However, in the energy-saving effect priority mode, in order to reduce the activation frequency of the main CPU 20A as much as possible, the next update time is set to 2 seconds later (time = 124.0 seconds) in accordance with the end of the updateable period of the update processing Mod1. to decide. In other words, the update time calculator 22A calculates the update time until the module Mod1 executes the update process based on the total time of the update interval and the allowable delay time stored in the update factor table 23. Then, the update time calculator 22A notifies the module Mod1 of the update time and sets the update timer 32 to "2 seconds" (FIG. 6(f)).

Based on the elapse of the update time set in the update timer 32, the main CPU 20A is activated again at time=124.0 seconds (FIG. 6(g)). Update processing is performed at the time (FIG. 6(h)). The update time calculator 22A sets the current update time=124.0 seconds in the previous update time area corresponding to the module Mod1 in the update factor table 23 (FIG. 6(i)).

The update time calculator 22A refers to the update factor table 23 and calculates the next updatable period of the update process Mod1 to be 1 second from 125.0 seconds to 126.0 seconds (FIG. 6(j)). Since the updatable periods of the update processes Mod1 and Mod2 do not overlap, the update time calculator 22A determines to perform the update process Mod2 with the closest updatable period at the next update time.

Since the mode is the energy saving effect priority mode, the update time calculation unit 22A sets the next update time to 0.8 seconds later (time=124.8 seconds) in line with the end of the updateable period of the update processing Mod2. decide. In other words, the update time calculator 22A calculates the update time until the module Mod2 executes the update process based on the total time of the update interval and the allowable delay time stored in the update factor table 23. Then, the update time calculator 22A notifies the module Mod2 of the update time and sets the update timer 32 to "0.8 second" (FIG. 6(k)).

Based on the elapse of the update time set in the update timer 32, the main CPU 20A is activated again at time=124.8 seconds ((l) in FIG. 6). Update processing is performed at the time (FIG. 6(m)). The update time calculator 22A sets the current update time=124.8 seconds in the previous update time area corresponding to the module Mod2 in the update factor table 23 (FIG. 6(n)).

The update time calculator 22A refers to the update factor table 23 and calculates the next updatable period of the update process Mod2 to be 1 second from 127.2 seconds to 127.6 seconds (FIG. 7(a)). In FIG. 6, the updatable period of the update process Mod2 (time=124.4 seconds to 124.8 seconds) and the updatable period of the update process Mod1 (time=125.0 seconds to 126.0 seconds) do not overlap. .

However, the updatable period of the update process Mod1 overlaps with the end of the activation period (0.2 seconds) of the main CPU 20 for executing the update process Mod2. In this case, after the update process Mod2 is performed, the frequency of starting the main CPU 20A can be lowered and the power consumption can be reduced by continuously performing the update process Mod1 without stopping the main CPU 20A.

Therefore, even in the energy saving effect priority mode, the update time calculation unit 22A sets the next update time to 0.2 seconds later (time=125.0 seconds) in accordance with the beginning of the update possible period of the update processing Mod1. decide to Then, the update time calculator 22A notifies the module Mod1 of the update time and sets the update timer 32 to "0.2 seconds" (FIG. 6(o)).

In other words, when the timing for the next activation of the main CPU 20A based on the update time calculated by the update time calculator 22A is included in the activation period of the main CPU 20A, the activation period of the main CPU 20A is extended. Then, both the update processes of the modules Mod1 and Mod2 are performed during the activation period. By lowering the activation frequency of the main CPU 20A, the power consumption required for stopping and starting the main CPU 20A can be reduced, and the power consumption of the electronic control unit 100A can be reduced.

While the main CPU 20A is running, the module Mod1 executes update processing at time=125.0 seconds based on the elapse of the update time set in the update timer 32 (FIG. 6(p)). The update time calculator 22A sets the current update time=125.0 seconds in the previous update time area corresponding to the module Mod1 in the update factor table 23 (FIG. 6(q)).

The update time calculator 22A refers to the update factor table 23 and calculates the next updatable period of the update process Mod1 to be 1 second from 126.0 seconds to 127.0 seconds (FIG. 7(b)). Since the updatable periods of the update processes Mod1 and Mod2 do not overlap, the update time calculator 22A determines to perform the update process Mod1 with the closest updatable period at the next update time. Since the mode is the energy saving effect priority mode, the update time calculation unit 22A determines the next update time to be two seconds later (time=127.0 seconds) in line with the end of the updateable period of the update processing Mod1. . Then, the update time calculator 22A notifies the module Mod1 of the update time and sets the update timer 32 to "2 seconds" (FIG. 6(r)).

Next, after the update time set in the update timer 32 has elapsed, the main CPU 20A is activated again at time=127.0 seconds (FIG. 7(c)). executes update processing at the update time (FIG. 7(d)). The update time calculator 22A sets the current update time=127.0 seconds in the previous update time area corresponding to the module Mod1 in the update factor table 23 (FIG. 7(e)).

The update time calculator 22A refers to the update factor table 23 and calculates the next updatable period of the update process Mod1 to be 1 second from 128.0 seconds to 129.0 seconds (FIG. 7(f)). The updatable period of the update process Mod1 (time=126.0 seconds to 127.0 seconds) and the updatable period of the update process Mod2 (time=127.2 seconds to 127.6 seconds) do not overlap. However, if the update process Mod2 is continuously performed without stopping the main CPU 20A after the update process Mod1 is performed, the activation frequency of the main CPU 20A is lowered and the power consumption can be suppressed. Therefore, in the same manner as described above, the update time calculator 22A determines that the next update time of the update process Mod2 is 0.2 seconds later (time=127.2 seconds), and sets the update time to the module Mod2. Along with notification, the update timer 32 is set to "0.2 seconds" (FIG. 7(g)).

The module Mod2 executes update processing at time=127.2 seconds based on the elapse of the update time set in the update timer 32 during the boot period of the main CPU 20A ((h) in FIG. 7). The update time calculator 22A sets the current update time=127.2 seconds in the previous update time area corresponding to the module Mod2 in the update factor table 23 (FIG. 7(i)).

The update time calculator 22A refers to the update factor table 23 and calculates the next updateable period (not shown) of the update process Mod2. Since the updatable periods of the update processes Mod1 and Mod2 do not overlap, the update time calculator 22A determines to perform the update process Mod1 with the closest updatable period at the next update time. Since the mode is the energy saving effect priority mode, the update time calculation unit 22A sets the next update time to 1.8 seconds later (time=129.0 seconds) in line with the end of the updatable period of the update processing Mod1, as described above. ). Then, the update time calculator 22A notifies the module Mod1 of the update time and sets the update timer 32 to "1.8 seconds" (FIG. 7(j)).

After that, similarly to the above, based on the information of the modules Mod1 and Mod2 stored in the update factor table 23, the update time corresponding to the start time of the main CPU 20A is updated so that the frequency of starting the main CPU 20A is reduced. A timer 32 is set. In FIGS. 6 and 7, the main CPU 20A is activated four times and update processes Mod1 and Mod2 are performed seven times during the seven seconds from time=122.0 seconds to 129 seconds. Therefore, the frequency of update processes Mod1 and Mod2 is once/second.

8 and 9 are timing charts showing an example of the operation of the main CPU 20A of the electronic control unit 100A of FIG. 5 in the operation delay elimination priority mode. FIG. 9 shows a continuation of FIG. Detailed descriptions of operations similar to those in FIGS. 4, 6, and 7 are omitted. 8 and 9 include operations by the control method by the main CPU 20A of the electronic control unit 100A, and operations by the control program of the electronic control unit 100A executed by the main CPU 20A. That is, FIGS. 6 and 7 show an example of a control method by the main CPU 20A, and show an example of processing performed by a control program executed by the main CPU 20A.

The operation from 122.0 seconds to 123.0 seconds is the same as in FIG. 6 except that the update timer 32 is set to "1 second". In the operation delay elimination priority mode, the update time calculator 22A adjusts the update time of each of the update processes Mod1 and Mod2 to the beginning of the updatable period calculated for each of the update processes Mod1 and Mod2 in order to reduce the delay of the update processes Mod1 and Mod2. set. In other words, the update time calculator 22A calculates the update time in the update processes Mod1 and Mod2 based on the update interval stored in the update factor table 23 .

Therefore, as shown in FIGS. 8 and 9, the update timer 32 is set for each of the update processes Mod1 and Mod2, and the main CPU 20A is activated for each of the update processes Mod1 and Mod2. However, if the update time set in the update timer 32 is 0.2 seconds or less, both the update processes Mod1 and Mod2 are executed during the startup period of the main CPU 20A (FIGS. 9A, 9B, and 9C). ), (d), (e), (f), (g), (h)). This can prevent the stop processing and start processing of the main CPU 20A from being inserted between the update processing Mod1 and Mod2. Therefore, for example, at time=127.0 seconds, the update process Mod1 can be started without delay, and at time=129.2 seconds, the update process Mod2 can be started without delay. Moreover, since the CPU 20A is activated less frequently, the power consumption of the main CPU 20A and the electronic control unit 100A can be suppressed.

In FIGS. 8 and 9, the main CPU 20A is activated eight times and the update processes Mod1 and Mod2 are performed ten times during the seven seconds from time=122.0 seconds to 129 seconds. Therefore, the frequency of update processes Mod1 and Mod2 is approximately 1.4 times/second. As described above, the update frequency of the modules Mod1 and Mod2 in the energy saving effect priority mode shown in FIGS. 6 and 7 can be made lower than the update frequency of the modules Mod1 and Mod2 in the operation delay elimination priority mode shown in FIGS. 8 and 9. I understand. In other words, the main CPU 20A can perform optimum operations according to the characteristics of the set operation mode.

FIG. 10 is a flowchart showing an example of the operation of the main CPU 20A of the electronic control unit 100A of FIG. The operation shown in FIG. 10 is started by the main CPU 20A executing the control program based on the activation of the main CPU 20A.

First, in step S10, the main CPU 20A refers to the mode register 25 and determines whether the operation mode is the energy saving effect priority mode or the operation delay elimination priority mode. The main CPU 20A performs step S12 when the operation mode is the energy saving effect priority mode, and performs step S14 when the operation mode is the operation delay elimination priority mode.

In step S12, the main CPU 20A calculates the update time based on the total time of the update interval and the allowable delay time stored in the update factor table 23, and shifts the process to step S16. In step S14, the main CPU 20A calculates the update time based on the update interval stored in the update factor table 23, and shifts the process to step S16.

In step S16, the main CPU 20A sets the update timer 32 to the update time calculated in step S12 or step S14. Next, in step S18, the main CPU 20A waits for a preset start-up period (for example, 0.2 seconds) to execute the update process Mod and calculate the update time. If so, the process proceeds to step S20. In step S20, the main CPU 20A stops after performing termination processing such as storing the snapshot in the non-volatile memory 50 and the like.

As described above, in the second embodiment, similarly to the above-described first embodiment, the update interval, the allowable delay time, and the previous update time of the update factor table 23 are used to determine which modules (Mod1, Mod2 ) and the update time can be calculated. As a result, the main CPU 20A, which repeats starting and stopping, can perform a plurality of types of update processes Mod1 and Mod2 during start-up without causing an error.

Furthermore, in the second embodiment, the update time to be set in the update timer 32 can be calculated according to the energy saving effect priority mode that prioritizes energy saving and the operation delay elimination priority mode that prioritizes processing performance. As a result, the power consumption of the main CPU 20A and the electronic control unit 100A can be reduced in the energy saving effect priority mode, and the operation delay of the main CPU 20A and the electronic control unit 100A can be eliminated in the operation delay elimination priority mode. That is, the main CPU 20A can perform optimum operations according to the characteristics of the set operation mode.

In the energy saving effect priority mode, the update time is calculated based on the total time of the update interval and the allowable delay time stored in the update factor table 23, and in the operation delay elimination priority mode, the update factor stored in the update factor table 23 is calculated. The update time is calculated based on the update interval. Accordingly, the update time calculator 22A can easily calculate the update time in each of the plurality of operation modes depending on whether or not the allowable delay time is taken into account.

If the next activation timing of the main CPU 20A based on the calculated update time is included in the activation period of the main CPU 20A, the activation period of the main CPU 20A is extended, and the update processes Mod1 and Mod2 are performed during the activation period. As a result, the activation frequency of the main CPU 20A is reduced, so that the power consumption required to stop and activate the main CPU 20A can be reduced, and the power consumption of the electronic control unit 100A can be reduced. Since the stop processing and start processing of the main CPU 20A are not inserted between two consecutive update processing Mods, the update processing Mod to be executed later can be started without delay.

By setting the energy saving effect priority mode or the operation delay elimination priority mode by the user operating the touch panel or the like, the operation mode can be set according to the usage environment of the electronic control unit 100A desired by the user. The update time calculator 22A can calculate the update time according to the operation mode by referring to the setting value of the mode register 25 set by the user.

(Comparative example)
FIG. 11 is a timing chart showing an example (comparative example) of the operation of the main CPU of another electronic control unit. A detailed description of the same operations as in FIG. 4 will be omitted.

The electronic control unit that executes the operation of FIG. 11 has a main CPU that repeats starting and stopping and a sub CPU that always operates, as in the above-described embodiment. However, the update time (set value of the update timer 32), which is the activation interval of the main CPU, is always set constant (for example, 1 second). For this reason, the main CPU is activated every second, executes the update process for 0.2 seconds, and stops the operation (FIG. 10(a)).

In this case, the update process Mod1 with an update interval of 1 second is normally executed, but the update process Mod2 with an update interval of 2.4 seconds is performed even if the allowable delay time of 0.4 seconds is taken into account. It cannot be executed during startup, and an error such as timeout occurs (FIG. 10(b)). In this way, when update processing of a plurality of modules (Mod1, Mod2, etc.) with mutually different update intervals is performed at a fixed update time, the update processing cannot be performed normally.

Although the present invention has been described above based on each embodiment, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without impairing the gist of the present invention, and can be determined appropriately according to the application form.

10 engine part 20, 20A main CPU
21 main CPU control unit 22, 22A update time calculation unit 23 update factor table 24 update timer notification unit 25 mode register 30 sub CPU
31 sub-CPU control unit 32 update timer 40 memory 50 non-volatile memory 60 RTC
100, 100A electronic controller

Japanese Patent Application Laid-Open No. 2009-132050

Claims (9)

a main processor that is repeatedly started and stopped;
a constantly operating sub-processor having an update timer in which an update time for determining the next activation timing of the main processor is set;
The main processor
a main processor control unit for controlling start and stop of the main processor;
An update interval, an allowable delay time indicating an allowable delay time for the update interval, and the previous update time are set corresponding to each of a plurality of update factors requiring update at a predetermined interval by the main processor. an update factor storage unit that stores the previous update time indicated by
an update time calculation unit that calculates the update time to be set in the update timer from the update interval, the allowable delay time, and the previous update time stored in the update factor storage unit, and the current time;
an update timer setting control unit that controls setting of the update time calculated by the update time calculation unit to the update timer;
An electronic control device comprising: The main processor has, as operation modes, an energy saving effect priority mode in which energy saving is prioritized and an operation delay elimination priority mode in which processing performance is prioritized,
the update frequency of the plurality of update factors in the energy saving effect priority mode is lower than the update frequency of the plurality of update factors in the operation delay elimination priority mode;
The electronic control device according to claim 1, characterized by: wherein, in the energy saving effect priority mode, the main processor calculates the update time based on the total time of the update interval and the allowable delay time stored in the update factor storage unit;
The electronic control device according to claim 2, characterized by: wherein, in the operation delay elimination priority mode, the main processor calculates the update time based on the update interval stored in the update factor storage unit;
The electronic control device according to claim 2, characterized by: The main processor extends the activation period of the main processor when the next activation timing based on the update time calculated by the update time calculation unit is included in the activation period of the main processor during activation, updating a plurality of said update factors during an activation period;
The electronic control device according to any one of claims 1 to 4, characterized by: Having an operation unit that can be operated by a user of the electronic control device,
The operation mode is set based on the operation of the operation unit by the user;
The electronic control device according to any one of claims 2 to 4, characterized by: an operation mode storage unit that stores the operation mode according to the operation of the operation unit by the user;
The update time calculation unit calculates the update time to be set in the update timer according to the operation mode set in the operation mode storage unit;
The electronic control device according to claim 6, characterized by: Control by the main processor of an electronic control device having a main processor that is repeatedly started and stopped, and a sub-processor that always operates and has an update timer that determines the next start timing of the main processor. a method,
An update interval, an allowable delay time indicating an allowable delay time for the update interval, and a previous update, which are respectively stored corresponding to a plurality of update factors requiring updating at predetermined intervals by the main processor. calculating the update time to be set in the update timer from the previous update time indicating the time and the current time;
controlling setting of the calculated update time to the update timer;
controlling start and stop of the main processor based on the operation of the update timer to which the update time is set;
A control method by a main processor of an electronic control device, characterized by: Executed by the main processor of an electronic control device having a main processor that repeatedly starts and stops, and a sub-processor that always operates and has an update timer that sets an update time for determining the next start timing of the main processor A control program for
An update interval, an allowable delay time indicating an allowable delay time for the update interval, and a previous update, which are respectively stored corresponding to a plurality of update factors requiring updating at predetermined intervals by the main processor. calculating the update time to be set in the update timer from the previous update time indicating the time and the current time;
controlling setting of the calculated update time to the update timer;
a process of controlling the starting and stopping of the main processor based on the operation of the update timer to which the update time is set;
A control program executed by a main processor of an electronic control unit, characterized by being executed by the main processor.

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