JP7293813B2 - semiconductor equipment - Google Patents

Description

The present invention relates to semiconductor devices.

When testing a memory that outputs serial data in synchronization with a clock, changing the phase of the clock for the first data, the middle data, and the last data shortens the test time of the timing margin test (for example, See Patent Document 1).

A memory controller with a memory monitoring function sequentially reads data from the memory based on a monitoring start instruction, determines whether there is an error and whether the error can be corrected, and corrects the data if correctable. (see, for example, Patent Document 2).

In a nonvolatile memory having a redundant area for relieving defective memory cells, by storing the defective address used for relieving in the cell array instead of programming it in the fuse, the chip area is reduced and the yield is improved (for example, patent Reference 3).

JP-A-6-36598 WO2006/100776 Japanese Patent Application Laid-Open No. 2000-260198

Recently, the amount of data handled by a processor such as a CPU (Central Processing Unit) tends to increase, and the storage capacity of memory accessed by the processor also tends to increase. In order to suppress an increase in memory latency due to an increase in storage capacity, a stacked memory has been used in which a plurality of memory chips are stacked to reduce the load capacity of wiring.

However, in a stacked memory, a plurality of memory chips are integrated by TSV (Through-Silicon Via) or the like, and the integrated memory chip is connected to a substrate such as a silicon interposer using bumps. Therefore, it is difficult to replace only the defective memory chip. Further, when a defect occurs in a memory chip, a serious failure such as system stop may occur. Therefore, it is preferable to detect the possibility of occurrence of a defect in advance and take preventive measures.

According to one aspect of the present invention, it is an object of the present invention to detect a memory block that may be defective in a stacked memory and stop using the memory block, thereby preventing the stacked memory from becoming defective. do.

According to one aspect, a semiconductor device includes a stacked memory including a plurality of stacked memories, and a test for executing a test with a reduced read margin for read data read from a plurality of memory blocks included in the plurality of memories. a first counter unit that holds the number of times an error occurs in the test by the test unit for each memory block; an error detection/correction unit that corrects a correctable error that occurs in the stacked memory; A second counter unit that holds the number of error corrections corrected by the detection/correction unit for each memory block, and a memory block in which the number of times held by the first counter unit exceeds a predetermined first threshold is used. and a memory management unit that prohibits the use of a memory block in which the number of error corrections held by the second counter unit exceeds a predetermined second threshold.

According to one aspect of the present invention, in a stacked memory, it is possible to prevent the stacked memory from becoming defective by detecting a memory block that may be defective and stopping the use of the memory block.

It is a figure which shows an example of the semiconductor device in one Embodiment. It is a figure which shows an example of the semiconductor device in another embodiment. 3 is a diagram showing an example of a main part of a test section in FIG. 2; FIG. 4 is a diagram showing an example of a set signal generated by the test section in FIG. 3; FIG. 4 is a diagram showing an example of a read test by the test section of FIG. 3; FIG. 3 is a diagram showing an example of the flow of user program processing executed by the CPU in FIG. 2; FIG. 3 is a diagram illustrating an example of a memory patrol startup flow executed by the CPU in FIG. 2; FIG. 3 is a diagram illustrating an example of a processing flow of memory patrol executed by the CPU in FIG. 2; FIG. 3 is a diagram showing an example of a processing flow for prohibiting use of a page executed by the CPU in FIG. 2; FIG. 3 is a diagram showing an example of a package in which the semiconductor device of FIG. 2 is mounted; FIG.

Embodiments will be described below with reference to the drawings.

FIG. 1 shows an example of a semiconductor device according to one embodiment. The semiconductor device 100 shown in FIG. 1 has a stacked memory MEM including a plurality of stacked memory chips 10 , a test section 12 , a first counter section 14 and a memory management section 16 . Memory chip 10 is an example of a memory. Each memory chip 10 has, for example, a plurality of memory blocks 10a (memory areas) that are units allocated to user programs. The test section 12 performs a test with a reduced read margin for read data read from the memory block 10a based on the address output to the stacked memory MEM. For example, the test unit 12 reduces the read margin by making the read data fetching timing earlier than the standard timing.

The first counter section 14 has a plurality of counter areas for holding the number of times an error has occurred in the read test by the test section 12 for each memory block 10a. Although the first counter section 14 is described as having eight counter areas, it actually has counter areas corresponding to all the memory blocks 10 a of the four memory chips 10 . The test unit 12 updates the counter value held in the counter area corresponding to the memory block 10a in which an error occurred in the read test with the reduced read margin. The memory management unit 16 prohibits the use of the memory block 10a for which the number of times (counter value) held by the first counter unit 14 exceeds a predetermined first threshold.

Since the test unit 12 performs the test by reducing the read margin, the memory block 10a in which an error occurred in the test operates normally unless the read margin is reduced. However, the read margin of the memory block 10a in which an error has occurred in the test by the test section 12 is lowered. Decrease in readout margin occurs due to software factors such as incident α-rays and power supply noise, but also due to deterioration of internal memory characteristics such as increase in threshold voltage of transistors, increase in resistance of internal wiring and plugs, etc. It may occur.

If the deterioration of the read margin is due to deterioration of the internal characteristics of the memory, the memory block 10a in which the error occurred may become defective in the future. For this reason, it is preferable to determine that the memory block 10a in which errors due to insufficient read margin have exceeded a predetermined number of times (first threshold value) is a sign of failure. In other words, regardless of whether the cause of the error is software or characteristic variation inside the memory, prohibiting the use is preferable in order to maintain the reliability of the semiconductor device 100 .

In this embodiment, by prohibiting the use of the memory block 10a with a reduced read margin, it is possible to prevent continued access to the memory block 10a with an insufficient read margin, thereby preventing the memory block 10a from becoming defective. can do. As a result, the reliability of the semiconductor device 100 can be maintained.

Even when the stacked memory MEM including the memory block 10a whose use is prohibited is continued to be used, the memory block 10a in which a defect may occur is not accessed, so that the stacked memory MEM does not become defective. Therefore, maintenance to replace the defective stacked memory MEM does not occur, and maintainability can be improved, and the operation cost of the system including the semiconductor device 100 can be reduced. For example, by catching a sign of the occurrence of a defect before an error occurs, it is possible to replace the stacked memory MEM well before the system goes down due to the occurrence of the error.

FIG. 2 shows an example of a semiconductor device according to another embodiment. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor device 102 shown in FIG. 2 has a stacked memory MEM similar to that shown in FIG. 1 and a CPU. A CPU is an example of an arithmetic processing unit. Although not particularly limited, the stacked memory MEM may be, for example, HBM (High Bandwidth Memory). Note that the semiconductor device 102 may have another processor instead of the CPU. Since the configuration of the stacked memory MEM is the same as that of FIG. 1, the description is omitted.

The CPU has a test section 12 , a first counter section 14 , a memory management section 17 , an output buffer 20 , an error detection/correction section 22 and a second counter section 24 . The output buffer 20 latches read data read from the stacked memory MEM in synchronization with the set signal setX, and outputs the latched read data to the test section 12 and the error detection/correction section 22 .

The test unit 12 performs a test with a reduced read margin for read data read out from the memory block 10a, as described with reference to FIG. The test unit 12 reduces the read data read margin by generating the set signal setX whose transition edge is shifted with respect to the set signal set. The test unit 12 updates (eg, increments) the counter value held in the counter area of the first counter unit 14 corresponding to the memory block 10a in which an error occurred in the read test with the reduced read margin. A counter area is provided corresponding to all the memory blocks 10 a of the memory chip 10 .

The error detection/correction unit 22 detects errors in data read from the output buffer 20 using, for example, an error detection/correction code, corrects correctable errors, and writes the data back to the memory chip 10 . The second counter section 24, like the first counter section 14, has counter areas respectively corresponding to the memory blocks 10a. When an error is detected, the error detection/correction unit 22 updates (eg, increments) the counter value held in the counter area of the second counter unit 24 for each memory block 10a.

The memory management unit 17, like the memory management unit 16 shown in FIG. 1, has a function of prohibiting the use of the memory block 10a whose number of times held by the first counter unit 14 exceeds a predetermined first threshold. have Furthermore, the memory management unit 17 has a function of prohibiting the use of the memory block 10a whose number of times held by the second counter unit 24 exceeds a predetermined second threshold. The first threshold and the second threshold may be the same value, and the second threshold may be greater than the first threshold. Note that the memory block 10a is also referred to as a page 10a in the following description. Page 10a has the minimum memory size that the CPU can allocate to the user program, and the memory size is, for example, 4 kB or 64 kB.

FIG. 3 shows an example of a main part of the test section 12 of FIG. The test unit 12 includes a register 32 that holds selection numbers, and a register unit 34 that holds a plurality of selection values sel (sel0, sel1, . , a delay adjustment circuit 36 and a multiplexer 38 . For example, the selection number indicates one of the areas in which the selection value sel held in the register section 34 is held. The register unit 34 outputs the selection value sel held in the area corresponding to the value of the selection number to the multiplexer 38 .

The delay adjustment circuit 36 has an inverter that inverts the logic of the set signal set and a plurality of buffers that sequentially delay the output signal from the inverter. The delay adjustment circuit 36 outputs to the multiplexer 38 a signal that does not delay the set signal set and a plurality of signals obtained by inverting the logic of the set signal set and sequentially delaying them.

The multiplexer 38 selects a signal (set signal set or a signal obtained by inverting and delaying the set signal set) corresponding to the selection value sel output from the register unit 34 according to the selection number held in the register 32, and selects The resulting signal is output as the set signal setX. For example, when the multiplexer 38 receives the selection value sel0, it selects the undelayed set signal set, and when it receives the selection value sel1, it selects the signal obtained by delaying the inverted set signal set by one stage with a buffer. When the multiplexer 38 receives the selection value sel2, it selects a signal obtained by delaying the inverted set signal set by two stages with a buffer. Select the delayed signal. In FIG. 3, the generation timing of the set signal setX used for the latch timing of the output buffer 20 can be easily generated by a simple logic circuit.

FIG. 4 shows an example of the set signal setX generated by the test section 12 of FIG. For example, when the selection value sel0 is selected, the set signal setX delayed by the delay time of the multiplexer 38 with respect to the set signal set is output. When one of the selection values sel1-seln is selected, the logic of the set signal set is inverted, and the set signal setX delayed by the delay time of the buffer with respect to the set signal set is output.

The delay amount of the set signal setX with respect to the set signal set increases as the number of the selection value sel increases. As a result, the phase of the rising edge of the set signal setX, which is the latch timing of the output buffer 20 shown in FIG.

FIG. 5 shows an example of a read test by the test section 12 of FIG. The test unit 12 executes a normal read test in order to correct the error by the error detection/correction unit 22, and executes a read test with a reduced read margin in order to determine deterioration of the read margin.

For example, a normal read test and a read test with reduced read margin are periodically performed on all memory areas (memory cells) of all pages 10a. Also, the read test shown in FIG. 5 is executed behind the scenes of the user program during user program processing. That is, the read test shown in FIG. 5 is repeatedly executed by so-called memory patrol.

In the read test, the test section 12 outputs the read address to the stacked memory MEM in synchronization with the rising edge of the set signal setX during normal operation. For example, the read address output period is equal to the cycle of the set signal setX, and the cycle of the set signal setX is the read cycle.

The stacked memory MEM accesses the memory area indicated by the read address based on the read address, and outputs read data output from the accessed memory area. The output buffer 20 latches the read data in synchronization with the rising edge of the set signal setX.

In a normal read test in which the read margin is not reduced, the time from the output of read data to the rising edge of the set signal setX is the time during which the output buffer 20 can latch the read data with a predetermined margin (setup time). is.

On the other hand, in a read test with a reduced read margin, the time from the output of read data to the rising edge of the set signal setX is shorter than in a normal read test. Therefore, the timing margin for the output buffer 20 to latch the read data is reduced.

The timing of the rising edge of the set signal setX in the read test with the reduced read margin is set to the timing at which the output buffer 20 can latch the read data output from the memory chip 10 whose read characteristics are not degraded. Therefore, the memory chip 10 whose read characteristics are not degraded passes the read test with a reduced read margin.

For example, in a test before mounting the stacked memory MEM on the semiconductor device 102, the output timing of the set signal setX that enables the output buffer 20 to latch the read data output from the normal memory chip 10 is evaluated. Then, the selection number corresponding to the output timing of the set signal setX determined by the evaluation is determined. The test unit 12 sets the selection number determined by the evaluation in the register 32 in the read test with the reduced read margin.

For example, in the memory chip 10, it is assumed that the read data output timing is delayed due to an increase in the threshold voltage of the transistor and a local increase in the resistance value of the internal wiring and plug portion. In this case, in a read test with a reduced read margin, the output buffer 20 may not be able to latch the read data and an error may occur. When an error occurs, the test section 12 increments the counter value of the counter area of the first counter section 14 corresponding to the page 10a that has output the read data. Then, as will be described later, the memory management unit 17 prohibits the use of the page 10a whose number of times held by the first counter unit 14 exceeds a predetermined first threshold.

FIG. 6 shows an example of the flow of user program processing executed by the CPU in FIG. For example, the semiconductor device 102 employs a virtual memory system. Therefore, each page 10a of the stacked memory MEM allocated to the physical address space is linked to the logical address space (virtual address space) by the logical address information stored in the page table PTBL that manages the usage status of the memory area. For example, the page table PTBL has an entry corresponding to each page 10a. Each entry has areas for storing information such as failure flags, valid flags, permission/prohibition of access, access restrictions, correspondence with logical addresses, and the like. Each entry also has the first counter section 14 and the second counter section 24 of FIG.

The failure flag is set when the test section 12 determines that the read margin of the page 10a has deteriorated. The valid flag is set when the page 10a is used by a user program or an OS (Operating System). Whether or not access is permitted is set when the use of the page 10a by the user program is permitted. For access restrictions, for example, information such as read only or both read and write is stored. The area indicating the correspondence with the logical address stores, for example, a predetermined number of high-order bits of the associated logical address.

In the processing flow shown in FIG. 6, first, in step S10, the OS executed by the CPU secures a memory area used by the user program before starting the user program processing. At this time, a memory area is secured by avoiding the page 10a for which the failure flag is set. Next, in step S11, the OS updates the page table PTBL according to the secured memory area, and determines the page 10a to be used by the user program. Next, in step S12, user program processing is started using the secured page 10a.

When the user program processing ends, in step S13, the OS sets a failure flag based on the counter values of the first counter unit 14 and the counter values of the second counter unit 24 corresponding to the page 10a used by the user program. to set. The counter value of the first counter section 14 and the counter value of the second counter section 24 are updated by memory patrol by the test section 12 that is executed during user program processing.

Note that the failure flag may be set during the user program processing, or after the page table PTBL is initialized in step S15. The OS does not secure the page 10a for which the failure flag is set as a memory area in the flow of subsequent user program processing.

Next, in step S14, the OS releases the memory area used by the user program. Next, in step S15, the OS initializes the page table PTBL entry corresponding to the page 10a allocated for use by the user program, and completes a series of operations for user program processing. Since the failure flag is not normally initialized even by the initialization of the entry, it is possible to prevent the failure flag from being reset once it has been set.

FIG. 7 shows an example of a memory patrol startup flow executed by the CPU in FIG. First, in step S20, the OS instructs activation of memory patrol. In step S21, the CPU starts memory patrol based on an activation instruction from the OS.

In step S22, the memory access controller mounted on the CPU outputs a read access request including an address and a control signal to the stacked memory MEM in order to read read data from the stacked memory MEM as the memory patrol starts. In step S23, the stacked memory MEM executes a read operation of reading data from the target page 10a based on the read access request.

Thereafter, by repeatedly executing steps S22 and S23, the memory patrol is repeatedly executed while changing the access area. An example of memory patrol processing is shown in FIG. When stopping the memory patrol, the OS instructs the CPU to stop the memory patrol, and the CPU stops the memory patrol. Since the OS only instructs to start and stop the memory patrol, the load due to the memory patrol is small. In addition, since the memory access controller controls the stacked memory MEM by memory patrol, the load on the CPU due to memory patrol is small.

FIG. 8 shows an example of a processing flow of memory patrol executed by the CPU in FIG. Steps S30, S31, S32, and S33 show memory patrol processing by the normal read test shown in FIG. Steps S34, S35, S36, and S37 show memory patrol processing by the read test with the reduced read margin shown in FIG. For example, in memory patrol, 1-bit error correction or 2-bit error detection is performed using an error detection/correction code.

First, in step S30, the CPU issues a read access request to the stacked memory MEM and receives read data output from the stacked memory MEM. Note that the CPU (test unit 12) sets a selection number for selecting the selection value sel0 in the register 32 (FIG. 3) before issuing the read access request. Therefore, the output buffer 20 latches the read data in synchronization with the set signal setX generated based on the undelayed set signal set.

Next, in step S31, if the error detection/correction unit 22 detects an error in the read data, the CPU proceeds to step S32, and if no error is detected, proceeds to step S34. In this example, for the sake of simplicity, it is assumed that no uncorrectable error occurs.

In step S32, the error detection/correction unit 22 corrects the read data error and writes it back to the stacked memory MEM. Next, in step S33, the error detection/correction unit 22 increments the counter value of the counter area corresponding to the page 10a in which the error is detected in the second counter unit 24, and proceeds to step S34.

In step S34, the CPU (test unit 12) sets the set signal setX to the timing for reducing the read margin, by changing the register 32 in which the standard state selection number is set to the selection number for reducing the read margin. rewrite. By providing the register 32 for storing the selection number, the timing of the set signal setX can be easily adjusted.

In step S35, the CPU issues a read access request to the stacked memory MEM and receives read data output from the stacked memory MEM. The output buffer 20 latches read data in synchronization with a set signal setX generated based on a signal obtained by inverting the set signal set and delaying it by a predetermined amount.

Next, in step S36, if the test section 12 detects an error in the read data, the process proceeds to step S37, and if no error is detected, the process ends. The error detected in step S36 may be a single bit error or a multiple bit error.

In step S37, the first counter unit 14 increments the counter value of the counter area corresponding to the page 10a in which the error is detected, and the process ends.

In this embodiment, the number of error occurrences is counted for each of a normal read test and a read test with a reduced read margin. As a result, even if an error other than an error due to insufficient read margin occurs (for example, an error due to a characteristic variation inside the memory), a sign of abnormality can be detected, and the page 10a in which the error has occurred becomes defective. You can degenerate before.

FIG. 9 shows an example of a processing flow for prohibiting use of a page executed by the CPU in FIG. For example, the processing shown in FIG. 9 is processing corresponding to step S13 in FIG. The processing shown in FIG. 9 is executed by the memory management unit 17 for each page 10a.

First, in step S40, the memory management unit 17 reads a counter value from the counter area of the second counter unit 24 corresponding to the target page 10a. In step S41, when the read counter value exceeds the second threshold value, the memory management unit 17 determines that there is a sign of some abnormality such as deterioration, and shifts the process to step S44. If the read counter value does not exceed the second threshold value, the memory management unit 17 shifts the process to step S42.

In step S41, the memory management unit 17 reads the counter value from the counter area of the first counter unit 14 corresponding to the target page 10a. In step S43, when the read counter value exceeds the first threshold value, the memory management unit 17 determines that there is a sign of some abnormality such as deterioration, and shifts the process to step S44. If the read counter value does not exceed the first threshold value, the memory management unit 17 shifts the process to step S45.

In step S44, the memory management unit 17 sets the failure flag of the entry corresponding to the target page 10a in the page table PTBL, and ends the process. That is, when one or both of the counter values to be evaluated of the first and second counter units 14 and 24 exceed the respective threshold values, degeneracy reservation is performed to stop using the corresponding page 10a. In this embodiment, since the storage area managed by the OS is allocated in units of pages 10a, the fallback reservation is a page offline operation. By setting the failure flag, the page 10a corresponding to the set failure flag is prohibited from being used by the user program. After step S44, the process of step S45 may be executed without ending the process.

In step S45, the memory management unit 17 clears the counter value of the first counter unit 14 corresponding to the target page 10a and the counter value of the second counter unit 24 corresponding to the target page 10a (for example, , "0"), the process ends.

The counter value of the first counter section 14 and the counter value of the second counter section 24 may be cleared at regular time intervals. For example, the counter value may be cleared every day, or when a page 10a swap occurs. As a result, the counter value exceeded the threshold because the number of software-generated errors accumulated over a long period of time, or because the frequency of errors increased due to signs of abnormalities such as deterioration. It is possible to judge whether

For example, the first threshold is "10", the second threshold is "3", and the first threshold is greater than the second threshold. A read test with a reduced read margin is more likely to cause an error than a normal read test. Exceeding increases the likelihood of fault flags being generated. Therefore, by setting the first threshold larger than the second threshold in consideration of the frequency of occurrence of errors, the frequency of setting the failure flag when the first threshold is exceeded and the frequency of setting the failure flag when the second threshold is exceeded are calculated. can be equated with the set frequency.

FIG. 10 shows an example of a package in which the semiconductor device 102 of FIG. 2 is mounted. The semiconductor device 102 has a structure in which a stacked memory MEM in which a plurality of memory chips 10 and logic chips 50 are interconnected via TSVs and a CPU chip are connected via a silicon interposer. Connections between chips and between the chips and the silicon interposer are made by bumps. Also, the silicon interposer is connected to the package substrate via bumps. Furthermore, the package substrate is connected to a system substrate or the like (not shown) via bumps.

As described above, in the embodiment shown in FIGS. 2 to 10, the same effects as in the embodiment shown in FIG. 1 can be obtained. In other words, during memory patrol, by executing a patrol operation with a reduced read margin in addition to the normal patrol operation, it is possible to detect a sign of an abnormality due to degradation of the memory chip transistor or the like for each page 10a. Then, by degenerating (offlining) the page 10a in which the sign of abnormality is detected, it is possible to prevent the page 10a from being used in the user program processing started thereafter. As a result, reliability of the semiconductor device 102 can be improved.

In addition, by executing memory patrol by not only a read test with a reduced read margin but also a normal read test, it is possible to set a failure flag in response to an error that occurs at normal read timing. As a result, even if an error other than an error due to insufficient read margin occurs (for example, an error due to a characteristic variation inside the memory), a sign of abnormality can be detected, and the page 10a in which the error has occurred becomes defective. You can degenerate before.

By making the first threshold larger than the second threshold, the frequency of setting the failure flag when the first threshold is exceeded can be made equal to the frequency of setting the failure flag when the second threshold is exceeded. That is, it is possible to equalize the frequency of setting fault flags based on the two read tests.

When the semiconductor device 102 adopts a virtual memory system and the page 10a is allocated each time the CPU executes the user program processing, subsequent use of the page whose number of errors exceeds the threshold can be prohibited. Reliability can be improved.

By clearing the counter value of the first counter unit 14 and the counter value of the second counter unit 24 at regular time intervals, it is possible to determine the reason why the counter value exceeds the threshold.

From the detailed description above, the features and advantages of the embodiments will become apparent. It is intended that the claims cover the features and advantages of such embodiments without departing from their spirit and scope. In addition, any improvements and modifications will readily occur to those skilled in the art. Accordingly, the scope of inventive embodiments is not intended to be limited to that described above, but can be relied upon by suitable modifications and equivalents within the scope disclosed in the embodiments.

10 memory chip 10a memory block (page)
12 test section 14 first counter section 16, 17 memory management section 20 output buffer 22 error detection correction section 24 second counter section 32 register 34 register section 36 delay adjustment circuit 100, 102 semiconductor device MEM laminated memory sel selection value set , setX set signal

Claims (6)

a stacked memory including a plurality of stacked memories;
a test unit that performs a test with a reduced read margin for read data read from a plurality of memory blocks of the plurality of memories;
a first counter unit that holds, for each memory block, the number of times an error has occurred in the test by the test unit;
an error detection and correction unit that corrects a correctable error that occurs in the stacked memory;
a second counter unit that holds the number of error corrections made by the error detection/correction unit for each memory block;
prohibiting the use of a memory block in which the number of times held by the first counter exceeds a predetermined first threshold , and the number of error corrections held by the second counter exceeds a predetermined second threshold; a memory management unit that prohibits the use of exceeding memory blocks ;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein said first threshold is greater than said second threshold. 3. The semiconductor device according to claim 2 , wherein said memory management unit clears the counter value of said second counter unit at a predetermined frequency. Having a buffer that holds read data read from the stacked memory,
4. The semiconductor device according to claim 1, wherein the test section shortens a read margin by advancing timing of loading the read data into the buffer. a processor for executing a user program using a predetermined number of said memory blocks;
5. The semiconductor device according to any one of claims 1 to 4, wherein the memory management unit prohibits use of the memory block for which use prohibition has been determined based on the termination of the user program. . 6. The semiconductor device according to claim 1, wherein said memory management unit clears the counter value of said first counter unit at a predetermined frequency .

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