JP7277756B2 - Information processing equipment - Google Patents

Description

The present invention relates to an information processing device.

In a distributed memory type parallel computer, a large-scale calculation is executed by distributing a calculation job to a plurality of nodes and performing calculations in parallel on each node. Each node is interconnected via a network and performs parallel computation while exchanging data with each other.

Communication between nodes is performed using MPI (Message Passing Interface). MPI is an API (Application Programming Interface) for mutual communication between nodes. By using MPI, multiple nodes can cooperate to realize various collective communications.

For example, one of a plurality of nodes is defined as a receiving node, and some nodes that did not complete the calculation normally send an error code to the receiving node, so that the calculation job does not end normally. can be determined by the receiving node.

In this case, in order to shorten the processing time required for transmitting and receiving data such as error codes, a method has been proposed in which the transmitting node encodes the data to reduce the amount of information, and the receiving node decodes the data. (For example, Patent Document 1). However, this method decodes data by finding the roots of algebraic equations, and the amount of calculation required for decoding becomes enormous.

JP 2017-097795 A

According to one aspect, the present invention aims to reduce the amount of calculation.

According to one aspect, an information processing apparatus comprising a plurality of transmitting nodes, an arithmetic device, and a receiving node, wherein the transmitting node generates a plurality of encoded vectors associated with each of the plurality of transmitting nodes. Among them, a first calculation unit for calculating a first vector obtained by encoding the transmission data by scalar-multiplying the encoding vector corresponding to itself by the transmission data; and a first transmitting unit that transmits to a plurality of transmitting nodes, and a second computing unit that computes a second vector by adding together the first vectors transmitted by each of the plurality of transmitting nodes. , and a second transmitter for transmitting the second vector to the receiving node, wherein the receiving node is a system of linear equations in which each component of the encoded vector corresponding to each of the transmitting nodes is a coefficient. and an information processing apparatus having a decoding unit that decodes the transmission data by solving simultaneous linear equations in which each component of the second vector is a constant term.

According to one aspect, the amount of calculation can be reduced.

FIG. 1 is a configuration diagram of a parallel computer used for the study. FIG. 2 is a hardware configuration diagram of the information processing apparatus according to this embodiment. FIG. 3 is a functional configuration diagram of the information processing apparatus 10 according to this embodiment. FIG. 4 is a diagram showing an example of the format of data that the transmission node according to this embodiment transmits to the arithmetic device. FIG. 5 is a diagram showing an example of the format of data obtained by the reduction operation in this embodiment. FIG. 6 is a flowchart for explaining the processing performed by the transmission node according to this embodiment. FIG. 7 is a flowchart for explaining the process of decoding the identifier of each transmission node based on the sum in this embodiment. FIG. 8 is a diagram schematically showing the contents of idc_list obtained in the example of FIG. FIG. 9 is a flowchart for explaining the process of decoding each piece of transmission data by the receiving node according to this embodiment.

Prior to the description of the present embodiment, matters examined by the inventors of the present application will be described.
FIG. 1 is a configuration diagram of a parallel computer used for the study.

This parallel computer 1 is a distributed memory type parallel computer and has a plurality of transmission nodes 2 , reduction devices 3 and reception nodes 4 .

Among these, each of the plurality of transmission nodes 2 is a computer that executes computation jobs in parallel. Depending on the scale of the parallel computer 1, the number of transmission nodes 2 is about several hundred to several hundred thousand. Most of the sending nodes 2 complete the calculation job normally, but some of the sending nodes 2 may experience an error during execution of the calculation job. Such anomalies include hardware failures and overflows.

The transmission node 2 in which an abnormality has occurred transmits an error code identifying the abnormality to the reduction device 3 as transmission data. Here, the error code is assumed to be an integer value. For example, the error code is "2" when an overflow occurs during calculation, and the error code is "3" when the calculation ends due to a hardware failure.

Note that the transmission node 2 that has completed the calculation normally transmits "1", which is the unit element of multiplication, as an error code.

The reduction device 3 is a device that receives an error code from the transmission node 2 and performs an MPI reduction operation on the error code. Reduction operations performed by the reduction device 3 include Reduce and Allreduce. Reduce is an operation in which various calculations are performed on an error code and only the reduction device 3 holds the calculation results. Allreduce is an operation for sharing the operation result among a plurality of transmission nodes 2 .

In this example, it is assumed that the reduction device 3 performs multiplicative Reduce to obtain the total product of the error codes of all transmission nodes 2 in which an abnormality has occurred. For example, three sending nodes 2 in which an abnormality has occurred send error codes "2", "3", and "2", respectively, and the remaining normal sending nodes 2 send "1" as the error code. think. In this case, the reduction device 3 obtains 12 (=2*3*2) as the total product of these error codes.

Then, the receiving node 4 receives the total product of the error codes from the reduction device 3, and obtains the error code from the total product as follows.

First, let the number of sending nodes 2 be k, and the i-th sending node 2 generates an integer error code _Ei . Also, k different integers A _i (i=1, . . . , k) are prepared in advance and distributed to all the transmission nodes 2 .

In this case, the i-th transmission node 2 transmits k pieces of data A ₁ +E _i , A ₂ +E _i , . . . , A _k +E _i to the reduction device 3 .

The reduction device 3 calculates k values G(A _i ) by performing the reduction operation of the following formula (1) on these data transmitted by all the transmission nodes 2, and each of these values to the receiving node 4.

Here, consider the equation (2) in which the integer A _i in the equation (1) is replaced with the unknown X.

Letting F(X):=G(-X), the root of the algebraic equation F(X)=0 is the error code E _i (i=1, …, k). Using this, the receiving node 4 uses k values G(A _i ) received from the reduction device 3 to decode the error code E _i (i=1, . . . , k).

According to the parallel computer 1 described above, the error codes E _i (i=1, . . . , k ) can be decrypted.

Particularly, in this example, only some transmission nodes 2 in which an abnormality has occurred participate in the communication. Such communication is also called information-intensive communication. In information-intensive communication, it can be expected that the communication speed will be faster than in the case where all sending nodes 2 participate in the communication.

However, this method requires a huge amount of calculation to find the roots of the algebraic equation, and the receiving node 4 cannot decode the error code E _i (i=1, . . . , k) at high speed.

The present embodiment capable of reducing the amount of calculation required for decoding will be described below.

(this embodiment)
[Hardware configuration]
FIG. 2 is a hardware configuration diagram of the information processing apparatus according to this embodiment.

The information processing device 10 is a distributed memory type parallel computer, and includes a plurality of nodes 11, relay devices 12, and arithmetic devices 13, respectively.

Among these, each of the plurality of nodes 11 is a computer that executes computation jobs in parallel. Although the number of nodes 11 is not particularly limited, the information processing apparatus 10 is provided with several hundred to several hundred thousand nodes 11, for example.

Each node 11 also includes a processor 14 and a memory 15 that cooperate to perform computational jobs. Note that the processor 14 is hardware having a calculation function such as a CPU (Central Processing Unit) or a GPU (Graphical Processing Unit). The memory 15 is a volatile memory such as DRAM (Dynamic Random Access Memory).

Furthermore, each node 11 has a network interface 16 , and each node 11 and the relay device 12 are connected via the network interface 16 .

The relay device 12 is, for example, a switch or router, and connects each node 11 and the arithmetic device 13 to each other. Also, in this example, each of the plurality of relay devices 12 is connected to each other via the network. Such networks include, for example, LANs (Local Area Networks).

The arithmetic device 13 is a reduction device that receives an error code from each node 11 and performs an MPI reduction operation on the error code. Reduction operations performed by the arithmetic unit 13 include, for example, Reduce and Allreduce described above. Further, the arithmetic device 13 has a processor 17 and a memory 18, and the reduction operation is performed by cooperation of these.

Note that the processor 17 is hardware such as a CPU or a GPU. The memory 18 is a volatile memory such as DRAM.

Also, in this example, the computing device 13 is accommodated in a housing different from the housing of the node 11 . Such an arithmetic device 13 is also called an independent housing type arithmetic device. Note that the node-embedded arithmetic device 13 housed in the housing of the node 11 may be used.

[Function configuration]
FIG. 3 is a functional configuration diagram of the information processing apparatus 10 according to this embodiment.
As shown in FIG. 3, the information processing device 10 includes a plurality of transmission nodes 21, reception nodes 22, and arithmetic devices 13. FIG.

In this example, one of the plurality of nodes 11 (see FIG. 2) is the receiving node 22 and the remaining nodes 11 are the transmitting nodes 21 . Also, the number of transmission nodes 21 is N, and each transmission node 21 is represented by node ₀ to node _N-1 .

Identifiers id ₀ to id _N-1 and identification codes idcode ₀ to idcode _N-1 are assigned in advance to each of these transmission nodes 21 .

Among them, the identifiers id ₀ to id _N−1 are numerical values that uniquely identify each transmission node 21 . In the following, integer values of 0 to N-1 are assigned to each transmission node 21 as identifiers id ₀ to id _N -1 so that id _r =r.

Also, the identification codes idcode ₀ to idcode _N-1 are values obtained by encoding each of the identifiers id ₀ to id _N-1 . The encoding method is not particularly limited. In this embodiment, when id _r =r, the identification code idcode ^r is the power of 2, where _r is the exponent.

Further, each transmission node 21 is associated with N encoded vectors encdvec(node ₀ ) to encdvec(node _N−1 ). The encoding vectors encdvec(node ₀ ) to encdvec(node _N−1 ) are vectors for encoding the transmission data of the transmission node 21, and each transmission node is encoded when the information processing device 10 is activated or when a calculation job is started. 21 is stored in the memory 15 .

Here, the components of the encoded vector encdvec(node ₀ ) to encdvec(node _N-1 ) are integers. Also, the number of dimensions k of the encoded vector encdvec(node _i ) (i=0, . . . , N−1) is equal to or less than the number N of transmission nodes 21 .

In the following, let V be the vector space spanned by N encoded vectors encdvec(node _i )(i=0, …, N-1), and its basis vectors be e ₀ , e ₂ , … e _N-1 .

Here, arbitrary j (≤k) coded vectors are selected from N coded vectors as shown in the following equation (3).

Also, let U be a subspace of V spanned by j basis vectors as in the following equation (4).

Let π be the orthogonal projection of any v ∈ V onto U, then the orthogonal projection π of each encoded vector in Equation (3) onto U is as follows.

In this embodiment, N encoded vectors encdvec(node _i ) (i=0, . Keep As a result, the following property holds for the matrix whose elements are the components of each encoded vector.

First, each of N encoded vectors encdvec(node _i )(i=0, .

Then, a matrix A ₀ of N rows and k columns having each component as an element is defined by the following equation (7).

This matrix A ₀ is hereinafter referred to as an encoding matrix. Arbitrarily select j (≦k) columns from the k columns of the encoding matrix A ₀ , and let the selected column numbers be i ₀ , _{i 1 ,} . Then, α _st (s= i ₀ , i ₁ , …i _j-1 , t= i ₀ , i ₁ , …i _j-1 ) is represented by the following equation (8) as the component of row s and column t Let A be a submatrix of j rows and j columns in .

At this time, since each encoded vector in Equation (5) is linearly independent, the submatrix A, which is a j×j square matrix, is regular. Therefore, predetermining N encoded vectors encdvec(node _i )(i=0, . It is nothing but to define the encoding matrix A ₀ of the equation (7) so that

As long as this condition is satisfied, the method of determining the encoded vector encdvec(node _i ) is not particularly limited.

_For example, ^the encoding vector ^encdvec (node _i ) may be generated. Note that res(z) is the remainder when z is divided by the smallest prime number p greater than or equal to N. In this case, res(z) may be a remainder that satisfies 0≤res(z)≤p-1 or may be the minimum absolute value remainder s. The absolute minimum remainder s is a remainder that satisfies -(p-1)/2≤s≤(p-1)/2.

If arbitrary k pieces of coded vectors are selected from the N pieces of coded vectors obtained from these remainders and the respective components are arranged to form a k×k square matrix, the square matrix becomes a Vandermonde matrix. Therefore, the encoded vector obtained by this can automatically satisfy the conditions described in the above equations (7) and (8).

Note that (1, res(i), res(i ² ), …res(i ^k-1 )) is the same as an element of a finite field F _p (=Z/Z _p ) of characteristic p. can be expressed simply as (1, i, i ² , . . . , i ^k-1 ).

Also, the prime number p may be stored in the memory 15 of each transmission node 21 when the information processing apparatus 10 is activated or when a calculation job is started.
Refer to FIG. 3 again.

Each transmission node 21 has an execution unit 31 , a first calculation unit 32 and a first transmission unit 33 . These units are implemented by the processor 14 and the memory 15 working together to execute the information processing program according to the present embodiment.

Among these, the execution unit 31 executes a calculation job assigned to each transmission node 21 . Also, the execution unit 31 at node _i (i=0, . . . , N-1) outputs an error code _Ei indicating whether the calculation job assigned to itself ended due to an error. Such anomalies include hardware failures and overflows.

In this example, the error code _Ei is an integer value. Then, when there is an abnormality, the error code E _i is set to a non-zero value, and the value is changed according to the type of abnormality. For example, the error code is "1" when an overflow occurs during calculation, and the error code is "2" when the calculation ends due to a hardware failure.
On the other hand, if there is no abnormality, the error code _Ei is set to zero.

Note that the execution unit 31 may output an error code E _i when the calculation load of its own device exceeds a threshold. In this case, the execution unit 31 outputs zero as the error code _Ei when the computational load does not exceed the threshold, and outputs a non-zero error code _Ei when the computational load exceeds the threshold. . For example, the execution unit 31 may output the time when the computational load exceeds the threshold as the error code _Ei .

Also _, the first calculator 32 of the i-th (i=0, . A first vector V _i =D _i ·encdvec(node _i ) obtained by multiplying the data D _i by a scalar is calculated. Thereby, the transmission data D _i is encoded.

The transmission data D _i is not particularly limited, but in this example, the error code E _i is used as the transmission data D _i . As a result, the transmission data D _i of the transmission node 21 whose calculation job ended normally becomes zero, and the transmission data D _i of the transmission node 21 whose calculation job ended abnormally becomes non-zero.

Then ^, when the transmission data D _i is not zero, the first transmission unit 33 of the i-th ₍ i=0, . The first vector V _i is sent to the arithmetic unit 13 . When the transmission data D _i is zero, the first transmission unit 33 transmits zero to the arithmetic unit 13 instead of "2 ⁱ " of the identification code idcode.

On the other hand, the computing device 13 has a first receiver 35 , a second calculator 36 and a second transmitter 37 . These units are implemented by the processor 17 (see FIG. 2) and the memory 18 working together to execute the information processing program according to the present embodiment.

Among them, the first receiving unit 35 receives the first vector V _i (i=0, . . . , N−1) from each of the N transmitting nodes 21 . Furthermore, the first receiving unit 35 receives the identification code idcode “2 ⁱ ” from each transmission node 21 .

Then, the second calculation unit 36 calculates a second _vector W (=V ₁ +V _{2 +} . calculate. Incidentally, as described above, the first vector V _i becomes a zero vector in the transmission node 21 where the calculation job has normally ended. Therefore, the second vector W is the sum of the first vectors V _i in some of the N transmission nodes 21 whose calculation jobs have ended abnormally.

Further, the second calculator 36 calculates the sum S of “2 ⁱ ” of the identification codes idcode _i transmitted by the N transmission nodes 21 . A sending node 21 that has successfully completed a computation job sends zero instead of "2 ⁱ ", but zero contributes to the sum S. Therefore, the total sum S is the sum of “2 ⁱ ” of the identification code idcode _i of some of the N transmitting nodes 21 whose calculation jobs have ended abnormally.

The second transmitting unit 37 then transmits the second vector W and the sum S to the receiving node 22 .

The receiving node 22 has a second receiving section 38 and a decoding section 39 . These units are implemented by the processor 14 (see FIG. 2) and the memory 15 working together to execute the information processing program according to the present embodiment.

The encoding matrix A ₀ is stored in advance in the memory 15 of the receiving node 22 . The timing for storing the encoded matrix _A0 in the memory 15 is not particularly limited, and is stored in the memory 15, for example, when the information processing apparatus 10 is started or when a calculation job is started.

Also, the second receiving unit 38 receives the second vector W from the computing device 13 .

Then, the decoding unit 39 uses the second vector W to decode the transmission data D _i as follows.

First, the decoding unit 39 uses the binary summation S to identify the transmission node 21 that transmitted the first vector V _i that is not the zero vector, as follows.

For example, consider the case where transmission data D _i at transmission nodes 21 with identifiers id _i of 1, 3, and 5 are non-zero, and these transmission nodes 21 transmit first vectors V _i that are not zero vectors. It is assumed that the transmission data D _i in transmission nodes 21 whose identifiers id _i are other than 1, 3, and 5 is zero, and that these transmission nodes 21 have transmitted zero instead of powers of two.

In this case, zeros transmitted by the transmitting nodes 21 whose identifiers id _i are other than 1, 3, and 5 do not contribute to the total sum S, so the total sum S is 2 ¹ +2 ³ +2 ⁵ . This is 101010 in binary notation. The exponents of the bits set to 1 in this binary notation are 1, 3, 5, which is equal to the identifier id _i . As a result, the decoding unit 39 can decode the identifier id _i of the transmission node 21 that has transmitted the non-zero transmission data from the total sum S.

Next, the decoding unit 39 uses the identifier id _i decoded in this way and the encoding matrix _A0 to generate a submatrix A as follows. First, the decoding unit 39 generates a submatrix A whose row number and column number are equal to the identifier id _i among the components of the encoding matrix _A0 . For example, if the identifier id _i is 1, 3, 5 as above, the 3 × 3 matrix created by α _ij (i = 1, 3, 5, j = 1, 3, 5) is the minor matrix A becomes.

It should be noted that each component of the submatrix A is equal to each component of the encoded vectors whose identifiers id _i are 1, 3, and 5, respectively. Therefore, the decoding unit 39 generates the submatrix A using the encoded vector components corresponding to the identifiers id _i of 1, 3, and 5, respectively.

Then, the decoding unit 39 decodes the transmission data D _i by solving the simultaneous linear equations represented by the following equation (9).

Note _that w ₁ , w ₂ , .

It is understood as follows that the solution ( _x1 , _x2 ,..., _xk ) of equation (9) is equal to the transmitted data ( _D1 , _D2 ,..., _Dk ).

First, the second vector W is obtained by adding a plurality of first vectors V _i obtained by scalar-multiplying the transmission data to the encoded vector, so the following equation (10) holds.

これと式（９）を合わせると次の式（１１）が得られる。

Combining this with equation (9), the following equation (11) is obtained.

As mentioned above, submatrix A is nonsingular, so it has an inverse. By multiplying both sides of equation (11) by the inverse matrix from the left, it can be seen that the solution (x ₁ , x ₂ ,..., x _k ) is equal to the transmitted data (D ₁ , D ₂ ,..., D _k ). . Therefore, the transmission data (D ₁ , D ₂ , . . . , D _k ) can be obtained by solving the equation (9).

The method of solving equation (9) is not particularly limited, and the decoding unit 39 may solve equation (9) by, for example, Gaussian elimination.

According to the information processing apparatus 10 described above, the decoding unit 39 of the receiving node 22 decodes the transmission data D _i by solving the simultaneous linear equations of Equation (9). Since the amount of calculation required to solve the simultaneous linear equations is smaller than the amount of calculation required to solve the algebraic equation of Equation (2), the receiving node 22 can decode the transmission data D _i at high speed.

In addition, since the transmission data D _i is either non-zero or zero-valued data, the submatrix A is generated only with each component of the encoded vector corresponding to the transmission node 21 with the transmission data D _i being non-zero. be done. Solving the simultaneous linear equations (9) with the submatrix A as the coefficient matrix decodes only the non-zero transmission data. Therefore, it is not necessary to unnecessarily decode transmission data D _i having a value of zero, and the amount of calculation can be further reduced.

Furthermore, when the amount of calculation is reduced in this way, the receiving node 22 can quickly identify what kind of error has occurred in the abnormal transmitting node 21 when an error code is adopted as the transmission data D _i . can.

Moreover, by adopting the power of 2 "2 ⁱ " as the identification code idcode _i , the identifier id _i can be decoded from the sum S. In particular, when the value of the transmission data D _i is zero, the transmission node 21 transmits _zero instead of the power of 2 “2 ^r ”. Identifier id _i can be decrypted.

[Concrete example]
Next, a specific example of this embodiment will be described.
In this example, each parameter has the following values.
- Number N of transmission nodes 21: 128 - Number of transmission nodes 21 that transmit non-zero error codes: 3 - Identifiers id of transmission nodes 21 that transmit non-zero error codes: 0, 1, 127

Also, the encoded vector encdvec(node _i )(i = 0, …, N-1) is encdvec(node _i ) = (1, res(i), res(i ² ), …res(i ^k-1 )). Note that res(z) is the remainder when z is divided by the smallest prime number p greater than or equal to N as described above. Since N=128 in this example, p=131. Also, let k=3.
In this case, the encoded vector of each transmitting node 21 is as follows.

・ encdvec(node ₀ ) = (1,res(0),res(0 ² )) = (1, 0, 0)
・ encdvec(node ₁ ) = (1, res(1), res(1 ² )) = (1, 0×131 + 1, 0×131 + 1) = (1, 1, 1)
・ encdvec(node ₁₂₇ ) = (1, res(127), res(127 ² )) = (1, res(0×131 + 127), res(123×131 + 16)) = (1,127,16)

Also, the transmission data D _i is as follows.
・_D0 = 15
・_D1 = 18
・_D127 = 3

In this case, the first vector V _i =D _i ·encdvec(node _i ) obtained by encoding the transmission data D _i is as follows.
・_V0 = _D0・encdvec( _node0 ) = 15 ・(1, 0, 0) = (15, 0, 0)
・_V1 = _D1・encdvec( _node1 ) = 18 ・(1, 1, 1) = (18, 18, 18)
・_V127 = _D127・encdvec( _node127 ) = 3 ・(1, 127, 16) = (3, 381, 48)

FIG. 4 is a diagram showing an example of the format of data that each transmission node 21 transmits to the arithmetic device 13. As shown in FIG.

As shown in FIG. 4, data transmitted by each transmission node 21 has an identification code portion 51 and an encoded payload 52 .

Among them, the identification code part 51 is an area for storing the identification code idcode _i of each transmission node 21 . Incidentally, in the transmission node 21 where the value of the transmission data D _i is zero, zero is stored in the identification code section 51 instead of the identification code idcode _i . For example, zero is stored in the identification code section 51 in the transmitting node 21 where the calculation has been completed normally and the error code _Ei has become zero.

Also, in this example, the identification code portion 51 is divided into word1 and word2. The lengths of word1 and word2 are both 64 bits. Then, an identification code idcode _i whose identifier id _i is 0 to 63 is stored in word1.

On the other hand, for the transmitting nodes 21 with identifiers id _i of 64 to 127, the value obtained by subtracting 64 from the identifier id _i is used as an identification code idcode _i that is a power of 2, and this idcode _i is stored in word2. For example, for the transmitting node 21 whose identifier id is 127, "2 ⁶³ (=2 ^127-64 )" is stored in word2 as the node's identification code idcode ₁₂₇ .

The encoded payload 52 is an area for storing the first vector V _i of each transmitting node 21 . Here, the encoded payload 52 is divided into word1 to word3, each of which stores the first, second and third components of the first vector V _i . The length of word1 to word3 is all 64 bits.

Also, since the first vector V _i is a zero vector at the transmission node 21 where the value of the transmission data D _i is zero, "0" is stored in each of word1 to word3.

Arithmetic unit 13 receives such data from all transmission nodes 21 and performs a reduction operation by addition as described above. A second vector W and a sum S are calculated by the reduction operation.

FIG. 5 is a diagram showing an example of the format of data obtained by the reduction operation.

This data is data stored in the memory 18 (see FIG. 2) of the arithmetic unit 13 after the reduction operation, and has an identification code portion 53 and an encoded payload 54 .

Among them, the identification code part 53 is divided into word1 and word2. Then, word1 stores the sum of the identification codes idcode _i of the transmission nodes 21 whose identifiers id _i are 0 to 63. Word2 stores the sum of the identification codes _idcodei of the transmission nodes 21 whose identifiers _idi are 64 to 127.

On the other hand, the encoded payload 54 is divided into word1 to word3. word1 is an area for storing the first component of the second vector W; Similarly, word2 and word3 are areas for storing the second and third components of the second vector W, respectively.

Receiving node 22 receives these data and solves the simultaneous linear equations of Equation (12) below in the same manner as Equation (9).

Note that the coefficient matrix on the left side of Equation (12) is encdvec(node ₀ ) = (1, 0, 0), encdvec(node ₁ ) = (1,1,1), encdvec(node ₁₂₇ ) = (1,127, 16) is generated by the receiving node 22 by arranging the encoded vectors.

The solution of equation (12) is _x1 =15, _x2 =18, _x3 =3. As described above, the transmission data D ₀ (=15), D ₁ (=18), and D ₁₂₇ (=3) have been decoded.
[flowchart]

Next, an information processing method according to this embodiment will be described with reference to flowcharts.

FIG. 6 is a flowchart for explaining the processing performed by the transmission node 21. As shown in FIG.

First, in step S1, the first calculator 32 of each transmission node 21 determines whether or not there is transmission data D _i to be transmitted. For example, in the transmitting node 21 having the identifier id _i , it is determined that there is no data to be transmitted (NO) when the error code E _i is zero. On the other hand, when the error code E _i is non-zero, it is determined that there is data to be transmitted (YES).
If YES is determined here, the process moves to step S2.

In step S2, the first calculator 32 encodes the transmission data D _i by calculating the first vector V _i . For example, in the transmission node 21 having the identifier id _i , the first calculator 32 calculates the first vector V _i by scalar-multiplying the encoded vector encdvec(node _i ) by the transmission data D _i .

Next, in step S3, the first transmission section 33 stores the identification code idcode _i in the identification code section 51 (see FIG. 4). For example, in the transmitting node 21 having the identifier id _i , the first transmitting section 33 stores “2 ⁱ ” in the identification code section 51 .

Next, moving to step S4, the first transmitting unit 33 of the transmitting node 21 having the identifier id _i stores each element of the first vector V _i in the encoded payload 52 (see FIG. 4).

On the other hand, if NO is determined in step S1, the process proceeds to step S5.

In step S5, the first transmitting section 33 of the transmitting node 21 having the identifier id _i stores "0" in the identification code section 51 (see FIG. 4).

Next, moving to step S6, the first transmitting unit 33 of the transmitting node 21 having the identifier id _i stores "0" in the encoded payload 52 (see FIG. 4).

After performing steps S4 and S6 as described above, the process proceeds to step S7.

In step S7, each of all the transmission nodes 21 transmits each data of the identification code part 51 and the encoded payload 52 to the arithmetic device 13. FIG.
With the above, the processing of the transmission node 21 is completed.

Next, the processing of the receiving node 22 that receives these data will be described. As described above, the processing performed by the receiving node 22 includes the processing of decoding the identifier id _i of each transmitting node 21 based on the sum S of the identification codes idcode _i , and the processing of decoding each transmission data D and a process of decoding _i .
First, the former process will be explained.

FIG. 7 is a flowchart for explaining the process of decoding the identifier id _i of each transmission node 21 based on the sum S.

First, in step S11, the decoding unit 39 substitutes word1 of the identification code unit 53 (see FIG. 5) for the variable idc_word. The variable idc_word is a working variable for identifying the bit set to 1 in each of word1 and word2 of the identification code portion 53 .

Next, moving to step S12, the decoding unit 39 substitutes 1 for the variable idc_word_count for storing the number of read words.

Subsequently, the process moves to step S13, and the decoding unit 39 substitutes an empty list for idc_list. idc_list is a list for storing decrypted identifiers id _i .

Next, moving to step S14, the decoding unit 39 determines whether or not there is a bit set to 1 in the variable idc_word.
If YES is determined here, the process moves to step S15.

In step S15, the decoding unit 39 identifies bits set to 1 in the variable idc_word, and adds exponents corresponding to the bits to the idc_list as identifiers id _i .

In the example of FIG. 5, the word1 of the identification code portion 53 is "3", which is 11 in binary notation. Thus, 0 and 1 are identified as identifier id _i .

Next, moving to step S16, the decoding unit 39 substitutes word2 of the identification code unit 53 for the variable idc_word. It should be noted that if the determination in step S14 is NO, step S15 is skipped and step S16 is performed.

Next, moving to step S17, the decoding unit 39 increments the variable idc_word_count by one.

Subsequently, the process moves to step S18, and the decoding unit 39 determines whether the variable idc_word is the last word of the identification code unit 53 or not. For example, when the value of the variable idc_word_count is 2, the decoding unit 39 determines that the variable idc_word is the last word of the identification code unit 53 (YES). Then, when the value of the variable idc_word_count is smaller than 2, the decoding section 39 determines that the variable idc_word is not the last word of the identification code section 53 (NO).

If NO is determined here, the process returns to step S14. On the other hand, if the answer is YES, the process ends.

By performing the processing according to the flowchart of FIG. 7 in this way, the idc_list in which the identifier id _i of the transmission node 21 is stored is completed.

FIG. 8 is a diagram schematically showing the contents of idc_list obtained in the example of FIG. In this example, the identifiers id ₀ = 0, id ₁ = 1, id ₁₂₇ = 127 are stored in idc_list.

As described above, in the present embodiment, the sum S of powers of 2 "2 ⁱ " with the identifier id _i as the exponent is calculated, and by specifying the bit in which 1 is set in the sum S, the identifier id _i can be easily decoded.

Next, processing for decoding each transmission data D _i by the receiving node 22 based on the second vector W will be described.

FIG. 9 is a flowchart for explaining the process of decoding each transmission data D _i by the receiving node 22 .

First, in step S21, the decoding unit 39 of the receiving node 22 sorts the identifiers id _i stored in the idc_list in ascending order. The identifiers id _i may be arranged in descending order instead of ascending order.

Next, moving to step S22, the decoding unit 39 generates an encoded vector corresponding to each identifier id _i . An encoding vector can be generated from the encoding matrix A ₀ in equation (7). For example, let the identifiers id stored in the idc_list be i ₁ , i ₂ , . . . _ij . Let α _ij be the element of the encoding matrix A ₀ . At this time, each column of the j×j submatrix A created by α _st (s= i ₁ , i ₂ , … i _j , j= i ₁ , i ₂ , … i _j ) is encoded vector encdvec( node _i1 ), encdvec(node _i2 ), … encdvec(node _ij ).

Next, moving to step S23, the decoding unit 39 generates a submatrix A by arranging the encoded vectors encdvec(node _i1 ), encdvec(node _i2 ), . . . encdvec(node _ij ).

Next, moving to step S24, the decoding unit 39 substitutes the submatrix A into the coefficient matrix of the simultaneous linear equation solver. The simultaneous linear equation solver is a program executed by the processor 14 and the memory 15 of the receiving node 22 in cooperation, and is a program that solves the simultaneous linear equations by Gaussian elimination, for example.

The simultaneous linear equations, as shown in Equation (9), are equations in which the submatrix A is the coefficient matrix and the components of the second vector W are w ₁ , w ₂ , . . . _wk as constant terms. be.

Next, moving to step S25, the decoding unit 39 substitutes the components w ₁ , w ₂ , . . . w _k of the second vector W into constant terms of the simultaneous linear equation solver. For example, the decoding unit 39 substitutes each component of the second vector W stored in each of word1, word2, and word3 of the encoded payload 54 (see FIG. 5) into the constant term of the simultaneous linear equation solver.

Then, the process moves to step S26, and the decoding unit 39 executes a simultaneous linear equation solver.

Next, in step S27, the decoding unit 39 arranges the solutions obtained by solving the simultaneous linear equations in ascending order and identifies them as the transmission data D _i .
Thus, the process of decoding the transmission data D _i is completed.

According to the present embodiment described above, in step S26, the transmission data is decoded by solving the simultaneous linear equations of Equation (9). Since simultaneous equations can be solved with a smaller amount of calculation than algebraic equations, transmission data can be decoded at high speed.

Furthermore, in this embodiment, it is also possible to increase the resolution k. The resolution k is the maximum number of transmission nodes 21 that can decode the transmission data D _i . For example, if the number of transmission nodes 21 exceeding the resolution k has transmitted the transmission data D _i , the transmission data D _i cannot be decoded.
The fact that the resolution k increases can be understood as follows.

First, let p be a prime number for generating an encoded vector, and let a be the number of bits of transmission data D _i . At this time, the number of bits of data stored in each of word1 to word3 of the encoded payload 52 (see FIG. 4) is reduced to a+ _log2p . Also, if the number of bits of word1 to word3 of the encoded payload 54 (see FIG. 5) is L, then if a+ _log2p + _log2k ≦L, it is guaranteed that no overflow will occur during the reduction operation. be.

On the other hand, in order to prevent overflow from occurring in the example of FIG. 1, it is necessary that k≦L/a. Assuming that the data length is a=16 and L=64, k≦4 in the example of FIG.

On the other hand, in the present embodiment, k≦2 ⁴⁸ /p, and within the range of p≦2 ⁴⁶ , the resolution k can be made larger than in the example of FIG.

As a result, in this embodiment _, the number of pieces of transmission data D _i that can be decoded can be made larger than in the example of FIG. It becomes possible.

The following supplementary remarks are further disclosed regarding each of the embodiments described above.

(Appendix 1) An information processing device comprising a plurality of transmission nodes, an arithmetic device, and a reception node,
The transmitting node
a first vector obtained by encoding the transmission data by scalar-multiplying the encoding vector corresponding to the transmission node, among the plurality of encoding vectors associated with each of the plurality of transmission nodes, by the transmission data; A first calculation unit that calculates
a first transmission unit that transmits the first vector to the arithmetic unit;
The computing device is
a second calculation unit that calculates a second vector obtained by adding the first vectors transmitted by each of the plurality of transmission nodes;
a second transmitter that transmits the second vector to the receiving node;
The receiving node
The transmission data is obtained by solving a simultaneous linear equation with each component of the encoded vector corresponding to each of the transmission nodes as a coefficient, the simultaneous linear equation with each component of the second vector as a constant term. having a decoding unit for decoding,
An information processing device characterized by:
(Appendix 2) The information processing apparatus according to appendix 1, wherein the transmission data is data indicating either zero or non-zero.
(Appendix 3) Each of the plurality of transmission nodes further includes an execution unit that executes computation jobs in parallel,
The execution unit outputs the transmission data indicating non-zero when the calculation job ends abnormally, and outputs the transmission data indicating zero when the calculation job ends normally. 3. The information processing device according to 2.
(Additional Note 4) The first transmission unit transmits to the arithmetic device a power of 2 whose exponent is an integer value that identifies itself,
The second calculation unit calculates the sum of the powers of 2 transmitted by each of the transmission nodes,
The second transmitting unit transmits the sum to the receiving node,
The decoding unit decodes the integer value from the sum by identifying a power exponent corresponding to a bit set to 1 when the sum is expressed in binary notation as the integer value. 1. The information processing device according to 1.
(Supplementary note 5) The information processing according to Supplementary note 4, wherein when the transmission data is data indicating zero, the first transmission unit transmits zero instead of the power of 2. Device.
(Supplementary note 6) Supplementary note 4, wherein the decoding unit generates the coefficients of the simultaneous linear equations using the components of the encoded vector corresponding to the transmission node to which the identified integer value is assigned. The information processing device according to .
(Appendix 7) comprising a plurality of elements specified by a plurality of arbitrary column numbers and a plurality of row numbers equal to the plurality of column numbers among the elements of the matrix in which the components of the plurality of encoded vectors are arranged; The information processing apparatus according to appendix 1, wherein the square matrix is regular.
(Appendix 8) N is the total number of the plurality of transmission nodes, k is an integer equal to or less than the N, i is an integer value that identifies each of the plurality of transmission nodes, p is the smallest prime number equal to or greater than the N, and The encoded vector is (1, res(i), res(i ² ), ... res(i ^k-1 )), where res(i) is the remainder when i is divided by p. The information processing apparatus according to Supplementary Note 1, characterized by:

Reference Signs List 1 Parallel computer 2 Transmission node 3 Reduction device 4 Reception node 10 Information processing device 11 Node 12 Relay device 13 Arithmetic device 14 Processor 15 Memory 16 Network interface 17 processor 18 memory 21 transmission node 22 reception node 31 execution unit 32 first calculation unit 33 first transmission unit 35 first reception unit 36... Second calculator 37... Second transmitter 38... Second receiver 39... Decoder 51... Identification code part 52... Encoded payload 53... Identification code part 54... Code payload.

Claims (5)

An information processing device comprising a plurality of transmitting nodes, computing devices, and receiving nodes,
The transmitting node
a first vector obtained by encoding the transmission data by scalar-multiplying the encoding vector corresponding to the transmission node, among the plurality of encoding vectors associated with each of the plurality of transmission nodes, by the transmission data; A first calculation unit that calculates
a first transmission unit that transmits the first vector to the arithmetic unit;
The computing device is
a second calculation unit that calculates a second vector obtained by adding the first vectors transmitted by each of the plurality of transmission nodes;
a second transmitter that transmits the second vector to the receiving node;
The receiving node
The transmission data is obtained by solving a simultaneous linear equation with each component of the encoded vector corresponding to each of the transmission nodes as a coefficient, the simultaneous linear equation with each component of the second vector as a constant term. having a decoding unit for decoding,
An information processing device characterized by: 2. The information processing apparatus according to claim 1, wherein said transmission data is data indicating either zero or non-zero. The first transmission unit transmits to the arithmetic device a power of 2 whose exponent is an integer value that identifies itself,
The second calculation unit calculates the sum of the powers of 2 transmitted by each of the transmission nodes,
The second transmitting unit transmits the sum to the receiving node,
The decoding unit decodes the integer value from the sum by specifying, as the integer value, an exponent corresponding to a bit set to 1 when the sum is expressed in binary notation. Item 1. The information processing apparatus according to item 1. 4. The information processing apparatus according to claim 3, wherein when the transmission data is data indicating zero, the first transmission unit transmits zero instead of the power of two. A square matrix having a plurality of elements specified by a plurality of arbitrary column numbers and a plurality of row numbers equal to the plurality of column numbers among the elements of the matrix in which the components of the plurality of encoded vectors are arranged is 2. The information processing apparatus according to claim 1, wherein the information is regular.

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