JP7274953B2 - Display device - Google Patents

Description

Embodiments of the present invention relate to display devices.

2. Description of the Related Art When manufacturing a liquid crystal display device, a manufacturing method has been put into practical use in which a liquid crystal material is dropped onto one substrate and then the other substrate is bonded together. In such a manufacturing method, the liquid crystal material may come into contact with the seal before it is completely cured, and the liquid crystal material may be inserted into the seal. In particular, when the liquid crystal material is inserted between the substrate and the seal, the adhesive strength of the seal may be lowered, leading to a decrease in reliability.
In order to solve such a problem, for example, a technique of providing a wall-shaped spacer surrounding the entire periphery of the seal has been proposed.

JP 2016-57487 A

An object of the present embodiment is to provide a display device that suppresses deterioration in reliability.

According to this embodiment,
a first display section including first pixels; a second display section adjacent to the first display section and including second pixels; and a liquid crystal layer provided in the first display section and the second display section. a seal surrounding the first display portion and the second display portion and provided between the first display portion and the second display portion to seal the liquid crystal layer; a first inner wall and a second display portion; two inner walls, the seal having a first inner surface surrounding the first indicator and a second inner surface surrounding the second indicator, the first inner wall A display device is provided, provided along an inner surface, wherein the second inner wall is provided along the second inner surface.

FIG. 1 is a plan view showing one configuration example of the display device DSP of this embodiment. FIG. 2 is a plan view showing main parts of the display panel PNL including the seal SE shown in FIG. FIG. 3 is a diagram for explaining a method of manufacturing the display panel PNL. FIG. 4 is a diagram for explaining the manufacturing method of the display panel PNL. FIG. 5 is a diagram for explaining the manufacturing method of the display panel PNL. FIG. 6 is a cross-sectional view along AB shown in FIG. FIG. 7 is a diagram for explaining the main configuration of the first substrate SUB1. FIG. 8 is a plan view showing the relationship between the signal line S and the second seal SE2. 9 is an enlarged plan view of the area A shown in FIG. 8. FIG. FIG. 10 is a plan view showing part of the first display section DA1 and the second display section DA2 on the first substrate SUB1. FIG. 11 is a cross-sectional view of the display panel PNL along line CD shown in FIG. FIG. 12 is a cross-sectional view showing another configuration example. FIG. 13 is a cross-sectional view showing another configuration example. FIG. 14 is a cross-sectional view showing another configuration example. FIG. 15 is a cross-sectional view showing another configuration example. FIG. 16 is a cross-sectional view showing another configuration example. FIG. 17 is a cross-sectional view showing another configuration example. FIG. 18 is a cross-sectional view showing another configuration example. FIG. 19 is a cross-sectional view showing another configuration example.

Hereinafter, this embodiment will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art will naturally include within the scope of the present invention any suitable modifications that can be easily conceived while maintaining the gist of the invention. In addition, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared to the actual embodiment, but this is only an example and does not apply to the present invention. It does not limit interpretation. In addition, in this specification and each figure, the same reference numerals are given to components that exhibit the same or similar functions as those described above with respect to the previous figures, and redundant detailed description may be omitted as appropriate. .

FIG. 1 is a plan view showing one configuration example of the display device DSP of this embodiment. In this embodiment, a liquid crystal display device will be described as an example of the display device DSP.
The display device DSP has a display panel PNL and an IC chip 1 . Here, for convenience, the direction in which the short sides of the display panel PNL extend is defined as a first direction X, the direction in which the long sides of the display panel PNL extend is defined as a second direction Y, and the thickness direction of the display panel PNL is defined as a third direction Z. . In one example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees.

The display panel PNL includes a first display portion DA1 and a second display portion DA2 that display images, and a light shielding portion LS. The first display portion DA1 and the second display portion DA2 are arranged in the second direction Y. As shown in FIG. The first display section DA1 includes a plurality of first pixels PX1. The second display section DA2 includes a plurality of second pixels PX2. The plurality of first pixels PX1 and the plurality of second pixels PX2 are arranged in the first direction X and the second direction Y in a matrix. Each configuration of the first pixel PX1 and the second pixel PX2 will be described later. In the example shown in FIG. 1, the first display portion DA1 and the second display portion DA2 are both formed in a rectangular shape, but they may be formed in other polygonal shapes, circular or elliptical shapes. may be formed.

The light shielding portion LS is provided so as to surround the first display portion DA1 and the second display portion DA2, respectively, as indicated by diagonal lines. In the example shown in FIG. 1, the light shielding portion LS includes a first light shielding portion LS1 formed in a frame shape along the outer edge of the display panel PNL, and a first light shielding portion LS1 between the first display portion DA1 and the second display portion DA2. and a second light shielding portion LS2 formed in a straight line extending in one direction X. As shown in FIG. The second light shielding part LS2 is connected to the first light shielding part LS1. Each of the first display portion DA1 and the second display portion DA2 is defined by the light shielding portion LS.

Although illustration is omitted, a linear light shielding portion extending in the first direction X or a linear light shielding portion extending in the second direction Y may be provided in the first display portion DA1 and the second display portion DA2. Alternatively, in the first display portion DA1 and the second display portion DA2, the linear light shielding portion extending in the first direction X and the linear light shielding portion extending in the second direction Y may be formed in separate steps. . Such a linear light shielding portion is connected to the light shielding portion LS.
In some cases, the first display section DA1 and the second display section DA2 are provided with grid-shaped light shielding sections formed along the first direction X and the second direction Y. As shown in FIG. Such a grid-shaped light shielding portion is connected to the light shielding portion LS.

The display panel PNL includes a first substrate SUB1, a second substrate SUB2, a liquid crystal layer LC, and a seal SE. The first substrate SUB1 and the second substrate SUB2 overlap in the third direction Z. As shown in FIG. The light shielding part LS is provided on the second substrate SUB2. The liquid crystal layer LC is made of a liquid crystal material containing liquid crystal molecules, is held between the first substrate SUB1 and the second substrate SUB2, and is provided in the first display section DA1 and the second display section DA2. A cell gap between the first substrate SUB1 and the second substrate SUB2 is formed by spacers provided in the first display portion DA1 and the second display portion DA2, respectively. The seal SE contains a filler (spacer in the seal) and contributes to maintaining the cell gap.

The seal SE bonds the first substrate SUB1 and the second substrate SUB2 together and seals the liquid crystal layer LC. In one example, the seal SE is formed in the shape of a continuous loop without interruption and does not include a liquid crystal injection port. In the example shown in FIG. 1, the seal SE consists of a first seal SE1 formed in a frame shape along the outer edge of the display panel PNL, and a first seal SE1 between the first display portion DA1 and the second display portion DA2. and a second seal SE2 formed in a straight line extending in X direction. The first seal SE1 is provided so as to entirely overlap the first light shielding portion LS1 and surround the first display portion DA1 and the second display portion DA2. The second seal SE2 entirely overlaps the second light shielding portion LS2, is provided between the first display portion DA1 and the second display portion DA2, and is connected to the first seal SE1. When such seals SE are drawn by a dispenser, the first seal SE1 and the second seal SE2 can be drawn with a single stroke. The shape of the seal SE is not limited to the illustrated example. For example, the second seal SE2 may be spaced apart from the first seal SE1.

The second seal SE2 has at least one opening OP that communicates the first display portion DA1 and the second display portion DA2. In the example shown in FIG. 1, the second seal SE2 has one opening OP. The opening OP allows the liquid crystal material of the first display portion DA1 to move to the second display portion DA2 or the liquid crystal material of the second display portion DA2 to move to the first display portion DA1. In other words, the first display section DA1 has a first chamber R1 surrounded by the first substrate SUB1, the second substrate SUB2, the first seal SE1 and the second seal SE2, and the second display section DA2 It has a second chamber R2 surrounded by a first substrate SUB1, a second substrate SUB2, a first seal SE1 and a second seal SE2. Further, the second seal SE2 is formed with a communication passage (opening OP) that communicates the first chamber R1 and the second chamber R2. It is filled with a liquid crystal layer LC. This allows the liquid crystal material of the liquid crystal layer LC to move from the first chamber R1 to the second chamber R2 and from the second chamber R2 to the first chamber R1 through the communication path.

The first substrate SUB1 has a mounting portion MA. The IC chip 1 is mounted on the mounting portion MA. The mounting portion MA includes a terminal portion TA for electrically connecting the flexible printed circuit board 2 indicated by dotted lines. Note that the IC chip 1 may be mounted on the flexible printed circuit board 2 .

FIG. 2 is a plan view showing main parts of the display panel PNL including the seal SE shown in FIG. The display panel PNL includes a first inner wall IW1, a second inner wall IW2, and a first outer wall OW1 and a second outer wall OW2. The first inner wall IW1 is provided between the first display portion DA1 and the seal SE. The second inner wall IW2 is provided between the second display portion DA2 and the seal SE.

More specifically, the seal SE includes a first inner surface I1 surrounding the first display portion DA1, a second inner surface I2 surrounding the second display portion DA2, a first outer surface O1, and a second outer surface O2. and have Of the seals SE, the first seal SE1 has a first outer surface O1 opposite to the first inner surface I1 and a second outer surface O2 opposite to the second inner surface I2. In the second seal SE2 of the seals SE, the second inner side surface I2 is located on the side opposite to the first inner side surface I1.

The first inner wall IW1 is provided along the first inner surface I1, and the second inner wall IW2 is provided along the second inner surface I2. The first outer wall OW1 is provided along the first outer surface O1, and the second outer wall OW2 is provided along the second outer surface O2. That is, among the stickers SE, the first seal SE1 around the first display portion DA1 is provided between the first inner wall IW1 and the first outer wall OW1, and the first seal SE1 around the second display portion DA2 is provided between the first inner wall IW1 and the first outer wall OW1. A second seal SE2 is provided between the second inner wall IW2 and the second outer wall OW2, and the second seal SE2 between the first display portion DA1 and the second display portion DA2 is provided between the first inner wall IW1 and the second inner wall IW2. there is

Each of the first display portion DA1 and the second display portion DA2 is formed in a substantially rectangular shape. The sticker SE is provided along each side of the first display section DA1 and the second display section DA2. For example, focusing on the first display portion DA1, the first display portion DA1 has four edges E11 to E14 and four corners C11 to C14. The first inner wall IW1 and the first outer wall OW1 are formed in a line shape along the edges E11 to E14, respectively, and are formed in a round shape (or an arc shape) corresponding to the corners C11 to C14.
Similarly, the second display portion DA2 has four edges E21 to E24 and four corners C21 to C24. The second inner wall IW2 and the second outer wall OW2 are formed in a line shape along edges E21 to E24, respectively, and are formed in a round shape (or arc shape) corresponding to corners C21 to C24.
The first inner wall IW1 and the second inner wall IW2 are formed in a line between the first display portion DA1 and the second display portion DA2. The first outer wall OW1 and the second outer wall OW2 are formed in a round shape at corners C13 and C23, respectively, and are connected to each other. Similarly, the first outer wall OW1 and the second outer wall OW2 are also formed in a round shape at corners C14 and C24, respectively, and connected.

The first seal SE1 along the edges E11 to E13 is formed linearly between the first inner wall IW1 and the first outer wall OW1. The first seal SE1 along the edges E21 to E23 is formed linearly between the second inner wall IW2 and the second outer wall OW2. The second seal SE2 along the edges E14 and E24 is formed linearly between the first inner wall IW1 and the second inner wall IW2. Also, the seal SE is formed in a round shape corresponding to corners C11 to C14 and corners C21 to C24.

The first inner wall IW1 and the second inner wall IW2 are provided between the seal SE and the liquid crystal layer LC to prevent contact between the liquid crystal layer LC and the seal SE. The first inner wall IW1 and the second inner wall IW2 each have a gap IS. In the gap IS, the liquid crystal layer LC is in contact with the seal SE. Note that the first outer wall OW1 and the second outer wall OW2 may each have a gap. Moreover, it is desirable that neither the first inner wall IW1 nor the second inner wall IW2 be provided in the opening OP so as not to hinder the movement of the liquid crystal material.

Next, an example of a method for manufacturing the display panel PNL will be described with reference to FIGS. 3 to 5. FIG. In the following manufacturing method, it is assumed that none of the first inner wall, the second inner wall, the first outer wall, and the second outer wall of the present embodiment are provided.

First, as shown in FIG. 3, a first mother substrate M1 is prepared. The first mother substrate M1 is formed using a large glass substrate as a base, and has a plurality of effective areas AA. A dashed-dotted line in the drawing indicates the cut line CL of the first mother substrate M1. Each of the effective areas AA is surrounded by cut lines CL. When the first mother substrate M1 is cut along the cut lines CL in a later process, each of the effective areas AA is provided with various insulating films, various conductive layers, etc., and constitutes the first substrate SUB1.
In each effective area AA of the first mother substrate M1, a seal SE is formed so as to surround the first display area DA1 and the second display area DA2, and all the effective areas AA are formed in the outermost periphery of the first mother substrate M1. An outermost peripheral seal SO is formed so as to surround it. The outermost peripheral seal SO is formed in a continuous loop shape without interruption. After bonding the first mother substrate M1 and the second mother substrate M2 together, the outermost peripheral seal SO forms each effective area AA when chemically polishing (thinning) the glass substrate with hydrofluoric acid. Provided to protect against hydrofluoric acid.

Subsequently, as shown in FIG. 4, in each effective area AA, the liquid crystal material LM is dropped inside the area surrounded by the seal SE. The dropping amount of the liquid crystal material LM is set based on the cell gap between the first substrate SUB1 and the second substrate SUB2. In each of the first display section DA1 and the second display section DA2, the pitch of the dropping positions of the liquid crystal material LM along the first direction X is set to be substantially equal, and the liquid crystal material LM is dropped along the second direction Y. The pitch of the positions is also set substantially equal.

Subsequently, as shown in FIG. 5, a second mother substrate M2 is prepared. The second mother substrate M2 is formed using a large glass substrate as a base. Then, the first mother substrate M1 and the second mother substrate M2 are bonded together in an environment (for example, a vacuum environment) where the pressure is reduced below the atmospheric pressure. After that, when released to an environment of atmospheric pressure, the atmospheric pressure is applied to the first mother substrate M1 and the second mother substrate M2, and the dropped liquid crystal material LM, the pre-cured seal SE and the outermost peripheral seal SO spread out. , in each effective area AA, the liquid crystal material LM and the seal SE are in contact. At this time, between the adjacent seals SE, an area (for example, an area in a vacuum state) AB whose pressure is reduced below the atmospheric pressure is formed. Therefore, the seal SE expands inward toward the liquid crystal material LM and outward toward the region AB.

FIG. 6 is a cross-sectional view along AB shown in FIG.
(A) of FIG. 6 schematically shows a state immediately after being released to an environment of atmospheric pressure. A stress F1 is generated in the liquid crystal material LM to spread toward the seal SE. A stress F2 that tends to spread toward the liquid crystal material LM and a stress F3 that tends to spread toward the region AB are generated in the seal SE. When region AB is in a high vacuum state, stress F3 increases and stress F2 decreases accordingly.
FIG. 6B schematically shows how the liquid crystal material LM and the pre-cured seal SE come into contact with each other. As shown in FIG. 6A, when the magnitude of the stress F1 exceeds the magnitude of the stress F2 as the stress F2 decreases, the liquid crystal material LM penetrates the seal SE before curing. In particular, the liquid crystal material LM is easily inserted into the interface between the seal SE and the first mother substrate M1 or the interface between the seal SE and the second mother substrate M2. Such a phenomenon in which the liquid crystal material LM is inserted causes a decrease in the adhesive strength between the seal SE and each substrate.

In a region where the liquid crystal material LM is dropped at a position close to the seal SE, the stress F1 of the liquid crystal material LM is particularly large, and the difference from the stress F2 of the seal SE is large, so insertion is likely to occur. If all drip positions are sufficiently far from the seal SE, insertion is less likely to occur. However, it is not always possible to set all dropping positions at desired positions due to various restrictions such as the convenience of manufacturing equipment, screen size, and substrate size. Therefore, it is required to suppress insertion without being subject to various restrictions.

According to this embodiment, as described with reference to FIG. 2, the first inner wall IW1 is provided along the first inner surface I1 of the seal SE, and the second inner wall IW2 is provided along the second inner surface I2. are set along. Therefore, the contact area between the seal SE and the liquid crystal layer LC can be reduced. As a result, in the manufacturing process described above, the stress F1 of the liquid crystal material LM does not directly act on the seal SE, and the insertion of the liquid crystal material LM into the seal SE (in particular, between the seal and the first substrate and between the seal and the first substrate). insertion between two substrates) is suppressed. Therefore, the deterioration of the adhesive strength of the seal SE is suppressed and the deterioration of reliability is suppressed without being subject to various restrictions.

Also, the first inner wall IW1 and the second inner wall IW2 are provided between the first display section DA1 and the second display section DA2. For this reason, the stress of each of the liquid crystal material LM dropped onto the first display portion DA1 and the liquid crystal material LM dropped onto the second display portion DA2 causes stress between the first display portion DA1 and the second display portion DA2. , the liquid crystal material LM is suppressed from being inserted into the second seal SE2.

A first outer wall OW1 is provided along the first outer surface O1 of the seal SE, and a second outer wall OW2 is provided along the second outer surface O2. For this reason, even when the pressure-reduced area AB is formed outside the seal SE in the manufacturing process described above, the first outer wall OW1 and the second outer surface O2 prevent the seal SE from spreading excessively. be. Moreover, the increase in the stress F3 shown in FIG. 6A is suppressed, and the decrease in the stress F2 is suppressed. Therefore, the difference between the magnitude of the stress F1 and the magnitude of the stress F2 becomes small, and the insertion of the liquid crystal material LM is suppressed.

A gap IS is provided between the first inner wall IW1 and the second inner wall IW2. For this reason, for example, when the first mother substrate M1 and the second mother substrate M2 are bonded together in a manufacturing process in a vacuum environment, there is a large gap between the seal SE and the first inner wall IW1, or between the seal SE and the second inner wall IW2. Even if an air bubble (vacuum void) is formed between the gaps IS, the air bubbles can escape. This prevents air bubbles from being left in the vicinity of the seal SE or being taken into the liquid crystal layer LC in a later process.

Each of the first inner wall IW1 and the second inner wall IW2 may be partially provided in a region where insertion is expected (a region where the dropping position and the seal are close to each other).

FIG. 7 is a diagram for explaining the main configuration of the first substrate SUB1.
The first substrate SUB1 includes a plurality of scanning lines G1 provided in the first display area DA1, a plurality of scanning lines G2 provided in the second display area DA2, and a plurality of scanning lines G2 provided in the first display area DA1 and the second display area DA2. a plurality of signal lines S provided across, gate drivers GD11 and GD12 provided close to the first display section DA1, gate drivers GD21 and GD22 provided close to the second display section DA2, It has

The gate drivers GD11 and GD21 are connected to each other via a bus line B1. The gate drivers GD12 and GD22 are connected to each other via a bus line B2. The bus wires B1 and B2 are electrically connected to the IC chip 1, for example. Each of the bus wires B1 and B2 includes, for example, a wire for supplying a start pulse, a wire for supplying a clock, a high potential power line (VGH), a low potential power line (VGL), and the like. A region of the bus wiring B1 between the gate driver GD11 and the gate driver GD21 is called a relay portion BR1. A region of the bus wiring B2 between the gate driver GD12 and the gate driver GD22 is called a relay portion BR2. These relay units BR1 and BR2 do not include a circuit configuration.

Attention will be paid to the relationship between the first light shielding portion LS1 and the second light shielding portion LS2 shown in FIG. 1 and the like and the gate drivers GD12 and GD22. The gate drivers GD12 and GD22 overlap the first light shielding portion LS1. The relay portion BR2 is provided at a connecting portion (crossing portion) between the first light shielding portion LS1 and the second light shielding portion LS2. None of the circuit configurations of the gate drivers GD12 and GD22 is provided in the vicinity of such a connection portion. Incidentally, the relay portion BR1 is also provided in the connection portion in the same manner.

The multiple scanning lines G1 are electrically connected to at least one of the gate drivers GD11 and GD12. The multiple scanning lines G2 are electrically connected to at least one of the gate drivers GD21 and GD22.

The IC chip 1 incorporates a display driver DD. The display driver DD outputs signals necessary for image display, such as video signals, to the display panel PNL in an image display mode for displaying an image. A plurality of signal lines S are electrically connected to the display driver DD. Each of the signal lines S is electrically connected to the first pixel PX1 and the second pixel PX2.

For example, in the first pixel PX1, the first substrate SUB1 includes a switching element SW1 and a pixel electrode PE1. The switching element SW1 is electrically connected to the scanning line G1 and the signal line S. The pixel electrode PE1 is electrically connected to the switching element SW1. The first substrate SUB1 also includes a common electrode CE1. The common electrode CE1 is provided in common for the plurality of first pixels PX1. Note that the common electrode CE1 may be provided on the second substrate SUB2. The capacitor CS1 is formed, for example, between an electrode having the same potential as the common electrode CE1 and an electrode having the same potential as the pixel electrode PE1. In the first display section DA1, the liquid crystal layer LC is driven by an electric field generated between the pixel electrode PE1 and the common electrode CE1.

In the second pixel PX2, the first substrate SUB1 includes a switching element SW2 and a pixel electrode PE2. The switching element SW2 is electrically connected to the scanning line G2 and the signal line S. The pixel electrode PE2 is electrically connected to the switching element SW2. The first substrate SUB1 also includes a common electrode CE2. The common electrode CE2 is provided in common for the plurality of second pixels PX2. Note that the common electrode CE2 may be provided on the second substrate SUB2. The capacitor CS2 is formed, for example, between an electrode having the same potential as the common electrode CE2 and an electrode having the same potential as the pixel electrode PE2. In the second display section DA2, the liquid crystal layer LC is driven by an electric field generated between the pixel electrode PE2 and the common electrode CE2. The first pixel PX1 and the second pixel PX2 each have a color filter, and these color filters may be provided on the first substrate SUB1 or the second substrate SUB2.

FIG. 8 is a plan view showing the relationship between the signal line S and the second seal SE2.
Each of the signal lines S intersects the second light shielding portion LS2, and is provided continuously across the first display portion DA1 and the second display portion DA2. Among the plurality of signal lines S, the first signal line S1 overlaps the opening OP of the second seal SE2 in the second light shielding portion LS2. Also, the second signal line S2 crosses the second seal SE2 at the second light shielding portion LS2.
No scanning line is provided to overlap the second light shielding portion LS2 and the second seal SE2. Alternatively, no wiring crossing the signal line S is provided in the region overlapping the second light shielding portion LS2 and the second seal SE2.

9 is an enlarged plan view of the area A shown in FIG. 8. FIG. This plan view shows only the main part. The plurality of second signal lines S2 intersect the first inner wall IW1, the second seal SE2, and the second inner wall IW2 between the first display portion DA1 and the second display portion DA2. Also, the second signal line S2 may intersect the second seal SE via the gap IS. If the pitch of the second signal lines S2 is smaller than the width of the gap IS, one or more second signal lines S2 are provided to pass through the gap IS.

FIG. 10 is a plan view showing part of the first display section DA1 and the second display section DA2 on the first substrate SUB1. Here, only the main parts necessary for explanation are illustrated, the first light shielding part LS1 and the second light shielding part LS2 are indicated by dotted lines, and the linear light shielding parts provided in the first display part DA1 and the second display part DA2 are shown. Alternatively, illustration of the grid-shaped light shielding portion is omitted.

The first substrate SUB1 includes a feeder line F and conductive films TF1 and TF2. The power supply line F is a wiring for supplying a common potential to the common electrodes CE1 and CE2, and is provided in the same layer as the signal line S, for example, as will be described later. Each of the conductive films TF1 and TF2 overlaps the first light shielding portion LS1 and the second light shielding portion LS2. The conductive film TF2 is separated from the conductive film TF1. A portion of the conductive film TF1 and a portion of the conductive film TF2 overlap the feeder line F, respectively. The conductive film TF1 is provided around the first display portion DA1 and separated from the pixel electrode PE1. The conductive film TF1 has a dummy pattern DP1 having the same shape as the pixel electrode PE1 on the side adjacent to the first display portion DA1. The conductive film TF2 is provided around the second display portion DA2 and separated from the pixel electrode PE2. The conductive film TF2 has a dummy pattern DP2 having the same shape as the pixel electrode PE2 on the side adjacent to the second display portion DA2. Both the dummy patterns DP1 and DP2 overlap the first light shielding portion LS1 and the second light shielding portion LS2.

The common electrode CE1 overlaps the pixel electrode PE1 in the first display portion DA1. Also, the common electrode CE1 overlaps the conductive film TF1 including the dummy pattern DP1. At the connection portion CN1 overlapping the first light shielding portion LS1, the power supply line F, the common electrode CE1, and the conductive film TF1 are electrically connected to each other. That is, the conductive film TF1 has the same potential as the common electrode CE1.
The common electrode CE2 is separated from the common electrode CE1. The common electrode CE2 overlaps the pixel electrode PE2 in the second display area DA2. Also, the common electrode CE2 overlaps the conductive film TF2 including the dummy pattern DP2. At the connection portion CN2 overlapping the first light shielding portion LS1, the power supply line F, the common electrode CE2, and the conductive film TF2 are electrically connected to each other.

FIG. 11 is a cross-sectional view of the display panel PNL along line CD shown in FIG. Although the cross-sectional structure of the first display portion DA1 will be described here, the second display portion DA2 also has the same cross-sectional structure as the first display portion DA1.

The first substrate SUB1 includes an insulating substrate 10, insulating films 11 to 13, bus wiring B1, power supply line F, signal line S, metal wiring ML, common electrode CE1, conductive film TF1, alignment film AL1, and the like. The scanning lines G1 and G2 and the switching elements SW1 and SW2 shown in FIG. 7 are provided between the insulating substrate 10 and the insulating film 11, for example. The bus wiring B1, the feeder line F, and the signal line S are provided between the insulating films 11 and 12. As shown in FIG. A drain electrode DE of the switching element is also provided between the insulating films 11 and 12 . A metal wiring ML is provided between the insulating films 12 and 13 . Note that the metal wiring ML extends along the second direction Y and is provided so as to overlap the signal line S in plan view. The metal wiring ML is in contact with the common electrode CE1. That is, the common electrode CE1 is electrically connected to the metal wiring ML. As a result, the resistance of the common electrode CE1 is reduced in the first display section DA1.
The conductive film TF1 is provided between the insulating film 13 and the alignment film AL1. An insulating film 13 is interposed between the common electrode CE1 and the conductive film TF1. The common electrode CE1 is in contact with the feeder line F at the connection portion CN1, and the conductive film TF1 is in contact with the common electrode CE1 at the connection portion CN1 and electrically connected to each other. Thereby, a common potential is supplied from the power supply line F to the common electrode CE1 and the conductive film TF1.
The pixel electrode PE1 is provided between the insulating film 13 and the alignment film AL1, similarly to the conductive film TF1. The pixel electrode PE1 is in contact with the drain electrode DE of the switching element and electrically connected to each other. The first spacer SP1 is provided at the connecting portion between the pixel electrode PE1 and the drain electrode DE.

The second substrate SUB2 includes an insulating substrate 20, a first light shielding portion LS1, a second light shielding portion LS2, a color filter layer CF, an overcoat layer OC, an alignment film AL2, and the like. The first light shielding part LS1 and the second light shielding part LS2 are provided between the insulating substrate 20 and the overcoat layer OC. The color filter layer CF is provided between the overcoat layer OC and the alignment film AL2. The color filter layer CF includes, for example, red color filters CFR, green color filters CFG, and blue color filters CFB. The color filter layer CF is provided not only in the first display section DA1 but also in the second display section DA2, and part of it overlaps the second light shielding section LS2. The second spacer SP2 is provided in contact with the first spacer SP1. These first spacer SP1 and second spacer SP2 form a cell gap.

The first seal SE1 is provided directly under the first light shielding part LS1 and is in contact with the alignment films AL1 and AL2. The first seal SE1 includes an in-seal spacer SS (or sometimes referred to as a filler). The second seal SE2 is constructed similarly to the first seal SE1.

The insulating substrates 10 and 20 are transparent substrates such as glass substrates and resin substrates. The insulating films 11 and 13 are transparent inorganic insulating films. The insulating film 12 and the overcoat layer OC are transparent organic insulating films. The bus wiring B1, the power supply line F, the signal line S, the drain electrode DE, and the metal wiring ML are made of an opaque metal material. The common electrode CE1, the conductive film TF1, and the pixel electrode PE1 are transparent electrodes made of a transparent conductive material. The first spacer SP1 and the second spacer SP2 are made of, for example, a transparent organic insulating material.

A first optical element OD1 including a first polarizing plate PL1 is adhered to an insulating substrate 10, and a second optical element OD2 including a second polarizing plate PL2 is adhered to an insulating substrate 20. FIG. Each of the first optical element OD1 and the second optical element OD2 may include a retardation plate or the like as necessary. The first polarizing plate PL1 and the second polarizing plate PL2 are provided so that the first polarizing axis AX1 of the first polarizing plate PL1 and the second polarizing axis AX2 of the second polarizing plate PL2 have a crossed Nicols relationship. .

Here, one configuration example of the first inner wall IW1 and the first outer wall OW1 surrounding the first seal SE1 will be described. The second inner wall IW2 has a cross-sectional structure similar to that of the first inner wall IW1, and the second outer wall OW2 has a cross-sectional structure similar to that of the first outer wall OW1. Description is omitted.
The first inner wall IW1 includes a first protrusion P1 provided on the first substrate SUB1 and a second protrusion P2 provided on the second substrate SUB2. The first protrusion P1 is provided on the conductive film TF1 and protrudes toward the second substrate SUB2. The second protrusion P2 faces the first protrusion P1, is provided on the overcoat layer OC, and protrudes toward the first substrate SUB1.
The first outer wall OW1 includes a third protrusion P3 provided on the first substrate SUB1 and a fourth protrusion P4 provided on the second substrate SUB2. The third protrusion P3 is provided on the insulating film 12 and protrudes toward the second substrate SUB2. The fourth protrusion P4 faces the third protrusion P3, is provided on the overcoat layer OC, and protrudes toward the first substrate SUB1.

The first protrusion P1 and the third protrusion P3 are made of the same material as the first spacer SP1. At least part of the first protrusion P1 and the third protrusion P3 is covered with the alignment film AL1. The second protrusion P2 and the fourth protrusion P4 are made of the same material as the second spacer SP2. At least part of the second protrusion P2 and the fourth protrusion P4 is covered with the alignment film AL2.
Although the alignment film AL1 is interposed between the first protrusion P1 and the third protrusion P3 and the first seal SE1, the first protrusion P1 and the third protrusion P3 are in contact with the first seal SE1. may be Although the alignment film AL2 is interposed between the second protrusion P2 and the fourth protrusion P4 and the first seal SE1, the second protrusion P2 and the fourth protrusion P4 are in contact with the first seal SE1. may be Further, a liquid crystal layer LC may be interposed between the first protrusion P1 and the second protrusion P2 and the first seal SE1. An air layer may be interposed between the third protrusion P3 and the fourth protrusion P4 and the first seal SE1.

In the configuration example shown in FIG. 11, the second protrusion P2 is positioned directly above the first protrusion P1 along the third direction Z and is spaced apart from the first protrusion P1. The first seal SE1 is in contact with the liquid crystal layer LC between the first protrusion P1 and the second protrusion P2. The gap between the first convex portion P1 and the second convex portion P2 functions in the same manner as the gap IS described with reference to FIG. 2 and the like. Therefore, when the first protrusion P1 and the second protrusion P2 are separated from each other at IW1 on the first inner wall, the gap IS shown in FIG. 2 may be omitted.

The fourth protrusion P4 is positioned directly above the third protrusion P3 along the third direction Z and is spaced apart from the third protrusion P3. The first seal SE1 is in contact with the air layer between the third protrusion P3 and the fourth protrusion P4.

In such a configuration example, in the manufacturing process of the display panel PNL, the first convex portion P1 and the second convex portion P2 function as barriers against the liquid crystal material spreading toward the first seal SE1. The insertion of the liquid crystal material between the first seal SE1 and between the alignment film AL2 and the first seal SE1 is suppressed.

Next, another configuration example will be described. 12 to 18, only main parts are shown, and illustration of the alignment films AL1 and AL2 is omitted.

FIG. 12 is a cross-sectional view showing another configuration example. In the configuration example shown in FIG. 12, the first protrusion P1 and the second protrusion P2 are in contact with each other on the first inner wall IW1, and the third protrusion P3 and the fourth convex portion P4 are in contact with each other. Between the first protrusion P1 and the second protrusion P2, the first seal SE1 is not in contact with the liquid crystal layer LC.
Even in such a configuration example, the same effect as the above configuration example can be obtained. In addition, in the manufacturing process, the inward expansion of the first seal SE1 is suppressed by the first inner wall IW1, and the outward expansion is suppressed by the first outer wall OW1. Also, contact of the liquid crystal material with the first seal SE1 is suppressed.

FIG. 13 is a cross-sectional view showing another configuration example. Compared with the configuration example shown in FIG. 11, the configuration example shown in FIG. The difference is that one outer wall OW1 is configured by the fourth convex portion P4. The second protrusion P2 and the fourth protrusion P4 may be omitted, and the first inner wall IW1 may be formed by the first protrusion P1, or the first outer wall OW1 may be formed by the third protrusion P3. good. That is, the first inner wall IW1 is composed of at least one of the first convex portion P1 and the second convex portion P2. Further, the first outer wall OW1 is composed of at least one of the third protrusion P3 and the fourth protrusion P4.
The second protrusion P2 is separated from the first substrate SUB1. The first seal SE1 is in contact with the liquid crystal layer LC between the second protrusion P2 and the first substrate SUB1. Note that the second protrusion P2 may be in contact with the first substrate SUB1. Also, although the fourth protrusion P4 is separated from the first substrate SUB1, it may be in contact with the first substrate SUB1.
Even in such a configuration example, the same effect as the above configuration example can be obtained.

FIG. 14 is a cross-sectional view showing another configuration example. Compared with the configuration example shown in FIG. 13, the configuration example shown in FIG. The difference is that a black layer 32 is provided to overlap. The black layers 31 and 32 are provided between the first light shielding part LS1 and the overcoat layer OC.
For example, the first light shielding portion LS1 is formed together with a linear light shielding portion extending in the first direction X in the first display portion DA1, and the black layers 31 and 32 are linear light shielding portions extending in the second direction Y in the first display portion DA1. It is formed together with the light shielding part. The black layers 31 and 32 are made of the same material as the first light shielding part LS1. In one example, the first light shielding part LS1 and the black layers 31 and 32 are made of a black organic insulating material. The overcoat layer OC covers the first light shielding part LS1 and the black layers 31 and 32 . An overcoat layer OC is interposed between the second convex portion P2 and the black layer 31 and between the fourth convex portion P4 and the black layer 32, respectively.
Even in such a configuration example, the same effect as the above configuration example can be obtained.

FIG. 15 is a cross-sectional view showing another configuration example. Compared with the configuration example shown in FIG. 13, the configuration example shown in FIG. The difference is that the colored layer 34 is provided to overlap. The colored layers 33 and 34 are provided between the first light shielding part LS1 and the overcoat layer OC.
The colored layers 33 and 34 are made of, for example, the same material as any one of the red color filter CFR, green color filter CFG, and blue color filter CFB shown in FIG. The color of the colored layer 33 may be the same as the color of the colored layer 34 or may be different from the color of the colored layer 34 . Also, each of the colored layers 33 and 34 may be a laminate in which two or more color filters are laminated. The overcoat layer OC covers the first light shielding portion LS1 and the colored layers 33 and . An overcoat layer OC is interposed between the second convex portion P2 and the colored layer 33 and between the fourth convex portion P4 and the colored layer 34, respectively.
Even in such a configuration example, the same effect as the above configuration example can be obtained.

FIG. 16 is a cross-sectional view showing another configuration example. In the configuration example shown in FIG. 16, in comparison with the configuration example shown in FIG. The difference is that a black layer 32 is provided instead. The black layers 31 and 32 are formed in the same manner as in the configuration example shown in FIG. The overcoat layer OC covers the first light shielding part LS1 and the black layers 31 and 32 .
The overcoat layer OC is separated from the first substrate SUB1. Between the overcoat layer OC and the first substrate SUB1, the first seal SE1 is in contact with the liquid crystal layer LC.
Even in such a configuration example, the same effect as the above configuration example can be obtained.

FIG. 17 is a cross-sectional view showing another configuration example. Compared with the configuration example shown in FIG. 13, the configuration example shown in FIG. The difference is that a colored layer 34 is provided instead. The colored layers 33 and 34 are formed in the same manner as in the configuration example shown in FIG. The overcoat layer OC covers the first light shielding portion LS1 and the colored layers 33 and .
Even in such a configuration example, the same effect as the above configuration example can be obtained.

FIG. 18 is a cross-sectional view showing another configuration example. The configuration example shown in FIG. 18 is different from the configuration example shown in FIG. is provided with a laminate of a black layer 32 and a colored layer 34 instead of the fourth convex portion P4. The black layer 31 is provided between the first light shielding portion LS1 and the colored layer 33 . The black layer 32 is provided between the first light shielding portion LS1 and the colored layer 34 . The overcoat layer OC covers the first light shielding part LS1, the black layers 31 and 32, and the colored layers 33 and 33. As shown in FIG.
Even in such a configuration example, the same effect as the above configuration example can be obtained.

FIG. 19 is a cross-sectional view showing another configuration example. Compared with the configuration example shown in FIG. 18, the configuration example shown in FIG. 32 and the colored layer 34, and a fourth convex portion P4 is provided.
Even in such a configuration example, the same effect as the above configuration example can be obtained.

In each of the configuration examples described above, the first outer wall OW1 is configured to have the same cross-sectional structure as the first inner wall IW1, but the configuration is not limited to this. That is, different configuration examples may be applied to the first inner wall IW1 and the first outer wall OW1.

As described above, according to this embodiment, it is possible to provide a display device that suppresses deterioration in reliability.

It should be noted that although several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and its equivalents.

DSP... display device PNL... display panel SUB1... first substrate SUB2... second substrate LC... liquid crystal layer SE... seal SE1... first seal SE2... second seal OP... opening DA1... first display section DA2... second display section LS...Light shielding part LS1...First light shielding part LS2...Second light shielding part IW1...First inner wall IW2...Second inner wall IS...Gap OW1...First outer wall OW2...Second outer wall P1...First convex part P2...Second convex part Part P3... 3rd convex part P4... 4th convex part 31, 32... Black layer 33, 34... Colored layer

Claims (8)

a first display unit having a first pixel;
a second display unit adjacent to the first display unit and including a second pixel;
a liquid crystal layer provided in the first display section and the second display section;
a seal provided around the first display section and the second display section and between the first display section and the second display section for sealing the liquid crystal layer;
a first inner wall and a second inner wall;
a first outer wall and a second outer wall ;
The seal has a first inner surface facing the first display portion, a second inner surface facing the second display portion, a first outer surface opposite to the first inner surface, and the second inner surface. a second outer surface opposite the inner surface ;
The first inner wall is provided along the first inner surface,
The second inner wall is provided along the second inner surface ,
The first outer wall is provided along the first outer surface,
The second outer wall is provided along the second outer surface,
The display device, wherein the first outer wall and the second outer wall are formed in a round shape at corners of the first display section and the second display section and are connected to each other. 2. The display device according to claim 1, wherein said first inner wall and said second inner wall are linearly formed along edges of said first display portion and said second display portion. 3. The display device according to claim 2, wherein said first inner wall and said second inner wall are rounded at corners of said first display portion and said second display portion. 4. The display device according to claim 1, wherein said first inner wall and said second inner wall have a gap. further comprising a first substrate and a second substrate that hold the liquid crystal layer and are bonded by the seal;
The first inner wall comprises at least one of a first protrusion provided on the first substrate and a second protrusion provided on the second substrate and facing the first protrusion. 5. The display device according to any one of 1 to 4 . 6. The display device according to claim 5 , wherein said first inner wall further comprises a black layer overlapping said second protrusion. 6. The display device according to claim 5 , wherein said first inner wall further comprises a colored layer superimposed on said second protrusion. 5. The display device according to claim 1, wherein said first inner wall is formed of at least one of a black layer and a colored layer.

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