JP7271754B2 - semiconductor equipment - Google Patents

Description

The present invention relates to semiconductor devices.

WL-CSP (Wafer Level Chip Size Package) is a semiconductor device packaging technology that performs rewiring, electrode formation, resin sealing, and dicing in a wafer process. Also known is a multi-chip WL-CSP that includes a plurality of stacked semiconductor chips.

The multi-chip WL-CSP is designed such that the planar size of the package is approximately the same as the planar size of any one of the semiconductor chips housed in the package, and the height of the package is the same as that of a plurality of semiconductors housed in the package. Since the height is substantially the same as the height of the stack of chips, it is possible to reduce the package size while improving the performance of the semiconductor device. In addition, since connection between a plurality of semiconductor chips is performed by flip-chip bonding, wire bonding becomes unnecessary, and performance can be improved, such as delay in communication between semiconductor chips being suppressed.

Patent Document 1 describes a process of forming columnar electrodes on a semiconductor wafer, a process of flip-chip bonding a second semiconductor chip on the semiconductor wafer, and a process of covering the columnar electrodes and the second semiconductor chip on the semiconductor wafer. A method of manufacturing a semiconductor device, comprising: forming a sealing portion for sealing; and grinding the sealing portion and the second semiconductor chip so that the top surface of the columnar electrode and the top surface of the second semiconductor chip are exposed. Are listed.

JP 2008-218926 A

One of the challenges of multi-chip WL-CSP is to improve the reliability of bonding between semiconductor chips.

One method for improving the reliability of bonding between semiconductor chips is to fill the gaps formed between the semiconductor chips with sealing resin and harden it to fix the bonding between the semiconductor chips. Conceivable.

However, since the sealing resin has a relatively high viscosity, it is not easy to evenly fill the gaps formed between the semiconductor chips with the sealing resin. If the gap formed between the semiconductor chips is not filled with the sealing resin, the reliability of the bonding between the semiconductor chips is lowered.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to improve the reliability of bonding between semiconductor chips by promoting filling of a sealing resin into a gap formed between semiconductor chips. and

A semiconductor device according to the present invention includes: a first semiconductor chip having a plurality of first electrodes on its surface; a second semiconductor chip having an inner peripheral region having a second electrode on the surface thereof, and an outer peripheral region surrounding the inner peripheral region and having a thickness smaller than the thickness of the inner peripheral region; a sealing resin filled between the surface and the inner peripheral region and between the surface of the first semiconductor chip and the outer peripheral region, respectively; the region includes a semiconductor substrate, a first insulating film, a second insulating film formed on the first insulating film, and a third insulating film formed on the second insulating film; It does not include a third insulating film, but includes the semiconductor substrate and the first insulating film.

According to the present invention, it is possible to promote the filling of the sealing resin into the gap formed between the semiconductor chips, and to improve the reliability of the bonding between the semiconductor chips.

1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment of the invention; FIG. 1 is a plan view showing an example of a configuration of a first semiconductor chip according to an embodiment of the invention; FIG. FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 2; 1 is a cross-sectional view showing an example of a configuration of a second semiconductor chip according to an embodiment of the invention; FIG. FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the first semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a preparation process for the second semiconductor chip according to the embodiment of the present invention; It is a sectional view showing an example of a packaging process concerning an embodiment of the present invention. It is a sectional view showing an example of a packaging process concerning an embodiment of the present invention. It is a sectional view showing an example of a packaging process concerning an embodiment of the present invention. It is a sectional view showing an example of a packaging process concerning an embodiment of the present invention. It is a sectional view showing an example of a packaging process concerning an embodiment of the present invention. FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to another embodiment of the invention; FIG. 4 is a cross-sectional view showing an example of the configuration of a second semiconductor chip according to another embodiment of the invention;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or portions are given the same reference numerals.

FIG. 1 is a cross-sectional view showing the overall configuration of a semiconductor device 1 according to an embodiment of the invention. FIG. 2 is a plan view of the first semiconductor chip 101 constituting the semiconductor device 1 viewed from the electrode forming surface S11 side. 3 is a cross-sectional view taken along line 3-3 in FIG. 2. FIG. FIG. 4 is a cross-sectional view of the second semiconductor chip 102 forming the semiconductor device 1. As shown in FIG.

The semiconductor device 1 has a first semiconductor chip 101, a second semiconductor chip 102 stacked on the first semiconductor chip 101, and a sealing resin 90 sealing the first semiconductor chip 101 and the second semiconductor chip 102. . The semiconductor device 1 has a package form of a multi-chip WL-CSP. That is, in the semiconductor device 1, the planar size of the package is substantially the same as the planar size of the first semiconductor chip 101, and the height of the package is substantially the same as the stack of the first semiconductor chip 101 and the second semiconductor chip 102. are the same.

The configuration of the first semiconductor chip 101 will be described below with reference to FIGS. 2 and 3. FIG. Circuit elements (not shown) such as transistors, resistance elements, and capacitors are formed on the surface of the semiconductor substrate 10 that constitutes the first semiconductor chip 101 . The surface of the semiconductor substrate 10 is covered with an interlayer insulating film 11 made of an insulator such as _SiO2 . On the surface of the interlayer insulating film 11, chip electrodes 12 connected to circuit elements formed on the semiconductor substrate 10 and a passivation film (protective film) 13 having openings partially exposing the surfaces of the chip electrodes 12 are provided. It is The first semiconductor chip 101 has a plurality of wiring layers that are electrically isolated from each other by an interlayer insulating film 11 . is provided in the same layer as (that is, the surface of the interlayer insulating film 11). The uppermost layer wiring 14 is covered with a passivation film 13 .

The surface of the passivation film 13 is covered with a lower insulating film 21 having a thickness of about 10 μm and made of a photosensitive organic insulating member such as polyimide or PBO (polybenzoxazole). The lower insulating film 21 is provided with an opening that partially exposes the surface of the chip electrode 12 .

A rewiring 40 is provided on the surface of the lower insulating film 21 via a first UBM (Under Bump Metallurgy) film 31 . The first UBM film 31 is composed of, for example, a laminated film including a Ti film and a Cu film. The Ti film functions as an adhesion layer for enhancing adhesion between the lower insulating film 21 and the rewiring 40 . The Cu film functions as a seed layer for forming the rewiring 40 by electroplating. The rewiring 40 is made of a conductor such as Cu, and is connected to the chip electrode 12 via the first UBM film 31 in the opening of the lower insulating film 21 . The Cu film forming the first UBM film 31 is incorporated into the Cu forming the rewiring 40 . Therefore, the structure is such that a Ti film functioning as an adhesion layer is interposed between the lower insulating film 21 and the rewiring 40 . The thickness of the rewiring 40 including the Cu film forming the first UBM film 31 is, for example, about 5 μm, and the thickness of the Ti film forming the first UBM film 31 is, for example, about 150 nm.

The surfaces of the lower insulating film 21 and the rewiring 40 are covered with an upper insulating film 22 made of a photosensitive organic insulating member such as polyimide or PBO. The thickness of the portion of the upper insulating film 22 covering the surface of the rewiring 40 is, for example, about 5 μm.

Here, the first semiconductor chip 101 has an inner peripheral region R11 and an outer peripheral region R12 surrounding the inner peripheral region R11. The upper insulating film 22 has an opening 22A that partially exposes the rewiring 40 at the formation position of the columnar electrode 35 in the outer peripheral region R12, and has an opening 22A at the formation position of the inter-chip bonding electrode 34 in the inner peripheral region R11. , has an opening 22B that partially exposes the rewiring 40 .

A plurality of inter-chip bonding electrodes 34 having a thickness of about 5 μm are provided in the inner peripheral region R11. Each of the inter-chip bonding electrodes 34 is provided at a position that includes each of the openings 22B of the upper insulating film 22 in a plan view. connected. The inter-chip bonding electrode 34 is made of a metal, such as SnAg, which does not diffuse into solder. For example, Ni can be suitably used as the material of the inter-chip bonding electrode 34 .

A plurality of columnar electrodes 35 are provided so as to surround each of the inter-chip bonding electrodes 34 in the outer peripheral region R12. Each of the columnar electrodes 35 is provided at a position including each of the openings 22A of the upper insulating film 22 in plan view, and is connected to the exposed portion of the rewiring 40 in the openings 22A via the second UBM film 32. It is As a material for the columnar electrodes 35, it is possible to suitably use Cu, which is easy to process. The columnar electrode 35 has, for example, a cylindrical shape. Incidentally, as shown in FIG. 2 , part of the columnar electrodes 35 may be connected to the inter-chip bonding electrodes 34 via rewirings 40 . The height from the surface of the upper insulating film 22 to the top of the columnar electrode 35 is, for example, 150 to 250 μm, preferably about 200 μm.

The second UBM film 32 is provided between the rewiring 40 and the columnar electrode 35 and between the rewiring 40 and the inter-chip bonding electrode 34 . Like the first UBM film 31, the second UBM film 32 is composed of a laminated film including a Ti film with a thickness of about 150 nm functioning as an adhesion layer and a Cu film with a thickness of about 300 nm functioning as a seed layer. The Cu film forming the second UBM film 32 is incorporated into the Cu forming the columnar electrode 35 . Therefore, the structure is such that a Ti film that functions as an adhesion layer is interposed between the columnar electrode 35 and the rewiring 40 . On the other hand, a laminated film containing a Ti film and a Cu film is interposed between the inter-chip junction electrode 34 and the rewiring 40 .

Next, the configuration of the second semiconductor chip 102 will be described with reference to FIG. Circuit elements (not shown) such as transistors, resistance elements, and capacitors are formed on the surface of the semiconductor substrate 50 that constitutes the second semiconductor chip 102 . The surface of the semiconductor substrate 50 is covered with an interlayer insulating film 51 made of an insulator such as _SiO2 . A chip electrode 52 connected to a circuit element formed on a semiconductor substrate 50 and a passivation film 53 having an opening partially exposing the surface of the chip electrode 52 are provided on the surface of the interlayer insulating film 51 . . The second semiconductor chip 102 has a plurality of wiring layers that are electrically isolated from each other by an interlayer insulating film 51 . is provided in the same layer as (that is, the surface of the interlayer insulating film 51). The uppermost layer wiring 54 is covered with a passivation film 53 .

The surface of the passivation film 53 is covered with a lower insulating film 61 having a thickness of about 10 μm and made of a photosensitive organic insulating member such as polyimide or PBO. The lower insulating film 61 is provided with an opening that partially exposes the surface of the chip electrode 52 .

A rewiring 80 is provided on the surface of the lower insulating film 61 with the third UBM film 71 interposed therebetween. The third UBM film 71 is composed of, for example, a laminated film including a Ti film and a Cu film. The Ti film functions as an adhesion layer for enhancing adhesion between the lower insulating film 61 and the rewiring 80 . The Cu film functions as a seed layer for forming the rewiring 80 by electroplating. The rewiring 80 is made of a conductor such as Cu, and is connected to the chip electrode 52 via the third UBM film 71 in the opening of the lower insulating film 61 . The Cu film forming the third UBM film 71 is incorporated into the Cu forming the rewiring 80 . Therefore, the structure is such that a Ti film functioning as an adhesion layer is interposed between the lower insulating film 61 and the rewiring 80 . The thickness of the rewiring 80 including the Cu film forming the third UBM film 71 is, for example, about 5 μm, and the thickness of the Ti film forming the third UBM film 31 is, for example, about 150 nm.

The surfaces of the lower insulating film 61 and the rewiring 80 are covered with an upper insulating film 62 made of a photosensitive organic insulating member such as polyimide or PBO. The thickness of the portion of the upper insulating film 62 covering the surface of the rewiring 80 is, for example, about 5 μm. The upper insulating film 62 has an opening 62A that partially exposes the rewiring 80 at the position where the inter-chip bonding electrode 74 is to be formed.

The second semiconductor chip 102 has a plurality of inter-chip bonding electrodes 74 with a thickness of approximately 5 μm. Each of the inter-chip joint electrodes 74 corresponds to each of the inter-chip joint electrodes 34 of the first semiconductor chip 101 . Each of the inter-chip bonding electrodes 74 is provided at a position that encloses each of the openings 62A of the upper insulating film 62 in plan view, and is connected to the portion of the rewiring 80 exposed in the openings 62A via the fourth UBM film 72. connected. The inter-chip bonding electrode 74 is made of a metal such as SnAg that does not diffuse into solder. For example, Ni can be suitably used as the material of the inter-chip bonding electrode 74 .

A bonding member 92 made of, for example, SnAg-based solder is provided on the surface of the inter-chip bonding electrode 74 . The bonding member 92 preferably contains Sn, Ag and Cu, and preferably has a ball-like shape with a diameter of 65 to 85 μm and a height of 60 to 80 μm.

In the second semiconductor chip 102 according to the present embodiment, the end portion 53E of the passivation film 53 is arranged closer to the inner peripheral side of the second semiconductor chip 102 than the end portion 51E of the interlayer insulating film 51 is. The end portion 61E of the lower insulating film 61 is arranged closer to the inner peripheral side of the second semiconductor chip 102 than the end portion 53E of the passivation film 53 is. The end portion 62E of the upper insulating film 62 is closer to the inner periphery of the second semiconductor chip 102 than the end portion 53E of the passivation film 53 and the outer periphery of the second semiconductor chip 102 than the end portion 61E of the lower insulating film 61. are placed in That is, the lower insulating film 61 is entirely covered with the upper insulating film 62 and is not exposed from the upper insulating film 62 . An end portion 51E of the interlayer insulating film 51, an end portion 53E of the passivation film 53, an end portion 61E of the lower insulating film 61, and an end portion 62E of the upper insulating film 62 are each parallel to the main surface of the second semiconductor chip 102. is the end in the direction of

In addition, the semiconductor substrate 50 forming the second semiconductor chip 102 has a concave portion 55 recessed toward the inner peripheral side of the second semiconductor chip on the side surface intersecting the electrode forming surface S21 on which the inter-chip bonding electrodes 74 are provided. As a result, on the side of the back surface S22 opposite to the electrode forming surface S21 of the semiconductor substrate 50, a projecting portion 56 projecting from the end portion 51E of the interlayer insulating film 51 toward the outer peripheral side of the second semiconductor chip 102 is formed. .

Here, the range over which the upper insulating film 62 of the second semiconductor chip 102 extends is defined as an inner peripheral region R21, and the region surrounding the inner peripheral region R21 of the second semiconductor chip 102 is defined as an outer peripheral region R22. Furthermore, the range in which the interlayer insulating film 51 extends in the outer peripheral region R22 is defined as a first outer peripheral region R23, and the region surrounding the first outer peripheral region R23 is defined as an outermost peripheral region R24. The inter-chip junction electrode 74 is provided in the inner peripheral region R21.

The second semiconductor chip 102 includes a semiconductor substrate 50, an interlayer insulating film 51, a lower insulating film 61 and an upper insulating film 62 in the inner peripheral region R21. The second semiconductor chip 102 does not include the upper insulating film 62 and the lower insulating film 61 but includes the semiconductor substrate 50 and the interlayer insulating film 51 in the first peripheral region R23. The second semiconductor chip 102 does not include the interlayer insulating film 51, the lower layer insulating film 61 and the upper layer insulating film 62, but includes the semiconductor substrate 50 (protruding portion 56) in the outermost peripheral region R24.

The thickness T1 in the inner peripheral region R21 of the second semiconductor chip 102 corresponds to the distance from the rear surface S22 of the semiconductor substrate 50 to the surface of the upper insulating film 62, and is, for example, approximately 200 to 250 μm. The thickness T2 in the first peripheral region R23 of the second semiconductor chip 102 corresponds to the distance from the rear surface S22 of the semiconductor substrate 50 to the surface of the interlayer insulating film 51, and is, for example, approximately 180 to 230 μm. The thickness T3 in the outermost peripheral region R24 of the second semiconductor chip 102 corresponds to the thickness of the projecting portion 56 of the semiconductor substrate 50, and is, for example, approximately 40 to 60 μm. Note that T3<T2<T1 is always established. The depth of the recess 55 of the semiconductor substrate 50 in the thickness direction of the semiconductor substrate 50 is, for example, about 120 to 190 μm.

In this manner, the thickness of the second semiconductor chip 102 increases stepwise from the outer peripheral side to the inner peripheral side. In other words, the second semiconductor chip 102 has a step structure in which the end position in the direction parallel to the main surface changes along the thickness direction of the second semiconductor chip 102 .

The width of the first peripheral region R23 of the second semiconductor chip 102 corresponds to the distance from the end surface of the recess 55 of the semiconductor substrate 50 to the end 62E of the upper insulating film 62, and is, for example, about 5 to 20 μm. The width of the outermost peripheral region R24 of the second semiconductor chip 102 corresponds to the width of the concave portion 55 of the semiconductor substrate 50, and is, for example, approximately 15 to 60 μm.

Next, the configuration of the semiconductor device 1 including the first semiconductor chip 101 and the second semiconductor chip 102 will be described with reference to FIG.

Each of the inter-chip bonding electrodes 34 of the first semiconductor chip and the inter-chip bonding electrodes 74 of the second semiconductor chip 102 are bonded via bonding members 92 . That is, the first semiconductor chip 101 and the electrode formation surface S21 of the second semiconductor chip are joined together with the electrode formation surface S11 facing each other. As a result, circuit elements (not shown) formed on the semiconductor substrate 50 of the second semiconductor chip 102 are connected to circuit elements (not shown) formed on the semiconductor substrate 10 of the first semiconductor chip 101. , to the external connection terminal 91 via the rewiring 40 and the columnar electrode 35 .

A gap 300 is formed between the electrode formation surface S11 of the first semiconductor chip 101 and the electrode formation surface S21 of the second semiconductor chip 102 . The length of the gap 300 is, for example, 50-80 μm, preferably 60-70 μm.

In this embodiment, the size of the second semiconductor chip 102 is smaller than the size of the first semiconductor chip 101, and the second semiconductor chip 102 is mounted in a region included in the inner peripheral region R11 of the first semiconductor chip 101. , surrounded by a plurality of columnar electrodes 35 . The columnar electrode 35 has one end connected to the rewiring 40 of the first semiconductor chip 101 and the other end (top) reaching the rear surface S22 of the second semiconductor chip 102 . The distance from the columnar electrode 35 to the second semiconductor chip 102 in plan view is, for example, 700 μm or less, preferably 500 to 600 μm.

The sealing resin 90 is provided on the electrode forming surface S11 side of the first semiconductor chip 101 so as to embed the second semiconductor chip 102 and the columnar electrodes 35 therein. The sealing resin 90 is provided between the first semiconductor chip 101 and the inner peripheral region R21 of the second semiconductor chip 102 (that is, the gap 300) and between the first semiconductor chip 101 and the outer peripheral region R22 of the second semiconductor chip 102. are filled between and respectively. Also, the sealing resin 90 is filled between the columnar electrodes 35 and the second semiconductor chip 102 . The side surface of the bonding member 92 is covered with the sealing resin 90 filling the gap 300 formed between the first semiconductor chip 101 and the second semiconductor chip 102 . The thickness from the rear surface S12 of the first semiconductor chip 101 to the surface of the sealing resin 90 is, for example, approximately 350 to 550 μm, preferably approximately 400 to 500 μm.

The top of the columnar electrode 35 and the back surface S22 of the second semiconductor chip 102 opposite to the electrode forming surface S21 are exposed from the surface of the sealing resin 90 . An external connection terminal 91 is provided on the top of the columnar electrode 35 exposed from the surface of the sealing resin 90 . The external connection terminals 91 are made of SnAg-based solder, for example. The semiconductor device 1 is mounted on a mounting board (not shown) via the external connection terminals 91 .

In this embodiment, the rear surface S22 of the second semiconductor chip 102 is exposed from the surface of the sealing resin 90, but the rear surface S22 of the second semiconductor chip 102 is covered with the sealing resin 90. good too. In this case, the thickness of the sealing resin 90 covering the rear surface S22 of the second semiconductor chip is, for example, about 30 μm.

A method for manufacturing the semiconductor device 1 will be described below. The manufacturing process of the semiconductor device 1 includes a preparation process of the first semiconductor chip 101, a preparation process of the second semiconductor chip 102, and a packaging process of bonding and sealing the first semiconductor chip 101 and the second semiconductor chip 102. include.

First, the preparation process of the first semiconductor chip 101 will be described with reference to FIGS. 5A to 5Q.

A semiconductor wafer on which the wafer process of the first semiconductor chip 101 has been completed is prepared (FIG. 5A). A wafer process for the first semiconductor chip 101 includes a step of forming circuit elements (not shown) such as transistors on the semiconductor substrate 10, and an interlayer insulating film 11 made of an insulator such as SiO ₂ on the surface of the semiconductor substrate 10. , forming a chip electrode 12 on the surface of the interlayer insulating film 11 , and forming a passivation film 13 on the surface of the interlayer insulating film 11 so as to partially expose the chip electrode 12 .

Next, for example, by applying a photosensitive organic insulating member such as polyimide or PBO to the surface of the first semiconductor chip 101 using a spin coating method, a lower layer covering the surfaces of the passivation film 13 and the chip electrode 12 is formed. An insulating film 21 is formed. Subsequently, the lower insulating film 21 is exposed and developed to form an opening 21A in which the surface of the chip electrode 12 is partially exposed. After that, the lower insulating film 21 is cured by heat treatment (FIG. 5B).

Next, a first UBM film 31 is formed to cover the surface of the lower insulating film 21 and the surface of the chip electrode 12 exposed in the opening 21A (FIG. 5C). The first UBM film 31 is formed, for example, by sequentially forming a Ti film and a Cu film using a sputtering method. The Ti film functions as an adhesion layer for enhancing adhesion between the lower insulating film 21 and the rewiring 40 . The Cu film functions as a seed layer for forming the rewiring 40 by electroplating.

Next, using a known photolithographic technique, a resist mask 200 having openings 200A corresponding to the pattern of the rewiring 40 is formed on the surface of the first UBM film 31 (FIG. 5D). The resist mask 200 is formed by applying a photosensitive resist onto the first UBM film 31 and exposing and developing the photosensitive resist.

Next, using electroplating, a rewiring 40 is formed on the surface of the first UBM film 31 (FIG. 5E). Specifically, the surface of the semiconductor substrate 10 is immersed in a plating solution, and current is supplied to a plating electrode (not shown) connected to the first UBM film 31 . As a result, metal is deposited on the exposed portion of the first UBM film 31 (seed layer), and the rewiring 40 is formed on the first UBM film 31 . Cu, for example, can be used as the material of the rewiring 40 . In this case, the seed layer forming the first UBM film 31 is incorporated into the Cu of the rewiring 40 . Therefore, the structure is such that a Ti film functioning as an adhesion layer is interposed between the rewiring 40 and the lower insulating film 21 .

After forming the rewiring 40, the resist mask 200 is removed using a known ashing process or an organic solvent. Thereafter, the unnecessary portion of the first UBM film 31 covered with the resist mask 200 is removed using the rewiring 40 as a mask (FIG. 5F).

Next, for example, using a spin coating method, a photosensitive organic insulating member such as polyimide or PBO is applied to the surface of the structure formed through the above treatments, thereby forming the lower insulating film 21. And an upper insulating film 22 covering the surface of the rewiring 40 is formed. Subsequently, the upper insulating film 22 is exposed and developed to form a first opening 22A and a second opening 22B in which the surface of the rewiring 40 is partially exposed. The first opening 22A is formed in a region included in the region where the columnar electrode 35 is formed in plan view. The second opening 22B is formed in a region included in the region where the inter-chip bonding electrode 34 is formed in plan view. After that, the upper insulating film 22 is cured by heat treatment (FIG. 5G).

Next, a second UBM film 32 is formed to cover the surface of the upper insulating film 22 and the surface of the rewiring 40 exposed in the first opening 22A and the second opening 22B (FIG. 5H). The second UBM film 32 is formed, for example, by sequentially forming a Ti film and a Cu film using a sputtering method. The Ti film functions as an adhesion layer for enhancing the adhesion between the upper insulating film 22 and the columnar electrodes 35 and inter-chip junction electrodes 34 . The Cu film functions as a seed layer for forming the columnar electrodes 35 and the inter-chip bonding electrodes 34 by electroplating.

Next, using a known photolithography technique, a resist mask 201 having an opening 201A at a position where the inter-chip bonding electrode 34 is to be formed is formed on the surface of the second UBM film 32 (FIG. 5I). The resist mask 201 is formed by applying a photosensitive resist onto the second UBM film 32 and exposing and developing the photosensitive resist. The opening 201A of the resist mask 201 encloses the second opening 22B of the upper insulating film 22 and exposes the second opening 22B.

Next, using electroplating, an inter-chip bonding electrode 34 is formed on the surface of the second UBM film 32 exposed in the opening 201A of the resist mask 201 (FIG. 5J). Specifically, the surface of the semiconductor substrate 10 is immersed in a plating solution, and current is supplied to a plating electrode (not shown) connected to the second UBM film 32 . As a result, metal is deposited on the exposed portion of the second UBM film 32 (seed layer), and the inter-chip bonding electrode 34 is formed on the second UBM film 32 . The inter-chip junction electrode 34 is connected to the rewiring 40 via the second UBM film 32 . As the material of the inter-chip bonding electrode 34, Ni, which does not diffuse into solder containing SnAg, can be preferably used. In this case, Ti, Cu, and Ni are stacked on the surface of the rewiring 40 exposed in the second opening 22B.

Next, the resist mask 201 is removed using a known ashing process or an organic solvent (FIG. 5K).

Next, a first layer dry film 211 is attached to the surface of the structure formed through the above processes so as to cover the surfaces of the second UBM film 32 and the inter-chip bonding electrode 34 . The dry film 211 of the first layer is a film-like resist member having photosensitivity, and is attached using, for example, an attaching machine. After that, the dry film 211 of the first layer is exposed and developed to form openings 211A at positions where the columnar electrodes 35 are to be formed. The opening 211A of the first layer dry film 211 encloses the first opening 22A of the upper insulating film 22 and exposes the opening 22A (FIG. 5L).

Next, using electroplating, columnar electrodes 35 are formed on the surface of the second UBM film 32 exposed in the openings 211A of the first layer dry film 211 (FIG. 5M). Specifically, the surface of the semiconductor substrate 10 is immersed in a plating solution, and current is supplied to a plating electrode (not shown) connected to the second UBM film 32 . As a result, the metal is deposited on the exposed portion of the second UBM film 32 (seed layer), and the lower layer portion 35 a of the columnar electrode 35 is formed on the second UBM film 32 . It is preferable to form the lower layer portion 35a so that the upper surface of the lower layer portion 35a of the columnar electrode 35 is lower than the upper surface of the dry film 211 of the first layer. As a material for the columnar electrodes 35, it is possible to suitably use Cu, which is easy to process. In this case, the Cu film that functions as a seed layer forming the second UBM film 32 is incorporated into the Cu forming the columnar electrode 35 . Therefore, the structure is such that a Ti film that functions as an adhesion layer is interposed between the columnar electrode 35 and the rewiring 40 .

Next, the dry film 212 of the second layer is attached to the surface of the dry film 211 of the first layer. The dry film 212 of the second layer is a film-like resist member having photosensitivity, like the dry film 211 of the first layer, and is attached using, for example, an attaching machine. After that, the dry film 212 of the second layer is exposed and developed to form openings 212</b>A at positions where the columnar electrodes 35 are to be formed. That is, the openings 212A of the second-layer dry film 212 communicate with the openings 211A of the first-layer dry film 212, and the lower layer portions of the columnar electrodes 35 are connected to the openings 212A of the second-layer dry film 212. 35a is exposed (Fig. 5N).

Next, using electroplating, the upper layer portion 35b of the columnar electrode 35 is formed on the surface of the lower layer portion 35a of the columnar electrode 35 exposed in the opening 212A of the second layer dry film 212 (FIG. 5O). . Specifically, the surface of the semiconductor substrate 10 is immersed in a plating solution, and current is supplied to a plating electrode (not shown) connected to the second UBM film 32 . Thereby, the metal is deposited on the surface of the lower layer portion 35a of the columnar electrode 35, and the upper layer portion 35b of the columnar electrode 35 is formed on the surface of the lower layer portion 35a of the columnar electrode 35. FIG. It is preferable to form the upper layer portion 35b so that the upper surface of the upper portion 35b of the columnar electrode 35 is higher than the upper surface of the dry film 212 of the second layer.

After forming the columnar electrodes 35, the first layer dry film 211 and the second layer dry film 212 are removed using an organic peeling solution or the like (FIG. 5P).

Next, unnecessary portions of the second UBM film 32 covered with the first dry film 211 are removed using the columnar electrodes 35 and the inter-chip bonding electrodes 34 as masks (FIG. 5Q). As a result, the plating electrodes (not shown) used in the plating process for forming the inter-chip bonding electrodes 34 and the columnar electrodes 35 are also removed.

Next, preparation steps for the second semiconductor chip 102 will be described with reference to FIGS. 6A to 6Q.

A semiconductor wafer on which the wafer process of the second semiconductor chip 102 has been completed is prepared (FIG. 6A). The wafer process of the second semiconductor chip 102 includes a step of forming circuit elements (not shown) such as transistors on the semiconductor substrate 50, and an interlayer insulating film 51 made of an insulator such as SiO ₂ on the surface of the semiconductor substrate 50. , forming a chip electrode 52 on the surface of the interlayer insulating film 51 , and forming a passivation film 53 on the surface of the interlayer insulating film 51 so as to partially expose the chip electrode 52 . A semiconductor wafer including the second semiconductor chip 102 has an element formation region in which a circuit element is formed, and a scribe line 110 that defines the element formation region. An interlayer insulating film 51 covers the entire surface of the semiconductor substrate 50, and a passivation film 53 covers an element formation region. The passivation film 53 has openings 53A that expose the scribe lines 110 .

Next, for example, by applying a photosensitive organic insulating member such as polyimide or PBO to the surface of the second semiconductor chip 102 by spin coating, the passivation film 53, the chip electrode 52 and the scribe line 110 are formed. A lower insulating film 61 is formed to cover the surface. Subsequently, the lower insulating film 61 is exposed and developed to form an opening 61A for partially exposing the surface of the chip electrode 52 and an opening 61B for exposing the scribe line 110 in the lower insulating film 61. The end portion 61E of the lower insulating film 61 is arranged closer to the inner peripheral side of the second semiconductor chip 102 than the end portion 53E of the passivation film 53 is. After that, the lower insulating film 61 is cured by heat treatment (FIG. 6B).

Next, a third UBM film 71 is formed to cover the surface of the lower insulating film 61 and the surface of the chip electrode 52 exposed in the opening 61A (FIG. 6C). The third UBM film 71 is formed by sequentially forming a Ti film and a Cu film using, for example, a sputtering method. The Ti film functions as an adhesion layer for enhancing adhesion between the lower insulating film 61 and the rewiring 80 . The Cu film functions as a seed layer for forming the rewiring 80 by electroplating.

Next, using a known photolithographic technique, a resist mask 400 having openings 400A corresponding to the pattern of the rewiring 80 is formed on the surface of the third UBM film 71 (FIG. 6D). The resist mask 400 is formed by applying a photosensitive resist onto the third UBM film 71 and exposing and developing the photosensitive resist.

Next, using electroplating, a rewiring 80 is formed on the surface of the third UBM film 71 (FIG. 6E). Specifically, the surface of the semiconductor substrate 50 is immersed in a plating solution, and current is supplied to a plating electrode (not shown) connected to the third UBM film 71 . As a result, metal is deposited on the exposed portion of the third UBM film 71 (seed layer), and the rewiring 80 is formed on the third UBM film 71 . For example, Cu can be used as the material of the rewiring 80 . In this case, the seed layer forming the third UBM film 71 is incorporated into the Cu of the rewiring 80 . Therefore, a structure is obtained in which a Ti film that functions as an adhesion layer is interposed between the rewiring 80 and the lower insulating film 61 .

After forming the rewiring 80, the resist mask 400 is removed using a known ashing process or an organic solvent. Thereafter, unnecessary portions of the third UBM film 71 covered with the resist mask 400 are removed using the rewiring 80 as a mask (FIG. 6F).

Next, for example, using a spin coating method, a photosensitive organic insulating member such as polyimide or PBO is applied to the surface of the structure formed through the above processes, thereby forming the lower insulating film 61. , an upper insulating film 62 covering the rewiring 80 and the scribe line 110 is formed. Subsequently, the upper insulating film 62 is exposed and developed to form an opening 62A partially exposing the surface of the rewiring 80 and an opening 62B exposing the scribe line 110 in the upper insulating film 62. The opening 62A is formed in a region included in the region where the inter-chip bonding electrode 74 is formed in plan view. The end portion 62E of the upper insulating film 62 is arranged closer to the inner periphery of the second semiconductor chip 102 than the end portion 53E of the passivation film 53, and is closer to the outer periphery of the second semiconductor chip 102 than the end portion 61E of the lower insulating film 61. placed in After that, the upper insulating film 62 is cured by heat treatment (FIG. 6G).

Next, a fourth UBM film 72 is formed to cover the surface of the upper insulating film 62 and the surface of the rewiring 80 exposed in the opening 62A (FIG. 6H). The fourth UBM film 72 is formed by sequentially forming a Ti film and a Cu film using, for example, a sputtering method. The Ti film functions as an adhesion layer for enhancing adhesion between the upper insulating film 62 and the inter-chip junction electrode 74 . The Cu film functions as a seed layer for forming the inter-chip bonding electrodes 74 by electroplating.

Next, using a known photolithography technique, a resist mask 401 having an opening 401A at the position where the inter-chip bonding electrode 74 is to be formed is formed on the surface of the fourth UBM film 72 (FIG. 6I). The resist mask 401 is formed by applying a photosensitive resist onto the fourth UBM film 72 and exposing and developing the photosensitive resist. The opening 401A of the resist mask 401 encloses the opening 62A of the upper insulating film 62 and exposes the opening 62A.

Next, using an electroplating method, an inter-chip bonding electrode 74 is formed on the surface of the fourth UBM film 72 exposed in the opening 401A of the resist mask 401 (FIG. 6J). Specifically, the surface of the semiconductor substrate 50 is immersed in a plating solution, and current is supplied to a plating electrode (not shown) connected to the fourth UBM film 72 . As a result, metal is deposited on the exposed portion of the fourth UBM film 72 (seed layer), and the inter-chip bonding electrode 74 is formed on the fourth UBM film 72 . The inter-chip junction electrode 74 is connected to the rewiring 80 via the fourth UBM film 72 . As a material for the inter-chip bonding electrode 74, Ni, which does not diffuse into solder containing SnAg, can be preferably used. In this case, Ti, Cu, and Ni are layered on the surface of the rewiring 80 exposed in the opening 62A.

Next, using electrolytic plating, a bonding member 92 made of SnAg-based solder is formed on the inter-chip bonding electrode 74 (FIG. 6K). Specifically, with the resist mask 401 left, the surface of the semiconductor substrate 50 is immersed in a plating solution, and current is supplied to a plating electrode (not shown) connected to the fourth UBM film 72 . As a result, metal is deposited on the surfaces of the inter-chip bonding electrodes 74 to form the bonding members 92 on the inter-chip bonding electrodes 74 .

Next, the resist mask 401 is removed using a known ashing process or an organic solvent (FIG. 6L). Next, using the inter-chip junction electrode 74 as a mask, an unnecessary portion of the fourth UBM film 72 covering the surface of the upper insulating film 62 and the surface of the scribe line 110 is removed (FIG. 6M).

Next, flux is applied to the electrode forming surface of the second semiconductor chip 102, and then the second semiconductor chip 102 is subjected to a reflow process to form the bonding member 92 into a ball shape (FIGS. 6N and 6O).

Next, grooves 120 are formed in the semiconductor substrate 50 along the scribe lines 110 of the semiconductor wafer including the semiconductor substrate 50 (FIG. 6P). The trench 120 is formed with a depth that does not penetrate the semiconductor substrate 50 . For example, the grooves 120 can be formed by scanning a dicing blade (not shown) having a width corresponding to the width of the grooves 120 along the scribe lines 110 . Before or after forming the grooves 120, the back surface S22 of the semiconductor substrate 50 may be ground so that the semiconductor substrate 50 has a desired thickness. When the rear surface S22 of the semiconductor substrate 50 is ground after the formation of the groove 120, the rear surface S22 of the semiconductor substrate 50, which is receded by grinding, does not reach the bottom of the groove 120. FIG.

Next, a dicing blade (not shown) having a width smaller than that of the dicing blade used to form the grooves 120 is inserted into the grooves 120 to scribe the semiconductor wafer including the semiconductor substrate 50 along the scribe lines 110. cut along. As a result, recesses 55 and protrusions 56 are formed on the side surface of the semiconductor substrate 50, and the second semiconductor chips 102 are singulated (FIG. 6Q).

Next, the packaging process will be described with reference to FIGS. 7A-7E.

First, a first semiconductor chip 101 is prepared (FIG. 7A). Next, the first semiconductor chip 101 and the second semiconductor chip 102 are bonded together (FIG. 7B). Specifically, the reflow process is performed while the bonding members 92 formed on the inter-chip bonding electrodes 74 of the second semiconductor chip 102 are in contact with the inter-chip bonding electrodes 34 of the first semiconductor chip 101 . Thereby, each of the inter-chip bonding electrodes 34 of the first semiconductor chip 101 and the inter-chip bonding electrodes 74 of the second semiconductor chip 102 are electrically and mechanically bonded via the bonding member 92 . A gap 300 is formed between the first semiconductor chip 101 and the second semiconductor chip 102 according to the thicknesses of the inter-chip bonding electrodes 34 and 74 and the bonding member 92 .

Next, a sealing resin 90 is formed on the side of the electrode forming surface S11 of the first semiconductor chip 101 so as to embed the second semiconductor chip 102 and the columnar electrodes 35 therein (FIG. 7C). Formation of the sealing resin 90 can be performed by, for example, compression molding or screen printing. The sealing resin 90 is provided between the first semiconductor chip 101 and the inner peripheral region R21 of the second semiconductor chip 102 (that is, the gap 300) and between the first semiconductor chip 101 and the outer peripheral region R22 of the second semiconductor chip 102. are filled respectively between Also, the sealing resin 90 is filled between the columnar electrodes 35 and the second semiconductor chip 102 . The side surface of the bonding member 92 is covered with the sealing resin 90 filling the gap 300 formed between the first semiconductor chip 101 and the second semiconductor chip 102 . The portion of the sealing resin 90 that fills the gap 300 and the portion of the sealing resin 90 that fills between the second semiconductor chip 102 and the columnar electrode 35 contain fillers of the same size.

Next, a portion of the sealing resin 90 covering the top of the columnar electrode 35 and the back surface S22 of the second semiconductor chip 102 is removed by grinding, thereby exposing the top of the columnar electrode 35 and the back surface S22 of the second semiconductor chip 102. (Fig. 7D). A grinder can be used for grinding the sealing resin 90 . In the case of a package form in which the rear surface S22 of the second semiconductor chip 102 is covered with the sealing resin 90, the height of the top of the columnar electrode 35 is set higher than the height of the rear surface S22 of the second semiconductor chip 102. , and only the tops of the columnar electrodes 35 are exposed by grinding the sealing resin 90 .

Next, external connection terminals 91 are formed on the tops of the columnar electrodes 35 exposed from the sealing resin 90 (FIG. 7E). The external connection terminal 91 is formed, for example, by mounting a solder ball containing, for example, SnAg on the top of the columnar electrode 35 and then performing a reflow process. Further, it is also possible to form the external connection terminals 91 by forming a conductor paste containing, for example, SnAg on the tops of the columnar electrodes 35 by screen printing and then performing a reflow treatment.

According to the semiconductor device 1 and the manufacturing method thereof according to the embodiment of the present invention, the second semiconductor chip 102 has an inner peripheral region R21 with a relatively thick thickness and an outer peripheral region R22 with a relatively thin thickness. . That is, the thickness of the second semiconductor chip 102 is gradually reduced from the inner peripheral side to the outer peripheral side, and has a stepped structure on its side surface. In other words, the gap formed between the first semiconductor chip 101 and the second semiconductor chip 102 widens stepwise from the inner peripheral side to the outer peripheral side. As a result, the width of the path through which the sealing resin 90 flows toward the gap 300 formed between the first semiconductor chip 101 and the second semiconductor chip 102 can be widened. Inflow of the resin 90 can be promoted. Furthermore, the flow of the sealing resin 90 along the step structure formed on the side surface of the second semiconductor chip 102 can further promote the flow of the sealing resin 90 into the gap 300 . As a result, filling of the gap 300 with the sealing resin 90 can be accelerated, and the risk of the gap 300 not being filled with the sealing resin 90 can be suppressed. Therefore, it is possible to evenly cover the side surface of the bonding member 92 used for bonding the first semiconductor chip 101 and the second semiconductor chip 102 with the sealing resin 90 , so that the first semiconductor chip 101 and the second semiconductor chip 102 are bonded together. It becomes possible to improve the reliability in joining.

Here, when a semiconductor device having solder terminals such as solder balls is mounted on a printed circuit board, the solder terminals are fixed by filling an underfill material in a gap formed between the semiconductor device and the printed circuit board. is commonly performed. This ensures the reliability of the bonding between the semiconductor device and the printed circuit board.

On the other hand, in the semiconductor device 1 according to this embodiment, consider the case where the gap 300 formed between the first semiconductor chip 101 and the second semiconductor chip 102 is filled with the underfill material. In the semiconductor device 1 , the circumference of the second semiconductor chip 102 is surrounded by the columnar electrodes 35 . Since the distance between the second semiconductor chip 102 and the columnar electrode 35 is extremely narrow, the nozzle of the dispenser for supplying the underfill material interferes with the columnar electrode 35, causing the tip of the nozzle to be separated from the first semiconductor chip 101 and the second columnar electrode. It is difficult to arrange it near the junction with the semiconductor chip 102 . That is, according to the semiconductor device 1 according to the present embodiment, it is considered difficult to fill the gap 300 formed between the first semiconductor chip 101 and the second semiconductor chip 102 with the underfill material. .

However, according to the semiconductor device 1 according to the present embodiment, as described above, the filling of the sealing resin 90 into the gap 300 formed between the first semiconductor chip 101 and the second semiconductor chip 102 is facilitated. Therefore, the bonding member 92 can be fixed without using an underfill material, and the reliability of bonding between the first semiconductor chip 101 and the second semiconductor chip 102 can be improved.

In addition, the sealing resin 90 functions as a sealing member that seals the first semiconductor chip 101 and the second semiconductor chip 102, and also the gap 300 formed between the first semiconductor chip 101 and the second semiconductor chip 102. It also functions as a reinforcing member that reinforces the mechanical strength of the joint member 92 by being filled in and covering the side surface of the joint member 92 . Therefore, the number of steps can be reduced compared to the case of separately filling the gap 300 formed between the first semiconductor chip 101 and the second semiconductor chip 102 with a reinforcing member such as an underfill material different from the sealing resin 90 . can be reduced. That is, according to the semiconductor device 1 according to this embodiment, it is possible to manufacture a highly reliable multi-chip WL-CSP at low cost.

[Second embodiment]
FIG. 8 is a cross-sectional view showing the configuration of a semiconductor device 1A according to the second embodiment of the invention. FIG. 9 is a cross-sectional view showing the configuration of a second semiconductor chip 102A according to the second embodiment of the present invention, which constitutes the semiconductor device 1A.

The second semiconductor chip 102A according to the second embodiment differs from the second semiconductor chip 102 according to the first embodiment in the position of the end portion 62E of the upper insulating film 62 . That is, in the second semiconductor chip 102A, the end portion 53E of the passivation film 53 is arranged closer to the inner peripheral side of the second semiconductor chip 102A than the end portion 51E of the interlayer insulating film 51 is. The end portion 61E of the lower insulating film 61 is arranged closer to the inner peripheral side of the second semiconductor chip 102A than the end portion 53E of the passivation film 53 is. The end portion 62E of the upper insulating film 62 is arranged closer to the inner circumference of the second semiconductor chip 102A than the end portion 61E of the lower insulating film 61 is. That is, in the second semiconductor chip 102A, the end portion 61E of the lower insulating film 61 is exposed from the upper insulating film 62. As shown in FIG.

Here, the range over which the upper insulating film 62 of the second semiconductor chip 102A extends is defined as an inner peripheral region R21, and the region surrounding the inner peripheral region R21 of the second semiconductor chip 102A is defined as an outer peripheral region R22. Further, the range in which the interlayer insulating film 51 extends and the lower layer insulating film 61 does not extend in the outer peripheral region R22 is defined as a first outer peripheral region R23, and the range in which the lower insulating film 61 extends in the outer peripheral region R22. is defined as a second peripheral region R25, and the region surrounding the first peripheral region R23 is defined as an outermost peripheral region R24. The inter-chip junction electrode 74 is provided in the inner peripheral region R21.

The second semiconductor chip 102A includes a semiconductor substrate 50, an interlayer insulating film 51, a lower insulating film 61 and an upper insulating film 62 in the inner peripheral region R21. The second semiconductor chip 102A does not include the upper insulating film 62 but includes the lower insulating film 61, the semiconductor substrate 50, and the interlayer insulating film 51 in the second peripheral region R25. The second semiconductor chip 102A does not include the upper insulating film 62 and the lower insulating film 61, but includes the semiconductor substrate 50 and the interlayer insulating film 51 in the first peripheral region R23. The second semiconductor chip 102A does not include the interlayer insulating film 51, the lower layer insulating film 61 and the upper layer insulating film 62, but includes the semiconductor substrate 50 (protruding portion 56) in the outermost peripheral region R24.

The thickness T1 in the inner peripheral region R21 of the second semiconductor chip 102A corresponds to the distance from the rear surface S22 of the semiconductor substrate 50 to the surface of the upper insulating film 62, and is, for example, approximately 200 to 250 μm. The thickness T2 in the first peripheral region R23 of the second semiconductor chip 102A corresponds to the distance from the rear surface S22 of the semiconductor substrate 50 to the surface of the interlayer insulating film 51, and is, for example, approximately 180 to 230 μm. The thickness T3 in the outermost peripheral region R24 of the second semiconductor chip 102A corresponds to the thickness of the projecting portion 56 of the semiconductor substrate 50, and is, for example, approximately 40 to 60 μm. The thickness T4 in the second peripheral region R25 of the second semiconductor chip 102A corresponds to the distance from the rear surface S22 of the semiconductor substrate 50 to the surface of the lower insulating film 61, and is, for example, approximately 190 to 240 μm. Note that T3<T2<T4<T1 is always established. The depth of the recess 55 of the semiconductor substrate 50 in the thickness direction of the semiconductor substrate 50 is, for example, about 120 to 190 μm.

Thus, the thickness of the second semiconductor chip 102A increases stepwise from the inner peripheral side to the outer peripheral side. In other words, the second semiconductor chip 102A has a stepped structure in which the end position in the direction parallel to the main surface thereof changes along the thickness direction of the second semiconductor chip 102A. The gap formed between the second semiconductor chip 102A widens stepwise from the inner peripheral side to the outer peripheral side.

The width of the first peripheral region R23 of the second semiconductor chip 102A corresponds to the distance from the end face of the recess 55 of the semiconductor substrate 50 to the end 61E of the lower insulating film 61, and is, for example, about 5 to 20 μm. The width of the second peripheral region R25 of the second semiconductor chip 102A corresponds to the distance from the edge 61E of the lower insulating film 61 to the edge 62E of the upper insulating film 62, and is about 5 to 10 μm, for example.

According to the semiconductor device 1A according to the second embodiment, similarly to the semiconductor device 1 according to the first embodiment, the gap 300 formed between the first semiconductor chip 101 and the second semiconductor chip 102A is sealed. Filling of the stopper resin 90 can be accelerated. As a result, it becomes possible to evenly cover the side surface of the bonding member 92 used for bonding the first semiconductor chip 101 and the second semiconductor chip 102A with the sealing resin 90, and the first semiconductor chip 101 and the second semiconductor chip 102A are It becomes possible to improve the reliability in the joining of the.

Here, in general, the number of semiconductor chips obtained from one semiconductor wafer can be increased by reducing the element formation regions and the scribe lines that define the element formation regions. In particular, by reducing the width of scribe lines where circuit elements are not formed, the number of semiconductor chips obtained from one semiconductor wafer can be increased without reducing the circuit elements. However, when the width of the scribe line is reduced, it becomes difficult to secure a region for covering the lower insulating film with the upper insulating film.

Therefore, by arranging the end portion of the upper insulating film on the surface of the lower insulating film, it becomes possible to cover the rewiring layer with the upper insulating film even in a semiconductor chip in which the width of the scribe line is reduced. It is possible to solve the problem of deterioration of long-term reliability due to corrosion caused by exposing the rewiring layer to the atmosphere. In addition, since the top layer wiring at the edge of the chip is protected by a passivation film, it is not possible to cover the passivation film on the top layer wiring with a lower layer insulation film in a general WL-CSP having an upper layer insulation film. No need.

However, in the semiconductor chip constituting the multi-chip WL-CSP, since the upper insulating film is sealed with a sealing resin, the area exposed from the lower insulating film covered with the upper insulating film, especially the chip electrode There is a possibility that the uppermost layer wiring covered only by the passivation film, which is arranged on the outer peripheral side, may cause problems such as disconnection due to filler attack by the sealing resin.

In the second semiconductor chip 102A according to the present embodiment, the uppermost layer wiring 54 provided in the uppermost layer among the plurality of wiring layers is provided closer to the outer circumference of the second semiconductor chip 102A than the chip electrodes 52 are. The uppermost layer wiring 54 is covered with a passivation film 53 and a lower layer insulating film 61 . Since the uppermost layer wiring 54 is covered with the passivation film 53 and the lower insulating film 61 in this way, problems such as disconnection due to filler attack can be prevented compared to the case where the uppermost layer wiring 54 is covered only with the passivation film 53. It is possible to control the risks that arise. This makes it possible to ensure long-term reliability of the multi-chip WL-CSP.

Note that the inter-chip bonding electrode 34 is an example of a first electrode in the present invention. The inter-chip junction electrode 74 is an example of the second electrode in the present invention. The interlayer insulating film 51 is an example of the first insulating film in the present invention. The lower insulating film 61 is an example of the second insulating film in the present invention. The upper insulating film 62 is an example of a third insulating film in the present invention.

1, 1A semiconductor devices 10, 50 semiconductor substrates 11, 51 interlayer insulating films 12, 52 chip electrodes 13, 53 passivation films 14, 54 uppermost wirings 21, 61 lower insulating films 22, 62 upper insulating films 34, 74 junctions between chips Electrode 35 Columnar electrodes 40, 80 Rewiring 55 Recess 56 Projection 90 Sealing resin 91 External connection terminal 92 Joining member 101 First semiconductor chip 102, 102A Second semiconductor chip 110 Scribe line 120 Groove 300 Gap R11 Inner peripheral region R12 Outer periphery Region R21 Inner peripheral region R22 Outer peripheral region R23 First peripheral region R24 Outermost peripheral region R25 Second peripheral region

Claims (10)

a first semiconductor chip having a plurality of first electrodes on its surface;
an inner peripheral region having, on the surface thereof, a plurality of second electrodes arranged spaced apart from the surface of the first semiconductor chip and connected to each of the first electrodes; a second semiconductor chip having a peripheral region having a thickness smaller than the thickness of the region;
a sealing resin filled between the surface of the first semiconductor chip and the inner peripheral region and between the surface of the first semiconductor chip and the outer peripheral region;
with
The second semiconductor chip includes, in the inner peripheral region, a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a second insulating film formed on the first insulating film, and the second insulating film. A semiconductor device including a third insulating film formed thereon and not including the third insulating film in the outer peripheral region and including the semiconductor substrate and the first insulating film. a joining member that joins each of the first electrodes and each of the second electrodes;
2. The semiconductor device according to claim 1, wherein a side surface of said joining member is covered with said sealing resin. The first semiconductor chip has a plurality of columnar electrodes surrounding the second semiconductor chip in plan view,
3. The semiconductor device according to claim 1, wherein said sealing resin is filled between each of said columnar electrodes and said second semiconductor chip. The outer peripheral region includes a first outer peripheral region having a thickness thinner than the thickness of the inner peripheral region, an outermost peripheral region surrounding the first outer peripheral region and thinner than the thickness of the first outer peripheral region,
4. The semiconductor device according to claim 1, comprising: The outer peripheral region, between the inner peripheral region and the first outer peripheral region, has a thickness thinner than the thickness of the inner peripheral region and a thickness greater than the thickness of the first outer peripheral region. 5. The semiconductor device according to claim 4, further comprising two peripheral regions. The second semiconductor chip has a plurality of wiring layers, and among the plurality of wiring layers arranged on the first insulating film in the second peripheral region, the uppermost layer wiring arranged in the uppermost layer is the first wiring layer. It is covered with said 2nd insulating film formed on an insulating film, and the surface of said 2nd insulating film of said 2nd peripheral area|region is exposed from said 3rd insulating film formed on said 2nd insulating film. 6. The semiconductor device according to 5. 7. The semiconductor device according to claim 5, wherein the second semiconductor chip has a recess recessed toward the inner periphery of the second semiconductor chip on a side surface that intersects the surface on which the second electrode is provided. 8. The semiconductor according to any one of claims 4 to 7, wherein the thickness of the second semiconductor chip in the inner peripheral region is three times or more the thickness of the second semiconductor chip in the outermost peripheral region. Device. A portion of the sealing resin filled between the first semiconductor chip and the second semiconductor chip, and a portion filled between each of the columnar electrodes and the second semiconductor chip are separated from each other. 4. The semiconductor device according to claim 3, comprising fillers of the same size. 10. The semiconductor device according to claim 1, wherein the thickness of the second semiconductor chip is gradually reduced from the inner peripheral side to the outer peripheral side.

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