JP7267719B2 - Photoelectric conversion device, moving object, signal processing device - Google Patents

Description

The present invention relates to a photoelectric conversion device, a moving object, and a signal processing device.

2. Description of the Related Art An imaging device is known that performs phase difference detection using signals based on charges generated by a plurality of photoelectric conversion units. Japanese Unexamined Patent Application Publication No. 2002-200000 describes an imaging device that includes a plurality of pixels each including a plurality of photoelectric conversion units. Each pixel outputs a signal based on charges generated by the plurality of photoelectric conversion units. Furthermore, Patent Document 1 discloses a configuration in which some of the plurality of pixels output signals based on charges generated by some of the photoelectric conversion units of each pixel.

JP 2013-211833 A

However, in Japanese Patent Laid-Open No. 2004-100000, in the case of further including a pixel including a light-shielded photoelectric conversion unit (hereinafter referred to as a “light-shielded pixel”), in what order the signals read from the plurality of pixels are subjected to arithmetic processing. No consideration has been given as to whether to input to the arithmetic processing circuit.

The present invention provides a suitable signal input order when signals read from a plurality of pixels including light-shielded pixels are input to an arithmetic processing circuit.

A photoelectric conversion device according to one embodiment of the present invention includes a pixel array in which a plurality of pixels each including a plurality of photoelectric conversion units are arranged two-dimensionally, and a memory to which a signal output from the pixel array is input. and an arithmetic processing circuit that receives a signal output from the memory and performs arithmetic processing using the signal, wherein the plurality of pixels are first pixels in which the plurality of photoelectric conversion units are shielded from light. , a second pixel and a third pixel in which light enters the plurality of photoelectric conversion units, and the pixel array includes a first signal based on charges generated by the plurality of photoelectric conversion units included in the first pixel. , a second signal based on charges generated by a plurality of photoelectric conversion units included in the second pixel, and a signal based on charges generated by one photoelectric conversion unit included in the third pixel and the third pixel a third signal including at least one of signals based on charges generated by the other photoelectric conversion unit included in the second photoelectric conversion unit, and outputting the first signal, the second signal, and the third signal in this order, and holding the first signal, the second signal, and the third signal in the memory and the first signal, the second signal, and the third signal output from the memory are input to the arithmetic processing circuit in the order of the first signal, the third signal, and the second signal , The arithmetic processing is performed during at least part of a period including a first period during which the third signal is input to the arithmetic processing circuit and a second period during which the second signal is input to the arithmetic processing circuit.

A photoelectric conversion device according to an aspect of the present invention includes a plurality of shielded photoelectric conversion units, a first pixel for outputting a black reference signal from the plurality of photoelectric conversion units;
a second pixel including a plurality of photoelectric conversion units for generating an image signal;
a pixel array including a plurality of photoelectric conversion units and a third pixel for generating an image signal and a focus detection signal;
a memory to which a signal output from the pixel array is input;
an arithmetic processing circuit that receives a signal output from the memory and performs arithmetic processing using the signal,
The pixel array includes a first signal that is a black reference signal output by the first pixel, a second signal that is an image signal output by the second pixel, and an image signal that is output by the third pixel. and a third signal including a signal for focus detection are output in this order,
the first signal, the second signal, and the third signal are held in the memory;
the first signal, the second signal, and the third signal output from the memory are input to the arithmetic processing circuit in the order of the first signal, the third signal, and the second signal;
The arithmetic processing is performed during at least part of a period including a first period during which the third signal is input to the arithmetic processing circuit and a second period during which the second signal is input to the arithmetic processing circuit.

A signal processing device according to one aspect of the present invention is a signal processing device to which a signal is input from a pixel array having a plurality of pixels,
The signal processing device includes a memory to which the signal output from the pixel array is input, and an arithmetic processing circuit to which the signal output from the memory is input and performs arithmetic processing using the signal,
The plurality of pixels included in the pixel array includes a first pixel in which a plurality of photoelectric conversion units are shielded from light, and a second pixel and a third pixel in which light enters the plurality of photoelectric conversion units,
From the pixel array, a first signal based on charges generated by a plurality of photoelectric conversion units included in the first pixel and a second signal based on charges generated by a plurality of photoelectric conversion units included in the second pixel , and at least one of a signal based on charges generated by one photoelectric conversion unit included in the third pixel and a signal based on charges generated by the other photoelectric conversion unit included in the third pixel. signals are output in this order,
the memory holds the first signal, the second signal, and the third signal;
the first signal, the second signal, and the third signal output from the memory are input to the arithmetic processing circuit in the order of the first signal, the third signal, and the second signal;
The arithmetic processing is performed during at least part of a period including a first period during which the third signal is input to the arithmetic processing circuit and a second period during which the second signal is input to the arithmetic processing circuit.

The input order of signals of a plurality of pixels including light-shielded pixels to the arithmetic processing circuit can be made suitable.

1 is a block diagram showing the configuration of a photoelectric conversion device according to a first embodiment; FIG. 1 is a diagram showing the configuration and circuitry of a photoelectric conversion device according to a first embodiment; FIG. 1 is a block diagram of a photoelectric conversion element and a signal processing circuit according to a first embodiment; FIG. (a) is a distribution diagram of each pixel, and (b) is a diagram showing addresses of digital signals stored in a memory. 4 is a timing chart showing the operation of the photoelectric conversion device according to the first embodiment; It is a figure which shows the mounting form of the photoelectric conversion apparatus which concerns on 1st Embodiment. It is a figure which shows the internal structure of the photoelectric conversion apparatus which concerns on 2nd Embodiment. FIG. 10 is a diagram showing outputs from a memory of the photoelectric conversion device according to the second embodiment; FIG. 9 is a timing chart showing the operation of the photoelectric conversion device according to the second embodiment; It is a figure which shows the internal structure of the photoelectric conversion apparatus which concerns on 3rd Embodiment. FIG. 10 is a diagram showing outputs from a memory of a photoelectric conversion device according to the third embodiment; FIG. 9 is a timing chart showing the operation of the photoelectric conversion device according to the third embodiment; FIG. 11 is a schematic diagram of a moving body according to a fourth embodiment;

A mode for carrying out the present invention will be described below with reference to the drawings. However, the configurations shown in the following embodiments are merely examples, and the present invention is not limited to the illustrated configurations. Note that the sizes and positional relationships of members shown in each drawing may be exaggerated for clarity of explanation.

Moreover, in the embodiments shown below, the same reference numerals are given to the same configurations, and the explanation may be omitted.

<First embodiment>
FIG. 1 is a diagram showing the configuration of a photoelectric conversion device according to the first embodiment. FIG. 1 shows an imaging device as an example of the photoelectric conversion device. Examples of imaging devices include digital still cameras, digital camcorders, surveillance cameras, copiers, facsimiles, mobile phones, vehicle-mounted cameras, and observation satellites. Note that the present invention is not limited to imaging devices, and photoelectric conversion devices according to the following embodiments can obtain effects even in devices that do not perform imaging. Devices that do not perform imaging include, for example, a distance measuring sensor and a photometric sensor. A ranging sensor is typically a sensor used to generate distance information to a subject, and includes, for example, a TOF (Time Of Flight) sensor. A photometric sensor is a sensor typically used to detect the brightness of a subject.

In FIG. 1, the lens 100 is arranged on the distal end side of the imaging optical system 120 . The aperture 101 adjusts the aperture diameter to adjust the amount of light during shooting. The lenses 102 and 103 are driven by a focus actuator 117, which will be described later, and move back and forth along the optical axis to adjust the focus of the imaging optical system 120. FIG.

A focal plane shutter 104 adjusts the exposure time during still image shooting. The optical low-pass filter 105 is used to reduce false colors and moire in the captured image. The photoelectric conversion element 106 photoelectrically converts the optical image of the subject formed by the imaging optical system 120 into an electric signal. An electrical signal output from the photoelectric conversion element 106 is output to the signal processing device 121 . The signal processing device 121 includes, for example, a front end 107 and a DSP (Digital Signal Processor) 108, which will be described later.

The front end 107 is a member containing a memory 300 and a transfer circuit 301, which will be described later. and send.

DSP 108 performs image processing. The DSP 108 performs processing such as correction, compression, etc. on image data captured by the photoelectric conversion element 106 and transmitted from the front end 107 . It also has a separation function for separating image data into A image data and B image data (described later), and a correlation calculation function for performing correlation calculation using A signal and B signal for performing focus detection processing. It also has a function of processing an image signal for display on the display unit 111 . The details of the signal processing flow in these photoelectric conversion element 106, front end 107, and DSP 108 will be described later.

A RAM (random access memory) 109 has the function of a signal holding means for holding digital signals from the front end 107, the function of an image data storage means for storing image data processed by the DSP 108, and the operation of a CPU 110, which will be described later. It also has the function of a work memory when performing. A DRAM (dynamic random access memory) is generally used as the RAM 109 . In this embodiment, the RAM 109 is used to realize these functions, but other types of memory may be used as long as the access speed is sufficiently high and the operation is not problematic. It is possible. In this embodiment, the RAM 109 is arranged outside the DSP 108 and the CPU 110 , but part or all of its functions may be incorporated in the DSP 108 or the CPU 110 .

A display unit 111 displays still images and moving images processed by the DSP 108, menus, and the like. The operation unit 112 sets the CPU 110 for shooting commands, shooting conditions, and the like. A recording medium 113 is a detachable recording medium for recording still image data and moving image data. ROM 114 stores programs that are loaded and executed by CPU 110 to control the operation of each unit.

The CPU 110 comprehensively controls the operation of the photoelectric conversion element 106 . The CPU 110 executes programs for controlling each part of the photoelectric conversion element 106 . It also has a function of controlling the focus drive circuit 116 (to be described later) and adjusting the focus of the photographic optical system 120 using the result of the correlation calculation output from the DSP 108 .

The CPU 110 controls the shutter drive circuit 115 and the aperture drive circuit 118 based on the settings of the operation unit 112 . A shutter drive circuit 115 drives and controls the focal plane shutter 104 under the control of the CPU 110 . A diaphragm drive circuit 118 controls the aperture of the diaphragm 101 by controlling the diaphragm actuator 119 .

Next, the configuration of the photoelectric conversion element 106 will be described with reference to FIG. FIG. 2A shows a pixel array 200 (pixel region) in which a plurality of pixels 201 are two-dimensionally arranged. A plurality of pixels 201 are arranged along the X-axis parallel to the row direction and the Y-axis parallel to the column direction.

As shown in FIG. 2(a), the pixel array 200 includes an effective pixel area and a shaded pixel area. The pixels arranged in the effective pixel area are light receiving pixels from which light enters the photoelectric conversion units 203a and 203b. Pixels included in the light-shielded pixel region are light-shielded pixels (first pixels) including photoelectric conversion units 203a and 203b that are shielded from light. The photoelectric conversion units 203a and 203b are, for example, photodiodes (PD). However, the photoelectric conversion units 203a and 203b may be formed by other than photodiodes, and for example, a photoelectric conversion film provided on a substrate (semiconductor substrate, glass substrate, or the like) may be used.

A light-receiving pixel includes a plurality of photoelectric conversion units 203a and 203b and a microlens 202, and is a pixel to which light passing through a single microlens 202 is incident. As a result, the photoelectric conversion units 203a and 203b have a pupil division structure, and separate images of the same object having a phase difference are incident on the two photoelectric conversion units 203a and 203b. . Hereinafter, these two separate images of the same object having a phase difference will be referred to as an A image and a B image. photoelectric conversion unit. That is, the A image is formed by the A signal based on the charge generated by the photoelectric conversion unit 203a, and the B image is formed by the B signal based on the charge generated by the photoelectric conversion unit 203b. In this embodiment, the B signal is generated by subtracting the A signal from the A+B signal obtained by adding the A signal and the B signal, and the B image is formed from the generated B signal. Also in this case, it is assumed that the B image is formed by the B signal.

A light-shielded pixel includes a plurality of light-shielded photoelectric conversion units 203a and 203b. Although the light-shielded pixels include microlenses in FIG. 2A, the light-shielded pixels may not include microlenses. A light-shielded pixel outputs a black reference signal from a plurality of photoelectric conversion units 203a and 203b. Typically, the black reference signal is used to determine the black level of the light receiving pixels. For example, a black level signal is generated by averaging the black reference signals of a plurality of light-shielded pixels. By subtracting this black level signal from the signal of the light-receiving pixel, the Signal Noise Ratio (hereinafter referred to as S/N ratio) of the signal of the light-receiving pixel can be improved.

FIG. 2B is a diagram for explaining the circuit configuration of the pixel 201. As shown in FIG. In FIG. 2B, photoelectric conversion units 203a and 203b are photoelectric conversion units into which light that has passed through the single microlens 202 described above is incident. Also, in the light-shielded pixel, the photoelectric conversion units 203 a and 203 b are photoelectric conversion units sharing one amplification transistor 207 . The A image transfer transistor TxA (204a) is controlled by the signal φtxa, and the B image transfer transistor TxB (204b) is controlled by the signal φtxb. By setting the signals φtxa and φtxb to High (hereinbelow, High is referred to as H), the transfer transistors become conductive, and charges accumulated in the respective photoelectric conversion units can be transferred to the floating diffusion unit (FD) 205 . Since the conduction/non-conduction (ON/OFF) of the transfer transistor can be independently controlled, the A signal and the B signal can be transferred independently.

A reset transistor 206 is a switch for initializing the FD 205 and is controlled by a signal φpres. The amplification transistor 207 is connected to a constant current source 212, which will be described later, via a selection transistor 208 and a vertical output line 211, which will be described later. When the input signal φsel of the selection transistor 208 becomes H, the amplification transistor 207 is connected to the constant current source 212 . Since the FD 205 is connected to the amplification transistor 207, the charges transferred from the photoelectric conversion units 203a and 203b to the FD 205 are converted by the amplification transistor 207 into a voltage value corresponding to the amount of charge, and output as a signal to the vertical output line 211. be done. Each transistor is composed of, for example, a MOS transistor.

A signal obtained by adding a signal from one photoelectric conversion unit 203a and a signal from the other photoelectric conversion unit 203b (hereinafter referred to as an "A+B signal") is an image signal, and two signals read out from the photoelectric conversion units 203a and 203b. The signal can be used as a signal for focus detection.

Although the A+B signal for image and the A and B signals for focus detection may be read out, the following may be done in consideration of the processing load. Signals (A+B signals) from a plurality of photoelectric conversion units and a focus detection signal (for example, A signal) from one of the photoelectric conversion units 203a and 203b are read out. Then, by taking the difference between the A+B signal and the A signal, the other focus detection signal (for example, the B signal) having parallax is acquired. Alternatively, the focus detection signals (A signal and B signal) of the photoelectric conversion units 203a and 203b are respectively read out, and the read signals are added to acquire the image signal (A+B signal).

FIG. 2C shows a detailed circuit configuration of the photoelectric conversion element 106. As shown in FIG. As described above, a plurality of pixels 201 are arranged in the pixel array 200 . In addition, in FIG.2(c), the light-shielding pixel is abbreviate|omitted and shown.

A timing generator (TG) 210 supplies control pulses necessary for reading to each circuit according to a program set by the CPU 110 .

A vertical scanning circuit 209 outputs a signal to a vertical output line 211 by supplying a pulse to the pixel 201 . The vertical scanning circuit 209 can also select specific pixels and switch driving between selected pixels and non-selected pixels. Although the TG 210 is built in the photoelectric conversion element 106 in this embodiment, it may be arranged outside the photoelectric conversion element 106 .

A signal generated by a photoelectric conversion unit included in each pixel 201 is output to the vertical output line 211 row by row by a driving signal supplied from the vertical scanning circuit 209 as described above. The constant current source 212 forms a source follower circuit in combination with the amplifying transistor 207 described above.

The readout circuit 213 has a function of amplifying the output from the vertical output line 211 of each column. An AD conversion circuit (ADC) 214 converts the output of the readout circuit 213 into a digital signal. The digital signals converted by the ADC 214 are sequentially selected by the horizontal scanning circuit 215 , appropriately image-processed by the image processing unit 216 , and output from the output unit 217 to the outside of the photoelectric conversion element 106 .

Next, detailed configurations of the photoelectric conversion element 106, the front end 107, and the DSP 108 will be described with reference to FIG.

Front end 107 includes memory 300 and transfer circuitry 301 as previously described. The memory 300 stores digital signals output from the output section 217 of the photoelectric conversion element 106 . Specifically, a digital signal output from the pixel array 200 via the output unit 217 is input to the memory 300 and stored in the memory 300 . As the memory 300, for example, a RAM can be used, and both DRAM and SRAM (static random access memory) are applicable. Although the details will be described later, it is preferable to use an SRAM when signals are output from the memory 300 in an order different from the order of addresses in the memory 300 . It is also possible to use a memory other than the RAM as long as the memory has a sufficiently high access speed and does not cause any problem in operation. Transfer circuit 301 transfers the digital signal stored in memory 300 to DSP 108 .

Front end 107 further includes control circuitry 302 . The control circuit 302 can control the memory 300 and the transfer circuit 301 and control the order in which the digital signals are transferred.

The DSP 108 includes a receiving circuit 303 and an arithmetic processing circuit (hereinafter referred to as arithmetic circuit) 305 . The receiving circuit 303 sends the digital signal transferred from the front end 107 to the arithmetic circuit 305 . The arithmetic circuit 305 can perform various arithmetic operations based on pixel information. In the following, as an example of calculation, a case of obtaining a defocus amount for driving the lens 102 and the lens 103 by performing a correlation calculation of the A signal and the B signal will be described. In this embodiment, a case where all pixels are pupil-divided will be described, but only some pixels are pupil-divided (that is, the pixel array has pixels that are not pupil-divided), and the pupil-divided Phase-difference detection may be performed on the selected pixels.

In addition, the arithmetic circuit 305 performs calculation for creating an image to be displayed on the display unit 111, calculation for creating a depth map for obtaining image depth information from the A and B images, tracking calculation for detecting the movement of the subject, and exposure control. AE calculation for control can be performed. Further, WB calculation for determining the white balance of an image, calculation for detecting flicker in an image, light control calculation for determining the amount of flash light emission, and the like are conceivable. Note that the calculations that can be performed by the arithmetic circuit 305 are not limited to the configuration and calculations given here.

The calculations performed by the arithmetic circuit 305 of the DSP 108 do not necessarily require information on all pixels in the pixel array 200 .

FIG. 4A is an example schematically showing an arrangement example of each pixel of the pixel array 200 and a signal output from each pixel. As shown in FIG. 4A, the pixel array 200 includes a light-shielded pixel group including light-shielded first pixels and a second pixel group including second pixels that are light-receiving pixels and output signals for an image. and a third pixel group including third pixels that are light-receiving pixels and output signals for focus detection. In FIG. 4A, the pixel array 200 further includes a fourth pixel group including fourth pixels that are light-receiving pixels and output signals for an image. The second pixel and the fourth pixel have the same configuration, and the only difference is the position in the pixel array 200 . For example, when the pixel array 200 includes n (n is an integer equal to or greater than 1) pixel rows, the pixel array 200 is arranged in n pixel rows from each pixel arranged in the first pixel row. Signals are sequentially output up to each pixel. Specifically, in the example shown in FIG. 4A, the pixel array 200 outputs signals in order of the light-shielded pixel (first pixel) group, the second pixel group, the third pixel group, and the fourth pixel group. That is, the pixel array 200 includes the A+B signal obtained based on the charges generated by the plurality of photoelectric conversion units included in the light-shielded pixel, the A+B signal of the second pixel arranged between the light-shielded pixel and the third pixel, and the A+B signal of the second pixel arranged between the light-shielded pixel and the third pixel. The A signal and A+B signal of three pixels and the A+B signal of the fourth pixel are output in this order. Hereinafter, an A+B signal obtained based on charges generated by a plurality of photoelectric conversion units included in a light-shielded pixel may be referred to as a first signal. Further, the A+B signal of the second pixel arranged between the light-shielded pixel and the third pixel may be called the second signal. Furthermore, the A signal and the A+B signal of the third pixel arranged between the second pixel and the fourth pixel may be called the third signal, and the A+B signal of the fourth pixel may be called the fourth signal.

The A+B signals are read out from the light-shielded pixel group and the second pixel group, and the A signal in addition to the A+B signals is read out from the third pixel group. As shown in FIG. 4A, the pixel array 200 does not read A signals from the light-shielded pixel group and the second pixel group in a certain frame period. Specifically, in a certain frame period, the pixel array 200 is configured not to output the A signal from each pixel arranged in the light-shielded pixel group and the second pixel group to the vertical output line. In the present embodiment, one frame period refers to the period from when the photoelectric conversion device starts generating signals to generate one image (the start of the charge accumulation period of the photoelectric conversion unit) to when signals from pixels are generated. It can be said that it is a period until reading is finished (a period until the vertical scanning circuit finishes scanning the pixel array). One frame period is a period from when the vertical scanning circuit 209 starts scanning each row of a plurality of pixels (vertical scanning) until it reaches the last row and finishes vertical scanning. may In one frame period, for example, when the pixel array is divided into a plurality of fields and read out, the row is selected once by the vertical scanning circuit 209, and then the row is selected again by the vertical scanning circuit 209. It may be a period until it is completed.

As described above, in this embodiment, the A signal is not output to the vertical output line from each pixel arranged in the light-shielded pixel group and the second pixel group in a certain frame period. Any method may be adopted as long as the A signal is not read from the pixels included in the light-shielded pixel group and the second pixel group from the photoelectric conversion element 106 . For example, there is a method in which signals from pixels included in the light-shielded pixel group and the second pixel group are not AD-converted, although signals are output from each pixel. In addition, a method of inputting the A signal to the horizontal scanning circuit 215 but not outputting it from the horizontal scanning circuit 215 and a method of inputting the A signal to the output section 217 but not outputting it from the output section 217 are available. Although it is possible not to always output the A signal from the pixels arranged in the light-shielded pixel group and the second pixel group, at least each pixel arranged in the second pixel group outputs the A signal in another frame period. You may

FIG. 4B is an example showing the order of digital signals stored in the memory 300. As shown in FIG. As shown in FIG. 4B, the data are stored in the order output from the output unit 217, starting from the beginning of the address of the memory 300. FIG. That is, the first signal, the second signal, the third signal, and the fourth signal are input to the memory 300 in this order. In this embodiment, signals are output from the memory 300 in the order of the first signal, the third signal, the second signal, and the fourth signal, and are input to the DSP 108 in this order. As described above, a DRAM is generally used as the RAM 109 . Compared to SRAM, DRAM has a lower degree of freedom in changing the order of writing and reading data. Therefore, by setting the writing order and reading order of the DRAM to a specific order in line with the design of the DRAM, it is possible to speed up the writing and reading of data to and from the DRAM. For example, it is possible to drive the DRAM at a particularly high speed when reading continuously from the beginning of the address of the DRAM. According to each of the following embodiments, the order of the signals is changed before the signals are input to the arithmetic circuit 305 so that the signals can be output in order from the beginning of the address of the RAM 109 . Since the DRAM can improve the driving speed of the DRAM when the signal is output in order from the head of the address, it is possible to reduce the decrease in the signal processing speed in the DSP 108 and reduce the decrease in the frame rate. .

Subsequently, when an image is captured while referring to the timing chart shown in FIG. 5, correlation calculation is performed by the arithmetic circuit 305, the lens is driven based on the information, and the image of the next frame is captured. processing will be described.

First, charge accumulation starts at time t500, and signal reading from the pixel array 200 starts at time t501. In the readout preprocessing period from time t500 to time t501, the photoelectric conversion units 203a and 203b accumulate charges, the AD conversion period, the signal output period to the horizontal scanning circuit 215, and the output unit 217. includes the period for transferring the signal to In other words, the period from reset cancellation of the photoelectric conversion units 203a and 203b to before the signal is read out from the output unit 217 corresponds to the readout preprocessing period. A period from outputting the signal from the photoelectric conversion element 106 to completing storage of the signal in the memory 300 corresponds to a reading period.

In signal readout, the signals obtained from each pixel are output from the pixel array 200 in spatial arrangement order regardless of whether the pixel 201 belongs to the second pixel group 402 or the third pixel group 403 . As an example of acquisition of signals output from pixels, for example, signals are acquired in order from the top of the pixel array 200 . As a result, the temporal order is not changed in the pixel array 200, and the linearity of the slit rolling distortion is ensured, so that the discomfort of the image can be reduced. At the same time as the signal is read out, the pixel information (header information) read out is started to be stored in the memory 300 .

At time t<b>502 , signal readout and storage in the memory 300 are completed, and the first signal output from each light-shielded pixel included in the light-shielded pixel group is output from the memory 300 and transferred from the transfer circuit of the front end 107 to the DSP 108 . begin to be transferred. A first signal obtained based on charges generated by a plurality of photoelectric conversion units included in a light-shielded pixel is used in image processing within the DSP 108 . Specifically, the first signal is used to improve the S/N ratio of the signal of the light-receiving pixel, as described above. used as Compared to the third signal for focus detection by comparing the A signal and the B signal, the first signal may require less accuracy for the A signal and the B signal. Therefore, in this embodiment, the A+B signal is output as the first signal, and the reference value of the A signal is obtained by dividing the A+B signal by the number of photoelectric conversion units per pixel. In such a case, it takes a long time to generate the A signal for the first pixel. According to this embodiment, since the first signal is output before the second signal and the third signal are output, it is possible to secure a period for arithmetic processing of the A signal. The reference value of the A signal can also be obtained by adding a predetermined value as an offset to the A+B signal. Typically, the reference value of the A signal can be obtained by subtracting a predetermined value from the A+B signal.

At time t<b>503 , transfer of the signals of all the light-shielded pixels included in the light-shielded pixel group 404 is completed, and the A signal and the A+B signal obtained from the pixels included in the third pixel group 402 are output from the memory 300 . Although the signals obtained from the pixels included in the second pixel group 403 are stored in the memory 300 before the signals obtained from the pixels included in the third pixel group 402, the signals obtained from the pixels included in the third pixel group 402 are stored in the memory 300 at this time. do not output. That is, the third signal is output prior to the second signal read out from the pixel array 200 .

At time t504, transfer of the A signal and the A+B signal of all the third pixels included in the third pixel group 402 is completed, and the arithmetic processing circuit in the DSP 108 starts the correlation calculation of the A signal and the B signal. start. In addition, transfer of the A+B signal of the second pixel group 403, the A+B signal of the third pixel group, and the A+B signal of the fourth pixel group from the memory 300 is started. The A+B signal of the third pixel group is output to the DSP 108 from time t503 to time t504. signals can be input to the RAM 109 in the order of output.

At time t505, the correlation calculation is completed, and driving of the lens 100 is started based on the result.

At time t506, driving of the lens 100 is completed, and the next accumulation can be started. At the same time, charge accumulation in the photoelectric conversion unit is started in the next frame.

At time t507, the transfer of the second signal, the A+B signal of the third pixel group, and the fourth signal whose transfer was started at time t504 is completed. Upon completion of the transfer of the second signal, the A+B signal of the third pixel group, and the fourth signal, the photographing of one image is completed.

In this timing chart, it has been explained that the correlation calculation is started after the transfer of the signal output from the third pixel group 402 from the memory 300 to the DSP 108 is completed. However, if the correlation calculation can be started with only a part of the pixel information of the third pixel group 402, the calculation is started after all the signals of the third pixel group 402 are transferred from the memory to the outside of the photoelectric conversion element. do not have to.

Next, with reference to FIGS. 6(a) to 6(d), a plurality of specific examples regarding the configuration of the chip on which the photoelectric conversion element 106, the front end 107, and the DSP 108 are arranged will be described.

In the example shown in FIG. 6A, a chip 600 includes a semiconductor substrate including photoelectric conversion elements 106, and a chip 601 includes a front end 107 and includes a semiconductor substrate different from the semiconductor substrate. A chip 600 and a chip 601 are mounted on a mounting substrate 603 including conductive regions. Also, a chip 602 includes the DSP 108 and is mounted on a mounting substrate 604 that includes conductive areas. The photoelectric conversion element 106, the front end 107, and the DSP 108 are electrically connected.

In the example shown in FIG. 6(b), a chip 605 is formed by stacking a chip 600 and a chip 601, and the chip 605 is mounted on a mounting substrate 603 as shown in FIG. 6(a). Different from the example.

In the example shown in FIG. 6C, the chip 606 forms a fifth chip 606 by disposing the photoelectric conversion element 106 and the front end 107 on one semiconductor substrate. A fifth chip 606 is mounted on the mounting substrate 603 and is connected to the first chip 602 , which includes at least the DSP 108 , mounted on the mounting substrate 604 .

The example shown in FIG. 6(d) differs from the example shown in FIG. 6(a) in that a chip 602, a chip 601, and a chip 600 are stacked in order. Note that the arrangement of the chips 601 and 602 may be interchanged.

As described above, according to the present embodiment, information is obtained from pixels in the order of reducing the sense of incongruity of the image, and the calculation necessary for capturing the image is performed while the reference value for correction is obtained. A pixel can be transferred from the pixel information used for Thereby, the correction processing by the arithmetic processing circuit can be started at the timing when the signal of the third pixel group is input to the arithmetic processing circuit. Also, the order of signals input to the arithmetic processing circuit and the order of signals output from the arithmetic processing circuit are the same. If the order of the signals input to the arithmetic processing circuit and the order of the signals output from the arithmetic processing circuit are different, the drive speed for outputting the signals from the RAM may decrease, and the frame rate may decrease. be. On the other hand, according to this embodiment, it is possible to reduce the decrease in the processing speed of the arithmetic processing unit and improve the frame rate. Further, in this embodiment, the A signal and the A+B signal of the third pixel group are input to the arithmetic processing circuit before the A+B signal of the second pixel group is input to the arithmetic processing circuit. As a result, it is possible to advance the timing of starting the correlation calculation related to focus detection, so focus detection can be performed more quickly. As a result, the focusing operation of driving the lens based on the focus detection result can also be performed quickly. As a result, the photoelectric conversion device of this embodiment has the effect of being able to quickly start the charge accumulation operation for the next frame.

<Modification>
The first embodiment can be modified to have a configuration described later. Effects similar to those of the first embodiment can be obtained even when the configuration is modified as follows.

In FIG. 1, a digital signal after AD conversion is output from the photoelectric conversion element 106 . Not limited to this, an analog signal may be output from the photoelectric conversion element 106 . In this case, as the memory 300, a memory that holds the voltage value of the analog signal can be used. However, there is a possibility that leak current or the like may occur in the analog signal held in the memory, which may deteriorate the generated image. In this embodiment, since the third signal is output first while the second signal is held in the memory, the second signal is held in the memory for a longer period of time than when the signals are output in order of spatial arrangement. Therefore, it is preferable that the memory 300 hold a digital signal that is less likely to be deteriorated by leakage current or the like than an analog signal.

In FIG. 4A, a row including light-shielded pixels consists of only a plurality of light-shielded pixels. Without being limited to this, one row may include a light-shielding pixel and a second pixel.

When a pixel row including a light-shielded pixel and a second pixel is located in one row between the light-shielded pixel group and the third pixel group, the signal from the pixel row of the third pixel group is output from the memory 300. After that, the signal from the pixel row containing the light-shielded pixel and the second pixel may be output.

One image may be generated based on signals read out from the entire pixel array 200, or an image may be generated by cropping and reading out a partial region of the pixel array 200. FIG. A range-finding frame 401 is an area in which an object exists, which is set via the operation unit 112, for example. Here, for example, the vertical scanning circuit 209 can be used to select pixels to be used for correlation calculation. Let the selected pixels be a third pixel group 402 and the unselected pixels be a second pixel group 403. Not used.

<Second embodiment>
FIG. 7 is a diagram showing configurations of the photoelectric conversion element 106, the front end 107, and the DSP 108 in the second embodiment. The front end 107 according to the present embodiment differs from the first embodiment in that it includes a write control circuit 700 and a selector 701 and that a memory 300 is composed of a plurality of memories 704 and 705 . different. Other configurations are substantially the same as those of the first embodiment.

The write control circuit 700 can switch between inputting the pixel information output from the photoelectric conversion element 106 to the memory 704, inputting it to the memory 705, or inputting it to both, according to a control signal from the control circuit 702. can. The selector 701 can switch pixel information to be transferred from the transfer circuit 301 to pixel information from the memory 704 or pixel information from the memory 705 according to a control signal from the control circuit 702 .

FIG. 8 shows an example of image information stored in the memory 704 and the memory 705 and their order in the second embodiment. A memory 704 stores the image information of the A+B signal output from the light-shielded pixel group and the A signal and the A+B signal of the third pixel group. Further, the memory 705 stores the image information of the A+B signals of the third pixel group and the second pixel group. In this embodiment, the order of the signals is changed before being input to the memories 704 and 705 so that the signals can be output in order from the beginning of the addresses of the memories 704 and 705 . In this embodiment, it is preferable to use DRAMs as the memories 704 and 705 because signals can be output continuously in the order of addresses.

The operation of the photoelectric conversion device according to the second embodiment will be described with reference to the timing chart of FIG. The timing chart of FIG. 9 stores the A+B signal of the light-shielded pixel in the memory 704, stores the A+B signal of the third pixel in both memories 704 and 705, stores the A signal of the third pixel in the memory 704, and stores the A+B signal of the third pixel in the memory 704. A+B signals of two pixels are stored in memory 705 .

Accumulation starts at time t900, and signal reading starts at time t901. Signals are read out from the pixel array 200 in an order regardless of whether the pixels belong to the shaded pixel group 404, the third pixel group 402, or the second pixel group 403, as in the first embodiment. be That is, signals are read out from the pixel array 200 in order from the top of the screen. Simultaneously with reading the signal, the memory 704 and memory 705 begin to store the read signal.

At time t902, the A+B signals of the shaded pixel group 404 stored in the memory 704 begin to be read out. At this time, the control circuit 702 controls the selector 701 so that the signal can be transferred from the memory 704 to the DSP 108 , and starts transferring the signal of the shaded pixel group 404 to the DSP 108 .

At time t903, the A signal and the A+B signal of the third pixel group 402 stored in the memory 704 start to be transferred to the DSP .

At time t904, the transfer of the third pixel group 402 is completed, and the correlation calculation can be started. At the same time, transfer of the A+B signal of the second pixel group, the A+B signal of the third pixel group 402, and the A+B signal of the second pixel group stored in the memory 705 is started. At this time, the control circuit 702 controls the selector 701 so that the signal can be transferred from the memory 705 to the DSP 108 .

At time t905, the correlation calculation is completed, and the driving of the lens is started based on the result.

At time t906, driving of the lens is completed, and the next accumulation can be started. At the same time, accumulation of the next frame is started. At time t907, the transfer of the A+B signal of the third pixel group 402 and the A+B signal of the second pixel group 403, whose transfer was started at time t904, is completed.

As described above, by performing the operation shown in FIG. 9, the signals stored in the memories 704 and 705 can be read out in the order of storage. As a method, before the signals are stored in the memories 704 and 705, the order of the signals is rearranged in advance according to the order of reading. As described above, this feature is suitable for the memories 704 and 705, such as DRAMs, which are particularly effective for reading in the order of storage. It goes without saying that the memories 704 and 705 may be memories other than DRAM, and the memories described in the first embodiment can be used.

<Third Embodiment>
FIG. 10 is a diagram showing configurations of the photoelectric conversion element 106, the front end 107, and the DSP 108 in the third embodiment. FIG. 11 is a diagram showing image information input to each memory of the photoelectric conversion device according to the third embodiment and the order thereof, and FIG. 12 shows operation timings of the photoelectric conversion device according to the third embodiment. It is the figure which showed the chart.

The photoelectric conversion device according to the third embodiment differs from the second embodiment in that the rearrangement circuit 304 is used to perform arithmetic processing in the arithmetic circuit while reducing the number of transfers of the A+B signals of the third pixel group. is different. This can reduce transmission of redundant signals. Specifically, by using the A+B signal used to generate the focus detection signal as the image signal, it is not necessary to read out the A+B signal of the third pixel again.

The rearrangement circuit 304 rearranges the order of the digital signals input to the DSP so as to match the spatial arrangement order of the pixel array 200 before inputting them to the RAM 109 .

As shown in FIG. 11, the memory 704 stores the A+B signal of the shaded pixel group and the A signal and the A+B signal of the third pixel group. Also, the memory 705 stores the A+B signal of the second pixel group.

As shown in the timing chart of FIG. 12, accumulation starts at time t1100, and the signals output from pixel array 200 start to be stored in memory 704 and memory 705 at time t1101. At the same time, reading of the signals stored in the memories 704 and 705 is started.

At time t1102, the A+B signals of the shaded pixel group 404 stored in the memories 704 and 705 begin to be read. At this time, the control circuit 302 controls the selector 701 so that pixel information can be transferred from the memory 704 to the DSP 108 , and starts transferring the signals of the light-shielded pixel group 404 to the DSP 108 .

At time t1103, transfer of the A signal and the A+B signal of the third pixel group 402 stored in the memory 704 to the DSP 108 is started.

When the transfer of the A signal and the A+B signal of the third pixel group 402 is completed at time t1104, correlation calculation can be started from this point. At the same time, transfer of the A+B signals of the second pixel group stored in the memory 705 is started. At this time, the control circuit 702 controls the selector 701 so that the pixel information can be transferred from the memory 705 to the DSP 108 .

At time t1105, the correlation calculation is completed, and the driving of the lens is started based on the result. At time t1106, the driving of the lens is completed, and the next accumulation can be started. At the same time, accumulation of the next frame is started.

At time t1107, transfer of the A+B signal of the second pixel group 403, which started at time t1104, is completed. At the same time, the rearrangement circuit 304 rearranges the digital signals input to the DSP from the transfer order to the spatial arrangement order of the pixel array 200 . Specifically, the A+B signals of the third pixel group are exchanged among the plurality of second pixel groups according to the arrangement of the pixels and stored in the RAM 109 .

By performing the operation described above with reference to FIG. 12, it is not necessary to transfer overlapping signals a plurality of times in addition to memory reading in the storage order. This makes it possible to prevent redundant transfers.

<Fourth Embodiment>
A moving body according to the present embodiment will be described with reference to FIG. 13 .

FIG. 13(a) shows an example of a photoelectric conversion device for an in-vehicle camera. The photoelectric conversion device 1 has a photoelectric conversion element 10 and a signal processing device 121 . The photoelectric conversion element 10 and the signal processing device 121 are the photoelectric conversion device and signal processing device according to any one of the first to third embodiments. The photoelectric conversion device 1 includes an image processing unit 312 that performs image processing on a plurality of image data acquired by the photoelectric conversion elements 10 , and a parallax (parallax image position) from the plurality of image data acquired by the photoelectric conversion elements 10 . phase difference) is provided. The photoelectric conversion device 1 also includes a distance measurement unit 316 that calculates the distance to the object based on the calculated parallax, and a collision determination unit that determines whether there is a possibility of collision based on the calculated distance. 318 and . Here, the parallax calculation unit 314 and the distance measurement unit 316 are examples of distance information acquisition means for acquiring distance information to the target object. That is, the distance information is information related to parallax, defocus amount, distance to the object, and the like. The collision determination unit 318 may use any of these distance information to determine the possibility of collision. The distance information acquisition means may be implemented by specially designed hardware, or may be implemented by a software module. Moreover, it may be implemented by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like, or by a combination thereof.

The photoelectric conversion device 1 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Further, the photoelectric conversion device 1 is connected to a control ECU 330 which is a control device that outputs a control signal for generating a braking force to the vehicle based on the determination result of the collision determination section 318 . The photoelectric conversion device 1 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination section 318 . For example, if the collision determination unit 318 determines that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, or suppressing the engine output. The alarm device 340 warns the user by sounding an alarm such as sound, displaying alarm information on a screen of a car navigation system, or vibrating a seat belt or steering wheel.

In this embodiment, the photoelectric conversion device 1 captures an image of the surroundings of the vehicle, for example, the front or rear. FIG. 13B shows a photoelectric conversion device for capturing an image in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends an instruction to the photoelectric conversion device 1 or photoelectric conversion element 10 to perform a predetermined operation. With such a configuration, the accuracy of distance measurement can be further improved.

In the above, an example of controlling so as not to collide with another vehicle was explained, but it can also be applied to control to automatically drive following another vehicle or control to automatically drive so as not to stray from the lane. . Furthermore, the photoelectric conversion device can be applied not only to vehicles such as own vehicles but also to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent transportation systems (ITS).

[Modified embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible. For example, an example in which a part of the configuration of one of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced is also an embodiment of the present invention.

It should be noted that the above-described embodiments are merely examples of specific implementations of the present invention, and the technical scope of the present invention should not be construed to be limited by these. That is, the present invention can be embodied in various forms without departing from its technical concept or main features.

106 photoelectric conversion element 201 pixel 300 memory

Claims (20)

a pixel array in which a plurality of pixels each including a plurality of photoelectric conversion units are arranged two-dimensionally;
a memory to which a signal output from the pixel array is input;
an arithmetic processing circuit that receives a signal output from the memory and performs arithmetic processing using the signal,
the plurality of pixels includes a first pixel in which the plurality of photoelectric conversion units are shielded from light, and a second pixel and a third pixel in which light enters the plurality of photoelectric conversion units;
The pixel array includes a first signal based on charges generated by a plurality of photoelectric conversion units included in the first pixels and a second signal based on charges generated by a plurality of photoelectric conversion units included in the second pixels. , and a third signal including at least one of a signal based on charges generated by one photoelectric conversion unit included in the third pixel and a signal based on charges generated by the other photoelectric conversion unit included in the third pixel , in this order,
the first signal, the second signal, and the third signal are held in the memory;
the first signal, the second signal, and the third signal output from the memory are input to the arithmetic processing circuit in the order of the first signal, the third signal, and the second signal ;
performing the arithmetic processing during at least part of a period including a first period during which the third signal is input to the arithmetic processing circuit and a second period during which the second signal is input to the arithmetic processing circuit; A photoelectric conversion device characterized by: a first pixel that includes a plurality of shielded photoelectric conversion units and outputs a black reference signal from the plurality of photoelectric conversion units;
a second pixel including a plurality of photoelectric conversion units for generating an image signal;
a pixel array including a plurality of photoelectric conversion units and a third pixel for generating an image signal and a focus detection signal;
a memory to which a signal output from the pixel array is input;
an arithmetic processing circuit that receives a signal output from the memory and performs arithmetic processing using the signal,
The pixel array includes a first signal that is a black reference signal output by the first pixel, a second signal that is an image signal output by the second pixel, and an image signal that is output by the third pixel. and a third signal including a signal for focus detection are output in this order,
the first signal, the second signal, and the third signal are held in the memory;
the first signal, the second signal, and the third signal output from the memory are input to the arithmetic processing circuit in the order of the first signal, the third signal, and the second signal ;
performing the arithmetic processing during at least part of a period including a first period during which the third signal is input to the arithmetic processing circuit and a second period during which the second signal is input to the arithmetic processing circuit; A photoelectric conversion device characterized by: a pixel array in which a plurality of pixels each including a plurality of photoelectric conversion units are arranged two-dimensionally;
a memory to which a signal output from the pixel array is input;
an arithmetic processing circuit that receives a signal output from the memory and performs arithmetic processing using the signal,
the plurality of pixels includes a first pixel in which the plurality of photoelectric conversion units are shielded from light, and a second pixel and a third pixel in which light enters the plurality of photoelectric conversion units;
The pixel array includes a first signal based on charges generated by a plurality of photoelectric conversion units included in the first pixels and a second signal based on charges generated by a plurality of photoelectric conversion units included in the second pixels. , and a third signal including at least one of a signal based on charges generated by one photoelectric conversion unit included in the third pixel and a signal based on charges generated by the other photoelectric conversion unit included in the third pixel , in this order,
the first signal, the second signal, and the third signal are held in the memory;
the first signal, the second signal, and the third signal output from the memory are input to the arithmetic processing circuit in the order of the first signal, the third signal, and the second signal;
The photoelectric conversion device, wherein the arithmetic processing is arithmetic processing related to focus detection using the third signal . a first pixel that includes a plurality of shielded photoelectric conversion units and outputs a black reference signal from the plurality of photoelectric conversion units;
a second pixel including a plurality of photoelectric conversion units for generating an image signal;
a pixel array including a plurality of photoelectric conversion units and a third pixel for generating an image signal and a focus detection signal;
a memory to which a signal output from the pixel array is input;
an arithmetic processing circuit that receives a signal output from the memory and performs arithmetic processing using the signal,
The pixel array includes a first signal that is a black reference signal output by the first pixel, a second signal that is an image signal output by the second pixel, and an image signal that is output by the third pixel. and a third signal including a signal for focus detection are output in this order,
the first signal, the second signal, and the third signal are held in the memory;
the first signal, the second signal, and the third signal output from the memory are input to the arithmetic processing circuit in the order of the first signal, the third signal, and the second signal;
The photoelectric conversion device, wherein the arithmetic processing is arithmetic processing related to focus detection using the third signal . each of at least the second pixel and the third pixel among the plurality of pixels includes one microlens;
the microlens included in the second pixel is arranged such that light passing through the microlens is incident on the plurality of photoelectric conversion units included in the second pixel;
5. The microlens included in the third pixel is arranged such that light passing through the microlens is incident on the plurality of photoelectric conversion units included in the third pixel. 2. The photoelectric conversion device according to item 1 . 6. The signal based on the plurality of photoelectric conversion units included in the first pixel is a signal obtained by adding a signal of one photoelectric conversion unit and a signal of the other photoelectric conversion unit. The photoelectric conversion device according to any one of items 1 and 2. further comprising a write control circuit,
7. The photoelectric conversion device according to claim 1, wherein the write control circuit changes the order of the signals output from the pixel array before inputting them to the memory. further comprising a write control circuit,
8. The photoelectric conversion device according to claim 1, wherein said write control circuit changes the order of the signals output from said memory before inputting them to said arithmetic processing circuit. 9. The photoelectric conversion device according to claim 1, wherein said memory is a RAM (random access memory). 10. The photoelectric conversion device according to claim 9 , wherein said memory is a DRAM (dynamic random access memory). The memory has a first memory, a second memory, and a selector connected to the first memory and the second memory, wherein the selector receives a signal from each of the first memory and the second memory. 11. The photoelectric conversion device according to claim 1 , outputting to said arithmetic processing circuit . further comprising a vertical scanning circuit that controls signals output from the pixel array;
The vertical scanning circuit selects, in order, a pixel row including the first pixels, a pixel row including the second pixels, and a pixel row including the third pixels. 12. The photoelectric conversion device according to claim 1, wherein the signal, the second signal, and the third signal are output in this order. a plurality of the first pixels arranged in a row direction and a column direction;
changing the order of the first signals obtained from the first pixels arranged in the column direction;
13. The photoelectric conversion device according to claim 1, wherein the order of the first signals obtained from the first pixels arranged in the row direction is not changed. The pixel array is arranged on a first chip,
the memory is arranged on a second chip that is a different chip from the first chip;
14. The photoelectric conversion device according to claim 1, wherein the first chip and the second chip are laminated. The pixel array is arranged on a first chip,
The arithmetic processing circuit is arranged on a second chip that is different from the first chip,
15. The photoelectric conversion device according to claim 1, wherein the first chip and the second chip are laminated. being mobile,
a photoelectric conversion device according to any one of claims 1 to 15 ;
a mobile device;
a processing device that acquires information from the signal output from the photoelectric conversion unit;
a control device that controls the mobile device based on the information;
A moving body characterized by having A signal processing device to which a signal from a pixel array having a plurality of pixels is input,
The signal processing device includes a memory to which the signal output from the pixel array is input, and an arithmetic processing circuit to which the signal output from the memory is input and performs arithmetic processing using the signal,
The plurality of pixels included in the pixel array includes a first pixel in which a plurality of photoelectric conversion units are shielded from light, and a second pixel and a third pixel in which light enters the plurality of photoelectric conversion units,
From the pixel array, a first signal based on charges generated by a plurality of photoelectric conversion units included in the first pixel and a second signal based on charges generated by a plurality of photoelectric conversion units included in the second pixel , and at least one of a signal based on charges generated by one photoelectric conversion unit included in the third pixel and a signal based on charges generated by the other photoelectric conversion unit included in the third pixel. signals are output in this order,
the memory holds the first signal, the second signal, and the third signal;
the first signal, the second signal, and the third signal output from the memory are input to the arithmetic processing circuit in the order of the first signal, the third signal, and the second signal ;
performing the arithmetic processing during at least part of a period including a first period during which the third signal is input to the arithmetic processing circuit and a second period during which the second signal is input to the arithmetic processing circuit; A signal processor characterized by: The signal processing device further comprises a write control circuit,
18. The signal processing device according to claim 17 , wherein the write control circuit changes the order of the signals output from the pixel array before inputting them to the memory. The signal processing device further comprises a write control circuit,
18. The signal processing apparatus according to claim 17 , wherein said write control circuit changes the order of the signals output from said memory before inputting them to said arithmetic processing circuit. 20. The signal processing apparatus according to any one of claims 17 to 19 , wherein said memory is a RAM (random access memory).

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