JP7267121B2 - Semiconductor integrated circuit device - Google Patents

Description

The invention disclosed in this specification relates to a semiconductor integrated circuit device.

FIG. 6 is a diagram showing a conventional example of a semiconductor integrated circuit device. The conventional semiconductor integrated circuit device X has a function of amplifying an analog input signal AI externally input from a sensor or the like inside the device and subjecting it to various internal processes. The semiconductor integrated circuit device X also has a function of externally outputting an analog output signal AO corresponding to the amplified signal as means for checking whether the analog input signal AI is correctly amplified inside the device. there is

As an example of conventional technology related to the above, Patent Document 1 can be cited.

JP 2007-304095 A

However, in the conventional semiconductor integrated circuit device X, both the terminal X1 for receiving the external input of the analog input signal AI and the terminal X2 for externally outputting the analog output signal AO are provided side by side on one side X3 of the package X3. had been

Therefore, between the terminals X1 and X2 (for example, between the parallel running portions of the substrate wiring pattern connected to the terminals X1 and X2 outside the semiconductor integrated circuit device X, or between the terminals inside the semiconductor integrated circuit device X). Mutual interference may occur between the analog input signal AI and the analog output signal AO due to capacitive coupling between the parallel running portions of the wires connected to X1 and X2 respectively.

The invention disclosed in this specification is to provide a semiconductor integrated circuit device capable of suppressing interference between analog inputs and outputs in view of the above-described problems found by the inventors of the present application. aim.

Therefore, a semiconductor integrated circuit device disclosed in this specification includes a first terminal for receiving an external input of an analog input signal, an amplifier for amplifying the analog input signal to generate an amplified signal, a logic unit for generating a digital output signal according to the signal; and a second terminal for externally outputting an analog output signal according to the amplified signal. The second terminal is provided on a second side different from the first side (first configuration).

The semiconductor integrated circuit device having the first configuration may further have a third terminal for externally outputting the digital output signal (second configuration).

In the semiconductor integrated circuit device having the second configuration, the third terminal may be provided on a third side facing the first side (third configuration).

Further, the semiconductor integrated circuit device having any one of the first to third configurations has a fourth terminal for externally outputting a threshold voltage to be compared with the amplified signal, and the fourth terminal is the third terminal. A configuration (fourth configuration) in which the first terminal and the second terminal are not adjacent to each other is preferable.

Further, the semiconductor integrated circuit device having the second or third configuration further has a fourth terminal for externally outputting a threshold voltage to be compared with the amplified signal, the fourth terminal being connected to the third A configuration (fifth configuration) provided at a position not adjacent to the terminal is preferable.

Further, the semiconductor integrated circuit device having the fourth or fifth configuration is provided with a threshold voltage generating section that generates the threshold voltage, and a comparison signal between the amplified signal and the threshold voltage, which is generated and output to the logic section. and a buffer amplifier provided between the threshold voltage generator and the comparator (sixth configuration).

The semiconductor integrated circuit device having any one of the first to sixth configurations further has a fifth terminal for externally connecting the oscillator, and the terminals adjacent to the fifth terminal are a test terminal and a ground terminal. , or a configuration (seventh configuration) that is an unused terminal.

In the semiconductor integrated circuit device having the seventh configuration, the fifth terminal is provided on one of the four sides of the package to which the digital output signal is output (eighth configuration). do it.

In the semiconductor integrated circuit device having any one of the first to eighth configurations, the sixth terminals provided at the four corners of the package may be test terminals, ground terminals, or unused terminals. 9).

Further, the semiconductor integrated circuit device having the third configuration described above further includes a comparator that generates a comparison signal between the amplified signal and a predetermined threshold value and outputs the comparison signal to the logic section, wherein the amplifier and the comparator A configuration (tenth configuration) in which the amplifier is upstream and the comparator is downstream is preferably arranged in the first direction along the signal path from the first terminal to the third terminal.

Further, in the semiconductor integrated circuit device having the tenth configuration, a plurality of the comparators may be arranged in a second direction perpendicular to the first direction (eleventh configuration).

In the semiconductor integrated circuit device having the eleventh configuration, a signal line extending in the second direction is connected to a connection node between the amplifier and the comparator, and a buffer amplifier connected to the signal line. It is preferable that the analog output signal is externally output from the second terminal via the (twelfth configuration).

In the semiconductor integrated circuit device having the twelfth structure, the second terminal may be provided near the center of the second side (thirteenth structure).

In the semiconductor integrated circuit device having any one of the first to thirteenth configurations, the analog input signal is a signal received by a vibrator externally connected to the first terminal (fourteenth configuration). configuration).

Further, the semiconductor integrated circuit device having the fourteenth configuration may further include transmitting means for outputting a burst wave to the vibrator (fifteenth configuration).

Further, in the semiconductor integrated circuit device having the fifteenth configuration, the transmission means includes a first output stage and a second output stage for outputting burst waves to a first oscillator and a second oscillator which are externally connected as the oscillators, respectively. It is preferable that two output stages are included and the reference potential lines of the respective output stages are separated from each other (sixteenth configuration).

Further, the ultrasonic flowmeter disclosed in the present specification is arranged opposite to the semiconductor integrated circuit device having the sixteenth configuration above and the fluid conduit at a predetermined angle with respect to the flow of the fluid. A configuration (a seventeenth configuration) includes the first oscillator and the second oscillator.

According to the semiconductor integrated circuit device disclosed in this specification, it is possible to suppress interference between analog inputs and outputs.

Diagram showing the overall configuration of an ultrasonic flowmeter FIG. 11 is a diagram showing a pin arrangement (first example) of a semiconductor integrated circuit device; FIG. 10 is a diagram showing a pin arrangement (second example) of a semiconductor integrated circuit device; A diagram showing the internal structure of a semiconductor integrated circuit device subjected to a pin arrangement replacement experiment. Figure showing the result of pin arrangement swapping experiment A diagram showing a configuration example of transmission means A diagram showing a conventional example of a semiconductor integrated circuit device

<Ultrasonic flow meter>
FIG. 1 is a diagram showing the overall configuration of an ultrasonic flowmeter. The ultrasonic flowmeter 100 shown in the figure includes a first transducer 1 and a second transducer 2 . The first vibrator 1 and the second vibrator 2 are arranged to face a fluid conduit (not shown) at a predetermined angle with respect to the fluid flow. For example, the first oscillator 1 is arranged on the upstream side of the fluid, and the second oscillator 2 is arranged on the downstream side of the fluid.

If the speed of sound is C and the speed of flow is v, the propagation speed of ultrasonic waves from the upstream side to the downstream side of the fluid is (C+v), and the propagation speed of ultrasonic waves from the downstream side to the upstream side is (C−v ). The flow velocity v is obtained from the difference in propagation velocity (and the difference in propagation time), and the flow rate Q (= v S K, where S is the cross-sectional area of the fluid conduit, and K is the correction coefficient). Calculated.

Further, the ultrasonic flowmeter 100 includes a semiconductor integrated circuit device 5 including an analog section 3 and a logic section 4, and a first oscillator 6, a battery 7, a shutoff valve 11, and a seismic detector arranged outside the semiconductor integrated circuit device 5. A device 12, a pressure sensor 13, a display means 14, a microcomputer 10, and the like are provided.

The first oscillator 6 generates a clock with a frequency of, for example, 32 kHz (32.768 kHz to be exact). The clock generated by the first oscillator 6 is referred to herein as the "slow clock".

The analog section 3 includes transmission means 31 , switching means 32 , conversion means 33 , first amplification means 34 , second amplification means 35 , first comparator 36 , second comparator 37 , and third comparator 38 . and an internal power supply regulator 39 .

The first amplifying means 34 and the second amplifying means 35 (or these and the converting means 33) amplify the analog input signal AI externally input from the first oscillator 1 or the second oscillator 2 to obtain a received signal ER. It can also be understood as a receiving amplifier 3A that generates (=amplified signal).

The analog section 3 further has a bias section 3B and a buffer amplifier 3C. More specifically, the analog section 3 has a threshold voltage generating section 3D and a buffer amplifier 3E.

The transmission means 31 outputs the burst wave BURST to one of the first oscillator 1 and the second oscillator 2 via the switching means 32 . Note that the burst wave BURST is a rectangular wave signal or a sine wave signal that is intermittently generated at a predetermined frequency (for example, 520 kHz). The number of pulses N of the burst wave BURST is appropriately set depending on the types of the first transducer 1 and the second transducer 2 and the type of the ultrasonic flowmeter 100, and is set to N=4 to 6, for example.

The switching means 32 receives the transmission/reception direction control signal SJ from the logic section 4 and switches the transmission side of the burst wave BURST to one of the first oscillator 1 and the second oscillator 2 . When the first transducer 1 is on the transmission side of the burst wave BURST, the second transducer 2 is on the reception side, and when the second transducer 2 is on the transmission side of the burst wave BURST, the first Transducer 1 becomes the receiving side.

The converting means 33 converts the output format of the signal received by the first oscillator 1 or the second oscillator 2 via the switching means 32 . Specifically, when the output format of the signal is the current output format, the conversion means 33 performs a process of converting the current signal into a voltage signal, ie, a so-called I/V conversion process. On the other hand, when the output format of the signal is the voltage output format, a process of converting a voltage signal of a certain level into a voltage signal of a different level, that is, a V/V conversion process is performed. However, if such V/V conversion processing is unnecessary, the conversion means 33 may be omitted.

The first amplifying means 34 amplifies the signal input from the first oscillator 1 or the second oscillator 2 via the converting means 33 with a predetermined first gain, thereby increasing the amplified signal amplitude to a predetermined magnitude. Adjust coarsely.

The second amplifying means 35 further amplifies the signal amplified by the first amplifying means 34 with a predetermined second gain, thereby finely adjusting the amplified signal amplitude to a predetermined magnitude.

Further, if one of the first amplifying means 34 and the second amplifying means 35 has a gain adjusting function, the other can be omitted. A PGA (programmable gain amplifier) capable of adjusting the gain in multiple stages (for example, 256 stages) can be used as the amplifying means having the gain adjustment function. It should be noted that the "reception signal ER" in this specification is synonymous with the amplified signal output from the reception amplifier 3A.

Further, an enable signal VCCCNT is input to each of the converting means 33, the first amplifying means 34, and the second amplifying means 35. FIG. For example, when the enable signal VCCCNT is set to a high level, the converting means 33, the first amplifying means 34, and the second amplifying means 35 are enabled (=predetermined circuit operations can be performed).

The first comparator 36 detects whether or not the peak value of the reception signal ER (=output signal of the reception amplifier 3A) falls within a predetermined range.

The second comparator 37 serves as a so-called envelope comparator that detects whether the received signal ER exceeds a predetermined threshold. For example, the envelope comparison signal ENV_CMP generated by the second comparator 37 becomes high level when the reception signal ER exceeds a predetermined threshold voltage ENVREF, and becomes low level when it falls below the threshold voltage ENVREF.

A third comparator 38 detects the zero-crossing point of the received signal ER. For example, the zero-cross detection signal ZERO_CMP generated by the third comparator 38 becomes high level when the received signal ER exceeds the zero-cross point, and becomes low level when it falls below it.

The internal power supply regulator 39 stabilizes an external power supply voltage (for example, 1.8 V or 2.2 V) supplied from the battery 7 and generates an internal power supply voltage for driving the analog section 3 and the logic section 4 . As the battery 7, for example, a lithium ion battery may be used.

An enable signal ANGCNT is input to each of the first comparator 36, the second comparator 37, and the third comparator 38. FIG. For example, when the enable signal ANGCNT is set to high level, the first comparator 36, the second comparator 37, and the third comparator 38 are enabled.

As described above, the reception amplifier 3A amplifies the analog input signal AI externally input from the first oscillator 1 or the second oscillator 2 to generate the reception signal ER (=amplified signal).

The bias section 3B sets the bias potential of the received signal ER (=amplified signal).

The buffer amplifier 3C receives the reception signal ER output from the reception amplifier 3A, and outputs an analog output signal AO corresponding to the reception signal ER (=amplified signal) in the test mode of the semiconductor integrated circuit device 5. Output to the outside of the semiconductor integrated circuit device 5 .

The threshold voltage generation unit 3D generates the aforementioned threshold voltage ENVREF.

The buffer amplifier 3E outputs to the second comparator 37 the threshold voltage ENVREF input from the threshold voltage generator 3D.

The logic unit 4 is a circuit block that generates a digital output signal DO according to the received signal ER (more specifically, the output signals of the comparators 36 to 38). 2 oscillators 43 , a first propagation time counter 44 , a third oscillator 45 , a second propagation time counter 46 , an error counter 47 and a microcomputer interface 48 .

The control means 40 corresponds to the central part of the logic part 4, measures the propagation time of fluid (for example, gas), verifies the clocks generated by the second oscillator 43 and the third oscillator 34, and variously controls the analog part 3. I do. The control means 40 also has a function of adjusting the gains of the first amplifying means 34 and the second amplifying means 35 based on various signals input from the analog section 3 . In addition, for the above gain adjustment, for example, it is conceivable to divide the maximum 40 db (100 times) into 128 and perform the gain adjustment digitally in 1 to 128 steps.

The transmission/reception direction control means 42 generates a transmission/reception direction control signal SJ according to an instruction from the control means 40 or the microcomputer-in-interface 48 .

The second oscillator 43 is composed of, for example, a CR oscillator using resistors and capacitors. More specifically, as the second oscillator 43, it is preferable to employ a CR oscillator that generates a clock by charging and discharging a capacitor with a constant current. The frequency of the clock generated by the second oscillator 43 is set to 4 MHz, for example. Further, the second oscillator 43 may be replaced with a ceramic oscillator (not shown) provided outside the semiconductor integrated circuit device 5 instead of the CR oscillator. In this document, the clock generated by the second oscillator 43 is called "medium speed clock".

In particular, by incorporating the second oscillator 43 into the semiconductor integrated circuit device 5, it is possible to eliminate the installation of a CR oscillator or a ceramic oscillator, which has conventionally been prepared outside the semiconductor integrated circuit device 5. It is possible to reduce the size and cost of the total 100.

A first propagation time counter 44 counts the clock generated by the second oscillator 43 .

The third oscillator 45 is composed of, for example, a ring oscillator. The frequency of the clock generated by the third oscillator 45 is set to 500 MHz, for example. The clock generated by the third oscillator 45 is referred to herein as the "fast clock".

A second propagation time counter 46 counts the clock generated by the third oscillator 45 .

As described above, the "low-speed clock", "medium-speed clock", and "high-speed clock" are oscillation signals generated by the first oscillator 6, the second oscillator 43, and the third oscillator 45, respectively. Yes, the high-speed clock has a faster propagation time than the medium-speed clock, and the medium-speed clock has a faster propagation time than the low-speed clock. In other words, regarding the frequency of each clock, there is a magnitude relationship of high-speed clock>medium-speed clock>low-speed clock.

The error counter 47 counts the number of errors occurring when measuring the propagation time of the fluid M times. Here, the error means that the received signal ER is larger than a predetermined threshold ER_H_Vth (high error), smaller than a predetermined threshold ER_L_Vth (low error), and that a predetermined time has passed since the burst wave BURST was transmitted. It means when the received signal ER is nevertheless not detected (overflow).

In the measurement of the propagation time, the measurement from upstream to downstream of the fluid conduit and the measurement from downstream to upstream are regarded as one packet, and measurement is performed, for example, 64 packets. is the role of For example, if an error occurs 10 times or more out of 64 packets of measurement, the gain is readjusted or reset in the first amplifying means 34, the second amplifying means 35, etc. of the analog section 3. It will be. The number of errors described above can be arbitrarily set based on the accuracy required for the ultrasonic flowmeter 100 . If the error counter 47 is not provided, the accuracy of the ultrasonic flowmeter 100 may deteriorate. However, the error counter 47 is not an essential component.

The microcomputer interface 48 sends various data taken out from the first propagation time counter 44, the second propagation time counter 46, and the error counter 47 to the microcomputer 10 outside the semiconductor integrated circuit device 5 to perform various arithmetic processing. Plays a role as a repeater.

The shut-off valve 11, the seismoscope 12, the pressure sensor 13, the display means 14, etc. are provided outside the semiconductor integrated circuit device 5 as means for realizing the attached functions of the ultrasonic flowmeter 100. , are all controlled by the microcomputer 10 .

<Pin arrangement>
FIG. 2A is a diagram showing the pin arrangement (first example) of the semiconductor integrated circuit device 5. FIG. The semiconductor integrated circuit device 5 employs a 48-pin QFP [Quad Flat Package] as its package 50 (=a package in which 12 bending pins are derived from each of the four sides of the package 50, for a total of 48 bending pins).

When the up, down, left, and right directions of the paper surface are defined as the up, down, left, and right directions in plan view of the package 50, the lower side 52 (=corresponding to the second side) of the package 50 is provided with 1 to 12 pins in order from the left side of the paper surface. there is The right side 53 (=corresponding to the third side) of the package 50 is provided with 13 to 24 pins in order from the bottom of the page. The upper side 54 (=corresponding to the fourth side) of the package 50 is provided with 25 to 36 pins in order from the right side of the paper. The left side 51 (=corresponding to the first side) of the package 50 is provided with 37 to 48 pins in order from the upper side of the paper surface. The function of each pin will be briefly described below.

1 pin (N.C.) is an unused terminal. 2 pin (VBG) is a bandgap voltage output terminal. Pin 3 (VIN) is a storage battery (battery) power supply terminal. Pin 4 (SWVREG) is the H-bridge regulator power supply. Pin 5 (VREG) is an LDO regulator output terminal (analog block power supply terminal (2.2V)). Pin 6 (AVSS) is an analog ground terminal. The 7th pin (A3INP) is an amplifier output monitor terminal. Pin 8 (ENVREF) is an envelope threshold voltage monitor terminal. Pin 9 (HALT) is a regulator/ceramic resonator control terminal (L=off, H=on). A 10th pin (XTOUT) is a ceramic oscillator output terminal. The 11th pin (XTIN) is a ceramic oscillator input terminal. That is, a ceramic vibrator forming the second oscillator 43 is externally connected between the 10th pin and the 11th pin. Pin 12 (TEST3) is a test input/output terminal (L output during normal operation).

The 13th pin (N.C.) is an unused terminal. A 14th pin (SCL) is a serial interface clock terminal. A 15th pin (SDA) is a serial interface data terminal. That is, the microcomputer 10 is externally connected to the 14th pin and the 15th pin. A 16th pin (VSSIO) is an interface ground terminal. A 17th pin (SIORQ) is a measurement cycle check terminal. Pin 18 (DIR) is a signal terminal for downstream/upstream monitoring. A 19th pin (VCCCNT) is an amplifier power supply control terminal (L=off, H=on). The 20th pin (TEST4) and the 21st pin (TEST5) are test input/output terminals (L output during normal operation). A 22nd pin (XTOUT2) is a crystal oscillator output terminal. A 23rd pin (XTIN2) is a crystal oscillator input terminal. That is, a crystal oscillator forming the first oscillator 6 is externally connected between the 22nd and 23rd pins. A 24th pin (TEST6) is a test input/output terminal (L output during normal operation).

A 25th pin (DVSS) is a digital ground terminal. A 26th pin (RESET) is a reset input terminal (effective at L). A 27th pin (IORQ) is an interrupt output terminal. The 28th pin (TEST0), 29th pin (TEST1), and 30th pin (TEST2) are test input terminals (connected to ground during normal operation). A 31st pin (VREG2) is an LDO regulator output terminal (digital block power supply terminal (1.8V)). Pin 32 (DVDD) is a logic power supply terminal (shorted with VREG2 in PWB). A 33rd pin (ZEOUT) is a zero cross comparator output terminal. A 34th pin (ANGCNT) is a comparator power supply control terminal (L=off, H=on). A 35th pin (RCOSCRES) is a resistor connection terminal for an RC oscillator (=second oscillator 43). Pin 36 (VSSRCOSC) is the ground terminal for the RC oscillator.

Pin 37 (OSCTEST) is an analog test input terminal (connected to ground during normal operation). Pin 38 (TESTMODE) is a test mode control terminal (0=off, 1=on, grounded during normal operation). A 39th pin (PANATESTMODE) is a PANA test mode control terminal (0=off, 1=on, grounded during normal operation). Pins 40 (SNHP) and 41 (SNHL) are upstream ultrasonic transducer terminals. The first vibrator 1 is externally connected between the 40th pin and the 41st pin. Pins 42 (VSSHBRDRVH) and 43 (VSSHBRDRVL) are ground terminals for the H-bridge output stage. Pins 44 (SNLN) and 45 (SNLP) are downstream ultrasonic transducer terminals. A second vibrator 2 is externally connected between the 44th and 45th pins. Pins 46 (AVSS) and 47 (AVSS) are analog ground terminals. The 48th pin (N.C.) is an unused terminal.

Of the 48 pins, the 40th pin (SNHP) and 41st pin (SNHL), and the 44th pin (SNLN) and 45th pin (SNLP) are the first pins for receiving the external input of the analog input signal AI. Corresponds to a terminal. A 7th pin (A3INP) corresponds to a second terminal for externally outputting an analog output signal AO corresponding to the received signal ER (=amplified signal). A 15th pin (SDA) corresponds to a third terminal for externally outputting the digital output signal DO. An eighth pin (ENVREF) corresponds to a fourth terminal for externally outputting a threshold voltage ENVREF to be compared with the received signal ER (=amplified signal).

Here, first terminals (40th, 41st, 44th and 45th pins) functioning as analog input terminals are provided on the first side 51 of the package 50 . On the other hand, the second terminal (pin 7) functioning as an analog output terminal is provided on the second side 52 different from the first side 51 .

By adopting such a pin arrangement, compared to the conventional example (FIG. 6) in which both the analog input terminal and the analog output terminal are provided on the same side, Interference can be suppressed. Therefore, the measurement accuracy of the ultrasonic flowmeter 100 can be improved while monitoring the analog output signal AO.

For example, when the receiving amplifier 3A has a high gain (e.g., 60 dB or more), conventionally, an offset flow rate of about 20 Lh (=error detected at zero flow rate when no fluid is flowing) occurs. By adopting the pin arrangement, the offset flow rate can be improved to almost 0 L/h.

In this figure, an example in which the analog output terminal is provided on the second side 52 has been described. Any one of the pins provided on the four sides 54 may be used as an analog output terminal.

Furthermore, a characteristic internal configuration of the semiconductor integrated circuit device 5 will be described. First, the arrangement position of the first oscillator 6 that generates the slowest but most accurate "low-speed clock" among the plurality of clocks will be described.

It is desirable that the first oscillator 6 be provided near one of the four sides of the package 50 (=the right side 53) where logic output with little noise is performed. More specifically, the first oscillator 6 is a package 50 formed by the right side 53 and an upper side 54 on which a digital ground terminal (25 pins) and test terminals (28 pins, 29 pins, and 30 pins) are arranged. It is desirable to provide near the upper right corner of the

Also, on both sides of pins 22 and 23 to which the crystal oscillator of the first oscillator 6 is connected, it is preferable to provide test input/output terminals (pins 21 and 24) which are set to low level during normal operation.

Next, the arrangement position of the second oscillator 43 that generates the "medium-speed clock" that has the second accuracy and is used as the control clock among the plurality of clocks will be described.

Like the first oscillator 6, the second oscillator 43 is desirably provided in the vicinity of one of the four sides of the package 50 (=right side 53) where logic output with low noise is performed. More specifically, the second oscillator 43 is preferably provided near the serial communication terminals (pins 14 and 15) between the logic section 4 and the microcomputer 10 .

Also, next to at least one of the 10th pin and 11th pin (next to the 11th pin in this figure) to which the ceramic oscillator of the second oscillator 43 is connected, there is a test input/output terminal (pin 12) which is set to a low level during normal operation. ) should be provided.

Next, signal paths inside the semiconductor integrated circuit device 5 will be described. By arranging the analog input terminals (40, 41, 44 and 45 pins) on the left side 51 of the package 50 and arranging the digital output terminals (14 and 15 pins) on the right side 53 of the package 50, analog input The signal path from the terminal to the digital output terminal becomes a straight line.

The receiving amplifier 3A and the comparators 36 to 38 are arranged in the first direction (=horizontal direction on the paper surface) along the signal path, with the receiving amplifier 3A on the upstream side and the comparators 36 to 38 on the downstream side. Note that the comparators 36 to 38 are arranged in a second direction (=vertical direction on the paper surface) perpendicular to the first direction.

A signal line extending in the second direction is connected to a connection node between the reception amplifier 3A and the comparators 36 to 38. An analog output signal AO is output via the buffer amplifier 3C connected to this signal line. is output to the outside of the semiconductor integrated circuit device 5 . The buffer amplifier 3C is arranged along the second direction.

The analog output terminals (7 pins) are located on the left side 51 where the analog input terminals (40 pins, 41 pins, 44 pins, and 45 pins) are provided, and on the right side where the digital output terminals (14 pins and 15 pins) are provided. It is preferable to provide it on the lower side 52, which is different from both, instead of 53.

The analog output terminal (pin 7) is preferably provided near the center of the lower side 52, and the analog ground terminal (pin 6) is preferably provided next to it.

<Pin arrangement replacement experiment>
FIG. 3 is a diagram showing the internal structure of a semiconductor integrated circuit device subjected to a pin arrangement replacement experiment. In the semiconductor integrated circuit device 200 of this figure, a terminal T1 corresponds to a first terminal for receiving an external input of an analog input signal AI, and is connected to a semiconductor chip 210 via a wire W1. On the other hand, the terminals T2a and T2b respectively correspond to second terminals for externally outputting the analog output signal AO.

In the pin arrangement exchange experiment, the terminal T2b provided on the same side as the first pin arrangement (=terminal T1) was connected to the analog output pad of the semiconductor chip 210 via the wire W2b. the output signal AO is externally output), and the second pin arrangement (=terminal T2a provided on a side different from terminal T1 is connected to the analog output pad of semiconductor chip 210 via wire W2a, The behavior of the analog output signal AO (=received signal ER) in the reception standby state was measured for each of the cases where the analog output signal AO is externally output from the terminal T2a.

4A and 4B are diagrams showing the results of the pin arrangement permutation experiment. As shown on the left side of the figure, in the first pin arrangement (=when the analog output signal AO is externally output from the terminal T2b provided on the same side as the terminal T1 as in the conventional case), even in the reception standby state, The analog output signal AO (=received signal ER) exceeds the threshold voltage ENVREF, resulting in erroneous detection.

On the other hand, as shown on the right side of the figure, in the second pin arrangement (=when the analog output signal AO is externally output from the terminal T2a provided on the side different from the terminal T1, unlike the conventional case), the gain is high. Even with the setting, the analog output signal AO (=receiving signal ER) does not exceed the threshold voltage ENVREF, and erroneous detection does not occur in the reception standby state.

In order to suppress the interference between the analog inputs and outputs described above, it is important to provide the analog input terminals and the analog output terminals on different sides. This is because when both the analog input terminal and the analog output terminal are provided on the same side, the wires connecting each terminal and the semiconductor chip run in parallel. Therefore, no matter how much the distance between terminals is increased, capacitive coupling between wires cannot be avoided.

On the other hand, if the analog input terminal and the analog output terminal are provided on different sides, the wires connecting each terminal and the semiconductor chip do not run parallel. Specifically, referring to FIG. 3, the angle θ between the terminals T1 and T2a is larger than the angle φ between the terminals T1 and T2b. Therefore, it is possible to weaken the capacitive coupling between wires.

Moreover, in order to further increase the effect of suppressing interference between analog input and output, it is desirable to provide the terminal T2a at a position as far away from the terminal T1 as possible.

<Other pin assignments>
Returning to FIG. 2A, the description of other pin arrangements continues. In a plan view of the package 50, the third terminals (14 pins, 15 pins) functioning as digital output terminals are located on the first side where the first terminals (40 pins, 41 pins, 44 pins, and 45 pins) are provided. It is desirable to provide not on the third side 51 but on the third side 53 opposite thereto.

By adopting such a pin arrangement, the main signal path of the ultrasonic flowmeter 100 becomes straight from the left side to the right side of the paper surface, so that the wiring on the substrate on which the semiconductor integrated circuit device 5 is mounted can be simply laid out It becomes possible to

Further, in this figure, the fourth terminal (8th pin) for externally outputting the threshold voltage ENVREF is provided next to the second terminal (7th pin). It is desirable to provide the fourth terminal at a position adjacent to none of the first terminals (pins 40, 41, 44, and 45) and the second terminal (pin 7).

Furthermore, for the same reason as above, the fourth terminal is not only the first terminal (pins 40, 41, 44 and 45) and the second terminal (pin 7), but also the third terminal (pin 15). ) (at a position as far away from them as possible).

In view of the above, for example, as shown in FIG. 2B, it is desirable to use one of the 25th to 36th pins (for example, 29th pin) as the fourth terminal (=the external output terminal for the threshold voltage ENVREF).

Also, for the same reason as above, it is desirable to provide a buffer amplifier 3E between the threshold voltage generator 3D and the second comparator 37 .

Further, next to the fifth terminals (22nd and 23rd pins, and 10th and 11th pins) for externally connecting the first oscillator 6 and the second oscillator 43 (particularly their respective oscillators), during normal operation, It is desirable to provide test terminals, ground terminals, or unused terminals (the hatched terminals in this figure correspond to these terminals) that are grounded or open.

Adopting such a pin arrangement makes it difficult for noise to be superimposed on the fifth terminal, so that the first oscillator 6 and the second oscillator 43 can be stably operated.

Sixth terminals (pins 1, 12, 13, 24, 25, 36, 37 and , 48 pins) may be the above test terminals, ground terminals, or unused terminals.

By adopting such a pin arrangement, even if a short circuit occurs between the terminals at the four corners of the package 50 when it is mounted on the substrate, the operation of the semiconductor integrated circuit device 5 will not be hindered, so mounting reliability can be improved. can be increased.

<Transmission means>
FIG. 5 is a diagram showing a configuration example of the transmission means 31. As shown in FIG. The transmission means 31 in this configuration example comprise two H-bridge output stages HBR1 and HBR2.

The H-bridge output stage HBR1 is means for outputting a burst wave to the first oscillator 1, and includes P-channel MOS field effect transistors P11 and P12 and N-channel MOS field effect transistors N11 and N12.

Sources of the transistors P11 and P12 are connected to the regulator power supply SWVREG. The drains of transistors P11 and N11 are connected to pin 40 (SNHP). The drains of transistors P12 and N12 are connected to pin 41 (SNHN). The sources of transistors N11 and N12 are connected to pin 42 (VSSHBRDRVH).

The H-bridge output stage HBR2 is means for outputting a burst wave to the second oscillator 2, and includes P-channel MOS field effect transistors P21 and P22 and N-channel MOS field effect transistors N21 and N22.

Sources of the transistors P21 and P22 are connected to the regulator power supply SWVREG. The drains of transistors P21 and N21 are connected to pin 44 (SNLN). The drains of transistors P22 and N22 are connected to pin 45 (SNLP). The sources of transistors N21 and N22 are connected to pin 43 (VSSHBRDRVL).

Thus, in the transmitting means 31, the reference potential lines (GND) of the H-bridge output stages HBR1 and HBR2 are separated from each other by connecting to independent ground terminals (pins 42 and 43).

When the first transducer 1 is used to transmit burst waves, the second transducer 2 is used to receive burst waves. Conversely, when the second transducer 2 is used to transmit burst waves, the first transducer 1 is used to receive burst waves.

Therefore, if the H-bridge output stages HBR1 and HBR2 each have a common reference potential line (GND), if the reference potential on the transmitting side fluctuates due to the transmission operation of the burst wave, Since it fluctuates to the reference potential, it may adversely affect the burst wave receiving operation. On the other hand, if the reference potential lines (GND) of the H-bridge output stages HBR1 and HBR2 are separated from each other, such a problem will not occur.

<Other Modifications>
In the above embodiments, a semiconductor integrated circuit device employing a QFP package was taken as an example, but the type of package is not limited to this, and QFN [Quad Flat Non-leaded Package], QFJ [Quad Flat J-leaded Package], SOP [Small Outline Package], SON [Small Outline Non-leaded Package], SOJ [Small Outline J-leaded Package], or DIP [Dual In-line Package], etc. The previously proposed pin arrangement is effective for a package in which leads are led out from the sides.

In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments. It is to be understood that a range and equivalents are meant to include all changes that fall within the range.

The invention disclosed in this specification can be used, for example, in ultrasonic gas flow measurement systems as well as LSIs and module products that require connection with sensors.

1 first oscillator 2 second oscillator 3 analog section 4 logic section 5 semiconductor integrated circuit device 6 first oscillator (low-speed clock)
7 battery 10 microcomputer 11 cutoff valve 12 seismoscope 13 pressure sensor 14 display means 31 transmission means 32 switching means 33 conversion means 34 first amplification means 35 second amplification means 36 first comparator 37 second comparator 38 third comparator 39 inside Power supply regulator 3A Reception amplifier 3B Bias section 3C Buffer amplifier 3D Threshold voltage generation section 3E Buffer amplifier 40 Control means 42 Transmission/reception direction control means 43 Second oscillator (medium speed clock)
44 first propagation time counter 45 third oscillator (high-speed clock)
46 second propagation time counter 47 error counter 48 microcomputer interface 50 package 51 left side (first side)
52 lower side (second side)
53 right side (third side)
54 Upper side (4th side)
100 Ultrasonic flowmeter 200 Semiconductor integrated circuit device 210 Semiconductor chip HBR1, HBR2 H-bridge output stage P11, P12, P21, P22 P-channel MOS field effect transistor N11, N12, N21, N22 N-channel MOS field effect transistor T1 1 terminal T2a, T2b 2nd terminal W1, W2a, W2b wire

Claims (17)

a first terminal for receiving an external input of an analog input signal;
an amplifier that amplifies the analog input signal to generate an amplified signal;
a logic unit that generates a digital output signal according to the amplified signal;
a second terminal for externally outputting an analog output signal corresponding to the amplified signal;
has
A semiconductor integrated circuit device, wherein the first terminal is provided on a first side of a package, and the second terminal is provided on a second side different from the first side. 2. The semiconductor integrated circuit device according to claim 1, further comprising a third terminal for externally outputting said digital output signal. 3. The semiconductor integrated circuit device according to claim 2, wherein said third terminal is provided on a third side facing said first side. further comprising a fourth terminal for externally outputting a threshold voltage to be compared with the amplified signal;
4. The semiconductor integrated circuit device according to claim 1, wherein said fourth terminal is provided at a position not adjacent to said first terminal and said second terminal. further comprising a fourth terminal for externally outputting a threshold voltage to be compared with the amplified signal;
4. The semiconductor integrated circuit device according to claim 2, wherein said fourth terminal is provided at a position not adjacent to said third terminal. a threshold voltage generator that generates the threshold voltage;
a comparator that generates a comparison signal between the amplified signal and the threshold voltage and outputs the comparison signal to the logic unit;
a buffer amplifier provided between the threshold voltage generator and the comparator;
6. The semiconductor integrated circuit device according to claim 4, further comprising: further comprising a fifth terminal for externally connecting an oscillator;
7. The semiconductor integrated circuit device according to claim 1, wherein a terminal adjacent to said fifth terminal is a test terminal, a ground terminal, or an unused terminal. 8. The semiconductor integrated circuit device according to claim 7, wherein said fifth terminal is provided on one of four sides of said package to which said digital output signal is output. 9. The semiconductor integrated circuit according to claim 1, wherein the sixth terminals provided at the four corners of said package are test terminals, ground terminals, or unused terminals. Device. further comprising a comparator that generates a comparison signal between the amplified signal and a predetermined threshold value and outputs the comparison signal to the logic unit;
The amplifier and the comparator are arranged in a first direction along a signal path from the first terminal to the third terminal, with the amplifier on the upstream side and the comparator on the downstream side. 4. The semiconductor integrated circuit device according to claim 3. 11. The semiconductor integrated circuit device according to claim 10, wherein a plurality of said comparators are arranged in a second direction perpendicular to said first direction. A signal line extending in the second direction is connected to a connection node between the amplifier and the comparator, and the analog output signal is output from the second terminal to the outside via a buffer amplifier connected to the signal line. 12. The semiconductor integrated circuit device according to claim 11, which is output. 13. The semiconductor integrated circuit device according to claim 12, wherein said second terminal is provided near the center of said second side. 14. The semiconductor integrated circuit device according to claim 1, wherein said analog input signal is a signal received by a vibrator externally connected to said first terminal. 15. The semiconductor integrated circuit device according to claim 14, further comprising transmitting means for outputting a burst wave to said oscillator. The transmission means includes a first output stage and a second output stage that output burst waves to a first oscillator and a second oscillator that are externally connected as the oscillators, respectively, and the reference potential line of each output stage is: 16. The semiconductor integrated circuit device according to claim 15, wherein the semiconductor integrated circuit devices are separated from each other. A semiconductor integrated circuit device according to claim 16;
the first oscillator and the second oscillator arranged opposite to each other in the fluid conduit at a predetermined angle with respect to the flow of the fluid;
An ultrasonic flowmeter characterized by comprising:

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