JP7263103B2 - Device - Google Patents

Description

Embodiments of the present invention relate to multi-series unit converter clusters, power converters and reactive power compensators.

A three-phase two-level converter, for example, is used as a power converter that converts AC power to DC power or DC power to AC power. A 3-phase 2-level converter can be configured using six semiconductor switching elements, and can be miniaturized and reduced in cost.

On the other hand, when the input DC voltage is Vdc, the output voltage waveform of the 3-phase 2-level converter is a pseudo voltage waveform that switches between +Vdc/2 and -Vdc/2 by PWM (Pulse Width Modulation) for each phase. AC waveform. Therefore, the output voltage waveform of the 3-phase 2-level converter contains harmonic voltages caused by the switching of the semiconductor switching elements.

A method has been proposed for reducing harmonic components caused by switching by inserting a filter composed of a reactor and a capacitor at the output end of a three-phase two-level converter. However, in order to reduce the harmonic components that flow into the power system to a level that does not adversely affect other devices, it is necessary to use a large-capacity filter, which increases the cost and weight of the power converter. rice field.

Also, in order to reduce the size of the filter, it is being studied to increase the switching frequency of the semiconductor switching element. However, if the switching frequency of the semiconductor switching element is increased, energy loss due to switching increases, power loss increases, and it becomes necessary to improve the cooling performance of the power converter. For example, when the power converter is used in an environment where it is difficult to install a cooling fan, such as outdoors, the size of the cooling unit is increased.

On the other hand, like a modular multi-level converter, research and development of a power converter capable of converting a high voltage equivalent to the power system and distribution system voltage by connecting unit converters in multiple stages is also underway. When modular multi-level converters are put to practical use, the output voltage and current waveforms become closer to sinusoidal waves due to the multi-level conversion, and the advantage of eliminating the need for harmonic filters can be enjoyed. Furthermore, by staggering the switching timing of each unit converter, it is possible to achieve an output voltage and current containing similar harmonic components at a lower switching frequency, thus reducing switching loss. Become.

Japanese Patent Application Laid-Open No. 2017-212828

Each unit converter that constitutes a modular multi-level converter has a capacitor, and it is necessary to control all capacitor voltages to appropriate voltages. Therefore, the capacitor voltage is detected by a voltage detector provided for each unit converter, and the detection signal is fed back to control to finely adjust the gate signal of each unit converter. Therefore, the control circuit needs to perform feedback control for as many unit converters as there are unit converters. An increase in the amount of data causes a reduction in the calculation cycle. In addition, fine tuning of the gate signal to control the capacitor voltage has also resulted in increased harmonics.

The embodiments of the present invention have been made in view of the above circumstances, and it is an object of the present invention to provide a compact multi-series unit converter cluster, a power converter, and a reactive power compensator that are low in cost and have few harmonics. and

A device according to an embodiment includes a control unit that outputs a plurality of gate signals, a first switching element, a second switching element whose drain is connected to the source of the first switching element, and a a capacitor connected between the drain and the source of the second switching element, and first to N-th unit converters connected in series, and n is any one from 1 to (N-1) and between the drain of the first switching element of the n-th unit converter and the capacitor, and between the drain of the first switching element and the capacitor of the (n+1)-th unit converter, when taken as integers. , and provided for at least one of the first to N-th unit converters, and the first to (N-1)th balance circuits provided with balance switching elements provided in the paths connecting the and a voltage detector for detecting the voltage of the capacitor, wherein the n-th unit converter comprises the source of the first switching element and the drain of the second switching element of the (n+1)-th unit converter. is electrically connected to the (n+1)-th unit converter between and the control unit selects, among a plurality of output gate signals, the second switching element of the (n+1)-th unit converter A gate signal and a gate signal of the balance switching element of the n-th balance circuit are used as a common signal.

FIG. 1 is a diagram schematically showing one configuration example of a power converter according to a first embodiment. FIG. 2 is a diagram schematically showing one configuration example of an arm of the power converter shown in FIG. FIG. 3 is a diagram for explaining an example of the motion of the arm shown in FIG. 2; FIG. 4 is a diagram for explaining an example of the relationship between the time constant and the period during which the balance switch of the balance circuit of the power converter according to the embodiment is turned on. FIG. 5 is a block diagram for explaining a configuration example of a control circuit of the power converter shown in FIG. 1. As shown in FIG. FIG. 6 is a diagram schematically showing a modification of the power conversion device of the first embodiment. FIG. 7 is a diagram schematically showing a modification of the power converter of the first embodiment. FIG. 8 is a diagram schematically showing one configuration example of an arm of the power converter of the second embodiment. FIG. 9 is a diagram for explaining an example of the motion of the arm shown in FIG. 6; FIG. 10 is a diagram schematically showing one configuration example of the power converter of the third embodiment. FIG. 11 is a block diagram schematically showing one configuration example of the control circuit of the power converter of the third embodiment. FIG. 12 is a diagram schematically showing one configuration example of a reactive power compensator according to the fourth embodiment. 13 is a diagram schematically showing a configuration example of each phase arm of the reactive power compensator shown in FIG. 12. FIG. 14 is a diagram for explaining an example of the motion of the arm shown in FIG. 13; FIG. 15 is a block diagram for explaining a configuration example of a control circuit of the reactive power compensator shown in FIG. 12. FIG. 16 is a block diagram for explaining a configuration example of a delay circuit of a control circuit of the reactive power compensator shown in FIG. 15. FIG. 17 is a diagram for explaining an example of the operation of the control circuit of the reactive power compensator shown in FIGS. 15 and 16. FIG. 18 is a block diagram for explaining another configuration example of the control circuit of the reactive power compensator shown in FIG. 12. FIG. 19 is a diagram for explaining an example of the operation of the control circuit of the reactive power compensator shown in FIG. 18. FIG. FIG. 20 is a diagram schematically showing one configuration example of an arm of the reactive power compensator of the fifth embodiment. 21 is a diagram for explaining an example of the motion of the arm shown in FIG. 20; FIG. FIG. 22 is a diagram schematically showing another configuration example of the reactive power compensator of the embodiment; 23 is a diagram schematically showing another configuration example of the arm of the power converter shown in FIG. 1. FIG.

Hereinafter, power converters according to embodiments will be described in detail with reference to the drawings.
FIG. 1 is a diagram schematically showing one configuration example of a power converter according to a first embodiment.
The power converter 20 of the present embodiment is connected between a three-phase AC power supply (or AC load) 10 and a DC power supply (or DC load) (not shown). The AC power supply 10 is, for example, a commercial power supply. The DC power supply includes, for example, a photovoltaic power generation system, a DC power supply such as a UPS (Uninterruptible Power Supply), a battery, and other power converters.

The power converter 20 includes AC terminals UT, VT, WT, a DC positive terminal PT, a DC negative terminal MT, a control circuit CTR, a U-phase positive arm 30U, a U-phase negative arm 30X, a V-phase It has a positive arm 30V, a V-phase negative arm 30Y, a W-phase positive arm 30W, a W-phase negative arm 30Z, and reactors LU to LZ.

AC terminals UT, VT, and WT are electrically connected to a three-phase AC power supply 10 . DC positive terminal PT and DC negative terminal MT are electrically connected to a DC power supply (not shown).

One end (low potential side end) of U-phase positive arm 30U is electrically connected to AC terminal UT via reactor LU. The other end (high potential side end) of U-phase positive arm 30U is electrically connected to DC positive terminal PT.
One end (high potential side end) of the U-phase negative arm 30X is electrically connected to an AC terminal UT via a reactor LX. The other end (low potential side end) of U-phase negative arm 30X is electrically connected to DC negative terminal MT.

One end (low potential side end) of the V-phase positive arm 30V is electrically connected to the AC terminal VT via a reactor LV. The other end (high potential side end) of the V-phase positive arm 30V is electrically connected to the DC positive terminal PT.
One end (high potential side end) of the V-phase negative arm 30Y is electrically connected to the AC terminal VT via the reactor LY. The other end (low potential side end) of the V-phase negative arm 30Y is electrically connected to the DC negative terminal MT.

One end (low potential side end) of the W-phase positive arm 30W is electrically connected to an AC terminal WT via a reactor LW. The other end (high potential side end) of the W-phase positive arm 30W is electrically connected to the DC positive terminal PT.
One end (high potential side end) of the W-phase negative arm 30Z is electrically connected to an AC terminal WT via a reactor LXZ. The other end (low potential side end) of the W-phase negative arm 30Z is electrically connected to the DC negative terminal MT.

The control circuit CTR controls the operation of the power conversion device 20 based on command values supplied from the outside and various detection values detected by the power conversion device 20 . The control circuit CTR may be, for example, an FPGA (Field Programmable Gate Array), and stores at least one processor such as a CPU (central processing unit) or MPU (micro processing unit) and a program executed by the processor. and a memory.

FIG. 2 is a diagram schematically showing one configuration example of an arm of the power converter shown in FIG.
Here, as an example, a configuration of one positive side arm or one negative side arm for each UVW phase is shown, and the configuration will be described as an arm (multi-series unit converter cluster) 30 .

Arm 30 comprises three unit converters 31-33 and balance circuits B12, B23.
When N is a positive integer, the N-th unit converter includes a first _N- switching element Q1p and a second _N- switching element Q1n whose drain (D) is connected to the source (S) of the first _N- switching element Q1p. , and an Nth capacitor C connected between the drain (D) of the first _N switching element Q1p and the source (S) of the second _N switching element Q1n.
When N is n, the nth unit converter is electrically connected to the (n+1)th unit converter between the source of the 1n switching element Q1p and the drain of the 2nth switching element Q1n.
FIG. 2 shows an example of the configuration of the unit converter cluster when N≦3, where the unit converter 33 is the first unit converter, the unit converter 32 is the second unit converter, and the unit converter 31 is the second unit converter. Equivalent to a 3-unit converter.
The unit converters 31-33 are connected in series between the DC positive terminal PT or the DC negative terminal MT and the AC terminals UT, VT, WT. In the positive arm, one end (high potential side end) of the unit converter 31 is electrically connected to the DC positive terminal PT, and the other end (low potential side end) is one end (high potential side end) of the unit converter 32. is electrically connected to One end (high potential side end) of the unit converter 33 is electrically connected to the other end (low potential side end) of the unit converter 32, and the other end (low potential side end) of the unit converter 33 is connected to the reactor LU, It is electrically connected to one of the AC terminals UT, VT, WT via one of LX and LZ.
In the negative arm, one end (high potential side end) of the unit converter 31 is electrically connected to any one of the AC terminals UT, VT, and WT via any one of the reactors LX, LY, and LZ, and the other end ( low potential side end) is electrically connected to one end (high potential side end) of the unit converter 32 . One end (high potential side end) of the unit converter 33 is electrically connected to the other end (low potential side end) of the unit converter 32, and the other end (low potential side end) of the unit converter 33 is a DC negative terminal. It is electrically connected with MT.

The unit converter 31 includes a switching element (first switching element) Q1p, a switching element (second switching element) Q1n, a capacitor C1, a voltage detector SV for detecting the voltage of the capacitor C1, and a drive circuit (first A drive circuit) DV1p, a drive circuit (second drive circuit) DV1n, an isolation circuit (first isolation circuit) 311, and a power supply circuit 331 are provided.

The switching element Q1p and the switching element Q1n are connected in series, and are electrically connected to the DC positive terminal PT or the DC negative terminal MT between the switching element Q1p and the switching element Q1n. It is electrically connected with the converter 32 .

The switching elements Q1p and Q1n are provided with self-extinguishing switching elements such as MOSFETs (metal-oxide semiconductor field-effect transistors). Self-arc-extinguishing switching elements are, for example, IEGT (injection enhanced gate transistor), GTO (gate turn-off thyristor), GCT (gate communicated turn-off thyristor), or IGBT (Insulated Gate Bipolar Transistor). It is possible to employ a switching element that can be electrically controlled to be on (conducting state) and off (non-conducting state). The switching elements Q1p and Q1n may include free wheel diodes connected in anti-parallel to the switching elements, if necessary. The switching elements Q1p and Q1n are controlled in operation by drive signals from drive circuits DV1p and DV1n.
When IGBTs or IEGTs are used as the switching elements Q1p and Q1n, the sources of the switching elements Q1p and Q1n are read as emitters, and the drains of the switching elements Q1p and Q1n are read as collectors.

One end (high potential side end) of the capacitor C1 is electrically connected to the drain of the switching element Q1p, and the other end (low potential side end) of the capacitor C1 is electrically connected to the source of the switching element Q1n. The source (low potential side end) of the switching element Q1p is electrically connected to the drain of the switching element Q1n.

The voltage detector SV detects the voltage of the capacitor C1 and outputs the detected voltage value (or the value corresponding to the voltage) to the control circuit CTR.
The power supply circuit 331 generates power using the voltage of the capacitor C1. The power supply circuit 331 supplies power to the isolation circuit 311, the drive circuit DVn, and the balance circuit B12. In this embodiment, the power supply circuit 331 generates power using the voltage of the capacitor C1. good too.

The isolation circuit 311 isolates the power supply circuit 331 and the drive circuit DV1p. The power supply circuit 331 and the drive circuit DV1p operate at different reference potentials. Isolation circuit 311 is, for example, a bootstrap circuit.
The drive circuit DV1p operates by being supplied with the power supply voltage through the isolation circuit 311, and drives the switching element Q1p based on the gate signal supplied from the control circuit CTR.
The drive circuit DV1n operates by being supplied with a power supply voltage from the power supply circuit 331, and drives the switching element Q1n based on the gate signal supplied from the control circuit CTR.

The unit converters 32 and 33 have the same configuration as the above-described unit converter 31 except that they do not have the voltage detector SV.
That is, the unit converter 32 includes a switching element (first switching element) Q2p, a switching element (second switching element) Q2n, a capacitor C2, a driving circuit (first driving circuit) DV2p, and a driving circuit (second drive circuit) DV2n, an isolation circuit (first isolation circuit) 312, and a power supply circuit 332.
In addition to the voltage detector SV, each of the unit converters 31-33 includes a circuit (not shown) that compares the voltage of the capacitors C1-C3 with a threshold value to detect overvoltage. Safety is ensured even if the voltage detector is omitted in -33.

The switching element Q2p and the switching element Q2n are connected in series, and between the switching element Q2p and the switching element Q2n of the unit converter (first unit converter) 32, the It is electrically connected to the drain of switching element Q1n and the source of capacitor C1. The source of switching element Q2n is electrically connected to unit converter 33 .

The switching elements Q2p and Q2n are provided with self-extinguishing switching elements such as MOSFETs (metal-oxide semiconductor field-effect transistors). Self-arc-extinguishing switching elements are, for example, IEGT (injection enhanced gate transistor), GTO (gate turn-off thyristor), GCT (gate communicated turn-off thyristor), or IGBT (Insulated Gate Bipolar Transistor). It is possible to employ a switching element that can be electrically controlled to be on (conducting state) and off (non-conducting state). The switching elements Q2p and Q2n may include free wheel diodes connected in anti-parallel to the switching elements, if necessary. The switching elements Q2p and Q2n are controlled in operation by drive signals from drive circuits DV1p and DV1n.
When IGBTs or IEGTs are used as the switching elements Q2p and Q2n, the sources of the switching elements Q2p and Q2n are read as emitters, and the drains of the switching elements Q2p and Q2n are read as collectors.

One end (high potential side end) of the capacitor C2 is electrically connected to the drain of the switching element Q2p, and the other end (low potential side end) of the capacitor C2 is electrically connected to the source of the switching element Q2n. The source of switching element Q2p is electrically connected to the drain of switching element Q2n.

The power supply circuit 332 generates power using the voltage of the capacitor C2. The power supply circuit 332 supplies power to the isolation circuit 312, the drive circuit DV2n, and the balance circuit B23. In this embodiment, the power supply circuit 332 generates power using the voltage of the capacitor C2. good too.

The isolation circuit 312 isolates the power supply circuit 332 and the drive circuit DV2p. The power supply circuit 332 and the drive circuit DV2p operate at different reference potentials. Isolation circuit 312 is, for example, a bootstrap circuit.
The drive circuit DV2p operates by being supplied with the power supply voltage through the isolation circuit 312, and drives the switching element Q2p based on the gate signal supplied from the control circuit CTR.
The drive circuit DV2n operates by being supplied with the power supply voltage from the power supply circuit 332, and drives the switching element Q2n based on the gate signal supplied from the control circuit CTR.

The unit converter 33 includes a switching element (first switching element) Q3p, a switching element (second switching element) Q3n, a capacitor C3, a driving circuit (first driving circuit) DV3p, a driving circuit (second driving circuit ) DV 3 n , an isolation circuit (first isolation circuit) 313 , and a power supply circuit 333 .
The switching element Q3p and the switching element Q3n are connected in series, and between the switching element Q3p and the switching element Q3n of the unit converter (first unit converter) 33, the It is electrically connected to the source of switching element Q2n and the other end (low potential side end) of capacitor C2. The source of switching element Q3n is electrically connected to one of AC terminals UT, VT, and WT.

The switching elements Q3p and Q3n are provided with self-extinguishing switching elements such as MOSFETs (metal-oxide semiconductor field-effect transistors). Self-arc-extinguishing switching elements are, for example, IEGT (injection enhanced gate transistor), GTO (gate turn-off thyristor), GCT (gate communicated turn-off thyristor), or IGBT (Insulated Gate Bipolar Transistor). It is possible to employ a switching element that can be electrically controlled to be on (conducting state) and off (non-conducting state). The switching elements Q3p and Q3n may include free wheel diodes connected in anti-parallel to the switching elements, if necessary. The switching elements Q3p and Q3n have their operations controlled by drive signals from the drive circuits DV1p and DV1n.
When IGBTs or IEGTs are used as the switching elements Q3p and Q3n, the sources of the switching elements Q3p and Q3n are read as emitters, and the drains of the switching elements Q3p and Q3n are read as collectors.

One end (high potential side end) of the capacitor C3 is electrically connected to the drain of the switching element Q3p, and the other end (low potential side end) of the capacitor C3 is electrically connected to the source of the switching element Q3n. The source of switching element Q3p is electrically connected to the drain of switching element Q3n.

The power supply circuit 333 generates power using the voltage of the capacitor C3. The power supply circuit 333 supplies power to the isolation circuit 313 and the drive circuit DV3n. In this embodiment, the power supply circuit 333 generates power using the voltage of the capacitor C3, but power may be supplied to the power supply circuit 333 from the outside. good too.

The isolation circuit 313 isolates the power supply circuit 333 and the drive circuit DV3p. The power supply circuit 333 and the drive circuit DV3p operate at different reference potentials. Isolation circuit 313 is, for example, a bootstrap circuit.
The drive circuit DV3p operates by being supplied with the power supply voltage through the isolation circuit 313, and drives the switching element Q3p based on the gate signal supplied from the control circuit CTR.
The drive circuit DV3n operates by being supplied with the power supply voltage from the power supply circuit 333, and drives the switching element Q3n based on the gate signal supplied from the control circuit CTR.

The balance circuit B12 includes a balance switching element Q12b, a drive circuit (balance switch drive circuit) DV12b, and an insulation circuit (second insulation circuit) 321.
The balance switching element Q12b includes a self-arc-extinguishing switching element such as a MOSFET (metal-oxide semiconductor field-effect transistor). Examples of self arc-extinguishing switching elements include IEGT (injection enhanced gate transistor), GTO (gate turn-off thyristor), GCT (gate communicated turn-off thyristor), MOSFET (metal-oxide semiconductor field-effect transistor), Alternatively, a switching element such as an IGBT (Insulated Gate Bipolar Transistor) capable of electrically controlling ON (conducting state) and OFF (non-conducting state) of the element can be employed. The balance switching element Q12b may include a freewheeling diode connected in anti-parallel to the switching element, if necessary.
When an IGBT or an IEGT is used as the balance switching element Q12b, the source of the balance switching element Q12b is read as the emitter, and the drain of the balance switching element Q12b is read as the collector.

The drain of the balance switching element Q12b is electrically connected to one end (high potential side end) of the capacitor C1 of the unit converter 31 and the drain of the first switching element Q1p. The source of the balance switching element Q12b is electrically connected to one end (high potential side end) of the capacitor C2 of the unit converter 32 and the drain of the first switching element Q1p.
That is, the balance switching element Q12b electrically connects the unit converter (first unit converter) 32 and the unit converter (second unit converter) 31 between the capacitor and the drain of the first switching element. It is provided on the connecting route.
Therefore, when the balance switching element Q12b is turned on (conducted), one end (high potential side end) of the capacitor C1 and one end (high potential side end) of the capacitor C2 are electrically connected.

The isolation circuit 321 isolates the power supply circuit 331 and the drive circuit DV12b. The power supply circuit 331 and the drive circuit DV12b operate at different reference potentials. Isolation circuit 321 is, for example, a bootstrap circuit. The drive circuit DV12b operates by being supplied with the power supply voltage through the isolation circuit 321, and drives the balance switching element Q12b based on the gate signal supplied from the control circuit CTR.

In this embodiment, the gate signal of the balance switching element Q12b is common to the switching element Q2n of the unit converter 32. FIG. That is, the gate signal input to the drive circuit DV12b and the gate signal input to the drive circuit DV2n are common. Therefore, the switching element Q2n and the balance switching element Q12b are conducted (turned on) at the same timing, and the capacitors C1 and C2 are connected in parallel. As a result, the voltages of the capacitors C1 and C2 become substantially equal.

The balance circuit B23 includes a balance switching element Q23b, a drive circuit (balance switch drive circuit) DV23b, and an insulation circuit (second insulation circuit) 322.
The balance switching element Q23b includes a self arc-extinguishing switching element such as a MOSFET (metal-oxide semiconductor field-effect transistor). Self-arc-extinguishing switching elements are, for example, IEGT (injection enhanced gate transistor), GTO (gate turn-off thyristor), GCT (gate communicated turn-off thyristor), or IGBT (Insulated Gate Bipolar Transistor). It is possible to employ a switching element that can be electrically controlled to be on (conducting state) and off (non-conducting state). The balance switching element Q23b may include a free wheel diode connected in anti-parallel to the switching element, if necessary.
When an IGBT or IEGT is used as the balance switching element Q23b, the source of the balance switching element Q23b is read as the emitter, and the drain of the balance switching element Q23b is read as the collector.

The drain of the balance switching element Q23b is electrically connected to one end (high potential side end) of the capacitor C2 of the unit converter 32 and the drain of the first switching element Q2p. The source of the balance switching element Q23b is electrically connected to one end (high potential side end) of the capacitor C3 of the unit converter 33 and the drain of the first switching element Q3p.
That is, the balance switching element Q23b electrically connects the unit converter (first unit converter) 33 and the unit converter (second unit converter) 32 between the capacitor and the drain of the first switching element. It is provided on the connecting route.
Therefore, when the balance switching element Q23b is turned on (conducted), one end (high potential side end) of the capacitor C2 and one end (high potential side end) of the capacitor C3 are electrically connected.

The isolation circuit 322 isolates the power supply circuit 332 and the drive circuit DV23b. The power supply circuit 332 and the drive circuit DV23b operate at different reference potentials. Isolation circuit 322 is, for example, a bootstrap circuit.
The drive circuit DV23b operates by being supplied with the power supply voltage through the isolation circuit 322, and drives the balance switching element Q23b based on the gate signal supplied from the control circuit CTR.

In this embodiment, the gate signal of the balance switching element Q23b is common to the switching element Q3n of the unit converter 33. FIG. That is, the gate signal input to the drive circuit DV23b and the gate signal input to the drive circuit DV3n are common. Therefore, the switching element Q3n and the balance switching element Q23b are conducted (turned on) at the same timing, and the capacitors C2 and C3 are connected in parallel. As a result, the voltages of the capacitors C2 and C3 become substantially equal.

FIG. 3 is a diagram for explaining an example of the motion of the arm shown in FIG. 2;
Here, for example, when the voltage of the capacitors C1-C3 is Vc, the output voltage Vout of the AC terminals UT, VT, WT is 3 times, 2 times, 1 time and zero of the voltage Vc. 31-33 of switching elements Q1p-Q3n and switching elements Q12b and Q23b of balance circuits B12 and B23 are shown in the conducting state. In FIG. 3, "1" indicates the state in which the switching element is conducting (ON state), and "0" indicates the state in which the switching element is not conducting (OFF state).

For example, when the output voltage is three times the voltage Vc, the switching element Q1p is on, the switching element Q1n is off, the switching element Q2p is on, the switching element Q2n is off, the switching element Q3p is on, and the switching element Q3n is off. Become. At this time, the switching element Q12b is turned off, the balance switching element Q23b is turned off, and the capacitors C1 to C3 are not connected to each other.

For example, when the output voltage is double the voltage Vc, the switching element Q1p is turned off, the switching element Q1n is turned on, the switching element Q2p is turned on, the switching element Q2n is turned off, the switching element Q3p is turned on, and the switching element Q3n is turned off. Become. At this time, the switching element Q12b is turned off, the balance switching element Q23b is turned off, and the capacitors C1 to C3 are not connected to each other.

For example, when the output voltage is 1 times the voltage Vc, the switching element Q1p is turned off, the switching element Q1n is turned on, the switching element Q2p is turned off, the switching element Q2n is turned on, the switching element Q3p is turned on, and the switching element Q3n is turned off. Become. At this time, the switching element Q12b is turned on, the balance switching element Q23b is turned off, the capacitors C1 and C2 are connected in parallel, and the capacitor C3 is not connected to the other capacitors C1 and C2. .

For example, when the output voltage becomes zero, the switching element Q1p is turned off, the switching element Q1n is turned on, the switching element Q2p is turned off, the switching element Q2n is turned on, the switching element Q3p is turned off, and the switching element Q3n is turned on. At this time, the switching element Q12b is turned on, the balance switching element Q23b is turned on, and the capacitor C1, the capacitor C2, and the capacitor C3 are connected in parallel.

As described above, when the output of the arm 30 is switched, the connection state of the capacitors C1-C3 is also switched, so that the voltages of the capacitors C1-C3 can be equalized at the same time that the power converter performs normal operation. Therefore, by obtaining the voltage of any one of the capacitors C1 to C3, the voltage value of the capacitors C1 to C3 can be controlled. - Eliminates the need for special control to equalize the voltages of C3.

FIG. 4 is a diagram for explaining an example of the relationship between the time constant and the period during which the balance switch of the balance circuit of the power converter according to the embodiment is turned on.
Here, for example, the period during which the balance switching element Q12b is turned on (on period) is Ton, the on period Ton, the total resistance in the circuit in which the capacitors of the unit converters are connected in parallel, and the total capacity of the capacitors of the unit converters 4 shows an example of changes in the balance current due to the relationship with the time constant τ caused by .

For example, when the time constant τ is smaller than the ON period Ton, a large balance current (current flowing between capacitors connected in parallel) flows when the balance switching element Q12b is turned ON, and the time constant τ is smaller than the ON period Ton. As τ becomes larger, the balance current changes less when the balance switching element Q12b is on.

For example, a large current flows through the circuit, causing an excessive loss, which causes malfunction of the elements that make up the circuit. Therefore, the period Ton during which the balance switching elements Q12b and Q23b are turned on must be smaller than the time constant τ. (Ton<τ) is desirable. This makes it possible to avoid failure of the unit converters 31-33.

FIG. 5 is a block diagram for explaining a configuration example of a control circuit of the power converter shown in FIG. 1. As shown in FIG. Here, a configuration example of the control circuit CTR when each of the positive side arm and the negative side arm of each phase is provided with N stages of unit converters is schematically shown.

The control circuit CTR includes a capacitor voltage average value control unit 41, a capacitor voltage balance control unit 42, a current control unit 43, subtractors 44U to 44W, adders 45X to 45Z, and PWM processing units 46U to 46W, 46X. ~46Z, and

The capacitor voltage average value control unit 41 uses the externally supplied cell capacitor voltage command value and the capacitor voltage value (or voltage equivalent) detected by at least one of the unit converters 31 to 33 of each phase arm 30. value) and The capacitor voltage average value control unit 41 calculates the average value of the received capacitor voltage values and outputs a control amount that makes the difference between the calculated average value and the cell capacitor voltage command value zero. Note that the capacitor voltage average value control section 41 may include, for example, a proportional control circuit or a proportional integral control circuit.

The capacitor voltage balance control unit 42 receives the capacitor voltage value (or voltage equivalent value) detected by at least one of the unit converters 31 to 33 of each phase arm 30, and calculates the received six capacitor voltage values. are substantially equal to each other. For example, the average value of the received six capacitor voltage values may be calculated, and the control amount may be calculated so that the difference between the average value and each capacitor voltage value becomes zero. Alternatively, the control amount may be calculated so that the difference between any one of the six capacitor voltage values and the other capacitor voltage values becomes zero. Note that the capacitor voltage balance control unit 42 may include, for example, a proportional control circuit or a proportional integral control circuit.

The current control unit 43 receives, for example, the system voltage value, the reactive power command value, and the active power command value from the outside, and receives the control amount output from the capacitor voltage average value control unit 41 . The current control unit 43 uses the system voltage value and the control amount from the capacitor voltage average value control unit 41 to calculate the control amount of each phase so as to realize the input reactive power command value and active power command value. and output.

Subtractor 44U calculates the difference obtained by subtracting the U-phase control amount output from current control unit 43 from the control amount output from capacitor voltage balance control unit 42, and applies the calculation result to the U-phase positive arm. Output as a voltage command value.
The subtractor 44V calculates the difference obtained by subtracting the V-phase control amount output from the current control unit 43 from the control amount output from the capacitor voltage balance control unit 42, and applies the calculation result to the V-phase positive arm. Output as a voltage command value.
The subtractor 44W calculates the difference obtained by subtracting the W-phase control amount output from the current control unit 43 from the control amount output from the capacitor voltage balance control unit 42, and applies the calculation result to the W-phase positive arm. Output as a voltage command value.

The adder 45X calculates the sum of the control amount output from the capacitor voltage balance control section 42 and the U-phase control amount output from the current control section 43, and outputs the calculation result to the U-phase negative side arm. output as the voltage command value of
The adder 45Y calculates the sum of the control amount output from the capacitor voltage balance control section 42 and the V-phase control amount output from the current control section 43, and outputs the calculation result to the V-phase negative side arm. output as the voltage command value of
The adder 45Z calculates the sum of the control amount output from the capacitor voltage balance control section 42 and the W-phase control amount output from the current control section 43, and outputs the calculation result to the W-phase negative side arm. output as the voltage command value of

PWM processing unit 46U receives the voltage command value for the U-phase positive arm from subtractor 44U, and generates and outputs gate signals for the switching elements of the N-stage unit converters of the U-phase positive arm. The PWM processing unit 46U can generate a gate signal by comparing the voltage command value and the value of the carrier wave, for example, using the carrier wave corresponding to each of the N-stage unit converters. For example, phase-shifted PWM may be applied.

The PWM processing unit 46V receives the voltage command value of the V-phase positive arm from the subtractor 44V, and generates and outputs gate signals for switching elements of the N-stage unit converters of the V-phase positive arm. The PWM processing unit 46V can generate a gate signal by comparing a voltage command value and a carrier wave value, for example, using a carrier wave corresponding to each of the N-stage unit converters.

The PWM processing unit 46W receives the voltage command value for the W-phase positive arm from the subtractor 44W, and generates and outputs gate signals for the switching elements of the N-stage unit converters of the W-phase positive arm. The PWM processing unit 46W can generate a gate signal by comparing a voltage command value and a carrier wave value, for example, using a carrier wave corresponding to each of the N-stage unit converters.

The PWM processing unit 46X receives the voltage command value for the U-phase negative arm from the adder 45X, and generates and outputs gate signals for the switching elements of the N-stage unit converters of the U-phase negative arm. The PWM processing unit 46X can generate a gate signal by comparing the voltage command value and the carrier wave value, for example, using the carrier wave corresponding to each of the N-stage unit converters.

The PWM processing unit 46Y receives the voltage command value of the V-phase negative arm from the adder 45Y, and generates and outputs gate signals for the switching elements of the N-stage unit converters of the V-phase negative arm. The PWM processing unit 46Y can generate a gate signal by comparing a voltage command value and a carrier wave value, for example, using a carrier wave corresponding to each of the N-stage unit converters.

The PWM processing unit 46Z receives the voltage command value of the W-phase negative arm from the adder 45Z, and generates and outputs gate signals for the switching elements of the N-stage unit converters of the W-phase negative arm. The PWM processing unit 46Z can generate a gate signal by comparing the voltage command value and the value of the carrier wave, for example, using the carrier wave corresponding to each of the N-stage unit converters.
A gate signal output from the control circuit CTR is input to a drive circuit that drives the switching element and the balance switching element of the corresponding unit converter.

According to the power converter 20 of the present embodiment, each arm 30 includes the balance circuits B12 and B23, and the balance switching elements of the balance circuits B12 and B23 in each arm 30 operate in synchronization with the switching elements of the unit converters. , it is possible to equalize the capacities of the unit converter capacitors in the arm 30 . This configuration eliminates the need to detect all the voltages of the capacitors of the unit converters included in the power converter 20 and control the individual voltages, and eliminates the need for detectors for detecting the voltages of the capacitors for each unit converter. At the same time, the amount of calculation in the control circuit CTR can be reduced. That is, according to the present embodiment, it is possible to provide a compact multi-serial unit converter cluster and a power converter that are low in cost and have few harmonics.

FIG. 6 is a diagram schematically showing a modification of the power conversion device of the first embodiment.
In this example, balance circuits B12, B23 comprise resistors R12, R23 connected in series with balance switching elements Q12b, Q23b.

When balance switching element Q12b and switching element Q2n become conductive, capacitor C1 and capacitor C2 are connected in parallel via resistor R12.
When balance switching element Q23b and switching element Q3n become conductive, capacitor C2 and capacitor C3 are connected in parallel via resistor R23.

Even when the balance circuits B12 and B23 include the resistors R12 and R23 as described above, the same effects as those of the first embodiment can be obtained.

FIG. 7 is a diagram schematically showing a modification of the power converter of the first embodiment.
In this example, balance circuits B12 and B23 have reactors L12 and L23 connected in series with balance switching elements Q12b and Q23b.

When balance switching element Q12b and switching element Q2n become conductive, capacitor C1 and capacitor C2 are connected in parallel via reactor L12.
When balance switching element Q23b and switching element Q3n become conductive, capacitor C2 and capacitor C3 are connected in parallel via reactor L23.

Even if the balance circuits B12 and B23 are provided with the reactors L12 and L23 as described above, the same effects as those of the above-described first embodiment can be obtained.

Next, the power conversion device of the second embodiment will be described in detail with reference to the drawings.
In addition, in the following description, the same reference numerals are given to the same configurations as in the above-described first embodiment, and the description thereof will be omitted.

FIG. 8 is a diagram schematically showing one configuration example of an arm of the power converter of the second embodiment.
The power conversion device 20 of this embodiment differs from that of the above-described first embodiment in the configuration of unit converters 31-33 and balance circuits B12 and B23.
FIG. 8 shows an example of the configuration of the unit converter cluster when N≦3, where the unit converter 31 is the first unit converter, the unit converter 32 is the second unit converter, and the unit converter 33 is the second unit converter. Equivalent to a 3-unit converter.

The unit converters 31-33 are connected in series between the DC positive terminal PT or the DC negative terminal MT and the AC terminals UT, VT, WT. One end (high potential side end) of the unit converter 31 is electrically connected to the DC positive terminal PT or the DC negative terminal MT, and the other end (low potential side end) of the unit converter 31 is one end of the unit converter 32. (high potential side end). One end (high potential side end) of the unit converter 33 is electrically connected to the other end (low potential side end) of the unit converter 32, and the other end (low potential side end) of the unit converter 33 is connected to the AC terminal. It is electrically connected with either.

The unit converter 31 includes switching elements Q1p and Q1n, a capacitor C1, a voltage detector SV that detects the voltage of the capacitor C1, drive circuits DV1p and DV1n, an isolation circuit 311, and a power supply circuit 331. there is

The switching element Q1p and the switching element Q1n are connected in series, and between the switching element Q1p and the switching element Q1n of the unit converter (first unit converter) 31, the unit converter (second unit converter) 32 and The drain of the switching element Q1p is electrically connected to the DC positive terminal PT or the DC negative terminal MT. The switching elements Q1p and Q1n are controlled in operation by drive signals from drive circuits DV1p and DV1n.

One end (high potential side end) of the capacitor C1 is electrically connected to the drain of the switching element Q1p, and the other end (low potential side end) of the capacitor C1 is electrically connected to the source of the switching element Q1n. The source of switching element Q1p is electrically connected to the drain of switching element Q1n.

The voltage detector SV detects the voltage of the capacitor C1 and outputs the detected voltage value (or the value corresponding to the voltage) to the control circuit CTR.
The power supply circuit 331 generates power using the voltage of the capacitor C1. Power supply circuit 331 supplies power to isolation circuit 311 and drive circuit DVn.

The isolation circuit 311 isolates the power supply circuit 331 and the drive circuit DV1p. The power supply circuit 331 and the drive circuit DV1p operate at different reference potentials. Isolation circuit 311 is, for example, a bootstrap circuit.
The drive circuit DV1p operates by being supplied with the power supply voltage through the isolation circuit 311, and drives the switching element Q1p based on the gate signal supplied from the control circuit CTR.
The drive circuit DV1n operates by being supplied with a power supply voltage from the power supply circuit 331, and drives the switching element Q1n based on the gate signal supplied from the control circuit CTR.

The unit converter 32 includes switching elements Q2p and Q2n, a capacitor C2, drive circuits DV2p and DV2n, an isolation circuit 312, and a power supply circuit 332.
The switching element Q2p and the switching element Q2n are connected in series. The drain of the switching element Q2p is electrically connected to the source of the switching element Q1p of the unit converter 31 and the drain of the switching element Q1n. The source of switching element Q2p and the drain of switching element Q2n are electrically connected to the drain of switching element Q3 of unit converter 33 and one end (high potential side end) of capacitor C3. The switching elements Q2p and Q2n are controlled in operation by drive signals from drive circuits DV2p and DV2n.

One end (high potential side end) of the capacitor C2 is electrically connected to the drain of the switching element Q2p, and the other end (low potential side end) of the capacitor C2 is electrically connected to the source of the switching element Q2n. The source of switching element Q2p is electrically connected to the drain of switching element Q2n.

The power supply circuit 332 generates power using the voltage of the capacitor C2. The power supply circuit 332 supplies power to the isolation circuit 312, the drive circuit DV2n, and the balance circuit B12.
The isolation circuit 312 isolates the power supply circuit 332 and the drive circuit DV2p. The power supply circuit 332 and the drive circuit DV2p operate at different reference potentials. Isolation circuit 312 is, for example, a bootstrap circuit.

The drive circuit DV2p operates by being supplied with the power supply voltage through the isolation circuit 312, and drives the switching element Q2p based on the gate signal supplied from the control circuit CTR.
The drive circuit DV2n operates by being supplied with the power supply voltage from the power supply circuit 332, and drives the switching element Q2n based on the gate signal supplied from the control circuit CTR.

The unit converter 33 includes switching elements Q3p and Q3n, a capacitor C3, drive circuits DV3p and DV3n, an isolation circuit 313, and a power supply circuit 333.
The switching element Q3p and the switching element Q3n are connected in series, and the source of the switching element Q3p and the drain of the switching element Q3n are electrically connected to one of AC terminals UT, VT, and WT. A drain of the switching element Q3p is electrically connected to the unit converter 32 . The switching elements Q3p and Q3n have their operations controlled by drive signals from drive circuits DV3p and DV3n.

One end (high potential side end) of the capacitor C3 is electrically connected to the drain of the switching element Q3p, and the other end (low potential side end) of the capacitor C3 is electrically connected to the source of the switching element Q3n. The source of switching element Q3p is electrically connected to the drain of switching element Q3n.

The power supply circuit 333 generates power using the voltage of the capacitor C3. The power supply circuit 333 supplies power to the isolation circuit 313, the drive circuit DV3n, and the balance circuit B23.
The isolation circuit 313 isolates the power supply circuit 333 and the drive circuit DV3p. The power supply circuit 333 and the drive circuit DV3p operate at different reference potentials. Isolation circuit 313 is, for example, a bootstrap circuit.

The drive circuit DV3p operates by being supplied with the power supply voltage through the isolation circuit 313, and drives the switching element Q3p based on the gate signal supplied from the control circuit CTR.
The drive circuit DV3n operates by being supplied with the power supply voltage from the power supply circuit 333, and drives the switching element Q3n based on the gate signal supplied from the control circuit CTR.

The balance circuit B12 includes a balance switching element Q12b and a drive circuit DV12b.
The drain of the balance switching element Q12b is electrically connected to the other end (low potential side end) of the capacitor C1 of the unit converter 31 and the source of the second switching element Q1n. The source of the balance switching element Q12b is electrically connected to the other end (low potential side end) of the capacitor C2 of the unit converter 32 and the source of the second switching element Q2n.
That is, the balance switching element Q23b electrically connects the unit converter (first unit converter) 31 and the unit converter (second unit converter) 32 between the capacitor and the source of the second switching element. It is provided on the connecting route.

The drive circuit DV12b operates by being supplied with power supply voltage from the power supply circuit 332, and drives the balance switching element Q12b based on the gate signal supplied from the control circuit CTR. In this embodiment, the balance switching element Q12b has the same voltage as that of the power supply circuit 332 as a reference. That is, the reference potentials of the source (emitter in the case of IGBT) of the switching element Q12b and the power supply circuit 332 are each connected to the N side (low potential side) potential of the capacitor C2. Therefore, when power is supplied from the power supply circuit 332 to the driving circuit DV12b, it is not necessary to interpose an insulating circuit in the preceding stage of the driving circuit DV12b.

In this embodiment, the gate signal of the balance switching element Q12b is common to the switching element Q1p of the unit converter 31. FIG. That is, the gate signal input to the drive circuit DV12b and the gate signal input to the drive circuit DV1p are common. Therefore, the switching element Q1p and the balance switching element Q12b become conductive (turned on) at the same timing, and the capacitors C1 and C2 are connected in parallel. As a result, the voltages of the capacitors C1 and C2 become substantially equal.

The balance circuit B23 includes a balance switching element Q23b and a drive circuit DV23b.
The drain of the balance switching element Q23b is electrically connected to the other end (low potential side end) of the capacitor C2 of the unit converter 32 and the source of the second switching element Q2n. The source of the balance switching element Q23b is electrically connected to the other end (low potential side end) of the capacitor C3 of the unit converter 33 and the source of the second switching element Q3n.
That is, the balance switching element Q23b electrically connects the unit converter (first unit converter) 32 and the unit converter (second unit converter) 33 between the capacitor and the source of the second switching element. It is provided on the connecting route.

The drive circuit DV23b operates by being supplied with power supply voltage from the power supply circuit 333, and drives the balance switching element Q23b based on the gate signal supplied from the control circuit CTR. In this embodiment, the balance switching element Q23b has the same reference voltage as that of the power supply circuit 333. FIG. Therefore, when power is supplied from the power supply circuit 333 to the driving circuit DV23b, it is not necessary to interpose an insulating circuit in the preceding stage of the driving circuit DV23b.

In this embodiment, the gate signal of the balance switching element Q23b is common to the switching element Q2p of the unit converter 32. FIG. That is, the gate signal input to the drive circuit DV23b and the gate signal input to the drive circuit DV2p are common. Therefore, the switching element Q2p and the balance switching element Q23b are conducted (turned on) at the same timing, and the capacitors C2 and C3 are connected in parallel. As a result, the voltage of the capacitor C2 and the voltage of the capacitor C3 become substantially equal.

9 is a diagram for explaining an example of the motion of the arm shown in FIG. 8. FIG.
Here, for example, when the voltage of the capacitors C1-C3 is Vc, the output voltage Vout of the AC terminals UT, VT, WT is 3 times, 2 times, 1 time and zero of the voltage Vc. 31-33 of switching elements Q1p-Q3n and switching elements Q12b and Q23b of balance circuits B12 and B23 are shown in the conducting state. In FIG. 8, "1" indicates the state in which the switching element is conducting (ON state), and "0" indicates the state in which the switching element is not conducting (OFF state).

For example, when the output voltage is three times the voltage Vc, the switching element Q1p is turned off, the switching element Q1n is turned on, the switching element Q2p is turned off, the switching element Q2n is turned on, the switching element Q3p is turned off, and the switching element Q3n is turned on. Become. At this time, the switching element Q12b is turned off, the balance switching element Q23b is turned off, and the capacitors C1 to C3 are not connected to each other.

For example, when the output voltage is double the voltage Vc, the switching element Q1p is on, the switching element Q1n is off, the switching element Q2p is off, the switching element Q2n is on, the switching element Q3p is off, and the switching element Q3n is on. Become. At this time, the switching element Q12b is turned on, the balance switching element Q23b is turned off, the capacitors C1 and C2 are connected in parallel, and the capacitor C3 is not connected to the other capacitors C1 and C2.

For example, when the output voltage is 1 times the voltage Vc, the switching element Q1p is on, the switching element Q1n is off, the switching element Q2p is on, the switching element Q2n is off, the switching element Q3p is off, and the switching element Q3n is on. Become. At this time, the switching element Q12b is turned on, the balance switching element Q23b is turned on, and the capacitors C1 to C3 are connected in parallel.

For example, when the output voltage becomes zero, the switching element Q1p is on, the switching element Q1n is off, the switching element Q2p is on, the switching element Q2n is off, the switching element Q3p is on, and the switching element Q3n is off. At this time, the switching element Q12b is turned on, the balance switching element Q23b is turned on, and the capacitors C1 to C3 are connected in parallel.

As described above, when the output of the arm 30 is switched, the connection state of the capacitors C1-C3 is also switched, so that the voltages of the capacitors C1-C3 can be equalized at the same time that the power converter performs normal operation. Therefore, by obtaining the voltage of any one of the capacitors C1 to C3, the voltage value of the capacitors C1 to C3 can be controlled. - Eliminates the need for special control to equalize the voltages of C3.

The power conversion device 20 of this embodiment is the same as that of the above-described first embodiment except for the configuration described above. That is, according to the power conversion device 20 of the present embodiment, each arm 30 includes the balance circuits B12 and B23, and the balance switching elements of the balance circuits B12 and B23 are synchronized with the switching elements of the unit converters in each arm 30. By operation, it is possible to equalize the capacities of the unit converter capacitors in arm 30 . This configuration eliminates the need to detect all the voltages of the capacitors of the unit converters included in the power converter 20 and control the individual voltages, and eliminates the need for detectors for detecting the voltages of the capacitors for each unit converter. At the same time, the amount of calculation in the control circuit CTR can be reduced.

Furthermore, the power conversion device 20 of the present embodiment does not require the insulating circuits of the balance circuits B12 and B23, and can be realized with fewer components than the above-described first embodiment.
That is, according to the present embodiment, it is possible to provide a compact multi-serial unit converter cluster and a power converter that are low in cost and have few harmonics.

Next, the power conversion device of the third embodiment will be described in detail with reference to the drawings.
FIG. 10 is a diagram schematically showing one configuration example of the power converter of the third embodiment.
The power converter 20 of the present embodiment is a neutral point clamped modular multilevel converter (hereinafter referred to as NPC-MMC (Neutral Point Clamped Modular Multilevel Converter)).

The power conversion device 20 of the present embodiment includes a DC positive terminal PT, a DC negative terminal MT, and AC terminals UT, VT, and WT. can be connected between

The power conversion device 20 includes a first capacitor CA, a second capacitor CB, first switching legs L1U, L1V, L1W, second switching legs L2U, L2V, L2W, positive arms 30U, 30V, 30W, It includes negative arms 30X, 30Y, 30Z, buffer reactors LU, LV, LW, LX, LY, LZ, a potential transformer 22, and a control device CTR.

The first capacitor CA and the second capacitor CB are connected in series between the DC positive terminal PT and the DC negative terminal MT. The first capacitor CA is electrically connected to the DC positive terminal PT at one end (high potential side end). The second capacitor CB is electrically connected between the other end (low potential side end) of the first capacitor CA and the DC negative terminal MT. A neutral point potential is applied between the first capacitor CA and the second capacitor.

The first switching legs L1U, L1V, L1W are connected in parallel with the first capacitor CA. The second switching legs L2U, L2V, L2W are connected in parallel with the second capacitor CB.

In the power converter 20 of the present embodiment, the first capacitor CA and the second capacitor CB are shared by the three phases, but two capacitors may be connected in parallel to each of the three phases.

Each of the first switching legs L1U, L1V, L1W includes a first switching element S1U, S1V, S1W, a second switching element S2U, S2V, S2W, and a first output terminal O1U, O1V, O1W. .

In the following description, it is assumed that the first switching elements S1U, S1V, S1W and the second switching elements S2U, S2V, S2W are MOSFETs (metal-oxide semiconductor field-effect transistors). The first switching elements S1U, S1V, S1W and the second switching elements S2U, S2V, S2W include, for example, a self arc-extinguishing switching element such as an IEGT (injection enhanced gate transistor) and a free wheel diode connected in anti-parallel to the IEGT. may be provided. A self-arc-extinguishing switching element, such as a GTO (gate turn-off thyristor), a GCT (gate communicated turn-off thyristor), or an IGBT (Insulated Gate Bipolar Transistor), can be turned on (conducting state) or off (non-conducting state). It is possible to adopt a switching element that can electrically control the conduction state). For example, when IGBTs are employed as the first switching elements S1U, S1V, S1W and the second switching elements S2U, S2V, S2W, the drain in the following description can be read as the collector and the source as the emitter. can.

The first switching elements S1U, S1V, and S1W are electrically connected to the DC positive terminal PT at drains. The second switching elements S2U, S2V, S2W are electrically connected at the source and drain of the first switching elements S1U, S1V, S1W, and electrically connected between the first capacitor CA and the second capacitor CB. Make an electrical connection at the neutral point and the source. The first output terminals O1U, O1V, O1W are provided between the first switching elements S1U, S1V, S1W and the second switching elements S2U, S2V, S2W.

Each of the second switching legs L2U, L2V, L2W comprises a third switching element S3U, S3V, S3W, a fourth switching element S4U, S4V, S4W, and a second output terminal O2U, O2V, O2W. .

In the following description, it is assumed that the third switching elements S3U, S3V, S3W and the fourth switching elements S4U, S4V, S4W are MOSFETs (metal-oxide semiconductor field-effect transistors). The third switching elements S3U, S3V, S3W and the fourth switching elements S4U, S4V, S4W include, for example, a self arc-extinguishing switching element such as an IEGT (injection enhanced gate transistor) and a free wheel diode connected in anti-parallel to the IEGT. may be provided. A self-arc-extinguishing switching element, such as a GTO (gate turn-off thyristor), a GCT (gate communicated turn-off thyristor), or an IGBT (Insulated Gate Bipolar Transistor), can be turned on (conducting state) or off (non-conducting state). It is possible to adopt a switching element that can electrically control the conduction state). For example, when IGBTs are employed as the third switching elements S3U, S3V, S3W and the fourth switching elements S4U, S4V, S4W, the drain in the following description can be read as the collector and the source as the emitter. can.

The third switching elements S3U, S3V, and S3W are electrically connected to the neutral point and the drain. The fourth switching elements S4U, S4V, S4W are electrically connected to the sources and drains of the third switching elements S3U, S3V, S3W, and electrically connected to the DC negative terminal MT at the sources. The second output terminals O2U, O2V, O2W are provided between the third switching elements S3U, S3V, S3W and the fourth switching elements S4U, S4V, S4W.

The first switching elements S1U, S1V, S1W and the second switching elements S2U, S2V, S2W are connected in series between the DC positive terminal PT and the neutral point potential. That is, the first switching elements S1U, S1V, S1W and the second switching elements S2U, S2V, S2W are connected in parallel with the first capacitor CA.

The third switching elements S3U, S3V, S3W and the fourth switching elements S4U, S4V, S4W are connected in series between the DC negative terminal MT and the neutral point potential. That is, the third switching elements S3U, S3V, S3W and the fourth switching elements S4U, S4V, S4W are connected in parallel with the second capacitor CB.

The first switching elements S1U, S1V, S1W, the second switching elements S2U, S2V, S2W, the third switching elements S3U, S3V, S3W, and the fourth switching elements S4U, S4V, S4W are, for example, GTO (gate turn-off thyristor), GCT (gate communicated turn-off thyristor), IGBT (Insulated Gate Bipolar Transistor) or MOSFET (metal-oxide-semiconductor field-effect transistor), etc. A self arc-extinguishing element such as a switching element that can electrically control the state).

Each of the positive side arms 30U, 30V, 30W and the negative side arms 30X, 30Y, 30Z includes a plurality of unit converters connected in series and a balance circuit. In this embodiment, the configuration of the positive side arms 30U, 30V, 30W and the negative side arms 30X, 30Y, 30Z is the configuration of the arms 30 in the power conversion device 20 of the above-described first and second embodiments. Configured. In the first and second embodiments described above, the arm 30 is connected between the DC terminals PT, MT and the AC terminals UT, VT, WT. They are connected between the output terminals O1U, O1V, O1W, O2U, O2V, O2W and the AC terminals TU, TV, TW.

For example, the positive arms 30U, 30V, 30W are connected in series between the AC terminals TU, TV, TW connected to the AC power supply 10 and the first output terminals O1U, O1V, O1W. -33, and balance circuits B12, B23. The negative arms 30X, 30Y, 30Z include a plurality of unit converters 31-33 connected in series between the AC terminals TU, TV, TW and the second output terminals O2U, O2V, O2W, and balance circuits B12, B23. and including.

In the example of the power converter 20 shown in FIG. 10, the positive arms 30U, 30V, 30W and the negative arms 30X, 30Y, 30Z are connected via buffer reactors LU, LV, LW, LX, LY, LZ. Although they are electrically connected to the AC terminals UT, VT, and WT, they may be connected via, for example, a coupling reactor or a transformer, or they may be directly connected.

The potential transformer 22 converts the AC voltage of the AC line connecting between the AC load 10 and the power converter 20 into a voltage that can be used by the control circuit CTR, and outputs the voltage to the control circuit CTR.

The control circuit CTR controls the first switching elements S1U, S1V, S1W, the second switching elements S2U, S2V, Controls the operations of S2W, the third switching elements S3U, S3V, S3W, the fourth switching elements S4U, S4V, S4W, the positive side arms 30U, 30V, 30W, and the negative side arms 30X, 30Y, 30Z. .

The control circuit CTR includes, for example, at least one processor such as a CPU (central processing unit) or MPU (micro processing unit), and a memory in which a program executed by the processor is recorded, and is operated by software. may be configured to

FIG. 11 is a block diagram schematically showing one configuration example of the control circuit of the power converter of the third embodiment.
Here, for the sake of explanation, only blocks that generate gate signals for the positive and negative arms of one phase (eg, U phase) and gate signals for the switching elements S1 to S4 are shown.

The control circuit CTR includes a capacitor voltage average value control section 41, a capacitor voltage balance control section 42, a current control section 43, a comparator COM, a multiplier M1, adders AD1 and AD2, and switches SP and SN. , PWM processing units 46U and 46X. The control circuit CTR may also include a detector that detects the voltages of the first capacitor C1 and the second capacitor C2. Also, the control circuit CTR may be configured to acquire the voltage values (or voltage equivalent values) of the first capacitor C1 and the second capacitor C2 detected by an external detector.

The capacitor voltage average value control unit 41 is, for example, a proportional control circuit or a proportional integral control circuit that performs control so that the difference between the cell capacitor voltage command value and the cell capacitor voltage average value becomes zero.

The capacitor voltage balance control unit 42 outputs an operation amount for matching, that is, balancing the voltages Vc of all the cell capacitors CA. The capacitor voltage balance control unit 42 is, for example, a proportional control circuit or a proportional integral control circuit that outputs a control amount so that the difference between each of the capacitor voltages supplied from the arm 30 and the capacitor voltage average value becomes zero. . Also, the capacitor voltage balance control unit 42 is, for example, a proportional control circuit or a proportional integral control circuit that outputs a control amount that makes the difference between one capacitor of the positive side arm 30U and one capacitor of the negative side arm 30X zero. may be

The current control unit 43 receives, for example, the system voltage value, the reactive power command value, and the active power command value from the outside, receives the control amount output from the capacitor voltage average value control unit 41, and controls these values Based on, the control amount (voltage command value) that realizes the reactive power command value and the active power command value is calculated and output.

The output value of the current control unit 43 is input to the comparator COM, the multiplier M1, one input terminal of the switch SN, and the adder AD2.

The comparator COM compares the control amount output from the current control unit 43 with the reference potential, and selects the first switching elements S1U, S1V, S1W, the second switching elements S2U, S2V, S2W, and the third switching element S3U. , S3V, S3W and the fourth switching elements S4U, S4V, S4W.

That is, the comparator COM turns on the first switching elements S1U, S1V, S1W and the third switching elements S3U, S3V, S3W when the control amount output from the current control unit 43 is positive (larger than the reference voltage). , to output gate signals for turning off the first switching elements S1U, S1V, S1W and the third switching elements S3U, S3V, S3W when the control amount output from the current control unit 43 is negative (smaller than the reference voltage). .

Further, the comparator COM turns on the second switching elements S2U, S2V, S2W and the fourth switching elements S4U, S4V, S4W when the control amount output from the current control unit 43 is negative (smaller than the reference voltage). , output gate signals for turning off the second switching elements S2U, S2V, S2W and the fourth switching elements S4U, S4V, S4W when the control amount output from the current control unit 43 is positive (larger than the reference voltage). .

Multiplier M1 multiplies the control amount input from current control unit 43 by -1 and outputs the result to one input terminal of adder AD1 and switch SP.
The adder AD1 adds the value input from the multiplier M1 and the value input from the capacitor voltage balance control section 42, and outputs the result to the other input terminal of the switch SP.
The adder AD2 adds the value input from the current control section 43 and the value input from the capacitor voltage balance control section 42, and outputs the result to the other input terminal of the switch SN.

The switches SP and SN are configured to switch their output values in synchronization with the timing at which the output value of the comparator COM switches.

For example, when the control amount output from the current control unit 43 is positive (larger than the reference voltage), the output value (voltage command value of the positive side arm) of the switch SP becomes the output value of the adder AD1. When the control amount output from the current control unit 43 is negative (smaller than the reference voltage), the output value (voltage command value for the positive side arm) is switched to the output value of the multiplier M1.

In addition, when the control amount output from the current control unit 43 is positive (larger than the reference voltage), the output value (voltage command value of the negative side arm) of the switch SN becomes the output value of the current control unit 43. , when the control amount output from the current control unit 43 is negative (smaller than the reference voltage), the output value (voltage command value for the negative arm) is switched to the output value of the adder AD2.

The PWM processing unit 46U uses the value input from the switch SP as a voltage command value, compares the voltage command value with the carrier wave, and determines the gate of the switching element of the unit converters 31 to 33 of the U-phase positive arm 30U. Generate and output a signal.

The PWM processing unit 46X uses the value input from the switch SN as a voltage command value, compares the voltage command value with the carrier wave, and outputs the gate signal of the switching element of the unit converters 31 to 33 of the negative arm 30X. Generate and output.

Each of the PWM processing units 46U and 46X generates a gate signal corresponding to each of the unit converters 31-33 using a carrier wave corresponding to each of the plurality of unit converters 31-33. be able to.

In the power conversion device 20 of the present embodiment, each arm 30 includes balance circuits B12 and B23 in the same manner as in the above-described first and second embodiments, and balance switching of the balance circuits B12 and B23 is performed in each arm 30. By synchronizing the operation of the elements with the switching elements of the unit converters, it is possible to equalize the capacities of the unit converter capacitors in arm 30 . This configuration eliminates the need to detect all the voltages of the capacitors of the unit converters included in the power converter 20 and control the individual voltages, and eliminates the need for detectors for detecting the voltages of the capacitors for each unit converter. At the same time, the amount of calculation in the control circuit CTR can be reduced.
That is, according to the present embodiment, it is possible to provide a compact multi-serial unit converter cluster and a power converter that are low in cost and have few harmonics.

Next, the reactive power compensator of the fourth embodiment will be described in detail with reference to the drawings.
FIG. 12 is a diagram schematically showing one configuration example of a reactive power compensator according to the fourth embodiment.
The reactive power compensator 22 of the present embodiment includes AC terminals UT, VT, WT, a U-phase arm 50U, a V-phase arm 50V, a W-phase arm 50W, a control circuit CTR, and buffer reactors LU, LV, LW. and have.

One end of U-phase arm 50U is electrically connected to AC terminal UT via buffer reactor LU. One end of the V-phase arm 50V is electrically connected to the AC terminal VT via a buffer reactor LV. One end of the W-phase arm 50W is electrically connected to the AC terminal WT via the buffer reactor LW. The other ends of U-phase arm 50U, V-phase arm 50V, and W-phase arm 50W are electrically connected to each other.

U-phase arm 50U, V-phase arm 50V, and W-phase arm 50W each include unit converters 51-53 and balance circuits B12 and B23.

13 is a diagram schematically showing a configuration example of each phase arm of the reactive power compensator shown in FIG. 12. FIG.
Here, the common configuration of the U-phase arm 50U, the V-phase arm 50V, and the W-phase arm 50W will be described as an arm 50. FIG. Arm 50 includes unit converters 51-53 and balance circuits B12 and B23.
When N is a positive integer, the Nth unit converter includes 3N switching elements whose drains are connected to the drains of the _1N switching elements and _2N switching elements whose drains are connected to the sources of _{the 3N} switching elements _. and a _4N switching element having a source connected to the source of the switching element.
FIG. 13 shows an example of the configuration of the unit converter cluster when N≦3. For example, the unit converter 53 is the first unit converter, the unit converter 52 is the second unit converter, and the unit converter 51 corresponds to the third unit converter.

The unit converter 51 includes a switching element (first switching element) Q11p, a switching element (second switching element) Q11n, a switching element (third switching element) Q12p, a switching element (fourth switching element) Q12n, A capacitor C1, a voltage detector SV, an isolation circuit (first isolation circuit) 511, a power supply circuit 531, a drive circuit (first drive circuit) DV1p, and a drive circuit (second drive circuit) DV1n. ing.

The switching elements Q11p, Q11n, Q12p, and Q12n are provided with self-arc-extinguishing switching elements such as MOSFETs (metal-oxide semiconductor field-effect transistors). Self arc-extinguishing switching elements are, for example, IEGT (injection enhanced gate transistor), GTO (gate turn-off thyristor), GTO (gate turn-off thyristor), GCT (gate communicated turn-off thyristor), or IGBT ( Insulated Gate Bipolar Transistor), etc., can be employed that can electrically control ON (conducting state) and OFF (non-conducting state) of the element. The switching elements Q11p, Q11n, Q12p, and Q12n may include freewheeling diodes connected in anti-parallel to the switching elements, if necessary.
When IGBTs or IEGTs are used as the switching elements Q11p, Q11n, Q12p, and Q12n, the sources of the switching elements Q11p, Q11n, Q12p, and Q12n are replaced with the emitters, and the drains of the switching elements Q11p, Q11n, Q12p, and Q12n are replaced with emitters. is read as a collector.

The switching element Q11p and the switching element Q11n are connected in series, and are electrically connected to one of AC terminals UT, VT, and WT between the switching element Q11p and the switching element Q11n.

Switching element Q12p and switching element Q12n are connected in series, and are electrically connected to unit converter 52 between switching element Q12p and switching element Q12n.

One end of capacitor C1 is electrically connected to the drain of switching element Q11p and the drain of switching element Q12p, and the other end of capacitor C1 is electrically connected to the source of switching element Q11n and the source of switching element Q12n. The source of switching element Q11p is electrically connected to the drain of switching element Q11n, and the source of switching element Q12p is electrically connected to the drain of switching element Q12n.

The voltage detector SV detects the voltage of the capacitor C1 and outputs the detected voltage value (or the value corresponding to the voltage) to the control circuit CTR.
The power supply circuit 531 generates power using the voltage of the capacitor C1. The power supply circuit 531 supplies power to the isolation circuit 511 and the drive circuit DV1n.

The isolation circuit 511 isolates the power supply circuit 531 and the drive circuit DV1p. The power supply circuit 531 and the drive circuit DV1p operate at different reference potentials. Isolation circuit 531 is, for example, a bootstrap circuit.
The drive circuit DV1p operates by being supplied with the power supply voltage through the isolation circuit 511, and drives the switching elements Q11p and Q12p based on the gate signal supplied from the control circuit CTR.
The drive circuit DV1n operates by being supplied with a power supply voltage from the power supply circuit 531, and drives the switching elements Q11n and Q12n based on the gate signal supplied from the control circuit CTR.

The unit converters 52 and 53 have the same configuration as the unit converter 51 except that they do not have the voltage detector SV.
The unit converter 52 includes a switching element (first switching element) Q21p, a switching element (second switching element) Q21n, a switching element (third switching element) Q22p, a switching element (fourth switching element) Q22n, It includes a capacitor C2, an isolation circuit (first isolation circuit) 512, a power supply circuit 532, a drive circuit (first drive circuit) DV2p, and a drive circuit (second drive circuit) DV2n.

The switching element Q21p and the switching element Q21n are connected in series, and between the switching element Q21p and the switching element Q21n of the unit converter (first unit converter) 52, the It is electrically connected between switching element Q12p and switching element Q12n.

The switching element Q22p and the switching element Q22n are connected in series, and switching of the unit converter (first unit converter) 53 is performed between the switching element Q22p and the switching element Q22n of the unit converter (second unit converter) 52. It is electrically connected between the element Q31p and the switching element Q31n.

One end of capacitor C2 is electrically connected to the drain of switching element Q21p and the drain of switching element Q22p, and the other end of capacitor C2 is electrically connected to the source of switching element Q21n and the source of switching element Q22n. The source of switching element Q21p is electrically connected to the drain of switching element Q21n, and the source of switching element Q22p is electrically connected to the drain of switching element Q22n.

The power supply circuit 532 generates power using the voltage of the capacitor C2. The power supply circuit 532 supplies power to the isolation circuit 512 and the drive circuit DV2n.
The isolation circuit 512 isolates the power supply circuit 532 and the drive circuit DV2p. The power supply circuit 532 and the drive circuit DV2p operate at different reference potentials. Isolation circuit 512 is, for example, a bootstrap circuit.

The drive circuit DV2p operates by being supplied with the power supply voltage through the isolation circuit 512, and drives the switching elements Q21p and Q22p based on the gate signal supplied from the control circuit CTR.
The drive circuit DV2n operates by being supplied with a power supply voltage from the power supply circuit 532, and drives the switching elements Q21n and Q22n based on the gate signal supplied from the control circuit CTR.

The unit converter 53 includes a switching element (first switching element) Q31p, a switching element (second switching element) Q31n, a switching element (third switching element) Q32p, a switching element (fourth switching element) Q32n, It includes a capacitor C3, an isolation circuit (first isolation circuit) 513, a power supply circuit 533, a drive circuit (first drive circuit) DV3p, and a drive circuit (second drive circuit) DV3n.

Switching element Q31p and switching element Q31n are connected in series, and are electrically connected between switching element Q22p and switching element Q22n of unit converter 52 between switching element Q31p and switching element Q31n.

The switching element Q32p and the switching element Q32n are connected in series, and are electrically connected to the unit converter 53 of the other arm between the switching element Q32p and the switching element Q32n.

One end of capacitor C3 is electrically connected to the drain of switching element Q31p and the drain of switching element Q32p, and the other end of capacitor C3 is electrically connected to the source of switching element Q31n and the source of switching element Q32n. The source of switching element Q31p is electrically connected to the drain of switching element Q31n, and the source of switching element Q32p is electrically connected to the drain of switching element Q32n.

The power supply circuit 533 generates power using the voltage of the capacitor C3. The power supply circuit 533 supplies power to the isolation circuit 513 and the drive circuit DV3n.
The isolation circuit 513 isolates the power supply circuit 533 and the drive circuit DV3p. The power supply circuit 533 and the drive circuit DV3p operate at different reference potentials. Isolation circuit 513 is, for example, a bootstrap circuit.

The drive circuit DV3p operates by being supplied with the power supply voltage through the isolation circuit 513, and drives the switching elements Q31p and Q32p based on the gate signal supplied from the control circuit CTR.
The drive circuit DV3n operates by being supplied with the power supply voltage from the power supply circuit 533, and drives the switching elements Q23n and Q23n based on the gate signal supplied from the control circuit CTR.

The balance circuit B12 includes a balance switching element Q121b, a balance switching element (second balance switching element) Q122b, drive circuits (balance switch drive circuits) DV121b and DV122b, insulation circuits (third insulation circuits) 5211 and 5212, It has
The balance switching elements Q121b and Q122b are provided with self-arc-extinguishing switching elements such as MOSFETs (metal-oxide semiconductor field-effect transistors). The self arc-extinguishing switching element is, for example, an IEGT (injection enhanced gate transistor), a GTO (gate turn-off thyristor), a GTO (gate turn-off thyristor), a GCT (gate communicated turn-off thyristor), or an IGBT (Insulated It is possible to employ a switching element such as a Gate Bipolar Transistor, which can be electrically controlled to be turned on (conducting state) and off (non-conducting state). The balance switching elements Q121b and Q122b may include free wheel diodes connected in anti-parallel to the switching elements, if necessary.
When IGBTs or IEGTs are used as the balance switching elements Q121b and Q122b, the sources of the balance switching elements Q121b and Q122b are read as emitters, and the drains of the balance switching elements Q121b and Q122b are read as collectors.

The balance switching element Q121b and the balance switching element Q122b are arranged such that the positions of the source and the drain are opposite to each other, and the drains are electrically connected to each other, for example.
One end (source) of the balance switching element Q121b is electrically connected to one end of the capacitor C1 of the unit converter 51 and the drains of the switching elements Q11p and Q12p. The other end (drain) of the balance switching element Q121b is electrically connected to one end (drain) of the balance switching element Q122b. The other end (source) of the balance switching element Q122b is electrically connected to one end of the capacitor C2 of the unit converter 52 and the drains of the switching elements Q21p and Q22p.
That is, the balance switching elements Q121b and Q122b are connected between the drain of the first switching element, the drain of the third switching element, and the capacitor, between the unit converter (first unit converter) 52 and the unit converter (second unit converter). converter) 51 is provided on a path electrically connecting to the converter) 51 .
Therefore, when the balance switching elements Q121b and Q122b are turned on (conducted), one end of the capacitor C1 and one end of the capacitor C2 are electrically connected.

The balance switching element Q121b may be arranged so that the source is on one end side of the capacitor C1 of the unit converter 51 and the drain is on one end side of the capacitor C2 of the unit converter 52. FIG. The balance switching element Q122b may be arranged so that the source is on one end side of the capacitor C2 of the unit converter 52 and the drain is on the one end side of the capacitor C1 of the unit converter 51 . That is, the balance switching element Q121b may be arranged so that the arrangement of the source and the drain is opposite to that of the balance switching element Q122b. The order in which Q122b and Q122b are arranged may be reversed from that in FIG.

The isolation circuit 5211 isolates the power supply circuit 531 and the drive circuit DV121b. The power supply circuit 531 and the drive circuit DV121b operate at different reference potentials. Isolation circuit 5211 is, for example, a bootstrap circuit.
The drive circuit DV121b operates by being supplied with the power supply voltage through the isolation circuit 5211, and drives the balance switching element Q121b based on the gate signal supplied from the control circuit CTR.

The isolation circuit 5212 isolates the power supply circuit 532 and the drive circuit DV122b. The power supply circuit 532 and the drive circuit DV122b operate at different reference potentials. Isolation circuit 5212 is, for example, a bootstrap circuit.
The drive circuit DV122b operates by being supplied with the power supply voltage through the isolation circuit 5212, and drives the balance switching element Q122b based on the gate signal supplied from the control circuit CTR.

In this embodiment, the gate signal of the balance switching element Q121b is common to the gate signal of the switching element Q12n of the unit converter 51. FIG. The gate signal of the balance switching element Q122b is common to the gate signal of the switching element Q21n of the unit converter 52. Therefore, the switching element Q12n and the balance switching element Q121b are conducted (turned on) at the same timing, the switching element Q21n and the balance switching element Q122b are conducted (turned on) at the same timing, and the switching element Q12n and the switching element Q21n are connected (turned on) at the same timing. The capacitor C1 and the capacitor C2 are connected in parallel at the timing when both of are turned on. As a result, the voltage of the capacitor C1 and the voltage of the capacitor C2 become substantially equal.

The balance circuit B23 includes a balance switching element Q231b, a balance switching element (second balance switching element) Q232b, drive circuits (balance switch drive circuits) DV231b and DV232b, insulation circuits (third insulation circuits) 5221 and 5222, It has
The balance switching elements Q231b and Q232b are provided with self-arc-extinguishing switching elements such as MOSFETs (metal-oxide semiconductor field-effect transistors). The self arc-extinguishing switching element is, for example, an IEGT (injection enhanced gate transistor), a GTO (gate turn-off thyristor), a GTO (gate turn-off thyristor), a GCT (gate communicated turn-off thyristor), or an IGBT (Insulated It is possible to employ a switching element such as a Gate Bipolar Transistor, which can be electrically controlled to be turned on (conducting state) and off (non-conducting state). The balance switching elements Q231b and Q232b may include free wheel diodes connected in anti-parallel to the switching elements, if necessary.
When IGBTs or IEGTs are used as the balance switching elements Q231b and Q232b, the sources of the balance switching elements Q231b and Q232b are read as emitters, and the drains of the balance switching elements Q231b and Q232b are read as collectors.

The balance switching element Q231b and the balance switching element Q232b are arranged such that the positions of the source and the drain are opposite to each other, and the drains are connected to each other, for example.
One end (source) of the balance switching element Q231b is electrically connected to one end of the capacitor C2 of the unit converter 52 and the drains of the switching elements Q21p and Q22p. The other end (drain) of the balance switching element Q231b is electrically connected to one end (drain) of the balance switching element Q232b. The other end (source) of the balance switching element Q232b is electrically connected to one end of the capacitor C3 of the unit converter 53 and the drains of the switching elements Q31p and Q32P.
That is, the balance switching elements Q231b and Q232b are arranged between the drain of the first switching element and the drain of the third switching element and the capacitor, between the unit converter (first unit converter) 53 and the unit converter (second unit converter). converter) 52.

Therefore, when the balance switching elements Q231b and Q232b are turned on (conducted), one end of the capacitor C2 is electrically connected to one end of the capacitor C2.

The balance switching element Q231b may be arranged so that the source is on one end side of the capacitor C2 of the unit converter 52 and the drain is on the one end side of the capacitor C3 of the unit converter 53. The balance switching element Q232b may be arranged such that the source is on one end side of the capacitor C3 of the unit converter 53 and the drain is on one end side of the capacitor C2 of the unit converter 52. FIG. That is, the balance switching element Q231b may be arranged such that the arrangement of the source and the drain is opposite to that of the balance switching element Q232b. The order in which Q232b is arranged may be reversed from that in FIG.

The isolation circuit 5221 isolates the power supply circuit 532 and the drive circuit DV231b. The power supply circuit 532 and the drive circuit DV231b operate at different reference potentials. Isolation circuit 5221 is, for example, a bootstrap circuit.
The drive circuit DV231b operates by being supplied with the power supply voltage through the isolation circuit 5221, and drives the balance switching element Q231b based on the gate signal supplied from the control circuit CTR.

The isolation circuit 5222 isolates the power supply circuit 533 and the drive circuit DV232b. The power supply circuit 533 and the drive circuit DV232b operate at different reference potentials. Isolation circuit 5222 is, for example, a bootstrap circuit.
The drive circuit DV232b operates by being supplied with the power supply voltage through the isolation circuit 5222, and drives the balance switching element Q232b based on the gate signal supplied from the control circuit CTR.

In this embodiment, the gate signal of the balance switching element Q231b is common to the gate signal of the switching element Q22n of the unit converter 52. FIG. The gate signal of the balance switching element Q232b is common to the gate signal of the switching element Q31n of the unit converter 53. Therefore, the switching element Q22n and the balance switching element Q231b are conducted (turned on) at the same timing, the switching element Q31n and the balance switching element Q232b are conducted (turned on) at the same timing, and the switching element Q22n and the switching element Q31n are conducted (turned on) at the same timing. are connected in parallel with the capacitor C2 and the capacitor C3. As a result, the voltages of the capacitors C2 and C3 become substantially equal.

14 is a diagram for explaining an example of the motion of the arm shown in FIG. 13; FIG.
Here, for example, when the voltage of the capacitors C1 to C3 is Vc, the output voltage Vout of the AC terminals UT, VT, and WT is 3 times, 2 times, 1 time, -1 times, -2 times, - It shows the conduction states of the switching elements Q11p-Q32n of the unit converters 51-53 and the balance switching elements Q121b, Q122b, Q231b, Q232b of the balance circuits B12, B23 when tripled and zero. In FIG. 13, "1" indicates the state in which the switching element is conducting (ON state), and "0" indicates the state in which the switching element is not conducting (OFF state).

For example, when the output voltage is three times the voltage Vc, the switching element Q11p is on, the switching element Q11n is off, the switching element Q12p is off, the switching element Q12n is on, the switching element Q21p is on, the switching element Q21n is off, The switching element Q22p is turned off, the switching element Q22n is turned on, the switching element Q31p is turned on, the switching element Q31n is turned off, the switching element Q32p is turned off, and the switching element Q32n is turned on. At this time, the balance switching element Q121b is on, the switching element Q122b is off, the switching element Q231b is on, the balance switching element Q232b is off, and the capacitors C1 to C3 are not connected to each other.

For example, when the output voltage is double the voltage Vc, the switching element Q11p is off, the switching element Q11n is on, the switching element Q12p is off, the switching element Q12n is on, the switching element Q21p is on, the switching element Q21n is off, The switching element Q22p is turned off, the switching element Q22n is turned on, the switching element Q31p is turned on, the switching element Q31n is turned off, the switching element Q32p is turned off, and the switching element Q32n is turned on. At this time, the balance switching element Q121b is on, the switching element Q122b is off, the switching element Q231b is on, the balance switching element Q232b is off, and the capacitors C1 to C3 are not connected in parallel with each other.

For example, when the output voltage is 1 times the voltage Vc, the switching element Q11p is off, the switching element Q11n is on, the switching element Q12p is off, the switching element Q12n is on, the switching element Q21p is off, the switching element Q21n is on, The switching element Q22p is turned off, the switching element Q22n is turned on, the switching element Q31p is turned on, the switching element Q31n is turned off, the switching element Q32p is turned off, and the switching element Q32n is turned on. At this time, the balance switching element Q121b is turned on, the switching element Q122b is turned on, the switching element Q231b is turned on, and the balance switching element Q232b is turned off. is not connected to

For example, when the output voltage becomes zero, the switching element Q11p is turned off, the switching element Q11n is turned on, the switching element Q12p is turned off, the switching element Q12n is turned on, the switching element Q21p is turned off, the switching element Q21n is turned on, and the switching element Q22p is turned on. OFF, the switching element Q22n is ON, the switching element Q31p is OFF, the switching element Q31n is ON, the switching element Q32p is OFF, and the switching element Q32n is ON. At this time, the balance switching element Q121b is turned on, the switching element Q122b is turned on, the switching element Q231b is turned on, the balance switching element Q232b is turned on, and the capacitors C1 to C3 are connected in parallel with each other.

For example, when the output voltage is -1 times the voltage Vc, the switching element Q11p is turned off, the switching element Q11n is turned on, the switching element Q12p is turned off, the switching element Q12n is turned on, the switching element Q21p is turned off, and the switching element Q21n is turned on. , the switching element Q22p is off, the switching element Q22n is on, the switching element Q31p is off, the switching element Q31n is on, the switching element Q32p is on, and the switching element Q32n is off. At this time, the balance switching element Q121b is turned on, the switching element Q122b is turned on, the switching element Q231b is turned on, the balance switching element Q232b is turned on, and the capacitors C1 to C3 are connected in parallel with each other.

For example, when the output voltage is -2 times the voltage Vc, the switching element Q11p is turned off, the switching element Q11n is turned on, the switching element Q12p is turned off, the switching element Q12n is turned on, the switching element Q21p is turned off, and the switching element Q21n is turned on. , the switching element Q22p is on, the switching element Q22n is off, the switching element Q31p is off, the switching element Q31n is on, the switching element Q32p is on, and the switching element Q32n is off. At this time, the balance switching element Q121b is on, the switching element Q122b is on, the switching element Q231b is off, the balance switching element Q232b is on, the capacitor C1 and the capacitor C2 are connected in parallel, and the capacitor C3 is in parallel with another capacitor. is not connected to

For example, when the output voltage is -3 times the voltage Vc, the switching element Q11p is turned off, the switching element Q11n is turned on, the switching element Q12p is turned on, the switching element Q12n is turned off, the switching element Q21p is turned off, and the switching element Q21n is turned on. , the switching element Q22p is on, the switching element Q22n is off, the switching element Q31p is off, the switching element Q31n is on, the switching element Q32p is on, and the switching element Q32n is off. At this time, the balance switching element Q121b is turned off, the switching element Q122b is turned on, the switching element Q231b is turned off, the balance switching element Q232b is turned on, and the capacitors C1 to C3 are not connected in parallel with each other.

As described above, when the output of the arm 50 is switched, the connection state of the capacitors C1-C3 is also switched, so that the voltages of the capacitors C1-C3 can be equalized at the same time that the power converter performs normal operation. Therefore, by obtaining the voltage of any one of the capacitors C1 to C3, the voltage value of the capacitors C1 to C3 can be controlled. - Eliminates the need for special control to equalize the voltages of C3.

15 is a block diagram for explaining a configuration example of a control circuit of the reactive power compensator shown in FIG. 12. FIG.
16 is a block diagram for explaining a configuration example of a delay circuit of a control circuit of the reactive power compensator shown in FIG. 15. FIG.

Here, for an example in which each phase arm includes N stages of unit converters, a configuration example of a circuit for generating a gate signal for one switching element of each unit converter is shown.
The control circuit CTR includes a capacitor voltage average value control unit 41, a capacitor voltage balance control unit 42, a current control unit 43, adders 45U to 45W, PWM processing units 46U to 46W, delay circuits 47U to 47W, It has

The capacitor voltage average value control unit 41 uses the externally supplied cell capacitor voltage command value and the capacitor voltage value (or voltage equivalent) detected by at least one of the unit converters 51 to 53 of each phase arm 50. value) and The capacitor voltage average value control unit 41 calculates the average value of the received capacitor voltage values and outputs a control amount that makes the difference between the calculated average value and the cell capacitor voltage command value zero. Note that the capacitor voltage average value control section 41 may include, for example, a proportional control circuit or a proportional integral control circuit.

The capacitor voltage balance control unit 42 receives the capacitor voltage value (or voltage equivalent value) detected by at least one of the unit converters 51 to 53 of each phase arm 50, and compares the received three capacitor voltage values. are substantially equal to each other. For example, the average value of the three received capacitor voltage values may be calculated, and the control amount may be calculated so that the difference between the average value and each capacitor voltage value becomes zero. Also, the control amount may be calculated so that the difference between any one of the three capacitor voltage values and the other capacitor voltage value is zero. Note that the capacitor voltage balance control unit 42 may include, for example, a proportional control circuit or a proportional integral control circuit.

The current control unit 43 receives, for example, the system voltage value and the reactive power command value from the outside, and receives the control amount output from the capacitor voltage average value control unit 41 . The current control unit 43 uses the system voltage value and the control amount from the capacitor voltage average value control unit 41 to calculate and output the control amount of each phase so as to realize the input reactive power command value.

Adder 45U calculates the sum of the control amount output from capacitor voltage balance control section 42 and the U-phase control amount output from current control section 43, and uses the calculation result as the voltage of the U-phase arm. Output as a command value.
The adder 45V calculates the sum of the control amount output from the capacitor voltage balance control section 42 and the V-phase control amount output from the current control section 43, and converts the calculation result into the voltage of the V-phase arm. Output as a command value.
The adder 45W calculates the sum of the control amount output from the capacitor voltage balance control section 42 and the W-phase control amount output from the current control section 43, and converts the calculation result into the voltage of the W-phase arm. Output as a command value.

PWM processing unit 46U receives the voltage command value of the U-phase arm from adder 45U, compares the carrier wave and the voltage command value, for example, and outputs the gate signal of the switching element of one unit converter of the U-phase arm. Generate and output.
The PWM processing unit 46V receives the voltage command value of the V-phase arm from the adder 45V, for example, compares the carrier wave and the voltage command value, and outputs the gate signal of the switching element of one unit converter of the V-phase arm. Generate and output.
The PWM processing unit 46W receives the voltage command value of the W-phase arm from the adder 45W, compares, for example, the carrier wave and the voltage command value, and outputs the gate signal of the switching element of one unit converter of the W-phase arm. Generate and output.

The delay circuit 47U delays the gate signal to the switching element of one unit converter output from the PWM processing unit 46U to generate a gate signal to the switching element of the other unit converter of the U-phase arm, It outputs gate signals corresponding to the switching elements of all the unit converters of the U-phase arm. The delay circuit 47U includes (N-1) delay circuits DLY, and the delay times of the (N-1) delay circuits DLY are different from each other.

The delay circuit 47V delays the gate signal to the switching element of one unit converter output from the PWM processing section 46V to generate a gate signal to the switching element of the other unit converter of the V-phase arm, It outputs gate signals corresponding to the switching elements of all the unit converters of the V-phase arm. The delay circuit 47V includes (N-1) delay circuits DLY, and the delay times of the (N-1) delay circuits DLY are different from each other.

The delay circuit 47W delays the gate signal to the switching element of one unit converter output from the PWM processing unit 46W to generate a gate signal to the switching element of the other unit converter of the W-phase arm, It outputs gate signals corresponding to the switching elements of all the unit converters of the W-phase arm. The delay circuit 47W includes (N−1) delay circuits DLY, and the delay times of the (N−1) delay circuits DLY are different from each other.

17 is a diagram for explaining an example of the operation of the control circuit of the reactive power compensator shown in FIGS. 15 and 16. FIG.
For example, the PWM processing unit 46U compares the carrier wave and the voltage command value to generate and output the first gate signal. The first gate signal is, for example, the gate signal of the switching element Q11p.

Delay circuit 47U receives the first gate signal from PWM processor 46U. The delay circuit 47U includes two delay circuits DLY with different delay times, and the two delay circuits DLY generate a second gate signal and a third gate signal using the input first gate signal. The second gate signal is, for example, the gate signal of the switching element Q21p. The third gate signal is, for example, the gate signal of the switching element Q31p.

Delay circuit 47U supplies the first gate signal, the second gate signal and the third gate signal to unit converters 51-53 of the U-phase arm.
The gate signal of the switching element Q11n is a signal obtained by inverting the first gate signal. The gate signal for the switching element Q12p can be generated by inverting the voltage command value and comparing it with the carrier wave. The gate signal of the switching element Q12n is a signal obtained by inverting the gate signal of the switching element Q12p.

Other unit converters 52 and 53 can also generate gate signals for all switching elements in the same manner as described above. A gate signal output from the control circuit CTR is input to a drive circuit that drives the switching element and the balance switching element of the corresponding unit converter.

As described above, by shifting the switching timing of the switching elements of the plurality of unit converters of each arm 50, the switching frequency can be lowered, and the content of harmonics in the output voltage can be suppressed.

According to the reactive power compensator 21 of the present embodiment, each arm 50 includes the balance circuits B12 and B23, and the balance switching elements of the balance circuits B12 and B23 are synchronized with the switching elements of the unit converters in each arm 50. By operation, it is possible to equalize the capacities of the unit converter capacitors in arm 50 . This configuration eliminates the need to detect all the voltages of the capacitors of the unit converters included in the reactive power compensator 21 and control the individual voltages. In addition, the amount of calculation in the control circuit CTR can be reduced. That is, according to this embodiment, it is possible to provide a compact multi-serial unit converter cluster and a reactive power compensator that are low in cost and have few harmonics.

Next, a modification of the reactive power compensator of the fourth embodiment described above will be described.
18 is a block diagram for explaining another configuration example of the control circuit of the reactive power compensator shown in FIG. 12. FIG.
Here, for an example in which each phase arm includes N stages of unit converters, a configuration example of a circuit for generating a gate signal for one switching element of each unit converter is shown.

In this example, the control circuit CTR does not include the delay circuits 47U, 47V, and 47W, and the PWM processing units 46U, 46V, and 46W use N carrier waves to transmit the N-stage unit converters 51-53 of each phase arm 50. The configuration is the same as that of the above-described fourth embodiment except that it generates a gate signal of .

19 is a diagram for explaining an example of the operation of the control circuit of the reactive power compensator shown in FIG. 18. FIG.
For example, the PWM processing unit 46U compares each of the first carrier wave, the second carrier wave, and the third carrier wave with the voltage command value to obtain the first gate signal, the second gate signal, and the third gate signal. is generated and output. The first carrier wave, the second carrier wave, and the third carrier wave are waveforms that are 120 degrees out of phase with each other, for example.

The first gate signal is generated by comparing the first carrier wave and the voltage command value, and is the gate signal for the switching element Q11p, for example. The second gate signal is generated by comparing the second carrier wave and the voltage command value, and is the gate signal for the switching element Q21p, for example. The third gate signal is generated by comparing the third carrier wave and the voltage command value, and is a gate signal for switching element Q31p, for example.

The PWM processing unit 46U supplies the first gate signal, the second gate signal and the third gate signal to the U-phase arm unit converters 51-53.
The gate signal of the switching element Q11n is a signal obtained by inverting the first gate signal. The gate signal for the switching element Q12p can be generated by inverting the voltage command value and comparing it with the first carrier wave. The gate signal of the switching element Q12n is a signal obtained by inverting the gate signal of the switching element Q12p.
Other unit converters 52 and 53 can also generate gate signals for all switching elements in the same manner as described above.

A gate signal output from the control circuit CTR is input to a drive circuit that drives the switching element and the balance switching element of the corresponding unit converter.
Even if the control circuit CTR does not include the delay circuits 47U, 47V, and 47W as described above, the same effects as those of the fourth embodiment can be obtained.

FIG. 20 is a diagram schematically showing one configuration example of an arm of the reactive power compensator of the fifth embodiment. FIG. 20 shows an example of the configuration of the unit converter cluster when N≦3. For example, the unit converter 53 is the first unit converter, the unit converter 52 is the second unit converter, and the unit converter 51 corresponds to the third unit converter.
The reactive power compensator of this embodiment differs from the above-described fourth embodiment in the configuration of the balance circuits B12 and B23 of the phase arms 50U, 50V and 50W. Here, the common configuration of the U-phase arm 50U, the V-phase arm 50V, and the W-phase arm 50W will be described as an arm 50. FIG.
Moreover, in the following description, the same reference numerals are given to the same configurations as in the above-described fourth embodiment, and the description thereof will be omitted.

The balance circuit B12 includes balance switching elements Q121b and Q122b and drive circuits DV121b and DV122b.
One end (source) of the balance switching element Q121b is electrically connected to the other end of the capacitor C1 of the unit converter 51 and the sources of the switching elements Q11n and Q12n. The other end (drain) of the balance switching element Q121b is electrically connected to one end (drain) of the balance switching element Q122b. The other end (source) of the balance switching element Q122b is electrically connected to the other end of the capacitor C2 of the unit converter 52 and the sources of the switching elements Q21n and Q22n.
The balance switching elements Q121b and Q122b are provided in the path electrically connecting the unit converters 52 and 51 between the source of the second switching element and the source of the fourth switching element and the capacitor. there is
Therefore, when the balance switching elements Q121b and Q122b are turned on (conducted), the other end of the capacitor C1 and the other end of the capacitor C2 are electrically connected.

The balance switching element Q121b may be arranged so that the source is on the other end side of the capacitor C1 of the unit converter 51 and the drain is on the other end side of the capacitor C2 of the unit converter 52. The balance switching element Q122b may be arranged so that the source is on the other end side of the capacitor C2 of the unit converter 52 and the drain is on the other end side of the capacitor C1 of the unit converter 51. That is, the balance switching element Q121b may be arranged so that the arrangement of the source and the drain is opposite to that of the balance switching element Q122b. The order in which Q122b and Q122b are arranged may be reversed from that in FIG.

The drive circuit DV121b operates by being supplied with power supply voltage from the power supply circuit 531, and drives the balance switching element Q121b based on the gate signal supplied from the control circuit CTR. In this embodiment, the balance switching element Q121b has the same reference voltage as that of the power supply circuit 531. FIG. Therefore, when power is supplied from the power supply circuit 531 to the driving circuit DV121b, it is not necessary to interpose an insulating circuit in the preceding stage of the driving circuit DV121b.

The drive circuit DV122b operates by being supplied with power supply voltage from the power supply circuit 532, and drives the balance switching element Q122b based on the gate signal supplied from the control circuit CTR. In this embodiment, the balance switching element Q122b has the same voltage as that of the power supply circuit 532 as a reference. Therefore, when power is supplied from the power supply circuit 532 to the driving circuit DV122b, it is not necessary to interpose an insulating circuit in the preceding stage of the driving circuit DV122b.

In this embodiment, the gate signal of the balance switching element Q121b is common to the gate signal of the switching element Q21p of the unit converter 52. FIG. The gate signal of the balance switching element Q122b is common to the gate signal of the switching element Q12p of the unit converter 52. Therefore, the switching element Q21p and the balance switching element Q121b are conducted (turned on) at the same timing, the switching element Q12p and the balance switching element Q122b are conducted (turned on) at the same timing, and the switching element Q21p and the switching element Q12p are conducted (turned on) at the same timing. The capacitor C1 and the capacitor C2 are connected in parallel at the timing when both of are turned on. As a result, the voltages of the capacitors C1 and C2 become substantially equal.

The balance circuit B23 includes balance switching elements Q231b and Q232b and drive circuits DV231b and DV232b.
One end (source) of the balance switching element Q231b is electrically connected to the other end of the capacitor C2 of the unit converter 52 and the sources of the switching elements Q21n and Q22n. The other end (drain) of the balance switching element Q231b is electrically connected to one end (drain) of the balance switching element Q232b. The other end (source) of the balance switching element Q232b is electrically connected to the other end of the capacitor C3 of the unit converter 53 and the sources of the switching elements Q31n and Q32n.
The balance switching elements Q231b and Q232b are connected between the unit converter (first unit converter) 53 and the unit converter (second unit converter) between the source of the second switching element and the source of the fourth switching element and the capacitor. ) 52.
Therefore, when the balance switching elements Q231b and Q232b are turned on (conducted), the other end of the capacitor C2 and the other end of the capacitor C3 are electrically connected.

The balance switching element Q231b may be arranged so that the source is on the other end side of the capacitor C2 of the unit converter 52 and the drain is on the other end side of the capacitor C3 of the unit converter 53. The balance switching element Q232b may be arranged so that the source is on the other end side of the capacitor C3 of the unit converter 53 and the drain is on the other end side of the capacitor C2 of the unit converter 52. That is, the balance switching element Q231b may be arranged such that the arrangement of the source and the drain is opposite to that of the balance switching element Q232b. The order in which Q232b is arranged may be reversed from that in FIG.

The drive circuit DV231b operates by being supplied with the power supply voltage from the power supply circuit 532, and drives the balance switching element Q231b based on the gate signal supplied from the control circuit CTR. In this embodiment, the balance switching element Q231b has the same reference voltage as that of the power supply circuit 532. FIG. Therefore, when power is supplied from the power supply circuit 532 to the driving circuit DV231b, it is not necessary to interpose an insulating circuit in the preceding stage of the driving circuit DV231b.

The drive circuit DV232b operates by being supplied with power supply voltage from the power supply circuit 533, and drives the balance switching element Q232b based on the gate signal supplied from the control circuit CTR. In this embodiment, the balance switching element Q232b has the same reference voltage as that of the power supply circuit 533. FIG. Therefore, when power is supplied from the power supply circuit 533 to the driving circuit DV232b, it is not necessary to interpose an insulating circuit in the preceding stage of the driving circuit DV232b.

In this embodiment, the gate signal of the balance switching element Q231b is common to the gate signal of the switching element Q31p of the unit converter 53. The gate signal of the balance switching element Q232b is common to the gate signal of the switching element Q22p of the unit converter 52. Therefore, the switching element Q31p and the balance switching element Q231b are conducted (turned on) at the same timing, the switching element Q22p and the balance switching element Q232b are conducted (turned on) at the same timing, and the switching element Q31p and the switching element Q22p are conducted (turned on) at the same timing. Capacitor C2 and capacitor C3 are connected in parallel at the timing when both are conductive. As a result, the voltages of the capacitors C2 and C3 become substantially equal.

21 is a diagram for explaining an example of the motion of the arm shown in FIG. 20; FIG.
Here, for example, when the voltage of the capacitors C1 to C3 is Vc, the output voltage Vout of the AC terminals UT, VT, and WT is 3 times, 2 times, 1 time, -1 times, -2 times, - It shows the conduction states of the switching elements Q11p-Q32n of the unit converters 51-53 and the balance switching elements Q121b, Q122b, Q231b, Q232b of the balance circuits B12, B23 when tripled and zero. In FIG. 13, "1" indicates the state in which the switching element is conducting (ON state), and "0" indicates the state in which the switching element is not conducting (OFF state).

For example, when the output voltage is three times the voltage Vc, the switching element Q11p is on, the switching element Q11n is off, the switching element Q12p is off, the switching element Q12n is on, the switching element Q21p is on, the switching element Q21n is off, The switching element Q22p is turned off, the switching element Q22n is turned on, the switching element Q31p is turned on, the switching element Q31n is turned off, the switching element Q32p is turned off, and the switching element Q32n is turned on. At this time, the balance switching element Q121b is on, the switching element Q122b is off, the switching element Q231b is on, the balance switching element Q232b is off, and the capacitors C1 to C3 are not connected in parallel with each other.

For example, when the output voltage is double the voltage Vc, the switching element Q11p is on, the switching element Q11n is off, the switching element Q12p is on, the switching element Q12n is off, the switching element Q21p is on, the switching element Q21n is off, The switching element Q22p is turned off, the switching element Q22n is turned on, the switching element Q31p is turned on, the switching element Q31n is turned off, the switching element Q32p is turned off, and the switching element Q32n is turned on. At this time, the balance switching element Q121b is turned on, the switching element Q122b is turned on, the switching element Q231b is turned on, and the balance switching element Q232b is turned off. is not connected to

For example, when the output voltage is 1 times the voltage Vc, the switching element Q11p is on, the switching element Q11n is off, the switching element Q12p is on, the switching element Q12n is off, the switching element Q21p is on, the switching element Q21n is off, The switching element Q22p is on, the switching element Q22n is off, the switching element Q31p is on, the switching element Q31n is off, the switching element Q32p is off, and the switching element Q32n is on. At this time, the balance switching element Q121b is turned on, the switching element Q122b is turned on, the switching element Q231b is turned on, the balance switching element Q232b is turned on, and the capacitors C1 to C3 are connected in parallel with each other.

For example, when the output voltage becomes zero, the switching element Q11p is on, the switching element Q11n is off, the switching element Q12p is on, the switching element Q12n is off, the switching element Q21p is on, the switching element Q21n is off, and the switching element Q22p is ON, the switching element Q22n is OFF, the switching element Q31p is ON, the switching element Q31n is OFF, the switching element Q32p is ON, and the switching element Q32n is OFF. At this time, the balance switching element Q121b is turned on, the switching element Q122b is turned on, the switching element Q231b is turned on, the balance switching element Q232b is turned on, and the capacitors C1 to C3 are connected in parallel with each other.

For example, when the output voltage is -1 times the voltage Vc, the switching element Q11p is on, the switching element Q11n is off, the switching element Q12p is on, the switching element Q12n is off, the switching element Q21p is on, and the switching element Q21n is off. , the switching element Q22p is on, the switching element Q22n is off, the switching element Q31p is off, the switching element Q31n is on, the switching element Q32p is on, and the switching element Q32n is off. At this time, the balance switching element Q121b is on, the switching element Q122b is on, the switching element Q231b is off, the balance switching element Q232b is on, the capacitor C1 and the capacitor C2 are connected in parallel, and the capacitor C3 is in parallel with another capacitor. is not connected to

For example, when the output voltage is -2 times the voltage Vc, the switching element Q11p is on, the switching element Q11n is off, the switching element Q12p is on, the switching element Q12n is off, the switching element Q21p is off, and the switching element Q21n is on. , the switching element Q22p is on, the switching element Q22n is off, the switching element Q31p is off, the switching element Q31n is on, the switching element Q32p is on, and the switching element Q32n is off. At this time, the balance switching element Q121b is turned off, the switching element Q122b is turned on, the switching element Q231b is turned off, the balance switching element Q232b is turned on, and the capacitors C1 to C3 are not connected in parallel with each other.

For example, when the output voltage is -3 times the voltage Vc, the switching element Q11p is turned off, the switching element Q11n is turned on, the switching element Q12p is turned on, the switching element Q12n is turned off, the switching element Q21p is turned off, and the switching element Q21n is turned on. , the switching element Q22p is on, the switching element Q22n is off, the switching element Q31p is off, the switching element Q31n is on, the switching element Q32p is on, and the switching element Q32n is off. At this time, the balance switching element Q121b is turned off, the switching element Q122b is turned on, the switching element Q231b is turned off, the balance switching element Q232b is turned on, and the capacitors C1 to C3 are not connected in parallel with each other.

As described above, when the output of the arm 50 is switched, the connection state of the capacitors C1-C3 is also switched, so that the voltages of the capacitors C1-C3 can be equalized at the same time that the power converter performs normal operation. Therefore, by obtaining the voltage of any one of the capacitors C1 to C3, the voltage value of the capacitors C1 to C3 can be controlled. - Eliminates the need for special control to equalize the voltages of C3.

That is, according to the reactive power compensator 21 of the present embodiment, each arm 50 includes the balance circuits B12 and B23, and in each arm 50, the balance switching elements of the balance circuits B12 and B23 are synchronized with the switching elements of the unit converters. It is possible to equalize the capacities of the capacitors of the unit converters in the arm 50 by operating as . This configuration eliminates the need to detect all the voltages of the capacitors of the unit converters included in the reactive power compensator 21 and control the individual voltages. In addition, the amount of calculation in the control circuit CTR can be reduced.

Furthermore, the reactive power compensator 21 of this embodiment does not require the insulating circuits of the balance circuits B12 and B23, and can be realized with fewer components than the above-described fourth embodiment.
That is, according to this embodiment, it is possible to provide a compact multi-serial unit converter cluster and a reactive power compensator that are low in cost and have few harmonics.

FIG. 22 is a diagram schematically showing another configuration example of the reactive power compensator of the embodiment;
In the fourth and fifth embodiments, the configuration of the reactive power compensator in which the U-phase arm 50U, the V-phase arm 50V, and the W-phase arm 50W are electrically connected to each other through the unit converter 53. Although described, the configuration of the reactive power compensator is not limited to the above.

In the example shown in FIG. 22, unit converter 53 of U-phase arm 50U is electrically connected to unit converter 51 of V-phase arm 50V via buffer reactor LV. Unit converter 53 of V-phase arm 50V is electrically connected to unit converter 51 of W-phase arm 50W via buffer reactor LW. Unit converter 53 of W-phase arm 50W is electrically connected to unit converter 51 of U-phase arm 50U via buffer reactor LU.

Even the reactive power compensator 21 having the above configuration has the same configuration as the arm 50 of the fourth and fifth embodiments described above, so that the same effect as the reactive power compensator of the fourth and fifth embodiments can be obtained. can be obtained.

23 is a diagram schematically showing another configuration example of the arm of the power converter shown in FIG. 1. FIG.
In the above-described embodiments, the configuration in which the voltages of the capacitors of all the unit converters included in the arm 30 (or arm 50) are substantially equal has been described. As shown, it is sufficient to have a configuration that equalizes the voltages of the capacitors of at least two unit converters.
FIG. 23 shows a configuration example of arm 30 including unit converters 31-34, balance circuits B12 and B34, and a voltage detector (not shown).
Each of the plurality of unit converters 31-34 has the same configuration as each of the unit converters 31-33 shown in FIG. 2 except for the voltage detector SV. The balance circuit B12 has the same configuration as the balance circuit B12 shown in FIG.

The balance circuit B34 includes a balance switching element Q34b, a drive circuit (balance switch drive circuit) DV34b, and an insulation circuit (second insulation circuit) 323.
The balance switching element Q34b includes a self-extinguishing switching element such as a MOSFET (metal-oxide semiconductor field-effect transistor). The self arc-extinguishing switching element is, for example, an IEGT (injection enhanced gate transistor), a GTO (gate turn-off thyristor), a GTO (gate turn-off thyristor), a GCT (gate communicated turn-off thyristor), or an IGBT (Insulated It is possible to employ a switching element such as a Gate Bipolar Transistor, which can be electrically controlled to be turned on (conducting state) and off (non-conducting state). The balance switching element Q34b may include a freewheeling diode connected in anti-parallel to the switching element, if necessary.
When an IGBT or IEGT is used as the balance switching element Q34b, the source of the balance switching element Q34b is read as the emitter, and the drain of the balance switching element Q34b is read as the collector.

One end (drain) of the balance switching element Q34b is electrically connected to one end of the capacitor C3 of the unit converter 33 . The other end (source) of the balance switching element Q34b is electrically connected to one end of the capacitor C4 of the unit converter . Therefore, when the balance switching element Q34b is turned on (conducted), one end of the capacitor C3 and one end of the capacitor C4 are electrically connected.

The isolation circuit 323 isolates the power supply circuit 333 and the drive circuit DV34b. The power supply circuit 333 and the drive circuit DV34b operate at different reference potentials. Isolation circuit 323 is, for example, a bootstrap circuit.
The drive circuit DV34b operates by being supplied with the power supply voltage through the isolation circuit 323, and drives the balance switching element Q34b based on the gate signal supplied from the control circuit CTR.

In this embodiment, the gate signal of the balance switching element Q34b is common to the switching element Q4n of the unit converter 34. FIG. That is, the gate signal input to the drive circuit DV34b and the gate signal input to the drive circuit DV4n are common. Therefore, the switching element Q4n and the balance switching element Q34b are conducted (turned on) at the same timing, and the capacitors C3 and C4 are connected in parallel. As a result, the voltage of the capacitor C3 and the voltage of the capacitor C4 become substantially equal.

As described above, in the example shown in FIG. 23, the voltage of the capacitor C1 of the unit converter 31 and the voltage of the capacitor C2 of the unit converter 32 are substantially equalized by the balance circuit B12. The voltage of the capacitor C3 of the unit converter 33 and the voltage of the capacitor C4 of the unit converter 34 are made substantially equal by the balance circuit B34.
The voltage detector is provided to detect the voltage of one of the capacitors C1 and C2 and the voltage of one of the capacitors C3 and C4, and supplies the detected values to the control circuit CTR. .

In this example, the unit converters connected by the balance circuits B12 and B34 are synchronously operated. That is, the switching element Q1p of the unit converter 31 and the switching element Q2p of the unit converter 32 are driven by the same gate signal. Similarly, the switching element Q1n of the unit converter 31 and the switching element Q2n of the unit converter 32 are driven by the same gate signal. The switching element Q3p of the unit converter 33 and the switching element Q4p of the unit converter 34 are driven by the same gate signal. Similarly, the switching element Q3n of the unit converter 33 and the switching element Q4n of the unit converter 34 are driven by the same gate signal. By driving a plurality of unit converters 31-34 as described above, output voltages of 0V, 2Vc, and 4Vc can be output by the arm shown in FIG. 23, for example.

When a plurality of unit converters 31 and 32 are driven by the same gate signal, an imbalance occurs between the voltage of the capacitor C1 and the voltage of the capacitor C2 due to slight variations, which can be eliminated by the balance circuit B12. Similarly, for the plurality of unit converters 33 and 34, the voltage imbalance of the capacitors C3 and C4 can be eliminated by the balance circuit B34.

As a result, for example, when the number of unit converters included in one arm increases, it is possible to prevent the number of gate signals from increasing and to simplify the configuration of the control circuit CTR and its peripherals.
The control circuit CTR receives voltage values (or voltage equivalent values) of at least two capacitors from each of the plurality of arms 30U to 30Z, and based on the received 12 voltage values (or voltage equivalent values), the plurality of arms The control amount can be calculated so that the values of the capacitors included in 30U-30Z are equal. Therefore, according to the power converter or reactive power compensator having the arm shown in FIG. 23, the same effects as those of the above-described embodiments can be obtained.

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 10...AC power supply (or AC load), 20...Power converter, 21...Var compensator, 22...Voltage transformer, 30...Arm, 30U...U-phase positive arm, 30U...Positive arm, 30V... V-phase positive arm 30W W-phase positive arm 30X U-phase negative arm 30Y V-phase negative arm 30Z W-phase negative arm 31-33 Unit converter 41 Capacitor voltage Average value control unit 42 Capacitor voltage balance control unit 43 Current control unit 44U to 44W Subtractor 45U to 45W Adder 45X to 45Z Adder 46U to 46W PWM processing unit 46X to 46Z... PWM processing section, 47U to 47W... delay circuit, 50... arm, 50U... U-phase arm, 50V... V-phase arm, 50W... W-phase arm, 51-53... unit converter, 311-313, 321, 322 , 511-513, 521, 522... isolation circuit, 331-333, 531-533... power supply circuit, AD1, AD2... adder, B12, B23... balance circuit, C1-C3... capacitor, DV12b, DV1n, DV1p, DV23b , DV2n, DV2p, DV3n, DV3p... drive circuit, M1... multiplier, Q1p-Q4n, Q11p-Q32n... switching element, Q12b, Q23b, Q121b, Q122b, Q231b, Q232b... balance switching element.

Claims (10)

a control unit that outputs a plurality of gate signals;
a first switching element, a second switching element having a drain connected to the source of the first switching element, and a capacitor connected between the drain of the first switching element and the source of the second switching element, respectively and, first to N-th unit converters connected in series;
When n is any integer from 1 to (N−1), between the drain of the first switching element of the n-th unit converter and the capacitor, and the (n+1)-th unit converter 1st to (N-1)th balance circuits each including a balance switching element provided on a path connecting between the drain of the first switching element and the capacitor of the nth unit converter;
a voltage detector provided for at least one of the first to Nth unit converters and detecting the voltage of the capacitor;
with
Between the source of the first switching element and the drain of the second switching element of the (n+1)th unit converter and the source of the second switching element of the nth unit converter are electrically connected connected and
The control unit shares the gate signal of the second switching element of the (n+1)-th unit converter and the gate signal of the balance switching element of the n-th balance circuit among a plurality of output gate signals. be the signal of
Device. a control unit that outputs a plurality of gate signals;
a first switching element, a second switching element having a drain connected to the source of the first switching element, and a capacitor connected between the drain of the first switching element and the source of the second switching element, respectively and, first to N-th unit converters connected in series;
When n is any integer from 1 to (N−1), between the source of the second switching element of the n-th unit converter and the capacitor, and the (n+1)-th unit converter first to (N−1)th balance circuits each including a balance switching element provided on a path connecting between the source of the second switching element and the capacitor;
a voltage detector provided for at least one of the first to Nth unit converters and detecting the voltage of the capacitor;
with
between the source of the first switching element of the n-th unit converter and the drain of the second switching element and the drain of the first switching element of the (n+1)-th unit converter are electrically connected connected and
The control section outputs a gate signal of the first switching element of the n-th unit converter and a gate signal of the balance switching element of the n-th balance circuit as a common signal. to be
Device. a control unit that outputs a plurality of gate signals;
a first switching element, a second switching element whose drain is connected to the source of the first switching element, a third switching element whose drain is connected to the drain of the first switching element, and the third switching element, respectively a fourth switching element having a drain connected to the source of the element and a source connected to the source of the second switching element; and a fourth switching element connected between the drain of the third switching element and the source of the fourth switching element. 1st to N-th unit converters connected in series, comprising a capacitor;
When n is any integer from 1 to (N−1), between the drain of the third switching element of the nth unit converter and the capacitor, and the (n+1)th unit converter a first balance switching element provided in a path connecting between the drain of the third switching element and the capacitor; and a second balance switching element to which the drain and the drain of the first balance switching element are connected. first to (N−1)th balance circuits;
a voltage detector provided for at least one of the first to Nth unit converters and detecting the voltage of the capacitor;
with
Between the source of the first switching element and the drain of the second switching element of the (n+1)-th unit converter, and between the source of the third switching element of the n-th unit converter and the fourth switching element is electrically connected to the drain of the element,
The control unit shares a gate signal of the fourth switching element of the n-th unit converter and a gate signal of the first balance switching element of the n-th balance circuit among a plurality of output gate signals. and the gate signal of the second switching element of the (n+1)th unit converter and the gate signal of the second balance switching element of the nth balance circuit are used as a common signal
device . a control unit that outputs a plurality of gate signals;
a first switching element, a second switching element whose drain is connected to the source of the first switching element, a third switching element whose drain is connected to the drain of the first switching element, and the third switching element, respectively a fourth switching element having a drain connected to the source of the element and a source connected to the source of the second switching element; and a fourth switching element connected between the drain of the third switching element and the source of the fourth switching element. 1st to N-th unit converters connected in series, comprising a capacitor;
When n is any integer from 1 to (N-1), between the source of the fourth switching element of the n-th unit converter and the capacitor, and the above-mentioned a first balance switching element provided on a path connecting between the source of a fourth switching element and the capacitor; and a second balance switching element to which the drain and the drain of the first balance switching element are connected. first to (N−1)th balance circuits;
a voltage detector provided for at least one of the first to Nth unit converters and detecting the voltage of the capacitor;
with
Between the source of the first switching element and the drain of the second switching element of the (n+1)-th unit converter, and between the source of the third switching element of the n-th unit converter and the fourth switching element is electrically connected to the drain of the element,
The control unit outputs a gate signal of the first switching element of the (n+1)-th unit converter and a gate signal of the first balance switching element of the n-th balance circuit among a plurality of output gate signals. is a common signal, and the gate signal of the third switching element of the n-th unit converter and the gate signal of the second balance switching element of the n-th balance circuit are common signals
device . Each of the first to Nth unit converters includes a power supply circuit that generates a power supply voltage using the voltage of the capacitor, and a power supply circuit that is connected to the power supply circuit via an isolation circuit to drive the first switching element. 1 drive circuit, and a second drive circuit electrically connected to the power supply circuit and driving the second switching element,
The n-th balance circuit includes a balance switch drive circuit connected to the power supply circuit of the n-th unit converter via a second insulating circuit and driving the balance switching element.
Apparatus according to claim 1 . Each of the first to Nth unit converters includes a power supply circuit that generates a power supply voltage using the voltage of the capacitor, and a power supply circuit that is connected to the power supply circuit via an isolation circuit to drive the first switching element. 1 drive circuit, and a second drive circuit electrically connected to the power supply circuit and driving the second switching element,
The nth balance circuit includes a balance switch drive circuit electrically connected to the power supply circuit of the (n+1)th unit converter and driving the balance switching element.
3. Apparatus according to claim 2 . Each of the first to Nth unit converters includes a power supply circuit that generates a power supply voltage using the voltage of the capacitor, and a first insulating circuit that is connected to the power supply circuit through the first switching element and the a first drive circuit that drives a third switching element; and a second drive circuit that is electrically connected to the power supply circuit and drives the second switching element and the fourth switching element,
The n-th balance circuit includes a first balance switch drive circuit connected to the power supply circuit of the n-th unit converter via a second isolation circuit to drive the first balance switching element, and a third isolation circuit. a second balance switch drive circuit connected to the power supply circuit of the (n+1)th unit converter via and driving the second balance switching element;
4. Apparatus according to claim 3. Each of the first to Nth unit converters includes a power supply circuit that generates a power supply voltage using the voltage of the capacitor, and a first insulating circuit that is connected to the power supply circuit through the first switching element and the a first drive circuit that drives a third switching element; and a second drive circuit that is electrically connected to the power supply circuit and drives the second switching element and the fourth switching element,
The n-th balance circuit includes a first balance switch drive circuit electrically connected to the power supply circuit of the n-th unit converter and driving the first balance switching element, and the (n+1)-th unit converter. a second balance switch drive circuit electrically connected to the power supply circuit of the device and driving the second balance switching element
5. Apparatus according to claim 4. When the first switching element, the second switching element, and the balance switching element are IGBTs or IEGTs, the source should be read as emitter, and the drain should be read as collector.
3. Apparatus according to claim 1 or claim 2. When the first switching element, the second switching element, the third switching element, the fourth switching element, the first balanced switching element, and the second balanced switching element are IGBTs or IEGTs, the source is Replace with emitter, and replace drain with collector
5. Apparatus according to claim 3 or claim 4.

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